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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DQualified for Automotive Applications
DESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D1−A Low-Dropout (LDO) Voltage Regulator
DAvailable in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V,
3-V, 3.3-V, 5-V Fixed-Output and Adjustable
Versions
DDropout Voltage Down to 230 mV at 1 A
(TPS76750)
DUltralow 85-µA Typical Quiescent Current
DFast Transient Response
D2% Tolerance Over Specified Conditions for
Fixed-Output Versions
DOpen Drain Power-On Reset With 200-ms
Delay (See TPS768xx for PG Option)
D20-Pin TSSOP PowerPAD (PWP) Package
DThermal Shutdown Protection
description
These devices are designed to have a fast transient
response and be stable with 10-µF low ESR
capacitors. This combination provides high
performance at a reasonable cost.
Because the PMOS device behaves as a low-value
resistor, the dropout voltage is very low (typically 230
mV at an output current of 1 A for the TPS76750) and
is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven
device, the quiescent current is very low and independent of output loading (typically 85 µA over the full range
of output current, 0 mA to 1 A). These two key specifications yield a significant improvement in operating life
for battery-powered systems. This low-dropout (LDO) family also features a sleep mode; applying a TTL high
signal to the enable (EN) input shuts down the regulator, reducing the quiescent current to 1 µA at TJ = 25°C.
The RESET output of the TPS767xx initiates a reset in microcomputer and microprocessor systems in the event
of an undervoltage condition. An internal comparator in the TPS767xx monitors the output voltage of the
regulator to detect an undervoltage condition on the regulated output voltage.
The TPS767xx is offered in 1.5-V, 1.8-V, 2.5-V, 2.7-V, 2.8-V, 3-V, 3.3-V, and 5-V fixed-voltage versions and in
an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is specified
as a maximum of 2% over line, load, and temperature ranges. The TPS767xx family is available in a 20-pin PWP
package.
Copyright 2008, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NC − No internal connection
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
GND/HSINK
GND/HSINK
GND
NC
EN
IN
IN
NC
GND/HSINK
GND/HSINK
GND/HSINK
GND/HSINK
NC
NC
RESET
FB/NC
OUT
OUT
GND/HSINK
GND/HSINK
PWP PACKAGE
(TOP VIEW)
PowerPAD is a trademark of Texas Instruments.
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2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
TPS76733
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
102
101
100
10−1
10−2 −20 140
IO = 1 A
IO = 10 mA
IO = 0
Co = 10 µF
t − Time − µs
TPS76733
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
1
0.5
300200100 400 500 700600 800 900 10000
Co = 10 µF
TA = 25°C
0
0
50
100
−50
−100
AVAILABLE OPTIONS†
TJ
OUTPUT
VOLTAGE
(V) TSSOP
(PWP)
‡
J
TYP
(PWP)‡
5 TPS76750QPWPRQ1
3.3 TPS76733QPWPRQ1
3 TPS76730QPWPRQ1§
2.8 TPS76728QPWPRQ1§
−40
°
C to 125
°
C
2.7 TPS76727QPWPRQ1§
−40
°
C to 125
°
C
2.5 TPS76725QPWPRQ1
1.8 TPS76718QPWPRQ1
1.5 TPS76715QPWPRQ1
Adjustable
1.5 V to 5.5 V TPS76701QPWPRQ1
†For the most current package and ordering information, see the
Package Option Addendum at the end of this document, or see
the TI web site at www.ti.com.
‡Available taped and reeled in quantities of 2000 per reel
§This devices is product preview.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
†See application information section for capacitor selection details.
RESET
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
0.1 µF
RESET
VO
10 µF
+
TPS767xx
Co†
Figure 1. Typical Application Configuration (for Fixed Output Options)
functional block diagram—adjustable version
200 ms Delay
_
+
Vref = 1.1834 V
OUT
FB/NC
EN
GND
RESET
_
+
IN
External to the device
R1
R2
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4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram—fixed-voltage version
_
+
Vref = 1.1834 V
OUT
EN
GND
R1
R2
RESET
_
+
IN
200 ms Delay
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
EN 5 I Enable
FB/NC 15 I Feedback voltage for adjustable device (no connect for fixed options)
GND 3 Regulator ground
GND/HSINK 1, 2, 9, 10, 11,
12, 19, 20 Ground/heatsink
IN 6, 7 IInput voltage
NC 4, 8, 17, 18 No connect
OUT 13, 14 ORegulated output voltage
RESET 16 O Reset
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timing diagram
†Vres is the minimum input voltage for a valid RESET. The symbol Vres is not currently listed within EIA or JEDEC standards for semiconductor
symbology.
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎ
V
I
Vres†Vres
t
t
t
VO
Threshold
Voltage
RESET
Output 200 ms
Delay 200 ms
Delay
Output
Undefined
Output
Undefined
VIT+‡
VIT−‡VIT−‡
VIT+‡
Less than 5% of the
output voltage
‡V
IT
−Trip voltage is typically 5% lower than the output voltage (95%V
O
) V
IT−
to V
IT+
is the hysteresis voltage.
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6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)Ĕ
Input voltage range‡, VI −0.3 V to 13.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at EN −0.3 V to VI + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum RESET voltage 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Peak output current Internally limited. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, VO (OUT, FB) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD rating, Human-Body Model (HBM) 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡All voltage values are with respect to network terminal ground.
DISSIPATION RATING TABLE − FREE-AIR TEMPERATURES
PACKAGE AIR FLOW
(CFM) TA < 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
PWP§
02.9 W 23.5 mW/°C1.9 W 1.5 W
PWP§
300 4.3 W 34.6 mW/°C 2.8 W 2.2 W
PWP¶
03 W 23.8 mW/°C1.9 W 1.5 W
PWP¶
300 7.2 W 57.9 mW/°C4.6 W 3.8 W
§This parameter is measured with the recommended copper heat-sink pattern on a 1-layer PCB, 5-in × 5-in PCB, 1-oz copper,
2-in × 2-in coverage (4 in2).
¶This parameter is measured with the recommended copper heat sink pattern on a 8-layer PCB, 1.5-in × 2-in PCB, 1-oz copper
with layers 1, 2, 4, 5, 7, and 8 at 5% coverage (0.9 in2) and layers 3 and 6 at 100% coverage (6 in2). For more information, refer
to TI technical brief SLMA002.
recommended operating conditions
MIN MAX UNIT
Input voltage, VI#2.7 10 V
Output voltage range, VO1.5 5.5 V
Output current, IO (see Note 1) 0 1.0 A
Operating virtual junction temperature, TJ (see Note 1) −40 125 °C
# To calculate the minimum input voltage for your maximum output current, use the following equation: VI(min) = VO(max) + VDO(max load).
NOTE 1: Continuous current and operating junction temperature are limited by internal protection circuitry, but it is not recommended that the
device operate under conditions beyond those specified in this table for extended periods of time.
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electrical characteristics over recommended operating free-air temperature range,
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TPS76701
1.5 V ≤ VO ≤ 5.5 V, TJ = 25°C VO
TPS76701 1.5 V ≤ VO ≤ 5.5 V, TJ = −40°C to 125°C0.98VO1.02VO
TPS76715
TJ = 25°C, 2.7 V < VIN < 10 V 1.5
TPS76715 TJ = −40°C to 125°C, 2.7 V < VIN < 10 V 1.470 1.530
TPS76718
TJ = 25°C, 2.8 V < VIN < 10 V 1.8
TPS76718 TJ = −40°C to 125°C, 2.8 V < VIN < 10 V 1.764 1.836
TPS76725
TJ = 25°C, 3.5 V < VIN < 10 V 2.5
TPS76725 TJ = −40°C to 125°C, 3.5 V < VIN < 10 V 2.450 2.550
Output voltage (10 µA to 1 A load)
TPS76727
TJ = 25°C, 3.7 V < VIN < 10 V 2.7
V
Output voltage (10 µA to 1 A load)
(see Note 2) TPS76727 TJ = −40°C to 125°C, 3.7 V < VIN < 10 V 2.646 2.754 V
(see Note 2)
TPS76728
TJ = 25°C, 3.8 V < VIN < 10 V 2.8
TPS76728 TJ = −40°C to 125°C, 3.8 V < VIN < 10 V 2.744 2.856
TPS76730
TJ = 25°C, 4.0 V < VIN < 10 V 3.0
TPS76730 TJ = −40°C to 125°C, 4.0 V < VIN < 10 V 2.940 3.060
TPS76733
TJ = 25°C, 4.3 V < VIN < 10 V 3.3
TPS76733 TJ = −40°C to 125°C, 4.3 V < VIN < 10 V 3.234 3.366
TPS76750
TJ = 25°C, 6.0 V < VIN < 10 V 5.0
TPS76750 TJ = −40°C to 125°C, 6.0 V < VIN < 10 V 4.900 5.100
Quiescent current (GND current)
10 µA < IO < 1 A, TJ = 25°C 85
A
Quiescent current (GND current)
EN = 0V, (see Note 2) IO = 1 A, TJ = −40°C to 125°C 125 µA
Output voltage line regulation (∆VO/VO)
(see Notes 2 and 3) VO + 1 V < VI ≤ 10 V, TJ = 25°C 0.01 %/V
Load regulation 3 mV
Output noise voltage (TPS76718) BW = 200 Hz to 100 kHz, IC = 1 A,
Co = 10 µF, TJ = 25°C55 µVrms
Output current limit VO = 0 V 1.7 2 A
Thermal shutdown junction temperature 150 °C
Standby current
EN = VI, TJ = 25°C,
2.7 V < VI < 10 V 1
A
Standby current EN = VI, TJ = −40°C to 125°C
2.7 V < VI < 10 V 10 µA
FB input current TPS76701 FB = 1.5 V 2 nA
High-level enable input voltage 1.7 V
Low-level enable input voltage 0.9 V
Power-supply ripple rejection (see Note 2) f = 1 KHz, Co = 10 µF,
TJ = 25°C60 dB
NOTES: 2. Minimum IN operating voltage is 2.7 V or VO(typ) + 1 V, whichever is greater. Maximum IN voltage 10 V.
3. If VO≤ 1.8 V then VImax = 10 V, VImin = 2.7 V:
Line Regulation (mV) +ǒ%ńVǓ VOǒVImax *2.7 VǓ
100 1000
If VO ≥ 2.5 V then VImax = 10 V, VImin = VO + 1 V:
Line Regulation (mV) +ǒ%ńVǓ
VOǒVImax *ǒVO)1V
ǓǓ
100 1000
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electrical characteristics over recommended operating free-air temperature range,
VI = VO(typ) + 1 V, IO = 1 mA, EN = 0 V, Co = 10 µF (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Minimum input voltage for valid RESET IO(RESET) = 300 µA 1.1 V
Trip threshold voltage VO decreasing 92 98 %VO
Reset
Hysteresis voltage Measured at VO0.5 %VO
Rese
t
Output low voltage VI = 2.7 V, IO(RESET) = 1 mA 0.15 0.4 V
Leakage current V(RESET) = 5 V 1µA
RESET time-out delay 200 ms
Input current (EN)
EN = 0 V −1 0 1
A
Input current (EN)EN = VI−1 1 µA
TPS76728
IO = 1 A, TJ = 25°C 500
TPS76728 IO = 1 A, TJ = −40°C to 125°C 825
TPS76730
IO = 1 A, TJ = 25°C 450
Dropout voltage (see Note 4)
TPS76730 IO = 1 A, TJ = −40°C to 125°C 675
mV
Dropout voltage (see Note 4)
TPS76733
IO = 1 A, TJ = 25°C 350 mV
TPS76733 IO = 1 A, TJ = −40°C to 125°C 575
TPS76750
IO = 1 A, TJ = 25°C 230
TPS76750 IO = 1 A, TJ = −40°C to 125°C 380
NOTE 4: IN voltage equals VO(typ) − 100 mV ; TPS76701 output voltage set to 3.3 V nominal with external resistor divider. TPS76715, TPS76718,
TPS76725, and TPS76727 dropout voltage limited by input voltage range limitations (i.e., TPS76730 input voltage needs to drop to 2.9 V
for purpose of this test).
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VO
Output voltage
vs Output current 2, 3, 4
VOOutput voltage vs Free-air temperature 5, 6, 7
Ground current vs Free-air temperature 8, 9
Power-supply ripple rejection vs Frequency 10
Output spectral noise density vs Frequency 11
Input voltage (min) vs Output voltage 12
ZoOutput impedance vs Frequency 13
VDO Dropout voltage vs Free-air temperature 14
Line transient response 15, 17
Load transient response 16, 18
VOOutput voltage vs Time 19
Dropout voltage vs Input voltage 20
Equivalent series resistance (ESR) vs Output current 22−25
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TYPICAL CHARACTERISTICS
Figure 2
IO − Output Current − A
TPS76733
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
3.2830
3.2815
3.2800 0.1 0.3
3.2825
3.2820
3.2810
0.2 0.8 1
3.2835
0 0.9
− Output Voltage − V
VO
3.2805
0.4 0.5 0.6 0.7
VI = 4.3 V
TA = 25°C
Figure 3
IO − Output Current − A
1.4975
1.4960
1.4950
1.4970
1.4965
1.4955
1.4985
− Output Voltage − V
VO
TPS76715
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
1.4980
0.1 0.30.2 0.8 10 0.90.4 0.5 0.6 0.7
VI = 2.7 V
TA = 25°C
Figure 4
IO − Output Current − A
TPS76725
OUTPUT VOLTAGE
vs
OUTPUT CURRENT
2.4955
2.4940
2.4920 0.1 0.3
2.4950
2.4945
2.4935
0.2 0.4 0.6
2.4960
0 0.5
− Output Voltage − V
VO
VI = 3.5 V
TA = 25°C
2.4930
2.4925
0.80.7 0.9 1
Figure 5
TA − Free-Air Temperature − °C
TPS76733
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
3.31
3.28
3.25 −40 0
3.30
3.29
3.27
−20 100 140
3.32
−60 120
3.26
20 40 60 80
VI = 4.3 V
IO = 1 A IO = 1 mA
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10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 6
TA − Free-Air Temperature − °C
TPS76715
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
1.515
1.500
1.485 −40 0
1.510
1.505
1.495
−20 100−60 120
1.490
20 40 60 80
VI = 2.7 V
IO = 1 A
IO = 1 mA
140
Figure 7
TA − Free-Air Temperature − °C
TPS76725
OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
− Output Voltage − V
VO
−40 0−20 100−60 12020 40 60 80
2.515
2.500
2.480
2.510
2.505
2.495
2.490
2.485
VI = 3.5 V
IO = 1 A
IO = 1 mA
TA − Free-Air Temperature − °C
TPS76733
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
Ground Current − Aµ
92
84
72
90
88
82
80
78
76
74
86
−40 0−20 100−60 12020 40 60 80 140
VI = 4.3 V
IO = 500 mA
IO = 1 A
IO = 1 mA
Figure 8
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TYPICAL CHARACTERISTICS
Figure 9
TA − Free-Air Temperature − °C
TPS76715
GROUND CURRENT
vs
FREE-AIR TEMPERATURE
Ground Current − Aµ
−40 0−20 100−60 12020 40 60 80 140
VI = 2.7 V
IO = 1 A
100
95
90
85
80
75
IO = 1 mA
IO = 500 mA
100k10k
PSRR − Power Supply Ripple Rejection − dB
f − Frequency − Hz
POWER-SUPPLY RIPPLE REJECTION
vs
FREQUENCY
70
60
50
40
30
20
10
0
−10
TPS76733
90
80
1k10010 1M
VI = 4.3 V
Co = 10 µF
IO = 1 A
TA = 25°C
Figure 10
TPS76733
OUTPUT SPECTRAL NOISE DENSITY
vs
FREQUENCY
f − Frequency − Hz
102103104105
10−5
10−6
10−8
10−7
IO = 7 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
V HzOutput Spectral Noise Density − µ
Figure 11
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12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 12
3
2.7
21.5 1.75 2 2.25 2.5 2.75
− Input Voltage (Min) − V
INPUT VOLTAGE (MIN)
vs
OUTPUT VOLTAGE
4
3 3.25 3.5
TA = 25°C
VI
VO − Output Voltage − V
IO = 1 A
TA = 125°C
TA = −40°C
Figure 13
f − Frequency − kHz
− Output Impedance −ZoΩ
101102105106
0
10−1
10−2 104
103
IO = 1 mA
IO = 1 A
VI = 4.3 V
Co = 10 µF
TA = 25°C
TPS76733
OUTPUT IMPEDANCE
vs
FREQUENCY
Figure 14
TA − Free-Air Temperature − °C
−40 0 20 120
103
−60 40 60 80 100
− Dropout Voltage − mV
VDO
TPS76733
DROPOUT VOLTAGE
vs
FREE-AIR TEMPERATURE
102
101
100
10−1
10−2 −20 140
IO = 1 A
IO = 10 mA
IO = 0
Co = 10 µF
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TYPICAL CHARACTERISTICS
Figure 15
VO− Change in
10
0
3.7
2.7
TPS76715
LINE TRANSIENT RESPONSE
VI
t − Time − µs
0604020 80 100 140120 160 180 200
− Input Voltage − V
∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
−10
Figure 16
t − Time − µs
TPS76715
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
Co = 10 µF
TA = 25°C
1
0.5
0
0 300200100 400 500 700600 800 900 100
0
0
50
100
−50
−100
Figure 17
TPS76733
LINE TRANSIENT RESPONSE
t − Time − µs
VO− Change in VI− Input Voltage − V
∆
Output Voltage − mV
5.3
604020 80 100 140120 160 180 200
Co = 10 µF
TA = 25°C
0
4.3
10
0
−10
Figure 18
t − Time − µs
TPS76733
LOAD TRANSIENT RESPONSE
I − Output Current − A
OVO− Change in∆
Output Voltage − mV
1
0.5
300200100 400 500 700600 800 900 100
0
0
Co = 10 µF
TA = 25°C
0
0
50
100
−50
−100
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14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 19
t − Time − ms
TPS76733
OUTPUT VOLTAGE
vs
TIME (AT STARTUP)
3
2
0.30.20.1 0.4 0.5 0.70.6 0.8 0.9 10
VO− Output Voltage − V
0
1
4
Enable Pulse − V
0
Co = 10 µF
IO = 1 A
TA = 25°C
Figure 20
VI − Input Voltage − V
600
300
034
500
400
200
3.52.5
− Dropout Voltage − mV
100
4.5 5
VDO
900
800
700
TA = 125°C
TA = −40°C
TA = 25°C
IO = 1 A
TPS76701
DROPOUT VOLTAGE
vs
INPUT VOLTAGE
IN
EN
OUT
+
GND Co
ESR
RL
VITo Load
Figure 21. Test Circuit for Typical Regions of Stability (Figures 22 Through 25) (Fixed-Output Options)
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO − Output Current − mA
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TA = 25°CRegion of Stability
Region of Instability
Figure 23
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
IO − Output Current − mA
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
10
1
0.01
Region of Instability
VO = 3.3 V
Co = 4.7 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
ESR − Equivalent Series Resistance − Ω
0.1
0 200 400 600 800 1000
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
10
IO − Output Current − mA
1
Region of Instability
Region of Stability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TA = 25°C
0.01
Region of Instability
Figure 24 Figure 25
ESR − Equivalent Series Resistance − Ω
TYPICAL REGION OF STABILITY
EQUIVALENT SERIES RESISTANCE†
vs
OUTPUT CURRENT
0.1
0 200 400 600 800 1000
10
1
IO − Output Current − mA
0.01
Region of Instability
VO = 3.3 V
Co = 22 µF
VI = 4.3 V
TJ = 125°C
Region of Stability
Region of Instability
†Equivalent series resistance (ESR) refers to the total series resistance, including the ESR of the capacitor, any series resistance added
externally, and PWB trace resistance to Co.
SGLS009B − MARCH 2003 − REVISED APRIL 2008
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
The TPS767xx family includes eight fixed-output voltage regulators (1.5 V, 1.8 V, 2.5 V, 2.7 V, 2.8 V, 3 V, 3.3 V,
and 5 V), and an adjustable regulator, the TPS76701 (adjustable from 1.5 V to 5.5 V).
device operation
The TPS767xx features very low quiescent current, which remains virtually constant even with varying loads.
Conventional LDO regulators use a pnp pass element, the base current of which is directly proportional to the
load current through the regulator (IB = IC/β). The TPS767xx uses a PMOS transistor to pass current; because
the gate of the PMOS is voltage driven, operating current is low and invariable over the full load range.
Another pitfall associated with the pnp-pass element is its tendency to saturate when the device goes into
dropout. The resulting drop in β forces an increase in IB to maintain the load. During power up, this translates
to large start-up currents. Systems with limited supply current may fail to start up. In battery-powered systems,
it means rapid battery discharge when the voltage decays below the minimum required for regulation. The
TPS767xx quiescent current remains low even when the regulator drops out, eliminating both problems.
The TPS767xx family also features a shutdown mode that places the output in the high-impedance state
(essentially equal to the feedback-divider resistance) and reduces quiescent current to 2 µA. If the shutdown
feature is not used, EN should be tied to ground.
minimum load requirements
The TPS767xx family is stable even at zero load; no minimum load is required for operation.
FB—pin connection (adjustable version only)
The FB pin is an input pin to sense the output voltage and close the loop for the adjustable option . The output
voltage is sensed through a resistor divider network to close the loop as shown in Figure 27. Normally, this
connection should be as short as possible; however, the connection can be made near a critical circuit to
improve performance at that point. Internally, FB connects to a high-impedance wide-bandwidth amplifier and
noise pickup feeds through to the regulator output. Routing the FB connection to minimize/avoid noise pickup
is essential.
external capacitor requirements
An input capacitor is not usually required; however, a ceramic bypass capacitor (0.047 µF or larger) improves
load transient response and noise rejection if the TPS767xx is located more than a few inches from the power
supply. A higher-capacitance electrolytic capacitor may be necessary if large (hundreds of milliamps) load
transients with fast rise times are anticipated.
Like all low dropout regulators, the TPS767xx requires an output capacitor connected between OUT and GND
to stabilize the internal control loop. The minimum recommended capacitance value is 10 µF and the equivalent
series resistance (ESR) must be between 50 mΩ and 1.5 Ω. Capacitor values 10 µF or larger are acceptable,
provided the ESR is less than 1.5 Ω. Solid tantalum electrolytic, aluminum electrolytic, and multilayer ceramic
capacitors are all suitable, provided they meet the requirements described above. Most of the commercially
available 10 - µF surface-mount ceramic capacitors, including devices from Sprague and Kemet, meet the ESR
requirements stated above.
SGLS009B − MARCH 2003 − REVISED APRIL 2008
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
external capacitor requirements (continued)
RESET
OUT
OUT
7
6
5
IN
IN
EN
GND
3
16
14
13
VI
C1
0.1 µF
RESET
VO
10 µF
+
TPS767xx
Co
250 kΩ
Figure 26. Typical Application Circuit (Fixed Versions)
programming the TPS76701 adjustable LDO regulator
The output voltage of the TPS76701 adjustable regulator is programmed using an external resistor divider as
shown in Figure 27. The output voltage is calculated using:
VO+Vref ǒ1)R1
R2Ǔ(
1)
Where:
V
ref
= 1.1834 V typ (the internal reference voltage)
Resistors R1 and R2 should be chosen for approximately 50-µA divider current. Lower value resistors can be
used but offer no inherent advantage and waste more power. Higher values should be avoided as leakage
currents at FB increase the output voltage error. The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 50 µA and then calculate R1 using:
R1 +ǒVO
Vref *1Ǔ R2 (2)
OUTPUT
VOLTAGE R1 R2
2.5 V
3.3 V
3.6 V
4.75 V
UNIT
33.2
53.6
61.9
90.8
30.1
30.1
30.1
30.1
kΩ
kΩ
kΩ
kΩ
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VO
VIRESET
OUT
FB / NC
R1
R2
GND
EN
IN
≤0.9 V
≥1.7 V
TPS76701
Reset Output
0.1 µF250 kΩ
Co
Figure 27. TPS76701 Adjustable LDO Regulator Programming
SGLS009B − MARCH 2003 − REVISED APRIL 2008
18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
reset indicator
The TPS767xx features a RESET output that can be used to monitor the status of the regulator. The internal
comparator monitors the output voltage: when the output drops to between 92% and 98% of its nominal
regulated value, the RESET output transistor turns on, taking the signal low. The open-drain output requires
a pullup resistor. If not used, it can be left floating. RESET can be used to drive power-on reset circuitry or as
a low-battery indicator. RESET does not assert itself when the regulated output voltage falls outside the
specified 2% tolerance, but instead reports an output voltage low relative to its nominal regulated value (refer
to timing diagram for start-up sequence).
regulator protection
The TPS767xx PMOS pass transistor has a built-in back diode that conducts reverse currents when the input
voltage drops below the output voltage (e.g., during power down). Current is conducted from the output to the
input and is not internally limited. When extended reverse voltage is anticipated, external limiting may be
appropriate.
The TPS767xx also features internal current limiting and thermal protection. During normal operation, the
TPS767xx limits output current to approximately 1.7 A. When current limiting engages, the output voltage scales
back linearly until the overcurrent condition ends. While current limiting is designed to prevent gross device
failure, care should be taken not to exceed the power dissipation ratings of the package. If the temperature of
the device exceeds 150°C (typ), thermal-protection circuitry shuts it down. Once the device has cooled below
130°C (typ), regulator operation resumes.
power dissipation and junction temperature
Specified regulator operation is assured to a junction temperature of 1 2 5 °C; the maximum junction temperature
should be restricted to 125°C under normal operating conditions. This restriction limits the power dissipation
the regulator can handle in any given application. To ensure the junction temperature is within acceptable limits,
calculate the maximum allowable dissipation, PD(max), and the actual dissipation, PD, which must be less than
or equal to PD(max).
The maximum power dissipation limit is determined using the following equation:
PD(max) +TJmax *TA
RθJA
Where:
TJmax is the maximum allowable junction temperature.
TA is the ambient temperature.
RθJA is the thermal resistance junction-to-ambient for the package, i.e., 172°C/W for the 8-terminal
SOIC and 32.6°C/W for the 20-terminal PWP with no airflow.
The regulator dissipation is calculated using:
PD+ǒVI*VOǓ IO
Power dissipation resulting from quiescent current is negligible. Excessive power dissipation triggers the
thermal protection circuit.