NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 1
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
240pin DDR2 SDRAM Fully Buffered DIMM Based on 64Mx8 & 128Mx4 DDR2 SDRAM - B die
Features
• 512MB 64Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM (NT5TU64M8BE-25C).
• 1GB 128Mx72 DDR2 Fully Buffered DIMM based on 64Mx8
DDR2 SDRAM (NT5TU64M8BE-25C).
• 2GB 256Mx72 DDR2 Fully Buffered DIMM based on 128Mx4
DDR2 SDRAM (NT5TU128M4BE-25C).
• JEDEC Standard 240-pin Fully Buffered ECC Dual In-Line
Memory Module.
• Performance:
FBDIMM PC2-6400
Speed Sort -2C
DRAM DDR2-800
Unit
DIMM Latency
5 t CK
Channel Clock 200 MHz
DRAM Clock 400 MHz
• Inputs and outputs are SSTL-18 compatible.
• VDD = 1.8Volt ± 0.1, VDDQ = 1.8Volt ± 0.1.
• Host Interface and AMB component industry standard
compliant.
• Support SMBus protocol interface for access to the AMB
configuration registers.
• Detects errors on the channel and reports them to the host
memory controller.
• Automatic DDR2 DRAM Bus Calibration.
• Full Host Control of the DDR2 DRAMs.
• Over-Temperature Detection and Alert.
• MBIST & IBIST Test Functions.
• Transparent Mode for DRAM Test Support.
• Serial Presence Detect (SPD)
• Gold contacts
• RoHS Compliance
• SDRAM in 60-ball BGA Package
Description
NT512T72U89B1BD-2C, NT1GT72U8PB1BD-2C, and NT2GT72U4NB1BD-2C are Fully Buffered 240-Pin Double Data Rate 2 (DDR2)
Synchronous DRAM Dual In-Line Memory Module (DIMM) with Intel designed Heat Spreader, organized as one rank on 64Mx72; two
ranks of 128Mx72, and 256Mx72 high-speed memory array. The module uses nine 64Mx8 (512MB), eighteen 64Mx8 (1GB), and
thirty-six 128Mx4 (2GB) DDR2 SDRAMs in BGA packages. These DIMMs are manufactured using raw cards developed for broad
industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA
DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25” long space-saving footprint. The DIMM is intended
for use in applications operating up to 400MHz clock speeds and achieves high-speed data transfer rates of up to 800 MHz.
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 2
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Ordering Information
Part Number AMB Speed Organization
Leads
Note
NT2GT72U4NB1BD-2C 256Mx72
NT1GT72U8PB1BD-2C 128Mx72
NT512T72U89B1BD-2C
IDT C1-800
400MHz
(2.5ns @ CL = 5)
DDR2-800
PC2-6400
64Mx72
Gold Intel Designed
Heat Spreader
Note:
Module revision will change if AMB, PCB, or Heat spreader version changes.
Example:
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 3
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DIMM Connector Pin Description
Pin Name Pin Description
SCK System Clock Input, positive line
System Clock Input, negative line
PN0-PN13 Primary Northbound Data, positive lines
- Primary Northbound Data, negative lines
PS0-PS9 Primary Southbound Data, positive lines
- Primary Southbound Data, negative lines
SN0-SN13 Secondary Northbound Data, positive lines
- Secondary Northbound Data, negative lines
SS0-SS9 Secondary Southbound Data, positive lines
- Secondary Southbound Data, negative lines
SCL Serial Presence Detect (SPD) Clock Input
SDA SPD Data Input / Output
SA0-SA2 SPD Address Inputs, also used to select the DIMM number in the AMB
VID0-VID1 Voltage ID: These pins must be unconnected for DDR2-based Fully Buffered DIMMs
VID0 is VDD value: OPEN=1.8V, GND=1.5V; VID1 is VCC value: OPEN=1.5V, GND=1.2V
AMB reset signal
RFU Reserved for Future Use
VCC AMB Core Power and AMB Channel Interface Power (1.5V)
VDD DRAM Power and AMB DRAM I/O Power (1.8V)
VTT DRAM Address/Command/Clock Termination Power (VDD/2)
VDDSPD SPD Power (3.3V)
VSS Ground
DNU/M_TEST
It provides an external connection on 512MB/1GB for testing the margin of Vref which is
produced by a voltage divider on the module. It is not intended to be used in normal
system operation and must not be connected (DNU) in a system. This test pin may have
other features on future card designs and if it does, will be included in this specification at
that time.
Note:
1. System Clock Signals SCK and SCK switch at one half the DRAM CK/ frequency
2. Eight pins reserved for forwarded clocks, eight pins reserved for future architecture flexibility
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 4
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DDR2 240-pin FBDIMM Pinout
Pin
Front Side
Pin
Front Side
Pin
Front Side
Pin
Back Side
Pin
Back Side
Pin
Back Side
1 VDD 42 VSS 82 PS4 121
VDD 162
VSS 202
SS4
2 VDD 43 VSS 83 122
VDD 163
VSS 203
3 VDD 44 RFU* 84 VSS 123
VDD 164
RFU* 204
VSS
4 VSS 45 RFU* 85 VSS 124
VSS 165
RFU* 205
VSS
5 VDD 46 VSS 86 RFU* 125
VDD 166
VSS 206
RFU*
6 VDD 47 VSS 87 RFU* 126
VDD 167
VSS 207
RFU*
7 VDD 48 PN12 88 VSS 127
VDD 168
SN12 208
VSS
8 VSS 49 89 VSS 128
VSS 169
209
VSS
9 VCC 50 VSS 90 PS9 129
VCC 170
VSS 210
SS9
10 VCC 51 PN6 91 130
VCC 171
SN6 211
11 VSS 52 92 VSS 131
VSS 172
212
VSS
12 VCC 53 VSS 93 PS5 132
VCC 173
VSS 213
SS5
13 VCC 54 PN7 94 133
VCC 174
SN7 214
14 VSS 55 95 VSS 134
VSS 175
215
VSS
15 VTT 56 VSS 96 PS6 135
VTT 176
VSS 216
SS6
16 VID1 57 PN8 97 136
VID0 177
SN8 217
17 58 98 VSS 137
DNU/M_TEST
178
218
VSS
18 VSS 59 VSS 99 PS7 138
VSS 179
VSS 219
SS7
19 RFU** 60 PN9 100
139
RFU** 180
SN9 220
20 RFU** 61 101
VSS 140
RFU** 181
221
VSS
21 VSS 62 VSS 102
PS8 141
VSS 182
VSS 222
SS8
22 PN0 63 PN10 103
142
SN0 183
SN10 223
23 64 104
VSS 143
184
224
VSS
24 VSS 65 VSS 105
RFU** 144
VSS 185
VSS 225
RFU**
25 PN1 66 PN11 106
RFU** 145
SN1 186
SN11 226
RFU**
26 67 107
VSS 146
187
227
VSS
27 VSS 68 VSS 108
VDD 147
VSS 188
VSS 228
SCK
28 PN2 KEY 109
VDD 148
SN2 KEY 229
29 69 VSS 110
VSS 149
189
VSS 230
VSS
30 VSS 70 PS0 111
VDD 150
VSS 190
SS0 231
VDD
31 PN3 71 112
VDD 151
SN3 191
232
VDD
32 72 VSS 113
VDD 152
192
VSS 233
VDD
33 VSS 73 PS1 114
VSS 153
VSS 193
SS1 234
VSS
34 PN4 74 115
VDD 154
SN4 194
235
VDD
35 75
VSS 116
VDD 155
195
VSS 236
VDD
36 VSS 76 PS2 117
VTT 156
VSS 196
SS2 237
VTT
37 PN5 77 118
SA2 157
SN5 197
238
VDDSPD
38 78 VSS 119
SDA 158
198
VSS 239
SA0
39 VSS 79 PS3 120
SCL 159
VSS 199
SS3 240
SA1
40 PN13 80 160
SN13 200
41 81 VSS 161
201
VSS
Note:
RFU = Reserved Future Use
* These pin positions are reserved for forwarded clocks to be used in future module implementation
** These pin positions are reserved for future architecture flexibility
The following signals are CRC bits and thus appear out of the normal sequence: PN12/, SN12/, PN13/, SN13/,
PS9/, SS9/
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 5
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Functional Block Diagram (512MB, 1Rank, 64Mx8 DDR2 SDRAMs)
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 6
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Functional Block Diagram (1GB, 2Ranks, 64Mx8 DDR2 SDRAMs)
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NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 7
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Functional Block Diagram (2GB, 2Ranks, 128Mx4 DDR2 SDRAMs)
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 8
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
DC Electrical Characteristics and Operating Conditions
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See Device AC Characteristics)
Symbol Parameter Min Typ. Max Units
Notes
VCC AMB supply Voltage 1.46 1.5 1.54 V
VDD Supply Voltage 1.7 1.8 1.9 V 1
VDDSPD EEPROM supply Voltage 3.0 3.3 3.6 V
VDDL Supply Voltage for DLL 1.7 1.8 1.9 V 5
VDDQ Supply Voltage for Output 1.7 1.8 1.9 V 1,5
VREF I/O Reference Voltage 0.48 x VDDQ
0.50xVDDQ
0.52 x VDDQ
V 2,3
VTT I/O Termination Voltage (System) VREF - 0.04 VREF VREF + 0.04
V 4
Note:
1. There is no specific device VDD supply requirement for SSTL_18 compliance. However, under all conditions VDDQ must be less
than or equal to VDD.
2. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5VDDQ of the transmitting device and VREF is expected to track variations is VDDQ.
3. Peak to peak AC noise on VREF may not exceed ±0.2% VREF(dc).
4. VTT of transmitting device must track VREF of receiving device.
5. VDDQ tracks with VDD, VDDL tracks with VDD.
Input DC Logic Level
Symbol
Parameter/Condition Min Max Unit
VIH (AC)
Input High (Logic 1) Voltage VREF + 0.125 VDDQ + 0.3 V
VIL (AC)
Input Low (Logic 0) Voltage -0.3 VREF - 0.125 V
Input AC Logic Level
Symbol
Parameter/Condition Min Max Unit
VIH (AC)
Input High (Logic 1) Voltage V REF + 0.20 - V
VIL (AC)
Input Low (Logic 0) Voltage - V REF - 0.20 V
Environmental Requirements
Symbol Parameter Rating Units Note
TOPR Operating temperature - 1
HOPR Operating humidity (relative) 10 to 90 % 2
TSTG Storage temperature -50 to +100 ºC 2
HSTG Storage humidity (without condensation) 5 to 95 % 2
PBAR Barometric pressure (operating & Storage) 105 to 69 K pascal
2
Note:
1. The designer must meet the case temperature specifications for individual module components. Please refer to device spec.
2. Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only and device
functional operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 9
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect -- Part 1 of 2
PC2-6400 (-2C)
Serial PD Data Entry
(Hexadecimal)
Byte Description
512MB
1GB 2GB
0 Number of Serial PD Bytes Written / SPD Device Size / CRC Coverage 92 92 92
1 SPD Revision 11 11 11
2 Key Byte / DRAM Device Type 09 09 09
3 Voltage Levels of this Assembly 12 12 12
4 SDRAM Addressing 44 44 48
5 Module Physical Attributes 23 23 23
6 Modules Type / Thickness 07 07 07
7 Module Organization 09 11 10
8 Fine Timebase Dividend and Divisor 52 52 52
9 Medium Timebase Dividend 01 01 01
10 Medium Timebase Divisor 04 04 04
11 SDRAM Minimum Cycle Time (tCKmin) 0A 0A 0A
12 SDRAM Maximum Cycle Time (tCKmax) 20 20 20
13 SDRAM Latencies Supported 43 43 43
14 SDRAM Minimum CAS Latency Time (tCAS) 32 32 32
15 SDRAM Write Recovery Times Supported 42 42 42
16 SDRAM Write Recovery Time (tWR) 3C 3C 3C
17 SDRAM Write Latencies Supported 42 42 42
18 SDRAM Additive Latencies Supported 40 40 40
19 SDRAM Minimum to Delay (tRCD) 32 32 32
20 SDRAM Minimum Row Active to Row Active Delay (tRRD) 1E 1E 1E
21 SDRAM Minimum Row Precharge Time (tRP) 32 32 32
22 SDRAM Upper Nibbles for tRAS and tRC 00 00 00
23 SDRAM Minimum Active to Precharge Time (tRAS) B4 B4 B4
24 SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Time (tRC) F0 F0 F0
25~26
SDRAM Minimum Auto-Refresh to Active/Auto-Refresh Command Period
(tRFC) A401 A401 A401
27 SDRAM Internal Write to Read Command Delay (tWTR) 1E 1E 1E
28 SDRAM Internal Read to Precharge Command Delay (tRTP) 1E 1E 1E
29 SDRAM Burst Lengths Supported 03 03 03
30 SDRAM Terminations Supported 07 07 07
31 SDRAM Drivers Supported 01 01 01
32 SDRAM Average Refresh Interval (tREFI)/Double Refresh mode bit/High
Temperature self-refresh rate support indication C2 C2 C2
33 Tcasemax / DT4R4W 53 51 51
34 Thermal resistance of SDRAM device package from top (case0 to ambient
(Psi T-A SDRAM) 7A 7A 7A
35 DT0: Case temperature rise from ambient due to IDD2N/precharge
operation minus 2.8°C offset temperature 50 60 60
36
DT2N/DT2Q: Case temperature rise from ambient due to IDD2Q/precharge
quiet standby operation for FBDIMM 2F 35 35
37 DT2P: Case temperature rise from ambient due to IDD2P/precharge
power-down operation 37 37 37
38 DT3N: Case temperature rise from ambient due to IDD3N/active standby
operation 27 2F 2F
39 DT4R: Case temperature rise from ambient due to Page Open Burst
Read/DT4R4W Mode Bit (DT4R/DT4R4W) 4C 56 56
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 10
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Serial Presence Detect – Part 2 of 2
PC2-6400 (-2C)
Serial PD Data Entry
(Hexadecimal)
Byte Description
512MB
1GB 2GB
40 DT5B: Case temperature rise from ambient due to IDD5B/burst refresh
operation 26 29 29
41 DT7: Case temperature rise from ambient due to IDD7/bank interleave
read mode operation 28 28 28
42-78
Reserved -- -- --
79 ODT termination 01 21 21
80 Reserved 00 00 00
81-82
FB-DIMM Channel Protocols Supported 0200 0200 0200
83 Back to back access turn around time 10 10 10
84 AMB Read Access Time for DDR2-800 36 36 36
85 AMB Read Access Time for DDR2-667 34 34 34
86 AMB Read Access Time for DDR2-533 32 32 32
87 Thermal resistance of AMB package from top(junction) to ambient(Psi T-A
SDRAM) at still air condition 2A 2A 2A
88 AMB DT Idle_0 5D 5D 64
89 AMB DT Idle_1 71 71 7B
90 AMB DT Idle_2 65 65 65
91 AMB DT Active_1 9B 9B A3
92 AMB DT Active_2 7F 7F 87
93 AMB DT L0s 00 00 00
94-97
Reserved -- -- --
98 AMB junction temp. Max. (Tjmax) 1F 1F 1F
99 Reserved 0A 0A 0A
100 Reserved 00 00 00
101 AMB personality Bytes: Pre-initialization(1) 00 00 00
102 AMB personality Bytes: Pre-initialization(2) E2 E2 E2
103 AMB personality Bytes: Pre-initialization(3) 62 62 62
104 AMB personality Bytes: Pre-initialization(4) 20 20 20
105 AMB personality Bytes: Pre-initialization(5) 80 80 80
106 AMB personality Bytes: Pre-initialization(6) 9C 9C 9C
107 AMB personality Bytes: Post-initialization(1) 00 00 00
108 AMB personality Bytes: Post-initialization(2) 00 00 00
109 AMB personality Bytes: Post-initialization(3) F0 F0 F0
110 AMB personality Bytes: Post-initialization(4) 70 70 70
111 AMB personality Bytes: Post-initialization(5) 60 60 60
112 AMB personality Bytes: Post-initialization(6) 60 60 60
113 AMB personality Bytes: Post-initialization(7) 60 60 60
114 AMB personality Bytes: Post-initialization(8) 60 60 60
115-116
AMB manufacture’s JEDEC ID code 7FB3 7FB3 7FB3
117-118
Module ID: Module Manufacture’s JEDEC ID code 830B 830B 830B
119-255
Reserved -- -- --
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 11
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Operating, Standby, and Refresh Currents
(Test condition: Vdd=1.8V, Vcc=1.5V, Room temperature)
Symbol Parameter/Condition 512MB 1GB 2GB Unit
Idd_Idle_0
968 1364 2431 mA
Icc_Idle_0
Idle Current, single or last DIMM. L0 state, idle (0BW). Primary
channel enabled; Secondary Channel disabled. Command and
address lines stable, DRAM clock active. CKE high. 2871 2871 2871 mA
Idd_Idle_1
968 1364 2431 mA
Icc_Idle_1
Idle Current, first DIMM. L0 stage, idle (0BW). Primary and
Secondary channels enabled. CKE high. Command and address line
stable. DRAM clock active. 4301 4301 4301 mA
Idd_Idle_2
209 231 297 mA
Icc_Idle_2
Idle Current, DRAM power down. L0stage, idle (0BW). Primary and
Secondary channels enabled CKE low. Command and address lines
floated. DRAM clock active, ODT and CKE driven low. 4312 4312 4312 mA
Idd_Active_1
(Read) 2640 3498 5412 mA
Icc_Active_1
(Read)
Active Power. L0 state. 50% DRAM BW to downstream DIMM, 100%
read. Primary and Secondary channels enabled, DRAM clock active,
CKE high. 4851 4851 4851 mA
Idd_Active_1
(Write) 2728 3498 5412 mA
Icc_Active_1
(Write)
Active Power. L0 state. 50% DRAM BW to downstream DIMM, 100%
write. Primary and Secondary channels enabled, DRAM clock active,
CKE high. 4653 4653 4653 mA
Idd_Active_2
979 1386 2464 mA
Icc_Active_2
Active Power, data pass through. L0 state. 50% DRAM BW to
downstream DIMM, 67% read, 33% write. Primary and Secondary
channels enabled. CKE high. Command and address lines stable.
DRAM clock active. 4554 4554 4554 mA
Idd_Training
979 1386 2453 mA
Icc_Training
Primary and Secondary channels enabled. 100% toggle on all channel
lanes. DRAMs idle. 0BW. CKE high, Command and address line
stable. DRAM clock active. CKE high. 4224 4224 4224 mA
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 12
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
-2C
Symbol
Parameter Min.
Max.
Unit
Notes
tCK Average clock period 2500
8000
ps
tCH Average clock high-level width 0.48
0.52
tCK
tCL Average clock low-level width 0.48
0.52
tCK
WL Average command to DQS associated clock
edge RL-1 nCK
tDQSS Write command to 1st DQS latching transition -0.25
0.25
tCK
tDSS DQS falling edge to CK setup time
(write cycle) 0.2
- tCK
tDSH DQS falling edge hold time from CK
(write cycle) 0.2
- tCK
tDQSL,(H)
DQS input low (high) pulse width
(write cycle) 0.35
- tCK
tWPRE Write preamble 0.35
- tCK
tWPST Write postamble 0.40
0.60
tCK
tIS Address and control input setup time 175
- ps
tIH Address and control input hold time 250
- ps
tIPW Input pulse width 0.6
- tCK
tDS DQ and DM input setup time 50
- ps
tDH DQ and DM input hold time 125
- ps
tDIPW DQ and DM input pulse width (each input) 0.35
- tCK
tAC DQ output access time from CK/ -400
+400
ps
tDQSCK DQS output access time from CK/ -350
+350
ps
tHZ Data-out high-impedance time from CK/ - tAC max
ps
tLZ(DQS) DQS/ low-impedance time from CK/ tAC min
tAC max
ps
tLZ(DQ) Data-out low-impedance time from CK/ 2tAC
min tAC max
ps
tDQSQ DQS-DQ skew (DQS & associated DQ signals)
- 200
ps
tHP Minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH(abs)
or
tCL(abs)
- ps
tQHS Data hold Skew Factor - 300
ps
tQH Data output hold time from DQS tHP -
tQHS
- ps
tRPRE Read preamble 0.9
1.1
tCK
tRPST Read postamble 0.4
0.6
tCK
tRRD Active bank A to Active bank B command 7.5
- ns
tFAW Four Activate Window 35
- ns
tCCD to command delay 2 - nCK
tWR Write recovery time 15
- ns
tDAL Auto precharge write recovery + precharge time
WR
+tnRP
- nCK
tWTR Internal write to read command delay 7.5
- ns
tRTP Internal read to precharge command delay 7.5
- ns
tCKE CKE minimum pulse width 3 - nCK
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 13
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2)
-2C
Symbol
Parameter Min.
Max.
Unit
Notes
tXSNR Exit self refresh to a Non-read command tRFC
+10
- ns
tXSRD Exit self refresh to a Read command 200
- nCK
tXP Exit precharge power down to any Non- read
command 2 - nCK
tXARD Exit active power down to read command 2 - nCK
tXARDS Exit active power down to read command 8-AL
- nCK
tAOND ODT turn-on delay 2 2 nCK
tAON ODT turn-on tAC(min)
tAC(max)
+0.7
ns
tAONPD ODT turn-on (Power down mode) tAC(min)
+2
2tCK +
tAC(max)
+1
ns
tAOFD ODT turn-off delay 2.5
2.5
nCK
tAOF ODT turn-off tAC(min)
tAC(max)
+0.6
ns
tAOFPD ODT turn-off (Power down mode) tAC(min)
+2
2.5tCK
+
tAC(max)
+1
ns
tANPD ODT to power down entry latency 3 - nCK
tAXPD ODT power down exit latency 8 nCK
tMRD Mode register set command cycle time 2 - nCK
tMOD MRS command to ODT update delay 0 12
ns
tOIT OCD drive mode output delay 0 12
ns
tDelay Minimum time clocks remains ON after CKE
asynchronously drops Low
tIS +
tCK +
tIH - ns
WR Write recovery time with Auto-Precharge tWR/tCK
ns
Refresh parameters
tRFC Refresh to active/Refresh command time 105 ns
Average Periodic Refresh Interval
(85ºC < TCASE < 95ºC) 3.9 =s
tREFI Average Periodic Refresh Interval
(0ºC < TCASE < 85ºC) 7.8 =s
Speed Grade Definition
tRAS ACT to PRE delay 45
70000
ns
tRCD ACT to RD(A) or WT(A) delay 12.5
- ns
tRP PRE to ACT delay 12.5
- ns
tRC ACT to ACT delay 57.5
- ns
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 14
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Package Dimensions
22"25>% "5
1"5
"2
4
3"4
5
2"25 >%"5
">% "
?
@"6"6
"5>% "
"6>% "'-,
2"6
".+,
"5
"5
NT512T72U89B1BD-2C / NT1GT72U8PB1BD-2C / NT2GT72U4NB1BD-2C
512MB: 64Mx72 / 1GB: 128Mx72 / 2GB: 256Mx72
REV 1.0 15
09/2007 © NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Revision Log
Rev Date Modification
0.1 09/2007 Preliminary Release.
1.0 09/2007 Official Release.
