UL6264A Low Voltage 8K x 8 SRAM p Packages: Features p 8192 x 8 bit static CMOS RAM p 250 and 500 ns Access Times p Common data inputs and data outputs p Three-state outputs p Typ. operating supply current: p p p p p p p p p 250 ns: 12 mA 500 ns: 7 mA Standby current < 5 A Standby current at 25 C and 3.3 V: typ. 50 nA TTL/CMOS-compatible Automatic reduction of power dissipation in long Read or Write cycles Power supply voltage 3.3 V Operating temperature ranges 0 to 70 C -25 to 85 C -40 to 85 C Quality assessment according to CECC 90000, CECC 90100 and CECC 90111 ESD protection > 2000 V (MIL STD 883C M3015.7) Latch-up immunity > 100 mA change, the data outputs go High-Z until the new read information is available. The data outputs have no preferred state. If the memory is driven by CMOS levels in the active state, and if there is no change of the address, data input and control signals W or G, the operating current (at IO = 0 mA) drops to the value of the operating current in the Standby mode. The Read cycle is finished by the falling edge of E2 or W, or by the rising edge of E1, respectively. Data retention is guaranteed down to 2 V. With the exception of E2, all inputs consist of NOR gates, so that no pull-up/pull-down resistors are required. This gate circuit allows to achieve low power standby requirements by activation with TTL-levels too. If the circuit is inactivated by E2 = L, the standby current (TTL) drops to 100 A typ. PDIP28(600 mil) SOP28 (330 mil) Description The UL6264A is a static RAM manufactured using a CMOS process technology with the following operating modes: - Read - Standby - Write - Data Retention The memory array is based on a 6-transistor cell. The circuit is activated by the rising edge of E2 (at E1 = L) or the falling edge of E1 (at E2 = H). The address and control inputs open simultaneously. According to the information of W and G the data inputs, or outputs, are active. In the active state E1 = L and E2 = H, each address change leads to a new Read or Write cycle. In a Read cycle, the data outputs are activated by the falling edge of G, afterwards the data word read will be available at the outputs DQ0 - DQ7. After the address Pin Description Pin Configuration n.c. 1 28 VCC A12 2 27 W (WE) A7 3 26 E2 (CE2) A6 4 25 A8 Signal Name A5 5 24 A9 A0 - A12 Address Inputs A4 6 23 A11 DQ0 - DQ7 Data In/Out A3 7 E1 8 PDIP 22 SOP 21 Chip Enable 1 A2 A1 9 20 E (CE1) G (OE) A10 A0 10 19 DQ7 DQ0 11 18 DQ6 DQ1 12 17 13 16 DQ2 VSS 14 15 DQ5 DQ4 DQ3 Top View December 12, 1997 315 Signal Description E2 Chip Enable 2 G Output Enable W Write Enable VCC Power Supply Voltage VSS Ground n.c. not connected UL6264A A3 A10 Memory Cell Array 256 Rows x 256 Columns DQ0 Sense Amplifier/ Write Control Logic Address Change Detector Clock Generator E2 VSS VCC 1 W DQ1 Common Data-I/O A2 Row Decoder A1 Column Decoder A0 Row Address Inputs A4 A5 A6 A7 A8 A9 A11 A12 Column Address Inputs Block Diagram DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 G E1 Truth Table Operating Mode E1 E2 W G DQ0 - DQ7 Standby/not selected * L * * High-Z H * * * High-Z Internal Read L H H H High-Z Read L H H L Data Outputs Low-Z Write L H L * Data Inputs High-Z * H or L Characteristics All voltages are referenced to V SS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified. Dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of V I, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the t dis-times, in which cases transition is measured 200 mV from steady-state voltage. Maximum Ratings Symbol Min. Max. Unit VCC -0.3 7 V Input Voltage VI -0.3 VCC + 0.5 V Output Voltage VO -0.3 VCC + 0.5 V Power Dissipation PD 1 W Power Supply Voltage Operating Temperature Storage Temperature C-Type G-Type K-Type Ta 0 -25 -40 70 85 85 C C C Tstg -55 125 C 316 December 12, 1997 UL6264A Recommended Operating Conditions Symbol Conditions Min. Max. Unit 3.6 V Power Supply Voltage VCC 3.0 Data Retention Voltage VCC(DR) 2.0 Input Low Voltage* VIL -0.3 0.8 V Input High Voltage VIH 2.0 VCC + 0.3 V Max. Unit 20 30 mA mA 5 A 2 (typ. 0.7) mA V * -2 V at Pulse Width 10 ns Electrical Characteristics Supply Current - Operating Mode Symbol ICC(OP) Conditions VCC VIL VIH tcW tcW = = = = = 3.6 V 0.8 V 2.0 V 500 ns 250 ns Supply Current - Standby Mode (CMOS level) ICC(SB) VCC VE1 = VE2 = 3.6 V = VCC - 0.2 V Supply Current - Standby Mode (TTL level) ICC(SB)1 VCC VE1 = VE2 = 3.6 V = 2.0 V VCC IOH VCC IOL = 3.0 V = -1.0 mA = 3.0 V = 2.0 mA VCC VIH VCC VIL = 3.6 V = 3.6 V = 3.6 V = 0V VCC VOH VCC VOL = = = = VCC VOH VCC VOL = 3.6 V = 3.6 V = 3.6 V = 0V Output High Voltage VOH Output Low Voltage VOL Input High Leakage Current IIH Input Low Leakage Current IIL Output High Current IOH Output Low Current IOL Output Leakage Current High at Three-State Outputs IOHZ Low at Three-State Outputs IOLZ December 12, 1997 317 Min. 3.0 V 2.4 V 3.0 V 0.4 V 2.4 V 0.4 V 1 A A -1 -1 2.0 mA 1 -1 mA A A UL6264A Symbol Min. Max. Unit Switching Characteristics Alt. IEC 25 50 Time to Output in Low-Z tLZ tt(QX) 20 20 ns G LOW to Output in Low-Z tOLZ ttG(QX) 10 10 ns Cycle Time Write Cycle Time Read Cycle Time tWC tRC tcW tcR 250 250 500 500 ns ns Access Time E1 LOW or E2 HIGH to Data Valid G LOW to Data Valid Address to Data Valid tACE tOE tAA ta(E) ta(G) ta(A) - - Pulse Widths Write Pulse Width Chip Enable to End of Write tWP tCW tw(W) tw(E) 120 180 150 210 ns ns Setup Times Address Setup Time Chip Enable to End of Write Write Pulse Width Data Setup Time tAS tCW tWP tDS tsu(A) tsu(E) tsu(W) tsu(D) 0 180 120 80 0 210 150 100 ns ns ns ns Data Hold Time Address Hold Time from End of Write tDH tAH th(D) th(A) 0 0 0 0 ns ns Output Hold Time from Address Change tOH tv(A) 20 20 ns tHZCE tdis(E) 0 0 60 60 ns tHZWE tHZOE tdis(W) tdis(G) 0 0 0 0 60 40 60 40 ns ns E1 HIGH or E2 LOW to Output in High-Z W LOW to Output in High-Z G HIGH to Output in High-Z 25 250 100 250 50 500 100 500 ns ns ns Data Retention Mode E2-Controlled Data Retention Mode E1-Controlled VCC 3.0 V VCC 3.0 V VCC(DR) 2 V VCC(DR) 2 V 2.0 V tDR Data Retention trec 2.0 V E1 0V tDR 0.8 V Data Retention VE2(DR) 0.2 V E2 trec 0.8 V 0V VE2(DR) VCC(DR) - 0.2 V or VE2(DR) 0.2 V VCC(DR) - 0.2 V VE1(DR) VCC(DR) + 0.3 V Chip Deselect to Data Retention Time Operating Recovery Time tDR: trec: min 0 ns min tcR 318 December 12, 1997 UL6264A Test Configuration for Functional Check VIL E1 E2 W G DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Simultaneous Measure- VIH 3.3 V VCC ment of all 8 output pins Input level according to the relevant test measurement A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 960 VO Q Q 510 VSS L1 Conditions 5 pF 100 pF L1: For dynamic measurement except tdis-times Capacitance VO Q L2 L2: For tdis-times Symbol Min. Max. Unit Input Capacitance VCC = 3.3 V VI = VSS CI 8 pF Output Capacitance f Ta CO 10 pF = 1 MHz = 25 C All pins not under test must be connected with ground by capacitors. IC Code Numbers Example UL6264A D G 25 Type Access Time 25 = 250 ns 50 = 500 ns Package D = PDIP S = SOP Operating Temperature Range C = 0 to 70 C G = -25 to 85 C K = -40 to 85 C The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last 2 digits the calendar week. December 12, 1997 319 UL6264A Read Cycle 1 (during Read Cycle: E1 = G = VIL, E2 = W = VIH) tcR Ai Addresses Valid ta(A) DQi Output AAAAAAAAAAA AAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAA Previous Data Valid tv(A ) Output Data Valid AAAAAAAA AAAA AAAAAAAA AAAA AAAAAAAA Read Cycle 2 (during Read Cycle: W = VIH) tcR Ai Addresses Valid tsu(A ) ta(E) tt(QX) E1 tdis(E) ta(E) tsu(A) E2 tdis(E) tt(QX) ta(G) G ttG(QX) DQi tdis(G) AAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAA AAA Output Output Data Valid Write Cycle 1 (W-controlled) tcW Ai Addresses Valid tsu(E) E1 AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAA AA E2 AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tsu(A ) th(A ) AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tsu(E) AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tw(W) W tsu(D) DQi Input tdis(W) DQi High-Z Output G th(D) Input Data Valid tt(QX) AAAA AAAA AAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAA AAA AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA 320 December 12, 1997 UL6264A Write Cycle 2 (E1-controlled) tcW Ai Addresses Valid tsu(A) tw(E) th(A ) E1 tsu(E) E2 AAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAA W AAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA tsu(W) AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA tsu(D) AAAAAAAAAAAA th(D) AAAAAAAAAAAAAAAAAAAA DQi Input Input Data Valid tdis(W) tt(QX ) DQi High-Z Output AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA G Write Cycle 3 (E2-controlled) tcW Ai Addresses Valid tsu(E) AAAA AAAAAAAA AAAAAAAA AAAAAA AA AAAAAAAA AAAAAAAA AAAAAA AA AAAA E1 tsu(A ) th(A ) AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA tw(E) E2 AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA W tsu(W) tsu(D) DQi Input DQi th(D) Input Data Valid tdis(W) tt(QX) AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAA High-Z Output AAAA AAAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA AAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAA AAA G undefined December 12, 1997 AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAAAAAAAAAAAA L- or H-Level 321 AAAA AAAA AAAA AA AAAA AAAA AAAA AAAA AAAA AAAA A AAAA AAAA AAAA AAAAAAAAAAAAAA LIFE SUPPORT POLICY ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the ZMD product could create a situation where personal injury or death may occur. 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