UL6264ASC50G1 - Alliance Memory, Inc.

315 December 12, 1997

UL6264A

p

Packages:PDIP28(600 mil)

SOP28 (330 mil)

Description

The UL6264A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read - Standby

- Write - Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the rising

edge of E2 (at E1 = L) or the falling

edge of E1 (at E2 = H). The

address and control inputs open

simultaneously. According to the

information of W and G the data

inputs, or outputs, are active. In the

active state E1 = L and E2 = H,

each address change leads to a

new Read or Write cycle. In a Read

cycle, the data outputs are activa-

ted by the falling edge of G, after-

wards the data word read will be

available at the outputs

DQ0 - DQ7. After the address

change, the data outputs go High-Z

until the new read information is

available. The data outputs have no

preferred state. If the memory is

driven by CMOS levels in the active

state, and if there is no change of

the address, data input and control

signals W or G, the operating cur-

rent (at IO = 0 mA) drops to the

value of the operating current in the

Standby mode. The Read cycle is

finished by the falling edge of E2 or

W, or by the rising edge of E1,

respectively.

Data retention is guaranteed down

to 2 V.

With the exception of E2, all inputs

consist of NOR gates, so that no

pull-up/pull-down resistors are

required. This gate circuit allows to

achieve low power standby require-

ments by activation with TTL-levels

too.

If the circuit is inactivated by E2 = L,

the standby current (TTL) drops to

100 µA typ.

Features

p

8192 x 8 bit static CMOS RAM

p

250 and 500 ns Access Times

p

Common data inputs and data

outputs

p

Three-state outputs

p

Typ. operating supply current:

250ns:12 mA

500 ns: 7 mA

p

Standby current < 5 µA

p

Standby current at 25 °C

and 3.3 V: typ. 50 nA

p

TTL/CMOS-compatible

p

Automatic reduction of power

dissipation in long Read or Write

cycles

p

Power supply voltage 3.3 V

p

Operating temperature ranges

0 to 70 °C

-25 to 85 °C

-40 to 85 °C

p

Quality assessment according to

CECC 90000, CECC 90100 and

CECC 90111

p

ESD protection > 2000 V

(MIL STD 883C M3015.7)

p

Latch-up immunity > 100 mA

Low Voltage 8K x 8 SRAM

Pin Description

Signal Name Signal Description

A0 - A12 Address Inputs

DQ0 - DQ7 Data In/Out

E1 Chip Enable 1

E2 Chip Enable 2

GOutput Enable

WWrite Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Configuration

1n.c. VCC28

2A12W (WE)27

4A6 A825

5A5 A924

3A7 E2 (CE2)26

6A4 A1123

7A3 G (OE)22

8A2 A1021

12DQ1DQ517

9A1 E (CE1)20

10A0 DQ719

11DQ0DQ618

13DQ2DQ416

14VSS DQ315

PDIP

Top View

SOP

316 December 12, 1997

UL6264A

Address

Change

Detector

*H or L

Operating Mode E1 E2 W G DQ0 - DQ7

Standby/not

selected*L** High-Z

H*** High-Z

Internal Read L H H H High-Z

Read L H H L Data Outputs Low-Z

Write L H L * Data Inputs High-Z

Truth Table

A0

A1

A2

A3

A10

Memory Cell

Array

256 Rows x

256 Columns

Row Decoder

Row Address

Inputs

Column D ecoder

Common Da ta-I/O

Sense Amplifier/

Write Control Logic

Clock

Generator

1

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

Maximum Ratings Symbol Min. Max. Unit

Power Supply Voltage VCC -0.3 7 V

Input Voltage VI-0.3 VCC + 0.5 V

Output Voltage VO-0.3 VCC + 0.5 V

Power Dissipation PD1W

Operating

Temperature C-Type

G-Type

K-Type

Ta0

-25

-40

70

85

°C

Storage Temperature Tstg-55 125 °C

E2

E1

Characteristics

Column Address

Inputs

VCC VSS W G

Block DiagramA4

A5

A6

A7

A8

A9

A11

A12

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI,as well as

input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.

317 December 12, 1997

UL6264A

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode

(CMOS level)

Supply Current- Standby Mode

(TTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

VE1 = V E2

VCC

VE1 = V E2

= 3.6 V

= 0.8 V

= 2.0 V

= 500 ns

= 250 ns

= 3.6 V

= V

CC - 0.2 V

= 3.6 V

= 2.0 V

20

30

5

2

(typ. 0.7)

mA

µA

mA

Output High Voltage

Output Low Voltage

VOH

VOL

VCC

IOH

VCC

IOL

= 3.0 V

=-1.0 mA

= 3.0 V

= 2.0 mA

2.4

0.4

V

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 3.6 V

= 0 V -1

1 µA

µA

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

= 3.0 V

= 2.4 V

= 3.0 V

= 0.4 V2.0

-1 mA

mA

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

= 3.6 V

=3.6 V

= 0 V -1

1 µA

µA

Recommended Operating

Conditions Symbol Conditions Min. Max. Unit

Power Supply Voltage VCC 3.0 3.6 V

Data Retention Voltage VCC(DR) 2.0 V

Input Low Voltage* VIL -0.3 0.8 V

Input High Voltage VIH 2.0 VCC + 0.3 V

* -2 V at Pulse Width 10 ns

318 December 12, 1997

UL6264A

Switching Characteristics Symbol Min. Max. Unit

Alt.IEC25502550

Time to Output in Low-Z tLZ tt(QX)20 20 ns

G LOW to Output in Low-Z tOLZttG(QX)10 10 ns

Cycle Time

Write Cycle Time

Read Cycle TimetWC

tRC

tcW

tcR

250

250500

500ns

ns

Access Time

E1 LOW or E2 HIGH to Data Valid

G LOW to Data Valid

Address to Data Valid

tACE

tOE

tAA

ta(E)

ta(G)

ta(A)

-

250

100

250

500

100

500

ns

Pulse Widths

Write Pulse Width

Chip Enable to End of Write tWP

tCW

tw(W)

tw(E)

120

180150

210ns

ns

Setup Times

Address Setup Time

Chip Enable to End of Write

Write Pulse Width

Data Setup Time

tAS

tCW

tWP

tDS

tsu(A)

tsu(E)

tsu(W)

tsu(D)

0

180

120

80

0

210

150

100

ns

Data Hold Time

Address Hold Time from End of Write tDH

tAH

th(D)

th(A)

0

00

0ns

ns

Output Hold Time from Address

ChangetOH tv(A)20 20 ns

E1 HIGH or E2 LOW to Output in

High-Z

W LOW to Output in High-Z

G HIGH to Output in High-Z

tHZCE

tHZWE

tHZOE

tdis(E)

tdis(W)

tdis(G)

0

60

40

60

40

ns

VCC(DR) ≥ 2 V

Data Retention Mode E1-Controlled Data Retention Mode E2-Controlled

Data Retention

3.0 V

tDR trec

VCC

E1

VCC(DR) ≥ 2 V

VE2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V

VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V

0 V

Data Retentiontrec

tDR

0.8 V0.8 V VE2(DR) ≤ 0.2 V

2.0 V2.0 V

3.0 V

0 V

VCC

E2

Chip Deselect to Data Retention Time tDR:min 0 ns

Operating Recovery Time trec:min t

cR

319 December 12, 1997

UL6264A

Test Configuration for Functional Check

VIH

VIL

VSS

VCC 3.3 V

960

510

5 pF

VO

Simultaneous Measure-

men t of all 8 output pins

Input leve l acco r di ng to the

relevant test measurement

L1: For dynamic measurement except tdis-times L2: For tdis-times

IC Code Numbers

Example

The date of manufacture is given by the 4 last digits of the mark, the first 2 digits indicating the year, and the last

2 digits the calendar week.

DUL6264A 25G

Type

Package

D = PDIP

S = SOP

Access Time

25 = 250 ns

50 = 500 ns

Operating Temperature Range

C = 0 to 70 °C

G = -25 to 85 °C

K = -40 to 85 °C

All pins not under test must be connected with ground by capacitors.

100 pF

VO

QQ Q

L1 L2

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC = 3.3 V

VI = VSS CI8pF

Output Capacitance f = 1 MHz

Ta = 25 °CCO10 pF

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

E1

E2

W

G

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

320 December 12, 1997

UL6264A

th(D)

Read Cycle 1 (during Read Cycle: E1 = G = VIL, E2 = W = VIH)

Read Cycle 2 (during Read Cycle:W = VIH)

Write Cycle 1 (W-controlled)

ta(A)

Valid

tcR

Addresses Valid

tv(A)

AAAA

AAA

Ai

DQi

Ai

E1

E2

G

DQi

Output

tdis(E)

tcR

tsu(A)ta(E)

tsu(A)

tt(QX)

ttG(QX)

ta(G)

ta(E)tdis(E)

tdis(G)

Addresses Valid

Output Data

Valid

AAAA

AAA

Ai

E1

E2

W

DQi

Input

G

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A)

tsu(E)

tsu(D)

tdis(W)tt(QX)

Addresses Valid

Input Data

Valid

High-Z

AAAA

AA

AAAA

AAA

AAAA

AAA

321 December 12, 1997

UL6264A

High-Z

Input Data

Valid

th(D)

tsu(W)

tw(E)

tsu(D)

tcW

Addresses Valid

tsu(A)

tsu(E)th(A)

tt(QX) tdis(W)

AAAA

AA

AAAA

AAA

AAAA

Ai

E1

E2

W

DQi

Input

G

DQi

Output

tsu(A)

AAAA

A

AAA

A

AAA

A

AAA

AAAA

A

AAAA

A

AAA

A

AAA

A

AAA

AAAA

A

undefined L- or H-Level

Write Cycle 2 (E1-controlled)

Write Cycle 3 (E2-controlled)

th(D)

Ai

E1

E2

W

DQi

Input

G

DQi

Output

tcW

tw(E)th(A)

tsu(W)

tsu(E)

tsu(D)

tdis(W)

tt(QX)

Addresses Valid

Input Data

Valid

High-Z

AAAA

AAA

AAAA

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