TDI-CCD image sensors
Operating the back-thinned CCD in TDI mode
delivers high sensitivity.
S10201-04S10200-02 S10202-08 S10202-16
www.hamamatsu.com 1
Sequential imaging of high-speed moving samples
Semiconductor inspection
TDI mode gives high sensitivity
Inspection tasks on electronic parts production line
Flow cytometery
High-speed, continuous image acquisition
Back-thinned structure ensures high sensitivity from UV
to near IR
Multiple ports for high-speed line rate
TDI-CCD image sensers capture clear and bright images even under low-light-level conditions. During TDI (time delay in-
tegration) mode, the CCD captures an image of a moving object while transferring integrated signal charges synchronously
with the object movement. This operation mode dramatically boosts sensitivity to high levels even when capturing fast mov-
ing objects. Our new TDI-CCD uses the back-thinned structure to achieve even higher quantum ef ciency over a wide spec-
tral range from UV to near IR region (200 to 1100 nm).
Schematic diagram showing integrated
exposure by TDI mode
TDI mode
In FFT-CCD, signal charges in each line are vertically transferred during charge readout. TDI mode synchronizes this vertical
transfer timing with the movement of the object, so that signal charges are integrated a number of times equal to the number
of vertical stages of the CCD pixels.
In the TDI mode, the signal charges must be transferred in the same direction at the same speed as those of the object to be
imaged. These speeds are expressed by the following equation:
v = f × d
v : object moving speed, charge transfer speed
f : vertical transfer frequency
d : pixel size
In the right gure, when the rst stage charges are transferred
to the second stage, an additional charges are produced in the
second stage by photoelectric conversion and accumulated.
When this operation is continuously repeated until reaching
the last stage M (the number of vertical stages), signal charges
which are M times greater than the initial charges are accumu-
lated. Since the signal charges on each line are output from the
CCD horizontal shift register, a two-dimensional image can be
continuously acquired. In this way the TDI mode achieves sen-
sitivity which is M times higher than linear image sensors (S/N
is improved times). The TDI mode also improves sensitivity
variations compared to frame mode operation.
Time1 Time2 Time3
First stage
·
·
·
·
·
Last stage M
Charge transfer
·
Object movement
Charge
KMPDC0139EA
M
Features Applications
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
Selection guide
2
Type no.
Number of
total pixels
(H × V)
Number of
effective pixels
(H × V)
Number of
ports
Pixel rate
(MHz/port)
Line rate
(kHz)
Vertical
transfer
Applicable*1
camera
S10200-02 1040 × 128 1024 × 128 2
30 50 Bi-directional
-
S10201-04 2080 × 128 2048 × 128 4 C10000-201
S10202-08 4160 × 128 4096 × 128 8 -
S10202-16 4224 × 128 4096 × 128 16 100 C10000-701A/-701B
*1: The C10000 series cameras are products manufactured by Hamamatsu Photonics, System Division (refer to page 15).
Structure
Parameter Specification
Pixel size (H × V) 12 × 12 μm
TDI stage 128
Anti-blooming FW × 100 (min.)
Vertical clock 3 phases
Horizontal clock 2 phases
Output circuit Two-stage MOSFET source follower
Package Ceramic DIP (refer to dimensional outlines)
Window Quartz glass*2
*2: Resin sealing
Parameter Symbol Min. Typ. Max. Unit
Operating temperature*3Topr -50 - 60 °C
Storage temperature Tstg -50 - 70 °C
Output transistor drain voltage VOD -0.5 - 25 V
Reset drain voltage VRD -0.5 - 18 V
Overflow drain voltage VOFD -0.5 - 18 V
Overflow gate voltage VOFG -10 - 15 V
Summing gate voltage VSG -10 - 15 V
Output gate voltage VOG -10 - 15 V
Reset gate voltage VRG -10 - 15 V
Transfer gate voltage VTG -10 - 15 V
Vertical clock voltage VP1V, VP2V, VP3V -8 - +8 V
Horizontal clock voltage VP1H, VP2H -10 - 15 V
Note: Exceeding the absolute maximum ratings even momentarily may cause a drop in product quality. Always be sure to use the
product within the absolute maximum ratings.
*3: Chip temperature
Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 12 15 18 V
Reset drain voltage VRD 11 12 13 V
Output gate voltage VOG 357V
Substrate voltage VDGND, VAGND -0-V
Overflow drain voltage VOFD 8 9 11 V
Overflow gate voltage VOFG 567V
Vertical shift register clock voltage High VP1VH, VP2VH, VP3VH 468
V
Low VP1VL, VP2VL, VP3VL -6 -5 -4
Horizontal shift register clock voltage High VP1HH, VP2HH 468
V
Low VP1HL, VP2HL -6 -5 -4
Summing gate voltage High VSGH 468
V
Low VSHL -6 -5 -4
Reset gate voltage High VRGH 789
V
Low VRGL -6 0 -
Transfer gate voltage High VTGH 468
V
Low VTGL -6 -5 -4
External load resistance RL2.0 2.2 2.4 kΩ
Absolute maximum ratings (Ta=25 °C)
Operating conditions (TDI mode, Ta=25 °C)
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
Parameter Symbol Min. Typ. Max. Unit
Signal output frequency fc - 30 35 MHz
Vertical shift register
capacitance
S10200-02
CP1V, CP2V, CP3V
- 250 -
pFS10201-04 - 400 -
S10202-08/-16 - 650 -
Line rate
S10200-02
LR
-50-
kHz
S10201-04 - 50 -
S10202-08 - 50 -
S10202-16 - 100 -
Horizontal shift register
capacitance
S10200-02
CP1H, CP2H
-50-
pFS10201-04 - 90 -
S10202-08/-16 - 90 -
Transfer gate capacitance
S10200-02
CTG
-40-
pFS10201-04 - 60 -
S10202-08/-16 - 100 -
Summing gate capacitance
S10200-02
CSG
-20-
pFS10201-04 - 40 -
S10202-08/-16 - 40 -
Reset gate capacitance
S10200-02
CRG
-20-
pFS10201-04 - 40 -
S10202-08/-16 - 40 -
Charge transfer efficiency*4CTE 0.99995 0.99999 - -
DC output level*5Vout - 7.5 - V
Output impedance*6Zo - 300 - Ω
Output MOSFET supply current/node Ido - 5 10 mA
Power consumption*5 *6P - 75 - mW
*4: Charge transfer efficiency per pixel, measured at half of the full well capacity
*5: The values depend on the load resistance. (VOD=15 V, Load resistance=2.2 kΩ)
*6: Power consumption of the on-chip amplifier plus load resistance
Electrical characteristics (Ta=25 °C)
Parameter Symbol Min. Typ. Max. Unit
Saturation output voltage Vsat - FW × Sv - V
Full well capacity*7FW 80 100 120 ke-
CCD node sensitivity Sv 3 3.5 4 μV/e-
Dark current*7 *8DS - 100 300 e-/pixel
Readout noise*9Nr - 100 200 e- rms
Dynamic range DR 800 1000 - -
Photoresponse nonuniformity*10 PRNU - ±3 ±10 %
Spectral response range λ- 200 to 1100 - nm
*7: TDI mode
*8: Line rate 50 kHz, accumulated dark signal after 128-stage transfer
*9: Readout frequency 30 MHz
*10: Measured at half of the full well capacity, using LED light (peak emission wavelength: 660 nm), in TDI mode
Fixed pattern noise (peak to peak)
Signal × 100
[%]Photoresponse nonuniformity (PRNU) =
Electrical and optical characteristics (Ta=25 °C)
3
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
Spectral response (without window)*11
KMPDB0268EA KMPDB0269EA
Wavelength (nm)
Photosensitivity (V/µJ · cm2)
0
500
1000
1500
2000
2500
200 400 600 900800 1000300 500 700 1100
3000 (Typ. Ta=25 °C)
Wavelength (nm)
Quantum efficiency (%)
0
10
20
30
40
50
60
70
80
90
200 300 400 500 600 700 800 900 1000 1100 1200
100 (Typ. Ta=25 °C)
Back-thinned CCD
S10200-02
S10201-04
S10202-08
S10202-16
Front-illuminated CCD
*11: Spectral response with sapphire window is decreased according to the spectral transmittance characteristics of window material.
Spectral transmittance characteristics of window material
KMPDB0303EA
Wavelength (nm)
(Typ. Ta=25 °C)
Transmittance (%)
0
100
80
90
70
50
30
10
60
40
20
1200
100 300 400200 500 600 700 800 900
1000 1100
4
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
5
TGb
P3V
P2V
P1V
TGa
RG
RD
OD
AGND
OG
SG
P2H
P1H
OSa1
OSa2
OSb1
OSb2
OFD
OFG
DGND
B port side
512 pixels
A port side
Bidirectional transfer
128 pixels
Sensor structure
KAPDC0251EA
S10200-02
TGb
P3V
P2V
P1V
TGa
RG
RD
OD
AGND
OG
SG
P2H
P1H
OSa1
OSa2
OSb1
OSb2
OSa3 OSb3
OSa4 OSb4
OFD
OFG
DGND
B port side
512 pixels
A port side
Bidirectional transfer
128 pixels
KMPDC0260EA
S10201-04
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
TGb
P3V
P2V
P1V
TGa
RG
RD
OD
AGND
OG
SG
P2H
P1H
OSa1
OSa2
OSb1
OSb2
OSa3 OSb3
OSa4 OSb4
OFD
OFG
DGND
B port side
512 pixels
A port side
OSa5 OSb5
OSa8 OSb8
Bidirectional transfer
128 pixels
KMPDC0261EA
S10202-08
6
TGb
P3V
P2V
P1V
TGa
RG
RD
OD
AGND
OG
SG
P2H
P1H
OSa1
OSa2
OSb1
OSb2
OSa3 OSb3
OSa4 OSb4
OFD
OFG
DGND
B port side
256 pixels
A port side
OSa5 OSb5
OSa16 OSb16
OSa6 OSb6
OSa7 OSb7
OSa8 OSb8
OSa9 OSb9
OSa15 OSb15
Bidirectional
transfer
128 pixels
KMPDC0262EA
S10202-16
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
OSb6
OSb7
OSb8
OSa6
OSa7
OSa8
Thinning
V=128
H=512 × 8 (number of ports)
Thinning
OSa1
OSa2
OSa3
OSb1
OSb2
OSb3
8 blank pixels
512 pixels
128 TDI stages
KMPDC0252EA
Device structure (typical example: S10202-08, conceptual drawing of top view)
7
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
KMPDC0253ED
OSb
RGb H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
P2Hb, SGb
P1Hb
TGb
P1V
P2V
P3V
TGa
P1Ha
P2Ha, SGa
RGa
OSa
S510
S254
S511
S255
D1
Tprr, Tpwr, Tpfr
D2 D3..D8, S1..S509
D3..D8, S1..S253
S512 : S10200-02, S10201-04, S10202-08
S256 : S10202-16
Tprs, Tpws, Tpfs
Tprh, Tpwh, TpfhTovr
518
262
519
263
520
264
S10200-02, S10201-04, S10202-08:
S10202-16: 1 2 3
4..517
4..261
TovrvTprv, Tpwv, Tpfv
Tovrv
Tovrv
KMPDC0253ED
Timing chart
B port side readout
8
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
OSb
RGb
P2Hb, SGb
P1Hb
TGb
P1V
P2V
P3V
TGa
P1Ha
P2Ha, SGa
RGa
OSa
S510
S254
S511
S255
D1 D2 D3..D8, S1..S509
D3..D8, S1..S253
S512 : S10200-02, S10201-04, S10202-08
S256 : S10202-16
518
262
519
263
520 : S10200-02, S10201-04, S10202-08
264 : S10202-16
4..517
4..261
123
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
KMPDC0254ED
Parameter Symbol Min. Typ. Max. Unit
P1V, 2V, 3V, TG
Pulse width Tpwv 120 770 - ns
Rise and fall times Tprv, Tpfv 2 10 - ns
Overlap time Tovrv 30 300 - ns
P1H, P2H
Pulse width*12 Tpwh 14.5 16.5 - ns
Rise and fall times*12 Tprh, Tpfh 3 6 - ns
Duty ratio*12 --50-%
SG
Pulse width Tpws 14.5 16.5 - ns
Rise and fall times Tprs, Tpfs 2 4 - ns
Duty ratio - - 50 - %
RG Pulse width Tpwr 5 6 - ns
Rise and fall times Tprr, Tpfr 1 2 - ns
TG - P1H Overlap time Tovr 30 1000 - ns
*12: Symmetrical clock pulses should be overlapped at 50% of maximum pulse amplitude.
A port side readout
9
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
10
* Distance from upper surface of window to photosensitive surface
Photosensitive area 12.288
23.84 ± 0.1
0.457 ± 0.05 1.27 ± 0.1
27.94 ± 0.33
30.48 ± 0.35
40 21
1
Index mark 20
10.16 ± 0.25
3 ± 0.1
9.91 ± 0.25
2.5 ± 0.1
Photosensitive area 1.536
3.44 ± 0.35
1.48 ± 0.15 *
0.25+0.05
-0.03
2.84 ± 0.3
C0.5
9.66 ± 0.1
KMPDA0218EC
S10200-02
* Distance from upper surface of window to photosensitive surface
Photosensitive area 24.576
33 ± 0.1
0.457 ± 0.05 1.27 ± 0.1
38.1 ± 0.43
40.64 ± 0.45
40 21
1
Index mark
20
10.16 ± 0.25
3 ± 0.1
9.66 ± 0.1
9.91 ± 0.25
2.5 ± 0.1
Photosensitive area 1.536
3.44 ± 0.35
1.48 ± 0.15 *
0.25+0.05
-0.03
2.84 ± 0.3
C0.5
KMPDA0219EC
S10201-04
Dimensional outlines (unit: mm)
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
11
* Distance from upper surface of window to photosensitive surface
Photosensitive area 49.152
100 51
50
55 ± 0.1
63.5 ± 0.64
66.04 ± 0.66
9.91 ± 0.25
6.5 ± 0.1
2.5 ± 0.25
Photosensitive area 1.536
1
Index mark
3 ± 0.3
0.42 ± 0.251.27 ± 0.13
0.8 ± 0.05
2.42 ± 0.2 *
2.4 ± 0.24
3.8 ± 0.38
0.25+0.05
-0.03
10.16
±
0.25
C0.5
KMPDA0220EC
S10202-08/-16
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
12
S10200-02 S10201-04
Pin no.
Symbol Function Remark
Pin no.
Symbol Function Remark
1 P2V CCD vertical register clock-2 1 P2V CCD vertical register clock-2
2 P3V CCD vertical register clock-3 2 P3V CCD vertical register clock-3
3 P1V CCD vertical register clock-1 3 P1V CCD vertical register clock-1
4 TGa Transfer gate-a 4 TGa Transfer gate-a
5 SSD Digital GND GND 5 SSD Digital GND GND
6 NC No connection 6 OSa1 Output transistor source-a1 RL=2.2 kΩ
7 SSA Analog GND GND 7 SSA Analog GND GND
8 OSa1 Output transistor source-a 1 RL=2.2 kΩ8 OSa2 Output transistor source-a2 RL=2.2 kΩ
9 OD1 Output drain-1 +15 V 9 OD1 Output drain-1 +15 V
10 OSa2 Output transistor source-a 2 RL=2.2 kΩ10 OSa3 Output transistor source-a3 RL=2.2 kΩ
11 NC No connection 11 OD3 Output drain-3 +15 V
12 NC No connection 12 OSa4 Output transistor source-a4 RL=2.2 kΩ
13 OG Output gate +5 V 13 OG Output gate +5 V
14 RD Reset drain +12 V 14 RD Reset drain +12 V
15 OFD Overflow drain +9 V 15 OFD Overflow drain +9 V
16 SSD Digital GND GND 16 SSD Digital GND GND
17 RGa Reset gate-a 17 RGa Reset gate-a
18 SGa Summing gate-a 18 SGa Summing gate-a
19 P1Ha CCD horizontal register-a clock-1 19 P1Ha CCD horizontal register-a clock-1
20 P2Ha CCD horizontal register-a clock-2 20 P2Ha CCD horizontal register-a clock-2
21 P2Hb CCD horizontal register-b clock-2 21 P2Hb CCD horizontal register-b clock-2
22 P1Hb CCD horizontal register-b clock-1 22 P1Hb CCD horizontal register-b clock-1
23 SGb Summing gate-b 23 SGb Summing gate-b
24 RGb Reset gate-b 24 RGb Reset gate-b
25 SSD Digital GND GND 25 SSD Digital GND GND
26 OFG Overflow gate +6 V 26 OFG Overflow gate +6 V
27 RD Reset drain +12 V 27 RD Reset drain +12 V
28 OG Output gate +5 V 28 OG Output gate +5 V
29 NC No connection 29 OSb4 Output transistor source-b4 RL=2.2 kΩ
30 NC No connection 30 OD4 Output drain-4 +15 V
31 OSb2 Output transistor source-b2 RL=2.2 kΩ31 OSb3 Output transistor source-b3 RL=2.2 kΩ
32 OD2 Output drain-2 +15 V 32 OD2 Output drain-2 +15 V
33 OSb1 Output transistor source-b1 RL=2.2 kΩ33 OSb2 Output transistor source-b2 RL=2.2 kΩ
34 SSA Analog GND GND 34 SSA Analog GND GND
35 NC No connection 35 OSb1 Output transistor source-b1 RL=2.2 kΩ
36 SSD Digital GND GND 36 SSD Digital GND GND
37 TGb Transfer gate-b 37 TGb Transfer gate-b
38 P1V CCD vertical register clock-1 38 P1V CCD vertical register clock-1
39 P3V CCD vertical register clock-3 39 P3V CCD vertical register clock-3
40 P2V CCD vertical register clock-2 40 P2V CCD vertical register clock-2
Pin connections
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
S10202-08
Pin no.
Symbol Function Remark
Pin no.
Symbol Function Remark
1 P1Ha1 CCD horizontal register-a1 clock-1 51 P1Hb2 CCD horizontal register-b2 clock-1
2 P2Ha1 CCD horizontal register-a1 clock-2 52 P2Hb2 CCD horizontal register-b2 clock-2
3 SGa1 Summing gate-a1 53 SGb2 Summing gate-b2
4 RGa1 Reset gate-a1 54 RGb2 Reset gate-b2
5 SSD Digital GND GND 55 SSD Digital GND GND
6 SSA Analog GND GND 56 SSA Analog GND GND
7 OFG Overflow gate +6 V 57 OFG Overflow gate +6 V
8 OSa1 Output transistor source-a1 RL=2.2 kΩ58 NC No connection
9 OFD Overflow drain +9 V 59 OFD Overflow drain +9 V
10 NC No connection 60 OSb8 Output transistor source-b8 RL=2.2 kΩ
11 RD Reset drain +12 V 61 RD Reset drain +12 V
12 OSa2 Output transistor source-a2 RL=2.2 kΩ62 NC No connection
13 OG Output gate +5 V 63 OG Output gate +5 V
14 NC No connection 64 OSb7 Output transistor source-b7 RL=2.2 kΩ
15 OD1 Output drain-1 +15 V 65 NC No connection
16 OSa3 Output transistor source-a3 RL=2.2 kΩ66 NC No connection
17 NC No connection 67 OD8 Output drain-8 +15 V
18 NC No connection 68 OSb6 Output transistor source-b6 RL=2.2 kΩ
19 OD3 Output drain-3 +15 V 69 NC No connection
20 OSa4 Output transistor source-a4 RL=2.2 kΩ70 NC No connection
21 NC No connection 71 OD6 Output drain-6 +15 V
22 NC No connection 72 OSb5 Output transistor source-b5 RL=2.2 kΩ
23 SSD Digital GND GND 73 SSD Digital GND GND
24 TGa Transfer gate-a 74 P1V CCD vertical register clock-1
25 P2V CCD vertical register clock-2 75 P3V CCD vertical register clock-3
26 P3V CCD vertical register clock-3 76 P2V CCD vertical register clock-2
27 P1V CCD vertical register clock-1 77 TGb Transfer gate-b
28 SSD Digital GND GND 78 SSD Digital GND GND
29 OSa5 Output transistor source-a5 RL=2.2 kΩ79 NC No connection
30 OD5 Output drain-5 +15 V 80 NC No connection
31 NC No connection 81 OSb4 Output transistor source-b4 RL=2.2 kΩ
32 NC No connection 82 OD4 Output drain-4 +15 V
33 OSa6 Output transistor source-a6 RL=2.2 kΩ83 NC No connection
34 OD7 Output drain-7 +15 V 84 NC No connection
35 NC No connection 85 OSb3 Output transistor source-b3 RL=2.2 kΩ
36 NC No connection 86 OD2 Output drain-2 +15 V
37 OSa7 Output transistor source-a7 RL=2.2 kΩ87 NC No connection
38 OG Output gate +5 V 88 OG Output gate +5 V
39 NC No connection 89 OSb2 Output transistor source-b2 RL=2.2 kΩ
40 RD Reset drain +12 V 90 RD Reset drain +12 V
41 OSa8 Output transistor source-a8 RL=2.2 kΩ91 NC No connection
42 OFD Overflow drain +9 V 92 OFD Overflow drain +9 V
43 NC No connection 93 OSb1 Output transistor source-b1 RL=2.2 kΩ
44 OFG Overflow gate +6 V 94 OFG Overflow gate +6 V
45 SSA Analog GND GND 95 SSA Analog GND GND
46 SSD Digital GND GND 96 SSD Digital GND GND
47 RGa2 Reset gate-a2 97 RGb1 Reset gate-b1
48 SGa2 Summing gate-a2 98 SGb1 Summing gate-b1
49 P2Ha2 CCD horizontal register-a2 clock-2 99 P2Hb1 CCD horizontal register-b1 clock-2
50 P1Ha2 CCD horizontal register-a2 clock-1 100 P1Hb1 CCD horizontal register-b1 clock-1
13
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
14
S10202-16
Pin no.
Symbol Function Remark
Pin no.
Symbol Function Remark
1 P1Ha1 CCD horizontal register-a1 clock-1 51 P1Hb2 CCD horizontal register-b2 clock-1
2 P2Ha1 CCD horizontal register-a1 clock-2 52 P2Hb2 CCD horizontal register-b2 clock-2
3 SGa1 Summing gate-a1 53 SGb2 Summing gate-b2
4 RGa1 Reset gate-a1 54 RGb2 Reset gate-b2
5 SSD Digital GND GND 55 SSD Digital GND GND
6 SSA Analog GND GND 56 SSA Analog GND GND
7 OFG Overflow gate +6 V 57 OFG Overflow gate +6 V
8 OSa1 Output transistor source-a1 RL=2.2 kΩ58 OSb16 Output transistor source-b16 RL=2.2 kΩ
9 OFD Overflow drain +9 V 59 OFD Overflow drain +9 V
10 OSa2 Output transistor source-a2 RL=2.2 kΩ60 OSb15 Output transistor source-b15 RL=2.2 kΩ
11 RD Reset drain +12 V 61 RD Reset drain +12 V
12 OSa3 Output transistor source-a3 RL=2.2 kΩ62 OSb14 Output transistor source-b14 RL=2.2 kΩ
13 OG Output gate +5 V 63 OG Output gate +5 V
14 OSa4 Output transistor source-a4 RL=2.2 kΩ64 OSb13 Output transistor source-b13 RL=2.2 kΩ
15 OD1 Output drain-1 +15 V 65 OD16 Output drain-16 +15 V
16 OSa5 Output transistor source-a5 RL=2.2 kΩ66 OSb12 Output transistor source-b12 RL=2.2 kΩ
17 OD2 Output drain-2 +15 V 67 OD15 Output drain-15 +15 V
18 OSa6 Output transistor source-a6 RL=2.2 kΩ68 OSb11 Output transistor source-b11 RL=2.2 kΩ
19 OD5 Output drain-5 +15 V 69 OD12 Output drain-12 +15 V
20 OSa7 Output transistor source-a7 RL=2.2 kΩ70 OSb10 Output transistor source-b10 RL=2.2 kΩ
21 OD6 Output drain-6 +15 V 71 OD11 Output drain-11 +15 V
22 OSa8 Output transistor source-a8 RL=2.2 kΩ72 OSb9 Output transistor source-b9 RL=2.2 kΩ
23 SSD Digital GND GND 73 SSD Digital GND GND
24 TGa Transfer gate-a 74 P1V CCD vertical register clock-1
25 P2V CCD vertical register clock-2 75 P3V CCD vertical register clock-3
26 P3V CCD vertical register clock-3 76 P2V CCD vertical register clock-2
27 P1V CCD vertical register clock-1 77 TGb Transfer gate-b
28 SSD Digital GND GND 78 SSD Digital GND GND
29 OSa9 Output transistor source-a9 RL=2.2 kΩ79 OSb8 Output transistor source-b8 RL=2.2 kΩ
30 OD9 Output drain-9 +15 V 80 OD8 Output drain-8 +15 V
31 OSa10 Output transistor source-a10 RL=2.2 kΩ81 OSb7 Output transistor source-b7 RL=2.2 kΩ
32 OD10 Output drain-10 +15 V 82 OD7 Output drain-7 +15 V
33 OSa11 Output transistor source-a11 RL=2.2 kΩ83 OSb6 Output transistor source-b6 RL=2.2 kΩ
34 OD13 Output drain-13 +15 V 84 OD4 Output drain-4 +15 V
35 OSa12 Output transistor source-a12 RL=2.2 kΩ85 OSb5 Output transistor source-b5 RL=2.2 kΩ
36 OD14 Output drain-14 +15 V 86 OD3 Output drain-3 +15 V
37 OSa13 Output transistor source-a13 RL=2.2 kΩ87 OSb4 Output transistor source-b4 RL=2.2 kΩ
38 OG Output gate +5 V 88 OG Output gate +5 V
39 OSa14 Output transistor source-a14 RL=2.2 kΩ89 OSb3 Output transistor source-b3 RL=2.2 kΩ
40 RD Reset drain +12 V 90 RD Reset drain +12 V
41 OSa15 Output transistor source-a15 RL=2.2 kΩ91 OSb2 Output transistor source-b2 RL=2.2 kΩ
42 OFD Overflow drain +9 V 92 OFD Overflow drain +9 V
43 OSa16 Output transistor source-a16 RL=2.2 kΩ93 OSb1 Output transistor source-b1 RL=2.2 kΩ
44 OFG Overflow gate +6 V 94 OFG Overflow gate +6 V
45 SSA Analog GND GND 95 SSA Analog GND GND
46 SSD Digital GND GND 96 SSD Digital GND GND
47 RGa2 Reset gate-a2 97 RGb1 Reset gate-b1
48 SGa2 Summing gate-a2 98 SGb1 Summing gate-b1
49 P2Ha2 CCD horizontal register-a2 clock-2 99 P2Hb1 CCD horizontal register-b1 clock-2
50 P1Ha2 CCD horizontal register-a2 clock-1 100 P1Hb1 CCD horizontal register-b1 clock-1
Cat. No. KMPD1098E06 Sept. 2012 DN
www.hamamatsu.com
HAMAMATSU PHOTONICS K.K., Solid State Division
1126-1 Ichino-cho, Higashi-ku, Hamamatsu City, 435-8558 Japan, Telephone: (81) 53-434-3311, Fax: (81) 53-434-5184
U.S.A.: Hamamatsu Corporation: 360 Foothill Road, P.O.Box 6910, Bridgewater, N.J. 08807-0910, U.S.A., Telephone: (1) 908-231-0960, Fax: (1) 908-231-1218
Germany: Hamamatsu Photonics Deutschland GmbH: Arzbergerstr. 10, D-82211 Herrsching am Ammersee, Germany, Telephone: (49) 8152-375-0, Fax: (49) 8152-265-8
France: Hamamatsu Photonics France S.A.R.L.: 19, Rue du Saule Trapu, Parc du Moulin de Massy, 91882 Massy Cedex, France, Telephone: 33-(1) 69 53 71 00, Fax: 33-(1) 69 53 71 10
United Kingdom: Hamamatsu Photonics UK Limited: 2 Howard Court, 10 Tewin Road, Welwyn Garden City, Hertfordshire AL7 1BW, United Kingdom, Telephone: (44) 1707-294888, Fax: (44) 1707-325777
North Europe: Hamamatsu Photonics Norden AB: Thorshamnsgatan 35 16440 Kista, Sweden, Telephone: (46) 8-509-031-00, Fax: (46) 8-509-031-01
Italy: Hamamatsu Photonics Italia S.R.L.: Strada della Moia, 1 int. 6, 20020 Arese, (Milano), Italy, Telephone: (39) 02-935-81-733, Fax: (39) 02-935-81-741
China: Hamamatsu Photonics (China) Co., Ltd.: 1201 Tower B, Jiaming Center, No.27 Dongsanhuan Beilu, Chaoyang District, Beijing 100020, China, Telephone: (86) 10-6586-6006, Fax: (86) 10-6586-2866
Product specifications are subject to change without prior notice due to improvements or other reasons. Before assembly into final products, please contact
us for the delivery specification sheet to check the latest information.
T
ype numbers of products listed in the delivery specification sheets or supplied as samples may have a suffix "(X)" which means preliminary specifications or
a suffix "(Z)" which means developmental specifications.
T
he product warranty is valid for one year after delivery and is limited to product repair or replacement for defects discovered and reported to us within that
one year period. However, even if within the warranty period we accept absolutely no liability for any loss caused by natural disasters or improper product
use.
Copying or reprinting the contents described in this material in whole or in part is prohibited without our prior permission.
Information described in this material is current as of September, 2012.
TDI-CCD image sensors
S10200-02, S10201-04, S10202-08, S10202-16
Handle these sensors with bare hands or wearing cotton gloves. In addition, wear anti-static clothing or use a wrist band with an earth
ring, in order to prevent electrostatic damage due to electrical charges from friction.
Avoid directly placing these sensors on a work-desk, etc. that may carry an electrostatic charge.
Provide ground lines or ground connection with the work- oor, work-desk and work-bench to allow static electricity to discharge.
Ground the tools used to handle these sensors, such as tweezers and soldering irons.
It is not always necessary to provide all the electrostatic measures stated above. Implement these measures according to the amount of
damage that occurs.
Precautions (Electrostatic countermeasures)
15
The TDI camera C10000 series is useful in a wide range of imaging
applications that require both high speed and high sensitivity,
including in-line monitoring and inspection.
C10000-201 (Board type) C10000-701A/-701B
TDI camera C10000 series
Product information
http://jp.hamamatsu.com/products/camera/5007/index_en.html