TECHNICAL NOTE General-purpose CMOS Logic IC Series (BU4000B Series) High Voltage CMOS Logic ICs <Function Logic> BU4015B/F, BU4021B/F, BU4094BC/F/FV, BU4538B, BU4028B Description BU4015B series ICs are 4-stage static shift registers, each consisting of 2 circuits. The D flip-flops of each stage share a common reset input, enabling asynchronous reset at any time. BU4021B series ICs are 8-bit static shift registers configured with 8 register cells, each of which has parallel input. Control of the parallel/serial input (P/S) enables serial input/output with clock synchronization and well as parallel input/serial output conversions. BU4094BC series ICs are shift/store registers, each consisting of an 8-bit shift register and an 8-bit latch. Output can be held in the data transfer mode because the data read into the shift register can be latched by the asynchronous strobe input, The BU4538B IC is a monostable multivibrator that can be reset and retriggered from either edge of an input pulse. A wide range of accurate output pulse widths is available because the output pulse width and accuracy are determined by the external timing constants Cx an Rx. The BU4028B IC is a decoder which converts BCD signals into decimal signals. Of the 10 outputs (Q0 ~ Q9), those corresponding to the input codes A-D are set to "H", while the others are set to "L". Features 1) Low power consumption 2) Wide operating supply voltage range 3) High impedance 4) High fan out 5) L-TTL2 and LS-TTL1 inputs can be driven directly. Applications BU4015B: serial / parallel data conversion and ring counter. BU4021B: control circuits, timing circuits and as a general purpose register requiring high degree of noise tolerance. BU4094BC: series/parallel data conversion and data receivers. BU4538B: can obtain the output pulse amplitude with improved accuracy by external capacity and resistance. BU4028B: code conversion, address decoding, memory selection control, demultiplexing or readout and decoding, etc. Lineup High Voltage CMOS Logic<Function Logic> 2 4-bit register circuits BU4015B/F (Dual 4-bit static shift register) 1 circuit 8-bit register BU4021B/F (8-bit static shift register) 2 circuits 8-bit register BU4094BC/F/FV (8-bit bus compatible shift/store register) 1 circuit Monostable multivibrator BU4538B (Dual high accuracy monostable multivibrator) 1 circuit BCD Decimal BU4028B (BCD to Decimal decoder) Apr.2008 Absolute Maximum Ratings Parameter Symbol Power Supply Voltage Supply Current Operating Temperature Storage Temperature Input Voltage Maximum Junction Temperature VDD Iin Topr Tstg VIN Limit BU4094BC -0.3 to 18 10 -40 to 85 -55 to 150 -0.3 to VDD+0.3 Tjmax 150 BU4015B BU4021B BU4538B BU4028B Unit V mA V Recommended Operating Conditions Parameter Symbol Operating Power Supply Input Voltage VDD VIN BU4015B BU4021B 3 to 16 Limit BU4094BC BU4538B (3 to 18V @BU4094BC) 0 to VDD BU4028B Unit V V Thermal Derating Curve Power dissipation Pd [mW] 1400 1250[mV] BU4 620[mV] BU4FV 380[mV] BU4F 1200 1000 (*1) (*2) (*3) ()Below shows BU4 BU4015B BU4021B BU4094BC BU4538B BU4028B 800 600 400 200 0 85 25 50 75 1 2 100 Ambient temperature 125 Ta 150 175 [] 10.0 5.0 3 Unit 3.1 mW/ When used at Ta=25 or higher the value above is reduced per 1. by using the sample mounted on a 70mmx70mmx1.6mm FR4 glass-epoxy PCB (cupper area is less than 3%) Input / Output Equivalent Circuits VDD VDD VDD VDD GND GND GND GND Input Output 2/16 Power Dissipation is measured Electrical CharacteristicsBU4015B DC Characteristics (Unless otherwise noted VSS=0[V],Ta=25[]) Limits Parameter Symbol Min Typ Max 3.5 Input `H' voltage VIH 7.0 11.0 1.5 Input `L' voltage VIL 3.0 4.0 Input `H' current IIH 0.3 Input `L' current IIL -0.3 4.95 Output `H' voltage VOH 9.95 14.95 0.05 Output `L' voltage VOL 0.05 0.05 -0.16 Output `H' current IOH -0.4 -1.2 0.44 Output `L' current IOL 1.1 3.0 20 Static supply current IDD 40 80 Unit V V A A V V mA mA A VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15 Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 180 5 Output rising time tTLH 90 ns 10 65 15 100 5 Output falling time TTHL 50 ns 10 40 15 310 5 Propagation delay time tPLH 125 10 ns CLOCK, DQ tPHL 90 15 460 5 Propagation delay time tPLH 180 10 ns RESETQ tPHL 120 15 100 5 Set up time Tsu 50 ns 10 40 15 185 5 Minimum clock pulse 85 10 tW(CLK) ns width 55 15 200 5 Minimum reset pulse 80 10 tW(RST) ns width 60 15 20 5 Maximum clock f (CLK) 6.0 10 MHz frequency Max. 7.5 15 100 5 Maximum clock tr(CLK) 40 10 s rising/falling time tf(CLK) 15 15 Input capacitance CIN 5 pF 3/16 Condition Fig. No VIH=15[V] VIL=0[V] IO=0[mA] 1 IO=0[mA] 2 VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VSS or GND 1 2 Condition Fig. No 34 56 78 9 10 Electrical CharacteristicsBU4021B DC Characteristics (Unless otherwise noted Parameter Symbol Input `H' voltage VIH Input `L' voltage VIL Input `H' current Input `L' current IIH IIL Output `H' voltage VOH Output `L' voltage VOL Output `H' current IOH Output `L' current IOL Static supply current IDD VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 20 40 80 Unit V V A A V V mA mA A VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15 Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Limits Parameter Symbol Unit Min Typ Max VDD[V] 180 5 Output rising time tTLH 90 ns 10 65 15 100 5 Output falling time tTHL 50 ns 10 40 15 400 5 "L" to "H" 170 10 Propagation delay time tPLH ns CLOCKQ P/SQ 115 15 400 5 "H" to "L" 170 10 Propagation delay time tPHL ns CLOCKQ P/SQ 115 15 150 5 Set up time tsu 50 ns 10 30 15 150 5 Minimum clock pulse 75 10 tW(CLK) ns width 40 15 3.0 5 Maximum clock f (CLK) 6.0 10 MHz frequency Max. 8.0 15 15 5 Maximum clock tr(CLK) 5.0 10 s rising/falling time tf(CLK) 4.0 15 150 5 Minimum P/S 75 10 tw(P/S) ns Control pulse width 40 15 Input capacitance CIN 5 pF 4/16 Condition Fig. No VIH=15[V] VIL=0[V] IO=0[mA] 11 IO=0[mA] 12 VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND 11 12 Condition Fig. No 1315 1416 17 19 20 Electrical CharacteristicsBU4094BC DC Characteristics (Unless otherwise noted VSS=0[V],Ta=25[]) Parameter Symbol Input `H' voltage VIH Input `L' voltage VIL Input `H' current Input `L' current IIH IIL Output `H' voltage VOH Output `L' voltage VOL Output `H' current IOH Output `L' current IOL Static supply current IDD Min 3.5 7.0 11.0 4.95 9.95 14.95 -0.44 -1.1 -3.0 0.44 1.1 3.0 Limits Typ Max 1.5 3.0 4.0 0.3 -0.3 0.05 0.05 0.05 5 10 20 Unit V V A A V V mA mA A VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15 Condition Fig. No VIH=15[V] VIL=0[V] IO=0[mA] 21 IO=0[mA] 22 VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND 21 22 Switching Characteristics (Unless otherwise noted VSS=0[V],Ta=25[],CL=50[pF]) Parameter Symbol Output rising time tTLH Output falling time tTHL Propagation delay time tPLH tPHL CLOCKQS Propagation delay time CLOCKQ'S Propagation delay time CLOCKQN Propagation delay time STROBEQN 3state Propagation delay time Output EnableQN 3 state Propagation delay time Output EnableQN Minimum set up time DATACLOCK Minimum hold time CLOCK DATA Minimum clock pulse width Maximum clock rising/falling time tPLH tPHL tPLH tPHL tPLH tPHL tPHZ tPZH tPLZ tPZL tsu tH tW(CLK) Min Limits Typ 100 50 40 100 50 40 350 125 95 230 110 75 420 195 135 290 145 100 140 75 55 140 75 55 20 8 6 10 Max 200 100 80 200 100 80 600 250 190 460 220 150 840 390 270 580 290 200 280 150 110 280 150 110 125 55 35 40 10 20 5 100 50 40 15 200 100 80 tr(CL) tf(CL) Maximum clock frequency f CL Minimum strobe pulse width TwH Input capacitance CIN 2.5 5 12.5 100 40 35 5 ns ns ns ns ns ns ns ns ns ns ns s NO Limit 1.25 2.5 3.0 Unit 200 80 70 5/16 MHz ns pF VDD[V] 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Condition Fig. No 23 24 25 26 RL=1[k] 27 RL=1[k] 28 29 30 31 Electrical CharacteristicsBU4538B DC Characteristics (Unless otherwise noted Parameter Symbol Input `H' voltage VIH Input `L' voltage VIL Input `H' current Input `L' current IIH IIL Output `H' voltage VOH Output `L' voltage VOL Output `H' current IOH Output `L' current IOL Static supply current IDD VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 20 40 80 Switching Characteristics (Unless otherwise noted Parameter Symbol Output rising time tTLH Output falling time tTHL Propagation delay time A,BQ,Q tPLH tPHL Propagation delay time CDQ,Q tPLH tPHL Minimum input pulse width tWIN Output pulse width 1 tWOUT1 Output pulse width 2 tWOUT2 Minimum trigger time trr Input capacitance CIN Min 185 185 185 8.8 8.8 8.8 Unit V V A A V V mA mA A VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15 VSS=0[V],Ta=25[],CL=50[pF]) Limits Unit Typ Max VDD[V] 100 5 50 ns 10 40 15 100 5 50 ns 10 40 15 300 5 150 10 ns 100 15 250 5 125 10 ns 95 15 50 5 30 10 ns 25 15 200 215 5 200 215 s 10 200 215 15 9.4 10.0 5 9.4 10.0 ms 10 9.4 10.0 15 0 5 0 ns 10 0 15 5 pF 6/16 Condition Fig. No VIH=15[V] VIL=0[V] IO=0[mA] IO=0[mA] VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND Condition Fig. No 3233 3435 36 CX=2000[pF] RX=100[k] CX=0.1[uF] RX=100[k] 38 39 Electrical CharacteristicsBU4028B DC Characteristics (Unless otherwise noted Parameter Symbol Input `H' voltage VIH Input `L' voltage VIL Input `H' current Input `L' current IIH IIL Output `H' voltage VOH Output `L' voltage VOL Output `H' current IOH Output `L' current IOL Static supply current IDD VSS=0[V],Ta=25[]) Limits Min Typ Max 3.5 7.0 11.0 1.5 3.0 4.0 0.3 -0.3 4.95 9.95 14.95 0.05 0.05 0.05 -0.16 -0.4 -1.2 0.44 1.1 3.0 1 2 4 Switching Characteristics (Unless otherwise noted Parameter Symbol Output rising time tTLH Output falling time tTHL "L" to "H" Propagation delay time tPLH "H" to "L" Propagation delay time tPHL Input capacitance CIN Min Unit V V A A V V mA mA A VDD[V] 5 10 15 5 10 15 15 15 5 10 15 5 10 15 5 5 15 5 10 15 5 10 15 VSS=0[V],Ta=25[],CL=50[pF]) Limits Unit Typ Max VDD[V] 180 5 90 ns 10 65 15 100 5 50 ns 10 40 15 300 5 130 10 ns 90 15 300 5 130 10 ns 90 15 5 pF 7/16 Condition Fig. No VIH=15[V] VIL=0[V] IO=0[mA] 40 IO=0[mA] 41 VOH=4.6[V] VOH=9.5[V] VOH=13.5[V] VOL=0.4[V] VOL=0.5[V] VOL=1.5[V] VI=VDD or GND 40 41 Condition Fig. No 42 43 44 45 Electrical Characteristics CurvesBU4015B 600 50 50 40 VDD=15[V] -40[] 25[] 85[] VDD=10[V] -40[] 25[] 85[] -40[] 20 10 25[] 40 VDD=15[V] -40[] 30 25[] 85[] 20 -40[] 25[] VDD=10[V] 85[] 10 -40[] 25[] VDD=5[V] 85[] 85[] VDD=5[V] 0 0 0 5 10 15 0 20 5 Propagation Delay Time (RESETQ) [ns] [BU4015B/F] VDD=3[V] 400 Operating Temperature Range VDD=5[V] 200 VDD=10[V] 100 VDD=16[V] 0 -25 0 25 10 15 50 75 600 Operating Temperature Range VDD=5[V] 200 VDD=10[V] 100 VDD=16[V] 0 -50 -25 0 25 50 75 Hold Time (CLKQ) [ns] Setup Time (QCLK) [ns] VDD=5[V] 50 VDD=10[V] 500 VDD=5[V] 300 200 80 60 0 25 50 75 -25 100 25 50 75 [BU4015B/F] 20 VDD=16[V] -50 -25 0 25 50 75 Ambient Temperature [] Fig.7Set up time tsu QCLK Fig.8 Hold time th CLKQ Operating Temperature Range 400 VDD=3[V] 300 200 VDD=5[V] 100 VDD=10[V] VDD=16[V] 0 -50 100 -25 0 25 50 75 Fig.9 Minimum CLK pulse width Switching characteristics 20[ns] 150 VDD=3[V] 20[ns] 100 50% tsu 75 VDD=5[V] VDD=10[V] tPLH 0 -25 0 25 50 75 100 Q0(Output () Q0 data) Ambient Temperature [] 50% 10% tTLH Fig.10Minimum RESET pulse width 8/16 th GND(VSS) VDD tWH 25 VDD=16[V] 20[ns] 20[ns] 90% 50% 10% CLOCK 50 -50 VDD 90% D (Input data) 10% 100 Ambient Temperature [] Operating Temperature Range 125 100 Fig.6 Propagation delay tPHL RESETQ VDD=5[V] 40 Ambient Temperature [] [BU4015B/F] 0 Ambient Temperature [] VDD=10[V] 200 175 VDD=16[V] 0 -50 VDD=3[V] 0 -25 VDD=10[V] 100 100 Operating Temperature Range VDD=16[V] -50 Operating Temperature Range 400 500 25 0 100 VDD=3[V] 600 [BU4015B/F] Operating Temperature Range 75 75 [BU4015B/F] 100 100 50 700 Fig.5 Propagation delay tPLH RESETQ [BU4015B/F] VDD=3[V] 25 800 Ambient Temperature [] 150 0 Fig.3 Propagation delay tPLH CLKQ 400 300 -25 Ambient Temperature [] VDD=3[V] 100 200 Minimum Reset Pulse Width [ns] VDD=16[V] -50 500 Fig.4 Propagation delay tPHL CLKQ 125 VDD=10[V] 100 20 [BU4015B/F] Ambient Temperature [] 175 VDD=5[V] 200 Minimum Clock Pulse Width [ns] Propagation Delay Time (CLKQ) [ns] 600 -50 Operating Temperature Range 300 Fig.2 Output sink currentvoltage Fig.1 Output source currentvoltage 300 VDD=3[V] 400 Output Voltage [V] Output Voltage [V] 500 [BU4015B/F] 500 0 Propagation Delay Time (RESETQ) [ns] 30 Propagation Delay Time (CLKQ) [ns] [BU4015B/F] Output Sink Current [mA] Output Source Current [mA] [BU4015B/F] GND(VSS) tWL tPHL 90% VOH VOL tTHL Electrical Characteristics CurvesBU4021B 50 40 VDD=15[V] -40[] 25[] 85[] 20 VDD=10[V] -40[] 25[] 85[] 10 -40[] 25[] 85[] VDD=5[V] 0 0 5 40 VDD=15[V] -40[] 30 25[] 85[] 20 -40[] 25[] VDD=10[V] 85[] 10 -40[] 25[] VDD=5[V] 85[] 0 10 15 20 0 5 Output Voltage [V] VDD=3[V] Operating Temperature Range 400 VDD=5[V] 300 200 VDD=10[V] 100 VDD=16[V] 0 -25 0 25 50 75 20 -50 VDD=3[V] 600 500 Operating Temperature Range 400 VDD=5[V] 300 200 VDD=10[V] 100 VDD=16[V] 150 VDD=3[V] 100 75 VDD=5[V] 25 VDD=10[V] VDD=16[V] -25 0 25 50 75 -25 0 25 50 75 100 160 140 VDD=3[V] 100 80 VDD=5[V] 60 40 VDD=10[V] 20 VDD=16[V] -25 0 25 120 100 CLOCK or P/S 80 VDD=5[V] VDD=10[V] 20 VDD=16[V] -25 0 25 50 75 VDD=5[V] 300 200 VDD=10[V] 100 VDD=16[V] -25 0 25 50 75 100 [BU4021B/F] VDD=3[V] 160 140 Operating Temperature Range 120 100 VDD=5[V] 80 60 VDD=10[V] 40 VDD=16[V] 20 75 -50 100 -25 0 25 50 tsu Fig.19 Minimum CLK pulse width 20[ns] 10% tTLH Ambient Temperature [] Fig.20 Minimum P/S pulse width 9/16 tf th GND(VSS) VDD GND(VSS) 50% 10% 100 tr 90% 50% tPLH OUTPUT VDD tW 90% 75 Ambient Temperature [] 90% 50% 10% 0 -50 50 20[ns] 40 Operating Temperature Range 400 Switching characteristics Parallel Data or Serial Data VDD=3[V] 60 500 0 -50 Ambient Temperature [] 140 VDD=3[V] 600 180 120 Operating Temperature Range 160 [BU4021B/F] Fig.16 Propagation delay tPHL P/SQS Operating Temperature Range Fig.18 Hold time th CLKQ [BU4021B/F] 100 200 Ambient Temperature [] 180 75 Ambient Temperature [] [BU4021B/F] 180 Fig.17 Set up time tsu QCLK 200 50 700 -50 100 0 -50 25 0 Minimum CLK Pulse Width [ns] Operating Temperature Range 0 Fig.13 Propagation delay tPLH CLKQS 200 50 -25 Ambient Temperature [] Fig.15 Propagation delay tPLH P/SQS [BU4021B/F] 125 VDD=16[V] 800 -50 Hold Time (CLKDATA) [ns] Setup Time (DATACLK) [ns] 100 Ambient Temperature [] 0 Hold Time (CLKDATA) [ns] 15 700 100 Fig.14 Propagation delay tPHL CLKQS 175 VDD=10[V] 200 0 10 [BU4021B/F] Ambient Temperature [] 200 VDD=5[V] 300 0 -50 Operating Temperature Range 400 800 Propagation Delay Time (P/SQS) [ns] Propagation Delay Time (CLKQS) [ns] 700 500 500 Fig.12 Output sink currentvoltage [BU4021B/F] 600 VDD=3[V] 600 Output Voltage [V] Fig.11 Output source currentvoltage 800 [BU4021B/F] 700 Propagation Delay Time (P/SQS) [ns] 30 800 [BU4021B/F] Propagation Delay Time (CLKQS) [ns] [BU4021B/F] Output Sink Current [mA] Output Source Current [mA] 50 tPHL VOH VOL tTHL 100 Electrical Characteristics CurvesBU4094BC 50 40 VDD=15[V] -40[] 30 25[] 85[] 20 VDD=10[V] -40[] 25[] -40[] 85[] 25[] 10 40 VDD=15[V] -40[] 25[] 30 85[] -40[] 20 25[] VDD=10[V] 85[] 10 -40[] 25[] VDD=5[V] 85[] 85[] VDD=5[V] 0 15 20 0 5 Output Voltage [V] 300 [BU4094BC/F/FV] tPHL VDD=3[V] tPLH VDD=5[V] VDD=3[V] VDD=10[V] VDD=5[V] VDD=16[V] VDD=10[V] VDD=16[V] 200 100 Operating Temperature Range 0 -50 -25 0 25 50 75 500 Propagation Delay Time (CLKQN) [ns] Propagation Delay Time (CLKQ'S) [ns] 400 400 300 Operating Temperature Range 0 VDD=10[V] VDD=16[V] 50 Operating Temperature Range 0 -25 0 25 50 75 100 Propagation Delay Time (Output Enable QN) [ns] Propagation Delay Time (Output EnableQN) [ns] VDD=5[V] VDD=5[V] -50 -25 0 25 Minimum CLK Pulse Width [ns] 150 VDD=3[V] 100 VDD=5[V] VDD=10[V] VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V] tPLH VDD=10[V] VDD=16[V] 100 50 Operating Temperature Range -50 -25 0 25 50 75 100 0 25 50 75 Ambient Temperature [] Fig.30 Hold time tH CLKDATA 200 100 Operating Temperature Range 0 -50 100 -25 0 25 50 75 100 Ambient Temperature [] Fig.26 Propagation delay STROBEQN Operating Temperature Range 40 30 VDD=3[V] 20 VDD=5[V] 10 VDD=10[V] VDD=16[V] [BU4094BC/F/FV] Operating Temperature Range 150 VDD=3[V] VDD=5[V] 100 VDD=10[V] VDD=16[V] 50 -50 -25 0 25 50 75 100 Ambient Temperature [] Fig.31 Minimum CLK pulse width tW(CLK) 10/16 -50 -25 0 25 50 75 Ambient Temperature [] 0 -25 100 VDD=10[V] VDD=16[V] 0 0 VDD=16[V] 0 75 [BU4094BC/F/FV] tPHL VDD=3[V] VDD=5[V] 200 -50 300 [BU4094BC/F/FV] [BU4094BC/F/FV] Operating Temperature Range 50 50 200 150 25 tPLH tPHL VDD=3[V] VDD=3[V] VDD=5[V] VDD=5[V] VDD=10[V] VDD=16[V] 400 100 Fig.28 Propagation delay tPLZ Output EnableQN Fig.27 Propagation delay tPHZ Output EnableQN 50 75 Ambient Temperature [] Ambient Temperature [] 200 50 0 [BU4094BC/F/FV] Fig.25 Propagation delay CLKQN tPLH VDD=3[V] VDD=10[V] VDD=16[V] VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V] 100 -50 -25 500 Ambient Temperature [] [BU4094BC/F/FV] 100 -50 Fig.23 Propagation delay CLKQS VDD=3[V] VDD=5[V] VDD=10[V] VDD=16[V] 200 100 200 VDD=3[V] 100 Ambient Temperature [] tPLH tPHL Fig.24 Propagation delay CLKQ'S tPHL 200 20 [BU4094BC/F/FV] Ambient Temperature [] 150 15 Fig.22 Output sink currentvoltage Fig.21 Output source currentvoltage 500 10 Output Voltage [V] Propagation Delay Time (STROBEQN) [ns] 10 300 0 Setup Time (DATACLK [ns] 5 400 tPLH [BU4094BC/F/FV] VDD=3[V] tPHL VDD=5[V] VDD=3[V] VDD=10[V] VDD=5[V] VDD=16[V] VDD=10[V] VDD=16[V] Operating Temperature Range 0 0 Hold Time (CLKDATA) [ns] 500 [BU4094BC/F/FV] Propagation Delay (CLK Qs) [ns] [BU4094BC/F/FV] Output Sink Current [mA] Output Source Current [mA] 50 Fig.29 Set up time tsu DATACLK Switching characteristics are stated on page 14. 100 Electrical Characteristics CurvesBU4538B 1000 Operating Temperature Range 800 VDD=3[V] 600 400 VDD=5[V] 200 VDD=10[V] 800 VDD=3[V] 600 0 25 50 75 VDD=10[V] VDD=16[V] -25 25 50 75 VDD=3[V] 400 300 VDD=5[V] 200 200 VDD=10[V] 100 -25 0 25 50 75 120 VDD=3[V] 100 80 VDD=5[V] 60 40 VDD=10[V] VDD=16[V] -50 -25 VDD=3[V] 1 VDD=5[V] 0 -1 VDD=10[V] -2 VDD=16[V] -3 Operating Voltage Range -4 -50 -25 0 25 50 75 25 50 75 100 80 3 40 VDD=3[V] -2 VDD=5[V] -3 Operating Voltage Range -4 -25 0 25 50 75 100 Ambient Temperature [] Fig.39 Output pulse width tWOUT2 (CX=0.1[F],RX=100[k]) 20[ns] 50% 20[ns] 50% 10% 20[ns] 20[ns] 90% 50% 10% 20[ns] 20[ns] 90% 90% 50% CD tPLH Q 50% tPLH 90% 50% tPLH tPLH 50% 50% tTLH 10% 90% tPHL 50% 10% 10% WOUT Q tTHL 90% 50% tPLH 50% 10% 11/16 10% 0 25 50 75 100 Fig.37 Minimum RESET pulse width tRESET 0 -1 -25 Ambient Temperature [] 90% B VDD=16[V] -50 100 1 Switching Characteristics A VDD=10[V] 20 VDD=16[V] VDD=10[V] 2 -50 Fig.38 Output pulse width tWOUT1 (CX=2000[pF],RX=100[k]) VDD=5[V] 60 [BU4538B] 4 100 Ambient Temperature [] VDD=3[V] 120 -5 -5 100 Operating Temperature Range 140 5 Normalized Pulse Width Change [%] 2 0 Fig.36 Minimum input pulse width tWIN 3 75 [BU4538B] 160 Ambient Temperature [] [BU4538B] 4 50 0 Ambient Temperature [] 5 25 180 Operating Temperature Range 20 Fig.35 Propagation delay tPLH CDQ 0 Fig.34 Propagation delay tPHL CDQ 140 100 -25 Ambient Temperature [] 0 -50 VDD=16[V] 200 160 VDD=16[V] VDD=10[V] 100 -50 Minimum RESET Pulse Width [ns] Minimum Input Pulse Width [ns] Operating Temperature Range 600 VDD=5[V] 300 100 [BU4538B] 180 0 Normalized Pulse Width Change [%] 0 200 [BU4538B] 500 Operating Temperature Range 400 Fig.33 Propagation delay tPHL AQ 800 700 500 Ambient Temperature [] Fig.32 Propagation delay tPLH AQ VDD=3[V] 600 0 -50 100 [BU4538B] 700 0 Ambient Temperature [] Propagation Delay Time (CDQ) [ns] VDD=5[V] 200 VDD=16[V] -25 Operating Temperature Range 400 0 -50 800 [BU4538B] Propagation Delay Time (CDQ) [ns] [BU4538B] Propagation Delay Time (AQ) [ns] Propagation Delay Time (AQ) [ns] 1000 trr Reference dataBU4028B 50 50 [BU4028B] 400 [BU4028B] [BU4028B] VDD=15[V] -40[] 25[] 30 85[] 20 VDD=10[V] -40[] 25[] -40[] 85[] 25[] 85[] VDD=5[V] 0 0 5 VDD=15[V] -40[] 30 25[] 85[] 20 -40[] 25[] VDD=10[V] 85[] 10 0 10 15 0 20 5 150 VDD=10[V] 100 VDD=16[V] Operating Voltage Range 15 20 -50 -25 0 25 50 75 100 Output Voltage [V] Ambient Temperature [] Fig.40 Output source currentvoltage Fig.41 Output sink currentvoltage Fig.42 Propagation delay tTLH 500 500 350 VDD=3[V] 300 250 Operating Temperature Range VDD=5[V] 150 100 VDD=10[V] 50 VDD=3[V] 400 Operating Temperature Range 200 VDD=5[V] VDD=10[V] 100 VDD=16[V] 0 25 50 75 -50 100 300 Operating Temperature Range 200 VDD=5[V] VDD=10[V] 100 VDD=16[V] 0 0 0 VDD=3[V] 400 300 VDD=16[V] -25 [BU4028B] [BU4028B] Propagation Delay Time [ns] Output Fall Time [ns] VDD=5[V] 200 0 10 [BU4028B] -50 250 Output Voltage [V] 400 200 VDD=3[V] 300 50 -40[] 25[] VDD=5[V] 85[] Propagation Delay Time [ns] 10 40 Output Rise Time [ns] 40 Output Sink Current [mA] Output Sourace Current [mA] 350 -25 0 25 50 75 -50 100 Fig.43 Propagation delay tTHL -25 0 25 50 75 100 Ambient Temperature [] Ambient Temperature [] Ambient Temperature [] Fig.45 Propagation delay tPHL Fig.44 Propagation delay tPLH () Switching characteristics is shown in P15. Description of BU4015B series model FunctionDual 4-bit static shift register 1) Description of operation Dual 4-bit static shift register of BU4015B is configured with 2 independent serial input/parallel output registers of the same 4-state. Each register is provided with an independent clock and reset input having one series data input. Register state is the D type master/slave flip-flop. Data is shifted to the next stage during the rise time of the clock. Each register can be cleared by addition of "H" level to reset. PIN arrangement CLOCK B 1 16 VDD Q3B 2 15 D8 CL Q2B Q1A 3 R Q0 D Q3 Q2 Q1 Q0 4 14 13 RESET B D D Q0B CL CLOCK Q0A RESET A DA VSS 5 12 7 8 CL R D Q R Q Q1 D CL Q R Q Q2 D D Q CL R Q3 Q CL Q R RESET 11 10 9 Q2B Q3A CLOCK A D L X RESET L Q0 L H L H X L L X H L Q1 Q0 Q0 Q2 Q1 Q1 XDon't Care 12/16 L I/O Function CLOCKB I Clock input (CHB) 2 Q3B O Output 3 (CHB) 3 Q2A O Output 2 (CHA) 4 Q1A O Output 1 (CHB) 5 Q0A O Output 0 (CHA) 6 RESETA I Reset input (CHA) 7 DA I Data input (CHA) 8 VSS Power supply(-) 9 CLOCKA I Clock input (CHA) Q3A O Output 3 (CHA) 11 Q2B O Output 2 (CHB) 12 Q1B O Output 1 (CHB) Q2 13 Q0B O Output 0 (CHB) Q2 14 RESETB I Reset input (CHB) Q3 No Change L Symbol 1 10 Truth table CLOCK PIN No. Q Q1B Q0 Q1 Q2 Q3 6 PIN description Block diagram L 15 DB I Data input (CHB) 16 VDD Power supply(+) Description of BU4021B series model Function: 8-stage static shift register 1) Description of operation BU4021B is an 8-bit static shift register capable of parallel input/series output and series input/series output. In parallel operation, DS (data) being asynchronous with the clock is inputted into each F/F and obtained at output. In series operation, DS (data) is triggered by clock. When P/S input level is "H", parallel operation is effective, and when P/S input level is "L", series operation is effective. PIN arrangement P8 1 Q6 2 P4 4 P3 5 P2 6 P2 CLOCK P1 P/S 7 P1 P2 P3 P4 P5 P6 P7 P8 D Q D Q D Q D Q D Q C C C C D Q CQ D Q CQ D C P/S D CLOCK CQ I/O Function P8 I Parallel data input 8 Q6 O Output 6 Q8 O Output 8 P4 I Parallel data input 4 P3 I Parallel data input 3 P5 12 Q7 P2 I Parallel data input 2 11 DS P1 I Parallel data input 1 10 CLOCK VSS Power supply(-) P/S I Parallel/Serial control 10 CLOCK I Clock input 11 DS I Serial data input 12 Q7 O Output 7 13 P5 I Parallel data input 5 14 P6 I Parallel data input 6 15 P7 I Parallel data input 7 16 VDD Power supply (+) 9 Q6 Q7 Q8 P/S Truth table X Symbol 13 8 CLOCK PIN No. P6 DS P3 PIN description 14 Q7 P4 VSS P7 Q5 Q8 P1 VDD 15 P6 Q6 3 16 P7 P8 Q8 Block diagram D RESET Q0 Q1 Q2 Q3 L L L Q0 Q1 H L H Q0 Q1 X L X H CLOCK DS P/S Dm Q2 X H L L Q2 X H H H XDon't Care No Change L L L Qm* *:Q6,Q7,Q8: outside *Q6,Q7,Q8 L XDon't Care Description of BU4094BC series model Function: Dual 4-bit static shift register 1) Description of operation BU4094BC is an 8-stage shift/store register provided in each stage with a data latch with 3-state output. Data read into shift register is read into the latch during the fall time of asynchronous STROBE input, and in the data transfer mode, output can be held. Data is passed through the latch and outputted when the STROBE is in "H" level. Because the parallel output becomes high impedance when the OUTPUT ENABLE terminal is set to "L" level by 3-state, the parallel output can be connected directly with the 8-bit pass line. PIN arrangement PIN description PIN No. STROBE 1 SERIAL IN 2 CLOCK 3 STROBE SERIA IN CLOCK 16 OUTPUT ENABLE 15 Q5 14 Q1 4 Q1 Q6 13 Q2 5 Q2 Q7 12 Symbol I/O Function Latch input STROBE I SERIALIN I Data input CLOCK I Clock input Q1 O Parallel data input Q1 Q2 O Parallel data input Q2 Q3 O Parallel data input Q3 Q6 Q4 O Parallel data input Q4 Q7 VSS Power supply(-) QS O Serial data output QS Q8 10 Q'S O Serial data output Q'S 11 Q8 O Parallel data output Q8 12 Q7 O Parallel data output Q7 13 Q6 O Parallel data output Q6 14 Q5 O Parallel data output Q5 15 ENABLE I Output enable 16 VDD Power supply (+) VDD OUTPUT ENABLE Q5 Q3 6 Q3 Q8 11 Q4 7 Q4 Q'S 10 Q'S VSS 8 QS 9 QS 13/16 Block diagram Truth table SERIAL IN QS 8 STAGE SHIFT REGISTER CLOCK OUTPUT SERIAL STROBE IN ENABLE Q'S CLOCK SERIAL OUTPUT STROBE 8 BIT LACTH OUTPUT ENABLE 3 STATE OUTPUTS Q1 Parallel Output Serial Output Q1 Qn Qs Q's H H L L Qn-1 Q7 NC H H H H Qn-1 Q7 NC H L X NC NC Q7 NC L X X Z Z Q7 NC H X X NC NC NC Qs H H X Z Z NC Qs Q8 PARALLEL OUTPUTS Switching characteristics tr WH CLOCK 50% tf 90% 50% 50% 10% DATA su h tWL STROBE OUTPUT ENABLE 50% 50% 90% 50% 10% Q1Q7 tPLH tPHL tPLH 90% tTLH tPZH tPZL tPHZ 50% 10% 50% 90% 10% tTHL 50% 50% tpLH Q'S QS' 10% tPHL tpLH QS 90% tPLZ tpHL 50% 50% Description of BU4538B series model Function: Dual high accuracy monostable multivibrator 1) Description of operation BU4538B is a re-triggerable monostable multi vibrator. Triggering is possible from either edge of the rise time and fall time of input pulse. Output pulse setting is determined by the time constant (Rx * Cx) of external Rx and Cx. Recommended output pulse amplitude is 200[s]~1[s]. (Cautions on use: In case of system power down, etc., electric charge accumulated in the capacity Cx is discharged to the VDD terminal through protective diode of 2 pins of 14 pins. When the electric current due to accumulated electric charge exceeds 10[mA], IC may be destructed. When a large capacity Cx is used, electric current flowing into the IC can be restricted by inserting the diode Dx.) PIN description PIN arrangement T1A 1 T2A 2 CDA 3 AA 4 BA 5 QA 6 QA 7 VSS 16 BA CD CHA Q Q T1 T2 BA CD 8 Block diagram CHB Q Q T1 T2 VDD 15 T1B 14 T2B 13 CDB 12 AB 11 BB 10 QB VDD DX PIN No. RX R Q Output Latch S Q CX Vref1 Enable A Vref2 Enable Control S CD Q Reset Latch Q R QB Truth table INPUT A OUTPUT B CD H H L Q Q H L H H H L H L H X H I/O L L H XDon't Care 14/16 Q Q Function Passive component T1A T2A CDA I AA I Input A(CHA) BA I Input B(CHA) VDD B 9 Symbol connection pin 1(CHA) Passive component connection pin 2(CHA) Reset input (CHA) QA O Output Q(CHA) QAB O Output QB(CHA) VSS Power supply(-) QBB O Output QB(CHB) 10 QB O Output Q(CHB) 11 BB I Input B(CHB) 12 AB I Input A(CHB) 13 CCB I Reset input (CHB) 14 T2B 15 T1B 16 VDD Passive component connection pin 1(CHB) Passive component connection pin 2(CHB) Power supply (+) Description of BU4028B series model Function: BCD to decimal decoder 1) Description of operation BU4028B is a decoder to convert BCD signals into decimal signals. Out of 10 outputs of Q0~Q9, output applicable for the input code of A~D becomes "H" level and all other outputs become "L" level. When the input of D is made to be inhibit input by using 3 inputs of A~C, this product can be used as a 1-OF-8 decoder. PIN arrangement Q4 Q2 16 1 Q2 2 Q4 Q3 PIN description Block diagram 15 VDD Q1 Q0 3 Q7 4 Q9 5 Q5 6 Q5 Q6 7 Q6 B Q7 C Q9 14 13 12 VSS Q1 C 11 D A 10 A 8 9 B B D Q8 IN C D Q8 Truth table INPUT D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H Switching characteristics 20[ns] OUTPUT A L H L H L H L H L H L H L H L H Symbol I/O Function Q4 O Output 4 Q1 Q2 O Output 2 Q2 Q0 O Output 0 Q3 Q7 O Output 7 Q4 Q9 O Output 9 Q5 Q5 O Output 5 Q6 Q6 O Output 6 Q7 VSS Power supply(-) Q8 Q8 O Output 8 Q9 10 A I Input A 11 D I Input D 12 C I Input C 13 B I Input B 14 Q1 O Output 1 Q3 A Q0 PIN No. Q0 Q9 Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 L L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L H L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L L 20[ns] 90% Input wave 50% 10% tPHL tPLH Neg. 15 Q3 O Output 3 16 VDD Power supply (+) 90% 50% Output wave Pos. 10% tTLH tTHL Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses. 2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC. 9. Ground Wiring Pattern When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either. 10. Unused input terminals Connect all unused input terminals to VDD or VSS in order to prevent excessive current or oscillation Insertion of a resistor (100k approx.) is also recommended. 15/16 Dimension DIP16 SSOP-B16 SOP16 <Dimension> <Dimension> <Dimension> (Unit:mm) (Unit:mm) (Unit:mm) Part Number Explanation B U 4 0 9 4 B C F Package Type BlankDIP16 F SOP16 FV SSOP-B16 Part Number BU4015B BU4538B BU4021B BU4028B BU4094BC DIP16 SOP16, SSOP-B16 <Packing information> <Tape and Reel information> Tape 2 Package and forming specification Blank : Container tube E2 : Embossed tape reel Pin 1 opposite of feeding side Embossed carrier tape Container Tube Quantity 1,000pcs Quantity 2500pcs Direction Direction of products is fixed in a container tube. of feed Direction of feed E2 (The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand) 1234 1234 1234 1Pin 1234 1234 1234 1234 1234 Reel Please order in multiples of the minimum package quantity. E Direction of feed When you order , please order in times the amount of package quantity. 16/16 Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2008 ROHM CO.,LTD. THE AMERICAS / EUROPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21 Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0