CS42L52-CNZ - Cirrus Logic, Inc.

http://www.cirrus.com MAY '08

DS680F1

Low-power, Stereo CODEC w/ Headphone & Speaker Amps

Stereo CODEC

High Performance Stereo ADC & DAC

– 99 dB (ADC), 98 dB (DAC) Dyn. Range (A-wtd)

– -88 dB THD+N

Flexible Stereo Analog Input Architecture

– 4:1 Analog Input MUX

– Analog Input Mixing

– Analog Passthrough with Volume Control

– Analog Programmable Gain Amplifier (PGA)

Programmable Automatic Level Control (ALC)

– Noise Gate for Noise Suppression

– Programmable Threshold & Attack/Release

Rates

Dual MIC Inputs

– Differential or Single-ended

– +16 dB to +32 dB w/ 1dB step MIC Pre-

Amplifiers

– Programmable, Lo w-noise MIC Bias Levels

Digital Signal Processing Engine

– Bass & Treble Tone Control, De-emphasis

– Master Vol. and Independent PCM SDIN + ADC

SDOUT Mix Volume Control

– Soft-ramp & Zero-Cross Transitions

– Programmable Peak-detect and Limiter

– Beep Generator w/Full Tone Control

Class D Stereo/Mono Speaker Amplifier

No External Filter Required

High-power Stereo Output at 10% THD+N

– 2 x 1.00 W into 8 Ω @ 5.0 V

– 2 x 550 mW into 8 Ω @ 3.7 V

– 2 x 230 mW into 8 Ω @ 2.5 V

High-power Mono Output at 10% THD+N

– 1 x 1.90 W into 4 Ω @ 5.0 V

– 1 x 1.00 W into 4 Ω @ 3.7 V

– 1 x 350 mW into 4 Ω @ 2.5 V

Direct Battery-powered Operation

– Battery Level Monitoring & Compensation

81% Efficiency at 800 mW

Phase-aligned PWM Output Reduces Idle

Channel Current

Spread Spectrum Modulation

Low Quiescent Current

Stereo Headphone Amplifier

Ground-centered Outputs

– No DC-Blocking Capacitor s Required

– Integrated Negative Voltage Regulator

High-power Output at -75 dB THD+N

– 2 x 23 mW Into 16 Ω @ 1.8 V

– 2 x 44 mW Into 16 Ω @ 2.5 V

(Features continued on page 2)

Serial Audio

Input/Output

I2C Control

+1.65 V to +3.47 V

Interface Supply

Control Port Serial Audio Port

Level Shifter

Multi-bit

∆Σ ADC

Beep

+1.65 V to +2.63 V

Analog Supply

Multi-bit

∆Σ ADC

ALC

Left HP/Line

Output

Ground-Centered

Amps

Mono mix,

Limiter , Bass,

Treble Adjust

Volume, Mono

Swap, Mix

Right HP/Line

Output

Left

Inputs

Right

Inputs

+1.65 V to +2.63 V

Headphone Supply

Speaker/HP

Switch

+1.60 V to +5.25 V

Battery

Charge Pump

+VHP

-VHP

+1.65 V to +2.63 V

Digital Supply

+1.65 V to +2.63 V

Analog Supply

Pulse-Width

Modulator

(PWM)

Stereo/Mono

Full-Bridge

Speaker

Outputs

Battery Level Moni toring & Compensation

Multi-bit

∆Σ DAC

MIC Bias

HPF

Selectable

Bias Voltage

ΣALC

Summing

Programmable

Gain Amps

+16 to +32 dB Diff./

S.E. MIC Pre-Amps

Class D Amps

Reset

CS42L52

DRAFTv1

5/13/08

2DS680F1

CS42L52

5/13/08

System Features

12, 24, and 27 MHz Master Clock Support in

Addition to Typical Audio Clock Rates

High-performance 24-bit Converters

– Multi-bit Delta-Sigma Architecture

– Very Low 64Fs Oversampling Clock Reduces

Power Consumption

Low-power Operation

– Stereo Analog Passth rough: 10 mW @ 1.8 V

– Stereo Playback: 14 mW @ 1.8 V

– Stereo Rec. and Playback: 23 mW @ 1.8 V

Variable Power Supplies

– 1.8 V to 2.5 V Digital & Analog

– 1.6 V to 5 V Class D Amplifier

– 1.8 V to 2.5 V Headphone Amplifier

– 1.8 V to 3.3 V Interface Logic

Power-down Management

– ADC, DAC, CODEC, MIC Pre-Amplifier, PGA,

Headphone Amplifier, Speaker Amplifier

Analog & Digital Routing/Mixes:

– Line/Headphone Out = Analog In (ADC

Bypassed)

– Line/Headphone/Speaker

Out = ADC + Digital In

– Digital Out = ADC + Digital In

– Internal Digital Loopback

– Mono Mixes

Flexible Clocking Options

– Master or Slave Operation

– High-impedance Digital Output Option (for easy

MUXing between CODEC & other data

sources)

– Quarter-speed Mode - (i.e. allows 8 kHz Fs

while maintaining a flat noise floor up to 16 kHz)

– 4 kHz to 96 kHz Sample Rates

I²C® Control Port Operation

Headphone/Speaker Detection Input

Pop and Click Suppression

Applications

Digital Voice Recorders, Digital Cameras, &

Camcorders

PDA’s

Personal Media Players

Portable Game Consoles

General Description

The CS42L52 is a highly integrated, low-power stereo CO-

DEC with headphone and Class D speaker amplifiers. The

CS42L52 offers many features suitable for low-powe r, porta-

ble system applications.

The ADC input path allows independent channel control of a

number of features. Input summing amplifiers mix and select

line-level and/or microphone-level inputs for each channel.

The microphone input path includes a selectable programma-

ble-gain pre-amplifier stage and a low-noise MIC bias voltage

supply. A PGA is availab le for line or microphone inputs and

provides analog gain with soft-ramp and zero-cross transi-

tions. The ADC also features a digital volume control with soft

ramp transitions. A programmable ALC and Noise Gate mon-

itor the input signals and adjust the volume levels

appropriately. To conserve power, the ADC may be bypassed

while still allowing full analog volume control.

The DAC output path includes a digital signal processing en-

gine with various fixed-function controls. Tone Control

provides bass and treble adjustment of four selectable corner

frequencies. The Digital Mixer provides independent volume

control for both the ADC output and PCM input signal paths,

as well as a master volume control. Digital Volume controls

may be configured to change on soft-ramp transitions while

the analog controls can be configured to occur on every zero

crossing. The DAC also includes de-emphasis, limiting func-

tions and a BEEP generator, delivering tones selectable

across a range of two full octaves.

The stere o headphone ampl ifier is powered from a separate

positive supply and the integrated charge pump provides a

negative supply. This allows a ground-centered, analog output

with a wide signa l swin g and e limina tes external DC-bl ocking

capacitors.

The Class D stereo speaker amplifier does not require an

external filter and provides the high-efficiency amplification re-

quired by power-sensitive por table applications. The speaker

amplifier may be powered directly from a battery while the in-

ternal DC supply monitoring and compensation provides a

constant gain level as the battery’s voltage decays.

In addition to its many features, the CS42L52 operates from a

low-voltage analog and digital core making it ideal for portable

systems that require extremely low power consumption in a

minimal amount of space.

The CS42L52 is available in a 40-pin QFN package in both

Commercial (-40 to + 85 °C) and Automotive (-40 to +105 °C)

grades. The CS42L52 Customer Demonstration board is also

available for device evaluation and implementation sugges-

tions. Please refer to “Ordering Information” on page 81 for

complete ordering information.

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TABLE OF CONTENTS

1. PIN DESCRIPTIONS .............................................................................................................................. 8

1.1 I/O Pin Characteristics ................. ... ... ................ ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ..................... 9

2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 10

3. CHARACTERISTIC AND SPECIFICATIONS ...................................................................................... 11

RECOMMENDED OPERATING CONDITIONS ................................................................................... 11

ABSOLUTE MAXIMUM RATINGS .......................................................................................................11

ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ) .......................................................... 12

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) .......................................................... 13

ADC DIGITAL FILTER CHAR ACTERI S TI CS ................. ... ... ................ ... .... ... ... ... .... ................ ... ... ... ... 14

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) ...................................................... 15

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) ...... ... .... ... ... ... ................ .... ... ... ... ... 16

ANALOG PASSTHROUGH CHARACTERISTICS ............................................................................... 17

PWM OUTPUT CHA RACTERI STICS ........ ... .... ... ... ... ................. ... ... ... ... .... ... ................ ... ... .... ... ... ... ... 17

HEADPHONE OUTP UT POWER CHARA CTERISTI CS ............................. ... ... ... .... ... ... ... ... .... ... ... ... ... 19

LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS ..................................................................... 20

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE .............................. 20

SWITCHING SPECIFICATIONS - SERIAL PORT ............................................................................... 21

SWITCHING SPECIFICATIONS - I²C CONTROL PORT ..................................................................... 22

DC ELECTRICAL CHARACTERISTICS .............................................................................................. 23

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS ..................................................... 23

POWER CONSUMPTION .................................................................................................................... 24

4. APPLICATIONS ................................................................................................................................... 25

4.1 Overview ......................................................................................................................................... 25

4.1.1 Basic Architecture ................................................................................................................. 25

4.1.2 Line & MIC Inputs .................................................................................................................. 25

4.1.3 Line & Headphone Outputs ................................................................................................... 25

4.1.4 Speaker Driver Outputs ......................................................................................................... 25

4.1.5 Fixed Function DSP Engine .................................................................................................. 25

4.1.6 Beep Generator ..................................................................................................................... 25

4.1.7 Power Management .............................................................................................................. 25

4.2 Analog Inputs ................................................................................................................................. 26

4.2.1 MIC Inputs ............................................................................................................................. 27

4.2.2 Automatic Level Control (ALC) .............................................................................................. 27

4.2.3 Noise Gate ............................................................................................................................ 28

4.3 Analog Outputs .............................................................................................................................. 29

4.3.1 Beep Generator ..................................................................................................................... 30

4.3.2 Limiter .................................................................................................................................... 31

4.4 Analog In to Analog Out Passthrough ............................................................................................ 32

4.4.1 Overriding the ADC Power Down ............................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 32

4.4.2 Overriding the PGA Power Down ............................. .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 33

4.5 PWM Outputs ................................................................................................................................. 33

4.5.1 Mono Speaker Output Configuration ..................................................................................... 33

4.5.2 VP Battery Compensation .............. .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ................ ... .... ... ... ...... 33

4.5.2.1 Maintaining a Desired Output Level ........................................................................... 34

4.6 Serial Port Clocking ........................................................................................................................ 34

4.7 Digital Interface Formats ................................................................................................................ 36

4.7.1 DSP Mode ............................................................................................................................. 36

4.8 Initialization ..................................................................................................................................... 37

4.9 Recommended Power-up Sequence ..............................................................................................37

4.10 Recommended Power-down Sequence ....................................................................................... 37

4.11 Required Initialization Settings ..................................................................................................... 37

4.12 Control Port Operation ........ ... .... ... ... ... ... ....................................................................................... 38

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4.12.1 I²C Control ........................................................................................................................... 38

4.12.2 Memory Address Pointer (MAP) .......................................................................................... 39

4.12.2.1 Map Increment (INCR) ............................................................................................. 39

5. REGISTER QUICK REFERENCE ........................................................................................................ 40

6. REGISTER DESCRIPTION .................................................................................................................. 42

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 42

6.1.1 Chip I.D. (Read Only) ............................................................................................................ 42

6.1.2 Chip Revision (Read Only) .................................................................................................... 42

6.2 Power Control 1 (Address 02h) ...................................................................................................... 42

6.2.1 Power Down ADC Charge Pump .......................................................................................... 42

6.2.2 Power Down PGAx ................................................................................................................ 42

6.2.3 Power Down ADCx ................................................................................................................ 43

6.2.4 Power Down .......... ... ... ... .... ... ... ... ... ................. ... ... ... .... ................ ... ... ... .... ............................ 43

6.3 Power Control 2 (Address 03h) ...................................................................................................... 43

6.3.1 Power Down ADC Override ................................................................................................... 43

6.3.2 Power Down MICx ................................................................................................................. 43

6.3.3 Power Down MIC Bias .......................................................................................................... 43

6.4 Power Control 3 (Address 04h) ...................................................................................................... 44

6.4.1 Headphone Power Control .......... ................ .... ... ... ... .... ... ... ... ... ................. ... ... ... ... .... ... ... ... ... 44

6.4.2 Speaker Power Control ...................... ... ... ... ................. ... ... ... ... .... ... ................ ... ... .... ... ... ...... 44

6.5 Clocking Control (Address 05h) ...................................................................................................... 44

6.5.1 Auto-Detect . ... ... .... ... ... ................ ... .... ... ... ................ .... ... ... ... ................ .... ... ... ... ................... 44

6.5.2 Speed Mode .......... ... ... ... .... ... ... ... ... ................. ... ... ... .... ................ ... ... ... .... ............................ 45

6.5.3 32kHz Sample Rate Group ................................................................................................... 45

6.5.4 27 MHz Video Clock .............................................................................................................. 45

6.5.5 Internal MCLK/LRCK Ratio ................................................................................................... 45

6.5.6 MCLK Divide By 2 .............. ... ... ... ... .... ... ... ... ................. ... ... ... ... ................. ... ... ... ... ................ 46

6.6 Interface Control 1 (Address 06h) .................................................................................................. 46

6.6.1 Master/Slave Mode ..... ... .... ... ... ... ... .... ... ... ............................................................................. 46

6.6.2 SCLK Polarity ........... ... ... .... ... ... ... ... .... ................ ... ... .... ... ................ ... ... .... ... ......................... 46

6.6.3 ADC Interface Format .... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ................ ... ... .... ... ......... 46

6.6.4 DSP Mode ............. ... ... ... .... ... ... ... ... ................. ... ... ... .... ................ ... ... ... .... ............................ 46

6.6.5 DAC Interface Format .... .... ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ................ ... ... .... ... ......... 47

6.6.6 Audio Word Length ................................................................................................................ 47

6.7 Interface Control 2 (Address 07h) .................................................................................................. 47

6.7.1 SCLK equals MCLK .............................................................................................................. 47

6.7.2 SDOUT to SDIN Digital Loopback ......................................................................................... 47

6.7.3 Tri-State Serial Port Int erface ................... ... ................. ... ... ... ... .... ... ................ ... ... .... ... ......... 48

6.7.4 Speaker/Headphone Switch Invert ..................... ... ... ................ .... ... ... ... .... ... ... ... ... .... ... ... ... ... 48

6.7.5 MIC Bias Level ...................... ................ ... ... .... ... ... ................ ... .... ... ... ................ ... ................ 48

6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h) ....................... 48

6.8.1 ADC Input Select ............................ .... ... ................................................................................ 48

6.8.2 PGA Input Mapping ........................ .... ... ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ......... 49

6.9 Analog & HPF Control (Address 0Ah) ............................................................................................ 49

6.9.1 ADCx High-Pass Filter .......................................................................................................... 49

6.9.2 ADCx High-Pass Filter Freeze .............................................................................................. 49

6.9.3 Ch. x Analog Soft Ramp ........................... ... ................. ... ... ... ... .... ... ................ ... ... .... ... ......... 49

6.9.4 Ch. x Analog Zero Cross .......................... ... .... ... ... ... .... ................ ... ... ... .... ... ... ...................... 49

6.10 ADC HPF Corner Frequency (Address 0Bh) ................................................................................ 50

6.10.1 HPF x Corner Frequency .................................................................................................... 50

6.11 Misc. ADC Control (Address 0Ch) ................................................................................................ 50

6.11.1 Analog Front-End Volume Setting B=A ............................................................................... 50

6.11.2 Digital MUX ......................................................................................................................... 50

6.11.3 Digital Sum .......................................................................................................................... 50

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6.11.4 Invert ADC Signal Polarity ................ ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... ... .... ... ......... 51

6.11.5 ADC Mute ............... ... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ... .... ............................ 51

6.12 Playback Control 1 (Address 0Dh) ............................................................................................... 51

6.12.1 Headphone Analog Gain ..................................................................................................... 51

6.12.2 Playback Volume Setting B=A ............................................................................................ 51

6.12.3 Invert PCM Signal Polarity ............... ................................................................................... 52

6.12.4 Master Playback Mute ......................................................................................................... 52

6.13 Miscellaneous Controls (Address 0Eh) .................. ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 52

6.13.1 Passthrough Analog .................. ................ .... ... ... ... .... ... ... ... ... .... ... ... ... ................ .... ... ......... 52

6.13.2 Passthrough Mute .. ... ... .... ... ... ... ... .... ... ... ................ .... ... ... ... ... .... ... ... ... .... ... ... ... ................... 52

6.13.3 Freeze Registers ....... ... .... ................ ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ............ 52

6.13.4 HP/Speaker De-emphasis ......... ... .... ... ... ............................................................................. 53

6.13.5 Digital Soft Ramp ................................................................................................................ 53

6.13.6 Digital Zero Cross ............. ... ... ... ................ .... ... ... ... .... ... ... ... ................ .... ... ... ... ... .... ............ 53

6.14 Playback Control 2 (Address 0Fh) ... ... ... .... ................................................................................... 54

6.14.1 Headphone Mute ................. ... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... .... ... ... ... ... .... ... ......... 54

6.14.2 Speaker Mute .. .... ... ... ... .... ... ... ... ... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ............ 54

6.14.3 Speaker Volume Setting B=A ..............................................................................................54

6.14.4 Speaker Channel Swap ....................................................................................................... 54

6.14.5 Speaker MONO Control ...................................................................................................... 54

6.14.6 Speaker Mute 50/50 Control ............................................................................................... 54

6.15 MICx Amp Control:MIC A (Address 10h) & MIC B (Address 11h) ................................................ 55

6.15.1 MIC x Select ........................................................................................................................ 55

6.15.2 MICx Configuration ....... .... ... ... ... ................ .... ... ... ... .... ... ... ... ................ .... ... ... ... ... .... ............ 55

6.15.3 MICx Gain ........... ... ... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ... .... ............................ 55

6.16 PGAx Vol. & ALCx Transition Ctl.:

ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h) .................................................................. 55

6.16.1 ALCx Soft Ramp Disable ..................................................................................................... 55

6.16.2 ALCx Zero Cross Disable .................................................................................................... 56

6.16.3 PGAx Volume ............ ... .... ... ... ... ... .... ... ... ... .... ... ... ................ ... .... ... ... ... .... ... ... ...................... 56

6.17 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 57

6.17.1 Passthrough x Volume ........................................................................................................ 57

6.18 ADCx Volume Control: ADCAVOL (Address 16h) & ADCBVOL (Address 17h) .......................... 57

6.18.1 ADCx Volume ............... .... ... ... ... ................ .... ... ... ... .... ... ... ... ................ .... ... ... ... ... .... ............ 57

6.19 ADCx Mixer Volume: ADCA (Address 18h) & ADCB (Address 19h) ................... ................... ...... 58

6.19.1 ADC Mixer Channel x Mute ................................................................................................. 58

6.19.2 ADC Mixer Channel x Volume ............................................................................................. 58

6.20 PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) ....... ... .... ... ... ... ... ................ 58

6.20.1 PCM Mixer Channel x Mute ................................................................................................58

6.20.2 PCM Mixer Channel x Volume ............................................................................................ 58

6.21 Beep Frequency & On Time (Address 1Ch) ................................................................................. 59

6.21.1 Beep Frequency ............... ... ... ... ... .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 59

6.21.2 Beep On Time .................. ... ... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ................ ............ 60

6.22 Beep Volume & Off Time (Address 1Dh) ......................................................................................60

6.22.1 Beep Off Time . .... ... ... ... .... ... ... ... ... ................. ... ... ... .... ... ... ... ... .... ................ ... ... ... .... ............ 60

6.22.2 Beep Volume .................... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 61

6.23 Beep & Tone Configuration (Address 1Eh) .................................................................................. 61

6.23.1 Beep Configuration ................. ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ................ ... ... .... ............ 61

6.23.2 Beep Mix Disable ................................................................................................................ 61

6.23.3 Treble Corner Frequency ....................... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ................ ...... 62

6.23.4 Bass Corner Frequency ... ... ... ................ ... .... ... ... ... .... ... ... ................ ... .... ... ... ... ... .... ... ... ...... 62

6.23.5 Tone Control Enable ........ ... ... ... ... .... ... ................ ... .... ... ... ... ... .... ... ... ................ ... .... ... ......... 62

6.24 Tone Control (Address 1Fh) ...... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... ................. ... ... ... ... .... ............ 62

6.24.1 Treble Gain ............. ... ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ... .... ... ................ ... ... ................ 62

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6.24.2 Bass Gain ............................................................................................................................ 63

6.25 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h) ....................................... 63

6.25.1 Master Volume Control ........................................................................................................ 63

6.26 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h) ..................................... 63

6.26.1 Headphone Volume Control ................................................................................................63

6.27 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h) ...................................... 64

6.27.1 Speaker Volume Control ..................................................................................................... 64

6.28 ADC & PCM Channel Mixer (Address 26h) .................................................................................. 64

6.28.1 PCM Mix Channel Swap ..................................................................................................... 64

6.28.2 ADC Mix Channel Swap ...................................................................................................... 64

6.29 Limiter Control 1, Min/Max Thresholds (Address 27h) ................................................................. 65

6.29.1 Limiter Maximum Threshold ................................................................................................ 65

6.29.2 Limiter Cushion Threshold .................................................................................................. 65

6.29.3 Limiter Soft Ramp Disable ... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... .... ...... ...... ....... ......... 65

6.29.4 Limiter Zero Cross Disable .................................................................................................. 66

6.30 Limiter Control 2, Release Rate (Address 28h) ............................................................................ 66

6.30.1 Peak Detect and Limiter ...................................................................................................... 66

6.30.2 Peak Signal Limit All Channels ........................................................................................... 66

6.30.3 Limiter Release Rate ........................................................................................................... 66

6.31 Limiter Attack Rate (Address 29h) ................................................................................................ 67

6.31.1 Limiter Attack Rate .............................................................................................................. 67

6.32 ALC Enable & Attack Rate (Address 2Ah) ................................................................................... 67

6.32.1 ALCx Enable ....................................................................................................................... 67

6.32.2 ALC Attack Rate .................................................................................................................. 67

6.33 ALC Release Rate (Address 2Bh) ................................................................................................ 68

6.33.1 ALC Release Rate ............................................................................................................... 68

6.34 ALC Threshold (Address 2Ch) ..................................................................................................... 68

6.34.1 ALC Maximum Threshold .................................................................................................... 68

6.34.2 ALC Minimum Threshold ..................................................................................................... 69

6.35 Noise Gate Control (Address 2Dh) ......................... ... ... ... ................ .... ... ... ................ ... .... ... ......... 69

6.35.1 Noise Gate All Channels ..................................................................................................... 69

6.35.2 Noise Gate Enable .............................................................................................................. 69

6.35.3 Noise Gate Threshold and Boost ........................................................................................ 70

6.35.4 Noise Gate Delay Timing .................................................................................................... 70

6.36 Status (Address 2Eh) (Read Only) ........ .... ................ ... ... .... ... ... ... ... .... ... ... ... .... ... ................ ... ...... 70

6.36.1 Serial Port Clock Error (Read Only) .................................................................................... 70

6.36.2 DSP Engine Overflow (Read Only) ..................................................................................... 71

6.36.3 PCMx Overflow (Read Only) ...............................................................................................71

6.36.4 ADCx Overflow (Read Only) ...............................................................................................71

6.37 Battery Compensation (Address 2Fh) .......................................................................................... 71

6.37.1 Battery Compensation ......................................................................................................... 71

6.37.2 VP Monitor .............. ... ... .... ................ ... ... ... .... ... ... ................ ... .... ... ... ... .... ............................ 71

6.37.3 VP Reference ...................................................................................................................... 72

6.38 VP Battery Level (Address 30h) (Read Only) ...............................................................................72

6.38.1 VP Voltage Level (Read Only) ............................................................................................72

6.39 Speaker Status (Address 31h) (R ead Only) .............. ................ ... ... .... ... ... ... ................ .... ... ... ... ... 72

6.39.1 Speaker Current Load Status (Read Only) ......................................................................... 72

6.39.2 SPKR/HP Pin Status (Read Only) ....................................................................................... 73

6.40 Charge Pump Frequency (Address 34h) ...................................................................................... 73

6.40.1 Charge Pump Frequency .................................................................................................... 73

7. ANALOG PERFORMANCE PLOTS ....... ... ... .... ... ... ... ................. ... ... ... ... .... ... ... ... .... ... ... ... ... ................74

7.1 Headphone THD+N versus Output Power Plots ............................................................................ 74

8. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 76

8.1 Auto Detect Enabled ....................................................................................................................... 76

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8.2 Auto Detect Disabled ...................................................................................................................... 76

9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 77

9.1 Power Supply, Grounding ............................................................................................................... 77

9.2 QFN Thermal Pad .......................................................................................................................... 77

10. ADC & DAC DIGITAL FILTERS ........................................................................................................ 78

11. PARAMETER DEFINITIONS ....... ................ .... ... ... ... .... ... ... ... ................ .... ... ... ... .... ... ... ... ... ................ 79

12. PACKAGE DIMENSIONS ........ ... .... ... ... ... ... .... ................ ... ... .... ... ... ... ................ .... ... ... ... ... .... ............ 80

THERMAL CHARACTERISTICS ................... .... ................ ... ... .... ... ... ... ... .... ... ... ... .... ... ................ ... ...... 80

13. ORDERING INFORMATIO N ....... .... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ... ... .... ... ................ ......... 81

14. REFERENCES ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ................. ... ... ... ... .... ... ................ ...................... 81

15. REVISION HISTORY ............. ... ... .... ... ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... ......................... 81

LIST OF FIGURES

Figure 1. Typical Connection Diagram ...................................................................................................... 10

Figure 2. Headphone Output Test Load .................................................................................................... 19

Figure 3. Serial Audio Interface Timing ..................................................................................................... 21

Figure 4. Control Port Timing - I²C ............................................................................................................ 22

Figure 5. Analog Input Signal Flow ........................................................................................................... 26

Figure 6. Single-Ended MIC Configuration ............................................................................................... 27

Figure 7. Differential MIC Configuration .................................................................................................... 27

Figure 8. ALC ............................................................................................................................................ 28

Figure 9. Noise Gate Attenuation .............................................................................................................. 28

Figure 10. DSP Engine Signal Flow .......................................................................................................... 29

Figure 11. PWM Output Stage .................................................................................................................. 30

Figure 12. Analog Output Stage ................................................................................................................ 30

Figure 13. Beep Configuration Options ..................................................................................................... 31

Figure 14. Peak Detect & Limiter .............................................................................................................. 32

Figure 15. Battery Compensation ............................................................................................................. 34

Figure 16. I²S Format ................................................................................................................................ 36

Figure 17. Left-Justified Format ................................................................................................................ 36

Figure 18. Right-Justified Format (DAC only) ........................................................................................... 36

Figure 19. DSP Mode Format) .................................................................................................................. 36

Figure 20. Control Port Timing, I²C Write .................................................................................................. 38

Figure 21. Control Port Timing, I²C Read .................................................................................................. 38

Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load) .......... ................ ... ... ... .... ... ... ...... 74

Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) .......... ................ ... ... ... .... ... ... ...... 74

Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) .......... ................ ... ... ... .... ... ... ...... 75

Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) .......... ................ ... ... ... .... ... ... ...... 75

Figure 26. ADC Passband Ripple ............................................................................................................. 78

Figure 27. ADC Stopband Rejection ......................................................................................................... 78

Figure 28. ADC Transition Band ............................................................................................................... 78

Figure 29. ADC Transition Band (Detail) ................................................................................................... 78

Figure 30. DAC Passband Ripple ............................................................................................................. 78

Figure 31. DAC Stopband ......................................................................................................................... 78

Figure 32. DAC Transition Band ............................................................................................................... 78

Figure 33. DAC Transition Band (Detail) ................................................................................................... 78

8DS680F1

CS42L52

5/13/08

1. PIN DESCRIPTIONS

Pin Name # Pin Description

SDA 1 Serial Control Data (Input/Output) - SDA is a data I/O in I²C Mode.

SCL 2 Serial Control Port Clock (Input) - Serial clock for the serial control port.

AD0 3 Address Bit 0 (Input) - Chip address bit 0.

SPKR_OUTA+

SPKR_OUTA-

SPKR_OUTB+

SPKR_OUTB-

PWM Speaker Output (Output) - Full-bridge amplified PWM speaker outputs.

VP 5

8Power for PWM Drivers (Input) - Power supply for the PWM output driver stages.

-VHPFILT 10 Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge

pump that provides the negative rail for the headpho ne /l i ne amplifie rs.

FLYN 11 Charge Pump Cap Negative Node (Output) - Negative node for the inverting charge pump’s fly-

ing capacitor.

FLYP 12 Charge Pump Cap Positive Node (Output) - Positive node for the inverting charge pump’s flying

capacitor.

+VHP 13 Positive Analog Power fo r Headphone (Input) - Positive voltage rail and power for the internal

headphone amplifiers and inverting charge pump.

HP/LINE_OUTB, A 14,15 Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs.

VA 16 Analog Power (Input) - Positive power for the internal analog section.

GND/Therma l Pad

SDOUT

MCLK

SCLK

SDIN

SDA

LRCK

FLYN

+VHP

HP/LINE_OUTB

HP/LINE_OUTA

MICBIAS

AIN4A/MIC1+/MIC2A

AIN2A

AD0

SPKR_OUTA+

SPKR_OUTB-

-VHPFILT AIN4B/MIC2+/MIC2B

AIN1B

AIN2B

AFILTB

AIN3B/MIC2-/MIC1B

AFILTA

AIN1A

AIN3A/MIC1-/MIC1A

SPKR_OUTB+

SCL

DGND

SPKR_OUTA-

FLYP

AGND

FILT+

RESET

SPKR/HP

Top-Down (Through-Package) View

40-Pin QFN Package

DS680F1 9

CS42L52

5/13/08

1.1 I/O Pin Characteristics

Input and output levels and associated power supply voltage are shown in the table below. Logic levels

should not exceed the corresponding power supply voltage.

AGND 17 Analog Ground (Input) - Ground reference for the internal analog section.

FILT+ 18 Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-

cuits.

VQ 19 Quiescent Voltage (Output) - Filter connection for the internal quiescent voltage.

MICBIAS 20 Microphone Bias (Output) - Low noise bias supply for an external microphone. Electrical charac-

teristics are specified in the DC Electrical Characteristics table.

AIN4A,B

AIN3A,B 21,22

23,24 Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.

MIC1+,-

MIC2+,- 21,23

22,24 Differential Microphone Inputs (Input) - Differential stereo microphone inputs.

MIC2A,B

MIC1A,B 21,22

23,24 Single-Ended Microphone Inputs (Input) - Single-ended stereo microphone inputs.

AIN2A,B

AIN1A,B 25,26

29,30 Line-Level Analog Inputs (Input) - Single-ended stereo line-level analog inputs.

AFILTA,B 27,28 Anti-alias Filter Connection (Output) - Anti-alias filter connection for the ADC inputs.

SPKR/HP 31 Speaker/Headphone Switch (Input) - Powers down the left and/or right channel of the speaker

and/or headphone outputs.

RESET 32 Reset (Input) - The device enters a low power mode when this pin is driven low.

VL 33 Dig ital Interface Power (Input) - Determines the required signal level for the serial audio inter-

face and host control po rt .

VD 34 Digital Power (Input) - Positive power for the internal digital section.

DGND 35 Digital Ground (Input) - Ground reference for the internal digital section.

SDOUT 36 Serial Audio Data Output (Output) - Output for two’s complement serial audio data.

MCLK 37 Master Clock (Input) - Clock source for the delta-sigma modulator s.

SCLK 38 Serial Clock (Input/Output) - Serial cloc k for the serial audio interface.

SDIN 39 Serial Audio Data Input (Input) - Input for two’s complement serial audio data.

LRCK 40 Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on

the serial audio data line.

GND/Thermal Pad - Ground reference for PWM power FETs and charge pump; thermal relief pad for optimized heat

dissipation.

Power

Supply Pin Name I/O Internal

Connections Driver Receiver

RESET Input - - 1 .65 V - 3.47 V, with Hysteresis

SCL Input - - 1.65 V - 3.47 V, with Hysteresis

SDA Input/

Output - 1.65 V - 3.47 V, CMOS/Open

Drain 1.65 V - 3.47 V, with Hystere s is

MCLK Input - - 1.65 V - 3.47 V

LRCK Input/

Output Weak Pullup

(~1 MΩ)1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V

SCLK Input/

Output Weak Pullup

(~1 MΩ)1.65 V - 3.47 V, CMOS 1.65 V - 3.47 V

SDOUT Output Weak Pullup

(~1 MΩ)1.65 V - 3.47 V, CMOS

SDIN Input - - 1.65 V - 3.47 V

VA SPKR/HP Input - - 1.65 V - 2.63 V

SPKR_OUTA+ Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTA- Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTB+ Output - 1.6 V - 5.25 V Power MOSFET -

SPKR_OUTB- Output - 1.6 V - 5.25 V Power MOSFET -

10 DS680F1

CS42L52

5/13/08

2. TYPICAL CONNECTION DIAGRAM

Note 4

Note 3

Note 2

Note 1

1 µF

+1.8 V to +2.5 V 0.1 µF

1 µF

DGND

0.1 µF

+1. 8 V to + 3 .3 V

SCL

SDA

RESET

2 kΩ

LRCK

Digital Audio

Processor

MCLK

SCLK

MIC1-

AIN3A/MIC1A

Microphone 1

SDIN

SDOUT

CS42L52

2 kΩ

MICBIAS

+1.8 V to +2 .5 V

HP/LINE_OUTB

HP/LINE_OUTA

AIN1A Left 1

1800 pF

100 kΩ

100 Ω

AIN1B Right 1

0.1 µF

Headphone Out

Left & Right

Line Level Out

Left & Right

FLYP

FLYN

-VHPFILT

0.1 µF

51.1 Ω

0.022 µF

100 kΩ

100 Ω

SPKR_OUTA+

SPKR_OUTA-

SPKR/HP

51.1 Ω

0.022 µF

MIC1+

AIN4A/MIC2A

MIC2+

AIN4B/MIC2B

Microphone 2

MIC2-

AIN3B/MIC1B

100 kΩ

1 µF

0.1 µF

+VHP

1 µF

10 µF

AGND

* Capacitors must be C 0G or equivalent

150 pF

AFILTA

AFILTB

150 pF 1 µF

FILT+

1 µF

* *Use low E SR ceram ic capacitors.

See Note 5

SPKR_OUTB+

SPKR_OUTB-

1 µF VP

+1.6 V to

+5 V Stereo Speakers

AIN2A Left 2

1800 pF

100 kΩ

100 Ω

AIN2B Right 2

100 kΩ

100 Ω

1 µF

0.1 µF

Analog

Inp u t 1

Analog

Inp u t 2

10 µF

Mic-Level

Inputs

47 kΩ

Notes:

1. Recomme nded values for the default charge pump switching

frequency. The required capacitance follows an inverse

relationship with the charge pump’s switching frequency . When

increasing the switching frequency, the capacitance may

decrease; when lowe ring the switching frequency, the

capacitance must increase .

2. Larger capacitance reduces the ripple on the internal

amplifier’s supply. This may reduce the distortion at higher

output power levels.

3. Additional bulk capacitance may be added to improve P S R R

at low frequencies.

4. These capacitors serve as a charge reservoir for the internal

switched capacitor ADC mod ulators. They are on ly needed

when the PGA (Programmab le Gain Am plifier) is bypassed.

5. Series resistance in the path of the power supplies must be

avoided. Any voltage drop on VH P w ill directly impact the

negative charge pump supply (-VH P FILT) and clip the audio

output.

6. The value of RL, a current-limiting resistor used with electret

condenser microphones , is dictated by the microphone

cartridge.

7. The negative terminal of the MICx inputs connects to the

ground pin of the microphone cartridge. Gain is applied only to

the p o s itiv e te rminal.

Note 6

Note 7

Figure 1. Typical Connection Diagram

DS680F1 11

CS42L52

5/13/08

3. CHARACTERISTIC AND SPECIFICATIONS

RECOMMENDED OPERATING CONDITIONS

AGND=DGND=0 V, All voltages with respect to gr ound.

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V; All voltages with respect to ground.

WARNING:Operation at or beyo nd these limits may result in permanent damage to the device. Normal operation

is not guaranteed at these extremes.

Notes: 1. Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not cause

SCR latch-up.

2. The maximum over/unde r voltage is limited by the input current.

Parameters Symbol Min Max Units

DC Power Supply

Analog VA 1.65 2.63 V

Headphone Amplifier +VHP 1.65 2.63 V

Speaker Amplifier VP 1.60 5 .25 V

Digital VD 1.65 2.63 V

Serial/Control Port Interface VL 1.65 3.47 V

Ambient Temperature Commercial - CNZ

Automotive - DNZ TA-40

-40 +85

+105 °C

°C

Parameters Symbol Min Max Units

DC Power Supply Analog

Speaker

Digital

Serial/Control Port Interface

VA, VHP

-0.3

3.0

6.0

3.0

4.0

Input Current (Note 1) Iin -±10mA

External Voltage Applied to Analog Input (Note 2) VIN AGND-0.3 VA+0.3 V

External Voltage Applied to Analog Output VIN -VHP - 0.3 +VHP + 0.3 V

External Voltage Applied to Digital Input (Note 2) VIND -0.3 VL+ 0.3 V

Ambient Operating Temperature (power applied) TA-50 +115 °C

Storage Temperature Tstg -65 +150 °C

12 DS680F1

CS42L52

5/13/08

ANALOG INPUT CHARACTERISTICS (COMMERCIAL - CNZ)

Test Conditions (unless otherwise specified): Input sine wave (relative to digital full scale): 1 kHz through passive input filter; All

Supplies = VA; TA = +25°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise speci-

fied; “Required Initialization Settings” on page 37 written on power up.

3. Measured with DAC delivering full-scale output into specified load.

4. Measured between analog input and AGND.

VA = 2.5V VA = 1.8V

Parameters Min Typ Max Min Typ Max Unit

Analog In to ADC (PGA bypassed)

Dynamic Range A-weighted

unweighted 93

90 99

96 -

-90

87 96

93 -

-dB

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-86

-76

-36

-80

-30

-84

-73

-33

-78

-27

Analog In to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted 92

89 96

93 -

-89

86 95

92 -

-dB

PGA Setting: +12 dB A-weighted

unweighted 85

82 91

88 -

-82

79 88

85 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS

-60 dBFS -

--88

-33 -82

-27 -

--86

-32 -80

-26 dB

PGA Setting: +12 dB -1 dBFS - -85 -79 - -83 -77 dB

Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted -

-86

83 -

-83

80 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted -

-76

73 -

-74

71 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -2 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy

Interchannel Gain Misma tch - 0.2 - - 0.2 - dB

Gain Drift - ±100 - - ±100 - ppm/°C

Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB

Input

Interchannel Isolation - 90 - - 90 - dB

HP Amp to Analog Input Isolation RL = 10 kΩ

(Note 3) RL = 16 Ω

-100

70 -

-100

70 -

-dB

Sp eaker Amp to Analog Input Iso lation - 60 - - 60 - dB

Full-scale Input Voltage ADC

PGA (0 dB)

PGA (+12 dB)

MIC (+16 dB)

MIC (+32 dB)

0.73•VA

0.73•VA 0.769•VA

0.770•VA

0.194•VA

0.115•VA

0.019•VA

0.83•VA

0.83•VA 0.73•VA

0.73•VA 0.769•VA

0.770•VA

0.194•VA

0.115•VA

0.019•VA

0.83•VA

0.83•VA Vpp

Vpp

Input Impedance (Note 4) ADC

PGA

MIC

kΩ

DS680F1 13

CS42L52

5/13/08

ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) Test Conditions (unless

otherwise specified): Input sine wave (relative to full-scale ): 1 kHz through passive input filter; All Supplies = VA; TA = -40 to

+85°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz unless otherwise specified; “Required Initial-

ization Settings” on page 37 written on power up. VA = 2.37 - 2.63 V VA = 1.65 - 1.89 V

Parameters Min Typ Max Min Typ Max Unit

Analog In to ADC

Dynamic Range A-weighted

unweighted 91

88 99

96 -

-88

85 96

93 -

-dB

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-86

-76

-36

-78

-28

-84

-73

-33

-76

-25

Analog In to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted 90

87 96

93 -

-87

84 95

92 -

-dB

PGA Setting: +12 dB A-weighted

unweighted 83

80 91

88 -

-80

77 88

85 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS

-60 dBFS -

--88

-33 -80

-25 -

--86

-32 -78

-24 dB

PGA Setting: +12 dB -1 dBFS - -85 -77 - -83 -75 dB

Analog In to MIC Pre-Amp (+16 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted -

-86

83 -

-83

80 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -1 dBFS - -76 - - -74 - dB

Analog In to MIC Pre-Amp (+32 dB) to PGA to ADC

Dynamic Range

PGA Setting: 0 dB A-weighted

unweighted -

-76

73 -

-74

71 -

-dB

Total Harmonic Distortion + Noise

PGA Setting: 0 dB -2 dBFS - -74 - - -71 - dB

Other Characteristics

DC Accuracy

Interchannel Gain Mismatch - 0.1 - - 0.1 - dB

Gain Drift - ±100 - - ±100 - ppm/°C

Offset Error SDOUT Code with HPF On - 352 - - 352 - LSB

Input

Interchannel Isolation - 90 - - 9 0 - dB

HP Amp to Analog Input Isolation RL = 10 kΩ

(Note 3) RL = 16 Ω

-100

70 -

-100

70 -

-dB

Speaker Amp to Analog Input Isolation - 60 - - 60 - dB

Full-scale Input Vol tage ADC

PGA (0 dB)

PGA (+12 dB)

MIC (+16 dB)

MIC (+32 dB)

0.73•VA

0.769•VA

0.770•VA

0.194•VA

0.115•VA

0.019•VA

0.83•VA

0.73•VA

0.769•VA

0.770•VA

0.194•VA

0.115•VA

0.019•VA

0.83•VA

Vpp

Input Impedance (Note 4) ADC

PGA

MIC

kΩ

14 DS680F1

CS42L52

5/13/08

ADC DIGITAL FILTER CHARACTERISTICS

5. Response is clock-dependent and will scale with F s. Note that the response plots (Figures 26 to 29 on

page 78) have been normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.

HPF parameters are for Fs = 48 kHz.

Parameters (Note 5) Min Typ Max Unit

Passband (Frequency Response) to -0.1 dB corner 0 - 0.4948 Fs

Passband Ripple -0.09 - 0.17 dB

Stopband 0.6 - - Fs

Stopband Attenuation 33 - - dB

Total Group Delay -7.6/Fs- s

High-Pass Filter Characteristics (48 kHz Fs)

Frequency Response -3.0 dB

-0.13 dB -

-3.6

24.2 -

-Hz

Phase Deviation @ 20 Hz - 10 - Deg

Passband Ripple - - 0.17 dB

Filter Settling Time -10

5/Fs 0 s

DS680F1 15

CS42L52

5/13/08

ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ)

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = +25°C;

Sample Frequency = 48 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF for the line output

(see Figure 2); Test load RL = 16 Ω, CL = 10 pF (see Figure 2) for the headphone output; HP_GAIN[2:0] = 011; “Required Initial-

ization Settings” on page 37 written on power up.

6. One-half LSB of trian gular PDF dither is added to data.

7. Full-scale output voltage and power is determined by the gain setting, G, in register “Headphone Analog

Gain” on pa ge 51. High gain settings at certain VA and VHP supply levels may cause clipping when the

audio signal approaches full-scale, maximum power output, as shown in Figures 22 - 25 on page 75.

VA = 2.5 V VA = 1.8 V

Parameters (Note 6) Min Typ Max Min Typ Max Unit

RL = 10 k

Ω

Dynamic Range

18- to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-86

-75

-35

-86

-73

-33

-80

-29

-88

-72

-32

-88

-70

-30

-82

-26

RL = 16

Ω

Dynamic Range

18- to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-75

-35

-75

-73

-33

-69

-29

-75

-72

-32

-75

-70

-30

-69

-26

Other Characteristics for RL = 16

Ω

or 10 k

Ω

Output Parameters Modulation Index (MI)

(Note 7) Analog Gain Multiplier (G) -

-0.6787

0.6047 -

-0.6787

0.6047 -

Full-scale Output Voltage (2•G•MI•VA) (Note 7) Refer to Table “Line Output Voltage Level Characteris-

tics” on page 20 Vpp

Full-scale Output Power (Note 7) Refer to Table “Headphone Output Power Characteristics” on

page 19

Interchannel Isolation (1 kHz) 16 Ω

10 kΩ

-80

95 -

-80

93 -

-dB

Speaker Amp to HP Amp Isolation - 80 - - 80 - dB

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB

Gain Drift - ±100 - - ±100 - ppm/°C

AC Load Resistance (RL)(Note 8) 16 - - 16 - - Ω

Load Capacitance (CL)(Note 8) - - 150 - - 150 pF

16 DS680F1

CS42L52

5/13/08

ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ)

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; All Supplies = VA; TA = -40 to

+85°C; Sample Frequency = 48 kHz and 96 kHz; Measurement bandwidth is 20 Hz to 20 kHz; Test load RL = 10 kΩ, CL = 10 pF

for the line output (see Figure 2); Test load RL = 16 Ω, CL =10pF (see Figure 2) for the headphone ou tput;

HPGAIN[2:0] = 011. “Required Initialization Settings” on page 37 written on power up.

8. See Figure 2. RL and CL reflect the recommended minimum resistance and maximum capacitance re-

quired for the internal op-amp's stability and signal integrity. In this circuit topology, CL will effectively

move the band-limiting pole of the amp in the output stage. Increasing this value beyond the recom-

mended 150 pF can cause the internal op-amp to become unstable.

VA = 2.37 - 2.63 V VA = 1.65 - 1.89 V

Parameters (Note 6) Min Typ Max Min Typ Max Unit

RL = 10 k

Ω

Dynamic Range

18- to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-86

-75

-35

-86

-73

-33

-78

-27

-88

-72

-32

-88

-70

-30

-80

-24

RL = 16

Ω

Dynamic Range

18- to 24-Bit A-weighted

unweighted

16-Bit A-weighted

unweighted

Total Harmonic Distortion + Noise

18- to 24-Bit 0 dB

-20 dB

-60 dB

16-Bit 0 dB

-20 dB

-60 dB

-75

-35

-75

-73

-33

-67

-27

-75

-72

-32

-75

-70

-30

-67

-24

Other Characteristics for RL = 16

Ω

or 10 k

Ω

Output Parameters Modulation Index (MI)

(Note 7) Analog Gain Multiplier (G) -

-0.6787

0.6047 -

-0.6787

0.6047 -

Full-scale Output Voltage (2•G•MI•VA) (Note 7) Refer to the table in “Line Output Voltage Level Charac-

teristics” on page 20 Vpp

Full-scale Output Power (Note 7) Refer to the table in “Headphone Output Power Characteristics” on

page 19

Interchannel Isolation (1 kHz) 16 Ω

10 kΩ

-80

95 -

-80

93 -

-dB

Speaker Amp to HP Amp Isolation - 80 - - 80 - dB

Interchannel Gain Mismatch - 0.1 0.25 - 0.1 0.25 dB

Gain Drift - ±100 - - ±100 - ppm/°C

AC Load Resistance (RL)(Note 8) 16 - - 16 - - Ω

Load Capacitance (CL)(Note 8) - - 150 - - 150 pF

DS680F1 17

CS42L52

5/13/08

ANALOG PASSTHROUGH CHARACTERISTICS

Test Conditions (unless otherwise specified): Input sine wave (relative to full-scale): 1 kHz through passive input filter; PGA and

HP/Line Gain = 0 dB; All Supplies = VA; T A = +25°C; Sample Frequency = 48 kHz; Measurement Bandwidth is 20 Hz to 20 kHz;

“Required Initialization Settings” on page 37 written on power up.

PWM OUTPUT CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full scale 997 Hz signal; MCLK = 12.2880 MHz; Measurement

Bandwidth is 20 Hz to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 8 Ω for stereo full-bridge, RL = 4 Ω for mono parallel

full-bridge; VD = VL = VA = VHP = 1.8V; PWM Modulation Index of 0.85; PWM Switch Rate = 384 kHz; “Required Initialization

Settings” on page 37 written on power up. (Note 9)

VA = 2.5 V VA = 1.8 V

Parameters Min Typ Max Min Typ Max Unit

Analog In to HP/Line Amp (ADC is powered down)

RL = 10 k

Ω

Dynamic Range A-weighted

unweighted -

--96

-93 -

--94

-91 -

-dB

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-70

-73

-33

-70

-71

-31

Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp

Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp

Passband Ripple - 0/-0.3 - - 0/-0.3 - dB

RL = 16

Ω

Dynamic Range A-weighted

unweighted -

--96

-93 -

--94

-91 -

-dB

Total Harmonic Distortion + Noise -1 dBFS

-20 dBFS

-60 dBFS

-70

-73

-33

-70

-71

-31

Full-scale Input Voltage - 0.91•VA - - 0.91•VA - Vpp

Full-scale Output Voltage - 0.84•VA - - 0.84•VA - Vpp

Output Power - 32 - - 17 - mW

Passband Ripple - 0/-0.3 - - 0/-0.3 - dB

Parameters (Note 10) Symbol Conditions Min Typ Max Units

VP = 5.0 V

Power Output per Channel PO

Stereo Full-Bridge THD+N < 10%

THD+N < 1% -

-1.00

0.80 -

-Wrms

Wrms

Mono Parallel Full-Bridge THD+N < 10%

THD+N < 1% -

-1.90

1.50 -

-Wrms

Wrms

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge PO = 0 dBFS = 0.8W - 0.52 - %

Mono Parallel Full-Bridge PO = -3 dBFS = 0.75 W

PO = 0 dBFS = 1.5 W -

-0.10

0.50 -

Dynamic Range DR

Stereo Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-91

88 -

-dB

Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-91

88 -

-dB

18 DS680F1

CS42L52

5/13/08

9. The PWM driver should be used in captive speaker systems only.

10. Optimal PWM performance is achieved when MCLK > 12 MHz.

VP = 3.7 V

Power Output per Channel PO

Stereo Full-Bridge THD+N < 10%

THD+N < 1% -

-0.55

0.45 -

-Wrms

Wrms

Mono Parallel Full-Bridge THD+N < 10%

THD+N < 1% -

-1.00

0.84 -

-Wrms

Wrms

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge PO = 0 dBFS = 0.43 W - 0.54 - %

Mono Parallel Full-Bridge PO = -3 dBFS = 0.41 W

PO = 0 d BFS = 0.81 W -

-0.09

0.45 -

Dynamic Range DR

Stereo Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-91

88 -

-dB

Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-95

92 -

-dB

VP =2.5 V

Power Output per Channel PO

Stereo Full-Bridge THD+N < 10%

THD+N < 1% -

-0.23

0.19 -

-Wrms

Wrms

Mono Parallel Full-Bridge THD+N < 10%

THD+N < 1% -

-0.44

0.35 -

-Wrms

Wrms

Total Harmonic Distortion + Noise THD+N

Stereo Full-Bridge PO = 0 dBFS = 0.18 W - 0.50 - %

Mono Parallel Full-Bridge PO = -3 dBFS = 0.17 W

PO = 0 d BFS = 0.35 W -

-0.08

0.43 -

Dynamic Range DR

Stereo Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-91

88 -

-dB

Mono Parallel Full-Bridge PO = -60 dBFS, A-Weighted

PO = -60 dBFS, Unweighted -

-94

91 -

-dB

MOSFET On Resistance RDS(ON) VP = 5.0V, Id = 0.5 A - 600 - mΩ

MOSFET On Resistance RDS(ON) VP = 3.7V, Id = 0.5 A - 640 - mΩ

MOSFET On Resistance RDS(ON) VP = 2.5V, Id = 0.5 A - 760 - mΩ

Efficiency ηVP = 5.0 V, PO = 2 x 0.8 W, RL = 8 Ω-81-%

Output Operating Peak Current IPC --1.5A

VP Input Current During Reset IVP RESET, pin 32, is held low -0.85.0µA

Parameters (Note 10) Symbol Conditions Min Typ Max Units

DS680F1 19

CS42L52

5/13/08

HEADPHONE OUTPUT POWER CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; Sample Fr equency = 48 kHz;

Measurement Bandwidth is 20 Hz to 20 kHz; Test load RL = 16 Ω, CL = 10 pF (see Figure 2); “Required Initi alization Settings”

on page 37 written on power up.

11. VHP settings lower than VA reduces the headroom of the headphone amplifier. As a result, the DAC

may not achieve the full THD+N performance at full-scale output voltage and power.

Parameters VA = 2.5V

Min Typ Max VA = 1.8V

Min Typ Max Unit

AOUTx Power Into RL = 16

Ω

HP_GAIN[2:0] Analog

Gain (G) VHP

000 0.3959 1.8 V - 14 - - 7 - mWrms

2.5 V - 14 - - 7 - mWrms

001 0.4571 1.8 V - 19 - - 10 - mWrms

2.5 V - 19 - - 10 - mWrms

010 0.5111 1.8 V - 23 - - 12 - mWrms

2.5 V - 23 - - 12 - mWrms

011 (default) 0.6047 1.8 V (Note 11) -17 -mW

rms

2.5 V - 32 - - 17 - mWrms

100 0.7099 1.8 V (Note 11) -23 -mW

rms

2.5 V - 44 - - 23 - mWrms

101 0.8399 1.8 V (Note 7), Figure 22 on page 74 mWrms

2.5 V -32 -mW

rms

110 1.0000 1.8 V (Note 7, 11) See Figures 22 and 23 on page 74 mWrms

2.5 V mWrms

111 1.1430 1.8 V mWrms

2.5 V mWrms

AOUTx

AGND

0.022 µF

51 Ω

Figure 2. Headphone Output Test Load

20 DS680F1

CS42L52

5/13/08

LINE OUTPUT VOLTAGE LEVEL CHARACTERISTICS

Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth is 20 Hz

to 20 kHz; Sample Frequency = 48 kHz; Test load RL = 10 kΩ, CL = 10 pF (see Figure 2); “Required Initialization Setting s” on

page 37 written on power up.

COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE

12. Response is clock dependent and will scale with Fs. Note th at the r esponse plots (Figures 30 and 33 on

page 78) have been normalized to Fs and can be de-nor malized by multiplying the X-axis scale by Fs.

13. Measurement Bandwidth is from Stopband to 3 Fs.

Parameters VA = 2.5V

Min Typ Max VA = 1.8V

Min Typ Max Unit

AOUTx Voltage Into RL = 10 k

Ω

HP_GAIN[2:0] Analog

Gain (G) VHP

000 0.3959 1.8 V - 1.34 - - 0.97 - Vpp

2.5 V - 1.34 - - 0.97 - Vpp

001 0.4571 1.8 V - 1.55 - - 1.12 - Vpp

2.5 V - 1.55 - - 1.12 - Vpp

010 0.5111 1.8 V - 1.73 - - 1.25 - Vpp

2.5 V - 1.73 - - 1.25 - Vpp

011 (default) 0.6047 1.8 V - 2.05 - 1.41 1.48 1.55 Vpp

2.5 V 1.95 2.05 2.15 - 1.48 - Vpp

100 0.7099 1.8 V - 2.41 - - 1.73 - Vpp

2.5 V - 2.41 - - 1.73 - Vpp

101 0.8399 1.8 V - 2.85 - 2.05 Vpp

2.5 V - 2.85 - - 2.05 - Vpp

110 1.0000 1.8 V - 3.39 - - 2.44 - Vpp

2.5 V - 3.39 - - 2.44 - Vpp

111 1.1430 1.8 V (See (Note 11) -2.79-V

2.5 V - 3.88 - - 2.79 - Vpp

Parameters (Note 12) Min Typ Max Unit

Frequency Response 10 Hz to 20 kHz -0.01 - +0.08 dB

Passband to -0.05 dB corner

to -3 dB corner 0

-0.4780

0.4996 Fs

StopBand 0.5465 - - Fs

St opBand Attenuation (Note 13) 50 - - dB

Group Delay - 9/Fs - s

De-emphasis Error Fs = 32 kHz

Fs = 44.1 kHz

Fs = 48 kHz

+1.5/+0

+0.05/-0.25

-0.2/-0.4

DS680F1 21

CS42L52

5/13/08

SWITCHING SPECIFICATIONS - SERIAL PORT

Inputs: Logic 0 = DGND, Logic 1 = VL, SDOUT CLOAD = 15 pF.

14. After powering up the CS42L52, RESET should be held low after the power supplies and clocks are

settled.

15. See “Example System Clock Frequen cies” on page 76 for typical MCLK frequencies.

Parameters Symbol Min Max Units

RESET pin Low Pulse Width (Note 14) 1-ms

MCLK Frequency (Note 15) (See “Serial Port Clock-

ing” on page 34)MHz

MCLK Duty Cycle 45 55 %

Slave Mode

Input Sample Rate (LRCK) Fs(See “Serial Port Clock-

ing” on page 34)kHz

LRCK Duty Cycle 45 55 %

SCLK Frequency 1/tP- 64•FsHz

SCLK Duty Cycle 45 55 %

LRCK Setup Time Before SCLK Rising Edge ts(LK-SK) 40 - ns

LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns

SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns

SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns

SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns

SDIN Hold Time After SCLK Rising Edge th20 - ns

Master Mode

Output Sample Rate (LRCK) All Sp eed Modes Fs(See “Serial Port Clock-

ing” on page 34)Hz

LRCK Duty Cycle 45 55 %

SCLK Frequency SCLK=MCLK mode 1/tP- 12.0000 MHz

MCLK=12.0000 MHz 1/tP- 68•FsHz

all other modes 1/tP- 64•FsHz

SCLK Duty Cycle 45 55 %

LRCK Edge to SDOUT MSB Output Delay td(MSB) -52ns

SDOUT Setup Time Before SCLK Rising Edge ts(SDO-SK) 20 - ns

SDOUT Hold Time After SCLK Rising Edge th(SK-SDO) 30 - ns

SDIN Setup Time Before SCLK Rising Edge ts(SD-SK) 20 - ns

SDIN Hold Time After SCLK Rising Edge th20 - ns

th(SK-SDO)

ts(SD-SK)

MSB

MSB-1

LRCK

SCLK

SDOUT

SDIN

td(MSB)

ts(LK-SK) tP

ts(SDO-SK)

Figure 3. Serial Audio Interface Timing

22 DS680F1

CS42L52

5/13/08

SWITCHING SPECIFICATIONS - I²C CONTROL PORT

Inputs: Logic 0 = DGND, Logic 1 = VL, SDA CL=30pF.

16. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.

Parameters Symbol Min Max Unit

SCL Clock Frequency fscl - 100 kHz

RESET Rising Edge to Start tirs 550 - ns

Bus Free Time Between Transmissions tbuf 4.7 - µs

Start Condition Hold Time (prior to first clock pulse) thdst 4.0 - µs

Clock Low time tlow 4.7 - µs

Clock High Time thigh 4.0 - µs

Setup Time for Repeated Start Condition tsust 4.7 - µs

SDA Hold Time from SCL Falling (Note 16) thdd 0-µs

SDA Setup time to SCL Rising tsud 250 - ns

Rise Time of SCL and SDA trc -1µs

Fall T ime SCL and SDA tfc - 300 ns

Setup Time for Stop Condition tsusp 4.7 - µs

Acknowledge Delay from SCL Fallin g tack 300 1000 ns

tbuf thdst thdst

tlow tr

thdd

thigh

tsud tsust

tsusp

Stop Start Start Stop

Repeated

SDA

SCL

tirs

RST

Figure 4. Control Port Timing - I²C

DS680F1 23

CS42L52

5/13/08

DC ELECTRICAL CHARACTERISTICS

AGND = 0 V; All voltages with respect to ground.

17. Valid with the recommended capacitor values on FILT+ and VQ. Increasing the c apacitance will also

increase the PSRR.

18. The PGA is biased with VQ, created from a resistor divider from the VA supply. Increasing the capaci-

tance on VQ will also increase the PSRR at low frequencies. A 10 µF capacitor on VQ improves the

PSRR to 42 dB.

DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS

19. See “I/O Pin Character istic s” on pa ge 9 for serial and control port power rails.

Parameters Min Typ Max Units

VQ Characteristics

Nominal Voltage

Output Impedance

DC Current Source/Sink

0.5•VA

kΩ

µA

MIC BIAS Characteristics

Nominal Voltage BIASLVL[2:0] = 000

BIASLVL[2:0] = 001

BIASLVL[2:0] = 010

BIASLVL[2:0] = 011

BIASLVL[2:0] = 100

BIASLVL[2:0] = 101

DC Output Current

Power Supply Rejection Ratio (PSRR) 1 kHz

0.5•VA

0.6•VA

0.7•VA

0.8•VA

0.83•VA

0.91•VA

Power Supply Rejection Ratio Characteristics

PSRR @1 kHz (Note 17) PGA to ADC

ADC

DAC (HP & Line Amps)

PSRR @60 Hz (Note 17) PGA to ADC(Note 18)

ADC

DAC (HP & Line Amps)

PSRR @217 Hz Full-Bridge PWM Outputs - 56 - dB

Parameters (Note 19) Symbol Min Max Units

Input Leakage Current Iin -±10µA

Input Capacitance -10pF

1.8 V - 3.3 V Logic

High-Level Output Voltage (IOH = -100 µA) VOH VL - 0.2 - V

Low-Level Output Voltage (IOL = 100 µA) VOL -0.2V

High-Level Input Voltage VL = 1.65 V

VL = 1.8 V

VL = 2.0 V

VL > 2.0 V

VIH

0.85•VL

0.76•VL

0.68•VL

0.65•VL

Low-Level Input Voltage VIL -0.30•VLV

24 DS680F1

CS42L52

5/13/08

POWER CONSUMPTION See (Note 20).

20. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample

rate = 48 kHz; No load. Digital (VD) and logic (VL) supply current w ill vary depending on speed mode

and master/slave operation. “Required Initialization Settings” on page 37 written on power up.

21. RESET pin 25 held LO, all clocks and data lines are held LO.

22. RESET pin 25 held HI, all clocks and data lines are held HI.

23. VL current will slightly increase in master mode.

Power Ctl. Registers Typical Current (mA)

Operation 02h 03h 04h

PDN_PGAB

PDN_PGAA

PDN_ADCB

PDN_ADCA

PDN

PDN_MICB

PDN_MICA

PDN_MICBIAS

PDN_HPB[1:0]

PDN_HPA[1:0]

PDN_SPKB[1:0]

PDN_SPKA[1:0]

iVHP iVA iVD iVL

VL=3.3V

(Note 23)

iVP

VP=3.7V Total

Power

(mWrms)

1Off (Note 21) xxxxxxxxx x x x 1.8 0.00 0.00 0.00 0.00 0.00 0.00

2.5 0.00 0.00 0.00 0.00

2Standby (Note 22) xxxx1xxxx x x x 1.8 0.00 0.00 0.01 0.00 0.00 0.02

2.5 0.00 0.00 0.02 0.05

3Mono Record ADC11100111111111111.8 0.00 1.67 2.32 0.03 0.00 7.24

2.5 0.00 1.87 3.72 14.05

PGA to ADC10100111111111111.8 0.00 2.1 2.31 0.03 0.00 7.99

2.5 0.00 2.3 3.72 15.13

MIC to PGA to ADC

(with Bias) 10100100111111111.8 0.00 3.48 2.32 0.03 0.00 10.49

2.5 0.00 3.71 3.72 18.65

MIC to PGA to ADC

(no Bias) 10100101111111111.8 0.00 3.15 2.32 0.03 0.00 9.90

2.5 0.00 3.37 3.73 17.83

4Stereo Record ADC11000111111111111.8 0.00 2.31 2.37 0.03 0.00 8.48

2.5 0.00 2.53 3.82 15.95

PGA to ADC00000111111111111.8 0.00 3.18 2.37 0.03 0.00 10.04

2.5 0.00 3.42 3.81 18.15

MIC to PGA to ADC

(no Bias) 00000001111111111.8 0.00 5.32 2.37 0.03 0.00 13.90

2.5 0.00 5.57 3.81 23.53

5Mono Playback to Headphone 11110111101111111.8 1.59 1.99 2.72 0.01 0.00 11.36

2.5 2.07 2.62 4.27 22.43

6 Mono Playback to Speaker 11110111111110101.8 0.00 0.20 4.42 0.01 1.00 12.05

2.5 0.00 0.22 6.77 21.21

7 Stereo Playback to Headphone 11110111101011111.8 2.77 2.00 2.91 0.01 0.00 13.84

2.5 3.27 2.63 4.28 25.48

8Stereo Playback to Speaker 11110111111110101.8 0.00 0.20 4.38 0.01 1.00 11.98

2.5 0.00 0.22 6.80 21.28

9Stereo Passthrough to Head-

phone 11110111101011111.8 2.79 1.91 1.06 0.01 0.00 10.39

2.5 3.18 2.14 1.81 17.85

10 Mono Record & Playback

PGA in (no MIC) to Mono HP 10100111111011111.8 1.77 3.95 4.28 0.03 0.00 18.05

2.5 2.13 4.77 6.63 33.90

11 Phone Monitor

MIC (w/bias) in to Mono Out 10100100111011111.8 1.76 5.33 4.28 0.03 0.00 20.52

2.5 2.15 6.19 6.69 37.65

12 Stereo Record & Playback

PGA in (no MIC) to St. HP Out 00000111101011111.8 2.76 5.05 4.64 0.03 0.00 22.46

2.5 3.21 5.90 7.17 40.78

13 Stereo Rec. & Full Playback

PGA (no MIC) to St. HP & SPK 00000111101010101.8 3.49 5.24 7.20 0.03 1.00 32.47

2.5 3.95 6.10 10.46 55.07

DS680F1 25

CS42L52

5/13/08

4. APPLICATIONS

4.1 Overview

4.1.1 Basic Architecture

The CS42L52 is a highly integrated, low-power, 24-bit audio CODEC comprised of a stereo analog-to-

digital converte r (ADC), a stereo digital-to-analog converter ( DAC), a digital PWM modulator and two full-

bridge power back-ends. The ADC and DAC are designed using multi-bit delta-sigma techniques - the

DAC operates at an oversampling ratio of 128Fs and the ADC operates at 64Fs, where Fs is e qual to the

system sample rate.

The different clock rates maximize power savings while maintaining high performance. The PWM modu-

lator operates at a fixed frequency of 384 kHz. The power FETs are configured for either ster eo full-bridge

or mono parallel full-brid ge output. The CODEC oper ates in one of four sample r ate speed modes: Quar-

ter, Half, Single, and Doub le. It accepts and is capabl e of generatin g serial port clocks (SCLK, LRCK) de-

rived from an input Master Clo ck (M CLK).

4.1.2 Line & MIC Inputs

The analog input portion of the CODEC allows selection from and configuration of multiple combinations

of stereo and microphone (MIC) sources. Eight line inputs with an option for two balanced MIC inputs, a

MIC bias output, and a Programmable Gain Amplifier (PGA) comprise the analog front-end.

4.1.3 Line & Headphone Outputs

The analog output portion of the CODEC includes a headphone amplifier capable of driving headphone

and line-level loads. An on-chip charge pump creates a negative headphone supply allowing a full-scale

output swing centered around ground. This eliminates the need for large DC-Blocking capacitors and al-

lows the amplifier to deliver more power to headphone loads at lower supply voltages.

4.1.4 Speaker Driver Outputs

The Class D power amp lifiers drive 8 ohm (stere o) and 4 ohm ( mono) speakers dir ectly, without the need

for an external filter. The power MOSFETS are powered directly from a battery eliminating the efficiency

loss associated with an external regulator. Batter y level monitoring and compensation mainta ins a steady

output as battery levels fall. NOTE: The CS42L52 should only be used in captive speaker systems where

the outputs are permanently tied to the speaker terminals.

4.1.5 Fixed Function DSP Engine

The fixed-function digital signal processing engine processes both the PCM serial input data and ADC

output data, allowing a mix between the two. Independent vol ume control, left/right channel swaps, mono

mixes, tone control, and limiting functions also comprise the DSP engine.

4.1.6 Beep Generator

The beep generator delivers tones at select frequencies across approxim ately two o ctave major scales.

With independent volume control, beeps may be configure d to occur con tinuou sly, per iodi cally, or at sin-

gle time intervals.

4.1.7 Power Management

Three control registers provide independent power-down control of the ADC, DAC, PGA, MIC pre-amp,

MIC bias, Headphone, a nd Speaker outputs, allowing op eration in select applications with minimal power

consumption.

26 DS680F1

CS42L52

5/13/08

4.2 Analog Inputs

Referenced Control Register Location

Analog Front End

PDN_PGAx .........................

PGAxVOL[5:0].....................

ADCB=A..............................

ANLGSFTx..........................

ANLGZCx............................

ADCxSEL[2:0].....................

PGAxSEL5,4,3,2,1..............

BIASLVL[2:0].......................

PDN_BIAS...........................

PDN_ADCx .........................

PDN_CHRG........................

INV_ADCx...........................

HPFRZx...............................

HPFx ...................................

HPFx_CF[1:0]......................

ADCxOVFL..........................

Digital Volume

ADCxMUTE.........................

ADCxVOL............................

ALCx....................................

ALCxSRDIS.........................

ALCxZCDIS.........................

ALCARATE[5:0]...................

ALCRRATE[5:0] ..................

MAX[2:0]..............................

MIN[2:0]...............................

NGALL.................................

NG.......................................

THRESH[3:0].......................

NGDELAY[1:0] ....................

Miscellaneous

DIGSUM[1:0].......................

DIGMUX..............................

“Power Down PGAx” on page 42

“PGAx Volume” on page 56

“Analog Front-End Volume Setting B=A” on page 50

“Ch. x Analog Soft Ramp” on page 49

“Ch. x Analog Zero Cross” on page 49

“ADC Input Select” on page 48

“PGA Input Mapping” on page 49

“MIC Bias Level” on page 48

“Power Down MIC Bias” on page 43

“Power Down ADCx” on page 43

“Power Down ADC Charge Pump” on page 42

“Invert ADC Signal Polarity” on page 51

“ADCx High-Pass Filter Freeze” on page 49

“ADCx High-Pass Filter” on page 49

“HPF x Corner Frequency” on page 50

“ADCx Overflow (Read Only)” on page 71

“ADC Mute” on page 51

“ADCx Volume” on page 57

“ALCx Enable” on page 67

“ALCx Soft Ramp Disable” on page 55

“ALCx Zero Cross Disable” on page 56

“ALC Attack Rate” on page 67

“ALC Release Rate” on page 68

“ALC Maximum Threshold” on page 68

“ALC Minimum Threshold” on page 69

“Noise Gate All Channels” on page 69

“Noise Gate Enable” on page 69

“Noise Gate Threshold and Boost” on page 70

“Noise Gate Delay Timing” on page 70

“Digital Sum” on page 50

“Digital MUX” on page 50

AIN4A/ MIC1+/

MIC2A

G ain A d jus t

ALC

PDN_PGAA

PGAAVOL[5:0]

ADCB=A

ANLGSFTA

ANLGZCA

HPFRZA

HPFA

HPFA_CF[1:0]

PDN_ADCA

INV_ADCA

PDN_CHRG

ALCB

ALCBSRDIS

ALCBZCDIS

MICBIAS

BIASLVL[2:0]

PDN_BIAS

PCM Serial Interface

TO D SP Engine

ALCARATE[5:0]

ALCRRATE[5:0]

MAX[2:0]

MIN[2:0]

ALCA

ALCASRDIS

ALCAZCDIS

AIN1A

AIN2A

= PGAASEL [5:1]

ADC

PDN_PGAB

PGABVOL[5:0]

ADCB=A

ANLGSFTB

ANLGZCB

ADCBMUTE

DIGSFT

DIGZC

ADCBVOL[7:0]

+24/-96dB

1dB steps

HPFRZB

HPB

HPFB_CF[1:0]

PDN_ADCB

INV_ADCB

PDN_CHRG

Noise Gate NGALL

THRESH[3:0]

NGDELAY[1:0]

Gain Adjust

FROM DSP ENGINE

DIGMIX

AIN3A/MIC1-/

MIC1A

AIN4B/ MIC2+/

MIC2B

AIN1B

AIN2B

AIN3B/MIC2-/

MIC1B

ANALOG P ASS THRU TO

HEADPH ON E AM PLIFIER MUX

Swap/

Mix

DIGSUM[1:0]

ADCAMUTE

DIGSFT

DIGZC

ADCAVOL[7:0]

+24/-96dB

1dB steps

Re fe r to

“M IC Inp u ts ”

ADC

ADCASEL[2:0]

ADCBSEL[2:0]

= PGABSEL [5:1]

Re fe r to

“M IC Inp u ts ”

Figure 5. Analog Input Signal Flow

DS680F1 27

CS42L52

5/13/08

4.2.1 MIC Inputs

The input pins 21, 22, 23, and 24 accept stereo line-level or microphone signals. For microphone inputs,

either single-ended or differential configuration is allowed, providing programmable pre-amplification of

low-level signals. In the single-ended configur ation, an interna l MUX chooses one of two stereo sets (se-

lection is made independently on channels A and B). In the differential configuration, an internal voltage

follower cascaded with the pre-amplifier maintains high input impedance and provides noise rejection

above the MICxGAIN setting. The pre-amps are biased to VQ in both configurations.

4.2.2 Automatic Level Control (ALC)

When enabled, the ALC monitors the analog input signal after the digital attenuator, detects when peak

levels exceed the maximum (MAX) threshold settings, and responds by applying attenuation as neces-

sary to maintain the resulting level below the MAX threshold. To apply this attenuation, the ALC first low-

ers the PGA gain settings and then incr ease s the dig ita l attenuation levels. All attenuation is applied at a

programmable attack rate.

When input signal levels fall below the mini mum (M IN) threshold, the ALC responds by removing any at-

tenuation that it has previously applied until all ALC-applied attenuation has been removed or until the

MAX threshold is again crossed. To remove this attenuation, the ALC first decreases the digital attenua-

tion levels and then increases the PGA gain. All attenuation is removed at a programmable release rate.

It should be noted that the ALC is applied independently to channels A and B with one exception: the input

signals on both channels A and B must be below the MIN threshold in order for the ALC attenuation to be

released on channel B.

Attack and release rates are affected by the ADC soft -ramp/zero-cross settings and sample rate, Fs. ALC

soft-ramp and zero-cross dependency may be independently enabled/disabled.

Recommended settings: Best level control may be realized with the fastest attack and slowest release

setting with soft ramp enabled in the control registers.

Notes:

1. When ALC x is enabled and the PGAxVOL[5:0] is set above 12 dB, the ADCxVOL[7:0] should not be

set below 0 dB.

2. The maximum realized gain must be set in the PGAxVOL register. The ALC will only apply the gain

set in the PGAxVOL.

3. The ALC maintains the output signal between the MIN and MAX thresh olds. As the input signal leve l

Referenced Control Register Location

MICxCFG............................

PDN_MICx..........................

MICxGAIN...........................

“MICx Configuration” on page 55

“Power Down MICx” on page 43

“MICx Gain” on page 55

MIC1- -

MIC1+

MIC2- -

MIC2+

MICACFG=’1'b

MICBCFG=’1'b

MICAGAIN[4:0]

MICBGAIN[4:0]

16..32 dB/

1 dB steps

16..32 dB/

1 dB steps

PDN_MICA=’0'b

PDN_MICB=’0'b

to summ ing

PGA A

Note: Outp ut to P G A = (M I C + - MI C-)*gain + MIC -

to summ ing

PGA B

MIC1A -

MIC2A

MIC1B -

MIC2B

MICACFG=’0'b

MICBCFG=’0'b

MICAGAIN[4:0]

MICBGAIN[4:0]

16..32 dB/

1 dB steps

16..32 dB/

1 dB steps

PDN_MICA=’0'b

PDN_MICB=’0'b

MICASEL

MICBSEL

to summing

PGA A

to summing

PGA B

Figure 6. Single-Ended MIC Configuration Figure 7. Differential MIC Configuration

28 DS680F1

CS42L52

5/13/08

changes, the level-controlled output may not always be the same but will always fall within the

thresholds.

4.2.3 Noise Gate

The noise gate may be used to mute signal levels that fall below a programmable threshold. This prevents

the ALC from applying gain to noise. A programmable delay may be used to set the minimum time before

the noise gate attacks the signal.

Note: Maximum noise gate attenuation levels will depend on the gain applied in either the PGA or MIC

pre-amplifier. For example: If both +32 dB pre-amplification and +12 dB prog rammable gain is applied,

the maximum attenuation that the noise gate achieves will be 52 dB (-96 + 32 + 12) below full-scale.

Referenced Control Register Location

PGAxVOL[5:0

MAX[2:0], MIN[2:0] “PGAx Vol. & ALCx Transition Ctl.: ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)” on page 55

“ALC Threshold (Address 2Ch)” on page 68

Referenced Con t rol Register Location

Noise Gate Controls............ “Noise Gate Control (Address 2Dh)” on page 69

Output

(afte r A L C)

Input (before ALC )

RRATE[5:0]

PG A G ain and/or

Attenuator

ALC

Response

MAX[2:0]

ARATE[5:0

]

be lo w full s c a le

MIN[2:0]

below full scale

MIN[2:0]

b e lo w fu ll s c ale

MAX[2:0]

b e lo w fu ll s c ale

Figure 8. ALC

-96 -40

THRESH[2:0]

Maximum Attenuation*

-52 dB

Output

(dB)

Input (dB)

NGEN=1

NGEN=0

-80 dB

-64 dB

Figure 9. Noise Gate Attenuation

DS680F1 29

CS42L52

5/13/08

4.3 Analog Outputs

Referenced Control Register Location

DSP

DEEMPH.............................

PMIXxMUTE........................

PMIXxVOL[6:0]....................

INV_PCMx...........................

PCMxSWAP[1:0].................

AMIXxMUTE........................

AMIXxVOL[6:0]....................

ADCxSWAP[1:0]..................

MSTxVOL[7:0].....................

MSTxMUTE.........................

DIGSFT...............................

DIGZC.................................

PLYBCKB=A........................

TC_EN.................................

BASS_CF[1:0].....................

TREB_CF[1:0].....................

BASS[3:0]............................

TREB[3:0]............................

LIMIT...................................

LIMSRDIS ...........................

LIMZCDIS............................

LMAX[2:0]............................

CUSH[2:0]...........................

LIMARATE[7:0]....................

LIMRRATE[7:0] ...................

“HP/Speaker De-emphasis” on page 53

“PCM Mixer Channel x Mute” on page 58

“PCM Mixer Channel x Volume” on page 58

“Invert PCM Signal Polarity” on page 52

“PCM Mix Channel Swap” on page 64

“ADC Mixer Channel x Mute” on page 58

“ADC Mixer Channel x Volume” on page 58

“ADC Mix Channel Swap” on page 64

“Master Volume Control” on page 63

“Master Playback Mute” on page 52

“Digital Soft Ramp” on page 53

“Digital Zero Cross” on page 53

“Playback Volume Setting B=A” on page 51

“Tone Control Enable” on page 62

“Bass Corner Frequency” on page 62

“Treble Corner Frequency” on page 62

“Bass Gain” on page 63

“Treble Gain” on page 62

“Peak Detect and Limiter” on page 66

“Limiter Soft Ramp Disable” on page 65

“Limiter Zero Cross Disable” on page 66

“Limiter Maximum Threshold” on page 65

“Limiter Cushion Threshold” on page 65

“Limiter Attack Rate” on page 67

“Limiter Release Rate” on page 66

Beep

Generator

VOL

ΣBass/

Treble/

Control

ΣVOL

Peak

Detect

Limiter

Chnl Vol.

Settings

Channel

Swap

Demph VOL

VOL

+12dB/-102dB

0.5dB steps

MSTAVOL[7:0]

MSTBVOL[7:0]

+12dB/-51.5dB

0.5dB steps

AMIXAMUTE

AMIXBMUTE

AMIXAVOL[6:0]

AMIXBVOL[6:0]

+12dB/-51.5dB

0.5dB steps

PMIXAMUTE

PMIXBMUTE

PMIXAVOL[6:0]

PMIXBVOL[6:0]

0dB/-50dB

2.0dB steps

BPVOL[4:0]

DEEMPH TC_EN

BASS_CF[1:0]

TREB_CF[1:0]

BASS[3:0]

TREB[3:0]

+12.0dB/-10.5dB

1.5dB steps

Fixed Function DSP

MSTAMUTE

MSTBMUTE

DIGSFT

DIGZC

PLYBCKB=A

LIMARATE[7:0]

LIMRRATE[7:0]

LMAX[2:0]

CUSH[2:0]

LIMSRDIS

LIMZCDIS

LIMIT

PCMASWAP[1:0]

PCMBSWAP[1:0]

PCM Serial Interface

INPUTS FROM ADCA

and ADCB

OFFTIME[2:0]

ONTIME[3:0]

FREQ[3:0]

BEEP[1:0]

BEEPMIXDIS

Digital Mix to ADC

Serial Interface

Channel

Swap

INV_PCMA

INV_PCMB

ADCASWAP[1:0]

ADCBSWAP[1:0]

PWM

Modulator

DAC

Figure 10. DSP Engine Signal Flow

30 DS680F1

CS42L52

5/13/08

4.3.1 Beep Generator

The Beep Generato r generates audio frequencie s across approximately two octave major scales. It offers

three modes of operation: Continuous, multiple, and single (one-shot) beeps. Sixteen on and eight off

times are available.

Note: The Beep is generated before the limiter and may affect desired limiting performance. If the lim-

iter function is used, it may be re quired to set the b eep volume sufficiently b elow the thr eshold to prevent

the peak detect from triggering. Since the master volume control, MSTxVOL[7:0], will affect the beep vol-

ume, DAC volume may alternatively be controlled using the PMIXxVOL[6:0] bits.

Referenced Control Register Location

PWM Control

SPKxMUTE.........................

MUTE50/50.........................

SPKMONO..........................

SPKxVOL[7:0].....................

SPKSWAP...........................

SPKB=A ..............................

BATTCMP ...........................

VPREF[3:0] .........................

VPLVL[7:0] ..........................

PDN_SPKx[1:0]...................

SPKxSHRT..........................

“Speaker Mute” on page 54

“Speaker Mute 50/50 Control” on page 54

“Speaker MONO Control” on page 54

“Speaker Volume Control” on page 64

“Speaker Channel Swap” on page 54

“Speaker Volume Setting B=A” on page 54

“Battery Compensation” on page 71

“VP Reference” on page 72

“VP Voltage Level (Read Only)” on page 72

“Speaker Power Control” on page 44

“Speaker Current Load Status (Read Only)” on page 72

Referenced Control Register Location

Analog Output

HPxMUTE ...........................

HPxVOL[7:0] .......................

PDN_HPx[1:0].....................

HPGAIN[2:0]........................

PASSTHRUx .......................

PASSxMUTE.......................

PASSxVOL[7:0]...................

CHGFREQ ..........................

“Headphone Mute” on page 54

“Headphone Volume Control” on page 63

“Headphone Power Control” on page 44

“Headphone Analog Gain” on page 51

“Passthrough Analog” on page 52

“Passthrough Mute” on page 52

“Passthrough x Volume” on page 57

“Charge Pump Frequency” on page 73

Charge

Pump

DAC

CHGFREQ[3:0]

HPGAIN[2:0]

VOL

Analog Passthru

from PGA

HPAMUTE

HPBMUTE

HPA_VOL[7:0]

HPB_VOL[7:0]

+0dB/-102dB

0.5dB steps

PASSAMUTE

PASSBMUTE

PASSAVOL[7:0]

PASSBVOL[70]

+12dB/-60dB

0.5dB steps

(uses PGA)

PASSTHRUA

PASSTHRUB

PDN_HPA[1:0]

PDN_HPB[1:0]

from D S P

Engine HP/Line

Outputs

VOL PWM

Modulator

SPKAMUTE

SPKBMUTE

MUTE50/50

SPKMONO

SPKSWAP

SPKB=A

SPKAVOL[7:0]

SPKBVOL[7:0]

+0dB/-102dB

0.5dB steps

PDN_SPKA[1:0]

PDN_SPKB[1:0]

Short

Circuit

SPKASHRT

Battery

Compensation

BATTCMP

VPREF[3:0]

VPLVL[7:0]

SPKBSHRT

Gate

Drive

from DSP

Engine

Speaker

Outputs

Figure 11. PWM Output Stage Figure 12. Analog Output Stage

DS680F1 31

CS42L52

5/13/08

4.3.2 Limiter

When enabled, the limiter monitors the digita l input signal before the DAC and PWM modula tors, detects

when levels exceed the maximum threshold settings, and lowers the master volume at a programmable

attack rate below the m aximum threshold. When the input signal level falls below the maximum threshold,

the AOUT volume re turns to its original level set in th e Master Volume Control register at a progr ammable

release rate. Attack and release rate s are affected by the DAC soft-ramp/zer o-cross settings and sample

rate, Fs. Limiter soft-ramp and zero-cross dependency may be independently enabled/disabled.

Notes:

1. Recommended settings: Best limiting performance may be realized with the fastest attack and

slowest release setting with soft ramp enabled in the control registers. The MIN bits allow the user to

set a threshold slightly below the maximum threshold for hysteresis control - this cush ions the sound

as the limiter attacks and releases.

2. The Limiter maintains the output signal between the MIN and MAX thresholds. As the digi tal inpu t

signal level changes, the level-controlled output may not always be the same but will always fall within

the thresholds.

Referenced Control Register Location

MSTxVOL[7:0].....................

PMIXxVOL[6:0] ...................

OFFTIME[2:0] .....................

ONTIME[3:0].......................

FREQ[3:0]...........................

BEEP[1:0]............................

BEEPMIXDIS......................

BPVOL[4:0].........................

“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63

“PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 58

“Beep Off Time” on page 60

“Beep On Time” on page 60

“Beep Frequency” on page 59

“Beep Configuration” on page 61

“Beep Mix Disable” on page 61

“Beep Volume” on page 61

Referenced Control Register Location

Limiter Controls........ ...........

Master Volume Control........ “Limiter Control 2, Release Rate (Address 28h)” on page 66, “Limiter Attack Rate (Address 29h)” on page 67

“Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 63

FREQ[3:0]

...

BPVOL[4:0]

ONTIME[3:0] OFFTIME[2:0]

BEE P [1:0] =

'01'

BEE P [1:0] =

'10'

BEE P [1:0] =

'11'

SINGLE-BEEP: Beep turns on at a

configurable frequency (FREQ) and

volume (BPVOL) for the duration of

ONTIME. BEEP must be cleared

and set for additional beeps.

MULTI-BEEP: Beep turns on at a configurable frequency (FREQ)

and volume (BPVOL) for the duration of ONTIME and turns off for

the duration of OFFTIME. On and off cycles are repeated until

BEEP is cleared.

CONTINUOUS BEEP: Beep turns on at a configurable frequency (FRE Q) and volume (BPVOL) and remains on

until BEEP is cleared.

Figure 13. Beep Configuration Options

32 DS680F1

CS42L52

5/13/08

4.4 Analog In to Analog Out Passthrough

The CS42L52 accommodates analog routing of the analog input signal directly to the headphone amplifiers.

This feature is useful in applications that utilize an FM tuner where audio recovered over-the-air must be

transmitted to the headphone amplifier without digital conversion in the ADC and DAC. This analog

passthrough path reduces power consumption and is immune to modulator switching noise that could

interfere with some tuners.

4.4.1 Overriding the ADC Power Down

To accommodate automatic activation of the speaker amplifier when the SPK/HP_SW switch pin chang-

es, the CS42L52 provides the option to automatically power up the ADC whenever th e analog signal must

route to the digital PWM modulator, regardless of the PDN_ADC bit. Refer to the table below for details

on how this ADC power- down override functions in accordance with the state of the speaker channels.

The shaded cells represent norma l ADC operation when passthro ug h is disa ble d .

When PASSTHRU and PDN_OVRD are enabled, turning the speaker channel ON (by writing ‘11’b to

SPKx_PDN[1:0] or by automatic activation of the headphone detect switch, SPK/HP_SW) will automati-

cally disable the ADCx_PDN in order to convert the analog input to a digital signal for the PWM modulator.

This allows automatic analog input routing to the speaker amplifiers.

PDN_ADC PASSTHR U PDN_OVRD Speaker Channel ADC Status

0 x x x Powered UP

0 x x Powe red DOWN

10 x Powered DOWN

1OFF Powered DOWN

ON Powered UP

MAX[2:0]

Output

(after Lim iter)

Input

RRATE[5:0]ARATE[5:0]

Volume

Limiter

CUSH[2:0]

ATTACK/RELEASE SOUND

C U SHION

MAX[2:0]

ure 14. Peak Detect & Limite r

DS680F1 33

CS42L52

5/13/08

4.4.2 Overriding the PGA Power Down

To accommodate automatic activation of the headphone amplifier when the SPK/HP_SW switch pin

changes, the CS42L52 will automatically power up th e PGA whenever passthrough is enabled, regard-

less of the PDN_PGA setting. Refer to the table below for details on how this PGA power-down override

functions in accordance with the state of the headphone channels. The shaded cells represent normal

PGA operation when passthrough is disabled.

When passthrough is enabled, turning the headphone channel ON (by writing ‘11’b to HPx_PDN[1:0] or

by automatic activation of the headphone detect switch, SPK/HP_SW) will automatically disable the

PGAx_PDN in order to transmit the analog signal to the headphone.

4.5 PWM Outputs

4.5.1 Mono Speaker Output Configuration

The CS42L52 accommodates a stereo as well as a mono speaker output configuration. In mono mode

the output d rivers of each cha nnel are conne cted in parallel to deliver maximum power to a 4 ohm speak-

er. Refer to the table below for pin mapping in mono configuration.

4.5.2 VP Battery Compensation

The CS42L52 provides the op tion to maintain a desired power output le vel, independent of the VP supply.

When enabled, this feature works by monitoring the voltage on the VP supply and reducing the at tenu a-

tion on the speaker outputs when VP voltage levels fall.

Note: The internal ADC that monitors the VP supply operates from the VA supply. Calculations are

based on typical VA levels of 1.8 V and 2.5 V using the VPREF bits.

Referenced Control Register Location

PDN_ADCx.........................

PASSTHRU.........................

PDN_OVRD........................

SPKx_PDN[1:0]...................

“Power Down ADCx” on page 43

“Passthrough Analog” on page 52

“Power Down ADC Override” on page 43

“Speaker Power Control” on page 44

PDN_PGA PASSTHRU HP Channel PGA Status

0 x x Powered UP

10 x Powered DOWN

1OFF Powered DOWN

ON Powered UP

Referenced Control Register Location

PDN_PGAx.........................

PASSTHRU.........................

HPx_PDN[1:0].....................

“Power Down PGAx” on page 42

“Passthrough Analog” on page 52

“Headphone Power Control” on page 44

Pin Speaker Output

SPKMONO=0 SPKMONO=1

SPKSWAP=0 SPKSWAP=1 SPKSWAP=0 SPKSWAP=1

4 SPKOUTA+ SPKOUTB+ SPKOUTA+ SPKOUTB+

6 SPKOUTA- SPKOUTB- SPKOUTA+ SPKOUTB+

7 SPKOUTB+ SPKOUTA+ SPKOUTA- SPKOUTB-

9 SPKOUTB- SPKOUTA- SPKOUTA- SPKOUTB-

Referenced Control Register Location

SPKMONO..........................

SPKSWAP........................... “Speaker MONO Control” on page 54

“Speaker Channel Swap” on page 54

34 DS680F1

CS42L52

5/13/08

4.5.2.1 Maintaining a Desired Output Level

Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expect-

ed VP supply range (MAX relative to MIN). The CS42L52 then gradually reduces the attenuation as the

VP supply drops from its maximum level, maintaining a nearly constant power output.

Compensation Example 1 (VP Battery supply ranges from 4.5 V to 3.0 V)

1. Set speaker attenuation (SPKxVOL) to -3.5 dB. The VP supply changes ~3.5 dB.

2. Set the refe re nc e VP sup ply (VPR EF ) to 4. 5 V.

3. Enable battery compensation (BATTCMP).

The CS42L52 automatically adjusts the output level as the battery discharges.

Compensation Example 2 (VP Battery supply ranges from 5.0 V to 1.6 V)

1. Set speaker attenuation (SPKxVOL) to -10 dB. The VP supply changes ~9.9 dB.

2. Set the refe re nc e VP sup ply (VPR EF ) to 5. 0 V.

3. Enable battery compensation (BATTCMP).

The CS42L52 automatically ad justs the output level as the battery discharges. Refer to Figure 15 on page

34. In this example, the VP supply changes over a wide range, illustrating the accuracy of the CS42L52’s

battery compensation.

4.6 Serial Port Clocking

The CODEC serial audio interface port operates either as a slave or master, determined by the M/S bit. It

accepts externally generated clocks in Slave Mode and w ill generate synchronous clocks deriv ed from an

input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h

and 06h associated with a given MCLK and sample rate.

Referenced Cont ro l Register Location

VPREF................................

SPKxVOL............................ “VP Reference” on page 72

“Speaker Volume Contro l” on page 64

Referenced Control Register Location

M/S

“Master/Slave Mode” on page 46

“Clocking Control (Address 05h)” on page 44

“Interface Control 1 (Address 06h)” on page 46

-24

-22

-20

-18

-16

-14

-12

-10

-8

-6

1.61.92.22.52.83.13.43.744.34.64.9

Uncompensated

PWM Output

Level

Battery Compensated

PWM Output Level

VP Supply (V)

PWM Output Level (dB)

Figure 15. Battery Compen s at ion

DS680F1 35

CS42L52

5/13/08

MCLK

(MHz) Sample Rate,

Fs (kHz) SPEED[1:0]

(AUTO=’0’b)32kGROUP VIDEOCLK RATIO[1:0] MCLKDIV2

12.2880

8.0000 11 1 0 00 0

12.0000 11 0 0 00 0

16.0000 10 1 0 00 0

24.0000 10 0 0 00 0

32.0000 01 1 0 00 0

48.0000 01 0 0 00 0

96.0000 00 0 0 00 0

11.2896

11.0250 11 0 0 00 0

22.0500 10 0 0 00 0

44.1000 01 0 0 00 0

88.2000 00 0 0 00 0

18.4320

(Slave

Mode

ONLY)

8.0000 11 1 0 00 0

12.0000 11 0 0 00 0

16.0000 10 1 0 00 0

24.0000 10 0 0 00 0

32.0000 01 1 0 00 0

48.0000 01 0 0 00 0

96.0000 00 0 0 00 0

16.9344

(Slave

Mode

ONLY)

8.0182 11 0 0 10 0

11.0250 11 0 0 00 0

22.0500 10 0 0 00 0

44.1000 01 0 0 00 0

88.2000 00 0 0 00 0

12.0000

8.0000 11 1 0 01 0

11.029411 0 0110

12.0000 11 0 0 01 0

16.0000 10 1 0 01 0

22.058810 0 0110

24.0000 10 0 0 01 0

32.0000 01 1 0 01 0

44.117601 0 0110

48.0000 01 0 0 01 0

88.235300 0 0110

96.0000 00 0 0 01 0

24.0000

8.0000 11 1 0 01 1

11.029411 0 0111

12.0000 11 0 0 01 1

16.0000 10 1 0 01 1

22.058810 0 0111

24.0000 10 0 0 01 1

32.0000 01 1 0 01 1

44.117601 0 0111

48.0000 01 0 0 01 1

88.235300 0 0111

96.0000 00 0 0 01 1

27.0000

8.0000 11 1 1 01 0

12.0000 11 0 1 01 0

24.0000 10 0 1 01 0

32.0000 01 1 1 01 0

44.117601 0 1110

48.0000 01 0 1 01 0

11.029411 0 1110

22.058810 0 1110

16.0000 10 1 1 01 0

Table 1. MCLK, LRCK Quick Decode

36 DS680F1

CS42L52

5/13/08

4.7 Digital Interface Formats

The serial port oper ates in sta ndard I²S, Le ft-justified, Right- justified (DAC only), or DSP Mode digital inter-

face formats with varying bit depths from 16 to 24. Data is clocked out of the ADC or into the DAC on the

rising edge of SCLK.

4.7.1 D SP Mode

In DSP Mode, the LRCK acts as a frame sync for 2 data-packed words (left and right channel) input on

SDIN and output on SDOUT. The MSB is input/output on the first SCLK rising edg e af te r th e fr am e sync

rising edge. The right channel immediately follows the left channel.

LRCK

SCLK

MSB LSB MSB LSB

AOUTA / AINxA

Left Channel Right Channel

SDOUT

SDIN

AOUTB / AINxB

MSB

Figure 16. I²S Format

LRCK

SCLK

MSB LSB MSB LSB

Left Channel Right Channel

SDOUT

SDIN MSB

AOUTA / AINxA AOUTB / AINxB

Figure 17. Left-Justified Format

LRCK

SCLK

MSB LSB MSB LSB

Left Channel Right Channel

SDIN

AOUTL AOUTR

Audio W ord Length (AWL)

Figure 18. Right-Justified Format (DAC only)

LRCK

SCLK

MSB LSB

SDIN

HP/LINE OUTB

LSB Le ft Channe l Right Channel

MSB LSB MSB

Audio Word Lengt h (AWL)

1/fs

HP/LINE OUTA

Figure 19. DSP Mode Format)

DS680F1 37

CS42L52

5/13/08

4.8 Initialization

The CODEC enters a Po wer-down state upon initial power-up. The interpolation and d ecimation filters, del-

ta-sigma and PWM modulators, and control port registers are reset. The internal voltage reference, and

switched-capacitor low-pass filters are po we re d down .

The device will remain in the Power-down state until the RESET pin is brought high. The control port is ac-

cessible once RESET is high and the desi red reg ister se ttings can be loaded per the inter face descriptio ns

in the “Register Description” on page 42.

Once MCLK is valid, the quiescent voltage, VQ, and the internal voltage referenc e, FILT+, will begin power-

ing up to no rma l ope ratio n. Th e cha rge pum p s lowly po wers up and ch arge s t he capa cit ors. Power is then

applied to the headphone amplifiers and switched-capacitor filters, and the analog/digital outputs enter a mut-

ed state. Once LRCK is valid, MCLK occurrences are counted over one LRCK period to determine the

MCLK/LRCK frequency ratio and normal operation begins.

4.9 Recommended Power-up Sequence

1. Hold RESET low until the power supplies are stable.

2. Bring RESET high.

3. The default state of the PDN bit is ‘1’b. Loa d the de sired register settings while keeping the PDN bit set

to ‘1’b.

4. Load the required initialization settings listed in Section 4.11.

5. Start MCLK to the appropr iate frequency, as discussed in Section 4.6.

6. Set the PDN bit to ‘0’b.

7. Apply LRCK, SCLK, and SDIN for normal operation to begin.

8. Bring RESET low if the analog or digital supplies drop below the recommended operating condition to

prevent power glitch related issues.

4.10 Recommended Power-down Sequence

To minimize audible pops when turning off or placing the CODEC in standby:

1. Mute the DAC’s and ADC’s.

2. Set the PDN bit in the power control register to ‘1’b. The CODEC will not power down until it reaches a

fully muted sate. Do not remove MCLK until after the part ha s fully muted. Note that it may be necessa ry

to disable the soft-ramp and/or zero-cross volume transitions to achieve faster muting/power down.

3. Bring RESET low.

4.11 Required Initialization Settings

The current and thresholds required for various sections in the CODEC must be adjusted by implementing

the initialization settings shown below after power-up sequence step 3. All performance and power con-

sumption measurements were taken with the following settings:

1. Write 0x99 to register 0x00.

2. Write 0xBA to register 0x3E.

3. Write 0x80 to register 0x47.

4. Write ‘1’b to bit 7 in register 0x32.

5. Write ‘0’b to bit 7 in register 0x32.

6. Write 0x00 to register 0x00.

38 DS680F1

CS42L52

5/13/08

4.12 Control Port Operation

The control port is used to access the register s, allowing the CODEC to be configured fo r the desired oper -

ational modes and for mats. The operation of the control p ort may be completely a synchronous with respect

to the audio sample rates. However, to avoid potential interference problems, the control port pins should

remain static if no operation is required.

The control port operates using an I²C interface with the CODEC acting as a slave device.

4.12.1 I²C Control

SDA is a bidirectional data line. Data is clocked into and out of the par t by the clock, SCL. The signal tim-

ings for a read and write cycle are shown in Figure 20 and Figure 21. A Start condition is defined as a

falling transition of SDA while the clock is high. A Stop condition is defined as a rising transition of SDA

while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the

CS42L52 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low

for a write).

The upper 7 bits of the address field are fixed at 1001010. To communicate with the CS42L52, the chip

address field, which is the first byte sent to the CS42L52, should match 1001010. The eighth bit of the

address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP),

which selects the register to be read or written. If the opera tion is a read, the contents of the register point-

ed to by the MAP will be output. Setting the auto-increment bit in MAP allows successive reads or writes

of consecutiv e registers. Each by te is separated by an acknowledge bit. The ACK bit is output from the

CS42L52 after each input byte is read and is input to the CS42L52 from the microcontroller after each

transmitted byte.

Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown

in Figure 21, the write operation is aborted after the acknowledg e for the MAP byte by sending a stop con-

dition. The following pseudocode illustrates an aborted write operation followed by a read operation.

4 5 6 7 24 25

SCL

CHIP ADDRESS (WRITE) MAP BYTE DATA DATA +1

START

ACK STOP

ACKACKACK

1 0 0 1 0 1 0 0

SDA INCR 6 5 4 3 2 1 0 7 6 1 0 7 6 1 0 7 6 1 0

0 1 2 3 8 9 12 16 17 18 19 10 11 13 14 15 27 28

DATA +n

Figure 20. Control Port Timing, I²C Write

SCL

CHIP ADDRESS (WRITE) MAP BY TE DATA DATA + 1

START ACK

STOP

ACK

1 0 0 1 0 1 0 0

SDA 1 0 0 1 0 1 0 1

CHIP ADDRESS (READ)

START

INCR 6 5 4 3 2 1 0 7 0 7 0 7 0

16 8 9 12 13 14 15 4 5 6 7 0 1 20 21 22 23 24 26 27 28

2 3 10 11 17 18 19 25

ACK

DATA + n

STOP

Figure 21. Control Port Timing, I²C Read

DS680F1 39

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5/13/08

Send start condition.

Send 10010100 (ch ip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto-increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10010101 (chip address & read operation).

Receive acknowledge bit.

Receive byte, co nt en ts of selec te d re gis ter .

Send acknowledge bit.

Send stop condition.

Setting the auto-increment bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

4.12.2 Memory Address Pointer (MAP)

The MAP byte comes after the address byte and selects the register to be read or written. Refer to the

pseudo code above for implementation details.

4.12.2.1 Map Increment (INCR)

The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is

set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-in-

crement after each byte is read or written, allowing block reads or writes of successive registers.

40 DS680F1

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5. REGISTER QUICK REFERENCE

(Default values are shown below the bit names)

I²C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)

Adr. Function 7 6 5 4 3 2 1 0

01h ID CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0

p42 11100xxx

02h Power Ctl 1 PDN_CHRG Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN

p42 00000001

03h Power Ctl 2 Reserved Reserved Reserved OVRDB OVRDA PDN_MICB PDN_MICA PDN_BIAS

p43 00000111

04h Power Ctl 3 PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0

p44 00000101

05h Clocking Ctl AUTO SPEED1 SPEED0 32kGROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2

p44 10100000

06h Interface Ctl 1 M/S INV_SCLK ADCDIF DSP DACDIF1 DACDIF0 AWL1 AWL0

p46 00000000

07h Interface Ctl 2 Reserved SCLK=MCLK DIGLOOP 3ST_SP INV_SWCH BIASLVL2 BIASLVL1 BIASLVL0

p47 00000000

08h Input A Select ADCASEL2 ADCASEL1 ADCASEL0 PGAASEL5 PGAASEL4 PGAASEL3 PGAASEL2 PGAASEL1

p48 10000001

09h Input B Select ADCBSEL2 ADCBSEL1 ADCBSEL0 PGABSEL5 PGABSEL4 PGABSEL3 PGABSEL2 PGABSEL1

p48 10000001

0Ah Analog,

HPF Ctl HPFB HPFRZB HPFA HPFRZA ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA

p49 10100101

0Bh ADC HPF Cor-

ner Freq. Reserved Reserved Reserved Reserved HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0

p50 00000000

0Ch Misc. ADC Ctl ADCB=A DIGMIX DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADC BMUTE ADCAMUTE

p50 00000000

0Dh Playback Ctl 1 HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE

p51 01100000

0Eh Misc. Ctl PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC

p52 00000010

0Fh Playback Ctl 2 HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50

p54 00000 00

10h MICA Amp Ctl Reserved MICASEL MICACFG MICAGAIN4 MICAGAIN3 MICAGAIN2 MICAGAIN1 MICAGAIN0

p55 00000000

11h MICB Amp Ctl Reserved MICBSEL MICBCFG MICBGAIN4 MICBGAIN3 MICBGAIN2 MICBGAIN1 MICBGAIN0

p55 00000000

12h PGAA Vol, Misc ALCASRDIS ALCAZCDIS PGAAVOL5 PGAAVOL4 PGAAVOL3 PGAAVOL2 PGAAVOL1 PGAAVOL0

p55 00000000

13h PGAB Vol, Misc ALCBSRDIS ALCBZCDIS PGABVOL5 PGABVOL4 PGABVOL3 PGABVOL2 PGABVOL1 PGABVOL0

p55 00000000

14h Passthru A Vol PASSAVOL7 PASSAVOL6 PASSAVOL5 PASSAVOL4 PASSAVOL3 PASSAVOL2 PASSAVOL1 PASSAVOL0

p57 00000000

15h Passthru B Vol PASSBVOL7 PASSBVOL6 PASSBVOL5 PASSBVOL4 PASSBVOL3 PASSBVOL2 PASSBVOL1 PASSBVOL0

p57 00000000

16h ADCA Vol ADCAVOL7 ADCAVOL6 ADCAVOL5 ADCAVOL4 ADCAVOL3 ADCAVOL2 ADCAVOL1 ADCAVOL0

p57 00000000

17h ADCB Vol ADCBVOL 7 ADCBVOL6 ADCBVOL5 ADCBVOL4 ADCBVOL3 ADCBVOL2 ADCBVOL1 ADCBVOL0

p57 00000000

18h ADCMIXA Vol AMIXAMUTE AMIXAVOL6 AMIXAVOL5 AMIXAVOL4 AMIXAVOL3 AMIXAVOL2 AMIXAVOL1 AMIXAVOL0

p58 10000000

19h ADCMIXB Vol AMIXBMUTE AMIXBVOL6 AMIXBVOL5 AMIXBVOL4 AMIXBVOL3 AMIXBVOL2 AMIXBVOL1 AMIXBVOL0

p58 10000000

1Ah PCMMIXA Vol PMIXAMUTE PMIXAVOL6 PMIXAVOL5 PMIXAVOL4 PMIXAVOL3 PMIXAVOL2 PMIXAVOL1 PMIXAVOL0

p58 00000000

DS680F1 41

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1Bh PCMMIXB Vol PMIXBMUTE PMIXBVOL6 PMIXBVOL5 PMIXBVOL4 PMIXBVOL3 PMIXBVOL2 PMIXBVOL1 PMIXBVOL0

p58 000 00000

1Ch BEEP Freq,

On Time FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0

p59 000 00000

1Dh BEEP Vol,

Off Time OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0

p60 000 00000

1Eh BEEP,

Tone Cfg. BEEP1 BEEP0 BEEPMIXDIS TREB_CF1 TREB_CF0 BASS_CF1 BASS_CF0 TC_EN

p61 000 00000

1Fh Tone Ctl TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0

p62 100 01000

20h Master A Vol MSTAVOL7 MSTAVOL6 MSTAVOL5 MSTAVOL4 MSTAVOL3 MSTAVOL2 MSTAVOL1 MSTAVOL0

p63 000 00000

21h Master B Vol MSTBVOL7 MSTBVOL6 MSTBVOL5 MSTBVOL4 MSTBVOL3 MSTBVOL2 MSTBVOL1 MSTBVOL0

p63 000 00000

22h Headphone A

Volume HPAVOL7 HPAVOL6 HPAVOL5 HPAVOL4 HPAVOL3 HPAVOL2 HPAVOL1 HPAVOL0

p63 000 00000

23h Headphone B

Volume HPBVOL7 HPBVOL6 HPBVOL5 HPBVOL4 HPBVOL3 HPBVOL2 HPBVOL1 HPBVOL0

p63 000 00000

24h Speaker A

Volume SPKAVOL7 SPKAVOL6 SPKAVOL5 SPKAVOL4 SPKAVOL3 SPKAVOL2 SPKAVOL1 SPKAVOL0

p64 000 00000

25h Speaker B

Volume SPKBVOL7 SPKBVOL6 SPKBVOL5 SPKBVOL4 SPKBVOL3 SPKBVOL2 SPKBVOL1 SPKBVOL0

p64 000 00000

26h Channel Mixer

& Swap PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 ADCASWP1 ADCASWP0 ADCBSWP1 ADCBSWP0

p64 000 00000

27h Limit Ctl 1,

Thresholds LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS

p65 000 00000

28h Limit Ctl 2,

Release Rate LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0

p66 011 11111

29h Limiter Attack

Rate Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0

p67 110 00000

2Ah ALC Ctl 1,

Attack Rate ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0

p67 000 00000

2Bh ALC Release

Rate Reserved Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0

p68 001 11111

2Ch AL C Thresh-

olds ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALCMIN0 Reserved Reserved

p68 000 00000

2Dh Noise Gate Ctl NGALL NG NGBOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0

p69 000 00000

2Eh Overflow &

Clock Status Reserved SPCLKERR DSPBOVFL DSPAOVFL PCMAOVFL PCMBOVFL ADCAOVFL ADCBOVFL

p70 000 00000

2Fh Battery Com-

pensation BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0

p71 000 00000

30h VP Battery

Level VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0

p72 000 00000

31h Speaker Status Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved

p72 000 00000

32h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

001 11011

33h Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved

000 00000

34h Charge Pump

Frequency CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved

p73 010 11111

I²C Address: 1001010[R/W] - 10010100 = 0x94(Write); 10010101 = 0x95(Read)

Adr. Function 7 6 5 4 3 2 1 0

42 DS680F1

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6. REGISTER DESCRIPTION

All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are

read only. See the following bit definition tables for bit assignm ent info rmat ion. T he d efau lt stat e of ea ch b it af ter a

power-up sequence or reset is listed in each bit description. Unless otherwise specified, all “Reserved” bits must

maintain their default value.

6.1 Chip I.D. and Revision Register (Address 01h) (Read Only)

6.1.1 Chip I.D. (Read Only)

I.D. code for the CS42L52.

6.1.2 C hip Revision (Read Only)

CS42L52 revision level.

6.2 Power Control 1 (Address 02h)

6.2.1 Power Down ADC Charge Pump

Configures the power state of the ADC charge pump.

6.2.2 Power Down PGAx

Configures the power state of PGA channel x.

Notes:

1. The CS42L52 employs a clever scheme for controlling the power to the PGA when PASSTHRU

(“Passthrough Analog” on page 52) is enabled. Refer to the referenced application for more information.

2. This bit should be used in conjunction with ADCxSEL and PGAxSEL bits to determine the analog

76543210

CHIPID4 CHIPID3 CHIPID2 CHIPID1 CHIPID0 REVID2 REVID1 REVID0

CHIPID[4:0] Device

11100 CS42L52

REVID[2:0] Revision Level

000 A0

001 A1

010 B0

011 B1

76543210

PDN_CHRG Reserved Reserved PDN_PGAB PDN_PGAA PDN_ADCB PDN_ADCA PDN

PDN_CHRG ADC Charge Pump Status

0 Powered Up

1 Powered Down

PDN_PGAx PGA Status

0Powered Up (ONLY when the ADC or the analog passthru is used)

1 Powered Down

Application “Analog In to Analog Out Passthrough” on page 32

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input path. The PGAxSEL bits may be used to isolate the input signal(s) from the PGA outputs. When

the PGA is powered down, no input should be selected. Refer to “ADC Input Select” on page 48 and

“PGA Input Mapping” on page 49 for the required settings.

6.2.3 Power Down ADCx

Configures the power state of ADC channel x.

Notes:

1. The CS42L52 employs a clever scheme for controlling the power to the ADC when PASSTHRU

(“Passthrough Analog ” on page 52) and PDN_OVRD (“Power Down ADC Override” on page 43) are

enabled. Refer to the referenced application.

6.2.4 Power Down

Configures the power state of the entire CODEC.

6.3 Power Control 2 (Address 03h)

6.3.1 Power Down ADC Override

Configures an ove r ride of th e po we r do wn cont ro l for ADCx.

6.3.2 Power Down MICx

Configures the power state of the microphone pre-amplifier for channel x.

6.3.3 Power Down MIC Bias

Configures the power state of the microphone bias circuit.

PDN_ADCx ADC Status

0Powered Up

1 Powered Down

Application “Analog In to Analog Out Passthrough” on page 32

PDN CODEC Status

0 Powered Up

1Powered Down

76543210

Reserved Reserved Reserved OVRDB OVRDA PDN_MICB PDN_MICA PDN_BIAS

OVRDx PDN_ADC Override

0Disable

1 Enable

Application “Analog In to Analog Out Passthrough” on page 32

PDN_MICx MIC Pre-Amp Status

0 Powered Up

1Powered Down

Application “MIC Inputs” on page 27

PDN_BIAS MIC Bias Status

0 Powered Up

1Powered Down

44 DS680F1

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6.4 Power Control 3 (Address 04h)

6.4.1 Headphone Power Control

Configures how the SPKR/HP pin, 31, controls the power for the headphone amplifier.

6.4.2 Speaker Power Control

Configures how the SPKR/HP pin, 31, controls the power for the speaker amplifier.

6.5 Clocking Control (Address 05h)

6.5.1 Auto-Detect

Configures the auto-detect circuitry for detecting the speed mode of the CODEC when operating as a

slave.

Notes:

1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio.

2. When AUTO is disabled and the CODEC operates in master mode, the MCLKDIV2 bit is ignored.

3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit

(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on

page 45) and RATIO[1:0] bits (“Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also

affect dynamic range performance in the typical audio band. Refer to the referenced application for

more information.

76543210

PDN_HPB1 PDN_HPB0 PDN_HPA1 PDN_HPA0 PDN_SPKB1 PDN_SPKB0 PDN_SPKA1 PDN_SPKA0

PDN_HPx[1:0] Headphone Status

00 Headphone channel is ON when the SPKR/HP pin, 31, is LO.

Headphone channel is OFF when the SPKR/HP pin, 31, is HI.

01 Headphone channel is ON when the SPKR/HP pin, 31, is HI.

Headphone channel is OFF when the SPKR/HP pin, 31, is LO.

10 Headphone channel is always ON.

11 Headphone channel is always OFF.

PDN_SPKx[1:0] Speaker Status

00 Speaker channel is ON when the SPKR/HP pin, 31, is LO.

Speaker channel is OFF when the SPKR/HP pin, 31, is HI.

01 Speaker channel is ON when the SPKR/HP pin, 31, is HI.

Speaker channel is OFF when the SPKR/HP pin, 31, is LO.

10 Speaker channel is always ON.

11 Speaker channel is always OFF.

76543210

AUTO SPEED1 SPEED0 32k_GROUP VIDEOCLK RATIO1 RATIO0 MCLKDIV2

AUTO Auto-detection of Speed Mode

0 Disabled

1Enabled

Application: “Serial Port Clocking” on page 34

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6.5.2 Speed Mode

Configures the speed m ode of the CODEC in slave mode and sets the appropriate MCLK divide ratio for

LRCK and SCLK in master mode.

Notes:

1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.

2. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit

(“32kHz Sample Rate Group” on page 45) and/or the VIDEOCLK bit (“27 MHz Video Clock” on

page 45) and RATIO[1:0] bits ( “Internal MCLK/LRCK Ratio” on page 45). Low sample rates may also

affect dynamic range performance in the typical audio band. Refer to the referenced application for

more information.

3. These bits are ignored when the AUTO bit (“Auto-Detect” on page 44) is enabled.

6.5.3 32kHz Sample Rate Group

Specifies whether or not the input/output sample rate is 8 kHz, 16 kHz or 32 kHz.

6.5.4 27 MHz Video Clock

Specifies whether or not the external MCLK frequency is 27 MHz

6.5.5 Internal MCLK/LRCK Ratio

Configures the internal MCLK/LRCK ratio.

SPEED[1:0] Slave Mode Master Mode

Serial Port Speed MCLK/LRCK Ratio SCLK/LRCK Ratio

00 Double-Speed Mode (DSM - 50 kHz -100 kHz Fs) 512 64

01 Single-Speed Mode (SSM - 4 kHz -50 kHz Fs) 256 64

10 Half-Speed Mode (HSM - 12.5kHz -25 kHz Fs) 128 64

11 Quarter-Speed Mode (QSM - 4 kHz -12.5 kHz Fs) 128 64

Application: “Serial Port Clocking” on page 34

32kGROUP 8 kHz, 16 kHz or 32 kHz sample rate?

0No

1Yes

Application: “Serial Port Clocking” on page 34

VIDEOCLK 27 MHz MCLK?

0No

1Yes

Application: “Serial Port Clocking” on page 34

RATIO[1:0] Internal MCLK Cycles per LRCK SCLK/LRCK Ratio in Master Mode

00 128 64

01 125 62

10 132 66

11 136 68

Application: “Serial Port Clocking” on page 34

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6.5.6 MCLK Divide By 2

Divides the input MCLK by 2 prior to all internal circuitry.

Note: In slave mode, this bit is ignored when the AUTO bit (“Auto-Detect” on page 44) is disabled.

6.6 Interface Control 1 (Address 06h)

6.6.1 Master/Slave Mode

Configures the serial port I/O clocking.

6.6.2 S CLK Polarity

Configures the polarity of the SCLK signal.

6.6.3 A DC Interface Format

Configures the digital interface format for data on SDOUT.

6.6.4 D SP Mode

Configures a data-packed interface format for both the ADC and DAC.

Notes:

1. Select the audio word length using the AWL[1:0] bits (“Audio Word Length” on page 47).

2. The interface format for both the ADC and the DAC must be set to “Left-Justified” when DSP Mode

is enabled.

MCLKDIV2 MCLK signal into CODEC

0No divide

1 Divided by 2

Application: “Serial Port Clocking” on page 34

76543210

M/S INV_SCLK ADCDIF DSP DACDIF1 DACDIF0 AWL1 AWL0

M/S Serial Port Clocks

0Slave (input ONLY)

1 Master (output ONLY)

INV_SCLK SCLK Polarity

0Not Inverted

1 Inverted

ADCDIF ADC Interf ace Format

0Left Justified

1I²S

Application: “Digital Interface Formats” on page 36

DSP DSP Mode

0Disabled

1 Enabled

Application: “DSP Mode” on page 36

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6.6.5 DAC Interface Format

Configures the digital interface format for data on SDIN.

Note: Select the audio word length for Right Justified using the AWL[1:0] bits (“Audio Word Length” on

page 47).

6.6.6 Audio Word Length

Configures the audio sample word length used for the data into SDIN and ou t of SDOUT.

Note: When the internal MCLK/LRCK ratio is set to 125 in master mode, the 32-bit data width option

for DSP Mode is not valid unless SCLK=MCLK.

6.7 Interface Control 2 (Address 07h)

6.7.1 SCLK equals MCLK

Configures the SCLK signal source for master mode.

Note: This bit is only valid for MCLK = 12.0000 MHz.

6.7.2 SDOUT to SDIN Digital Loopback

Configures an internal loops the signal on the SDOUT pin to SDIN.

DACDIF[1:0] DAC Interface Format

00 Left Justified, up to 24-bit data

01 I²S, up to 24-bit data

10 Right Justified

11 Reserved

Application: “Digital Interface Formats” on page 36

AWL[1:0] Audio Word Length

DSP Mode Right Justified (DAC ONLY)

00 32-bit data 24-bit data

01 24-bit data 20-bit data

10 20-bit data 18-bit data

11 16-bit data 16-bit data

Application: “DSP Mode” on page 36

765432 10

Reserved SCLK=MCLK DIGLOOP 3ST_SP INV_SWCH BIASLVL2 BIASLVL1 BIASLVL0

SCLK=MCLK Output SCLK

0Re-timed signal, synchronously derived from MCLK

1 Non-retimed, MCLK signal

DIGLOOP Internal Loopback

0Disabled; SDOUT internally disconnect ed from SDIN

1 Enabled; SDOUT internally connected to SDIN

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6.7.3 Tri-State Serial Port Interface

Determines the state of the serial port drivers.

Notes:

1. Slave/Master Mode is determined by the M/S bit in “Master/Slave Mode” on page 46.

2. When the serial port is tri-stated in master mode, the ADC and DAC serial ports are clocked internally.

6.7.4 Speaker/Headphone Switch Invert

Determines the control signal polarity of the SPK/HP_SW pin.

6.7.5 MIC Bias Level

Sets the output voltage level on the MICBIAS output pin.

6.8 Input x Select: ADCA and PGAA (Address 08h), ADCB and PGAB (Address 09h)

6.8.1 A DC Input Select

Selects the specified analog input signal into ADCx.

3ST_SP Serial Port Status

Slave Mode Master Mode

0Serial Port clocks are inputs and SDOUT is output Serial Port clocks and SDOUT are outputs

1 Serial Port clocks are inputs and SDOUT is HI-Z Serial Port clocks and SDOUT are HI-Z

INV_SWCH SPK/HP_SW pin 6 Control

0Not inverted

1 Inverted

BIASLVL[2:0] Output Bias Level

000 0.5 x VA

001 0.6 x VA

010 0.7 x VA

011 0.8 x VA

100 0.83 x VA

101 0.91 x VA

110 Reserved

111 Reserved

7 6 5 4 3210

ADCASEL2 ADCASEL1 ADCASEL0 PGAASEL5 PGAASEL4 PGAASEL3 PGAASEL2 PGAASEL1

ADCxSEL[2:0] Selected Input to ADCx

000 AIN1x

001 AIN2x

010 AIN3x

011 AIN4x

100 PGAx - Use PGAxSEL bits (“PGA Input Mapping” on page 49) to select input channels

101 Reserved

110 Reserved

111 Reserved

Application: “Analog Inputs” on page 26

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6.8.2 PGA Input Mapping

Selects one or sums/mixes the analog input signal into the PGA. Each bit of the PGAx_SEL[5:1] word

corresponds to individual channels (i.e. PGAx_SEL1 selects AIN1x, PGAx_SEL2 selects AIN2x, etc.).

6.9 Analog & HPF Control (Address 0Ah)

6.9.1 ADCx High-Pass Filter

Configures the internal high -pass filter after ADCx.

6.9.2 ADCx High-Pass Filter Freeze

Configures the high pass filter’s digital DC subtraction and/or calib ra tio n afte r AD Cx.

6.9.3 Ch. x Analog Soft Ramp

Configures an incremental volume ramp from the current level to the new level at the specified rate.

6.9.4 Ch. x Analog Zero Cross

Configures when the sig nal level changes occur for the analog volume controls.

Note: If the signal does not encounter a zero crossing, the requested volume change will occur after a

timeout period of 102 4 sample periods (approximately 10.7 ms at 48 kHz sample rate).

PGAxSEL[5:1] Selected Input to PGAx (Examples)

00000 No inputs selected

00001 AIN1x

00010 AIN2x

00100 AIN3x

01000 AIN4x

10000 MICx; for single-ended MIC inputs, use MICxSEL (“MIC x Select” on page 55) to select MIC 1 or MIC 2; for

differential MIC inputs, enable MICxCFG (“MICx Configuration” on page 55)

10001 MICx + AIN1x

10011 MICx + AIN1x + AIN2x

Application: “Analog Inputs” on page 26

Note: Table does not show all possible combinations.

76543210

HPFB HPFRZB HPFA HPFRZA ANLGSFTB ANLGZCB ANLGSFTA ANLGZCA

HPFx High Pass Filter Status

0 Disabled

1Enabled

HPFRZx High Pass Filter Digital Subtraction

0Continuous DC Subtraction

1 Frozen DC Subtraction

ANLGSFTx Volume Changes Affected Analog Volume Controls

0Do not occur with a soft ramp MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”

on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)

1 Occur with a soft ramp

Ramp Rate: 1/2 dB every 16 LRCK cycles

ANLGZCx Volume Changes Affected Analog Volume Controls

0Do not occur on a zero cross-

ing MICxGAIN[4:0] (“MICx Gain” on page 55), PGAxVOL[5:0] (“PGAx Volume”

on page 56), and PASSxVOL[7:0] (“Passthrough x Volume” on page 57)

1Occur on a zero crossing

50 DS680F1

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6.10 ADC HPF Corner Frequency (Address 0Bh)

6.10.1 HPF x Corner Frequency

Sets the corner frequency (-3 dB point) for the internal High-Pass Filter (HPF).

6.11 Misc. ADC Control (Address 0Ch)

6.11.1 Analog Front-End Volume Setting B=A

Configures independent or ganged volume control and muting of the analog front end.

6.11.2 Digital MUX

Selects the signal source for the ADC serial port

6.11.3 Digital Sum

Configures a mix/swap of ADCA and ADCB.

76543210

Reserved Reserved Reserved Reserved HPFB_CF1 HPFB_CF0 HPFA_CF1 HPFA_CF0

HPFx_CF[1:0] HPF Corner Frequency Setting (Fs=48 kHz)

00 Normal setting as specified in “ADC Digital Filter Characteristics” on page 14

01 119 Hz

10 236 Hz

11 464 Hz

76543210

ADCB=A DIGMUX DIGSUM1 DIGSUM0 INV_ADCB INV_ADCA ADCBMUTE ADCAMUTE

ADCB=A Single Volume Control Affected Volume Controls

0Disabled ADCxVOL[7:0] (“ADCx Volume” on page 57),

ADCxMUTE (“ADC Mute” on page 51),

ALC and Limiter Attack/Release (page 66 to page 68)

MICxGAIN[4:0] (“MICx Gain” on page 55),

PGAxVOL[5:0] (“PGAx Volume” on page 56),

PASSxVOL[7:0] (“Passthrough x Volume” on page 57)

1 Enabled

DIGMUX SDOUT Signal Source

0ADC

1DSP

DIGSUM[1:0] Serial Output Signal

Left Channel Right Channel

00 ADCA ADCB

01 (ADCA + ADCB)/2 (ADCA + ADCB)/2

10 (ADCA - ADCB)/2 (ADCA - ADCB)/2

11 ADCB ADCA

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6.11.4 Invert ADC Signal Polarity

Configures the polarity of the ADC signal.

6.11.5 ADC Mute

Configures a digital mute on ADC channel x.

Note: When the ADCxMUTE bit is enabled, the PGA will automatically apply 6 dB of attenuation.

6.12 Playback Control 1 (Address 0Dh)

6.12.1 Headphone Analog Gain

Selects the gain multiplier for the headphone/lin e outputs.

Note: Refer to “Line Output Voltage Level Characteri stics” on page 20 and “Headphone Outp ut Power

Characteristics” on page 19.

6.12.2 Playback Volume Setting B=A

Configures independent or ganged volume control of all playback channels.

INV_ADCx ADC Signal Polarity

0Not Inverted

1 Inverted

ADCxMUTE ADC Mute

0Disabled

1 Enabled

76543210

HPGAIN2 HPGAIN1 HPGAIN0 PLYBCKB=A INV_PCMB INV_PCMA MSTBMUTE MSTAMUTE

HPGAIN[2:0] Headphone/Line Gain Setting (G)

000 0.3959

001 0.4571

010 0.5111

011 0.6047

100 0.7099

101 0.8399

110 1.000

111 1.1430

PLYBCKB=A Single Volume Control Affected Volume Controls

0Disabled HPxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),

AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),

PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),

MSTxVOL[7:0] (“Master Volume Control” on page 63),

HPxVOL[7:0] (“Headphone Volume Control” on page 63)

1 Enabled

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6.12.3 Invert PCM Signal Polarity

Configures the polarity of the digital input signal.

6.12.4 Master Playback Mute

Configures a digital mute on the ma ster volume control for channel x.

Note: The muting function is affected by the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC

(“Digital Zero Cross” on page 53) bits.

6.13 Miscellaneous Controls (Address 0Eh)

6.13.1 Passthrough Analog

Configures an analog passthrough from the PGA inputs to the headphone/lin e outputs.

Notes:

1. The Passthrough volume contro l is realized using a combina tion of the PGA volume control settings

(“PGAx Volume” on page 56) and the headphone amplifier volume control settings (hidden). When

passthrough is enabled and the PGA to ADC path is selected, the signal seen by the ADC will change

depending on the passthrough volume setting.

6.13.2 Passthrough Mute

Configures an analog mute on the ch annel x analog in to analog out passthrough.

6.13.3 Freeze Registers

Configures a hold on all register settings.

INV_PCMx PCM Signal Polarity

0Not Inverted

1 Inverted

MSTxMUTE Master Mute

0Not Inverted

1 Inverted

76543210

PASSTHRUB PASSTHRUA PASSBMUTE PASSAMUTE FREEZE DEEMPH DIGSFT DIGZC

PASSTHRUx Analog In Routed to HP/Line Output

0Disabled

1 Enabled

PASSxMUTE Passthrough Mute

0Disabled

1 Enabled

FREEZE Control Port Status

0Register changes take effect immediately

1Modifications may be made to all control port registers without the changes taking effect until after the

FREEZE is disabled.

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6.13.4 HP/Speaker De-emphasis

Configures a 15µs/50µs digital de-emphasis filte r response on the headphone/lin e and speaker outputs.

6.13.5 Digital Soft Ramp

Configures an incremental volume ramp from the current level to the new level at the specified rate.

Notes:

1. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to

occur with a soft ramp only when bits 7 and 6 in register 29h are set to ‘00’b.

6.13.6 Digital Zero Cross

Configures when the signal level changes occur for the digital volume controls.

Notes:

1. If the signal does not encounter a zero crossing, the requested volume change will occur after a

timeout period be tween 1 024 and 2048 sample pe riods (21.3 ms to 42.7 ms at 48 kHz samp le rate).

2. The zero cross function is independently monitored and implemented for each channel.

3. The DIS_LIMSFT bit (“Limiter Soft Ramp Disable” on page 65) is ignored when zero cross is en abled.

4. When the DIGSFT bit is enabled, the Master Volume (MSTxVOL[7:0]) transitions are guaranteed to

occur on a zero crossing only when bits 7 and 6 in register 29h are set to ‘00’b.

DEEMPHASIS Control Port Status

0Disabled

1 Enabled

DIGSFT Volume Changes Affected Digital Volume Controls

0 Do not occur with a soft ramp MSTxMUTE (“Master Playback Mute” on page 52),

HPxMUTE, SPKxMUTE (“Playback Control 2 (Address 0Fh)” on page 54),

ADCxVOL[7:0] (“ADCx Volume” on page 57),

AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),

PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),

MSTxVOL[7:0] (“Master Volume Control” on page 63),

HPxVOL[7:0] (“Headphone Volume Control” on page 63),

SPKxVOL[7:0] (“Speaker Volume Control” on page 64),

ALC and Limiter Attack/Release (page 66 to page 68)

Beep Volume (“Beep Volume” on page 61)

1Occur with a soft ramp

Ramp Rate: 1/8 dB every LRCK cycle

DIGZC Volume Changes Affected Digital Volume Controls

0Do not occur on a zero cross-

ing MSTxMUTE (“Master Playback Mute” on page 52),

AMIXxMUTE, AMIXxVOL[7:0] (“ADC Mixer Channel x Volume” on page 58),

PMIXxMUTE, PMIXxVOL[7:0] (“PCM Mixer Channel x Volume” on page 58),

MSTxVOL[7:0] (“Master Volume Control” on page 63),

ALC and Limiter Attack/Release (page 66 to page 68)

Beep Volume (“Beep Volume” on page 61)

1 Occur on a zero crossing

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6.14 Playback Control 2 (Address 0Fh)

6.14.1 Headphone Mute

Configures a digital mute on he adphone channel x.

6.14.2 Speaker Mute

Configures a digital mute on speaker channel x.

6.14.3 Speaker Volume Setting B=A

Configures independe nt or ganged volume control of the speaker output.

6.14.4 Speaker Channel Swap

Configures a channel swa p on the speaker channels.

6.14.5 Speaker MONO Control

Configures a parallel full-bridge output for the speaker channels.

6.14.6 Speaker Mute 50/50 Control

Configures how the speaker channels mute.

76543210

HPBMUTE HPAMUTE SPKBMUTE SPKAMUTE SPKB=A SPKSWAP SPKMONO MUTE50/50

HPxMUTE Headphone Mute

0Disabled

1 Enabled

SPKxMUTE Speaker Mute

0Disabled

1 Enabled

SPKB=A Single Volume Control Affected Volume Controls

0Disabled SPKxMUTE (“Speaker Mute” on page 54),

SPKxVOL[7:0] (“Speaker Volume Control” on page 64)

1 Enabled

SPKSWAP Speaker Output

0Channel A

1 Channel B

Application: “Mono Speaker Output Configuration” on page 33

SPKMONO Parallel Full Bridge Output

0Disabled

1 Enabled

Application: “Mono Speaker Output Configuration” on page 33

MUTE50/50 Speaker Mute 50/50

0Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.

1Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is

enabled.

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6.15 MICx Amp Control:MIC A (Address 10h) & MIC B (Address 11h)

6.15.1 MIC x Select

Selects one of two single-ended MIC inputs on channel x.

6.15.2 MICx Configuration

Configures the input topology for MICx.

6.15.3 MICx Gain

Sets the gain of the microphone pre-amplifier.

6.16 PGAx Vol. & ALCx Transition Ctl.:

ALC, PGA A (Address 12h) & ALC, PGA B (Address 13h)

6.16.1 ALCx Soft Ramp Disable

Configures an ove r rid e of the an alo g soft ram p se ttin g.

76543210

Reserved MICxSEL MICxCFG MICxGAIN4 MICxGAIN3 MICxGAIN2 MICxGAIN1 MICxGAIN0

MICxSEL MIC x Selection

0MIC 1x

1 MIC 2x

Application: “MIC Inputs” on page 27

MICxCFG MIC Input Topology

0Single-Ended

1 Differential

Application: “MIC Inputs” on page 27

MICxGAIN[4:0] Gain

1 1111 32 dB

... ...

1 0000 32 dB

0 1111 30.5 dB

0 1110 30 dB

... ...

0 0000 16 dB

Step Size: 1 dB (unless otherwise noted)

Application: “MIC Inputs” on page 27

76543210

ALCxSRDIS ALCxZCDIS PGAxVOL5 PGAxVOL4 PGAxVOL3 PGAxVOL2 PGAxVOL1 PGAxVOL0

ALCxSRDIS ALC Soft Ramp Disable

0OFF; ALC Attack Rate is dictated by the ANLGSFT (“Ch. x Analog Soft Ramp” on page 49) setting

1 ON; ALC volume changes take effect in one step, regardless of the ANLGSFT setting.

Application: “Automatic Level Control (ALC)” on page 27

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6.16.2 ALCx Zero Cross Disable

Configures an override of the analog zero cross setting.

6.16.3 PGAx Volume

Sets the volume/gain of the Programmable Gain Amplifier (PGA).

Note: The PGAxVOL bits are ignored when the PASSTHRUx bit (“Passthrough Analog ” on page 52) is

enabled.

ALCxZCDIS ALC Zero Cross Disable

0OFF; ALC Attack Rate is dictated by the ANLGZC (“Ch. x Analog Zero C ross” on page 49) setting

1 ON; ALC volume changes take effect at any time, regardless of the ANLGZC setting.

Application: “Automatic Level Control (ALC)” on page 27

PGAxVOL[5:0] Volume

01 1111 12 dB

... ...

01 1000 12 dB

... ...

00 0001 +0.5 dB

00 0000 0 dB

11 1111 -0.5 dB

... ...

10 1000 -6.0 dB

... ...

10 0000 -6.0 dB

Step Size: 0.5 dB

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6.17 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)

6.17.1 Passthrough x Volume

Sets the volume/gain of the signal routed from the PGA to the headphone/line output.

Notes:

1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 52) is disabled.

2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD,

and 0xB9 are not guaranteed to be monotonic.

6.18 ADCx Volume Control: ADCAVOL (Address 16h) & ADCBVOL (Address 17h)

6.18.1 ADCx Volume

Sets the volume of the ADC signal out the serial data output (SDOUT).

76543210

PASSxVOL7 PASSxVOL6 PASSxVOL5 PASSxVOL4 PASSxVOL3 PASSxVOL2 PASSxVOL1 PASSxVOL0

PASSxVOL[7:0] Gain

0111 1111 12 dB

... ...

0001 1000 12 dB

... ...

0000 0001 +0.5 dB

0000 0000 0 dB

11111 1111 -0.5 dB

... ...

1000 1000 -60.0 dB

... ...

1000 0000 -60.0 dB

Step Size: 0.5 dB (approximate)

Application: “Analog In to Analog Out Passthrough” on page 32

76543210

ADCAVOL7 ADCAVOL6 ADCAVOL5 ADCAVOL4 ADCAVOL3 ADCAVOL2 ADCAVOL1 ADCAVOL0

ADCxVOL[7:0] Volume

0111 1111 24 dB

... ...

0001 1000 24 dB

... ...

0000 0000 0 dB

1111 1111 -1.0 dB

1111 1110 -2.0 dB

... ...

1010 0000 -96.0 dB

... ...

1000 0000 -96.0 dB

Step Size: 1.0 dB

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6.19 ADCx Mixer Volume: ADCA (Address 18h) & ADCB (Address 19h)

6.19.1 ADC Mixer Channel x Mute

Configures a digital mute on the ADC mix in the DSP.

6.19.2 ADC Mixer Channel x Volume

Sets the volume/gain of the ADC mix in the DSP.

6.20 PCMx Mixer Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)

6.20.1 PCM Mixer Channel x Mute

Configures a digital mute on the PCM mix from the serial data input (SDIN) to the DSP.

6.20.2 PCM Mixer Channel x Volume

Sets the volume/gain of the PCM mix from the serial data input (SDIN) to th e DSP.

76543210

AMIXxMUTE AMIXxVOL6 AMIXxVOL5 AMIXxVOL4 AMIXxVOL3 AMIXxVOL2 AMIXxVOL1 AMIXxVOL0

AMIXxMUTE ADC Mixer Mute

0 Disabled

1Enabled

AMIXxVOL[6:0] Volume

001 1000 +12.0 dB

... ...

000 0001 +0.5 dB

000 0000 0 dB

111 1111 -0.5 dB

... ...

001 1001 -51.5 dB

Ste p Size: 0.5 dB

76543210

PMIXxMUTE PMIXxVOL6 PMIXxVOL5 PMIXxVOL4 PMIXxVOL3 PMIXxVOL2 PMIXxVOL1 PMIXxVOL0

PMIXxMUTE PCM Mixer Mute

0Disabled

1 Enabled

PMIXxVOL[6:0] Volume

001 1000 +12.0 dB

... ...

000 0001 +0.5 dB

000 0000 0 dB

111 1111 -0.5 dB

... ...

001 1001 -51.5 dB

Step Size: 0.5 dB

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6.21 Beep Frequency & On Time (Address 1Ch)

6.21.1 Beep Frequency

Sets the freque n cy of th e be ep sign a l.

Notes:

1. This setting must not change when BEEP is enabled.

2. Beep frequency will scale directly with sample rate, Fs, but is fixed at the nominal Fs within each

speed mode.

76543210

FREQ3 FREQ2 FREQ1 FREQ0 ONTIME3 ONTIME2 ONTIME1 ONTIME0

FREQ[3:0] Frequency (Fs = 12, 24, 48 or 96 kHz) Pitch

0000 260.87 Hz C4

0001 521.74 Hz C5

0010 585.37 Hz D5

0011 666.67 Hz E5

0100 705.88 Hz F5

0101 774.19 Hz G5

0110 888.89 Hz A5

0111 1000.00 Hz B5

1000 1043.48 Hz C6

1001 1200.00 Hz D6

1010 1333.33 Hz E6

1011 1411.76 Hz F6

1100 1600.00 Hz G6

1101 1714.29 Hz A6

1110 2000.00 Hz B6

1111 2181.82 Hz C7

Application: “Beep Generator” on page 30

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6.21.2 Beep On Time

Sets the on duration of the beep signal.

Notes:

1. This setting must not change when BEEP is enabled.

2. Beep on time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed

mode.

6.22 Beep Volume & Off Time (Address 1Dh)

6.22.1 Beep Off Time

Sets the off duration of the beep signal.

Notes:

1. This setting must not change when BEEP is enabled.

2. Beep off time will scale inversely with sample rate, Fs, but is fixed at the nominal Fs within each speed

mode.

ONTIME[3:0] On Time (Fs = 12, 24, 48 or 96 kHz)

0000 ~86 ms

0001 ~430 ms

0010 ~780 ms

0011 ~1.20 s

0100 ~1.50 s

0101 ~1.80 s

0110 ~2.20 s

0111 ~2.50 s

1000 ~2.80 s

1001 ~3.20 s

1010 ~3.50 s

1011 ~3.80 s

1100 ~4.20 s

1101 ~4.50 s

1110 ~4.80 s

1111 ~5.20 s

Application: “Beep Generator” on page 30

76543210

OFFTIME2 OFFTIME1 OFFTIME0 BPVOL4 BPVOL3 BPVOL2 BPVOL1 BPVOL0

OFFTIME[2:0] Off Time (Fs = 48 or 96 kHz)

000 ~1.23 s

001 ~2.58 s

010 ~3.90 s

011 ~5.20 s

100 ~6.60 s

101 ~8.05 s

110 ~9.35 s

111 ~10.80 s

Application: “Beep Generator” on page 30

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6.22.2 Beep Volume

Sets the volume of the beep signal.

Note: This setting must not change when BEEP is enabled.

6.23 Beep & Tone Configuration (Address 1Eh)

6.23.1 Beep Configuration

Configures a beep mixed with the HP/Line and SPK output.

Notes:

1. When used in analog pass-through mode, the output alternates between the signal from the PGA and

the beep signal. The beep signa l does not mix with the analog signal from the PGA.

2. Re-engaging the beep before it has completed its initial cycle will cause the beep signal to remain ON

for the maximum ONTIME duration.

6.23.2 Beep Mix Disable

Configures how the beep mixes with the serial data input.

Note: This setting must not change when BEEP is enabled.

BEEPVOL[4:0] Gain

00110 +6.0 dB

··· ···

00000 -6 dB

11111 -8 dB

11110 -10 dB

··· ···

00111 -56 dB

Step Size: 2 dB

Application: “Beep Generator” on page 30

76543210

BEEP1 BEEP0 BEEPMIXDIS TREBCF1 TREBCF0 BASSCF1 BASSCF0 TCEN

BEEP[1:0] Beep Occurrence

00 Off

01 Single

10 Multiple

11 Continuous

Application: “Beep Generator” on page 30

BEEPMIXDIS Beep Output to HP/Line and Speaker

0Mix Enabled; The beep signal mixes with the digital signal from the serial data input.

1Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The

beep signal does not mix with the digital signal from the serial data input.

Application: “Beep Generator” on page 30

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6.23.3 Treble Corner Frequency

Sets the corner frequency (-3 dB point) for the treble shel ving filter.

6.23.4 Bass Corner Frequency

Sets the corner frequency (-3 dB point) for the bass shelving filter.

6.23.5 Tone Control Enable

Configures the treble and bass activation.

6.24 Tone Control (Address 1Fh)

6.24.1 Treble Gain

Sets the gain of the treble shelving filter.

TREBCF[1:0] Treble Corner Frequency Setting

00 5 kHz

01 7 kHz

10 10 kHz

11 15 kHz

BASSCF[1:0] Bass Corner Frequency Setting

00 50 Hz

01 100 Hz

10 200 Hz

11 250 Hz

TCEN Bass and Treble Control

0Disabled

1 Enabled

Application: “Beep Generator” on page 30

76543210

TREB3 TREB2 TREB1 TREB0 BASS3 BASS2 BASS1 BASS0

TREB[3:0] Gain Setting

0000 +12.0 dB

··· ···

0111 +1.5 dB

1000 0 dB

1001 -1.5 dB

··· ···

1111 -10.5 dB

Step Size: 1.5 dB

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6.24.2 Bass Gain

Sets the gain of the bass shelving filter.

6.25 Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)

6.25.1 Master Volume Control

Sets the volume of the signal out the DSP.

6.26 Headphone Volume Control: HPA (Address 22h) & HPB (Address 23h)

6.26.1 Headphone Volume Control

Sets the volume of the signal out the DAC.

TREB[3:0] Gain Setting

0000 +12.0 dB

··· ···

0111 +1.5 dB

1000 0 dB

1001 -1.5 dB

··· ···

1111 -10.5 dB

Step Size: 1.5 dB

76543210

MSTxVOL7 MSTxVOL6 MSTxVOL5 MSTxVOL4 MSTxVOL3 MSTxVOL2 MSTxVOL1 MSTxVOL0

MSTxVOL[7:0] Master Volume

0001 1000 +12.0 dB

··· ···

0000 0000 0 dB

1111 1111 -0.5 dB

1111 1110 -1.0 dB

··· ···

0011 0100 -102 dB

··· ···

0001 1001 -102 dB

Step Size: 0.5 dB

76543210

HPxVOL7 HPxVOL6 HPxVOL5 HPxVOL4 HPxVOL3 HPxVOL2 HPxVOL1 HPxVOL0

HPxVOL[7:0] Headphone Volume

0000 0000 0 dB

1111 1111 -0.5 dB

1111 1110 -1.0 dB

··· ···

0011 0100 -96.0 dB

··· ···

0000 0001 Muted

Step Size: 0.5 dB

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6.27 Speaker Volume Control: SPKA (Address 24h) & SPKB (Address 25h)

6.27.1 Speaker Volume Control

Sets the volume of the signal out the PWM modulator.

Note: The maximum step size error is ±0.15 dB.

6.28 ADC & PCM Channel Mixer (Address 26h)

6.28.1 PCM Mix Channel Swap

Configures a mix/swap of the PCM Mix to the headphone/line or speaker outputs.

6.28.2 ADC Mix Channel Swap

Configures a mix/swap of the ADC Mix to the headphone/line or speaker outputs.

76543210

SPKxVOL7 SPKxVOL6 SPKxVOL5 SPKxVOL4 SPKxVOL3 SPKxVOL2 SPKxVOL1 SPKxVOL0

SPKxVOL[7:0] Speaker Volume

0000 0000 0 dB

1111 1111 -0.5 dB

1111 1110 -1.0 dB

··· ···

0100 0000 -96.0 dB

··· ···

0000 0001 Muted

Step Size: 0.5 dB

76543210

PCMASWP1 PCMASWP0 PCMBSWP1 PCMBSWP0 ADCASWP1 ADCASWP0 ADCBSWP1 ADCBSWP0

PCMxSWP[1:0] PCM Mix to HP/LINEOUTA PCM Mix to HP/LINEOUTB

00 Left Right

01 (Left + Right)/2 (Left + Right)/2

11 Right Left

ADCxSWP[1:0] ADC Mix to HP/LINEOUTA Channel ADC Mix to HP/LINEOUTB Channel

00 Left Right

01 (Left + Right)/2 (Left + Right)/2

11 Right Left

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6.29 Limiter Control 1, Min/Max Thresholds (Address 27h)

6.29.1 Limiter Maximum Threshold

Sets the maximum level, below full scale, at which to limit and attenuate the output signal at the attack

rate (LIMARATE - “Limiter Release Rate” on page 66).

Note: Bass, Treble, and dig ital g ain settin gs tha t bo ost the sig nal be yo nd the maximu m thr eshol d may

trigger an attack.

6.29.2 Limiter Cushion Threshold

Sets the minimum level at which to disengage the Limiter’s attenuation at the release rate (LIMRRATE -

“Limiter Release Rate” on page 66) until levels lie between th e LM AX an d CUSH thre sho l ds.

Note: This setting is usually set slightly be low the LM AX th re shold .

6.29.3 Limiter Soft Ramp Disable

Configures an over rid e of th e dig ita l soft ram p settin g.

Note: This bit is ignored when the DIGZC (“Digital Zero Cross” on page 53) is enabled.

76543210

LMAX2 LMAX1 LMAX0 CUSH2 CUSH1 CUSH0 LIMSRDIS LIMZCDIS

LMAX[2:0] Threshold Setting

000 0 dB

001 -3 dB

010 -6 dB

011 -9 dB

100 -12 dB

101 -18 dB

110 -24 dB

111 -30 dB

Application: “Limiter” on page 31

CUSH[2:0] Threshold Setting

000 0 dB

001 -3 dB

010 -6 dB

011 -9 dB

100 -12 dB

101 -18 dB

110 -24 dB

111 -30 dB

Application: “Limiter” on page 31

LIMSRDIS Limiter Soft Ramp Disable

0OFF; Limiter Attack Rate is dictated by the DIGSFT (“Digital Soft Ramp” on page 53) setting

1 ON; Limiter volume changes take effect in one step, regardless of the DIGSFT setting.

Application: “Limiter” on page 31

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6.29.4 Limiter Zero Cross Disable

Configures an override of the digital zero-cross setting.

6.30 Limiter Control 2, Release Rate (Address 28h)

6.30.1 Peak Detect and Limiter

Configures the peak-de tect and limiter circuitry.

6.30.2 Peak Signal Limit All Channels

Sets how channels are attenuated when the limiter is enabled.

6.30.3 Limiter Release Rate

Sets the rate at which the limiter relea ses the dig ita l attenuation from leve ls below the CUSH[2:0 ] thresh-

old (“Limiter Cushion Threshold” on page 65) and returns the analog output level t o the MSTxVOL[7:0]

(“Master Volume Control” on pag e 63) setting.

Note: The limiter release rate is user-selectable but is also a function of the sampling frequency, Fs,

and the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) set t ing.

LIMZCDIS Limiter Zero Cross Disable

0OFF; Limiter Attack Rate is dictated by the DIGZC (“Digital Zero Cross” on page 53) setting

1 ON; Limiter volume changes take effect in one step, regardless of the DIGZC setting.

Application: “Limiter” on page 31

76543210

LIMIT LIMIT_ALL LIMRRATE5 LIMRRATE4 LIMRRATE3 LIMRRATE2 LIMRRATE1 LIMRRATE0

LIMIT Limiter Status

0Disabled

1 Enabled

Application: “Limiter” on page 31

LIMIT_ALL Limiter action:

Apply the necessary attenuation on a specific channel only when the signal amplitude on that specific chan-

nel rises above LMAX.

Remove attenuation on a specific channel only when the signal amplitude on that specific channel falls below

CUSH.

1Apply the necessary attenuation on BOTH channels when the signal amplitude on any ONE channel rises

above LMAX.

Remove attenuation on BOTH channels only when the signal amplitude on BOTH channels fall below CUSH.

Application: “Limiter” on page 31

LIMRRATE[5:0] Release Time

00 0000 Fastest Release

··· ···

11 1111 Slowest Release

Application: “Limiter” on page 31

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6.31 Limiter Attack Rate (Address 29h)

6.31.1 Limiter Attack Rate

Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold

(“Limiter Maximum Threshold” on page 65).

Note: The limiter attack rate is user-selectable b ut is also a function of the sampling frequency, Fs, and

the DIGSFT (“Digital Soft Ramp” on page 53) and DIGZC (“Digital Zero Cross” on page 53) setting unless

the respective disable bit (“Limiter Soft Ramp Disable” on page 65 or “Limiter Zero Cross Disable” on

page 66) is enabled.

6.32 ALC Enable & Attack Rate (Address 2Ah)

6.32.1 ALCx Enable

Configures the automatic level controller.

Note: The ALC is not available in passthrough mode.

6.32.2 ALC Attack Rate

Sets the rate at which the ALC applies analog and/or digita l attenuation from levels above the AMAX[2:0]

threshold (“ALC Maximum Threshold” on page 68).

Note: The ALC attack ra te is use r-se lecta ble but is a lso a function of the sampling frequency, Fs, and

the ANLGSFTx (“Ch. x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on

page 49) setting unless the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero

Cross Disable” on page 56) is enabled.

76543210

Reserved Reserved LIMARATE5 LIMARATE4 LIMARATE3 LIMARATE2 LIMARATE1 LIMARATE0

LIMARATE[5:0] Attack Time

00 0000 Fastest Attack

··· ···

11 1111 Slowest Attack

Application: “Limiter” on page 31

76543210

ALCB ALCA ALCARATE5 AALCRATE4 ALCARATE3 ALCARATE2 ALCARATE1 ALCARATE0

ALC ALC Status

0Disabled

1 Enabled

Application: “Automatic Level Control (ALC)” on page 27

LIMARATE[5:0] Attack Time

00 0000 Fastest Attack

··· ···

11 1111 Slowest Attack

Application: “Automatic Level Control (ALC)” on page 27

68 DS680F1

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6.33 ALC Release Rate (Address 2Bh)

6.33.1 ALC Release Rate

Sets the rate at which the ALC releases the analog and/or digital attenuation from levels below the

MIN[2:0] threshold (“ALC Minimum Threshold” on page 69) and returns the signal level to the PGAx-

VOL[5:0] (“PGAx Volume” on page 56) and ADC xVO L[ 7:0 ] (“ADCx Volume” on page 57) setting.

Notes:

1. The ALC release rate is user-selectable but is also a function of the sampling frequen cy, Fs, and the

ANLGSFTx (“Ch. x Analog Soft Ramp” on page 4 9) and ANLGZCx (“Ch. x Analog Zero Cross” on

page 49) setting.

2. The Release Rate setting must always be slower than the Attack Rate.

6.34 ALC Threshold (Address 2Ch)

6.34.1 ALC Maximum Threshold

Sets the maximum level, below full scale, at which to limit and atte nuate the input signal a t the attack r ate

(ALCARATE - “ALC Attack Rate” on page 67).

76543210

Reserved Reserved ALCRRATE5 ALCRRATE4 ALCRRATE3 ALCRRATE2 ALCRRATE1 ALCRRATE0

ALCRRATE[5:0] Release Time

00 0000 Fastest Release

··· ···

11 1111 Slowest Release

Application: “Automatic Level Control (ALC)” on page 27

76543210

ALCMAX2 ALCMAX1 ALCMAX0 ALCMIN2 ALCMIN1 ALCMIN0 Reserved Reserved

MAX[2:0] Threshold Setting

000 0 dB

001 -3 dB

010 -6 dB

011 -9 dB

100 -12 dB

101 -18 dB

110 -24 dB

111 -30 dB

Application: “Automatic Level Control (ALC)” on page 27

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6.34.2 ALC Minimum Threshold

Sets the minimum level at which to disengage the ALC’s attenuation or amplify the input signal at the re-

lease rate (ALCRRATE - “ALC Rele as e Ra te ” on pa g e 68) until lev els lie between the ALCMAX and AL-

CMIN thresholds.

Notes:

1. This setting is usually set slightly below the ALCMAX threshold.

6.35 Noise Gate Control (Address 2Dh)

6.35.1 Noise Gate All Channels

Sets which channels are attenuated when clipping on any single channel occurs.

6.35.2 Noise Gate Enable

Configures the noise gate.

ALCMIN[2:0] Threshold Setting

000 0 dB

001 -3 dB

010 -6 dB

011 -9 dB

100 -12 dB

101 -18 dB

110 -24 dB

111 -30 dB

Application: “Automatic Level Control (ALC)” on page 27

76543210

NGALL NG NG_BOOST THRESH2 THRESH1 THRESH0 NGDELAY1 NGDELAY0

NGALL Noise Gate triggered by:

0Individual channel; Any channel that falls below the threshold setting triggers the noise gate attenuation for

both channels.

1Both channels A & B; Both channels must fall below the threshold setting for the noise gate attenuation to

take effect.

Application: “Noise Gate” on page 28

NG Noise Gate Status

0Disabled

1 Enabled

Application: “Noise Gate” on page 28

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6.35.3 Noise Gate Threshold and Boost

THRESH sets the threshold level of the noise gate. Input signals below the threshold level will be attenu-

ated to -96 dB. NG_BOOST configures a +30 dB boost to the threshold settings.

6.35.4 Noise Gate Delay Timing

Sets the delay time before the noise gate attacks.

Note: The Noise Gate attack rate is a functio n of the sampling frequency, Fs, and the ANLGSFTx (“Ch.

x Analog Soft Ramp” on page 49) and ANLGZCx (“Ch. x Analog Zero Cross” on page 49) setting unless

the respective disable bit (“ALCx Soft Ramp Disable” on page 55 or “ALCx Zero Cross Disable” on

page 56) is enabled.

6.36 Status (Address 2Eh) (Read Only)

For all bits in this register, a “1” means the associated error condition has occu rred at leas t once since th e

of the register. Reading the register resets all bits to 0.

6.36.1 Serial Port Clock Error (Read Only)

Indicates the status of the MCLK to LRCK ratio.

Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-

nizes.

THRESH[2:0] Minimum Setting (NG_BOOST = ‘0’b) Minimum Setting (NG_BOOST = ‘1’b)

000 -64 dB -34 dB

001 -67 dB -37 dB

010 -70 dB -40 dB

011 -73 dB -43 dB

100 -76 dB -46 dB

101 -82 dB -52 dB

110 Reserved -58 dB

111 Reserved -64 dB

Application: “Noise Gate” on page 28

NGDELAY[1:0] Delay Setting

00 50 ms

01 100 ms

10 150 ms

11 200 ms

Application: “Noise Gate” on page 28

76543210

Reserved SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL ADCAOVFL ADCBOVFL

SPCLKERR Serial Port Clock Status:

0 MCLK/LRCK ratio is valid.

1 MCLK/LRCK ratio is not valid.

Application: “Serial Port Clocking” on page 34

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6.36.2 DSP Engine Overflow (Read Only)

Indicates the over-range status in the DSP data path.

6.36.3 PCMx Overflow (Read Only)

Indicates the over-range status in the PCM mix data path.

6.36.4 ADCx Overflow (Read Only)

Indicates the over-range status in the ADC signal path.

6.37 Battery Compensation (Address 2Fh)

6.37.1 Battery Compensation

Configures automatic adjustment of the speaker volume when VP deviates from VPREF[3:0].

6.37.2 VP Monitor

Configures the internal ADC that monitors the VP voltage level.

Notes:

1. The internal ADC that monitors the VP supp ly is enabled automatica lly when BATTCMP is en ab led,

regardless of the VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be

enabled by enabling VPMONITOR; this provides a convenient battery monitor without enabling

battery compensation.

2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting.

DSPxOVFL DSP Overflow Status:

0 No digital clipping has occurred in the data path after the DSP.

1 Digital clipping has occurred in the data path after the DSP.

Application: “Analog Outputs” on page 29

PCMxOVFL PCM Overflow Status:

0No digital clipping has occurred in the data p ath of the PCM mix (“PCM Mixer Channel x Volume” on page 58)

of the DSP.

1 Digital clipping has occurred in the data path of the PCM mix of the DSP.

Application: “Analog Outputs” on page 29

ADCxOVFL ADC Overflow Status:

0 No clipping has occurred anywhere in the ADC signal path.

1 Clipping has occurred in the ADC signal path.

Application: “Analog Inputs” on page 26

76543210

BATTCMP VPMONITOR Reserved Reserved VPREF3 VPREF2 VPREF1 VPREF0

BATTCMP Automatic Battery Compensation

0Disabled

1 Enabled

Application: “Maintaining a Desired Output Level” on page 34

VPMONITOR VP ADC Status

0Disabled

1 Enabled

72 DS680F1

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6.37.3 VP Reference

Sets the desired VP reference used for battery compensa tion.

6.38 VP Battery Level (Address 30h) (Read Only)

6.38.1 VP Voltage Level (Read Only)

Indicates the unsig ne d VP voltage lev el.

6.39 Speaker Status (Address 31h) (Read Only)

6.39.1 Speaker Current Load Status (Read Only)

Indicates whet he r or not an y of the sp ea ker ou tp uts is shorted to groun d .

VPREF[3:0] Desired VP used to calculate the required attenuation on the speaker output:

(for VA = 1.8 V)

0000 1.5 V

0001 2.0 V

0010 2.5 V

0011 3.0 V

0100 3.5 V

0101 4.0 V

0110 4.5 V

0111 5.0 V (for VA = 2.5 V)

1000 1.5 V

1001 2.0 V

1010 2.5 V

1011 3.0 V

1100 3.5 V

1101 4.0 V

1110 4.5 V

1111 5.0 V

Application: “VP Battery Compensation” on page 33

76543210

VPLVL7 VPLVL6 VPLVL5 VPLVL4 VPLVL3 VPLVL2 VPLVL1 VPLVL0

VPLVL[7:0] VP Voltage

...

0101 1110 3.0 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.

...

0111 0010 3.7 V (for VA = 2.0 V); apply formula using actual VA voltage to calculate VP voltage.

...

Formula: VP Voltage = (Binary representation of VPLVL[7:0]) * VA / 63.3

76543210

Reserved Reserved SPKASHRT SPKBSHRT SPKR/HP Reserved Reserved Reserved

SPKxSHRT Speaker Output Load

0 No overload detected

1 Overload detected

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6.39.2 SPKR/HP Pin Status (Read Only)

Indicates the status of the SPKR/HP pin.

6.40 Charge Pump Frequency (Address 34h)

6.40.1 Charge Pump Frequency

Sets the charge pump frequency on FLYN and FLYP.

Note: The headphone output THD+N performance may be affected.

SPKR/HP Pin State

0 Pulled Low

1 Pulled High

76543210

CHGFREQ3 CHGFREQ2 CHGFREQ1 CHGFREQ0 Reserved Reserved Reserved Reserved

CHGFREQ[3:0] N

0000 0

...

0101 5

...

1111 15

Formula: Frequency = (64xFs)/(N+2)

74 DS680F1

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7. ANALOG PERFORMANCE PLOTS

7.1 Headphone THD+N versus Output Power Plots

Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement band-

width is 10 Hz to 20 kHz; Fs = 48 kHz.

G = 0.6047

G = 0.7099

G = 0.8399

G = 1.0000

G = 1.1430

Legend

-100

-10

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

080m10m 20m 30m 40m 50m 60m 70m

Figure 22. THD+N vs. Output Power per Channel at 1.8 V (16 Ω load)

VHP = VA = 1.8 V

NOTE: Graph shows the out-

put power per channel (i.e.

Output Power = 23 mW into

single 16 Ω and 46 mW into

stereo 16 Ω with THD+N = -

75 dB).

G = 0.6047

G = 0.7099

G = 0.8399

G = 1.0000

G = 1.1430

Legend

-100

-10

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

-20

-15

080m10m 20m 30m 40m 50m 60m 70m

Figure 23. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load)

VHP = VA = 2.5 V

NOTE: Graph shows the out-

put power per channel (i.e.

Output Power = 44 mW into

single 16 Ω and 88 mW into

stereo 16 Ω with THD+N = -

75 dB).

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G = 0.6047

G = 0.7099

G = 0.8399

G = 1.0000

G = 1.1430

Legend

-100

-20

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

060m6m 12m 18m 24m 30m 36m 42m 48m 54m

Figure 24. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load)

VHP = VA = 1.8 V

NOTE: Graph shows the out-

put power per channel (i.e.

Output Power = 22 mW into

single 32 Ω and 44 mW into

stereo 32 Ω with THD+N = -

75 dB).

G = 0.6047

G = 0.7099

G = 0.8399

G = 1.0000

G = 1.1430

Legend

-100

-20

-95

-90

-85

-80

-75

-70

-65

-60

-55

-50

-45

-40

-35

-30

-25

060m5m 10m 15m 20m 25m 30m 35m 40m 45m 50m 55m

Figure 25. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load)

VHP = VA = 2.5 V

NOTE: Graph shows the out-

put power per channel (i.e.

Output Power = 42 mW into

single 32 Ω and 84 mW into

stereo 32 Ω with THD+N = -

75 dB).

76 DS680F1

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8. EXAMPLE SYSTEM CLOCK FREQUENCIES *The”MCLKDIV2” bit must be enabled.

8.1 Auto Detect Enabled

8.2 Auto Detect Disabled

Sample Rate

LRCK (kHz) MCLK (MHz)

1024x 1536x 2048x* 3072x*

8 8.1920 12.2880 16.3840 24.5760

11.025 11.2896 16.9344 22.5792 33.8688

12 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

512x 768x 1024x* 1536x*

16 8.1920 12.2880 16.3840 24.5760

22.05 11.2896 16.9344 22.5792 33.8688

24 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

256x 384x 512x* 768x*

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688

48 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

128x 192x 256x* 384x*

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688

96 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

512x 768x 1024x 1536x 2048x 3072x

8 - 6.1440 8.1920 12.2880 16.3840 24.5760

11.025 - 8.4672 11.2896 16.9344 22.5792 33.8688

12 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

256x 384x 512x 768x 1024x 1536x

16 - 6.1440 8.1920 12.2880 16.3840 24.5760

22.05 - 8.4672 11.2896 16.9344 22.5792 33.8688

24 6.1440 9.2160 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

256x 384x 512x 768x

32 8.1920 12.2880 16.3840 24.5760

44.1 11.2896 16.9344 22.5792 33.8688

48 12.2880 18.4320 24.5760 36.8640

Sample Rate

LRCK (kHz) MCLK (MHz)

128x 192x 256x 384x

64 8.1920 12.2880 16.3840 24.5760

88.2 11.2896 16.9344 22.5792 33.8688

96 12.2880 18.4320 24.5760 36.8640

DS680F1 77

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9. PCB LAYOUT CONSIDERATIONS

9.1 Power Supply, Grounding

As with any high-reso lution co nverte r, the CS42L52 re quires ca refu l attention to power supply and gr ound-

ing arrangements if its p otential performance is to be realized. Figure 1 o n page 10 shows the reco mmend-

ed power arrangements, with VA and VHP connected to clean supplies VD, which powers the digital

circuitry, may be run from the system logic supply. Alternatively, VD may be powered from the analog supply

via a ferrite bead. In this case, no additional devices should be powered from VD.

Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling

capacitors are recommended. Decoupling capacitors should be as close to the pins of the CS4 2L52 as pos-

sible. The low value ceramic capacitor should be closest to the pin and should be mounted on the same

side of the board as the CS42L52 to minimize inductance effects.

All signals, especially clocks, should be kept away from the FILT+ and VQ pins in order to avoid unwante d

coupling into the modu lators. The FILT+ and VQ d ecoupling capacitors, particularly the 0.1 µF, must be po-

sitioned to minimize the electrical path from FILT+ and AGND. The CDB42L52 evaluation board demon-

strates the optimum layout and power supply ar rangements.

9.2 QFN Thermal Pad

The CS42L52 is available in a compact QFN package. The underside of the QFN package reveals a large

metal pad that serves as a thermal relief to provide for maximum h eat dissip ation. This pad must mate with

an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of

vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.

In split ground systems, it is recommended that this thermal pad be connected to AGND for best perfor-

mance. The CS42L52 evaluation board demonstr ates the optimum thermal pad and via configuration.

78 DS680F1

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10.ADC & DAC DIGITAL FILTERS

Figure 26. ADC Passband Ripple Figure 27. ADC Stopband Rejection

Figure 28. ADC Transition Band Figure 29. ADC Transition Band (Detail)

Figure 30. DAC Passband Ripple Figure 31. DAC Stopband

Figure 32. DAC Transition Band Figure 33. DAC Transition Band (Detail)

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11.PARAMETER DEFINITIONS

Dynamic Range

The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified

bandwidth. Dynamic Range is a signal-to-noise ratio mea surement over the specified band width made with

a -60 dBFS signal. 60 dB is added to resulting measurement to refer the measurement to full-scale. This

technique ensu res tha t the distortion co mpone nts are below the noise level and do n ot affect the m easure-

ment. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991,

and the Electronic Industries Association of Japan, EIAJ CP-307 . Exp re sse d in decib els .

Total Harmonic Distortion + Noise

The ratio of the rms value of the signal to the rms sum of all other spectral compon ents over th e specified

band width (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Measured

at -1 and -20 dBFS as suggested in AES17-1991 Annex A.

Frequency Response

A measure of the amplitude response variation from 10 Hz to 20 kHz relative to the amplitude response at

1 kHz. Units in decibels.

Interchannel Isolation

A measure of crosstalk betwe en the left and right cha nnel pairs. Measu red for each ch annel at the conver t-

er's output with no signal to the inpu t under test and a full- scale signal applied to the oth er channel. Units in

decibels.

Interchannel Gain Mismatch

The gain difference between left and right channel pairs. Units in decibels.

Gain Drift

The change in gain value with temperature. Units in ppm/°C.

Offset Error

The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV.

80 DS680F1

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12.PACKAGE DIMENSIONS

1. Dimensioning and tolerance per ASME Y 14.5M-1995.

2. Dimensioning lead width applies to the plated terminal and is measured between 0.20 mm and 0.25 mm

from the terminal tip.

THERMAL CHARACTERISTICS

INCHES MILLIMETERS NOTE

DIM MIN NOM MAX MIN NOM MAX

A----0.0394----1.001

A1 0.0000 -- 0.0020 0.00 -- 0.05 1

b 0.0071 0.0091 0.0110 0.18 0.23 0.28 1,2

D 0.2362 BSC 6.00 BSC 1

D2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1

E 0.2362 BSC 6.00 BSC 1

E2 0.1594 0.1614 0.1634 4.05 4.10 4.15 1

e 0.0197 BSC 0.50 BSC 1

L 0.0118 0.0157 0.0197 0.30 0.40 0.50 1

JEDEC #: MO-220

Controlling Dimension is Millimeters.

Parameter Symbol Min Typ Max Units

Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board θJA -

-44

19 -

-°C/Watt

40L QFN (6 X 6 mm BODY) PACKAGE DRAWING

PIN #1 IDENTIFIER

∅0.50±0.10

LASER MARKING

2.00 REF

PIN #1 CORNER

2.00 REF

DS680F1 81

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13.ORDERING INFORMATION

14.REFERENCES

1. Philips Semiconductor, The I²C-Bus Specification: Version 2.1, January 2000.

http://www.semiconductors.philips.com.

15.REVISION HISTORY

Product Description Package Pb-Free Grade Temp Range Container Order #

CS42L52

Low-Power Stereo

CODEC w/HP and

Speaker Amps for

Portable Apps

40L-QFN Yes Commerci al -40 to +85° C Rail CS42L52-CNZ

Tape & Reel CS42L52-CNZR

Automotive -40 to +105° C Rail CS42L52-DNZ

Tape & Reel CS42L52-DNZR

CDB42L52 CS42L52 Evaluation

Board - No - - - CDB42L52

CRD42L52 CS42L52 Reference

Design - No - - - CRD42L52

Revision Changes

Removed the Thermal Error Detection and Thermal Foldback Feature

Added “Internal Connections” to table in “I/O Pin Characteristics” on page 9.

Added and updated absolute maximum parameters in “Absolute Maximum Ratings” on page 11

Lowered the VP Current Consumption in “Power Consumption” on page 24.

Updated the expected ALC behavior when signals cross the MIN threshold in “Automatic Level Control (ALC)” on

page 27.

Added the Thermal Error Disable control port initialization setting in “Required Initializa tion Settings” on page 37.

Updated note 2 in “Power Down PGAx” on page 42.

Added note in “ADC Mute” on page 51.

Added note in “Digital Soft Ramp” on page 53.

Added notes in “Digital Zero Cross” on page 53.

Updated the ADCB=A, PLYBCKB=A and SPKRB=A descriptions in “Analog Front-End Volume Setting B=A” on

page 50, “Playback Volume Settin g B=A” on page 51, and “Speaker Volume Setting B=A” on page 54.

Corrected the MICxGAIN decode settings in “MICx Gain” on page 55.

Corrected BEEP volume settings to reflect level relative to DAC’s full scale in “Beep Volume” on page 61.

Added note 2 in “VP Monitor” on page 71.

82 DS680F1

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Contacting Cirrus Logic Support

For all product questions and inquiries, contact a Cirrus Logic Sales Representative.

To find one nearest you, go to www.cirrus.com.

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject

to change wi thout notice and is provi ded “AS I S” withou t warrant y of any kind (ex press or implied) . Customer s are ad vised to o btain the latest version of relevant

information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and cond itions of sa le

supplied at the time of order acknow ledgment, inclu ding those pertainin g to warranty, indemnific ation, and limitation of liability. No responsibility is assumed by Cirrus

for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or othe r rights o f third

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copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associate d with the information co ntained herein an d gives con-

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ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY

INDEMNIFY CI RRUS, I TS OFFI CERS, DIRECT ORS, EMPLOY EES, DIST RIBUT ORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT-

TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES .

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks

or service marks of their respective owners.

I²C is a registered trademark of Philips Semiconductor.