MOTOROLA SEMICONDUCTOR TECHNICAL DATA 8-Bit Serial-input/ Parallel-Output Shift Register High-Performance SiliconGate CMOS The MC54/74HC164 is identical in pinout to the LS164. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC54/74HC 164 is an 8-bit, serial input to parallel-output shift register. Two serial data inputs, A1 and A2, are provided so that_one input may be used as a data enable. Data is entered on each rising edge of the . clock. The activelow asynchronous Reset overrides the Clock and Serial Data inputs. Output Drive Capability: 10 LSTTL Loads _- Outputs Directly Interface to CMOS, NMOS, and TTL e Cperating Voltage Range: 2 to6V e Low Input Current: 1 pA e High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A e Chip Complexity: 244 FETs or 61 Equivalent Gates MC54/74HC164 Do Not Use for New Designs THIS DEVICE WILL BE SUPERCEDED BY MG54/74HC164A IN THE SECOND QUARTER OF 1996 een J SUFFIX iil CERAMIC PACKAGE 14 CASE 632-08 : en. N SUFFIX \i PLASTIC PACKAGE 14 CASE 646-06 1 D SUFFIX ue SOIC PACKAGE , CASE 7514-03 ORDERING INFORMATION LOGIC DIAGRAM MC54HCXXXJ Ceramic , MC74HCXXXN Plastic SERIAL | at ty 3 -MC74HOXXXD Soic DATA 2 DATA . T Qa INPUTS | A2- LS op 5 Q PIN ASSIGNMENT 6 H Op | PARALLEL Mie = 14 Vee 10 a. . - Qe | OUTPUTS A2(] 2 13 1 Qy LH g. On, [3 12 [10g 4 | 12 a6 Og 0] 4 11 15 CLOCK > p18 gy, Qc fl 5 10 1 Og 4 Op 6 9 1] RESET ; | GND {] 7 8 [J CLOCK RESET --_- PIN 14=Vec . . PIN 7 = GND FUNCTION TABLE Inputs Outputs Reset| Clock] A1 A2|/Qq Qp... Qy L X Xx XL Li. ek H NP XX No Change H Ss |H DD Qan Q6n H ~~ |D HI] D Qan .. Q@n _ D = data input Qan- QGn = data shifted from the preceding stage on a rising edge at the clock input. 10/95 ms . (MA) MOTOROLA _ 3-221 __ REV? _ . Motorola, Inc. 1995 -e ee = ans [iMC54/74HC164 MAXIMUM RATINGS* Symbol Parameter Value Unit This device contains protection Vv DC Supply Voltage (Referenced to GND -0.5to+7.0 v circuitry to guard against damage oC uPPY ge (Refe ND) . due to high static voltages or electric Vin DC Input Voltage (Referenced to GND) -15toVec+15}] Vv fields. However, precautions must _ be taken to avoid applications of any Vout | DC Output Voltage (Referenced to GND) O5t0oVcc +05] V voltage higher than maximum rated lin DC Input Current, per Pin 20 mA voltages to this high-impedance cir- - - cuit. For proper operation, Vjn and lout DC Output Current, per Pin +25 mA Vout should be constrained to the loc DC Supply Current, Voc and GND Pins +50 mA range GND s (Vin Or Vout) = Voc. Unused inputs must always be Pp Power Dissipation in Still Air, Plastic or Ceramic DIP 750 mw pu ys tied to an appropriate fogic voltage SOIC Packaget 500 level (e.g., either GND or Voc). Tstg | Storage Temperature ~ 65 to + 150 C Unused outputs must be left open. TL Lead Ternperature, 1 mm from Case for 10 Seconds c (Plastic DIP or SOIC Package) 260 (Ceramic DIP) 300 *Maximum Ratings are those values beyond which damage to the device may occur, Functional operation should be restricted to the Recommended Operating Conditions. jDerating Plastic DIP: 10 mW/*C from 65 to 125C Ceramic DIP: ~ 10 mW/C from 100 to 125C SOIC Package: - 7 mW/C from 68 to 125C For high frequency or heavy load considerations, see Chapter 2, RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min | Max | Unit Voc DC Supply Voltage (Referenced to GND) 2.0 6.0 Vv Vin: Vout | OC Input Voltage, Output Voltage (Referenced to GND) 0 Vec v Ta Operating Temperature, All Package Types 55 [+125] C tr, tf Input Rise and Fall Time : Voc =2.0V| 0 1000 | ns (Figure 1) Voc =45V 0 500 Voc=6.0V} 0 400 ; DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Voc 55 to Symbol Parameter Test Conditions Vv 25C = 85C | = 125C | Unit Vin Minimum High-Level Input Vout = 0.1 V or Voo~0.1V 2.0 1.5 1.5 15 Vv vote Ho! = 201 ao | Se | oe | ae VIL Maximum Low-Level Input Vout = 0.1 V or Voc - 0.1 V 2.0 0.3 0.3 0.3 Vv Voltage Hout! = 20 WA eo | t2 | 92 | 92 VOH Minimum High-Level Output Vin = ViH oF VIL 2.0 1.9 19 1.9 v Vvotage - Hout! = 20 uA eo | ss | go | s Vin=VIHOT VIL Houil s4.0mA] 4.5 3.98 3.84 3.70 llou! = 5.2 mA 6.0 5.48 5.34 5.20 VOL Maximum Low-Level Output Vin = Vin or Vib. 2.0 0.1 0.1 0.1 Vv Volage Hout! = 20 HA eo | o1 | ot | of Vin= VI or Vi Moyil s 4.0mA] 4.5 0.26 0.33 0.40 lou! = 5.2mA] 6.0 0.26 0.33 0.40 lin Maximum input Leakage Current | Vin = Voc or GND 6.0 0.1 1.0 1.0 pA loc Maximum Quiescent Supply Vin = Voc or GND 6.0 8 80 160 HA Current (per Package) lout = 0 pA NOTE: Information on typical parametric values can be found in Chapter 2. MOTOROLA 3-222 a High-Speed CMOS Logic Data OL129 Rev 6MC54/74HC164 AC ELECTRICAL CHARACTERISTICS (C,, = 50 pF, Input t; = tj = 6 ns) Guaranteed Limit Voc 55 to Symbol Parameter Vv 25C = 85C | = 125C | Unit frmax Maximum Clock Frequency (50% Duty Cycle) _ 2.0 6.0 4.8 4.0 MHz (Figures 1 and 4) . , 4.5 30 24 20 6.0 35 28 24 {PLH: Maximum Propagation Delay, Clock to Q . ~ 2.0 175 220 265 ns tPHL (Figures 1 and 4) 4.5 35 44 53 6.0 30 37 45 tPHL Maximum Propagation Delay, Reset to Q 2.0 205 255 310 ns (Figures 2 and 4) 45 41 51 62 6.0 35 43 53 tTLH: Maximum Output Transition Time, Any Output ~ , 2.0 75 95 110 ns tTHL (Figures 1 and 4) 45 15 19 22 6.0 13 16 19 Cin Maximum Input Capacitance . ae -_- 10 10 10 pF NOTES: : a 1. For propagation delays with loads other than 50 pF, see Chapter 2.- 2. Information on typical parametric values can be found in Chapter 2. Typical @ 25C, Voc =5.0 V Cpp Power Dissipation Capacitance (Per Package)* 140 pF * Used to determine the no-load dynamic power consumption: Pp = Cpp Vcc2F + Icc Voc. For load considerations, see Chapter 2. TIMING REQUIREMENTS (input t; = ty = 6 ns) Guaranteed Limit Voc 55 to Symbol Parameter Vv 25C = 85C | < 125C | Unit tsy Minimum Setup Time, A1 or A2 to Clock . . a 2.0 50 65 75 ns (Figure 3} - . oT 4.5 10 13 15 6.0 9 11 13 th Minimum Hold Time, Clack to A1 or A2 - 2.0 5 5 5 ns (Figure 3) - 45 5 5 5 6.0 5 5 5 trec Minimum Recovery Time, Reset Inactive to Clock . 2.0 5 5 5 ns (Figure 2} 4.5 5 5 5 6.0 5 5 5 tw Minimum Pulse Width, Clock _ 2.0 80 100 120 ns (Figure 1} 4.5 16 20 24 6.0 14 17 20 tw Minimum Pulse Width, Reset oo. _. 2.0 80 100 120 ns (Figure 2) / _ Se 4.5 16 20 24 6.0 14 7 20 tr, tf Maximum Input Rise and Fall Times - 2.0 1000 1000 1000 ns (Figure 1) 4.5 500 500 500 6.0 400 400 400 NOTE: Information on typical parametric values can be found in Chapter 2. - High-Speed CMOS Logic Data . _ 3-223 _ MOTOROLA DL129 Rev 6MC54/74HC 164 PIN DESCRIPTIONS INPUTS A1, A2 (Pins 1, 2) Serial Data Inputs. Data at these inputs determine the data to be entered into the first stage of the shift register. For a high level to be entered into the shift register, both At and A2 inputs must be high, thereby allowing one input to be used as a data-enable input. When only one serial input is used, the other must be connected to Voc. Clock (Pin 8) Shift Register Clock. A positive-going transition on this pin shifts the data at each stage to the next stage. The shift register is completely static, allowing clock rates down io DC in a continuous or intermittent mode. OUTPUTS | Qa - Qu (Pins 3, 4, 5, 6, 10, 11, 12, 13) Parallel Shift Register Outputs. The shifted data is pres- ented at these outputs in true, or noninverted, form. CONTROL INPUT Reset (Pin 9) ActiveLow, Asynchronous Reset Input. A low voltage ap- plied to this input resets all internal flip-flops and sets Out- puis Qa Quy to the low level state. SWITCHING WAVEFORMS Voc GND RESET _ CLOCK . 50% - GND Figure 1. Figure 2. TEST POINT VALID OUTPUT Voc DEVICE - A1 OR A2 50% UNDER : GND TEST CL su th [ Vec = CLOCK 50% = a ~ GND "Includes all probe and jig capacitance Figure 3. Figure 4. Test Circuit MOTOROLA 3-224 High-Speed CMOS Logic Data DL129 Rev 6MC54/74HC164 EXPANDED LOGIC DIAGRAM 8 CLOCK <p 4 <D- au mH ra > q B= es fl o ) = p a Pi 0 QD o bt O o bd = o oO iso oO oa band o o bt =a 2 o I Dp <p-4 <p- On Og Og Qp _ OF * QF Qg Qy TIMING DIAGRAM RESET aa I - a A 03 7 % [J MLE Ce 7 [ OF my - J] 1 CH] 1 High-Speed CMOS Logic Data 3-225 - MOTOROLA DLi29 Rev 6 .