Rev. 4158D–AERO–06/02
1
Features
Operating Voltage: 3.3V
Access Time: 40 ns
Very Low Power Consumption
Active: 180 mW (Max)
Standby: 70 µW (Typ)
Wide Temperature Range: -55°C to +125°C
400 Mils Width Package
TTL Compatible Inputs and Outputs
Asynchronous
Designedon0.35MicronProcess
Latch-up Immune
200 Krads capability
SEU LET Better Than 3 MeV
Description
The M65609E is a very low power CMOS static RAM organized as 131,072 x 8 bits.
Atmel brings the solution to applications where fast computing is as mandatory as low
consumption, such as aerospace electronics, portable instruments, or embarked
systems.
Utilizing an array of six transistors (6T) memory cells, the M65609E combines an
extremely low standby supply current (Typical value = 20 µA) with a fast access time
at 40 ns over the full military temperature range. The high stability of the 6T cell pro-
vides excellent protection against soft errors due to noise.
The M65609E is processed according to the methods of the latest revision of the MIL
STD 883 (class B or S), ESA SCC 9000 or QML.
It is produced on the same process as the MH1RT sea of gates series.
Rad. Hard
128K x 8
3.3-volt
Very Low Power
CMOS SRAM
M65609E
2M65609E 4158D–AERO–06/02
Block Diagram
Pin Configuration 32 pins Flatpack 400 MILS
Pin Description Table 1. Pin Names
Name Description
A0 - A16 Address Inputs
I/O1 - I/O8 Data Input/Output
CS1Chip Select 1
CS2Chip Select 2
WE Write Enable
OE Output Enable
VCC Power
GND Ground
3
M65609E
4158D–AERO–06/02
Table 2. Truth Table
Note: L = low, H = high, X = H or L, Z = high impedance.
CS1CS2WE OE Inputs/
Outputs Mode
HXXXZ
Deselect/
Power-down
XLXXZ
Deselect/
Power-down
LHHLDataOutRead
LHLXDataInWrite
LHHHZ
Output
Disable
4M65609E 4158D–AERO–06/02
Electrical Characteristics
Absolute Maximum Ratings
Military Operating Range
Recommended DC Operating Conditions
Capacitance
Note: 1. Guaranteed but not tested.
Supply Voltage to GND Potential............................ -0.5V + 5V
DC Input Voltage.............................. GND - 0.3V to VCC +0.3
DC Output Voltage High Z State...... GND - 0.3V to VCC +0.3
Storage Temperature.................................... -65°Cto+150°C
Output Current Into Outputs (Low) ............................... 20 mA
Electro Statics Discharge Voltage............................... > 2001V
(MIL STD 883D Method 3015.3)
*NOTE: Stresses greater than those listed under Absolute Max-
imum Ratings may cause permanent damage to the
device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
Operating Voltage Operating Temperature
3.3V + 0.3V -55°Cto+125°C
Parameter Description Min Typ Max Unit
VCC Supply voltage 3 3.3 3.6 V
Gnd Ground 0.0 0.0 0.0 V
VIL Input low voltage GND - 0.3 0.0 0.8 V
VIH Input high voltage 2.2 VCC +0.3 V
Parameter Description Min Typ Max Unit
CIN(1) Input low voltage 8 pF
COUT(1) Output high voltage 8 pF
5
M65609E
4158D–AERO–06/02
DC Parameters
DC Test Conditions
Consumption
Parameter Description Minimum Typical Maximum Unit
IIX (1)
1. Gnd<Vin<VCC, Gnd < Vout < VCC Output Disabled.
Input leakage
current -1 1 µA
IOZ (1) Output leakage
current -1 1 µA
VOL (2)
2. VCC min.IOL=1mA.
Output low voltage - 0.4 V
VOH (3)
3. VCC min. IOH = -0.5 mA.
Output high voltage 2.4 V
Symbol Description 65609E-40 Unit Value
ICCSB (1) Standby supply current 2.5 mA max
ICCSB1(2) Standby supply current 1.5 mA max
ICCOP (3) Dynamic operating
current 50 mA max
1. CS1>VIH or CS2<VIL and CS1<VIL.
2. CS1>VCC -0.3Vor,CS
2< Gnd + 0.3V and CS1<0.2V
3. F=1/T
AVAV,I
OUT =0mA,W=OE=VIH,Vin=GndorVCC,VCC max.
6M65609E 4158D–AERO–06/02
Write Cycle
Note: 1. Parameters guaranteed, not tested, with 5 pF output loading (see Section “AC Test Conditions Figure 2).
Read Cycle
Note: 1. Parameters guaranteed, not tested, with 5 pF output loading (seeSection AC Test Conditions Figure 2).
Symbol Parameter 65609E-40 Unit Value
tAVAW Write cycle time 35 ns min
tAVWL Address set-up time 0 ns min
tAVWH Address valid to end of write 28 ns min
tDVWH Data set-up time 28 ns min
tE1LWH CS1low to write end 28 ns min
tE2HWH CS2high to write end 28 ns min
tWLQZ Write low to high Z (1) 15 ns max
tWLWH Write pulse width 28 ns min
tWHAX Address hold from to end of
write +3 ns min
tWHDX Data hold time 0 ns min
tWHQX WritehightolowZ(1) 0nsmin
Symbol Parameter 65609E-40 Unit Value
tAVAV Read cycle time 40 ns min
tAVQV Address access time 40 ns max
tAVQX Address valid to low Z 3 ns min
tE1LQV Chip-select1access
time 40 ns max
tE1LQX CS1low to low Z (1) 3nsmin
tE1HQZ CS1high to high Z (1) 15 ns max
tE2HQV Chip-select2access
time 40 ns max
tE2HQX CS2high to low Z (1) 3nsmin
tE2LQZ CS2low to high Z (1) 15 ns max
tGLQV Output Enable access
time 12 ns max
tGLQX OE low to low Z (1) 0nsmin
tGHQZ OE high to high Z (1) 10 ns max
7
M65609E
4158D–AERO–06/02
AC Parameters
AC Test Conditions
AC Test Loads Waveforms
Input Pulse Levels:.......................................................GND to 3.0V
Input Rise/Fall Times: ..................................................5 ns
Input Timing Reference Levels: ...................................1.5V
Output loading IOL/IOH (see figure 1 and 2)................+30 pF
Figure 1 Figure 2 Figure 3
R1 2552
R1 2552
2824
2824
1340
3.3V 3.3V
V
8M65609E 4158D–AERO–06/02
Data Retention Mode Atmel CMOS RAM’s are designed with battery backup in mind. Data retention voltage
and supply current are guaranteed over temperature. The following rules ensure data
retention:
1. During data retention CS must be held high within VCC to VCC -0.2Vorchip
select BS must be held down within GND to GND +0.2V.
2. Output Enable (OE) should be held high to keep the RAM outputs high imped-
ance, minimizing power dissipation.
3. During power-up and power-down transitions CS and OE must be kept between
VCC + 0.3V and 70% of VCC, or with BS between GND and GND -0.3V.
4. The RAM can begin operation > tRns after VCC reaches the minimum operation
voltages (3V).
Figure 1. Data Retention Timing
Data Retention Characteristics
Notes: 1. TAVAV = Read Cycle Time
2. CS1 =VCC or CS2 = CS1 = GND, VIN = GND/VCC.
3V 3V
BS
Parameter Description Min Typical TA=25°CMax Unit
VCCDR VCC for data
retention 2.0 V
TCDR Chip deselect to
data retention time 0.0 ns
tROperation recovery
time tAVAV(1) ––ns
ICCDR1(2) Data retention
current at 2.0V 0.010 1.0 mA
9
M65609E
4158D–AERO–06/02
Write Cycle 1. WE Controlled.
OE High During Write
Write Cycle 2. WE Controlled.
OE Low
10 M65609E 4158D–AERO–06/02
Write Cycle 3. CS1orCS2
Controlled(1)
Note: 1. The internal write time of the memory is defined by the overlap of CS1 LOW and CS2 HIGH and W LOW. Both signals must
be activated to initiate a write and either signal can terminate a write by going in activated. The data input setup and hold
timing should be referenced to the actived edge of the signal that terminates the write. Data out is high impedance if OE =
VIH.
11
M65609E
4158D–AERO–06/02
Read Cycle nb 1
Read Cycle nb 2
Read Cycle nb 3
12 M65609E 4158D–AERO–06/02
Ordering Information
Note: 1. Contact Atmel for availability.
Part Number Temperature Range Speed Package Flow
MMDJ-65609EV-40 -55 to +125°C 40 ns FP32.4 Standard Mil
MMDJ-65609EV-40MQ -55 to +125°C40ns FP32.4 QMLQ
MMDJ-65609EV-40-E 25°C 40 ns FP32.4 Engineering Samples
MMDJ-65609EV-40/883(1) -55to+125°C 40 ns FP32.4 MIL 883 B
SMDJ-65609EV-40/883(1) -55to+125°C 40 ns FP32.4 MIL 883 S
MM0-65609EV-40-E 25°C 40 ns Die Engineering Samples
MM0-65609EV-40MQ -55 to +125°C40ns Die QMLQ
13
M65609E
4158D–AERO–06/02
Package Drawing
32-pin Flat Pack (400 Mils)
Printedonrecycledpaper.
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Other terms and product names may be the trademarks of others.
© Atmel Corporation 2002.
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which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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4158D–AERO–06/02 /xM