APA2120RI-TRG - Anpec Electronics Corp.

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise

customers to obtain the latest version of relevant information to verify before placing orders.

Stereo 2-W Audio Power Amplifier (with DC_Volume Control)

APA2120/1 is a monolithic integrated circuit, which pro-

vides precise DC volume control, and a stereo bridged

audio power amplifiers is capable of producing 2.7W(2.

0W) into 3Ω with less than 10% (1.0%)THD+N. The at-

tenuator range of the volume control in APA2120/1 is from

20dB (DC_Vol=0V) to -80dB (DC_Vol=3.54V) with 32

steps. The advantage of internal gain setting can be less

components and PCB area. Both of the depop circuitry

and the thermal shutdown protection circuitry are inte-

grated in APA2120/1 and reduce pops and clicks noise

during power up or shutdown mode operation. It also

improves the power off pop noise and protects the chip

from being destroyed by over temperature and short cur-

rent failure. To simplify the audio system design, APA2120/

1 combines a stereo bridge-tied loads (BTL) mode for

speaker drive and a stereo single-end (SE) mode for head-

phone drive into a single chip, where both modes are

easily switched by the SE/BTL input control pin signal.

Besides, the multiple input selection is used for portable

audio system.

•Low Operating Current with 14mA

•Improved Depop Circuitry to Eliminate Turn-on

and Turn-off Transients in Outputs

•High PSRR

•32 Steps Volume Adjustable by DC Voltage with

Hysteresis

•2W Per Channel Output Power into 4Ω Load at

5V, BTL Mode

•Two Output Modes Allowable with BTL and SE

Modes Selected by SE/BTL Pin

•Low Current Consumption in Shutdown Mode

(50µA)

•Short Circuit Protection

•Power off Depop Circuit Integration

•TSSOP-24P with or without Thermal Pad

Package

•Lead Free and Green Devices Available

(RoHS Compliant)

Features

Applications

General Description

Ordering and Marking Information

• NoteBook PC

• LCD Monitor or TV

APA2120/1

Handling Code

Temperature Range

Package Code

R : TSSOP-24P

Operating Ambient Temperature Range

I : - 40 to 85 oC

Handling Code

TR : Tape & Reel

Assembly Material

L : Lead Free Device G : Halogen and Lead Free Device

APA2120/1 R : APA2120/1

XXXXX XXXXX - Date Code

Assembly Material

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw2

(Over operating free-air temperature range unless otherwise noted.)

Symbol Parameter Rating Unit

VDD Supply Voltage Range -0.3 to 6 V

VIN

Input Voltage Range, SE/BTL, HP/LINE, SHUTDOWN, PCBEN -0.3 to VDD+0.3 V

TA Operating Ambient Temperature Range -40 to 85 °C

TJ Maximum Junction Temperature Intermal Limited(Note 1) °C

TSTG Storage Temperature Range -65 to +150 °C

TS Maximum Lead Soldering Temperature,10 Seconds 260 °C

PD Power Dissipation Intermal Limited

Absolute Maximum Ratings (Note 1)

Note 1: APA2120/1 integrated internal thermal shutdown protection when junction temperature ramp up to 150°C

Pin Configuration

APA2120/1

Bottom View

Thermal

Pad

Multiple Input Selection

PCBEEP Control Input

APA2120

SE/BTL PCBEN

APA2121

HP/LINE -

LOUT-

LHPIN

RBYPASS

GND

PCBEN

VOLUME

LOUT+

LLINEIN

LBYPASS

PVDD

GND

BYPASS

GND

RLINEIN

SHUTDOWN

ROUT+

RHPIN

SE/BTL

PVDD

GND

PC-BEEP

VDD

CLK

ROUT-

APA2120

TOP View

LOUT-

LHPIN

RBYPASS

GND

HP/LINE

VOLUME

LOUT+

LLINEIN

LBYPASS

PVDD

GND

BYPASS

GND

RLINEIN

SHUTDOWN

ROUT+

RHPIN

SE/BTL

PVDD

GND

PC-BEEP

VDD

CLK

ROUT-

APA2121

TOP View

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw3

Recommended Operating Conditions

Symbol Parameter Range Unit

VDD Supply Voltage 4.5 ~ 5.5 V

SHUTDOWN, PCBEN 2 ~

VIH High Level Threshold Voltage SE/BTL , HP/LINE 4 ~ V

SHUTDOWN, PCBEN ~ 1.0

VIL Low Level Threshold Voltage SE/BTL , HP/LINE ~ 3 V

VICM Common Mode Input Voltage VDD-1.0 ~ V

VDD=5V, -20°C<TA<85°C (unless otherwise noted)

Electrical Characteristics

Thermal Characteristics

Symbol Parameter Typical Value Unit

θJA Thermal Resistance from Junction to Ambient in Free Air (Note 2)

TSSOP-24P

45 °C/W

APA2120/1

Symbol Parameter Test Conditions Min.

Typ. Max.

Unit

VDD Supply Voltage 4.5 - 5.5 V

SE/BTL=0V - 14 25

IDD Supply Current SE/BTL=5V - 8.0 15 mA

ISD Supply Current in Shutdown Mode SE/BTL=5V

SHUTDOWN=0V - 50 - µA

IIH High input Current - 900 - nA

IIL Low Input Current - 900 - nA

VOS Output Differential Voltage - 5 - mV

Note 2 : 5 in2 printed circuit board with 2oz trace and copper pad through 9 25mil diameter vias. The thermal pad on the TSSOP_P

package with solder on the printed circuit board.

APA2120/1

Symbol Parameter Test Conditions Min.

Typ.

Max.

Unit

THD+N=10%, RL=3Ω, fin=1kHz - 2.7 -

THD+N=10%, RL=4Ω, fin=1kHz - 2.3 -

THD+N=10%, RL=8Ω, fin=1kHz - 1.5 -

THD+N=1%, RL=3Ω, fin=1kHz - 2.0 -

THD+N=1%, RL=4Ω, fin=1kHz - 1.9 -

PO Maximum Output Power

THD+N=0.5%, RL=8Ω, fin=1kHz 1 1.1 -

PO=1.5W, RL=4Ω, fin=1kHz - 0.05

THD+N Total Harmonic Distortion Plus Noise

PO=1W, RL=8Ω, fin=1kHz - 0.07

- %

PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF, fin=120Hz

- 60 - dB

Operating Characteristics, BTL mode

VDD=5V,TA=25°C,RL=4Ω, AV=2V/V (unless otherwise noted)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw4

Electrical Characteristics (Cont.)

APA2120/1

Symbol Parameter Test Conditions Min. Typ. Max.

Unit

THD+N=10%, RL=8Ω, fin=1kHz - 400 -

THD+N=10%, RL=32Ω, fin=1kHz - 110 -

THD+N=1%, RL=8Ω, fin=1kHz - 320 -

PO Maximum Output Power

THD+N=1%, RL=32Ω, fin=1kHz - 90 -

PO=250mW, RL=8Ω, fin=1kHz - 0.08 -

THD+N Total Harmonic Distortion Plus Noise

PO=75mW, RL=32Ω, fin=1kHz - 0.08 - %

PSRR Power Ripple Rejection Ratio VIN=0.1Vrms, RL=8Ω, CB=1µF,

fin=120Hz - 48 - dB

Xtalk Channel Separation CB=1µF, RL=32Ω, fin=1kHz - 100 - dB

S/N Signal to Noise Ratio PO=75mW, SE, RL=32Ω, A_weighting

- 100 - dB

Operating Characteristics, BTL mode

VDD=5V,TA=25°C,RL=4Ω, AV=2V/V (unless otherwise noted)

APA2120/1

Symbol Parameter Test Conditions Min.

Typ.

Max.

Unit

Xtalk Channel Separation CB=1µF, RL=8Ω, fin=1kHz - 90 - dB

S/N Signal to Noise Ratio PO=1.1mW, RL=8Ω, A_weighting - 95 - dB

Operating Characteristics, SE mode

VDD=5V,TA=25°C,RL=4Ω, Gain=1V/V (unless otherwise noted)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw5

0.01

0.1

20 20k50 100 200 500 1k 2k 5k

THD+N vs. Frequency

THD+N (%)

Frequency (W)

0.01

0.1

100m 3200m 500m 800m 2

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

10m 3100m 1 2

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

Typical Operating Characteristics

VDD=5V

RL=3Ω

PO=1.75W

BTL

AV=2

AV=5

AV=10

VDD=5V

RL=4Ω

PO=1.5W

BTL

VDD=5V

RL=4Ω

AV=2

BTL

fin=20Hz

fin=20kHz

fin=1kHz

VDD=5V

RL=3Ω

AV=2

BTL

fin=20Hz

fin=20kHz

fin=1kHz

AV=2

AV=5

AV=10

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw6

0.01

0.1

10m 500m

100m

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

0.01

0.1

10m 2100m 1

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

Typical Operating Characteristics (Cont.)

VDD=5V

RL=8Ω

AV=2

BTL

fin=20Hz

fin=20kHz

fin=1kHz

VDD=5V

RL=8Ω

PO=250mW

VDD=5V

RL=8Ω

PO=1.0W

BTL

AV=2

AV=5

AV=10

AV=1AV=5

AV=2.5

VDD=5V

RL=8Ω

AV=2

BTL

fin=20Hz

fin=20kHz

fin=1kHz

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw7

0.01

0.1

10m 200m50m 100m

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

0.01

0.1

10m 300m

100m

THD+N vs. Output Power

THD+N (%)

Output Power (W)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

VDD=5V

RL=32Ω

AV=1

BTL

fin=20Hz

fin=20kHz

fin=1kHz

VDD=5V

RL=16Ω

PO=100mW

AV=2AV=1

AV=2.5

VDD=5V

RL=16Ω

AV=1

BTL

fin=20Hzfin=20kHz

fin=1kHz

VDD=5V

RL=32Ω

PO=75mW

AV=1

AV=5

AV=2.5

Typical Operating Characteristics (Cont.)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw8

-120

-100

-80

-60

-40

-20

20 20k100 1k

Crosstalk vs. Frequency

Crosstalk (dB)

Frequency (Hz)

-120

-100

-80

-60

-40

-20

20 20k100 1k

Crosstalk vs. Frequency

Crosstalk (dB)

Frequency (Hz)

0.01

0.1

100m 3500m 12

THD+N vs. Output Swing

THD+N (%)

Output Swing (VRMS)

0.01

0.1

20 20k100 1k

THD+N vs. Frequency

THD+N (%)

Frequency (Hz)

VDD=5V

RL=10Ω

VO=1VRMS

VDD=5V

RL=10Ω

AV=1

fin=20Hz

fin=20kHz

fin=1kHz

AV=1

AV=5

AV=2.5

VDD=5V

RL=32Ω

PO=75mW

AV=1

R-ch to L-chL-ch to R-ch

VDD=5V

RL=8Ω

PO=1.0W

AV=2

BTL

R-ch to L-ch

L-ch to R-ch

Typical Operating Characteristics (Cont.)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw9

0.02

0.04

0.06

0.08

0.1

0.12

0.14

0.16

0.18

0.2

00.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4

Power Dissipation vs. Output Power

Power Dissipation (W)

Output Power (W)

1µ

100µ

2µ

5µ

10µ

20µ

50µ

20 20k100 1k

Noise Floor vs. Frequency

Noise Floor (µVRMS)

Frequency (Hz)

1µ

100µ

2µ

5µ

10µ

20µ

50µ

20 20k100 1k

Noise Floor vs. Frequency

Noise Floor (µVRMS)

Frequency (Hz)

1µ

100µ

2µ

5µ

10µ

20µ

50µ

20 20k100 1k

Noise Floor vs. Frequency

Noise Floor (µVRMS)

Frequency (Hz)

VDD=5V

RL=32Ω

AV=1

No Filter

A-Weighting

VDD=5V

RL=10kΩ

AV=1

No Filter

A-Weighting

VDD=5V

AV=1

RL=32Ω

RL=16Ω

RL=8Ω

VDD=5V

RL=8Ω

AV=2

BTL

No Filter

A-Weighting

Typical Operating Characteristics (Cont.)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw10

100

120

140

160

2.5 33.5 44.5 55.5

Output Power vs. Supply Voltage

Output Power (mW)

Supply Voltage (V)

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.5 33.5 44.5 55.5

Output Power vs. Supply Voltage

Output Power (W)

Supply Voltage (V)

0.2

0.4

0.6

0.8

1.2

1.4

1.6

1.8

00.5 11.5 22.5

Power Dissipation vs. Output Power

Power Dissipation (W)

Output Power (W)

2.5

7.5

12.5

17.5

11.5 22.5 33.5 44.5 55.5

Supply Current vs. Supply Voltage

Suuply Current (mA)

Supply Voltage (V)

RL=8Ω

AV=2

BTL

THD+N=10%

THD+N=1%

RL=32Ω

AV=1

THD+N=10%

THD+N=1%

VDD=5V

AV=2

BTL

RL=3Ω

RL=4Ω

RL=8Ω

No Load

BTL

Typical Operating Characteristics (Cont.)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw11

-6

-4

-2

20 20k100 1k

Close Loop Response

Loop Gain (dB)

Frequency (Hz)

-0

+12

+10

20 20k100 1k

Close Loop Response

Loop Gain (dB)

Frequency (Hz)

0.1

0.2

0.3

0.4

0.5

0.6

0.7

4 8 12 16 20 24 28 32 36 40 44 48 52 56 6064

Output Power vs. Load Resistance

Output Power (W)

Load Resistance (Ω)

0.5

1.5

2.5

4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64

Output Power vs. Load Resistance

Output Power (W)

Load Resistance (Ω)

VDD=5V

AV=2

BTL

THD+N=10%

THD+N=1%

VDD=5V

AV=1

THD+N=10%

THD+N=1%

AV=2

AV=5

AV=10

VDD=5V

RL=32Ω

AV=1

CO=330µF

AV=1

AV=2.5

AV=5

VDD=5V

RL=8Ω

AV=2

BTL

CO=330µF

Typical Operating Characteristics (Cont.)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw12

-80

-60

-40

-20

20 20k100 1k

PSRR vs. Frequency

Ripple Rejection Ratio (dB)

Frequency (Hz)

VDD=5V

Vin=100mVRMS

RL=8Ω

Cbypass=2.2µF

BTL

Typical Operating Characteristics (Cont.)

NAME NO. I/O/P FUNCTION

GND 1,12,

13,24 Ground connection, Connected to the thermal pad.

PCBEN 2 I/P BEEP mode control input, active H, for APA2120 only

HP/LINE 2 I/P Multi-input selection input, headphone mode when held high, line-in mode whe

n held

low for APA2121 only.

VOLUME 3 Input signal for internal volume gain setting.

LOUT+ 4 O/P Left channel positive output in BTL mode and SE mode.

LLINEIN 5 I/P Left channel line input terminal, selected when HP/LINE is held low.

LHPIN 6 O/P Left channel headphone input terminal, selected when HP/LINE is held high.

PVDD 7,18 Supply voltage only for power amplifier.

RBYPASS 8 I/P Right channel bypass voltage.

LOUT- 9 O/P Left channel negative output in BTL mode and high impedance in SE mode.

LBYPASS 10 I/P Left channel bias voltage generator.

BYPASS 11 Bias voltage generator

PC_BEEP 14 I/P PCBEP signal input

SE/BTL 15 I/P Output mode control input, high for SE output mode and low for BTL mode.

ROUT- 16 O/P Right channel negative output in BTL mode and high impedance in SE mode.

CLK 17 Clock signal generator

VDD 19 Supply voltage for internal circuit excepting power amplifier.

Pin Description

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw13

NAME NO. I/O/P FUNCTION

RHPIN 20 I/P Right channel headphone input terminal, selected when HP/LINE is held high.

ROUT+ 21 O/P Right channel positive output in BTL mode and SE mode.

SHUTDOWN

22 I/P It will be into shutdown mode when pull low.

RLINEIN 23 I/P Right channel line input terminal, selected when HP/LINE is held low.

Pin Description (Cont.)

Block Diagram

Shutdown

ckt

HP/LINE

Volume

Control

MUX

SE/BTL

LOUT+

LOUT-

ROUT+

ROUT-

LLINEIN

RLINEIN

LHPIN

RHPIN

HP/LINE

SE/BTL

SHUTDOWN RBYPASS

LBYPASS

VOLUME BYPASS BYPASS

PC-BEEP

ckt

PCBEEP Clock Gen CLK

For APA2121

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw14

Typical Application Circuits

APA2120

Shutdown

ckt

Volume

Control

MUX

SE/BTL

LOUT+

LOUT-

ROUT+

ROUT-

LLINEIN

RLINEIN

LHPIN

RHPIN

PCBEN

SE/BTL

SHUTDOWN RBYPASS

LBYPASS

VOLUME

BYPASS BYPASS

PC-BEEP

ckt

PCBEEP Clock

Gen CLK

4Ω

4ΩRing

Headphone Jack

Sleeve

Control

Tip

SE/BTL

0.47µF

2.2µF

1µF

220µF

1kΩ

L-LINE

R-LINE

R-HP

L-HP

VDD

100kΩ

BEEP

Signal

Shutdown

Signal

VDD

VDD PVDDGND

0Ω

47nF

100µF

0.1µF

PCBEN

Signal

50kΩ

100kΩ

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw15

APA2121

Typical Application Circuits (Cont.)

Shutdown

ckt

HP/LINE

Volume

Control

MUX

SE/BTL

LOUT+

LOUT-

ROUT+

ROUT-

LLINEIN

RLINEIN

LHPIN

RHPIN

RBYPASS

LBYPASS

VOLUME BYPASS BYPASS

PC-BEEP

ckt

PCBEEP Clock Gen CLK

4Ω

4ΩRing

Headphone Jack

Sleeve

Control

Tip

0.47µF

2.2µF

1µF

220µF

1kΩ

L-LINE

R-LINE

R-HP

L-HP

VDD

50kΩ

VDD

100kΩ

BEEP

Signal

Shutdown

Signal

HP/LINE

Signal

VDD

VDD PVDDGND

0Ω

47nF

100µF0.1µF

HP/LINE

SE/BTL

SHUTDOWN

SE/BTL

100kΩ

SE/BTL

SHUTDOWN PC-BEEP Operating Mode

X L Disable Shutdown mode

L H Disable Line input, BTL out

H H Disable HP input, SE out

X X Enable PCBEEP input, BTL out

SE/BTL HP/LINE SHUTDOWN PC-BEEP Operating Mode

X X L Disable Shutdown mode

L L H Disable Line input, BTL out

L H H Disable HP input, BTL out

H L H Disable Line input, SE out

H H H Disable HP input, BTL out

X X X Enable PCBEEP input, BTL out

For APA2121

Control Input Table

For APA2120

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw16

Volume Control Table_BTL Mode

Gain(dB) High(V) Low(V) Hysteresis(mV) Recommended Voltage(V)

20 0.12 0.00 0

18 0.23 0.17 52 0.20

16 0.34 0.28 51 0.31

14 0.46 0.39 50 0.43

12 0.57 0.51 49 0.54

10 0.69 0.62 47 0.65

8 0.80 0.73 46 0.77

6 0.91 0.84 45 0.88

4 1.03 0.96 44 0.99

2 1.14 1.07 43 1.10

0 1.25 1.18 41 1.22

-2 1.37 1.29 40 1.33

-4 1.48 1.41 39 1.44

-6 1.59 1.52 38 1.56

-8 1.71 1.63 37 1.67

-10 1.82 1.74 35 1.78

-12 1.93 1.85 34 1.89

-14 2.05 1.97 33 2.01

-16 2.16 2.08 32 2.12

-18 2.28 2.19 30 2.23

-20 2.39 2.30 29 2.35

-22 2.50 2.42 28 2.46

-24 2.62 2.53 27 2.57

-26 2.73 2.64 26 2.69

-28 2.84 2.75 24 2.80

-30 2.96 2.87 23 2.91

-32 3.07 2.98 22 3.02

-34 3.18 3.09 21 3.14

-36 3.30 3.20 20 3.25

-38 3.41 3.32 18 3.36

-40 3.52 3.43 17 3.48

-80 5.00 3.54 16 5

Supply Voltage Vdd=5V

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw17

Application Information

BTL Operation Single-Ended Operation

Consider the single-supply SE configuration shown Ap-

plication Circuit. A coupling capacitor is required to block

the DC offset voltage from reaching the load. These ca-

pacitors can be quite large (approximately 33µF to 1000µF)

so they tend to be expensive, occupied valuable PCB

area, and have the additional drawback of limiting low-

frequency performance of the system (refer to the Output

Coupling Capacitor).The rules described still hold with

the addition of the following relationship:

The APA2120/1 output stage (power amplifier) has two

pairs of operational amplifiers internally, allowed for dif-

ferent amplifier configurations.

Output SE/BTL Operation

The best cost saving feature of APA2120/1 is that they can

be switched easily between BTL and SE modes. This

feature eliminates the requirement for an additional head-

phone amplifier in applications where internal stereo

speakers are driven in the BTL mode but external head-

phone or speakers must be accommodated.

Figure 1 : APA2120/1 Internal Configuration.

(each channel)

Vbias

Circuit

OUT+

OUT- RL

OP1

OP2

Volume Control

amplifier output signal

The power amplifier’s OP1 gain is setting by internal unity-

gain and the input audio signal comes from the internal

volume control amplifier while the second amplifier OP2

is internally fixed in a unity-gain, inverting configuration.

Figure 1 shows that the output of OP1 is connected to the

input to OP2, which results in the output signals of both

amplifiers with identical in magnitude, but out of phase

180°. Consequently, the differential gain for each chan-

nel is 2 x (Gain of SE mode).

By driving the load differentially through outputs OUT+

and OUT-, an amplifier configuration commonly referred

to bridged mode is established. The BTL mode opera-

tion is different from the classical single-ended SE am-

plifier configuration where one side of its load is con-

nected to the ground.

A BTL amplifier design has a few distinct advantages over

the SE configuration, as it provides differential drive to the

load, thus doubling the output swing for a specified sup-

ply voltage.

When placed under the same conditions, a BTL amplifier

has four times the output power of a SE amplifier. A BTL

configuration, such as the one used in APA2120/1, also

creates a second advantage over SE amplifiers. Since

the differential outputs, ROUT+, ROUT-, LOUT+, and

LOUT-, are biased at half-supply, it’s not necessary for

DC voltage to be across the load. This eliminates the

need for an output coupling capacitor which is required in

a single supply, SE configuration.

Cbypass x 125kΩ≤1

RiCi<< 1

RLCC(1)

Internal to the APA2120/1, two separate amplifiers drive

OUT+ and OUT- (see Figure 1). The SE/BTL input con-

trols the operation of the follower amplifier that drives

LOUT- and ROUT-.

• When SE/BTL is held low, the OP2 is turned on and

the APA2120/1 is in the BTL mode.

• When SE/BTL is held high, the OP2 is in a high output

impedance state, which configures the APA2120/1 as SE

driver from OUT+. IDD is reduced by approximately one-

half in SE mode.

The control of the SE/BTL input can be a logic-level TTL

source, a resistor divider network, or the stereo head-

phone jack with switch pin as shown in the Application

Circuit.

Ring

Headphone Jack

Sleeve

Control

Tip

1kΩ

VDD

100kΩ

SE/BTL

Figure 2 : SE/BTL Input Selection by Phonejack Plug.

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw18

Volume Control Function

In Figure 2, input SE/BTL operates as below :

When the phonejack plug is inserted, the 1kΩ resistor is

disconnected and the SE/BTL input is pulled high and

enables the SE mode. When the input goes to a high

level, the OUT- amplifier is shutdown which causes the

speaker to mute. Then, the OUT+ amplifier drives through

the output capacitor (CC) into the headphone jack. When

there is no headphone plugged into the system, the con-

tact pin of the headphone jack is connected from the sig-

nal pin, and the voltage divider set up by resistors 100kΩ

and 1kΩ. Resistor 1kΩ then pulls low the SE/BTL pin,

enabling the BTL function.

APA2021 volume control curve

-44

-40

-36

-32

-28

-24

-20

-16

-12

-8

-4

00.2 0.4 0.6 0.8 11.2 1.4 1.6 1.8 22.2 2.4 2.6 2.8 33.2 3.4 3.6 3.8

(V)

Gain_BTL mode Forward

Backward

Figure 3 : Gain setting vs VOLUME Pin Voltage.

Output SE/BTL Operation (Cont.)

Application Information (Cont.)

APA2120/1 have an internal stereo volume control that

setting is the function of the DC voltage applied to the

VOLUME input pin. The APA2120/1 volume control con-

sists of 32 steps that are individually selected by a vari-

able DC voltage level on the VOLUME control pin. The

range of the steps, controlled by the DC voltage, are from

20dB to -80dB. Each gain step corresponds to a specific

input voltage range as shown in table. To minimize the

effect of noise on the volume control pin, which can affect

the selected gain level, hysteresis and clock delay are

implemented. The amount of hysteresis corresponds to

half of the step width is shown in the volume control graph.

For the highest accuracy, the voltage is shown in the ‘rec-

ommended voltage’ column of the table and used to se-

lect a desired gain. This recommended voltage is exactly

halfway between the two nearest transitions. The gain

levels are 2dB/step from 20dB to -40dB in BTL mode,

and the last step at -80dB as mute mode.

Input Resistance, Ri

The gain for each audio input of the APA2120/1 is set by

the internal resistors (Ri and Rf) of volume control ampli-

fier in inverting configuration.

SE Gain =RF

Ri(2)

AV=-

Ri(3)

BTL Gain=-2 x

BTL mode operation brings the factor of 2 in the gain

equation due to the inverting amplifier mirroring the volt-

age swing across the load. For the varying gain setting,

APA2120/1 generate each input resistance on the figure

4. The input resistance will affect the low frequency per-

formance of audio signal. The minmum input resistance

is 10kΩ when gain setting is 20dB, and the resistance

will ramp up when close loop gain below 20dB. The input

resistance has wide variation (+/-10%) caused by the pro-

cess variation.

Figure 4: Input Resistance vs Gain Setting.

Ri vs Gain(BTL)

100

120

-40 -30 -20 -10 0 10 20

Gain(dB)

Ri(kΩ)

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw19

In the typical application, an input capacitor, Ci, is required

to allow the amplifier to bias the input signal to the proper

DC level for optimum operation. In this case, Ci and the

minimum input impedance Ri (10kΩ) form a high-pass

filter with the corner frequency determined in the follow-

ing equation :

Input Capacitor, Ci

Application Information (Cont.)

FC(highpass)=1

2πx10kΩxCi(4)

The value of Ci is important to consider as it directly af-

fects the low frequency performance of the circuit. Con-

sider the example where Ri is 10kΩ and the specification

calls for a flat bass response down to 100Hz. Equation is

reconfigured as below :

Ci=1

2πx10kΩxfC(5)

When the input resistance variation is considered, the Ci

is 0.16µF. Therefore, a value in the range of 0.22µF to

1.0µF would be chosen.

A further consideration for this capacitor is the leakage

path from the input source through the input network

(Ri+Rf, Ci) to the load. This leakage current creates a DC

offset voltage at the input to the amplifier that reduces

useful headroom, especially in high gain applications.

For this reason, a low-leakage tantalum or ceramic ca-

pacitor is the best choice. When polarized capacitors are

used, the positive side of the capacitor should face the

amplifier input in most applications as the DC level there

is held at VDD/2, which is likely higher than the source DC

level. Please note that it is important to confirm the ca-

pacitor polarity in the application.

Effective Bypass Capacitor, Cbypass

As other power amplifiers, proper supply bypassing is

critical for low noise performance and high power supply

rejection.

The capacitors located on both the bypass and power

supply pins should be as close to the device as possible.

The effect of a larger bypass capacitor will improve PSRR

due to increased supply stability. Typical applications em-

ploy a 5V regulator with 1.0µF and a 0.1µF bypass capaci-

tor as supply filtering. This does not eliminate the need

for bypassing the supply nodes of the APA2120/1. The

selection of bypass capacitors, especially Cbypass, is

thus dependent upon desired PSRR requirements, click

and pop performance.

On the chip, there are three bypass pins for used, and

they are tied together in the internal circuit.

The effective capacitance is the Cbypass=(Cb//CLbyasss/

/CRbypass). When absolute minimum cost and/or com-

ponent space is required, one bypass capacitor can be

used.

To avoid the start-up pop noise, the bypass voltage should

rise slower than the input bias voltage and the relation-

ship shown in equation (6) should be maintained.

Cbypass x 125kΩ<< 1

100kΩ x Ci(6)

The bypass capacitor is fed from a 125kΩ resistor inside

the amplifier and the 100kΩ is maximum input resistance

of (Ri+ Rf). Bypass capacitor, Cb, values of 3.3µF to 10µF

ceramic or tantalum low-ESR capacitors are recom-

mended for the best THD and noise performance.

The bypass capacitance also effects to the start up time. It

is determined in the following equation :

Tstart up = 5 x (Cbypass x 125kΩ)(7)

Output Coupling Capacitor, Cc

In the typical single-supply SE configuration, an output

coupling capacitor (Cc) is required to block the DC bias at

the output of the amplifier thus preventing DC currents in

the load. As with the input coupling capacitor, the output

coupling capacitor and impedance of the load form a high-

pass filter governed by the following equation:

FC(highpass)=2πRLCC(8)

For example, a 330µF capacitor with an 8Ω speaker would

attenuate low frequencies below 60.6Hz. The main dis-

advantage of performance is that the load impedance is

typically small, which drives the low-frequency corner

higher degrading the bass response. Large values of CC

are required to pass low frequencies into the load.

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw20

Application Information (Cont.)

Power Supply Decoupling, Cs

The APA2120/1 provide PVDD and VDD two independent

power inputs for used. PVDD is used for power amplifier

only and VDD is used for volume control amplifier and inter-

nal circuit excepting power amplifier. The APA2120/1 are

high-performance CMOS audio amplifiers that requires

adequate power supply decoupling to ensure the output

total harmonic distortion (THD) is as low as possible.

Power supply decoupling also prevents the oscillations

being caused by long lead length between the amplifier

and the speaker. The optimum decoupling is achieved by

using two different types of capacitors that target on differ-

ent noise on the power supply leads.

For higher frequency transients, spikes, or digital hash

on the line, a good low equivalent-series-resistance(ESR)

ceramic capacitor, typically 0.1µF placed as close as pos-

sible to the device VDD and PVDD lead works the best. For

filtering lower-frequency noise signals, a large aluminum

electrolytic capacitor of 10µF or greater placed near the

audio power amplifier is recommended.

Optimizing Depop Circuitry

Circuitry has been included in the APA2120/1 to minimize

the amount of popping noise at power-up and when com-

ing out of shutdown mode. Popping occurs whenever a

voltage step is applied to the speaker. In order to elimi-

nate clicks and pops, all capacitors must be fully dis-

charged before turn-on. Rapid on/off switching of the de-

vice or the shutdown function will cause the click and pop

circuitry.

The value of Ci will also affect turn-on pops. (Refer to

Effective Bypass Capacitance) The bypass voltage should

rises slower than input bias voltage. Although the bypass

pin current source cannot be modified, the size of Cbypass

can be changed to alter the device turn-on time and the

amount of clicks and pops. By increasing the value of

Cbypass, turn-on pop can be reduced. However, the

tradeoff for using a larger bypass capacitor is to increase

the turn-on time for this device. There is a linear relation-

ship between the size of Cbypass and the turn-on time.

In a SE configuration, the output coupling capacitor, CC, is

of particular concern.

This capacitor discharges through the internal 10kΩ

resistors. Depending on the size of CC, the time constant

can be relatively large. To reduce transients in SE mode,

an external 1kΩ resistor can be placed in parallel with the

internal 10kΩ resistor. The tradeoff for using this resistor

is an increase in quiescent current. In most cases, choos-

ing a small value of Ci in the range of 0.33µF to 1µF, Cb

being equal to 4.7µF and an external 1kΩ resistor should

be placed in parallel, and the internal 10kΩ resistor

should produce a virtually clickless and popless turn-on.

A high gain amplifier intensifies the problem as the small

delta in voltage is multiplied by the gain. So it is advanta-

geous to use low-gain configurations.

Shutdown Function

In order to reduce power consumption while not in use,

the APA2120/1 contain a shutdown pin to externally turn

off the amplifier bias circuitry. This shutdown feature turns

the amplifier off when a logic low is placed on the SHUT-

DOWN pin. The trigger point between a logic high and

logic low level is typically 2.0V. It is best to switch be-

tween the ground and the supply VDD to provide maximum

device performance.

By switching the SHUTDOWN pin to low, the amplifier

enters a low-current state, IDD<50µA. APA2120/1 is in shut-

down mode, except PC-BEEP detect circuit. Under nor-

mal operation, SHUTDOWN pin pulls to high level to keep

the IC out of the shutdown mode. The SHUTDOWN pin

should be tied to a definite voltage to avoid unwanted

state changing.

Input HP/LINE Operation

APA2120/1 amplifiers have two separate inputs for each

of the left and right stereo channels. The APA2120 and

APA2121 have different control input by SE/BTL and HP/

LINE, respectively.

APA2120 internal multiplexor is selected by SE/BTL con-

trol input. Refer to the ‘Output SE/BTL Operation’, the volt-

age divider of 100kΩ and 1kΩ sets the voltage at the SE/

BTL pin to be approximately 50mV when no phonejack

plugged into the system.

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw21

• To enable the HP(headphone) inputs, set HP/LINE

pin to a high level.

As APA2121, HP/LINE input multiplexor and SE/BTL out-

put operating mode have independent control paths,

which can be used for multiple audio input system. This

function will be the same as APA2120 when HP/LINE and

SE/BTL are tied together.

• To select the LINE inputs, set HP/LINE pin to a low

level.

Application Information (Cont.)

Input HP/LINE Operation (Cont.)

This logic-low voltage at the SE/BTL pin makes APA2120

into LINE input mode operation. It becomes HP input

mode when phonejack plugged.

An internal multiplexor selects the input to connect to the

amplifier based on the state of the HP/LINE pin of the

APA2121.

PC-BEEP Detection

APA2120/1 integrate a BEEP detect circuit for NOTEBOOK

PC. When BEEP signal is provided on the PCBEEP input

pin, the BEEP mode is active. APA2120/1 will force to BTL

mode and the internal gain is fixed at -10dB. The PCBEEP

signal becomes the amplifier input signal and plays on

the speaker without coupling capacitor. It will be out of

shutdown mode whenever BEEP mode is enabled.

APA2120/1 will return to previous setting when it is out of

BEEP mode. The input impedance is 100kΩ on the

PCBEEP input pin.

APA2120 provide extra PCBEN control input signal to force

IC into BEEP mode. The BEEP mode will be enabled

when PCBEN goes to a high level. When the BEEP mode

is overridden, the signal from the PCBEEP will pass to

speaker directly.

Clock Generator

APA2120/1 integrate a clock block to avoid volume con-

trol function abnormal when VOLUME control signal with

spike or noise. APA2120/1 change each step of volume

gain after four clock cycles make sure control signal ready.

It provides 130kHz frequency if no capacitor is placed on

CLK pin to the ground. The larger capacitance will slow

down the and clock frequency. A capacitor 33nF between

CLK to the ground and will generate 147Hz frequency on

the CLK pin.

BTL Amplifier Efficiency

An easy-to-use equation to calculate efficiency starts out

as being equal to the ratio of power from the power sup-

ply to the power delivered to the load.

The following equations are the basis for calculating

amplifier efficiency.

Where :

PSUP

Efficiency =(9)

PO = =

VORMS x VORMS2RL

VPxVP

VORMS =√2

VP(10)

(11)

PSUP = VDD x IDDAVG = VDD x2VP

πRL

Table 1 Calculates Efficiencies for Four Different Output

Power Levels.

Note that the efficiency of the amplifier is quite low for

lower power levels and rises sharply as power to the load

is increased resulting in a nearly flat internal power dissi-

pation over the normal operating range. Note that the in-

ternal dissipation at full output power is less than the

dissipation in the half power range. Calculating the effi-

ciency for a specific system is the key to proper power

supply design. For a stereo 1W audio system with 8Ω

loads and a 5V supply, the maximum draw on the power

supply is almost 3W.

A final point to remember about linear amplifiers (either

SE or BTL) is how to manipulate the terms in the effi-

ciency equation to an utmost advantage when possible.

Note that in equation, VDD is in the denominator. This indi-

cates that as VDD goes down, efficiency goes up. In other

words, use the efficiency analysis to choose the correct

supply voltage and speaker impedance for the application.

Po (W)

Efficiency (%) IDD(A)

VPP(V)

PD (W)

0.25 31.25 0.16 2.00 0.55

0.50 47.62 0.21 2.83 0.55

1.00 66.67 0.30 4.00 0.5

1.25 78.13 0.32 4.47 0.35

**High peak voltages cause the THD to increase.

Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL

Systems

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw22

Power Dissipation

Whether the power amplifier is operated in BTL or SE

modes, power dissipation is a major concern. Equation13

states the maximum power dissipation point for a SE

mode operating at a given supply voltage and driving a

specified load.

In BTL mode operation, the output voltage swing is

doubled as in SE mode. Thus, the maximum power dis-

sipation point for a BTL mode operating at the same given

conditions is 4 times as in SE mode.

Since the APA2120/1 are dual channel power amplifiers,

the maximum internal power dissipation is 2 times that

both of equations depend on the mode of operation. Even

this substantial increase in power dissipation, the

APA2120/1 do not require extra heatsink. The power dis-

sipation from equation14, assuming a 5V-power supply

and an 8Ω load, must not be greater than the power dis-

sipation that results from the equation15 :

For TSSOP-24 package with thermal pad, the thermal

resistance (θJA) is equal to 45οC/W.

Since the maximum junction temperature (TJ,MAX) of

APA2120/1 are 150οC and the ambient temperature (TA)

are defined by the power system design, the maximum

power dissipation which the IC package is able to handle

can be obtained from equation16.

Thermal Pad Consideration

For good thermal conduction, the vias must be plated

through and solder filled. The copper plane used to con-

duct heat away from the thermal pad should be as large

as practical.

If the ambient temperature is higher than 25°C, a larger

copper plane or forced-air cooling will be required to keep

the APA2120/1 junction temperature below the thermal

shutdown temperature (150°C). In higher ambient

temperature, higher airflow rate and/or larger copper area

will be required to keep the IC out of the thermal shutdown.

The thermal pad on the bottom of the APA2120/1 should

be soldered down to a copper pad on the circuit board.

Heat can be conducted away from the thermal pad through

the copper plane to ambient. If the copper plane is not on

the top surface of the circuit board, 8 to 10 vias of 13 mil or

smaller in diameter should be used to thermally couple

the thermal pad to the bottom plane.

Application Information (Cont.)

SE mode : PD,MAX=(13)

VDD

2π RL

BTL mode : PD,MAX=(14)

4VDD

2π RL

TJ,MAX - TA

θJA

PD,MAX=(15)

Once the power dissipation is greater than the maximum

limit (PD,MAX), either the supply voltage (VDD) must be

decreased, the load impedance (RL) must be increased

or the ambient temperature should be reduced.

The thermal pad must be connected to the ground. The

package with thermal pad of the APA2120/1 require spe-

cial attention on thermal design. If the thermal design

issues are not properly addressed, the APA2120/1 4Ω

will go into thermal shutdown when driving a 4Ω load.

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw23

Package Information

TSSOP-24P

Note : 1. Followed from JEDEC MO-153 ADT.

2. Dimension "D" does not include mold flash, protrusions

or gate burrs. Mold flash, protrusion or gate burrs shall not

exceed 6 mil per side.

3. Dimension "E1" does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

LMIN. MAX.

1.20

0.05

0.09 0.20

7.70 7.9

0.15

MILLIMETERS

b0.19 0.30

0.65 BSC

TSSOP-24P

0.45 0.75

0.026 BSC

MIN. MAX.

INCHES

0.047

0.002

0.007 0.012

0.004 0.008

0.303 0.311

0.169 0.177

0.018 0.030

0.006

A2 0.80 1.05

4.30 4.50E1

0.031 0.041

3.50D1 0.138

E2 2.50 0.098

6.00

3.50

0.197

0.138

INCHES

8o0o8o

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

SEE VIEW A

EXPOSED

PAD

6.20 6.60 0.244 0.260

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw24

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

16.4+2.00

0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

16.0±0.30

1.75±0.10

7.50±0.10

P0 P1 P2 D0 D1 T A0 B0 K0

TSSOP-24P

4.00±0.10

8.00±0.10

2.00±0.10

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

6.9±0.20

8.30.±0.20

1.50±0.20

(mm)

Carrier Tape & Reel Dimensions

Package Type Unit Quantity

TSSOP-24P Tape & Reel 2000

Devices Per Unit

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw25

Test item Method Description

SOLDERABILITY MIL-STD-883D-2003 245°C, 5 sec

HOLT MIL-STD-883D-1005.7 1000 Hrs Bias @125°C

PCT JESD-22-B,A102 168 Hrs, 100%RH, 121°C

TST MIL-STD-883D-1011.9 -65°C~150°C, 200 Cycles

ESD MIL-STD-883D-3015.7 VHBM > 2KV, VMM > 200V

Latch-Up JESD 78 10ms, 1tr > 100mA

Reflow Condition (IR/Convection or VPR Reflow)

t 25 C to Peak

Ramp-up

Ramp-down

Preheat

Tsmax

Tsmin

Temperature

Time

Critical Zone

TL to TP

Reliability Test Program

Taping Direction Information

TSSOP-24P

USER DIRECTION OF FEED

Rev. A.2 - Oct., 2008

APA2120/2121

www.anpec.com.tw26

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Average ramp-up rate

(TL to TP) 3°C/second max. 3°C/second max.

Preheat

- Temperature Min (Tsmin)

- Temperature Max (Tsmax)

- Time (min to max) (ts)

100°C

150°C

60-120 seconds

150°C

200°C

60-180 seconds

Time maintained above:

- Temperature (TL)

- Time (tL) 183°C

60-150 seconds 217°C

60-150 seconds

Peak/Classification Temperature (Tp)

See table 1 See table 2

Time within 5°C of actual

Peak Temperature (tp) 10-30 seconds 20-40 seconds

Ramp-down Rate 6°C/second max. 6°C/second max.

Time 25°C to Peak Temperature 6 minutes max. 8 minutes max.

Note: All temperatures refer to topside of the package. Measured on the body surface.

Table 2. Pb-free Process – Package Classification Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 +0°C* 260 +0°C* 260 +0°C*

1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C*

≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C*

* Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated

classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL

level.

Customer Service

Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures

Package Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 240 +0/-5°C 225 +0/-5°C

≥2.5 mm 225 +0/-5°C 225 +0/-5°C

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838