NXP Semiconductors Data Sheet: Technical Data Document Number MPC5746C Rev. 6, 11/2018 MPC5746C MPC5746C Microcontroller Datasheet Features * 1 x 160 MHz Power Architecture(R) e200z4 Dual issue, 32-bit CPU - Single precision floating point operations - 8 KB instruction cache and 4 KB data cache - Variable length encoding (VLE) for significant code density improvements * 1 x 80 MHz Power Architecture(R) e200z2 Single issue, 32-bit CPU - Using variable length encoding (VLE) for significant code size footprint reduction * End to end ECC - All bus masters, for example, cores, generate a single error correction, double error detection (SECDED) code for every bus transaction - SECDED covers 64-bit data and 29-bit address * Memory interfaces - 3 MB on-chip flash memory supported with the flash memory controller - 3 x flash memory page buffers (3-port flash memory controller) - 384 KB on-chip SRAM across three RAM ports * Clock interfaces - 8-40 MHz external crystal (FXOSC) - 16 MHz IRC (FIRC) - 128 KHz IRC (SIRC) - 32 KHz external crystal (SXOSC) - Clock Monitor Unit (CMU) - Frequency modulated phase-locked loop (FMPLL) - Real Time Counter (RTC) * System Memory Protection Unit (SMPU) with up to 32 region descriptors and 16-byte region granularity * 16 Semaphores to manage access to shared resources * Interrupt controller (INTC) capable of routing interrupts to any CPU * 32-channel eDMA controller with multiple transfer request sources using DMAMUX * Boot Assist Flash (BAF) supports internal flash programming via a serial link (SCI) * Analog - Two analog-to-digital converters (ADC), one 10-bit and one 12-bit - Three analog comparators - Cross Trigger Unit to enable synchronization of ADC conversions with a timer event from the eMIOS or from the PIT * Communication - Four Deserial Serial Peripheral Interface (DSPI) - Four Serial Peripheral interface (SPI) - 16 serial communication interface (LIN) modules - Eight enhanced FlexCAN3 with FD support - Four inter-IC communication interface (I2C) - ENET complex (10/100 Ethernet) that supports Multi queue with AVB support, 1588, and MII/ RMII - Dual-channel FlexRay controller * Audio - Synchronous Audio Interface (SAI) - Fractional clock dividers (FCD) operating in conjunction with the SAI * Configurable I/O domains supporting FlexCAN, LINFlexD, Ethernet, and general I/O * Supports wake-up from low power modes via the WKPU controller * On-chip voltage regulator (VREG) * Debug functionality - e200z2 core:NDI per IEEE-ISTO 5001-2008 Class3+ - e200z4 core: NDI per IEEE-ISTO 5001-2008 Class 3+ * Crossbar switch architecture for concurrent access to peripherals, flash memory, and RAM from multiple bus masters NXP reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products. * Timer - 16 Periodic Interrupt Timers (PITs) - Two System Timer Modules (STM) - Three Software Watchdog Timers (SWT) - 64 Configurable Enhanced Modular Input Output Subsystem (eMIOS) channels * Device/board boundary Scan testing supported with Joint Test Action Group (JTAG) of IEEE 1149.1 and IEEE 1149.7 (CJTAG) * Security - Hardware Security Module (HSMv2) - Password and Device Security (PASS) supporting advanced censorship and life-cycle management - One Fault Collection and Control Unit (FCCU) to collect faults and issue interrupts * Functional Safety - ISO26262 ASIL-B compliance * Multiple operating modes - Includes enhanced low power operation MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 2 NXP Semiconductors Table of Contents 1 Block diagram.................................................................................... 4 2 Family comparison.............................................................................4 3 Ordering parts.....................................................................................8 6.3.3 Flash memory module life specifications............... 40 3.1 Determining valid orderable parts ..........................................8 6.3.4 Data retention vs program/erase cycles.................. 40 3.2 Ordering Information ............................................................. 9 6.3.5 Flash memory AC timing specifications................ 41 General............................................................................................... 9 6.3.6 Flash read wait state and address pipeline control 4 5 6 6.3.2 Flash memory Array Integrity and Margin Read specifications.......................................................... 39 4.1 Absolute maximum ratings..................................................... 9 settings ................................................................... 42 4.2 Recommended operating conditions....................................... 11 4.3 Voltage regulator electrical characteristics............................. 13 6.4.1 DSPI timing............................................................ 43 4.4 Voltage monitor electrical characteristics............................... 17 6.4.2 FlexRay electrical specifications............................ 49 4.5 Supply current characteristics................................................. 18 6.4.2.1 FlexRay timing....................................49 4.6 Electrostatic discharge (ESD) characteristics......................... 22 6.4.2.2 TxEN................................................... 49 4.7 Electromagnetic Compatibility (EMC) specifications............ 22 6.4.2.3 TxD..................................................... 50 I/O parameters....................................................................................23 6.4.2.4 RxD..................................................... 51 6.4 Communication interfaces.......................................................43 5.1 AC specifications @ 3.3 V Range...........................................23 6.4.3 Ethernet switching specifications........................... 52 5.2 DC electrical specifications @ 3.3V Range............................24 6.4.4 SAI electrical specifications .................................. 53 5.3 AC specifications @ 5 V Range..............................................25 5.4 DC electrical specifications @ 5 V Range..............................25 6.5.1 JTAG interface timing ........................................... 55 5.5 Reset pad electrical characteristics..........................................26 6.5.2 Nexus timing...........................................................58 5.6 PORST electrical specifications..............................................28 6.5.3 WKPU/NMI timing................................................ 60 Peripheral operating requirements and behaviours............................ 28 6.5.4 External interrupt timing (IRQ pin)........................ 61 6.1 Analog..................................................................................... 28 6.1.1 ADC electrical specifications................................. 28 6.1.2 Analog Comparator (CMP) electrical 6.5 7 specifications.......................................................... 33 6.2 Clocks and PLL interfaces modules........................................34 Dimensions.........................................................................................65 8.1 9 Thermal attributes................................................................... 61 Obtaining package dimensions ...............................................65 Pinouts................................................................................................66 6.2.1 Main oscillator electrical characteristics.................34 6.2.2 32 kHz Oscillator electrical specifications ............ 36 10 Reset sequence................................................................................... 66 6.2.3 16 MHz RC Oscillator electrical specifications......36 10.1 Reset sequence........................................................................ 66 6.2.4 128 KHz Internal RC oscillator Electrical 10.1.1 Reset sequence duration..........................................66 specifications ......................................................... 37 10.1.2 BAF execution duration..........................................66 PLL electrical specifications ..................................37 10.1.3 Reset sequence description..................................... 67 6.2.5 6.3 Thermal attributes.............................................................................. 61 7.1 8 Debug specifications............................................................... 55 Memory interfaces...................................................................38 6.3.1 Flash memory program and erase specifications.... 38 9.1 Package pinouts and signal descriptions................................. 66 11 Revision History.................................................................................69 11.1 Revision History......................................................................69 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 3 Block diagram 1 Block diagram 80 MHz e200z2 160 MHz e200z4 System bus masters 64-bit AHB 8 KB i-cache 4 KB d-cache SPFP-APU Nexus 3+ E2 E-ECC 64-bit AHB System E2 E-ECC Nexus 3+ 64-bit data E2 E-ECC Flash Memory 2xRAM E2 E-ECC E2 E-ECC 3 x SA-PF buffers 64-bit wide RAM Triple ported 256 KB array 3 MB array (inc EEE) 256 KB array Ethernet (ENET) HSMv2 eDMA Flexray SMPU Peripheral bridge E2 E-ECC WKPU 2 x STM BAF PMC FMPLL 16 MHz FIRC RTC/API DEBUG/ JTAG 2 x SWTs FCCU 16 x SEMA42 PASS 16 x PIT-RTI SSCM 32 KHz SXOSC MC_CGM, MC_PCU, MC_ME, MC_RGM 128 KHz SIRC SIUL 8-40 MHz FXOSC STCU (MBIST) MEMU CMU Padkeeper support TDM Low power unit interface (LPU) Peripheral clusters 68 ch 10-bit ADC0 31 ch 12-bit ADC1 1 x FlexCAN(PN)* (mix int and ext) 7 x FlexCAN* 16 x LINFlexD 4 x I2C 3 x analog comparator (CMP) 4 x DSPI 4 x SPI 3 x SAI 3 x FCD 2 x eMIOS + BCTU 2-core INTC DMA and 2 x channel mux 1 x CRC Register protection * All FlexCANs optionally support CAN FD Figure 1. MPC5746C block diagram 2 Family comparison The following table provides a summary of the different members of the MPC5746C family and their proposed features. This information is intended to provide an understanding of the range of functionality offered by this family. For full details of all of the family derivatives please contact your marketing representative. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 4 NXP Semiconductors Family comparison NOTE All optional features (Flash memory, RAM, Peripherals) start with lowest number or address (e.g., FlexCAN0) and end at highest available number or address (e.g., MPC574xB/C have 6 CAN, ending with FlexCAN5). Table 1. MPC5746C Family Comparison1 Feature MPC5745B MPC5744B MPC5746B MPC5744C MPC5745C MPC5746C CPUs e200z4 e200z4 e200z4 e200z4 e200z4 e200z4 e200z2 e200z2 e200z2 FPU e200z4 e200z4 e200z4 e200z4 e200z4 e200z4 Maximum Operating Frequency2 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 160MHz (Z4) 80MHz (Z2) 80MHz (Z2) 80MHz (Z2) Flash memory 2 MB 1.5 MB 2 MB 3 MB EEPROM support RAM 1.5 MB 3 MB Emulated up to 64K 256 KB 192 KB Emulated up to 128K 384 KB (Optional 512KB)3 192 KB ECC End to End SMPU 16 entry DMA 32 channels 10-bit ADC 36 Standard channels 256 KB 384 KB (Optional 512KB)3 32 External channels 12-bit ADC 15 Precision channels 16 Standard channels Analog Comparator 3 BCTU 1 SWT 1, SWT[0] STM 1, STM[0] PIT-RTI 24 2 16 channels PIT 1 channels RTI RTC/API Total Timer 1 I/O5 64 channels 16-bits LINFlexD FlexCAN DSPI/SPI 1 1 Master and Slave (LINFlexD[0], 11 Master (LINFlexD[1:11]) Master and Slave (LINFlexD[0], 15 Master (LINFlexD[1:15]) 6 with optional CAN FD support (FlexCAN[0:5]) 8 with optional CAN FD support (FlexCAN[0:7]) 4 x DSPI 4 x SPI Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 5 Family comparison Table 1. MPC5746C Family Comparison1 (continued) Feature MPC5745B MPC5744B MPC5746B MPC5744C I2C 4 4 4 4 SAI/I2S 3 3 3 3 FXOSC 8 - 40 MHz SXOSC 32 KHz FIRC 16 MHz SIRC 128 KHz FMPLL 1 Low Power Unit (LPU) Yes MPC5745C FlexRay 2.1 (dual channel) Yes, 128 MB Yes, 128 MB Yes, 128 MB Yes, 128 MB Ethernet (RMII, MII + 1588, Muti queue AVB support) 1 1 1 1 CRC 1 MEMU 2 STCU2 1 HSM-v2 (security) Optional Censorship Yes FCCU 1 Safety level Specific functions ASIL-B certifiable User MBIST Yes I/O Retention in Standby Yes GPI 1 (100 BGA), 17 (176 LQFP-EP), 18 (256 BGA), 18 (324 BGA) GPIO 65 (100 BGA), 129 (176 LQFP-EP), 178 (256 BGA), 246 (324 BGA) Debug JTAGC, MPC5746C cJTAG Nexus Z4 N3+ (Only available on 324BGA (development only) ) Z2 N3+ (Only available on 324BGA (development only) ) Packages 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 176 LQFP-EP 256 BGA 256 BGA 256 BGA 256 BGA 256 BGA 256 BGA, 100 BGA 100 BGA 100 BGA 100 BGA 100 BGA 324 BGA (development only) 100 BGA 1. Feature set dependent on selected peripheral multiplexing, table shows example. Peripheral availability is package dependent. 2. Based on 125C ambient operating temperature and subject to full device characterization. 3. Contact NXP representative for part number 4. Additional SWT included when HSM option selected MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 6 NXP Semiconductors Family comparison 5. See device datasheet and reference manual for information on to timer channel configuration and functions. Table 2. MPC5746C Family Comparison - NVM Memory Map 1 Start Address End Address Flash block RWW partition MPC5744 MPC5745 MPC5746 0x01000000 0x0103FFFF 256 KB code Flash block 0 6 available available available 0x01040000 0x0107FFFF 256 KB code Flash block 1 6 available available available 0x01080000 0x010BFFFF 256 KB code Flash block 2 6 available available available 0x010C0000 0x010FFFFF 256 KB code Flash block3 6 available available available 0x01100000 0x0113FFFF 256 KB code Flash block 4 6 not available available available 0x01140000 0x0117FFFF 256 KB code Flash block 5 7 not available available available 0x01180000 0x011BFFFF 256 KB code Flash block 6 7 not available not available available 0x011C0000 0x011FFFFF 256 KB code Flash block 7 7 not available not available available 0x01200000 0x0123FFFF 256 KB code Flash block 8 7 not available not available available 0x01240000 0x0127FFFF 256 KB code Flash block 9 7 not available not available available Table 3. MPC5746C Family Comparison - NVM Memory Map 2 Start Address End Address Flash block RWW partition MPC5744B MPC5745B MPC5746B MPC5744C MPC5745C MPC5746C 0x00F900001 0x00F93FFF 16 KB data Flash 2 available available1 0x00F94000 0x00F97FFF 16 KB data Flash 2 available available1 0x00F98000 0x00F9BFFF 16 KB data Flash 2 available available1 0x00F9C000 0x00F9FFFF 16 KB data Flash 2 available available1 0x00FA0000 0x00FA3FFF 16 KB data Flash 3 not available available1 0x00FA4000 0x00FA7FFF 16 KB data Flash 3 not available available1 0x00FA8000 0x00FABFFF 16 KB data Flash 3 not available available1 0x00FAC000 0x00FAFFFF 16 KB data Flash 3 not available available1 0x00FB0000 0x00FB7FFF 32 KB data Flash Reserved 0x00FB8000 0x00FBFFFF 32 KB data Flash Reserved 0x00FC0000 0x00FC7FFF 32 KB data Flash 0 available available 0x00FC8000 0x00FCFFFF 32 KB data Flash 1 available available 0x00FD0000 0x00FD7FFF 32 KB data Flash 1 available available 0x00FD8000 0x00FDFFFF 32 KB data Flash 1 available available 0x00FE0000 0x00FEFFFF 64 KB data Flash 0 available available 0x00FF0000 0x00FFFFFF 64 KB data Flash 1 available available MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 7 Ordering parts 1. Flexible patitions for boot and EEPROM Table 4. MPC5748G Family Comparison - NVM Memory Map 3 Start Address End Address Flash block RWW MPC5744B MPC5745B MPC5746B MPC5744C MPC5745C MPC5746C 0x00610000 0x0061FFFF 64 KB HSM Code block 2 0 available available 0x00620000 0x0062FFFF 64 KB HSM Code block 3 1 available available HSM Data 0x00630000 0x00F7FFFF 9536 KB Reserved HSM Data 0x00F80000 0x00F83FFF 16 KB HSM data block 0 4 available available 0x00F84000 0x00F87FFF 16 KB HSM data block 1 5 available available 0x00F88000 0x00F8BFFF 16 KB Reserved Small HSM Code Block 0x00F8C000 0x00F8FFFF 16 KB Code Flash block 0 available available Table 5. MPC5746C Family Comparison - RAM Memory Map Start Address End Address Allocated size Description MPC5744 MPC5745 MPC5746 0x40000000 0x40001FFF 8 KB SRAM0 available available available 0x40002000 0x4000FFFF 56 KB SRAM1 available available available 0x40010000 0x4001FFFF 64 KB SRAM2 available available available 0x40020000 0x4002FFFF 64 KB SRAM3 available available available 0x40030000 0x4003FFFF 64 KB SRAM4 not available available available 0x40040000 0x4004FFFF 64 KB SRAM5 not available not available available 0x40050000 0x4005FFFF 64 KB SRAM6 not available not available available 0x40060000 0x4006FFFF 64 KB SRAM7 not available not available optional 0x40070000 0x4007FFFF 64 KB SRAM8 not available not available optional 3 Ordering parts 3.1 Determining valid orderable parts To determine the orderable part numbers for this device, go to www.nxp.com and perform a part number search for the following device number: MPC5746C. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 8 NXP Semiconductors General 3.2 Ordering Information P Example Code PC 57 4 6 C S K0 M MJ 6 R Qualification Status Power Architecture Automotive Platform Core Version Flash Size (core dependent) Product Optional fields Fab and mask indicator Temperature spec. Package Code CPU Frequency R = Tape & Reel (blank if Tray) Product Version B = Single core C = Dual core Qualification Status P = Engineering samples S = Automotive qualified PC = Power Architecture Automotive Platform 57 = Power Architecture in 55nm Core Version 4 = e200z4 Core Version (highest core version in the case of multiple cores) Flash Memory Size 4 = 1.5 MB 5 = 2 MB 6 = 3 MB Optional fields Blank = No optional feature S = HSM (Security Module) Fab and mask version indicator K = TSMC Fab #(0,1,etc.) = Version of the maskset, like rev. 0=0N65H Package Code KU = 176 LQFP EP MJ = 256 MAPBGA MN M = 324 MAPBGA MH = 100MAPBGA Temperature spec. C = -40.C to +85.C Ta V = -40.C to +105.C Ta M = -40.C to +125.C Ta CPU Frequency F = CAN FD B = HSM + CAN FD R = 512K RAM T = HSM + 512K RAM G* = CAN FD + 512K RAM H* = HSM + CAN FD + 512K RAM * G and H for 5746 B/C only 2 = Z4 operates upto 120 MHz 6 = Z4 operates upto 160 MHz Shipping Method R = Tape and reel Blank = Tray Note: Not all part number combinations are available as production product 4 General 4.1 Absolute maximum ratings NOTE Functional operating conditions appear in the DC electrical characteristics. Absolute maximum ratings are stress ratings only, and functional operation at the maximum values is not guaranteed. See footnotes in Table 6 for specific conditions MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 9 General Stress beyond the listed maximum values may affect device reliability or cause permanent damage to the device. Table 6. Absolute maximum ratings Symbol Conditions1 Min Max Unit 3.3 V - 5. 5V input/output supply voltage -- -0.3 6.0 V 3.3 V flash supply voltage (when supplying from an external source in bypass mode) -- -0.3 3.63 V Decoupling pin for low power regulators7 -- -0.3 1.32 V 3.3 V / 5.0 V ADC1 high reference voltage -- -0.3 6 V 3.3 V to 5.5V ADC supply voltage -- -0.3 6.0 V 3.3V to 5.5V ADC supply ground -- -0.1 0.1 V Parameter VDD_HV_A, VDD_HV_B, VDD_HV_C2, 3 VDD_HV_FLA4, 5 VDD_LP_DEC6 8 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV9, 10, 11, 12 Core logic supply voltage -- -0.3 1.32 V VINA Voltage on analog pin with respect to ground (VSS_HV) -- -0.3 Min (VDD_HV_x, VDD_HV_ADCx, VDD_ADCx_REF) +0.3 V VIN Voltage on any digital pin with respect to ground (VSS_HV) Relative to VDD_HV_A, VDD_HV_B, VDD_HV_C -0.3 VDD_HV_x + 0.3 V Always -5 5 mA IINJPAD Injected input current on any pin during overload condition IINJSUM Absolute sum of all injected input currents during overload condition -- -50 50 mA Tramp Supply ramp rate -- 0.5 V / min 100V/ms -- TA13 Ambient temperature -- -40 125 C TSTG Storage temperature -- -55 165 C 1. All voltages are referred to VSS_HV unless otherwise specified 2. VDD_HV_B and VDD_HV_C are common together on the 176 LQFP-EP package. 3. Allowed VDD_HV_x = 5.5-6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ= 150 C, remaining time at or below 5.5 V. 4. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V 5. VDD_HV_FLA must be disconnected from ANY power sources when VDD_HV_A = 5V 6. This pin should be decoupled with low ESR 1 F capacitor. 7. Not available for input voltage, only for decoupling internal regulators 8. 10-bit ADC does not have dedicated reference and its reference is bonded to 10-bit ADC supply(VDD_HV_ADC0) inside the package. 9. Allowed 1.45 - 1.5 V for 60 seconds cumulative time at maximum TJ = 150 C, remaining time as defined in footnotes 10 and 11. 10. Allowed 1.38 - 1.45 V- for 10 hours cumulative time at maximum TJ = 150 C, remaining time as defined in footnote 11. 11. 1.32 - 1.38 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.326 V at maximum TJ = 150 C. 12. If HVD on core supply (VHVD_LV_x) is enabled, it will generate a reset when supply goes above threshold. 13. TJ=150C. Assumes TA=125C * Assumes maximum JA for 2s2p board. See Thermal attributes MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 10 NXP Semiconductors General 4.2 Recommended operating conditions The following table describes the operating conditions for the device, and for which all specifications in the data sheet are valid, except where explicitly noted. The device operating conditions must not be exceeded in order to guarantee proper operation and reliability. The ranges in this table are design targets and actual data may vary in the given range. NOTE * For normal device operations, all supplies must be within operating range corresponding to the range mentioned in following tables. This is required even if some of the features are not used. * If VDD_HV_A is in 5.0V range, VDD_HV_FLA should be externally supplied using a 3.3V source. If VDD_HV_A is in 3.3V range, VDD_HV_FLA should be shorted to VDD_HV_A. * VDD_HV_A, VDD_HV_B and VDD_HV_C are all independent supplies and can each be set to 3.3V or 5V. The following tables: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' and table 'Recommended operating conditions (VDD_HV_x = 5 V)' specify their ranges when configured in 3.3V or 5V respectively. Table 7. Recommended operating conditions (VDD_HV_x = 3.3 V) Symbol VDD_HV_A Conditions1 Min2 Max Unit HV IO supply voltage -- 3.15 3.6 V HV flash supply voltage -- 3.15 3.6 V HV ADC1 high reference voltage -- 3.0 5.5 V HV ADC supply voltage -- max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 3.6 V HV ADC supply ground -- -0.1 0.1 V Core supply voltage -- 1.2 1.32 V Analog Comparator DAC reference voltage -- 3.15 3.6 V Injected input current on any pin during overload condition -- -3.0 3.0 mA Parameter VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4, 5 VIN1_CMP_REF6, 7 IINJPAD Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 11 General Table 7. Recommended operating conditions (VDD_HV_x = 3.3 V) (continued) Symbol Parameter Conditions1 Min2 Max Unit TA8 Ambient temperature under bias fCPU 160 MHz -40 125 C TJ Junction temperature under bias -- -40 150 C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. VDD_HV_FLA must be connected to VDD_HV_A when VDD_HV_A = 3.3V 4. Only applicable when supplying from external source. 5. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating. 6. VIN1_CMP_REF VDD_HV_A 7. This supply is shorted VDD_HV_A on lower packages. 8. TJ=150C. Assumes TA=125C * Assumes maximum JA of 2s2p board. See Thermal attributes NOTE If VDD_HV_A is in 5V range, it is necessary to use internal Flash supply 3.3V regulator. VDD_HV_FLA should not be supplied externally and should only have decoupling capacitor. Table 8. Recommended operating conditions (VDD_HV_x = 5 V) Symbol Conditions 1 Min2 Max Unit HV IO supply voltage -- 4.5 5.5 V HV flash supply voltage -- 3.15 3.6 V HV ADC1 high reference voltage -- 3.15 5.5 V HV ADC supply voltage -- max(VDD_H V_A,VDD_H V_B,VDD_H V_C) - 0.05 5.5 V HV ADC supply ground -- -0.1 0.1 V Core supply voltage -- 1.2 1.32 V V Parameter VDD_HV_A VDD_HV_B VDD_HV_C VDD_HV_FLA3 VDD_HV_ADC1_REF VDD_HV_ADC0 VDD_HV_ADC1 VSS_HV_ADC0 VSS_HV_ADC1 VDD_LV4 6 VIN1_CMP_REF IINJPAD Analog Comparator DAC reference voltage -- 3.15 5.55 Injected input current on any pin during overload condition -- -3.0 3.0 mA TA7 Ambient temperature under bias fCPU 160 MHz -40 125 C TJ Junction temperature under bias -- -40 150 C 1. All voltages are referred to VSS_HV unless otherwise specified 2. Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. 3. When VDD_HV is in 5 V range, VDD_HV_FLA cannot be supplied externally.This pin is decoupled with Cflash_reg. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 12 NXP Semiconductors General 4. VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating 5. VIN1_CMP_REF VDD_HV_A 6. This supply is shorted VDD_HV_A on lower packages. 7. TJ=150C. Assumes TA=125C * Assumes maximum JA of 2s2p board. See Thermal attributes 4.3 Voltage regulator electrical characteristics The voltage regulator is composed of the following blocks: * Choice of generating supply voltage for the core area. * Control of external NPN ballast transistor * Generating core supply using internal ballast transistor * Connecting an external 1.25 V (nominal) supply directly without the NPN ballast * Internal generation of the 3.3 V flash supply when device connected in 5V applications * External bypass of the 3.3 V flash regulator when device connected in 3.3V applications * Low voltage detector - low threshold (LVD_IO_A_LO) for VDD_HV_IO_A supply * Low voltage detector - high threshold (LVD_IO_A_Hi) for VDD_HV_IO_A supply * Low voltage detector (LVD_FLASH) for 3.3 V flash supply (VDD_HV_FLA) * Various low voltage detectors (LVD_LV_x) * High voltage detector (HVD_LV_cold) for 1.2 V digital core supply (VDD_LV) * Power on Reset (POR_LV) for 1.25 V digital core supply (VDD_LV) * Power on Reset (POR_HV) for 3.3 V to 5 V supply (VDD_HV_A) The following bipolar transistors1 are supported, depending on the device performance requirements. As a minimum the following must be considered when determining the most appropriate solution to maintain the device under its maximum power dissipation capability: current, ambient temperature, mounting pad area, duty cycle and frequency for Idd, collector voltage, etc 1. BCP56, MCP68 and MJD31are guaranteed ballasts. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 13 General LPPREG VDD_LP_DEC VDD_HV_BALLAST ULPPREG CLP/ULPREG VRC_CTRL V SS_HV FPREG CBE_FPREG Flash voltage regulator V DD_LV VDD_HV_FLA CFLASH_REG CFP_REG VSS_HV VSS_HV DEVICE Figure 2. Voltage regulator capacitance connection NOTE On BGA, VSS_LV and VSS_HV have been joined on substrate and renamed as VSS. Table 9. Voltage regulator electrical specifications Symbol Cfp_reg 1 Clp/ulp_reg Cbe_fpreg3 Parameter Conditions Min Typ Max Unit 1.32 2.22 3 F -- 0.03 Ohm 1 1.4 F -- 0.1 Ohm External decoupling / stability capacitor Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor -- External decoupling / stability capacitor for internal low power regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. Combined ESR of external capacitor -- Capacitor in parallel to baseemitter BCP68 and BCP56 3.3 MJD31 4.7 0.001 0.8 0.001 nF Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 14 NXP Semiconductors General Table 9. Voltage regulator electrical specifications (continued) Symbol Conditions Min Typ Max Unit External decoupling / stability capacitor for internal Flash regulators Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1.32 2.2 3 F Combined ESR of external capacitor -- 0.001 -- 0.03 Ohm CHV_VDD_A VDD_HV_A supply capacitor 5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_VDD_B VDD_HV_B supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_VDD_C VDD_HV_C supply capacitor5 Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F CHV_ADC0 HV ADC supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 1 -- -- F HV ADC SAR reference supply decoupling capacitances Min, max values shall be granted with respect to tolerance, voltage, temperature, and aging variations. 0.47 -- -- F VDD_HV_BALL FPREG Ballast collector supply 7 voltage AST When collector of NPN ballast is directly supplied by an on board supply source (not shared with VDD_HV_A supply pin) without any series resistance, that is, RC_BALLAST less than 0.01 Ohm. 2.25 -- 5.5 V RC_BALLAST Series resistor on collector of FPREG ballast When VDD_HV_BALLAST is shorted to VDD_HV_A on the board -- -- 0.1 Ohm Start-up time with external ballastafter main supply (VDD_HV_A) stabilization Cfp_reg = 3 F -- 74 -- s tSU_int Start-up time with internal ballast after main supply (VDD_HV_A) stabilization Cfp_reg = 3 F -- 103 -- s tramp Load current transient Iload from 15% to 55% Cflash_reg4 CHV_ADC1 CHV_ADR6 tSU Parameter 1.0 s Cfp_reg = 3 F 1. Split capacitance on each pair VDD_LV pin should sum up to a total value of Cfp_reg 2. Typical values will vary over temperature, voltage, tolerance, drift, but total variation must not exceed minimum and maximum values. 3. Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is recommended. The tolerance +/-20% is acceptable. 4. It is required to minimize the board parasitic inductance from decoupling capacitor to VDD_HV_FLA pin and the routing inductance should be less than 1nH. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 15 General 5. 1. For VDD_HV_x, 1f on each side of the chip a. 0.1 f close to each VDD/VSS pin pair. b. 10 f near for each power supply source c. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter. 2. For VDD_LV, 0.1uf close to each VDD/VSS pin pair is required. Depending on the the selected regulation mode, this amount of capacitance will need to be subtracted from the total capacitance required by the regulator for e.g., as specified by CFP_REG parameter 6. Only applicable to ADC1 7. In external ballast configuration the following must be ensured during power-up and power-down (Note: If VDD_HV_BALLAST is supplied from the same source as VDD_HV_A this condition is implicitly met): * During power-up, VDD_HV_BALLAST must have met the min spec of 2.25V before VDD_HV_A reaches the POR_HV_RISE min of 2.75V. * During power-down, VDD_HV_BALLAST must not drop below the min spec of 2.25V until VDD_HV_A is below POR_HV_FALL min of 2.7V. NOTE For a typical configuration using an external ballast transistor with separate supply for VDD_HV_A and the ballast collector, a bulk storage capacitor (as defined in Table 9) is required on VDD_HV_A close to the device pins to ensure a stable supply voltage. Extra care must be taken if the VDD_HV_A supply is also being used to power the external ballast transistor or the device is running in internal regulation mode. In these modes, the inrush current on device Power Up or on exit from Low Power Modes is significant and may cause the VDD_HV_A voltage to drop resulting in an LVD reset event. To avoid this, the board layout should be optimized to reduce common trace resistance or additional capacitance at the ballast transistor collector (or VDD_HV_A pins in the case of internal regulation mode) is required. NXP recommends that customers simulate the external voltage supply circuitry. In all circumstances, the voltage on VDD_HV_A must be maintained within the specified operating range (see Recommended operating conditions) to prevent LVD events. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 16 NXP Semiconductors General 4.4 Voltage monitor electrical characteristics Table 10. Voltage monitor electrical characteristics Symbol Parameter State Conditions Configuration Power Up 1 VPOR_LV LV supply power on reset detector Fall Rise VHVD_LV_col LV supply high voltage d monitoring, detecting at device pin Fall VLVD_LV_PD LV supply low voltage 2_hot monitoring, detecting on the PD2 core (hot) area Fall VLVD_LV_PD LV supply low voltage 1_hot (BGFP) monitoring, detecting on the PD1 core (hot) area Fall VLVD_LV_PD LV supply low voltage 0_hot (BGFP) monitoring, detecting on the PD0 core (hot) area Fall VPOR_HV Fall HV supply power on reset detector Rise Rise Rise Rise VLVD_IO_A_H HV IO_A supply 3 low voltage I monitoring - high range Fall Rise Fall Rise Typ Max V 1.028 V Trimmed - - - V Untrimmed 0.980 1.029 1.078 V Trimmed - - - V 1.375 V Yes POR Min 0.979 No No Reset Type Unit 0.930 Untrimmed Yes Trimmed Rise VLVD_IO_A_L HV IO_A supply ,3 low voltage O monitoring - low range Untrimmed Mask Opt2 Threshold Function Disabled at Start al 1.325 1.345 Untrimmed Disabled at Start Trimmed 1.345 1.365 1.395 V 1.0800 1.1200 1.1600 V Trimmed 1.1250 1.1425 1.1600 V Untrimmed 1.1000 1.1400 1.1800 V Trimmed 1.1450 1.1625 1.1800 V 1.0800 1.1200 1.1600 V Trimmed 1.1140 1.1370 1.1600 V Untrimmed 1.1000 1.140 1.1800 V Trimmed 1.1340 1.1570 1.1800 V Untrimmed Untrimmed Untrimmed Yes Yes No POR 1.0800 1.1200 1.1600 V 1.1140 1.1370 1.1600 V Untrimmed 1.1000 1.1400 1.1800 V Trimmed 1.1340 1.1570 1.1800 V 2.7000 2.8500 3.0000 V Trimmed - - - V Untrimmed 2.7500 2.9000 3.0500 V Trimmed - - - V 2.7500 2.9230 3.0950 V Trimmed 2.9780 3.0390 3.1000 V Untrimmed 2.7800 2.9530 3.1250 V Trimmed 3.0080 3.0690 3.1300 V Function Disabled at Start al 4.0600 4.151 4.2400 V 4.3000 V Untrimmed Trimmed Yes Yes No No POR Trimmed Untrimmed Yes No No No Yes POR POR POR Trimmed Disabled at Start 4.1150 4.2010 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 17 General Table 10. Voltage monitor electrical characteristics (continued) Symbol Parameter State Conditions Configuration Power Up 1 VLVD_LV_PD LV supply low voltage 2_cold monitoring, detecting at the device pin Fall Untrimmed No Mask Opt2 Yes Trimmed Rise Threshold Reset Type Min Unit Typ Max Function Disabled at Start al 1.1400 1.1550 1.1750 V 1.1950 V Untrimmed Disabled at Start Trimmed 1.1600 1.1750 V 1. All monitors that are active at power-up will gate the power up recovery and prevent exit from POWERUP phase until the minimum level is crossed. These monitors can in some cases be masked during normal device operation, but when active will always generate a POR reset. 2. Voltage monitors marked as non maskable are essential for device operation and hence cannot be masked. 3. There is no voltage monitoring on the VDD_HV_ADC0, VDD_HV_ADC1, VDD_HV_B and VDD_HV_C I/O segments. For applications requiring monitoring of these segments, either connect these to VDD_HV_A at the PCB level or monitor externally. 4.5 Supply current characteristics Current consumption data is given in the following table. These specifications are design targets and are subject to change per device characterization. NOTE The ballast must be chosen in accordance with the ballast transistor supplier operating conditions and recommendations. Table 11. Current consumption characteristics Symbol IDD_BODY_1 2, 3 Parameter RUN Body Mode Profile Operating current Conditions1 LV supply + HV supply + HV Flash supply + Min Typ Max Unit -- -- 147 mA 2 x HV ADC supplies4 Ta = 125C , 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 80MHz IDD_BODY_2 6 RUN Body Mode Profile Operating current Ta = 105C -- -- 142 mA Ta = 85 C -- -- 137 mA 246 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 -- -- Ta = 125C5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 160MHz Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 18 NXP Semiconductors General Table 11. Current consumption characteristics (continued) Symbol Conditions1 Parameter IDD_BODY_3 7 RUN Body Mode Profile Operating current Min Typ Max Unit Ta = 105C -- -- 235 mA Ta = 85C -- -- 210 mA 181 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 -- -- Ta = 125 C 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 120MHz IDD_BODY_4 8 RUN Body Mode Profile Operating current Ta = 105 C -- -- 176 mA Ta = 85C -- -- 171 mA 264 mA LV supply + HV supply + HV Flash supply + 2 x HV ADC supplies4 -- -- Ta = 125 C 5 VDD_LV = 1.25 V VDD_HV_A = 5.5V SYS_CLK = 120MHz IDD_STOP STOP mode Operating current Ta = 105 C -- -- 176 mA Ta = 85 C -- -- 171 mA -- 49 mA -- 10.6 -- -- 8.1 -- -- 4.6 -- Ta = 125 C9 -- VDD_LV = 1.25 V Ta = 105 C VDD_LV = 1.25 V Ta = 85 C VDD_LV = 1.25 V Ta = 25 C VDD_LV = 1.25 V IDD_HV_ADC_REF 10, 11 ADC REF Operating current Ta = 125 C5 -- 200 400 A 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 105 C -- 200 -- -- 200 -- -- 200 -- 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 85 C 2 ADCs operating at 80 MHz VDD_HV_ADC_REF = 5.5 V Ta = 25 C 2 ADCs operating at 80 MHz Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 19 General Table 11. Current consumption characteristics (continued) Symbol Parameter Conditions1 Min Typ Max Unit -- 1.2 2 mA VDD_HV_ADC_REF = 3.6 V 11 IDD_HV_ADCx ADC HV Operating current Ta = 125 C5 ADC operating at 80 MHz VDD_HV_ADC = 5.5 V Ta = 25 C -- 1 2 ADC operating at 80 MHz VDD_HV_ADC = 3.6 V IDD_HV_FLASH12 Flash Operating current during read access Ta = 125 C5 -- 40 45 mA 3.3 V supplies 160 MHz frequency Ta = 105 C -- 40 45 -- 40 45 3.3 V supplies 160 MHz frequency Ta = 85 C 3.3 V supplies 160 MHz frequency 1. The content of the Conditions column identifies the components that draw the specific current. 2. Single e200Z4 core cache disabled @80 MHz, no FlexRay, no ENET, 2 x CAN, 8 LINFlexD, 2 SPI, ADC0 and 1 used constantly, no HSM, Memory: 2M flash, 128K RAM RUN mode, Clocks: FIRC on, XOSC, PLL on, SIRC on for TOD, no 32KHz crystal (TOD runs off SIRC). 3. Recommended Transistors:MJD31 @ 85C, 105C and 125C. In case of internal ballast mode, it is expected that the external ballast is not mounted and BAL_SELECT_INT pin is tied to VDD_HV_A supply on board. Internal ballast can be used for all use cases with current consumption upto 150mA. For internal ballast configuration the VRC_CTL pin should be left floating. 4. The power consumption does not consider the dynamic current of I/Os 5. Tj=150C. Assumes Ta=125C * Assumes maximum JA of 2s2p board. SeeThermal attributes 6. e200Z4 core, 160MHz, cache enabled; e200Z2 core , 80MHz, no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 256K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 7. e200Z4 core, 120MHz, cache enabled; e200Z2 core, 60MHz; no FlexRay, no ENET, 7 CAN, 16 LINFlexD, 4 SPI, 1x ADC used constantly, includes HSM at start-up / periodic use, Memory: 3M flash, 128K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 8. e200Z4 core, 160MHz, cache enabled; e200Z4 core, 80MHz; HSM fully operational (Z0 core @80MHz) FlexRay, 5x CAN, 5x LINFlexD, 2x SPI, 1x ADC used constantly, 1xeMIOS (5 ch), Memory: 3M flash, 384K RAM, Clocks: FIRC on, XOSC on, PLL on, SIRC on, no 32KHz crystal 9. Assuming Ta=Tj, as the device is in Stop mode. Assumes maximum JA of 2s2p board. SeeThermal attributes. 10. Internal structures hold the input voltage less than VDD_HV_ADC_REF + 1.0 V on all pads powered by VDDA supplies, if the maximum injection current specification is met (3 mA for all pins) and VDDA is within the operating voltage specifications. 11. This value is the total current for two ADCs.Each ADC might consume upto 2mA at max. 12. This assumes the default configuration of flash controller register. For more details, refer to Flash memory program and erase specifications MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 20 NXP Semiconductors General Table 12. Low Power Unit (LPU) Current consumption characteristics Symbol LPU_RUN Conditions1 Parameter with 256K RAM Ta = 25 C Min Typ Max Unit -- 10 -- mA -- 10.5 -- -- 11 -- -- -- 26 SYS_CLK = 16MHz ADC0 = OFF, SPI0 = OFF, LIN0 = OFF, CAN0 = OFF Ta = 85 C SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON Ta = 105 C SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON Ta = 125 C, 2 SYS_CLK = 16MHz ADC0 = ON, SPI0 = ON, LIN0 = ON, CAN0 = ON LPU_STOP with 256K RAM Ta = 25 C -- 0.18 Ta = 85 C -- 0.60 Ta = 105 C -- 1.00 Ta = 125 C 2 -- -- -- mA -- -- 10.6 1. The content of the Conditions column identifies the components that draw the specific current. 2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum JA of 2s2p board. SeeThermal attributes Table 13. STANDBY Current consumption characteristics Symbol STANDBY0 Conditions1 Parameter STANDBY with 8K RAM Ta = 25 C Ta = 85 C Ta = 105 C Ta = 125 C STANDBY1 STANDBY2 STANDBY with 64K RAM STANDBY with 128K RAM ,2 Ta = 25 C STANDBY3 FIRC ON Max Unit -- 71 -- A -- 125 700 -- 195 1225 -- 314 2100 72 -- Ta = 85 C -- 140 715 Ta = 105 C -- 225 1275 Ta = 125 C 2 -- 358 2250 Ta = 25 C -- Ta = 85 C Ta = 125 C STANDBY with 256K RAM Typ -- Ta = 105 C STANDBY3 Min 2 Ta = 25 C 75 -- -- 155 730 -- 255 1350 -- 396 2600 -- 80 -- Ta = 85 C -- 180 800 Ta = 105 C -- 290 1425 Ta = 125 C 2 -- 465 2900 Ta = 25 C -- 500 -- A A A A MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 21 General 1. The content of the Conditions column identifies the components that draw the specific current. 2. Assuming Ta=Tj, as the device is in static (fully clock gated) mode. Assumes maximum JA of 2s2p board. SeeThermal attributes NOTE For the Precision channel Analog inputs, SIUL2_MSCRn[PUS] must be configured to 0 before entering STANDBY. An increase in current would be observed when SIUL2_MSCRn[PUS] is configured to be 1, irrespective of the state of IBE or PUE. The current numbers would increase irrespective of whether the pad is pulled low/high externally. 4.6 Electrostatic discharge (ESD) characteristics Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n + 1) supply pin). This test conforms to the AEC-Q100-002/-003/-011 standard. NOTE A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification requirements. Complete DC parametric and functional testing shall be performed per applicable device specification at room temperature followed by hot temperature, unless specified otherwise in the device specification. Table 14. ESD ratings Symbol VESD(HBM) VESD(CDM) Parameter Conditions1 Electrostatic discharge TA = 25 C (Human Body Model) conforming to AECQ100-002 Electrostatic discharge TA = 25 C (Charged Device Model) conforming to AECQ100-011 Class Max value2 Unit H1C 2000 V C3A 500 V 750 (corners) 1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. 2. Data based on characterization results, not tested in production. 4.7 Electromagnetic Compatibility (EMC) specifications EMC measurements to IC-level IEC standards are available from NXP on request. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 22 NXP Semiconductors I/O parameters 5 I/O parameters 5.1 AC specifications @ 3.3 V Range Table 15. Functional Pad AC Specifications @ 3.3 V Range Prop. Delay (ns)1 Symbol Rise/Fall Edge (ns) L>H/H>L Min Max 1.9/1.5 25 2.5/2.5 8.25/7.5 0.8/0.6 3.25/3 50 6.4/5 19.5/19.5 3.5/2.5 12/12 200 2.2/2.5 8/8 0.55/0.5 3.9/3.5 25 pad_sr_hv Min 6/6 (output) pad_i_hv/ pad_sr_hv Drive Load (pF) Max MSB,LSB 0.090 1.1 0.035 1.1 asymmetry2 2.9/3.5 12.5/11 1/1 7/6 50 11/8 35/31 7.7/5 25/21 200 8.3/9.6 45/45 4/3.5 25/25 50 13.5/15 65/65 6.3/6.2 30/30 200 13/13 75/75 6.8/6 40/40 50 21/22 100/100 11/11 51/51 200 0.5/0.5 0.5 2/2 SIUL2_MSCRn[SRC 1:0] 11 10 01 003 NA (input)4 1. As measured from 50% of core side input to Voh/Vol of the output 2. This row specifies the min and max asymmetry between both the prop delay and the edge rates for a given PVT and 25pF load. Required for the Flexray spec. 3. Slew rate control modes 4. Input slope = 2ns NOTE The specification given above is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The specification given above is measured between 20% / 80%. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 23 I/O parameters 5.2 DC electrical specifications @ 3.3V Range Table 16. DC electrical specifications @ 3.3V Range Symbol Parameter Value Unit Min Max Vih (pad_i_hv) Pad_I_HV Input Buffer High Voltage 0.72*VDD_HV_ x VDD_HV_x + 0.3 V Vil (pad_i_hv) Pad_I_HV Input Buffer Low Voltage VDD_HV_x 0.3 0.45*VDD_HV_ x V Vhys (pad_i_hv) Pad_I_HV Input Buffer Hysteresis 0.11*VDD_HV_ x Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.67*VDD_HV_ x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VDD_HV_x 0.3 0.35*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.57 * VDD_HV_x1 VDD_HV_x1 + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VDD_HV_x 0.3 0.4 * VDD_HV_x1 V CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x1 V 15 A Vhys Pull_IIH (pad_i_hv) Weak Pullup Current2 Low Current3 Pull_IIH (pad_i_hv) Weak Pullup High 55 Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low 28 Pull_IIL (pad_i_hv) Weak Pulldown Current2 High Pull_Ioh Weak Pulldown Iinact_d Digital Pad Input Leakage Current (weak pull inactive) Voltage6 Voh Output High Vol Output Low Voltage7 A A 15 50 A 15 50 A -2.5 2.5 A 0.8 *VDD_HV_x1 -- V -- 0.2 *VDD_HV_x1 V Current5 Pull_Iol A 85 Current4 Weak Pullup V Output Low Voltage8 0.1 *VDD_HV_x Ioh_f Iol_f Ioh_h Iol_h 1. 2. 3. 4. 5. 6. 7. 8. 9. Full drive Ioh9 Full drive Iol9 Half drive Ioh9 Half drive Iol9 (SIUL2_MSCRn.SRC[1:0] = 11) 18 70 mA 21 120 mA 9 35 mA 10.5 60 mA (SIUL2_MSCRn.SRC[1:0] = 11) (SIUL2_MSCRn.SRC[1:0] = 10) (SIUL2_MSCRn.SRC[1:0] = 10) VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 24 NXP Semiconductors I/O parameters 5.3 AC specifications @ 5 V Range Table 17. Functional Pad AC Specifications @ 5 V Range Prop. Delay (ns)1 Symbol Rise/Fall Edge (ns) Drive Load (pF) SIUL2_MSCRn[SRC 1:0] L>H/H>L Min pad_sr_hv (output) pad_i_hv/ pad_sr_hv Max Min Max MSB,LSB 4.5/4.5 1.3/1.2 25 6/6 2.5/2 50 13/13 9/9 200 5.25/5.25 3/2 25 9/8 5/4 50 22/22 18/16 200 27/27 13/13 50 40/40 24/24 200 40/40 24/24 50 65/65 40/40 200 1.5/1.5 0.5/0.5 0.5 11 10 012 002 NA (input) 1. As measured from 50% of core side input to Voh/Vol of the output 2. Slew rate control modes NOTE The above specification is based on simulation data into an ideal lumped capacitor. Customer should use IBIS models for their specific board/loading conditions to simulate the expected signal integrity and edge rates of their system. NOTE The above specification is measured between 20% / 80%. 5.4 DC electrical specifications @ 5 V Range Table 18. DC electrical specifications @ 5 V Range Symbol Vih (pad_i_hv) Parameter pad_i_hv Input Buffer High Voltage Value Unit Min Max 0.7*VDD_HV_x VDD_HV_x + 0.3 V Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 25 I/O parameters Table 18. DC electrical specifications @ 5 V Range (continued) Symbol Vil (pad_i_hv) Vhys (pad_i_hv) Parameter pad_i_hv Input Buffer Low Voltage pad_i_hv Input Buffer Hysteresis Value Min Max VDD_HV_x 0.3 0.45*VDD_HV_ x 0.09*VDD_HV_ x V V Vih_hys CMOS Input Buffer High Voltage (with hysteresis enabled) 0.65* VDD_HV_x VDD_HV_x + 0.3 V Vil_hys CMOS Input Buffer Low Voltage (with hysteresis enabled) VDD_HV_x 0.3 0.35*VDD_HV_ x V Vih CMOS Input Buffer High Voltage (with hysteresis disabled) 0.55 * VDD_HV_x1 VDD_HV_x1 + 0.3 V Vil CMOS Input Buffer Low Voltage (with hysteresis disabled) VDD_HV_x 0.3 0.40 * VDD_HV_x1 V CMOS Input Buffer Hysteresis 0.09 * VDD_HV_x1 V 23 A Vhys Pull_IIH (pad_i_hv) Weak Pullup Current2 Low Current3 Pull_IIH (pad_i_hv) Weak Pullup High Pull_IIL (pad_i_hv) Weak Pulldown Current3 Low Pull_IIL (pad_i_hv) Weak Pulldown Current2 High 82 40 A A 130 A Pull_Ioh Weak Pullup Current4 30 80 A Pull_Iol Weak Pulldown Current5 30 80 A Iinact_d Digital Pad Input Leakage Current (weak pull inactive) -2.5 2.5 A 0.8 * VDD_HV_x1 -- V -- 0.2*VDD_HV_x V Voltage6 Voh Output High Vol Output Low Voltage7 Output Low Ioh_f Iol_f 1. 2. 3. 4. 5. 6. 7. 8. 9. Unit Voltage8 Full drive Ioh9 Full drive Iol9 0.1*VDD_HV_x (SIUL2_MSCRn.SRC[1:0] = 11) (SIUL2_MSCRn.SRC[1:0] = 11) 18 70 mA 21 120 mA Ioh_h Half drive Ioh9 (SIUL2_MSCRn.SRC[1:0] = 10) 9 35 mA Iol_h Half drive Iol9 (SIUL2_MSCRn.SRC[1:0] = 10) 10.5 60 mA VDD_HV_x = VDD_HV_A, VDD_HV_B, VDD_HV_C Measured when pad=0.69*VDD_HV_x Measured when pad=0.49*VDD_HV_x Measured when pad = 0 V Measured when pad = VDD_HV_x Measured when pad is sourcing 2 mA Measured when pad is sinking 2 mA Measured when pad is sinking 1.5 mA Ioh/Iol is derived from spice simulations. These values are NOT guaranteed by test. 5.5 Reset pad electrical characteristics The device implements a dedicated bidirectional RESET pin. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 26 NXP Semiconductors I/O parameters AA A VDD_HV_IOx A VDDMIN PORST VIH VIL device reset forced by PORST device start-up phase Figure 3. Start-up reset requirements VPORST hw_rst VDD_HV_IO A `1' VIH VIL `0' filtered by hysteresis filtered by lowpass filter filtered by lowpass filter unknown reset state device under hardware reset WFRST WFRST WNFRST Figure 4. Noise filtering on reset signal Table 19. Functional reset pad electrical specifications Symbol Parameter Conditions Value Min VIH CMOS Input Buffer High Voltage -- VIL CMOS Input Buffer Low Voltage -- Typ 0.65*VD -- Unit Max D_HV_x VDD_HV_x +0.3 VDD_HV_ -- x-0.3 _x V 0.35*VDD_HV V Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 27 Peripheral operating requirements and behaviours Table 19. Functional reset pad electrical specifications (continued) Symbol Parameter Conditions Value Min Unit Typ Max VHYS CMOS Input Buffer hysterisis -- 300 -- -- mV VDD_POR Minimum supply for strong pull-down activation -- -- -- 1.2 V IOL_R Strong pull-down current 1 Device under power-on reset 0.2 -- -- mA 11 -- -- mA VDD_HV_IO= V DD_POR VOL = 0.35*VDD_HV_IO Device under power-on reset 3.0 V < VDD_HV_IO < 5.5 V VOL = 0.35*VDD_HV_IO WFRST RESET input filtered pulse -- -- -- 500 ns WNFRST RESET input not filtered pulse -- 2000 -- -- ns |IWPU| Weak pull-up current absolute value RESET pin VIN = VDD 23 -- 82 A 1. Strong pull-down is active on PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for RESET. 5.6 PORST electrical specifications Table 20. PORST electrical specifications Symbol Parameter Value Min WFPORST PORST input filtered pulse WNFPORST PORST input not filtered pulse VIH VIL Unit Typ Max -- -- 200 ns 1000 -- -- ns Input high level 0.65 x VDD_HV_A -- -- V Input low level -- -- 0.35 x V VDD_HV_A 6 Peripheral operating requirements and behaviours 6.1 Analog 6.1.1 ADC electrical specifications The device provides a 12-bit Successive Approximation Register (SAR) Analog-toDigital Converter. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 28 NXP Semiconductors Analog Offset Error OSE Gain Error GE 4095 4094 4093 4092 4091 4090 ( 2) 1 LSB ideal =(VrefH-VrefL)/ 4096 = 3.3V/ 4096 = 0.806 mV Total Unadjusted Error TUE = +/- 6 LSB = +/- 4.84mV code out 7 ( 1) 6 5 (5) 4 (4) 3 (3) 2 1 (1) Example of an actual transfer curve (2) The ideal transfer curve (3) Differential non-linearity error (DNL) (4) Integral non-linearity error (INL) (5) Center of a step of the actual transfer curve 1 LSB (ideal) 0 1 2 3 Offset Error OSE 4 5 6 7 4089 4090 4091 4092 4093 4094 4095 Vin(A) (LSBideal) Figure 5. ADC characteristics and error definitions MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 29 Analog 6.1.1.1 Input equivalent circuit and ADC conversion characteristics EXTERNAL CIRCUIT INTERNAL CIRCUIT SCHEME VDD_IO Source Filter RS Current Limiter RF Sampling RSW1 RAD RL CF VA Channel Selection CP1 CP2 CS RS Source Impedance RF Filter Resistance CF Filter Capacitance RL Current Limiter Resistance RSW1 Channel Selection Switch Impedance RAD Sampling Switch Impedance CP Pin Capacitance (two contributions, CP1 and CP2) CS Sampling Capacitance Figure 6. Input equivalent circuit NOTE The ADC performance specifications are not guaranteed if two ADCs simultaneously sample the same shared channel. Table 21. ADC conversion characteristics (for 12-bit) Min Typ1 Max Unit 15.2 80 80 MHz -- -- 1.00 MHz 80 MHz@ 100 ohm source impedance 250 -- -- ns Conversion time4 80 MHz 700 -- -- ns Total Conversion time tsample + tconv (for standard and extended channels) 80 MHz 1.55 -- -- s 1 -- -- Symbol fCK fs Parameter Conditions ADC Clock frequency (depends on -- ADC configuration) (The duty cycle depends on AD_CK2 frequency) Sampling frequency tsample tconv ttotal_conv Sample 80 MHz time3 Total Conversion time tsample + tconv (for precision channels) CS, 6 ADC input sampling capacitance -- -- 3 5 pF 6 ADC input pin capacitance 1 -- -- -- 5 pF CP2 6 ADC input pin capacitance 2 -- -- -- 0.8 pF RSW16 Internal resistance of analog source VREF range = 4.5 to 5.5 V -- -- 0.3 k VREF range = 3.15 to 3.6 V -- -- 875 CP1 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 30 NXP Semiconductors Analog Table 21. ADC conversion characteristics (for 12-bit) (continued) Symbol Parameter Conditions Min Typ1 Max Unit RAD6 Internal resistance of analog source -- -- -- 825 INL Integral non-linearity (precise channel) -- -2 -- 2 LSB INL Integral non-linearity (standard channel) -- -3 -- 3 LSB DNL Differential non-linearity -- -1 -- 1 LSB OFS Offset error -- -6 -- 6 LSB GNE Gain error -- -4 -- 4 LSB Max leakage (precision channel) 150 C -- -- 250 nA Max leakage (standard channel) 150 C -- -- 2500 nA Max leakage (standard channel) 105 C TA -- 5 250 nA ADC Analog Pad (pad going to one ADC) -5 -- 5 mA TUEprecision channels Total unadjusted error for precision Without current injection channels With current injection7 Max positive/negative injection -6 +/-4 6 LSB TUEstandard/extended Total unadjusted error for standard/ Without current injection extended channels channels With current injection7 -8 trecovery +/-5 +/-6 LSB 8 +/-8 STOP mode to Run mode recovery time LSB LSB <1 s 1. Active ADC input, VinA < [min(ADC_VrefH, ADC_ADV, VDD_HV_IOx)]. VDD_HV_IOx refers to I/O segment supply voltage. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions (VDD_HV_x = 3.3 V)' for required relation between IO_supply_A,B,C and ADC_Supply. 2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral clock based on register configuration in the ADC. 3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 5. Apart from tsample and tconv, few cycles are used up in ADC digital interface and hence the overall throughput from the ADC is lower. 6. See Figure 2. 7. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here Table 22. ADC conversion characteristics (for 10-bit) Symbol Parameter Conditions Min Typ1 Max Unit fCK ADC Clock frequency (depends on ADC configuration) (The duty cycle depends on AD_CK2 frequency.) -- 15.2 80 80 MHz Sampling frequency -- -- -- 1.00 MHz 80 MHz@ 100 ohm source impedance 275 -- -- ns fs tsample Sample time3 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 31 Analog Table 22. ADC conversion characteristics (for 10-bit) (continued) Conditions Min Typ1 Max Unit Conversion time4 80 MHz 550 -- -- ns Total Conversion time tsample + tconv (for standard channels) 80 MHz 1 -- -- s 1.5 -- -- Symbol tconv ttotal_conv Parameter Total Conversion time tsample + tconv (for extended channels) ADC input sampling capacitance -- -- 3 5 pF CP15 CS ADC input pin capacitance 1 -- -- -- 5 pF CP25 ADC input pin capacitance 2 -- -- -- 0.8 pF RSW15 Internal resistance of analog source VREF range = 4.5 to 5.5 V -- -- 0.3 k VREF range = 3.15 to 3.6 V -- -- 875 Internal resistance of analog source -- -- -- 825 5 RAD INL Integral non-linearity -- -2 -- 2 LSB DNL Differential non-linearity -- -1 -- 1 LSB OFS Offset error -- -4 -- 4 LSB GNE Gain error -- -4 -- 4 LSB 150 C -- -- 2500 nA -5 -- 5 mA -- 5 250 nA -4 +/-3 4 LSB ADC Analog Pad (pad going to one ADC) Max leakage (standard channel) Max positive/negative injection Max leakage (standard channel) TUEstandard/extended Total unadjusted error for standard channels channels trecovery 105 C TA Without current injection With current injection6 STOP mode to Run mode recovery time +/-4 LSB <1 s 1. Active ADC Input, VinA < [min(ADC_ADV, IO_Supply_A,B,C)]. Violation of this condition would lead to degradation of ADC performance. Please refer to Table: 'Absolute maximum ratings' to avoid damage. Refer to Table: 'Recommended operating conditions' for required relation between IO_supply_A, B, C and ADC_Supply. 2. The internally generated clock (known as AD_clk or ADCK) could be same as the peripheral clock or half of the peripheral clock based on register configuration in the ADC. 3. During the sample time the input capacitance CS can be charged/discharged by the external source. The internal resistance of the analog source must allow the capacitance to reach its final voltage level within tsample. After the end of the sample time tsample, changes of the analog input voltage have no effect on the conversion result. Values for the sample clock tsample depend on programming. 4. This parameter does not include the sample time tsample, but only the time for determining the digital result and the time to load the result register with the conversion result. 5. See Figure 2-1 6. Current injection condition for ADC channels is defined for an inactive ADC channel (on which conversion is NOT being performed), and this occurs when voltage on the ADC pin exceeds the I/O supply or ground. However, absolute maximum voltage spec on pad input (VINA, see Table: Absolute maximum ratings) must be honored to meet TUE spec quoted here MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 32 NXP Semiconductors Analog 6.1.2 Analog Comparator (CMP) electrical specifications Table 23. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit IDDHS Supply current, High-speed mode (EN=1, PMODE=1) -- -- 250 A IDDLS Supply current, low-speed mode (EN=1, PMODE=0) -- 5 11 A VAIN Analog input voltage VSS -- VIN1_CMP_RE V F VAIO VH Analog input offset voltage 1 -47 -- 47 mV -- 1 25 mV -- 20 50 mV -- 40 70 mV -- 60 105 mV -- -- 250 ns -- 5 21 s Analog comparator initialization delay, High speed mode4 -- 4 s Analog comparator initialization delay, Low speed mode 4 -- 100 s 3.3V Reference Voltage -- 6 9 A 5V Reference Voltage -- 10 16 A Analog comparator hysteresis 2 * CR0[HYSTCTR] = 00 * CR0[HYSTCTR] = 01 * CR0[HYSTCTR] = 10 * CR0[HYSTCTR] = 11 tDHS tDLS IDAC6b Propagation Delay, High Speed Mode (Full Swing) 1, 3 Propagation Delay, Low power Mode (Full Swing) 1, 3 6-bit DAC current adder (when enabled) INL 6-bit DAC integral non-linearity -0.5 -- 0.5 LSB5 DNL 6-bit DAC differential non-linearity -0.8 -- 0.8 LSB 1. 2. 3. 4. Measured with hysteresis mode of 00 Typical hysteresis is measured with input voltage range limited to 0.6 to VDD_HV_A-0.6V Full swing = VIH, VIL Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 5. 1 LSB = Vreference/64 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 33 Clocks and PLL interfaces modules 6.2 Clocks and PLL interfaces modules 6.2.1 Main oscillator electrical characteristics This device provides a driver for oscillator in pierce configuration with amplitude control. Controlling the amplitude allows a more sinusoidal oscillation, reducing in this way the EMI. Other benefits arises by reducing the power consumption. This Loop Controlled Pierce (LCP mode) requires good practices to reduce the stray capacitance of traces between crystal and MCU. An operation in Full Swing Pierce (FSP mode), implemented by an inverter is also available in case of parasitic capacitances and cannot be reduced by using crystal with high equivalent series resistance. For this mode, a special care needs to be taken regarding the serial resistance used to avoid the crystal overdrive. Other two modes called External (EXT Wave) and disable (OFF mode) are provided. For EXT Wave, the drive is disabled and an external source of clock within CMOS level based in analog oscillator supply can be used. When OFF, EXTAL is pulled down by 240 Kohms resistor and the feedback resistor remains active connecting XTAL through EXTAL by 1M resistor. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 34 NXP Semiconductors Clocks and PLL interfaces modules Figure 7. Oscillator connections scheme Table 24. Main oscillator electrical characteristics Symbol Parameter Mode fXOSCHS Oscillator frequency gmXOSCHS Driver LCP Transconduct FSP ance VXOSCHS TXOSCHSSU Oscillation Amplitude Startup time Conditions FSP/LCP LCP1, 2 FSP/LCP1 Oscillator FSP Analog Circuit supply current Min Typ 8 Max 40 23 Unit MHz mA/V 33 8 MHz 1.0 16 MHz 1.0 40 MHz 0.8 8 MHz 2 16 MHz 1 40 MHz 0.5 8 MHz 2.2 16 MHz 2.2 VPP ms mA Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 35 Clocks and PLL interfaces modules Table 24. Main oscillator electrical characteristics (continued) Symbol Parameter Mode LCP Conditions Min Typ 40 MHz 3.2 8 MHz 141 16 MHz 252 40 MHz 518 VIH Input High EXT Wave level CMOS Schmitt trigger Oscillator supply=3.3 VIL Input low level EXT Wave CMOS Schmitt trigger Oscillator supply=3.3 Max Unit uA 1.95 V 1.25 V 1. Values are very dependent on crystal or resonator used and parasitic capacitance observed in the board. 2. Typ value for oscillator supply 3.3 V@27 C 6.2.2 32 kHz Oscillator electrical specifications Table 25. 32 kHz oscillator electrical specifications Symbol Parameter fosc_lo Oscillator crystal or resonator frequency tcst Crystal Start-up Time1, 2 Condition Min Typ 32 Max Unit 40 KHz 2 s 1. This parameter is characterized before qualification rather than 100% tested. 2. Proper PC board layout procedures must be followed to achieve specifications. 6.2.3 16 MHz RC Oscillator electrical specifications Table 26. 16 MHz RC Oscillator electrical specifications Symbol FTarget Parameter Conditions Value Unit Min Typ Max IRC target frequency -- -- 16 -- MHz IRC frequency variation after trimming -- -5 -- 5 % Tstartup Startup time -- -- 1.5 us TSTJIT Cycle to cycle jitter -- -- 1.5 % TLTJIT Long term jitter -- -- 0.2 % PTA NOTE The above start up time of 1 us is equivalent to 16 cycles of 16 MHz. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 36 NXP Semiconductors Clocks and PLL interfaces modules 6.2.4 128 KHz Internal RC oscillator Electrical specifications Table 27. 128 KHz Internal RC oscillator electrical specifications Symbol Foscu1 Parameter Oscillator frequency Condition Calibrated Min Typ 128 Unit 136.5 KHz Temperature dependence 600 ppm/C Supply dependence 18 %/V Clock running 2.75 A Clock stopped 200 nA Supply current 119 Max 1. Vdd=1.2 V, 1.32V, Ta=-40 C, 125 C 6.2.5 PLL electrical specifications Table 28. PLL electrical specifications Parameter Min Typ Max Unit Input Frequency 8 40 MHz VCO Frequency Range 600 1280 MHz Duty Cycle at pllclkout 48% 52% Period Jitter See Table 29 TIE See Table 29 Modulation Depth (Center Spread) +/- 0.25% Comments This specification is guaranteed at PLL IP boundary ps NON SSCG mode at 960 M Integrated over 1MHz offset not valid in SSCG mode +/- 3.0% Modulation Frequency 32 KHz Lock Time 60 s Calibration mode Table 29. Jitter calculation Type of jitter Jitter due to Supply Noise (ps) JSN1 Jitter due to Fractional Mode (ps) JSDM2 Jitter due to Fractional Mode JSSCG (ps) 3 1 Sigma Random Jitter JRJ (ps) 4 Total Period Jitter (ps) 0.1% of pllclkout1,2 +/-(JSN+JSDM+JSSCG+N[4] xJRJ) Long Term Jitter (Integer Mode) 40 +/-(N x JRJ) Long Term jitter (Fractional Mode) 100 +/-(N x JRJ) Period Jitter 60 ps 3% of pllclkout1,2 Modulation depth 1. This jitter component is due to self noise generated due to bond wire inductances on different PLL supplies. The jitter value is valid for inductor value of 5nH or less each on VDD_LV and VSS_LV. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 37 Memory interfaces 2. This jitter component is added when the PLL is working in the fractional mode. 3. This jitter component is added when the PLL is working in the Spread Spectrum Mode. Else it is 0. 4. The value of N is dependent on the accuracy requirement of the application. See Percentage of sample exceeding specified value of jitter table Table 30. Percentage of sample exceeding specified value of jitter N Percentage of samples exceeding specified value of jitter (%) 1 31.73 2 4.55 3 0.27 4 6.30 x 1e-03 5 5.63 x 1e-05 6 2.00 x 1e-07 7 2.82 x 1e-10 6.3 Memory interfaces 6.3.1 Flash memory program and erase specifications NOTE All timing, voltage, and current numbers specified in this section are defined for a single embedded flash memory within an SoC, and represent average currents for given supplies and operations. Table 31 shows the estimated Program/Erase times. Table 31. Flash memory program and erase specifications Symbol Characteristic1 Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20C TA 30C -40C TJ 150C -40C TJ 150C Unit Lifetime Max6 1,000 cycles 250,000 cycles tdwpgm Doubleword (64 bits) program time 43 100 150 55 500 s tppgm Page (256 bits) program time 73 200 300 108 500 s tqppgm Quad-page (1024 bits) program time 268 800 1,200 396 2,000 s t16kers 16 KB Block erase time 168 290 320 250 1,000 ms t16kpgm 16 KB Block program time 34 45 50 40 1,000 ms Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 38 NXP Semiconductors Memory interfaces Table 31. Flash memory program and erase specifications (continued) Characteristic1 Symbol Typ2 Factory Programming3, 4 Field Update Initial Max Initial Max, Full Temp Typical End of Life5 20C TA 30C -40C TJ 150C -40C TJ 150C Unit Lifetime Max6 1,000 cycles 250,000 cycles t32kers 32 KB Block erase time 217 360 390 310 1,200 ms t32kpgm 32 KB Block program time 69 100 110 90 1,200 ms t64kers 64 KB Block erase time 315 490 590 420 1,600 ms t64kpgm 64 KB Block program time 138 180 210 170 1,600 ms t256kers 256 KB Block erase time 884 1,520 2,030 1,080 4,000 -- ms t256kpgm 256 KB Block program time 552 720 880 650 4,000 -- ms 1. Program times are actual hardware programming times and do not include software overhead. Block program times assume quad-page programming. 2. Typical program and erase times represent the median performance and assume nominal supply values and operation at 25 C. Typical program and erase times may be used for throughput calculations. 3. Conditions: 150 cycles, nominal voltage. 4. Plant Programing times provide guidance for timeout limits used in the factory. 5. Typical End of Life program and erase times represent the median performance and assume nominal supply values. Typical End of Life program and erase values may be used for throughput calculations. 6. Conditions: -40C TJ 150C, full spec voltage. 6.3.2 Flash memory Array Integrity and Margin Read specifications Table 32. Flash memory Array Integrity and Margin Read specifications Symbol Characteristic Min Typical Max1 Units tai16kseq Array Integrity time for sequential sequence on 16 KB block. -- -- 512 x Tperiod x Nread -- tai32kseq Array Integrity time for sequential sequence on 32 KB block. -- -- 1024 x Tperiod x Nread -- tai64kseq Array Integrity time for sequential sequence on 64 KB block. -- -- 2048 x Tperiod x Nread -- tai256kseq Array Integrity time for sequential sequence on 256 KB block. -- -- 8192 x Tperiod x Nread -- tmr16kseq Margin Read time for sequential sequence on 16 KB block. 73.81 -- 110.7 s tmr32kseq Margin Read time for sequential sequence on 32 KB block. 128.43 -- 192.6 s tmr64kseq Margin Read time for sequential sequence on 64 KB block. 237.65 -- 356.5 s tmr256kseq Margin Read time for sequential sequence on 256 KB block. 893.01 -- 1,339.5 s 2 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 39 Memory interfaces 1. Array Integrity times need to be calculated and is dependent on system frequency and number of clocks per read. The equation presented require Tperiod (which is the unit accurate period, thus for 200 MHz, Tperiod would equal 5e-9) and Nread (which is the number of clocks required for read, including pipeline contribution. Thus for a read setup that requires 6 clocks to read with no pipeline, Nread would equal 6. For a read setup that requires 6 clocks to read, and has the address pipeline set to 2, Nread would equal 4 (or 6 - 2).) 2. The units for Array Integrity are determined by the period of the system clock. If unit accurate period is used in the equation, the results of the equation are also unit accurate. 6.3.3 Flash memory module life specifications Table 33. Flash memory module life specifications Symbol Array P/E cycles Data retention Characteristic Conditions Min Typical Units Number of program/erase cycles per block for 16 KB, 32 KB and 64 KB blocks.1 -- 250,000 -- P/E cycles Number of program/erase cycles per block for 256 KB blocks.2 -- 1,000 250,000 P/E cycles Minimum data retention. Blocks with 0 - 1,000 P/E cycles. 50 -- Years Blocks with 100,000 P/E cycles. 20 -- Years Blocks with 250,000 P/E cycles. 10 -- Years 1. Program and erase supported across standard temperature specs. 2. Program and erase supported across standard temperature specs. 6.3.4 Data retention vs program/erase cycles Graphically, Data Retention versus Program/Erase Cycles can be represented by the following figure. The spec window represents qualified limits. The extrapolated dotted line demonstrates technology capability, however is beyond the qualification limits. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 40 NXP Semiconductors Memory interfaces 6.3.5 Flash memory AC timing specifications Table 34. Flash memory AC timing specifications Symbol Characteristic Min Typical Max Units Time from setting the MCR-PSUS bit until MCR-DONE bit is set to a 1. -- 9.4 11.5 s plus four system clock periods plus four system clock periods Time from setting the MCR-ESUS bit until MCR-DONE bit is set to a 1. -- 16 20.8 plus four system clock periods plus four system clock periods Time from clearing the MCR-ESUS or PSUS bit with EHV = 1 until DONE goes low. -- -- 100 ns tdone Time from 0 to 1 transition on the MCR-EHV bit initiating a program/erase until the MCR-DONE bit is cleared. -- -- 5 ns tdones Time from 1 to 0 transition on the MCR-EHV bit aborting a program/erase until the MCR-DONE bit is set to a 1. -- 16 20.8 s plus four system clock periods plus four system clock periods Time to recover once exiting low power mode. 16 -- 45 tpsus tesus tres tdrcv s s Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 41 Memory interfaces Table 34. Flash memory AC timing specifications (continued) Symbol Characteristic Min Typical plus seven system clock periods. Max Units plus seven system clock periods taistart Time from 0 to 1 transition of UT0-AIE initiating a Margin Read or Array Integrity until the UT0-AID bit is cleared. This time also applies to the resuming from a suspend or breakpoint by clearing AISUS or clearing NAIBP -- -- 5 ns taistop Time from 1 to 0 transition of UT0-AIE initiating an Array Integrity abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Array Integrity suspend request. -- -- 80 ns Time from 1 to 0 transition of UT0-AIE initiating a Margin Read abort until the UT0-AID bit is set. This time also applies to the UT0-AISUS to UT0-AID setting in the event of a Margin Read suspend request. 10.36 tmrstop plus fifteen system clock periods plus four system clock periods -- 20.42 s plus four system clock periods 6.3.6 Flash read wait state and address pipeline control settings The following table describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsic flash access times of the flash module controller array at 125 C. Table 35. Flash Read Wait State and Address Pipeline Control Combinations Flash frequency RWSC setting APC setting 0 MHz < fFlash <= 33 MHz 0 0 33 MHz < fFlash <= 100 MHz 2 1 100 MHz < fFlash <= 133 MHz 3 1 133 MHz < fFlash <= 160 MHz 4 1 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 42 NXP Semiconductors Communication interfaces 6.4 Communication interfaces 6.4.1 DSPI timing Table 36. DSPI electrical specifications No 1 Symbol tSCK Parameter DSPI cycle time Conditions High Speed Mode1 low Speed mode Min Min Max Unit Max Master 25 -- 50 -- Slave (MTFE = 0) 40 -- 60 -- ns 2 tCSC PCS to SCK delay -- 16 -- -- -- ns 3 tASC After SCK delay -- 16 -- -- -- ns 4 tSDC SCK duty cycle -- tSCK/2 - 10 tSCK/2 + 10 -- -- ns 5 tA Slave access time SS active to SOUT valid -- 40 -- -- ns 6 tDIS Slave SOUT disable time SS inactive to SOUT High-Z or invalid -- 10 -- -- ns 7 tPCSC PCSx to PCSS time -- 13 -- -- -- ns 8 tPASC PCSS to PCSx time -- 13 -- -- -- ns 9 tSUI Data setup time for inputs Master (MTFE = 0) NA -- 20 -- ns 10 11 12 tHI tSUO tHO Data hold time for inputs Data valid (after SCK edge) Data hold time for outputs Slave 2 -- 2 -- Master (MTFE = 1, CPHA = 0) 15 -- 82 -- Master (MTFE = 1, CPHA = 1) 15 -- 20 -- Master (MTFE = 0) NA -- -5 -- Slave 4 -- 4 -- Master (MTFE = 1, CPHA = 0) 0 -- 112 -- Master (MTFE = 1, CPHA = 1) 0 -- -5 -- Master (MTFE = 0) -- NA -- 4 Slave -- 15 -- 23 Master (MTFE = 1, CPHA = 0) -- 4 -- 162 Master (MTFE = 1, CPHA = 1) -- 4 -- 4 Master (MTFE = 0) NA -- -2 -- ns ns ns Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 43 Communication interfaces Table 36. DSPI electrical specifications (continued) No Symbol High Speed Mode1 low Speed mode Min Max Min Max Slave 4 -- 6 -- Master (MTFE = 1, CPHA = 0) -2 -- 102 -- Master (MTFE = 1, CPHA = 1) -2 -- -2 -- Parameter Conditions Unit 1. Only one {SIN,SOUT and SCK} group per DSPI/SPI will support high frequency mode. See Table 3. 2. SMPL_PTR should be set to 1 NOTE Restriction For High Speed modes * DSPI2, DSPI3, SPI1 and SPI2 will support 40MHz Master mode SCK * DSPI2, DSPI3, SPI1 and SPI2 will support 25MHz Slave SCK frequency * Only one {SIN,SOUT and SCK} group per DSPI/SPI will support high frequency mode. See Table 38. * For Master mode MTFE will be 1 for high speed mode * For high speed slaves, their master have to be in MTFE=1 mode or should be able to support 15ns tSUO delay NOTE For numbers shown in the following figures, see Table 36 Table 37. Continuous SCK timing Spec Characteristics Pad Drive/Load Value Min Max 100 ns - tSCK SCK cycle timing strong/50 pF - PCS valid after SCK strong/50 pF - 15 ns - PCS valid after SCK strong/50 pF -4 ns - Table 38. DSPI high speed mode I/Os DSPI High speed SCK High speed SIN High speed SOUT DSPI2 GPIO[78] GPIO[76] GPIO[77] DSPI3 GPIO[100] GPIO[101] GPIO[98] SPI1 GPIO[173] GPIO[175] GPIO[176] SPI2 GPIO[79] GPIO[110] GPIO[111] MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 44 NXP Semiconductors Communication interfaces 2 3 PCSx 1 4 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN 10 First Data Last Data Data 12 SOUT First Data 11 Data Last Data Figure 8. DSPI classic SPI timing -- master, CPHA = 0 PCSx SCK Output (CPOL=0) 10 SCK Output (CPOL=1) 9 SIN Data First Data 12 SOUT First Data Last Data 11 Data Last Data Figure 9. DSPI classic SPI timing -- master, CPHA = 1 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 45 Communication interfaces 3 2 SS 1 4 SCK Input (CPOL=0) 4 SCK Input (CPOL=1) 5 First Data SOUT 9 6 Data Last Data Data Last Data 10 First Data SIN 11 12 Figure 10. DSPI classic SPI timing -- slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 12 SOUT First Data 9 SIN Data Last Data Data Last Data 6 10 First Data Figure 11. DSPI classic SPI timing -- slave, CPHA = 1 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 46 NXP Semiconductors Communication interfaces 3 PCSx 4 1 2 SCK Output (CPOL=0) 4 SCK Output (CPOL=1) 9 SIN 10 First Data Last Data Data 12 SOUT 11 First Data Last Data Data Figure 12. DSPI modified transfer format timing -- master, CPHA = 0 PCSx SCK Output (CPOL=0) SCK Output (CPOL=1) 10 9 SIN First Data Data 12 SOUT First Data Data Last Data 11 Last Data Figure 13. DSPI modified transfer format timing -- master, CPHA = 1 MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 47 Communication interfaces 3 2 SS 1 SCK Input (CPOL=0) 4 4 SCK Input (CPOL=1) 12 11 5 First Data SOUT Data Last Data 10 9 Data First Data SIN 6 Last Data Figure 14. DSPI modified transfer format timing - slave, CPHA = 0 SS SCK Input (CPOL=0) SCK Input (CPOL=1) 11 5 6 12 First Data SOUT 9 Last Data Data Last Data 10 First Data SIN Data Figure 15. DSPI modified transfer format timing -- slave, CPHA = 1 7 8 PCSS PCSx Figure 16. DSPI PCS strobe (PCSS) timing MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 48 NXP Semiconductors FlexRay electrical specifications 6.4.2 FlexRay electrical specifications 6.4.2.1 FlexRay timing This section provides the FlexRay Interface timing characteristics for the input and output signals. It should be noted that these are recommended numbers as per the FlexRay EPL v3.0 specification, and subject to change per the final timing analysis of the device. 6.4.2.2 TxEN TxEN 80 % 20 % dCCTxENFALL dCCTxENRISE Figure 17. TxEN signal Table 39. TxEN output characteristics1 Name Description Min Max Unit dCCTxENRISE25 Rise time of TxEN signal at CC -- 9 ns dCCTxENFALL25 Fall time of TxEN signal at CC -- 9 ns dCCTxEN01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxEN10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 C / 150 C, TxEN pin load maximum 25 pF MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 49 FlexRay electrical specifications PE_Clk TxEN dCCTxEN10 dCCTxEN01 Figure 18. TxEN signal propagation delays 6.4.2.3 TxD TxD dCCTxD50% 80 % 50 % 20 % dCCTxDRISE dCCTxDFALL Figure 19. TxD Signal Table 40. TxD output characteristics Name Description1 Min Max Unit dCCTxAsym Asymmetry of sending CC @ 25 pF load (=dCCTxD50% - 100 ns) -2.45 2.45 ns -- 92 ns dCCTxDRISE25+dCCTx Sum of Rise and Fall time of TxD signal at the output DFALL25 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 50 NXP Semiconductors FlexRay electrical specifications Table 40. TxD output characteristics (continued) Description1 Name Min Max Unit dCCTxD01 Sum of delay between Clk to Q of the last FF and the final output buffer, rising edge -- 25 ns dCCTxD10 Sum of delay between Clk to Q of the last FF and the final output buffer, falling edge -- 25 ns 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 C / 150 C, TxD pin load maximum 25 pF. 2. For 3.3 V 10% operation, this specification is 10 ns. PE_Clk* TxD dCCTxD10 dCCTxD01 *FlexRay Protocol Engine Clock Figure 20. TxD Signal propagation delays 6.4.2.4 RxD Table 41. RxD input characteristic Name Description1 Min Max Unit C_CCRxD Input capacitance on RxD pin -- 7 pF uCCLogic_1 Threshold for detecting logic high 35 70 % uCCLogic_0 Threshold for detecting logic low 30 65 % dCCRxD01 Sum of delay from actual input to the D input of the first FF, rising edge -- 10 ns dCCRxD10 Sum of delay from actual input to the D input of the first FF, falling edge -- 10 ns MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 51 FlexRay electrical specifications 1. All parameters specified for VDD_HV_IOx = 3.3 V -5%, +10%, TJ = -40 oC / 150 oC. 6.4.3 Ethernet switching specifications The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. 6.4.3.1 MII signal switching specifications The following timing specs meet the requirements for MII style interfaces for a range of transceiver devices. Table 42. MII signal switching specifications Symbol -- MII1 Description RXCLK frequency RXCLK pulse width high Min. Max. Unit -- 25 MHz 35% 65% RXCLK period MII2 RXCLK pulse width low 35% 65% RXCLK period MII3 RXD[3:0], RXDV, RXER to RXCLK setup MII4 RXCLK to RXD[3:0], RXDV, RXER hold 5 -- ns TXCLK frequency -- 25 MHz 35% 65% TXCLK -- MII5 5 TXCLK pulse width high -- ns period MII6 TXCLK pulse width low 35% 65% TXCLK period MII7 TXCLK to TXD[3:0], TXEN, TXER invalid 2 -- ns MII8 TXCLK to TXD[3:0], TXEN, TXER valid -- 25 ns MII6 MII5 TXCLK (input) MII8 MII7 TXD[n:0] Valid data TXEN Valid data TXER Valid data Figure 21. RMII/MII transmit signal timing diagram MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 52 NXP Semiconductors FlexRay electrical specifications MII2 MII1 MII3 MII4 RXCLK (input) RXD[n:0] Valid data RXDV Valid data RXER Valid data Figure 22. RMII/MII receive signal timing diagram 6.4.3.2 RMII signal switching specifications The following timing specs meet the requirements for RMII style interfaces for a range of transceiver devices. Table 43. RMII signal switching specifications Num -- Description EXTAL frequency (RMII input clock RMII_CLK) Min. Max. Unit -- 50 MHz RMII1 RMII_CLK pulse width high 35% 65% RMII_CLK period RMII2 RMII_CLK pulse width low 35% 65% RMII_CLK period RMII3 RXD[1:0], CRS_DV, RXER to RMII_CLK setup 4 -- ns RMII4 RMII_CLK to RXD[1:0], CRS_DV, RXER hold 2 -- ns RMII7 RMII_CLK to TXD[1:0], TXEN invalid 4 -- ns RMII8 RMII_CLK to TXD[1:0], TXEN valid -- 15 ns 6.4.4 SAI electrical specifications All timing requirements are specified relative to the clock period or to the minimum allowed clock period of a device Table 44. Master mode SAI Timing no S1 Parameter Value Unit Min Max Operating Voltage 2.7 3.6 V SAI_MCLK cycle time 40 - ns Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 53 FlexRay electrical specifications Table 44. Master mode SAI Timing (continued) no Parameter Value Unit Min Max 45% 55% MCLK period 80 - BCLK period 45% 55% ns S2 SAI_MCLK pulse width high/low S3 SAI_BCLK cycle time S4 SAI_BCLK pulse width high/low S5 SAI_BCLK to SAI_FS output valid - 15 ns S6 SAI_BCLK to SAI_FS output invalid 0 - ns S7 SAI_BCLK to SAI_TXD valid - 15 ns S8 SAI_BCLK to SAI_TXD invalid 0 - ns S9 SAI_RXD/SAI_FS input setup before SAI_BCLK 28 - ns S10 SAI_RXD/SAI_FS input hold after SAI_BCLK 0 - ns Figure 23. Master mode SAI Timing Table 45. Slave mode SAI Timing No Parameter Value Unit Min Max Operating Voltage 2.7 3.6 V S11 SAI_BCLK cycle time (input) 80 - ns S12 SAI_BCLK pulse width high/low (input) 45% 55% BCLK period S13 SAI_FS input setup before SAI_BCLK 10 - ns S14 SAI_FS input hold after SAI_BCLK 2 - ns Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 54 NXP Semiconductors Debug specifications Table 45. Slave mode SAI Timing (continued) No Parameter Value Unit Min Max S15 SAI_BCLK to SAI_TXD/SAI_FS output valid - 28 ns S16 SAI_BCLK to SAI_TXD/SAI_FS output invalid 0 - ns S17 SAI_RXD setup before SAI_BCLK 10 - ns S18 SAI_RXD hold after SAI_BCLK 2 - ns Figure 24. Slave mode SAI Timing 6.5 Debug specifications 6.5.1 JTAG interface timing Table 46. JTAG pin AC electrical characteristics 1 # Symbol Characteristic 2 Min Max Unit 62.5 -- ns 60 % 1 tJCYC TCK Cycle Time 2 tJDC TCK Clock Pulse Width 40 3 tTCKRISE TCK Rise and Fall Times (40% - 70%) -- 3 ns 4 tTMSS, tTDIS TMS, TDI Data Setup Time 5 -- ns 5 tTMSH, tTDIH TMS, TDI Data Hold Time 5 -- ns ns 6 tTDOV TCK Low to TDO Data Valid -- 203 7 tTDOI TCK Low to TDO Data Invalid 0 -- ns 8 tTDOHZ TCK Low to TDO High Impedance -- 15 ns -- 6004 ns 11 tBSDV TCK Falling Edge to Output Valid Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 55 Debug specifications Table 46. JTAG pin AC electrical characteristics 1 (continued) # Symbol Characteristic Min Max Unit 12 tBSDVZ TCK Falling Edge to Output Valid out of High Impedance -- 600 ns 13 tBSDHZ TCK Falling Edge to Output High Impedance -- 600 ns 14 tBSDST Boundary Scan Input Valid to TCK Rising Edge 15 -- ns 15 tBSDHT TCK Rising Edge to Boundary Scan Input Invalid 15 -- ns 1. These specifications apply to JTAG boundary scan only. 2. This timing applies to TDI, TDO, TMS pins, however, actual frequency is limited by pad type for EXTEST instructions. Refer to pad specification for allowed transition frequency 3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay. 4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay. TCK 2 3 2 1 3 Figure 25. JTAG test clock input timing MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 56 NXP Semiconductors Debug specifications TCK 4 5 TMS, TDI 6 7 8 TDO Figure 26. JTAG test access port timing MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 57 Debug specifications TCK 11 13 Output Signals 12 Output Signals 14 15 Input Signals Figure 27. JTAG boundary scan timing 6.5.2 Nexus timing Table 47. Nexus debug port timing 1 No. Symbol Parameter 1 tMCYC MCKO Cycle Time 2 tMDC MCKO Duty Cycle MCKO Low to MDO, MSEO, EVTO Data Valid2 Condition s Min Max Unit -- 15.6 -- ns -- 40 60 % -- -0.1 0.25 tMCYC 3 tMDOV 4 tEVTIPW EVTI Pulse Width -- 4 -- tTCYC 5 tEVTOPW EVTO Pulse Width -- 1 -- tMCYC -- 62.5 -- ns Time3 6 tTCYC TCK Cycle 7 tTDC TCK Duty Cycle -- 40 60 % 8 tNTDIS, tNTMSS TDI, TMS Data Setup Time -- 8 -- ns Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 58 NXP Semiconductors Debug specifications Table 47. Nexus debug port timing 1 (continued) No. Symbol Parameter Condition s Min Max Unit 9 tNTDIH, tNTMSH TDI, TMS Data Hold Time -- 5 -- ns 10 tJOV TCK Low to TDO/RDY Data Valid -- 0 25 ns 1. JTAG specifications in this table apply when used for debug functionality. All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. 2. For all Nexus modes except DDR mode, MDO, MSEO, and EVTO data is held valid until next MCKO low cycle. 3. The system clock frequency needs to be four times faster than the TCK frequency. 1 2 MCKO 3 MDO MSEO EVTO Output Data Valid 5 Figure 28. Nexus output timing EVTI 4 Figure 29. Nexus EVTI Input Pulse Width MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 59 Debug specifications 6 7 TCK 8 9 TMS, TDI 10 TDO/RDY Figure 30. Nexus TDI, TMS, TDO timing 6.5.3 WKPU/NMI timing Table 48. WKPU/NMI glitch filter No. Symbol Parameter Min Typ Max Unit 1 WFNMI NMI pulse width that is rejected -- -- 20 ns 2 WNFNMID NMI pulse width that is passed 400 -- -- ns MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 60 NXP Semiconductors Thermal attributes 6.5.4 External interrupt timing (IRQ pin) Table 49. External interrupt timing specifications No. Symbol Parameter Conditions Min Max Unit 1 tIPWL IRQ pulse width low -- 3 -- tCYC 2 tIPWH IRQ pulse width high -- 3 -- tCYC 3 tICYC IRQ edge to edge time -- 6 -- tCYC These values applies when IRQ pins are configured for rising edge or falling edge events, but not both. IRQ 1 2 3 Figure 31. External interrupt timing 7 Thermal attributes 7.1 Thermal attributes Board type Symbol Description 176LQFP Unit Notes Single-layer (1s) RJA Thermal 50.7 resistance, junction to ambient (natural convection) C/W 1, 2 Four-layer (2s2p) RJA Thermal 24.2 resistance, junction to ambient (natural convection) C/W 1, 2, 3 Single-layer (1s) RJMA Thermal 38.1 resistance, junction to ambient (200 ft./ min. air speed) C/W 1, 3 Four-layer (2s2p) RJMA Thermal 17.8 resistance, junction C/W 1, 3 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 61 Thermal attributes Board type Symbol Description 176LQFP Unit Notes to ambient (200 ft./ min. air speed) -- RJB Thermal 10.9 resistance, junction to board C/W 4 -- RJC Thermal 8.4 resistance, junction to case C/W 5 -- JT Thermal 0.5 resistance, junction to package top C/W 6 -- JB Thermal 0.3 characterization parameter, junction to package bottom C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal. 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal resistance between the die and the solder pad on the bottom of the package based on simulation without any interface resistance. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Board type Symbol Description 324 MAPBGA Unit Notes Single-layer (1s) RJA Thermal 31.0 resistance, junction to ambient (natural convection) C/W 1, 2 Four-layer (2s2p) RJA Thermal 24.3 resistance, junction to ambient (natural convection) C/W 1,2,3 Single-layer (1s) RJMA Thermal 23.5 resistance, junction to ambient (200 ft./ min. air speed) C/W 1, 3 Four-layer (2s2p) RJMA Thermal 20.1 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 -- RJB Thermal 16.8 resistance, junction to board C/W 4 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 62 NXP Semiconductors Thermal attributes Board type Symbol Description 324 MAPBGA Unit Notes -- RJC Thermal 7.4 resistance, junction to case C/W 5 -- JT Thermal 0.2 characterization parameter, junction to package top natural convection C/W 6 -- JB Thermal 7.3 characterization parameter, junction to package bottom natural convection C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification. 3. Per JEDEC JESD51-6 with the board horizontal 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Board type Symbol Description 256 MAPBGA Unit Notes Single-layer (1s) RJA Thermal 42.6 resistance, junction to ambient (natural convection) C/W 1, 2 Four-layer (2s2p) RJA Thermal 26.0 resistance, junction to ambient (natural convection) C/W 1,2,3 Single-layer (1s) RJMA Thermal 31.0 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 Four-layer (2s2p) RJMA Thermal 21.3 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 -- RJB Thermal 12.8 resistance, junction to board C/W 4 -- RJC Thermal 7.9 resistance, junction to case C/W 5 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 63 Thermal attributes Board type Symbol Description 256 MAPBGA Unit Notes -- JT Thermal 0.2 characterization parameter, junction to package top outside center (natural convection) C/W 6 -- RJB_CSB Thermal 9.0 characterization parameter, junction to package bottom outside center (natural convection) C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. Board type Symbol Description 100 MAPBGA Unit Notes Single-layer (1s) RJA Thermal 50.9 resistance, junction to ambient (natural convection) C/W 1,2 Four-layer (2s2p) RJA Thermal 27.0 resistance, junction to ambient (natural convection) C/W 1,2,3 Single-layer (1s) RJMA Thermal 38.0 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 Four-layer (2s2p) RJMA Thermal 22.2 resistance, junction to ambient (200 ft./ min. air speed) C/W 1,3 -- RJB Thermal 10.8 resistance, junction to board C/W 4 Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 64 NXP Semiconductors Dimensions Board type Symbol Description 100 MAPBGA Unit Notes -- RJC Thermal 8.2 resistance, junction to case C/W 5 -- JT Thermal 0.2 characterization parameter, junction to package top outside center (natural convection) C/W 6 -- JB Thermal 7.8 characterization parameter, junction to package bottom outside center (natural convection) C/W 7 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal. 3. Per JEDEC JESD51-6 with the board horizontal 4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board near the package. 5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1). 6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT. 7. Thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per JEDEC JESD51-12. When Greek letters are not available, the thermal characterization parameter is written as Psi-JB. 8 Dimensions 8.1 Obtaining package dimensions Package dimensions are provided in package drawing. To find a package drawing, go to www.nxp.com and perform a keyword search for the drawing's document number: Package NXP Document Number 100 MAPBGA 98ASA00802D 176-pin LQFP-EP 98ASA00698D 256 MAPBGA 98ASA00346D 324 MAPBGA 98ASA10582D MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 65 Pinouts 9 Pinouts 9.1 Package pinouts and signal descriptions For package pinouts and signal descriptions, refer to the Reference Manual. 10 Reset sequence 10.1 Reset sequence This section describes different reset sequences and details the duration for which the device remains in reset condition in each of those conditions. 10.1.1 Reset sequence duration Table 50 specifies the reset sequence duration for the five different reset sequences described in Reset sequence description. Table 50. RESET sequences No. Symbol Parameter TReset Unit Min Typ 1 Max 1 TDRB Destructive Reset Sequence, BIST enabled 6.2 7.3 - ms 2 TDR Destructive Reset Sequence, BIST disabled 110 182 - us 3 TERLB External Reset Sequence Long, Unsecure Boot 6.2 7.3 - ms 4 TFRL Functional Reset Sequence Long, Unsecure Boot 110 182 - us 5 TFRS Functional Reset Sequence Short, Unsecure Boot 7 9 - us 1. The Typ value is applicable only if the reset sequence duration is not prolonged by an extended assertion of RESET_B by an external reset generator. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 66 NXP Semiconductors Reset sequence 10.1.2 BAF execution duration Following table specifies the typical BAF execution time in case BAF boot header is present at first location (Typical) and last location (worst case). Total Boot time is the sum of reset sequence duration and BAF execution time. Table 51. BAF execution duration BAF execution duration Min Typ Max Unit BAF execution time (boot header at first location) -- 200 -- s BAF execution time (boot header at last location) -- -- 320 s 10.1.3 Reset sequence description The figures in this section show the internal states of the device during the five different reset sequences. The dotted lines in the figures indicate the starting point and the end point for which the duration is specified in . With the beginning of DRUN mode, the first instruction is fetched and executed. At this point, application execution starts and the internal reset sequence is finished. The following figures show the internal states of the device during the execution of the reset sequence and the possible states of the RESET_B signal pin. NOTE RESET_B is a bidirectional pin. The voltage level on this pin can either be driven low by an external reset generator or by the device internal reset circuitry. A high level on this pin can only be generated by an external pullup resistor which is strong enough to overdrive the weak internal pulldown resistor. The rising edge on RESET_B in the following figures indicates the time when the device stops driving it low. The reset sequence durations given in are applicable only if the internal reset sequence is not prolonged by an external reset generator keeping RESET_B asserted low beyond the last Phase3. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 67 Reset sequence Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE0 PHASE1,2 PHASE3 BIST Device Config Flash Init Establish IRC and PWR Self Test Setup PHASE1,2 Flash Init MBIST PHASE3 Device Config DRUN Application Execution TDRB, min < TRESET < TDRB, max Figure 32. Destructive reset sequence, BIST enabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE0 PHASE1,2 Establish IRC and PWR Flash Init PHASE3 DRUN BAF+ Application Execution Device Config TDR, min < TRESET < TDR, max Figure 33. Destructive reset sequence, BIST disabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE1,2 Flash Init PHASE3 Device Config BIST Self Test Setup PHASE1,2 PHASE3 Device Config Flash Init MBIST DRUN Application Execution TERLB, min < TRESET < TERLB, max Figure 34. External reset sequence long, BIST enabled Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE1,2 Flash Init PHASE3 Device Config DRUN BAF+ Application Ex ecut ion TFRL, min < TRESET < TFRL, max Figure 35. Functional reset sequence long MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 68 NXP Semiconductors Revision History Reset Sequence Trigger Reset Sequence Start Condition RESET_B PHASE3 DRUN BAF+ Application Execution TFRS, min < TRESET < TFRS, max Figure 36. Functional reset sequence short The reset sequences shown in Figure 35 and Figure 36 are triggered by functional reset events. RESET_B is driven low during these two reset sequences only if the corresponding functional reset source (which triggered the reset sequence) was enabled to drive RESET_B low for the duration of the internal reset sequence. See the RGM_FBRE register in the device reference manual for more information. 11 Revision History 11.1 Revision History The following table provides a revision history for this document. Table 52. Revision History Rev. No. Date Rev 1 14 March 2013 Rev 2 7 August 2015 Substantial Changes Initial Release * In features: * Updated BAF feature with sentence, Boot Assist Flash (BAF) supports internal flash programming via a serial link (SCI) * Updated FlexCAN3 with FD support * Updated number of STMs to two. * In Block diagram: * Updated SRAM size from 128 KB to 256 KB. * In Family Comparison: * Added note: All optional features (Flash memory, RAM, Peripherals) start with lowest number or address (e.g. FlexCAN0) and end at highest available number or address (e.g. MPC574xB/D have 6 CAN, ending with FlexCAN5). * Revised MPC5746C Family Comparison table. * In Ordering parts: * Updated ordering parts diagram to include 100 MAPBGA information and optional fields. * In table: Absolute maximum ratings * Removed entry: 'VSS_HV' * Added spec for 'VDD12' * Updated 'Max' column for 'VINA' Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 69 Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * Updated footnote for VDD_HV_ADC1_REF. * Added footnote to 'Conditions', All voltages are referred to VSS_HV unless otherwise specified * Removed footnote from 'Max', Absolute maximum voltages are currently maximum burn-in voltages. Absolute maximum specifications for device stress have not yet been determined. * In section: Recommended operating conditions * Added opening text: ''The following table describes the operating conditions ... " * Added note: "VDD_HV_A, VDD_HV_B and VDD_HV_C are all ... " * In table: Recommended operating conditions (VDD_HV_x = 3.3 V) and (VDD_HV_x = 5 V) * Added footnote to 'Conditions' cloumn, (All voltages are referred to VSS_HV unless otherwise specified). * Updated footnote for 'Min' column to Device will be functional down (and electrical specifications as per various datasheet parameters will be guaranteed) to the point where one of the LVD/HVD resets the device. When voltage drops outside range for an LVD/HVD, device is reset. * Removed footnote for 'VDD_HV_A', 'VDD_HV_B', and 'VDD_HV_C' entry and updated the parameter column. * Removed entry : 'VSS_HV' * Updated 'Parameter' column for 'VDD_HV_FLA', 'VDD_HV_ADC1_REF', 'VDD_LV' * Updated 'Min' column for 'VDD_HV_ADC0' 'VDD_HV_ADC1' * Updated 'Parameter' 'Min' 'Max' columns for 'VSS_HV_ADC0' and 'VSS_HV_ADC1' * Updated footnote for 'VDD_LV ' to VDD_LV supply pins should never be grounded (through a small impedance). If these are not driven, they should only be left floating. * Removed row for symbol 'VSS_LV' * Removed footnote from 'Max' column of 'VDD_HV_ADC0' and 'VDD_HV_ADC1', (PA3, PA7, PA10, PA11 and PE12 ADC_1 channels are coming from VDD_HV_B domain hence VDD_HV_ADC1 should be within 100 mV of VDD_HV_B when these channels are used for ADC_1). * In table: Recommended operating conditions (VDD_HV_x = 3.3 V) * Removed footnote from 'VIN1_CMP_REF', (Only applicable when supplying from external source). * In table: Recommended operating conditions (VDD_HV_x = 5 V) * Added spec for 'VIN1_CMP_REF' and corresponding footnotes. * In section: Voltage monitor electrical characteristics * Updated description for Low Voltage detector block. * Added note, BCP56, MCP68 and MJD31 are guaranteed ballasts. * In table: Voltage regulator electrical specifications * Added footnote, Ceramic X7R or X5R type with capacitance-temperature characteristics +/-15% of -55 degC to +125degC is recommended. The tolerance +/-20% is acceptable. * Revised table, Voltage monitor electrical characteristics * In section: Supply current characteristics * In table: Current consumption characteristics * IDD_BODY_4: Updated SYS_CLK to 120 MHz. * IDD_BODY_4: Updated Max for Ta= 105 C fand 85 C ) * Idd_STOP: Added condition for Ta= 105 C and removed Max value for Ta= 85 C. * IDD_HV_ADC_REF: Added condition for Ta= 105 C and 85 C and removed Max value for Ta= 25 C. * IDD_HV_FLASH: Added condition for Ta= 105 C and 85 C * In table: Low Power Unit (LPU) Current consumption characteristics * LPU_RUN and LPU_STOP: Added condition for Ta= 105 C and 85 C Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 70 NXP Semiconductors Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * In table: STANDBY Current consumption characteristics * Added condition for Ta= 105 C and 85 C for all entries. * In section: I/O parameters * In table: Functional Pad AC Specifications @ 3.3 V Range * Updated values for 'pad_sr_hv (output)' * In table: DC electrical specifications @ 3.3V Range * Updateded Min and Max values for Vih and Vil respectively. * In table: Functional Pad AC Specifications @ 5 V Range * Updated values for 'pad_sr_hv (output)' * In table DC electrical specifications @ 5 V Range * Updated Min value for Vhys * In section: Reset pad electrical characteristics * Revised table, Reset electrical characteristics * Deleted note, There are some specific ports that supports TTL functionality. These ports are, PB[4], PB[5], PB[6], PB[7], PB[8], PB[9], PD[0], PD[1], PD[2], PD[3], PD[4], PD[5], PD[6], PD[7], PD[8], PD[9], PD[10], and PD[11]. * In section: PORST electrical specifications * In table: PORST electrical specifications * Updated 'Min' value for WNFPORST * In section: Peripheral operating requirements and behaviours * Changed section title from Input impedance and ADC accuracy to Input equivalent circuit and ADC conversion characteristics. * Revised table: ADC conversion characteristics (for 12-bit) and ADC conversion characteristics (for 10-bit) * Removed table, ADC supply configurations. * In section: Analogue Comparator (CMP) electrical specifications * In table: Comparator and 6-bit DAC electrical specifications * Updated 'Max' value of IDDLS * Updated 'Min' and 'Max' for VAIO and DNL * Updated 'Descripton' 'Min' 'Max' od VH * Updated row for tDHS * Added row for tDLS * Removed row for VCMPOh and VCMPOl * In section: Clocks and PLL interfaces modules * In table: Main oscillator electrical characteristics * VXOSCHS: Removed values for 4 MHz. * TXOSCHSSU: Updated range to 8-40 MHz. * In table: 16 MHz RC Oscillator electrical specifications * Updated 'Max' for Tstartup and TLTJIT * Removed FUntrimmed row * In table: 128 KHz Internal RC oscillator electrical specifications * Fosc: Removed Uncaliberated 'Condition' and updated 'Min', 'Typ', and 'Max' for Caliberated condition * Fosc: Updated 'Temperature dependence' and 'Supply dependence' Max values * In table: PLL electrical specifications * Removed entries for Input Clock Low Level, Input Clock High Level, Power consumption, Regulator Maximum Output Current, Analog Supply, Digital Supply (VDD_LV), Modulation Depth (Down Spread), PLL reset assertion time, and Power Consumption Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 71 Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * Removed 'Typ' value for Duty Cycle at pllclkout * Removed 'Min' value for Lock Time in calibration mode. * In table: Jitter calculation * Added 1 Sigma Random Jitter and Total Period Jitter values for Long Term Jitter (Interger and Fractional Mode) rows. * In section Flash read wait state and address pipeline control settings * In Flash Read Wait State and Address Pipeline Control: Updated APC for 40 MHz. * Removed section: On-chip peripherals * In section, Thermal attributes * Added table for 100 MAPBGA * In section Obtaining package dimensions * Updated package details for 100 MAPBGA * Editoral updates throughtout including correction of various module names. Rev 3 2 March 2016 * In section, Recommended operating conditions * Added a new Note * In section, Voltage regulator electrical characteristics * In table, Voltage regulator electrical specifications: * Added a new row for CHV_VDD_B * Added a footnote on VDD_HV_BALLAST * Added a new Note at the end of this section * In section, Voltage monitor electrical characteristics * In table, Voltage monitor electrical characteristics: * Removed "VLVD_FLASH" and "VLVD_FLASH during low power mode using LPBG as reference" rows * Updated Fall and Rise trimmed Minimum values for VHVD_LV_cold * In section, Supply current characteristics * In table, Current consumption characteristics: * Updated the footnote mentioned in the Condition column of IDD_STOP row * Updated all TBD values * In table, Low Power Unit (LPU) Current consumption characteristics: * Updated the typical value of LPU_STOP to 0.18 mA * Updated all TBD values * In table, STANDBY Current consumption characteristics: * Updated all TBD values * In section, AC specifications @ 3.3 V Range * In table, Functional Pad AC Specifications @ 3.3 V Range: * Updated Rise/Fall Edge values * In section, DC electrical specifications @ 3.3V Range * In table, DC electrical specifications @ 3.3V Range: * Updated Max value for Vol to 0.1 * VDD_HV_x * In section, AC specifications @ 5 V Range * In table, Functional Pad AC Specifications @ 5 V Range: * Updated Rise/Fall Edge values * In section, DC electrical specifications @ 5 V Range * In table, DC electrical specifications @ 5 V Range: Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 72 NXP Semiconductors Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * Updated Min and Max values for Pull_Ioh and Pull_Iol rows * Updated Max value for Vol to 0.1 * VDD_HV_x * In section, Reset pad electrical characteristics * In table, Functional reset pad electrical specifications: * Updated parameter column for VIH, VIL and VHYS rows * Updated Min and Max values for VIH and VIL rows * In section, PORST electrical specifications * In table, PORST electrical specifications: * Updated Unit and Min/Max values for VIH and VIL rows * In section, Input equivalent circuit and ADC conversion characteristics * In table, ADC conversion characteristics (for 12-bit): * Updated "ADC Analog Pad (pad going to one ADC)" row * In table, ADC conversion characteristics (for 10-bit): * Updated "ADC Analog Pad (pad going to one ADC)" row * In section, Analog Comparator (CMP) electrical specifications * In table, Comparator and 6-bit DAC electrical specifications: * Updated Min and Max values for VAIO to 47 mV * Updated Max value for tDLS to 21 s * In section, Main oscillator electrical characteristics * In table, Main oscillator electrical characteristics: * Updated VIH Min value to 1.95V * Updated VIL Max value to 1.25V * Removed VIH Typ value * In section, PLL electrical specifications * In table, PLL electrical specifications: * Updated Max value for Modulation Depth (Center Spread) to +/- 3.0% Rev 4 9 March 2016 * In section, Voltage regulator electrical characteristics * In table, Voltage regulator electrical specifications: * Updated the footnote on VDD_HV_BALLAST Rev 5 27 February 2017 * In Family Comparison section: * Updated the "MPC5746C Family Comparison" table. * added "NVM Memory Map 1", "NVM Memory Map 2", and "RAM Memory Map" tables. * Updated the product version, flash memory size and optional fields information in Ordering Information section. * In Recommended Operating Conditions section, removed the note related to additional crossover current. * VDD_HV_C row added in "Voltage regulator electrical specifications" table in Voltage regulator electrical characteristics section. * In Voltage Monitor Electrical Characteristics section, updated the "Trimmed" Fall and Rise specs of VHVD_LV_cold parameter in "Voltage Monitor Electrical Characteristics" table. * In AC Electrical Specifications: 3.3 V Range section, changed the occurrences of "ipp_sre[1:0]" to "SIUL2_MSCRn.SRC[1:0]" in the table. Table continues on the next page... MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 73 Revision History Table 52. Revision History (continued) Rev. No. Date Substantial Changes * In DC Electrical Specifications: 3.3 V Range section, changed the occurrences of "ipp_sre[1:0]" to "SIUL2_MSCRn.SRC[1:0]" and updated "Vol min and max" values in the table. * In AC Electrical Specifications: 5 V Range section, changed the occurrences of "ipp_sre[1:0]" to "SIUL2_MSCRn.SRC[1:0]" in the table. * In DC Electrical Specifications: 5 V Range section, changed the occurrences of "ipp_sre[1:0]" to "SIUL2_MSCRn.SRC[1:0]" and updated "Vol min and max" values in the table. * In "Flash memory AC timing specifications" table in Flash memory AC timing specifications section: * Updated the "tpsus" typ value from 7 us to 9.4 us. * Updated the "tpsus" max value from 9.1 us to 11.5 us. * Added "Continuous SCK Timing" table in DSPI timing section. * Added "ADC pad leakage" at 105C TA conditions in "ADC conversion characteristics (for 12-bit)" table in ADC electrical specifications section. * In "STANDBY Current consumption characteristics" table in Supply current characteristics section: * Updated the Typ and max values of IDD Standby current. * Added IDD Standby3 current spec for FIRC ON. * Removed IVDDHV and IVDDLV specs in 16 MHz RC Oscillator electrical specifications section. * Added Reset Sequence section, with Reset Sequence Duration, BAF execution duration section, and Reset Sequence Distribution as its sub-sections. Rev 5.1 22 May 2017 * Removed the Introduction section from Section 4 "General". * In AC Specifications@3.3V section, removed note related to Cz results and added two notes. * In AC Specifications@5V section, added two notes. * In ADC Electrical Specifications section, added spec value of "ADC Analog Pad" at Max leakage (standard channel)@ 105 C TA in "ADC conversion characteristics (for 10-bit)" table. * In PLL Electrical Specifications section, updated the first footnote of "Jitter calculation" table. * In Analog Comparator Electrical Specifications section, updated the TDLS (propagation delay, low power mode) max value in "Comparator and 6-bit DAC electrical specifications" table to 21 us. * In Recommended Operating Conditions section, updated the footnote link to TA in "Recommended operating conditions (V DD_HV_x = 5V)" table. Rev 6 21 Nov 2018 * In Table 2 changed the Code Flash Block 9 (0x01240000 - 0x0127FFFF) from 'not available' to 'available' for MPC5746. * In Table 3 added 32 and 64 KB flash blocks and footnote "Flexible patitions for boot and EEPROM". * Added Table 4. MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 74 NXP Semiconductors Revision History Table 52. Revision History Rev. No. Date Substantial Changes * Updated GPIO and added GPI row in Table 1. * Changed the EEPROM support for MPC574xC devices from Emulated up to"64K" to "Emulated up to 128K" in Table 1. * Changed "VDD_HV_A" to "VDD_HV_IO" and changed the condition from "VDD_HV_A = VDD_POR" to "3.0 V < VDD_HV_IO < 5.5 V" in Table 19. * Added the text "For internal ballast configuration the VRC_CTL pin should be left floating" in existing foot note "Recommended Transistors:MJD31 @ 85C....." in Table 11. * Added note "For the Precision channel Analog inputs...pulled low/high externally" after the table "STANDBY Current consumption characteristics" in Supply current characteristics. * In Table 36 : * Added footnote in "High Speed Mode" column. * For Parameter "DSPI cycle time" changed the Condition from "Master (MTFE=0)" to "Master". * In Voltage monitor electrical characteristics * Under the column "Reset Type" changed "Destructive" to "POR" throughout the table "Voltage monitor electrical characteristics". * Changed the Reset type of "VLVD_IO_A_HI" to "Functional" MPC5746C Microcontroller Datasheet, Rev. 6, 11/2018 NXP Semiconductors 75 How to Reach Us: Home Page: nxp.com Web Support: nxp.com/support Information in this document is provided solely to enable system and software implementers to use NXP products. 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