CY7C1061G Automotive 16-Mbit (1 M words x 16 bit) Static RAM with Error-Correcting Code (ECC) 16-Mbit (1 M words x 16 bit) Static RAM with Error-Correcting Code (ECC) Features Functional Description CY7C1061G[1] is a high-performance CMOS fast static RAM automotive part with embedded ECC. ECC logic can detect and correct single-bit error in read data word during read cycles. High speed tAA = 10 ns Temperature range Automotive-E: -40 C to 125 C Embedded error-correcting code (ECC) for single-bit error correction Low active and standby currents ICC = 90-mA typical at 100 MHz ISB2 = 20-mA typical Operating voltage range: 2.2 V to 3.6 V 1.0-V data retention Transistor-transistor logic (TTL) compatible inputs and outputs Available in Pb-free 48-ball VFBGA and 48-pin TSOP I packages This device has single chip enable input and is accessed by asserting the chip enable input (CE) LOW. To perform data writes, assert the Write Enable (WE) input LOW and provide the data and address on the device data pins (I/O0 through I/O15) and address pins (A0 through A19) respectively. The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs control byte writes and write data on the corresponding I/O lines to the memory location specified. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. To perform data reads, assert the Output Enable (OE) input and provide the required address on the address lines. Read data is accessible on I/O lines (I/O0 through I/O15). You can perform byte accesses by asserting the required byte enable signal (BHE or BLE) to read either the upper byte or the lower byte of data from the specified address location. All I/Os (I/O0 through I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), or control signals are de-asserted (OE, BLE, BHE). Refer to the below logic block diagram. The CY7C1061G automotive device is available in 48-ball VFBGA and 48-pin TSOP I packages. Logic Block Diagram - CY7C1061G M EM O RY ARRAY ECC DECODER SENSE IN P U T B U F F E R AMPLIFIERS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 ROW DECODER ECC EN CO D ER I/ O 0 I/ O 7 I/ O 8 I/ O 1 5 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 CO LU M N D ECO D ER BHE WE OE CE BLE Note 1. The device does not support automatic write-back on error detection. Cypress Semiconductor Corporation Document Number: 001-84821 Rev. *H * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised October 28, 2015 CY7C1061G Automotive Contents Pin Configurations ........................................................... 3 Product Portfolio .............................................................. 3 Maximum Ratings ............................................................. 4 Operating Range ............................................................... 4 DC Electrical Characteristics .......................................... 4 Capacitance ...................................................................... 5 Thermal Resistance .......................................................... 5 AC Test Loads and Waveforms ....................................... 5 Data Retention Characteristics ....................................... 6 Data Retention Waveform ................................................ 6 AC Switching Characteristics ......................................... 7 Switching Waveforms ...................................................... 8 Truth Table ...................................................................... 12 Document Number: 001-84821 Rev. *H Ordering Information ...................................................... 13 Ordering Code Definitions ......................................... 13 Package Diagrams .......................................................... 14 Acronyms ........................................................................ 15 Document Conventions ................................................. 15 Units of Measure ....................................................... 15 Document History Page ................................................. 16 Sales, Solutions, and Legal Information ...................... 18 Worldwide Sales and Design Support ....................... 18 Products .................................................................... 18 PSoC(R) Solutions ...................................................... 18 Cypress Developer Community ................................. 18 Technical Support ..................................................... 18 Page 2 of 18 CY7C1061G Automotive Pin Configurations Figure 1. 48-ball VFBGA (6 x 8 x 1.0 mm) pinout [2] 1 2 3 4 5 6 BLE OE A0 A1 A2 NC A I/O8 BHE A3 A4 CE I/O0 B I/O9 I/O10 A5 A6 I/O1 I/O2 C VSS I/O11 A17 A7 VCC D VCC I/O12 NC A16 I/O4 VSS E I/O14 I/O13 A14 A15 I/O5 I/O6 F I/O15 A19 A12 A13 WE I/O7 G A18 A8 A9 A10 A11 NC H I/O3 Figure 2. 48-pin TSOP I (12 x 18.4 x 1 mm) pinout [2] A4 A3 A2 A1 A0 NC CE I/O0 I/O1 I/O2 I/O3 VDD GND I/O4 I/O5 I/O6 I/O7 WE NC A19 A18 A17 A16 A15 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 A5 A6 A7 A8 OE BHE BLE I/O15 I/O14 I/O13 I/O12 GND VDD I/O11 I/O10 I/O9 I/O8 NC A9 A10 A11 A12 A13 A14 Product Portfolio Current Consumption Product CY7C1061G30 Range Automotive VCC Range (V) 2.2 V-3.6 V Speed (ns) 10 Operating ICC (mA) f = fmax Standby, ISB2 (mA) Typ[3] Max Typ[3] Max 90 160 20 50 Notes 2. NC pins are not connected internally to the die. 3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V, TA = 25 C. Document Number: 001-84821 Rev. *H Page 3 of 18 CY7C1061G Automotive DC input voltage [4] .................................. -0.5 V to VCC + 0.5 V Maximum Ratings Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage temperature ..................................... -65 C to +150 C Ambient temperature with power applied ........................................ -55 C to +125 C Supply voltage on VCC relative to GND ........... -0.5 V to +6.0 V DC voltage applied to outputs in High-Z State [4] .....................................-0.5 V to VCC + 0.5 V Current into outputs (LOW) ............................................. 20 mA Static discharge voltage (MIL-STD-883, Method 3015) ......................................> 2001 V Latch-up current .........................................................> 140 mA Operating Range Grade Ambient Temperature VCC Automotive-E -40 C to +125 C 2.2 V to 3.6 V DC Electrical Characteristics Over the operating range of -40 C to 125 C Parameter Description Test Conditions 10 ns Min Typ [5] Max Output HIGH 2.2 V to 2.7 V voltage 2.7 V to 3.6 V VCC = Min, IOH = -1.0 mA 2.0 - - VCC = Min, IOH = -4.0 mA 2.2 - - VOL Output LOW 2.2 V to 2.7 V voltage 2.7 V to 3.6 V VCC = Min, IOL = 2 mA - - 0.4 VIH[4] Input HIGH voltage VOH VCC = Min, IOL = 8 mA Unit V - - 0.4 2.2 V to 2.7 V - 2.0 - VCC + 0.3 2.7 V to 3.6 V - 2.0 - VCC + 0.3 2.2 V to 2.7 V - -0.3 - 0.6 2.7 V to 3.6 V V V VIL[4] Input LOW voltage - -0.3 - 0.8 IIX Input leakage current GND < VIN < VCC -5.0 - +5.0 A IOZ Output leakage current GND < VOUT < VCC, Output disabled -5.0 - +5.0 A ICC Operating supply current VCC = Max, IOUT = 0 mA, f = fMAX = 1/tRC CMOS levels - 90.0 160.0 mA ISB1 Automatic CE power down current - TTL inputs Max VCC, CE > VIH, VIN > VIH or VIN < VIL, f = fMAX - - 60.0 mA ISB2 Automatic CE power down current - CMOS inputs Max VCC, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V, f = 0 - 20.0 50.0 mA V Notes 4. VIL (min) = -2.0 V and VIH (max) = VCC +2 V for pulse durations of less than 2 ns. 5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC = 3 V, TA = 25 C. Document Number: 001-84821 Rev. *H Page 4 of 18 CY7C1061G Automotive Capacitance Parameter [6] Description CIN Input capacitance COUT I/O capacitance Test Conditions All Packages Unit 10 pF 10 pF TA = 25 C, f = 1 MHz, VCC = VCC(typ) Thermal Resistance Parameter [6] Description JA Thermal resistance (junction to ambient) JC Thermal resistance (junction to case) Test Conditions 48-ball VFBGA 48-pin TSOP I Unit Still air, soldered on a 3 x 4.5 inch, four layer printed circuit board 31.50 57.99 C/W 15.75 13.42 C/W AC Test Loads and Waveforms Figure 3. AC Test Loads and Waveforms [7] High-Z Characteristics: VCC 50 Output VTH Z0 = 50 Output 30 pF* * Including JIG and Scope (b) All Input Pulses VHIGH GND R2 5 pF* (a) * Capacitive load consists of all components of the test environment R1 90% 90% 10% 10% Rise Time: > 1 V/ns (c) Parameters 3.0 V Unit R1 317 R2 351 VTH 1.5 V VHIGH 3 V Fall Time: > 1 V/ns Notes 6. Tested initially and after any design or process changes that may affect these parameters. 7. Full-device AC operation assumes a 100-s ramp time from 0 to VCC(min) and 100-s wait time after VCC stabilizes to its operational value. Document Number: 001-84821 Rev. *H Page 5 of 18 CY7C1061G Automotive Data Retention Characteristics Over the operating range of -40 C to 125 C Parameter VDR Description Conditions Min Max Unit 1.0 - V VCC for data retention - Data retention current VCC = VDR, CE > VCC - 0.2 V, VIN > VCC - 0.2 V or VIN < 0.2 V - 50.0 mA tCDR[8] Chip deselect to data retention time - 0 - ns tR[8] Operation recovery time VCC > 2.2 V 10.0 - ns ICCDR Data Retention Waveform Figure 4. Data Retention Waveform [9] VCC VCC(min) DATA RETENTION MODE VDR = 1 V tCDR VCC(min) tR CE Notes 8. Tested initially and after any design or process changes that may affect these parameters. 9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s. Document Number: 001-84821 Rev. *H Page 6 of 18 CY7C1061G Automotive AC Switching Characteristics Over the operating range of -40 C to 125 C Parameter [10] Description 10 ns Min Max Unit Read Cycle tPOWER VCC(stable) to the first access[11] 100.0 - s tRC Read cycle time 10.0 - ns tAA Address to data - 10.0 ns tOHA Data hold from address change 3.0 - ns tACE CE LOW to data - 10.0 ns tDOE OE LOW to data - 5.0 ns 0 - ns tLZOE OE LOW to low-Z [12, 13] [12, 13] tHZOE OE HIGH to high-Z tLZCE CE LOW to low-Z [12, 13] tHZCE tPU CE HIGH to high-Z - 5.0 ns 3.0 - ns [12, 13] - 5.0 ns [14] 0 - ns CE LOW to power-up tPD CE HIGH to power-down tDBE Byte enable to data valid tLZBE tHZBE Write Cycle Byte enable to low-Z [14] [12, 13] Byte disable to high-Z [12, 13] - 10.0 ns - 5.0 ns 0 - ns - 6.0 ns [15, 16] tWC Write cycle time 10.0 - ns tSCE CE LOW to write end 7.0 - ns tAW Address setup to write end 7.0 - ns tHA Address hold from write end 0 - ns tSA Address setup to write start 0 - ns tPWE WE pulse width 7.0 - ns tSD Data setup to write end 5.0 - ns tHD Data hold from write end 0 - ns tLZWE WE HIGH to low-Z [12, 13] 3.0 - ns tHZWE WE LOW to high-Z [12, 13] - 5.0 ns tBW Byte Enable to write end 7.0 - ns Notes 10. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in part (a) of Figure 3 on page 5, unless specified otherwise. 11. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed. 12. tHZOE, tHZCE, tHZWE,and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 5. Hi-Z, Lo-Z transition is measured 200 mV from steady state voltage. 13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device. 14. These parameters are guaranteed by design and are not tested. 15. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE, or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 16. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 001-84821 Rev. *H Page 7 of 18 CY7C1061G Automotive Switching Waveforms Figure 5. Read Cycle No. 1 of CY7C1061G (Address Transition Controlled) [17, 18] tRC ADDRESS tAA tOHA DATA I/O PREVIOUS DATAOUT VALID DATAOUT VALID Figure 6. Read Cycle No. 2 (OE Controlled) [18, 19] ADDRESS tRC CE tPD tHZCE tACE OE tHZOE tDOE tLZOE BHE/ BLE tDBE tLZBE DATA I/O HIGH IMPEDANCE tHZBE DATAOUT VALID HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU ISB Notes 17. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL. 18. WE is HIGH for read cycle. 19. Address valid prior to or coincident with CE LOW transition. Document Number: 001-84821 Rev. *H Page 8 of 18 CY7C1061G Automotive Switching Waveforms (continued) Figure 7. Write Cycle No. 1 (CE Controlled) [20, 21] tW C ADD RESS t SA t SCE CE t AW t HA t PW E WE t BW BH E/ BLE OE t HZO E DA TA I/O t HD t SD Note 22 D ATA IN VALID Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [20, 21, 23] tWC ADDRESS tSCE CE tBW BHE/ BLE tSA tAW tHA tPWE WE tHZWE DATA I/O Note 22 tSD tLZWE tHD DATAIN VALID Notes 20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 21. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 22. During this period, the I/Os are in output state. Do not apply input signals. 23. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD. Document Number: 001-84821 Rev. *H Page 9 of 18 CY7C1061G Automotive Switching Waveforms (continued) Figure 9. Write Cycle No. 3 (WE Controlled) [24, 25] tW C ADDRESS tS C E CE tA W tS A tH A tP W E WE tB W B H E /B L E OE tH Z O E D A T A I/O Note 26 tH D tS D D A T A I N V A L ID Notes 24. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 25. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 26. During this period the I/Os are in output state. Do not apply input signals. Document Number: 001-84821 Rev. *H Page 10 of 18 CY7C1061G Automotive Switching Waveforms (continued) Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [27, 28] tWC ADDRESS tSCE CE tAW tSA tHA tBW BHE/ BLE tPWE WE tHZWE DATA I/O Note 29 tSD tHD tLZWE DATAIN VALID Notes 27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates the write. 28. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH. 29. During this period, the I/Os are in output state. Do not apply input signals. Document Number: 001-84821 Rev. *H Page 11 of 18 CY7C1061G Automotive Truth Table CE H OE [30] X WE BLE BHE [30] [30] [30] High Z High Z Power down Standby (ISB) X X X I/O0-I/O7 I/O8-I/O15 Mode Power L L H L L Data out Data out Read all bits Active (ICC) L L H L H Data out High Z Read lower bits only Active (ICC) L L H H L High Z Data out Read upper bits only Active (ICC) L X L L L Data in Data in Write all bits Active (ICC) L X L L H Data in High Z Write lower bits only Active (ICC) L X L H L High Z Data in Write upper bits only Active (ICC) L H H X X High Z High Z Selected, outputs disabled Active (ICC) L X X H H High Z High Z Selected, outputs disabled Active (ICC) Note 30. The input voltage levels on these pins should be either at VIH or VIL. Document Number: 001-84821 Rev. *H Page 12 of 18 CY7C1061G Automotive Ordering Information Speed (ns) 10 Voltage Range 2.2 V-3.6 V Package Diagram Ordering Code Package Type (all Pb-free) CY7C1061G30-10BV1XE 51-85150 48-ball VFBGA (6 x 8 x 1.0 mm) (Pb-free) CY7C1061G30-10ZXE 51-85183 48-pin TSOP I (12 x 18.4 x 1.0 mm) (Pb-free) Operating Range Automotive-E Ordering Code Definitions CY 7 C 1 06 1 G XX - 10 XX 1 X E Temperature Range: E = Automotive-E (-40 C to 125 C) Pb-free Chip enables: 1 = Single Chip Enable Package Type: XX = BV or Z BV = 48-ball VFBGA; Z = 48-pin TSOP I Speed: 10 ns Voltage Range: 30 = 2.2 V-3.6 V Revision Code "G": Process Technology - 65 nm Data Width: 1 = x 16-bits Density: 06 = 16-Mbit Family Code: 1 = Fast Asynchronous SRAM family Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 001-84821 Rev. *H Page 13 of 18 CY7C1061G Automotive Package Diagrams Figure 11. 48-ball VFBGA (6 x 8 x 1.0 mm) BV48/BZ48 Package Outline, 51-85150 51-85150 *H Figure 12. 48-pin TSOP I (12 x 18.4 x 1.0 mm) Z48A Package Outline, 51-85183 51-85183 *D Document Number: 001-84821 Rev. *H Page 14 of 18 CY7C1061G Automotive Acronyms Acronym Document Conventions Description Units of Measure BHE Byte High Enable BLE Byte Low Enable C degree Celsius CE Chip Enable MHz megahertz CMOS Complementary Metal Oxide Semiconductor A microampere I/O Input/Output s microsecond OE Output Enable mA milliampere SRAM Static Random Access Memory mm millimeter TSOP Thin Small Outline Package ns nanosecond TTL Transistor-Transistor Logic ohm VFBGA Very Fine-Pitch Ball Grid Array % percent WE Write Enable pF picofarad V volt W watt Document Number: 001-84821 Rev. *H Symbol Unit of Measure Page 15 of 18 CY7C1061G Automotive Document History Page Document Title: CY7C1061G Automotive, 16-Mbit (1 M words x 16 bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-84821 Rev. ECN No. Orig. of Change Submission Date ** 3825225 MEMJ 11/29/2012 New data sheet. *A 4003550 NILE 05/20/2013 Updated Document Title to read as "CY7C1061G Automotive, 16-Mbit (1 M words x 16 bit) Static RAM with Error-Correcting Code (ECC)". Updated Features. Updated Functional Description. Removed "Logic Block Diagram - CY7C1061GE". Updated Logic Diagram for Single Chip Enable. Updated Pin Configurations: Updated Pin diagram to have BV1XE without ERR pin Updated Product Portfolio. Updated Operating Range. Updated Capacitance. Updated Thermal Resistance. Updated Data Retention Characteristics. Updated AC Switching Characteristics: Removed 12 ns, 17 ns speed bin related information and included 10 ns speed bin related information. Updated Switching Waveforms. Removed "ERR Output - CY7C1061GE". Updated Package Diagrams: Added 48-pin TSOP I Package Diagram (Figure 11). *B 4292074 MEMJ 02/28/2014 Updated Features: Mentioned frequency of measurement for ICC (typical). Updated Functional Description: Replaced "an error detection" with "a single-bit error detection". Added Note 1 (for ECC) and referred the same note in CY7C1061G. Updated Product Portfolio: Replaced CY7C1061G with CY7C1061G30. Updated Operating Range: Replaced Automotive with Automotive-E. Updated DC Electrical Characteristics: Added typical value for ICC parameter (90 mA). Added typical value for ISB2 parameter (20 mA). Added Note 5 and referred the same note in "Typ" column. Updated AC Switching Characteristics: Added tPOWER parameter and its details. Added Note 11 and referred the same note in description of tPOWER parameter. Added Note 13 and referred the same note in description of tLZOE, tHZOE, tLZCE, tHZCE, tLZBE, tHZBE, tLZWE, and tHZWE parameters. Added Note 16 and referred the same note in "Write Cycle". Updated Switching Waveforms: Added Note 22 and referred the same note in Figure 7 and Figure 8. Added Note 23 and referred the same note in Figure 8. Added Figure 9. Added Note 26 and referred the same note in Figure 9 (to indicate that I/Os are in output state). Added Note 29 and referred the same note in Figure 10 (to indicate that I/Os are in output state). Document Number: 001-84821 Rev. *H Description of Change Page 16 of 18 CY7C1061G Automotive Document History Page (continued) Document Title: CY7C1061G Automotive, 16-Mbit (1 M words x 16 bit) Static RAM with Error-Correcting Code (ECC) Document Number: 001-84821 Rev. ECN No. Orig. of Change Submission Date Description of Change *B (cont.) 4292074 MEMJ 02/28/2014 Updated Truth Table: Added Note 30 and referred the same note in "X" corresponding to Power down mode. Added condition to place outputs in disable state by making both BHE and BLE HIGH. Added Errata. Updated to new template. *C 4330547 AJU 04/02/2014 No technical updates. *D 4397546 AJU 06/03/2014 Updated AC Switching Characteristics: Updated Note 12 (Removed tLZOE, tLZCE, tLZWE, and tLZBE; and added Hi-Z, Lo-Z transition). *E 4469360 NILE 09/18/2014 No technical updates. *F 4576640 VINI 11/21/2014 No technical updates. *G 4800949 NILE 09/30/2015 Updated Logic Block Diagram - CY7C1061G. Updated Package Diagrams: spec 51-85183 - Changed revision from *C to *D. Removed Errata. Updated to new template. *H 4983893 NILE 10/28/2015 Changed status from Preliminary to Final. Document Number: 001-84821 Rev. *H Page 17 of 18 CY7C1061G Automotive Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC(R) Solutions Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/memory cypress.com/go/psoc cypress.com/go/touch psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-84821 Rev. *H Revised October 28, 2015 Page 18 of 18 QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document may be the trademarks of their respective holders.