CY7C1061G Automotive
16-Mbit (1 M words × 16 bit) Static RAM
with Error-Correcting Code (ECC)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 001-84821 Rev. *H Revised October 28, 2015
16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Features
■High speed
❐tAA = 10 ns
■Temperature range
❐Automotive-E: –40 °C to 125 °C
■Embedded error-correcting code (ECC) for single-bit error
correction
■Low active and standby currents
❐ICC = 90-mA typical at 100 MHz
❐ISB2 = 20-mA typical
■Operating voltage range: 2.2 V to 3.6 V
■1.0-V data retention
■Transistor-transistor logic (TTL) compatible inputs and outputs
■Available in Pb-free 48-ball VFBGA and 48-pin TSOP I
packages
Functional Description
CY7C1061G[1] is a high-performance CMOS fast static RAM
automotive part with embedded ECC. ECC logic can detect and
correct single-bit error in read data word during read cycles.
This device has single chip enable input and is accessed by
asserting the chip enable input (CE) LOW.
To perform data writes, assert the Write Enable (WE) input LOW
and provide the data and address on the device data pins (I/O0
through I/O15) and address pins (A0 through A19) respectively.
The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs
control byte writes and write data on the corresponding I/O lines
to the memory location specified. BHE controls I/O8 through
I/O15 and BLE controls I/O0 through I/O7.
To perform data reads, assert the Output Enable (OE) input and
provide the required address on the address lines. Read data is
accessible on I/O lines (I/O0 through I/O15). You can perform
byte accesses by asserting the required byte enable signal (BHE
or BLE) to read either the upper byte or the lower byte of data
from the specified address location.
All I/Os (I/O0 through I/O15) are placed in a high-impedance state
when the device is deselected (CE HIGH), or control signals are
de-asserted (OE, BLE, BHE). Refer to the below logic block
diagram.
The CY7C1061G automotive device is available in 48-ball
VFBGA and 48-pin TSOP I packages.
Logic Block Diagram – CY7C1061G
MEMORY
ARRAY
ROWDECODER
A1
A2
A3
A4
A5
A6
A7
A8
A9
A0
COLUM NDECODER
A10
SENSE
AMPLIFIERS
ECCDECODER
A11
A12
A13
A14
A15
A16
A17
ECCENCODER IN PU TBUFFER
I/O 0‐I/O 7
I/O 8‐I/O 15
BHE
WE
OE
BLE
CE
A18
A19
Note
1. The device does not support automatic write-back on error detection.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 2 of 18
Contents
Pin Configurations ...........................................................3
Product Portfolio ..............................................................3
Maximum Ratings ............................................................. 4
Operating Range ............................................................... 4
DC Electrical Characteristics ..........................................4
Capacitance ......................................................................5
Thermal Resistance ..........................................................5
AC Test Loads and Waveforms .......................................5
Data Retention Characteristics ....................................... 6
Data Retention Waveform ................................................6
AC Switching Characteristics .........................................7
Switching Waveforms ......................................................8
Truth Table ......................................................................12
Ordering Information ...................................................... 13
Ordering Code Definitions ......................................... 13
Package Diagrams .......................................................... 14
Acronyms ........................................................................ 15
Document Conventions ................................................. 15
Units of Measure ....................................................... 15
Document History Page ................................................. 16
Sales, Solutions, and Legal Information ...................... 18
Worldwide Sales and Design Support ....................... 18
Products .................................................................... 18
PSoC® Solutions ...................................................... 18
Cypress Developer Community ................................. 18
Technical Support ..................................................... 18
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 3 of 18
Pin Configurations
Figure 1. 48-ball VFBGA (6 × 8 × 1.0 mm) pinout [2]
Figure 2. 48-pin TSOP I (12 × 18.4 × 1 mm) pinout [2]
WE
A
11
A
10
A
6
A
0
A
3
CE
I/O
10
I/O
8
I/O
9
A
4
A
5
I/O
11
I/O
13
I/O
12
I/O
14
I/O
15
V
SS
A
9
A
8
OE
A
7
I/O
0
BHE
NC
A
17
A
2
A
1
BLE
I/O
2
I/O
1
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
A
15
A
14
A
13
A
12
A
19
A
18
NC
326
5
41
D
E
B
A
C
F
G
H
A
16
NC
V
CC
V
CC
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A
4
A
3
A
2
A
1
A
0
NC
CE
I/O
0
I/O
1
I/O
2
I/O
3
V
DD
GND
I/O
4
I/O
5
I/O
6
I/O
7
WE
NC
A
19
A
18
A
17
A
16
A
15
A
5
A
6
A
7
A
8
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
GND
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
NC
A
9
A
10
A
11
A
12
A
13
A
14
Product Portfolio
Product Range VCC Range (V) Speed
(ns)
Current Consumption
Operating ICC (mA) Standby, ISB2 (mA)
f = fmax
Typ[3] Max Typ[3] Max
CY7C1061G30 Automotive 2.2 V–3.6 V 10 90 160 20 50
Notes
2. NC pins are not connected internally to the die.
3. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC =3V, T
A = 25 °C.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 4 of 18
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage temperature ..................................... –65 C to +150 C
Ambient temperature
with power applied ........................................ –55 C to +125 C
Supply voltage on VCC relative to GND ........... –0.5 V to +6.0 V
DC voltage applied to outputs
in High-Z State [4] .....................................–0.5 V to VCC + 0.5 V
DC input voltage [4] ..................................–0.5 V to VCC + 0.5 V
Current into outputs (LOW) .............................................20 mA
Static discharge voltage
(MIL-STD-883, Method 3015) ......................................> 2001 V
Latch-up current .........................................................> 140 mA
Operating Range
Grade Ambient Temperature VCC
Automotive-E –40 C to +125 C 2.2 V to 3.6 V
DC Electrical Characteristics
Over the operating range of –40 C to 125 C
Parameter Description Test Conditions 10 ns Unit
Min Typ [5] Max
VOH Output HIGH
voltage
2.2 V to 2.7 V VCC = Min, IOH = –1.0 mA 2.0 – – V
2.7 V to 3.6 V VCC = Min, IOH = –4.0 mA 2.2 – –
VOL Output LOW
voltage
2.2 V to 2.7 V VCC = Min, IOL = 2 mA – – 0.4 V
2.7 V to 3.6 V VCC = Min, IOL = 8 mA – – 0.4
VIH[4] Input HIGH
voltage
2.2 V to 2.7 V – 2.0 – VCC + 0.3 V
2.7 V to 3.6 V – 2.0 – VCC + 0.3
VIL[4] Input LOW
voltage
2.2 V to 2.7 V – –0.3 – 0.6 V
2.7 V to 3.6 V – –0.3 – 0.8
IIX Input leakage current GND < VIN < VCC –5.0 – +5.0 A
IOZ Output leakage current GND < VOUT < VCC, Output disabled –5.0 – +5.0 A
ICC Operating supply current VCC = Max, IOUT = 0 mA,
CMOS levels
f = fMAX = 1/tRC –90.0160.0mA
ISB1 Automatic CE power down
current – TTL inputs
Max VCC, CE > VIH,
VIN > VIH or VIN < VIL, f = fMAX
– – 60.0 mA
ISB2 Automatic CE power down
current – CMOS inputs
Max VCC, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V, f = 0
– 20.0 50.0 mA
Notes
4. VIL (min) = –2.0 V and VIH (max) = VCC +2 V for pulse durations of less than 2 ns.
5. Typical values are included only for reference and are not guaranteed or tested. Typical values are measured at VCC =3V, T
A = 25 °C.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 5 of 18
Capacitance
Parameter [6] Description Test Conditions All Packages Unit
CIN Input capacitance TA = 25 C, f = 1 MHz, VCC = VCC(typ) 10 pF
COUT I/O capacitance 10 pF
Thermal Resistance
Parameter [6] Description Test Conditions 48-ball VFBGA 48-pin TSOP I Unit
JA
Thermal resistance
(junction to ambient)
Still air, soldered on a 3 × 4.5 inch, four
layer printed circuit board
31.50 57.99 C/W
JC
Thermal resistance
(junction to case)
15.75 13.42 C/W
AC Test Loads and Waveforms
Figure 3. AC Test Loads and Waveforms [7]
90%
10%
VHIGH
GND
90%
10%
All Input Pulses
VCC
Output
5 pF*
* Including
JIG and
Scope (b)
R1
R2
Rise Time: Fall Time:
> 1 V/ns
(c)
Output
50
Z
0
= 50
V
TH
30 pF*
* Capacitive load consists
of all components of the
test environment
High-Z Characteristics:
(a)
> 1 V/ns
Parameters 3.0 V Unit
R1 317
R2 351
VTH 1.5 V
VHIGH 3V
Notes
6. Tested initially and after any design or process changes that may affect these parameters.
7. Full-device AC operation assumes a 100-µs ramp time from 0 to VCC(min) and 100-µs wait time after VCC stabilizes to its operational value.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 6 of 18
Data Retention Characteristics
Over the operating range of –40 C to 125 C
Parameter Description Conditions Min Max Unit
VDR VCC for data retention – 1.0 – V
ICCDR
Data retention current VCC = VDR, CE > VCC – 0.2 V,
VIN > VCC – 0.2 V or VIN < 0.2 V
–50.0mA
tCDR[8] Chip deselect to data retention
time
–0–ns
tR[8] Operation recovery time VCC > 2.2 V 10.0 – ns
Data Retention Waveform
Figure 4. Data Retention Waveform [9]
Notes
8. Tested initially and after any design or process changes that may affect these parameters.
9. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 s or stable at VCC(min) > 100 s.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 7 of 18
AC Switching Characteristics
Over the operating range of –40 C to 125 C
Parameter [10] Description 10 ns Unit
Min Max
Read Cycle
tPOWER VCC(stable) to the first access[11] 100.0 - s
tRC Read cycle time 10.0 – ns
tAA Address to data – 10.0 ns
tOHA Data hold from address change 3.0 – ns
tACE CE LOW to data – 10.0 ns
tDOE OE LOW to data – 5.0 ns
tLZOE OE LOW to low-Z [12, 13] 0–ns
tHZOE OE HIGH to high-Z [12, 13] –5.0ns
tLZCE CE LOW to low-Z [12, 13] 3.0 – ns
tHZCE CE HIGH to high-Z [12, 13] –5.0ns
tPU CE LOW to power-up [14] 0–ns
tPD CE HIGH to power-down [14] –10.0ns
tDBE Byte enable to data valid – 5.0 ns
tLZBE Byte enable to low-Z [12, 13] 0–ns
tHZBE Byte disable to high-Z [12, 13] –6.0ns
Write Cycle [15, 16]
tWC Write cycle time 10.0 – ns
tSCE CE LOW to write end 7.0 – ns
tAW Address setup to write end 7.0 – ns
tHA Address hold from write end 0–ns
tSA Address setup to write start 0 – ns
tPWE WE pulse width 7.0 – ns
tSD Data setup to write end 5.0 – ns
tHD Data hold from write end 0 – ns
tLZWE WE HIGH to low-Z [12, 13] 3.0 – ns
tHZWE WE LOW to high-Z [12, 13] –5.0ns
tBW Byte Enable to write end 7.0 – ns
Notes
10. Test conditions assume signal transition time (rise/fall) of 3 ns or less, timing reference levels of 1.5 V (for VCC > 3 V) and VCC/2 (for VCC < 3 V), and input pulse levels
of 0 to 3 V (for VCC > 3 V) and 0 to VCC (for VCC < 3V). Test conditions for the read cycle use the output loading shown in part (a) of Figure 3 on page 5, unless specified otherwise.
11. tPOWER gives the minimum amount of time that the power supply is at stable VCC until the first memory access is performed.
12. tHZOE, tHZCE, tHZWE,and tHZBE are specified with a load capacitance of 5 pF, as shown in part (b) of Figure 3 on page 5. Hi-Z, Lo-Z transition is measured 200 mV from steady state voltage.
13. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
14. These parameters are guaranteed by design and are not tested.
15. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL and BHE, or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
16. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 8 of 18
Switching Waveforms
Figure 5. Read Cycle No. 1 of CY7C1061G (Address Transition Controlled) [17, 18]
Figure 6. Read Cycle No. 2 (OE Controlled) [18, 19]
ADDRESS
DATA I/O PREVIOUS DATAOUT
VALID DATAOUT VALID
tRC
tOHA
tAA
tRC
tHZCE
tPD
tACE
tDOE
tLZOE
tDBE
tLZBE
tLZCE
tPU
HIGH IMPEDANCE DATAOUT VALID HIGH
IMPEDANCE
ADDRESS
CE
OE
BHE/
BLE
DATA I/O
VCC
SUPPLY
CURRENT
tHZOE
tHZBE
ISB
Notes
17. The device is continuously selected, OE = VIL, CE = VIL, BHE or BLE or both = VIL.
18. WE is HIGH for read cycle.
19. Address valid prior to or coincident with CE LOW transition.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 9 of 18
Figure 7. Write Cycle No. 1 (CE Controlled) [20, 21]
Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [20, 21, 23]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/
BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
Note 22
ADDRESS
CE
DATA I/O
tWC
tSCE
tHD
tSD
tBW
BHE/
BLE
tAW tHA
tSA tPWE
tLZWE
tHZWE
WE
DATAIN VALID
Note 22
Notes
20. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
21. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
22. During this period, the I/Os are in output state. Do not apply input signals.
23. The minimum write pulse width for Write Cycle No. 2 (WE Controlled, OE LOW) should be sum of tHZWE and tSD.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 10 of 18
Figure 9. Write Cycle No. 3 (WE Controlled) [24, 25]
Switching Waveforms (continued)
ADDRESS
CE
WE
BHE/BLE
DATA I/O
OE
tWC
tSCE
tAW
tSA
tPWE
tHA
tBW
tHD
tHZOE tSD
DATAIN VALID
Note 26
Notes
24. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
25. Data I/O is in high impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
26. During this period the I/Os are in output state. Do not apply input signals.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 11 of 18
Figure 10. Write Cycle No. 3 (BLE or BHE Controlled) [27, 28]
Switching Waveforms (continued)
DATAIN VALID
ADDRESS
CE
WE
DATA I/O
tWC
tSCE
tAW
tSA
tBW
tHA
tHD
tHZWE tSD
BHE/
BLE
tPWE
tLZWE
Note 29
Notes
27. The internal write time of the memory is defined by the overlap of WE = VIL, CE = VIL, and BHE or BLE = VIL. These signals must be LOW to initiate a write, and the
HIGH transition of any of these signals can terminate the operation. The input data setup and hold timing should be referenced to the edge of the signal that terminates
the write.
28. Data I/O is in high-impedance state if CE = VIH, or OE = VIH or BHE, and/or BLE = VIH.
29. During this period, the I/Os are in output state. Do not apply input signals.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 12 of 18
Truth Table
CE OE WE BLE BHE I/O0–I/O7I/O8–I/O15 Mode Power
HX
[30] X[30] X[30] X[30] High Z High Z Power down Standby (ISB)
L L H L L Data out Data out Read all bits Active (ICC)
L L H L H Data out High Z Read lower bits only Active (ICC)
L L H H L High Z Data out Read upper bits only Active (ICC)
L X L L L Data in Data in Write all bits Active (ICC)
L X L L H Data in High Z Write lower bits only Active (ICC)
L X L H L High Z Data in Write upper bits only Active (ICC)
L H H X X High Z High Z Selected, outputs disabled Active (ICC)
L X X H H High Z High Z Selected, outputs disabled Active (ICC)
Note
30. The input voltage levels on these pins should be either at VIH or VIL.
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 13 of 18
Ordering Code Definitions
Ordering Information
Speed
(ns) Voltage Range Ordering Code Package
Diagram
Package Type
(all Pb-free) Operating Range
10 2.2 V–3.6 V CY7C1061G30-10BV1XE 51-85150 48-ball VFBGA
(6 × 8 × 1.0 mm) (Pb-free)
Automotive-E
CY7C1061G30-10ZXE 51-85183 48-pin TSOP I
(12 × 18.4 × 1.0 mm) (Pb-free)
Temperature Range: E = Automotive-E (–40 C to 125 C)
Pb-free
Chip enables: 1 = Single Chip Enable
Package Type: XX = BV or Z
BV = 48-ball VFBGA; Z = 48-pin TSOP I
Speed: 10 ns
Voltage Range: 30 = 2.2 V–3.6 V
Revision Code “G”: Process Technology – 65 nm
Data Width: 1 = × 16-bits
Density: 06 = 16-Mbit
Family Code: 1 = Fast Asynchronous SRAM family
Technology Code: C = CMOS
Marketing Code: 7 = SRAM
Company ID: CY = Cypress
CCY 1 -10 X706 G1 XX
XX 1E
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 14 of 18
Package Diagrams
Figure 11. 48-ball VFBGA (6 × 8 × 1.0 mm) BV48/BZ48 Package Outline, 51-85150
Figure 12. 48-pin TSOP I (12 × 18.4 × 1.0 mm) Z48A Package Outline, 51-85183
51-85150 *H51-85150 *H
51-85183 *D
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 15 of 18
Acronyms Document Conventions
Units of Measure
Acronym Description
BHE Byte High Enable
BLE Byte Low Enable
CE Chip Enable
CMOS Complementary Metal Oxide Semiconductor
I/O Input/Output
OE Output Enable
SRAM Static Random Access Memory
TSOP Thin Small Outline Package
TTL Transistor-Transistor Logic
VFBGA Very Fine-Pitch Ball Grid Array
WE Write Enable
Symbol Unit of Measure
°C degree Celsius
MHz megahertz
Amicroampere
smicrosecond
mA milliampere
mm millimeter
ns nanosecond
ohm
%percent
pF picofarad
Vvolt
Wwatt
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 16 of 18
Document History Page
Document Title: CY7C1061G Automotive, 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84821
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
** 3825225 MEMJ 11/29/2012 New data sheet.
*A 4003550 NILE 05/20/2013 Updated Document Title to read as “CY7C1061G Automotive, 16-Mbit (1 M
words × 16 bit) Static RAM with Error-Correcting Code (ECC)”.
Updated Features.
Updated Functional Description.
Removed “Logic Block Diagram – CY7C1061GE”.
Updated Logic Diagram for Single Chip Enable.
Updated Pin Configurations:
Updated Pin diagram to have BV1XE without ERR pin
Updated Product Portfolio.
Updated Operating Range.
Updated Capacitance.
Updated Thermal Resistance.
Updated Data Retention Characteristics.
Updated AC Switching Characteristics:
Removed 12 ns, 17 ns speed bin related information and included 10 ns speed
bin related information.
Updated Switching Waveforms.
Removed “ERR Output – CY7C1061GE”.
Updated Package Diagrams:
Added 48-pin TSOP I Package Diagram (Figure 11).
*B 4292074 MEMJ 02/28/2014 Updated Features:
Mentioned frequency of measurement for ICC (typical).
Updated Functional Description:
Replaced “an error detection” with “a single-bit error detection”.
Added Note 1 (for ECC) and referred the same note in CY7C1061G.
Updated Product Portfolio:
Replaced CY7C1061G with CY7C1061G30.
Updated Operating Range:
Replaced Automotive with Automotive-E.
Updated DC Electrical Characteristics:
Added typical value for ICC parameter (90 mA).
Added typical value for ISB2 parameter (20 mA).
Added Note 5 and referred the same note in “Typ” column.
Updated AC Switching Characteristics:
Added tPOWER parameter and its details.
Added Note 11 and referred the same note in description of tPOWER parameter.
Added Note 13 and referred the same note in description of tLZOE, tHZOE, tLZCE,
tHZCE, tLZBE, tHZBE, tLZWE, and tHZWE parameters.
Added Note 16 and referred the same note in “Write Cycle”.
Updated Switching Waveforms:
Added Note 22 and referred the same note in Figure 7 and Figure 8.
Added Note 23 and referred the same note in Figure 8.
Added Figure 9.
Added Note 26 and referred the same note in Figure 9 (to indicate that I/Os
are in output state).
Added Note 29 and referred the same note in Figure 10 (to indicate that I/Os
are in output state).
CY7C1061G Automotive
Document Number: 001-84821 Rev. *H Page 17 of 18
*B (cont.) 4292074 MEMJ 02/28/2014 Updated Truth Table:
Added Note 30 and referred the same note in “X” corresponding to Power down
mode.
Added condition to place outputs in disable state by making both BHE and BLE
HIGH.
Added Errata.
Updated to new template.
*C 4330547 AJU 04/02/2014 No technical updates.
*D 4397546 AJU 06/03/2014 Updated AC Switching Characteristics:
Updated Note 12 (Removed tLZOE, tLZCE, tLZWE, and tLZBE; and added Hi-Z,
Lo-Z transition).
*E 4469360 NILE 09/18/2014 No technical updates.
*F 4576640 VINI 11/21/2014 No technical updates.
*G 4800949 NILE 09/30/2015 Updated Logic Block Diagram – CY7C1061G.
Updated Package Diagrams:
spec 51-85183 – Changed revision from *C to *D.
Removed Errata.
Updated to new template.
*H 4983893 NILE 10/28/2015 Changed status from Preliminary to Final.
Document History Page (continued)
Document Title: CY7C1061G Automotive, 16-Mbit (1 M words × 16 bit) Static RAM with Error-Correcting Code (ECC)
Document Number: 001-84821
Rev. ECN No. Orig. of
Change
Submission
Date Description of Change
Document Number: 001-84821 Rev. *H Revised October 28, 2015 Page 18 of 18
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All products and company names mentioned in this document
may be the trademarks of their respective holders.
CY7C1061G Automotive
© Cypress Semiconductor Corporation, 2012-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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