LM49450SQ/NOPB - Texas Instruments

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

LM49450 Boomer ™ I

S Input, 2.5W/Channel, Low EMI, Stereo, Class D Audio Sub-

System with Ground Referenced Headphone Amplifier, 3D Enhancement, and Headphone

Sense

Check for Samples: LM49450

1FEATURES KEY SPECIFICATIONS

23• 24–Bit Stereo DAC • SNR at Headphone Output: 102dBA (typ)

• Stereo Filterless Class D Operation • Speaker Amplifier Efficiency at 3.6V,

650mW/Channel into 8Ω: 87% (typ)

• Selectable Spread Spectrum Mode Reduces

EMI • Speaker Amplifier Efficiency at 5V,

1.1W/Channel into 8Ω: 80% (typ)

• Ground Referenced Headphone Amplifiers

with 100dB SNR • Quiescent Power Supply Current Line Inputs:

• I2S Compatible Audio Interface – Speaker Mode at LSVDD = 3.6V: 7.5mA

(typ)

• Audio Sample Rates up to 192kHz – Headphone Mode at HPVDD = 2.5V: 5.3mA

• TI’s 3D Enhancement (typ)

• 32-Step Digital Volume Control • Output Power/Channel Speaker at LSVDD = 5V:

• I2C-Compatible Control Interface – RL= 4Ω, THD+N ≤10%: 2.5W (typ)

• Headphone Sense Input – RL= 8Ω, THD+N ≤1%: 1.25W (typ)

• Stereo Analog Line Inputs • Headphone at HPVDD = 2.5V:

• Output Short Circuit Protection – RL= 16Ω, THD+N ≤1%: 34mW (typ)

• Thermal Overload Protection – RL= 32Ω, THD+N ≤1%: 36mW (typ)

• Minimum External Components • PSRR at 1kHz

• Click and Pop Suppression – Speaker Mode: 67dB ( typ)

• Micro-Power Shutdown – Headphone Mode: 77dB (typ)

• Available in Space-Saving 32-Pin WQFN • Shutdown current: 0.02μA (typ)

Package

DESCRIPTION

APPLICATIONS The LM49450 is a fully integrated audio subsystem

• Portable Media Players designed for portable media player applications. The

• Portable Navigation Devices LM49450 combines a 24-bit I2S digital-to-analog

converter (DAC), 2.5W/channel stereo Class D

• Multi-Media Monitors speaker drivers, 36mW stereo ground referenced

• Laptops headphone drivers, volume control, and TI’s unique

• Portable Gaming Devices 3D sound enhancement into a single device.

• Mobile Handsets

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2is a trademark of ~ Texas Instruments.

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

REF

CPGND

I2C

INTERFACE

I2C

BUS

VDD

MCLK

I2S_CLK

I2S_SDI

I2S_WS

SDA

SCL

DGND

HPR

HPL

LSGND

RLS-

RLS+

LLS-

LLS+

LSVDD

VDD

HPS

CREF

CLASS D

CLASS

INL

INR

24-BIT

STEREO

DAC

32-STEP

VOLUME

CONTROL

CHARGE PUMP

C1P

C1N

HPVDD

HPGND

CPVDD

HPVSS

OSCILLATOR

HPVDD

I2S

INTERFACE 3D

PROCESSOR

BYPASS

CBYPASS

GND

IOVDD DVDD

1.8V to 4.5V2.7V to 4.5V

IOVDD DVDD

2.7V to 5.5V

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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DESCRIPTION (CONTINUED)

The filterless Class D amplifiers deliver 1.25W/channel into an 8Ωload with <1% THD+N with a 5V supply. The

LM49450 offers two logic selectable modulation schemes, fixed frequency mode, and an EMI reducing spread

spectrum mode. The 36mW/channel headphone drivers feature TI’s ground referenced architecture that creates

a ground-referenced output from a single supply, eliminating the need for bulky and expensive DC-blocking

capacitors, saving space and minimizing system cost. A headphone sense input (HPS) automatically detects the

presence of a headphone, and configures the device accordingly.

The LM49450 stereo, 24-bit DAC supports a wide range of sample rates (including 192kHz, 96kHz, 48kHz, and

44.1kHz). The digital audio signal path features better than 100dB SNR, and low 0.05% THD+N when measured

at the headphone outputs. The flexible 3-wire I2S interface supports left or right justified audio data.

The LM49450 features separate 32-step volume control for the headphones and speaker outputs. 3D

enhancement, mode selection, shutdown control, and volume are controlled through an I2C compatible interface.

Output short circuit and thermal overload protection prevent the device from being damaged during fault

conditions. Superior click and pop suppression eliminates audible transients on power-up/down and during

shutdown. The LM49450 is available in a space saving 32-pin WQFN package.

Typical Application

Figure 1. Typical Audio Amplifier Application Circuit

Product Folder Links: LM49450

C1P

CPGND

SDA

DGND

I2S_WS

I2S_SDI

MCLK

I2S_CLK

SCL

DVDD

IOVDD

GND

REF

INR

INL

VDD

BYPASS

LSVDD

LLS+

LLS-

LSGND

RLS-

RLS+

LSVDD

CPVDD

HPGND

HPS

HPR

HPL

HPVDD

HPVSS

C1N

LM49450

www.ti.com

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Connection Diagram

Figure 2. RTV Package Top View

5mm x 5mm x 0.8mm

Package Number RTV0032A

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Product Folder Links: LM49450

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Absolute Maximum Ratings(1)(2)(3)

Supply Voltage(1) 6.0V

Storage Temperature −65°C to +150°C

Input Voltage –0.3V to VDD +0.3V

Power Dissipation(4) Internally Limited

ESD Susceptibility(5) 2000V

ESD Susceptibility(6) 200V

Junction Temperature (TJMAX) 150°C

Thermal Resistance

θJC 2.4°C/W

θJA 28.4°C/W

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All

voltages are measured with respect to the ground pin, unless otherwise specified

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(4) The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX ,θJA, and the ambient temperature,

TA. The maximum allowable power dissipation is PDMAX = (TJMAX – TA) / θJA or the number given in Absolute Maximum Ratings,

whichever is lower.

(5) Human body model, applicable std. JESD22-A114C.

(6) Machine model, applicable std. JESD22-A115-A.

Operating Ratings(1)(2)

Temperature Range

TMIN ≤TA≤TMAX −40°C ≤TA≤+85°C

Supply Voltage 2.7V ≤VDD ≤5.5V

(VDD, LSVDD)

Headphone Supply Voltage 1.8V ≤VDD ≤2.7V

(CPVDD, HPVDD)

Digital Core Supply Voltage (DVDD) 2.7V ≤DVDD ≤4.5V

Digital IO Supply Voltage (IOVDD) 1.8V ≤IOVDD ≤4.5V

(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of

device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or

other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating

Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All

voltages are measured with respect to the ground pin, unless otherwise specified

(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

Product Folder Links: LM49450

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Electrical Characteristics VDD = LSVDD = 3.6V, HPVDD = CPVDD = 2.5V(1)(2)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, C1= C2= 2.2μF, unless

otherwise specified. Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

DVDD = 2.7V, fS= 48kHz,

DIDD Digital Core Supply Current 9 11.2 mA (max)

fMCLK = 12.28MHz

Digital Current 0.03 1 μA (max)

ISD Shutdown Supply Current Analog Current 0.02 1 μA (max)

SPEAKER AMPLIFIERS (Headphone Amplifiers Disabled, HPS = 0)

fS= 48kHz, DAC Active, No Load 9.8 13 mA (max)

IDDLS Analog Supply Current Line Inputs Active, No Load 7 10 mA (max)

DAC Active 8 45 mV (max)

VOS Output Offset Voltage Line Inputs Active 8 mV (max)

RL= 4Ω, f = 1kHz

THD+N = 1% 1 W

THD+N = 10% 1.2 W

POUT Output Power RL= 8Ω, f = 1kHz

THD+N = 1% 625 525 mW (min)

THD+N = 10% 725 W

PO= 300mW, f = 1kHz, RL= 8Ω

THD+N Total Harmonic Distortion DAC Active 0.06 %

Line Inputs Active 0.07 %

VRIPPLE = 200mVP-P, f = 1kHz

DAC Active, Internal Reference 59 45 dB (min)

PSRR Power Supply Rejection Ratio DAC Active, External Reference 62 dB

Line Inputs Active 67 dB

PO= 650, f = 1kHz

ηEfficiency 87 %

RL= 8Ω

PO= 500mW, f = 1kHz, RL= 8Ω

DAC Active, 81 dB

Line Inputs Active 77 dB

Xtalk Crosstalk PO= 500mW, f = 10kHz, RL= 8Ω

DAC Active, 60 dB

Line Inputs Active 60 dB

PO= 500mW, f = 1kHz, A-weighted

DAC Active, Internal Reference 89 dB

SNR Signal to Noise Ratio DAC Active, External Reference 92 dB

Line Inputs Active 90 dB

Maximum Gain Setting, Line Inputs 22.5 dB (min)

23.6

Active 24.1 dB (max)

AVDigitally Controlled Gain Level Minimum Gain Setting, Line Inputs –49 dB (min)

–48

Active –46 dB (max)

Mute Mute Attenuation Line Inputs Active –91 dB

Channel-to-Channel Gain

ΔACH-CH 0.3 dB

Matching

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) RLis a resistive load in series with two inductors to simulate an actual speaker load. For RL= 8Ω, the load is 15µH + 8Ω+15µH. For RL

= 4Ω, the load is 15µH + 4Ω+ 15µH.

(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of

product characterization and are not ensured.

(4) Datasheet min/max specification limits are specified by test or statistical analysis.

Product Folder Links: LM49450

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Electrical Characteristics VDD = LSVDD = 3.6V, HPVDD = CPVDD = 2.5V(1)(2) (continued)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, C1= C2= 2.2μF, unless

otherwise specified. Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

Input Referred, A-weighted

DAC Active, Internal Reference 43.5 μV

εOS Output Noise DAC Active, External Reference 45.4 μV

Line Inputs Active 40 μV

tON Turn-On Time 27 ms

tOFF Turn-Off Time 1 ms

HEADPHONE AMPLIFIERS (Speaker Amplifiers Disabled, HPS = 1)

fS= 48kHz, DAC active 7.2 8.25 mA (max)

IDDHP Analog Supply Current Line Inputs Active 5.3 6.5 mA (max)

DAC active, AV= –6dB 7 mV

VOS Output Offset Voltage 30

Line Inputs Active, , AV= –6dB 5 mV (max)

RL= 16Ω, f = 1kHz

THD+N = 1%, Single Channel 66 mW

THD+N = 1%, Two Channels in 34 mW

Phase

POOutput Power RL= 32Ω, f = 1kHz

THD+N = 1%, Single Channel 49 42 mW (min)

THD+N = 1%, Two Channels in 36 27 mW (min)

Phase

f = 1kHz, DAC Active

THD+N Total Harmonic Distortion RL= 16Ω, PO= 5mW 0.05 %

RL= 32Ω, PO= 5mW 0.03 %

VRIPPLE = 200mVP-P, f = 1kHz

DAC Active, Internal Reference 71.2 56 dB (min)

PSRR Power Supply Rejection Ratio DAC Active, External Reference 71.3 dB

Line Inputs Active 76.9 dB

PO= 5mW, f = 1kHz, RL= 32Ω

DAC Active, 82 dB

Line Inputs Active 79 dB

Xtalk Crosstalk PO= 5mW, f = 10kHz, RL= 32Ω

DAC Active, 78 dB

Line Inputs Active 76 dB

PO= 5mW, f = 1kHz, A-weighted

DAC Active, Internal Reference 99 dB

SNR Signal to Noise Ratio DAC Active, External Reference 102 dB

Line Inputs Active 98 dB

Maximum Gain Setting, Line Inputs 17.0 dB (min)

17.8

Active 18.5 dB (max)

AVDigitally Controlled Gain Level Minimum Gain Setting, Line Inputs –56 dB (min)

–53.8

Active –52 dB (max)

Mute Mute Attenuation Line Inputs Active –102 dB

Channel-to-Channel Gain

ΔACH-CH 0.3 dB

Matching Input Referred, A-weighted

DAC Active, Internal Reference 10 μV

εOS Output Noise DAC Active, External Reference 10 μV

Line Inputs Active 10 μV

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Electrical Characteristics VDD = LSVDD = 3.6V, HPVDD = CPVDD = 2.5V(1)(2) (continued)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, C1= C2= 2.2μF, unless

otherwise specified. Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

Full-Scale Headphone Amplifier mVRMS

VOUT_FS RL= No Load 942 850

Output Voltage (min)

tON Turn-On Time 27 ms

tOFF Turn-Off Time 1 ms

HEADPHONE SENSE INPUT (HPS)

VIH Input High Voltage 1 V

VIL Input Low Voltage 0.6 V

DIGITAL INTERFACE

VIH Input High Voltage 2.8 V (min)

VIL Input Low Voltage 0.8 V (max)

VOH Output High Voltage 2 V (min)

VOL Output Low Voltage 1 V (max)

Electrical Characteristics VDD = LSVDD = 5.0V(1)(2)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified.

Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

SPEAKER AMPLIFIERS (Headphone Amplifiers Disabled, HPS = 0)

fS= 48kHz, DAC Active 14 18 mA (max)

IDDLS Analog Supply Current Line Inputs Active 10.4 16 mA (max)

DAC Voltage 15 50 mV (max)

VOS Output Offset Voltage AV = 0dB, Line Inputs Active 12 48 mV (max)

RL= 4Ω, f = 1kHz

THD+N = 1% 1.9 W

THD+N = 10% 2.5 W

POUT Output Power RL= 8Ω, f = 1kHz

THD+N = 1% 1.25 mW (min)

THD+N = 10% 1.54 W

PO= 635mW, f = 1kHz, RL= 8Ω

THD+N Total Harmonic Distortion DAC Active 0.06 %

Line Inputs Active 0.04 %

VRIPPLE = 200mVP-P, f = 1kHz

DAC Active, Internal Reference 60 dB

PSRR Power Supply Rejection Ratio DAC Active, External Reference 60 dB

Line Inputs Active 70 dB

PO= TBDmW, f = 1kHz

ηEfficiency 80 %

RL= 8Ω

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) RLis a resistive load in series with two inductors to simulate an actual speaker load. For RL= 8Ω, the load is 15µH + 8Ω+15µH. For RL

= 4Ω, the load is 15µH + 4Ω+ 15µH.

(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of

product characterization and are not ensured.

(4) Datasheet min/max specification limits are specified by test or statistical analysis.

Product Folder Links: LM49450

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Electrical Characteristics VDD = LSVDD = 5.0V(1)(2) (continued)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified.

Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

PO= 500mW, f = 1kHz, RL= 8Ω

DAC Active, 74 dB

Line Inputs Active 79 dB

Xtalk Crosstalk PO= 500mW, f = 10kHz, RL= 8Ω

DAC Active, 60 dB

Line Inputs Active 60 dB

PO= 500mW, f = 1kHz, A-weighted

DAC Active, Internal Reference 88 dB

SNR Signal to Noise Ratio DAC Active, External Reference 89 dB

Line Inputs Active 98 dB

Maximum Gain Setting, Line Inputs 22.5 dB (min)

24.2

Active 24.2 dB (max)

AVDigitally Controlled Gain Level Minimum Gain Setting, Line Inputs –49 dB (min)

–48

Active –46 dB (max)

Mute Mute Attenuation Line Inputs Active –92 dB

Channel-to-Channel Gain

ΔACH-CH 0.3 dB

Matching Input Referred, A-weighted

DAC Active, Internal Reference 60 μV

εOS Output Noise DAC Active, External Reference 85 μV

Line Inputs Active 40 μV

tON Turn-On Time 27 ms

tOFF Turn-Off Time 1 ms

Timing Characteristics(1)(2)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified.

Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

AUDIO INTERFACE TIMING

tMCLKL MCLK Pulse Width Low 16 ns (min)

tMCLKH MCLK Pulse Width High 16 ns (min)

tMCLKY MCLK Period 32 ns (min)

tBCLKR BCLK Rise Time 3 ns (max)

tBCLKCF BCLK Fall Time 3 ns (max)

tBCLKDS BCLK Duty Cycle 50 %

LRC Propagation Delay from ns (max)

tDL 10

BCLK falling edge

DATA Setup Time to BCLK Rising 10 ns (min)

tDST Edge

(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as

otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and

are not ensured.

(2) RLis a resistive load in series with two inductors to simulate an actual speaker load. For RL= 8Ω, the load is 15µH + 8Ω+15µH. For RL

= 4Ω, the load is 15µH + 4Ω+ 15µH.

(3) Typical values represent most likely parametric norms at TA= +25ºC, and at the Recommended Operation Conditions at the time of

product characterization and are not ensured.

(4) Datasheet min/max specification limits are specified by test or statistical analysis.

Product Folder Links: LM49450

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Timing Characteristics(1)(2) (continued)

The following specifications apply for Headphone: AV= 0dB, RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified.

Limits apply for TA= 25°C. LM49450 Units

Symbol Parameter Conditions (Limits)

Typical(3) Limit(4)

DATA Hold Time from BCLK 10 ns (min)

tDHT Rising Edge

CONTROL INTERFACE TIMING

SCLK Frequency 400 kHz (max)

Hold Time (repeated START 0.6 μs (min)

1Condition)

2 Clock Low Time 1.3 μs (min)

3 Clock High Time 600 ns (min)

Setup Time for a Repeated 600 ns (min)

4START Condition

Data Hold Time Output 300 ns (min)

50 ns (min)

Input 900 ns (max)

6 Data Setup Time 100 ns (min)

20+0.1CBns (min)

7 Rise Time of SDA and SCL 300 ns (max)

Fall Time of SDA and SCL 15+0.1CBns (min)

8300 ns (max)

9 Setup Time for STOP Condition 600 ns (min)

Bus Free time Between a STOP 1.3 μs ( min)

10 and START Condition

Bus Capacitance 10 pF (min)

CB200 pF (max)

PIN DESCRIPTIONS

Pin Name Description

1 C1P Charge Pump Flying Capacitor Positive Terminal

2 CPGND Charge Pump Ground

3 SDA I2C Serial Data Input

4 DGND Digital Ground

5 I2S_WS I2S Word Select Input

6 I2S_SDI I2S Serial Data Input

7 I2S_CLK I2S Clock Input

8 MCLK Master Clock

9 SCL I2C Clock Input

10 DVDD Digital Core Power Supply

11 IOVDD Digital Interface Power Supply

12 GND Analog Ground

13 REF DAC Reference Bypass

14 INR Right Channel Analog Input

15 INL Left Channel Analog Input

16 VDD Analog Power Supply

17 BYPASS Mid-Rail Bias Bypass

18, 24 LSVDD Speaker Power Supply

19 LLS+ Left Channel Non-Inverting Speaker Output

20 LLS- Left Channel Inverting Speaker Output

21 LSGND Speaker Ground

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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PIN DESCRIPTIONS (continued)

Pin Name Description

22 RLS- Right Channel Inverting Speaker Output

23 RLS+ Right Channel Non-Inverting Speaker Output

25 HPGND Headphone Amplifier Ground

26 HPS Headphone Sense Input

27 HPR Right Channel Headphone Amplifier Output

28 HPVDD Headphone Amplifier Power Supply

29 HPL Left Channel Headphone Amplifier Output

30 HPVSS Charge Pump Output and Headphone Amplifier Negative Power Supply.

31 C1N Charge Pump Flying Capacitor Negative Terminal

32 CPVDD Charge Pump Power Supply

Product Folder Links: LM49450

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

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100

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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THD+N (%)

0.001

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FREQUENCY (Hz)

THD+N (%)

LM49450

www.ti.com

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Typical Performance Characteristics

THD+N vs Frequency THD+N vs Frequency

VDD = 3.0V, POUT = 50mW, RL= 4ΩVDD = 3.0V, POUT = 150mW, RL= 8Ω

DAC Input, Internal Reference, Speaker Mode DAC Input, Internal Reference, Speaker Mode

Figure 3. Figure 4.

THD+N vs Frequency THD+N vs Frequency

VDD = 3.0V, POUT = 50mW, RL= 4ΩVDD = 3.0V, POUT = 150mW, RL= 8Ω

DAC Input, External Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 5. Figure 6.

THD+N vs Frequency THD+N vs Frequency

VDD = 3.0V, POUT = 100mW, RL= 4ΩVDD = 3.0V, POUT = 80mW, RL= 8Ω

Analog Input, Speaker Mode Analog Input, Speaker Mode

Figure 7. Figure 8.

Product Folder Links: LM49450

0.001

0.01

0.1

100

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FREQUENCY (Hz)

THD+N (%)

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THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

www.ti.com

Typical Performance Characteristics (continued)

THD+N vs Frequency THD+N vs Frequency

VDD = 3.6V, POUT = 100mW, RL= 4ΩVDD = 3.6V, POUT = 100mW, RL= 4Ω

DAC Input, Internal Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 9. Figure 10.

THD+N vs Frequency THD+N vs Frequency

VDD = 3.6V, POUT = 100mW, RL= 8ΩVDD = 3.6V, POUT = 200mW, RL= 8Ω

Analog Input, Speaker Mode DAC Input, Internal Reference, Speaker Mode

Figure 11. Figure 12.

THD+N vs Frequency THD+N vs Frequency

VDD = 3.6V, POUT = 200mW, RL= 8ΩVDD = 3.6V, POUT = 100mW, RL= 4Ω

DAC Input, External Reference, Speaker Mode Analog Input, Speaker Mode

Figure 13. Figure 14.

Product Folder Links: LM49450

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

THD+N (%)

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FREQUENCY (Hz)

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0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

LM49450

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Typical Performance Characteristics (continued)

THD+N vs Frequency THD+N vs Frequency

VDD = 5.0V, POUT = 750mW, RL= 4ΩVDD = 5.0V, POUT = 750mW, RL= 4Ω

DAC Input, Internal Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 15. Figure 16.

THD+N vs Frequency THD+N vs Frequency

VDD = 5.0V, POUT = 800mW, RL= 8ΩVDD = 5.0V, POUT = 800mW, RL= 8Ω

DAC Input, Internal Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 17. Figure 18.

THD+N vs Frequency THD+N vs Frequency

VDD = 5.0V, POUT = 700mW, RL= 8ΩVDD = 5.0V, POUT = 1.0W, RL= 4Ω

Analog Input, Speaker Mode Analog Input, Speaker Mode

Figure 19. Figure 20.

Product Folder Links: LM49450

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Typical Performance Characteristics (continued)

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.0V, POUT = 10mW, RL= 16ΩHPVDD = 2.5V, POUT = 25mW, RL= 16Ω

DAC Input, Internal Reference, Headphone Mode DAC Input, Internal Reference, Headphone Mode

Figure 21. Figure 22.

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.0V, POUT = 15mW, RL= 32ΩHPVDD = 2.5V, POUT = 25mW, RL= 32Ω

DAC Input, Internal Reference, Headphone Mode DAC Input, Internal Reference, Headphone Mode

Figure 23. Figure 24.

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.0V, POUT = 10mW, RL= 16ΩHPVDD = 2.5V, POUT = 25mW, RL= 16Ω

DAC Input, External Reference, Headphone Mode DAC Input, External Reference, Headphone Mode

Figure 25. Figure 26.

Product Folder Links: LM49450

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

0.001

0.01

0.1

100

10 100 1000 10000 100000

FREQUENCY (Hz)

THD+N (%)

LM49450

www.ti.com

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Typical Performance Characteristics (continued)

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.0V, POUT = 15mW, RL= 32ΩHPVDD = 2.0V, POUT = 25mW, RL= 32Ω

DAC Input, External Reference, Headphone Mode DAC Input, External Reference, Headphone Mode

Figure 27. Figure 28.

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.0V, POUT = 10mW, RL= 16ΩHPVDD = 2.0V, POUT = 10mW, RL= 32Ω

Analog Input, Headphone Mode Analog Input, Headphone Mode

Figure 29. Figure 30.

THD+N vs Frequency THD+N vs Frequency

HPVDD = 2.5V, POUT = 15mW, RL= 16ΩHPVDD = 2.5V, POUT = 15mW, RL= 32Ω

Analog Input, Headphone Mode Analog Input, Headphone Mode

Figure 31. Figure 32.

Product Folder Links: LM49450

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

0.01

0.1

100

0.001 0.01 0.1 1 10

OUTPUT POWER (W)

THD+N (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Typical Performance Characteristics (continued)

THD+N vs Output Power THD+N vs Output Power

AV= 12dB, RL= 4Ω, f = 1kHz AV= 12dB, RL= 4Ω, f = 1kHz

DAC Input, Internal Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 33. Figure 34.

THD+N vs Output Power THD+N vs Output Power

AV= 12dB, RL= 8Ω, f = 1kHz AV= 12dB, RL= 8Ω, f = 1kHz

DAC Input, Internal Reference, Speaker Mode DAC Input, External Reference, Speaker Mode

Figure 35. Figure 36.

THD+N vs Output Power THD+N vs Output Power

AV= 6dB, RL= 4Ω, f = 1kHz AV= 6dB, RL= 8Ω, f = 1kHz

Analog Input, Speaker Mode Analog Input, Speaker Mode

Figure 37. Figure 38.

Product Folder Links: LM49450

0.01

0.1

100

0.001 0.01 0.1

OUTPUT POWER (W)

THD+N (%)

HPVDD = 2.5V

HPVDD = 2.0V

TWO CHANNELS

IN PHASE

-70

-60

-50

-40

-30

-20

-10

10 100 1000 10000 100000

FREQUENCY (Hz)

PSRR (dB)

0.01

0.1

100

0.001 0.01 0.1

OUTPUT POWER (W)

THD+N (%)

HPVDD = 2.5V

HPVDD = 2.0V

TWO CHANNELS

IN PHASE

0.01

0.1

100

0.001 0.01 0.1

OUTPUT POWER (W)

THD+N (%)

HPVDD = 2.5V

HPVDD = 2.0V

TWO CHANNELS

IN PHASE

0.01

0.1

100

0.001 0.01 0.1

OUTPUT POWER (W)

THD+N (%)

HPVDD = 2.5V

HPVDD = 2.0V

TWO CHANNELS

IN PHASE

0.01

0.1

100

0.001 0.01 0.1

OUTPUT POWER (W)

THD+N (%)

HPVDD = 2.5V

HPVDD = 2.0V

TWO CHANNELS

IN PHASE

LM49450

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Typical Performance Characteristics (continued)

THD+N vs Output Power THD+N vs Output Power

AV= 9dB, RL= 16Ω, f = 1kHz AV= 9dB, RL= 16Ω, f = 1kHz

DAC Input, Internal Reference, Headphone Mode DAC Input, External Reference, Headphone Mode

Figure 39. Figure 40.

THD+N vs Output Power THD+N vs Output Power

AV= 9dB, RL= 32Ω, f = 1kHz AV= 0dB, RL= 16Ω, f = 1kHz

DAC Input, External Reference, Headphone Mode Analog Input, Headphone Mode

Figure 41. Figure 42.

THD+N vs Output Power PSRR vs Frequency

AV= 0dB, RL= 32Ω, f = 1kHz VDD = 3.6V, VRIPPLE = 200mVP-P, RL= 8Ω

Analog Input, Headphone Mode DAC Input, Internal Reference, Speaker Mode

Figure 43. Figure 44.

Product Folder Links: LM49450

100

0 500 1000 1500 2000

OUTPUT POWER (mW)

EFFICIENCY (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

100

0 500 1000 1500

OUTPUT POWER (mW)

EFFICIENCY (%)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

-100

-90

-80

-70

-60

-50

-40

-30

-20

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FREQUENCY (Hz)

PSRR (dB)

-120

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FREQUENCY (Hz)

PSRR (dB)

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PSRR (dB)

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10 100 1000 10000 100000

FREQUENCY (Hz)

PSRR (dB)

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Typical Performance Characteristics (continued)

PSRR vs Frequency PSRR vs Frequency

VDD = 3.6V, VRIPPLE = 200mVP-P, RL= 8ΩVDD = 3.6V, VRIPPLE = 200mVP-P, RL= 8Ω

DAC Input, External Reference, Speaker Mode Analog Input, Speaker Mode

Figure 45. Figure 46.

PSRR vs Frequency PSRR vs Frequency

HPVDD = 2.5V, VRIPPLE = 200mVP-P, RL= 32ΩHPVDD = 2.5V, VRIPPLE = 200mVP-P, RL= 32Ω

DAC Input, Internal Reference, Headphone Mode Analog Input, Headphone Mode

Figure 47. Figure 48.

Efficiency vs Output Power Efficiency vs Output Power

RL= 4Ω, f = 1kHz, Speaker Mode RL= 8Ω, f = 1kHz, Speaker Mode

Figure 49. Figure 50.

Product Folder Links: LM49450

2.5 3 3.5 4 4.5 5 5.5

SUPPLY VOLTAGE (V)

OUTPUT POWER (W)

THD+N = 1%

THD+N = 10%

0.5

1.5

2.5 3 3.5 4 4.5 5 5.5

SUPPLY VOLTAGE (V)

OUTPUT POWER (W)

THD+N = 1%

THD+N = 10%

100

125

150

0 10 20 30 40 50 60 70

OUTPUT POWER (mW)

POWER DISSIPATION (mW)

HPVDD = 2.0V

HPVDD = 2.5V

POUT = POUTL

+ POUTR

100

125

150

0 10 20 30 40 50 60 70

OUTPUT POWER (mW)

POWER DISSIPATION (mW)

HPVDD = 2.0V

HPVDD = 2.5V

POUT = POUTL

+ POUTR

100

200

300

400

500

0 500 1000 1500 2000 2500 3000

OUTPUT POWER (mW)

POWER DISSIPATION (mW)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

POUT = P + POUTROUTL

250

500

750

1000

0 1000 2000 3000 4000

OUTPUT POWER (mW)

POWER DISSIPATION (mW)

VDD = 5V

VDD = 3.6V

VDD = 3.0V

POUT = P + POUTROUTL

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Typical Performance Characteristics (continued)

Power Dissipation vs Output Power Power Dissipation vs Output Power

RL= 4Ω, f = 1kHz, Speaker Mode RL= 8Ω, f = 1kHz, Speaker Mode

Figure 51. Figure 52.

Power Dissipation vs Output Power Power Dissipation vs Output Power

RL= 16Ω, f = 1kHz, Headphone Mode RL= 32Ω, f = 1kHz, Headphone Mode

Figure 53. Figure 54.

Output Power vs Supply Voltage Output Power vs Supply Voltage

RL= 4Ω, f = 1kHz, Speaker Mode RL= 8Ω, f = 1kHz, Speaker Mode

Figure 55. Figure 56.

Product Folder Links: LM49450

10 100 1000 10000 100000

FREQUENCY (Hz)

PVRMS)NOISE (

10 100 1000 10000 100000

FREQUENCY (Hz)

PVRMS)NOISE (

10 100 1000 10000 100000

FREQUENCY (Hz)

PVRMS)NOISE (

10 100 1000 10000 100000

FREQUENCY (Hz)

PVRMS)NOISE (

1.8 1.95 2.1 2.25 2.4 2.55 2.7

SUPPLY VOLTAGE (V)

OUTPUT POWER (mW)

THD+N = 1%

THD+N = 10%

1.8 1.95 2.1 2.25 2.4 2.55 2.7

SUPPLY VOLTAGE (V)

OUTPUT POWER (mW)

THD+N = 1%

THD+N = 10%

LM49450

SNAS440D –FEBRUARY 2008–REVISED MAY 2013

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Typical Performance Characteristics (continued)

Output Power vs Supply Voltage Output Power vs Supply Voltage

RL= 16Ω, f = 1kHz, Headphone Mode RL= 32Ω, f = 1kHz, Headphone Mode

Figure 57. Figure 58.

Output Noise vs Frequency Output Noise vs Frequency

VDD = 3.6V, RL= 8ΩVDD = 3.6V, RL= 8Ω

DAC Input, Internal Reference, Speaker Mode Analog Input, Speaker Mode

Figure 59. Figure 60.

Output Noise vs Frequency Output Noise vs Frequency

VDD = 2.5V, RL= 32ΩHPVDD = 2.5V, RL= 32Ω

DAC Input, Internal Reference, Headphone Mode Analog Input, Headphone Mode

Figure 61. Figure 62.

Product Folder Links: LM49450

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

10 100 1000 10000 100000

FREQUENCY (Hz)

CROSSTALK (dB)

-100

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10 100 1000 10000 100000

FREQUENCY (Hz)

CROSSTALK (dB)

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Typical Performance Characteristics (continued)

Crosstalk vs Frequency Crosstalk vs Frequency

VDD = 3.6V, VRIPPLE = 1VP-P, RL= 8ΩVDD = 2.5V, VRIPPLE = 1VP-P, RL= 8Ω

Analog Input, Speaker Mode Analog Input, Headphone Mode

Figure 63. Figure 64.

Product Folder Links: LM49450

START MSB DEVICE ADDRESS W

LSB ACK

SCL

SDA STOPMSB REGISTER ADDRESS LSB MSB REGISTER DATA LSB

ACK ACK

SDA

SCL SP

START condition STOP condition

LM49450

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APPLICATION INFORMATION

I2C-COMPATIBLE INTERFACE

The LM49450 is controlled through an I2C-compatible serial interface that consists of a serial data line (SDA) and

a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open collector). The LM49450

and the master can communicate at clock rates up to 400kHz. Figure 65 shows the I2C interface timing diagram.

Data on the SDA line must be stable during the HIGH period of SCL. The LM49450 is a transmit/receive slave-

only device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a

START condition and a STOP condition (Figure 66). Each data word, register address and register data,

transmitted over the bus is 8 bits long as is always followed by and acknowledge pulse (Figure 67). The

LM49450 device address is 1111101.

Figure 65. I2C Timing Diagram

Figure 66. START and STOP Diagram

Figure 67. Example I2C Write Cycle

BUS FORMAT

The I2C bus format is shown in Figure 69. The START signal, the transition of SDA from HIGH to LOW while

SDA is HIGH, is generated, altering all devices on the bus that a device address is being written to the bus.

The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit (R/W = 0

indicates the master is writing to the LM49450, R/W = 1 indicates the master wants to read data from the

LM49450). The data is latched in on the rising edge of the clock. Each address bit must be stable while SDA is

HIGH. After the last address bit is transmitted, the master device releases SDA, during which time, an

acknowledge clock pulse is generated by the slave device. If the LM49450 receives the correct address, the

device pulls the SDA line low, generating and acknowledge bit (ACK).

Product Folder Links: LM49450

X X 23 22 012 X X 23 22 12 0

I2S_CLK

I2S_WS

I2S_DATA

LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD

23 22 21 20 012 X 23 21 20 012 X22 3

I2S_CLK

I2S_WS

I2S_DATA

LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD

X23 22 21 01 X X 23 22 21 01 X X

I2S_CLK

I2S_WS

I2S_DATA

LEFT CHANNEL DATA WORD RIGHT CHANNEL DATA WORD

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

Once the master device registers the ACK bit, the 8-bit register address word is sent. Each data bit should be

stable while SCL is HIGH. After the 8-bit register address is sent, the LM49450 sends another ACK bit. Following

the acknowledgement of the register address, the 8-bit register data word is sent. Each data bit should be stable

while SCL is HIGH. After the 8-bit register data is sent, the LM49450 sends another ACK bit. Following the

acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SDA is

high.

I2S DATA FORMAT

The LM49450 supports three I2S formats: Normal Mode (Figure 68), Left Justified Mode (Figure 69), and Right

Justified Mode (Figure 70). In Normal Mode, the audio data is transmitted MSB first, with the unused bits

following the LSB. In Left Justified Mode, the audio data format is similar to the Normal Mode, without the delay

between the LSB and the change in I2S_WS. In Right Justified Mode, the audio data MSB is transmitted after a

delay of a preset number of bits.

Figure 68. I2S Normal Input Format

Figure 69. I2S Left-Justified Input Format

Figure 70. I2S Right-Justified Input Format

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GENERAL AMPLIFIER FUNCTION

Class D Amplifier

The LM49450 features a high-efficiency stereo Class D audio power amplifier that utilizes TI’s filterless

modulation scheme which reduces external component count, conserves board space and reduces system cost.

The Class D outputs transition between VDD and GND with a 300kHz switching frequency. With no signal

applied, the outputs switch with a 50% duty cycle, in phase, causing the two outputs to cancel. This cancellation

results in no net voltage across the speaker, thus there is no current to the load in the idle state.

With the input signal applied, the duty cycle (pulse width) of the LM49450 outputs changes. For increasing output

voltage, the duty cycle of V_LS+ increases while the duty cycle of V_LS- decreases. For decreasing output

voltages, the converse occurs. The difference between the two pulse widths yield the differential output voltage.

Fixed Frequency Mode

The LM49450 features two modulation schemes, a fixed frequency mode and a spread spectrum mode. Select

the fixed frequency mode by setting the SS bit (B3) in the Mode Control Register (0x00h) to 0. In fixed frequency

mode, the speaker amplifier outputs switch at a constant 300kHz. The output spectrum in fixed frequency mode

consists of the fundamental and its associated harmonics (see Typical Performance Characteristics).

Spread Spectrum

The logic selectable spread spectrum mode eliminates the need for output filters, ferrite beads or chokes. In

spread spectrum mode, the switching frequency varies randomly by 30% about a 300kHz center frequency,

reducing the wide-band spectral content, improving EMI emissions radiated by the speaker and associated

cables and traces. Where a fixed frequency class D exhibits large amounts of spectral energy at multiples of the

switching frequency, the spread spectrum architecture of the LM49450 spreads that energy over a larger

bandwidth (see Typical Performance Characteristics). The cycle-to-cycle variation of the switching period does

not affect the audio reproduction, efficiency, or PSRR. Set the SS bit (B3) in the Mode Control Register (0x00h)

to 1 to select spread spectrum mode.

Headphone Amplifier

The LM49450 headphone amplifiers feature TI’s ground referenced architecture that eliminates the large DC-

blocking capacitors required at the outputs of traditional headphone amplifiers. A low-noise inverting charge

pump creates a negative supply (HPVSS) from the positive supply voltage (CPVDD). The headphone amplifiers

operate from these bipolar supplies, with the amplifier outputs biased about GND, instead of a nominal DC

voltage (typically VDD/2), like traditional amplifiers. Because there is no DC component to the headphone output

signals, the large DC-blocking capacitors (typically 220µF) are not necessary, conserving board space and

system cost, while improving frequency response.

Power Supplies

The LM49450 uses different power supplies for each portion of the device, allowing for the optimum combination

of headroom, power dissipation and noise immunity. The analog input, and gain (volume control) stages for both

speaker and headphones are powered from VDD. The speaker output stage is powered from LSVDD. The

headphone amplifiers and charge pump are powered from HPVDD. The separate power supplies allow the class

D amplifiers to operate from a higher voltage, maximizing headroom, while the headphones operate from a lower

voltage, improving power dissipation, as well as minimizing switching noise coupling between the speaker and

headphone amplifiers. The digital portion of the device is powered from DVDD, including the 3D processing core

and DAC. IOVDD powers the I2S and I2C, allowing the LM49450 to interface with lower voltage digital controllers.

TI's 3D Enhancement

The LM49450 digital audio path features TI’s 3D enhancement that widens or narrows the perceived soundstage

of a stereo audio signal. The 3D enhancement either increases or decreases the apparent stereo channel

separation, improving audio reproduction whenever the placement of both left and right speakers is not ideal.

Product Folder Links: LM49450

HPR

HPL

RLS-

RLS+

LSS-

LSS+

HPS

ENABLE

LM49450

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SNAS440D –FEBRUARY 2008–REVISED MAY 2013

The LM49450 3D function is controlled through the I2C interface. The headphone and speakers have

independent 3D controls, allowing each signal path to have its own individual 3D configuration. The LM49450 3D

features two effect modes, a narrow effect that decreases the channel separation, making the speakers sound

closer together, and a wide effect that makes the speakers sound farther apart. Because the narrow effect mode

adds a portion of the left and right signals together, a selectable 6dB attenuation mode is provided to maintain a

constant output amplitude when the narrow effect mode is active without changing the volume level. The high

pass 3dB roll off frequency, 3D gain (amount channel mixing), and narrow/wide effect selection is done through

registers 0x05h (headphone) and 0x06h (speaker. See the Headphone 3D Configuration Register and

Headphone 3D Configuration Register sections for more information.

Headphone Sense

The LM49450 features a headphone sense input (HPS) that monitors the headphone jack and configures the

device depending on the presence of a headphone. When the HPS pin is low, indicating that a headphone is not

present, the LM49450 speaker amplifiers are active and the headphone amplifiers are disabled. When the HPS

pin is high, indicating that a headphone is present, the headphone amplifiers are active while the speaker

amplifiers are disabled.

Figure 71. HPS Connection

Volume Control

The LM49450 features two separate 32-step volume controls, one for the speaker channels and one for the

headphone channels. This allows for the gain of the headphone and speakers to be set independently of each

other.

External Reference

The LM49450 can be used with an external reference. Disable the internal reference by setting bit B7 of the

Mode Control Register (0x00h) to 1. This allows an external reference voltage to be applied to REF. For proper

operation, do not allow the VREF to exceed VDD.

Product Folder Links: LM49450

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Low Power Shutdown

The LM49450 features an I2C selectable low power shutdown mode that disables the entire device, reducing

quiescent current consumption to 0.05µA (digital + analog current). Set bit B0 in the mode control register

(0x00h) to 0 to disable the device. Set B0 to 1 to enable the device.

I2S CLOCK CONTROL

The LM49450 features the ability to derive multiple clock signals, including the DAC clock, I2S clock and word

select clock in master mode, and the charge pump oscillator frequency, from the MCLK input.

DAC Clock Divider (RDIV)

Bits B5-B0 in the CLOCK CONTROL register (0x01h) are the RDIV bits that set the DAC clock divider ratio. The

DAC clock derived from MCLK needs to match the DAC sampling rate. For example, with fMCLK = 12.288MHz

and a 64*fSoversampling ratio (fS= 48kHz), the DAC requires a 6.144MHz clock. In this case, set the RDIV ratio

to divide by 2. In other instances, there may not be a suitable divider ratio for a given sampling rate and MCLK

frequency. In this case, fMCLK may need to be altered. See the Clock Control Register section for more

information.

I2S WS Clock Dividers (I2S_CLK, WS_CLK)

In I2S master mode, the LM49450 I2S CLOCK CONTROL register (0x04h) can be used to set the I2S clock and

WS clock frequency. In I2S clock master mode, bits B7-B4 of the I2S CLOCK CONTROL register, the I2S_CLK

bits, set the I2S clock divider ratio. The LM49450 derives the I2S clock from DAC clock based on the ratio set by

the I2S_CLK bits. The I2S clock is output on I2S_CLK.

In I2S master mode, bits B3 and B2 (I2S_WS) of the I2S CLOCK CONTROL register set the bit length per data

word of the I2S WS.

Charge Pump Clock Divider (CPDIV)

The ground referenced headphone amplifiers charge pump derives its clock from MCLK. Bits B7-B0 of the

CHARGE PUMP CLOCK register (0x02h) set the charge pump clock divider ratio. See the Charge Pump Clock

Table 1. CONTROL REGISTERS — Register Map

Addess Name

MODE DAC_MO DAC_MODE

0x00h EXT_REF COMP SS MUTE LINE_IN ENABLE

CONTROL DE_1 _ 0

DAC_DIT DAC_DIT

0x01h CLOCK RDIV_5 RDIV_4 RDIV_3 RDIV_2 RDIV_1 RDIV_0

HER_OFF HER_ON

CHARGE PUMP

0x02h CLOCK CPDIV_7 CPDIV_6 CPDIV_5 CPDIV_4 CPDIV_3 CPDIV_2 CPDIV_1 CPDIV_0

FREQUENCY I2S I2S_WOR

RESERVE I2S_WRD I2S_WRD_ I2S_MODE_ I2S_MODE

0x03h I2S MODE I2S_WRD_1 STEREO D

D _2 0 1_ _0

_REVERSE _ORDER

0x04h I2S CLOCK I2S_CLK_ I2S_CLK_ I2S_CLK_1 I2S_CLK_0 I2S_WS_1 I2S_WS_0 I2S_WS_M I2S_CLK_

3 2 S MS

HEADPHONE 3D RESERVE HP_3DAT HP_3DFREQ HP_3DFRE HP_3D_GAI HP_3D_G HP_3D_MO

0x05h HP_3DEN

CONTROL D TN _1 Q_0 N_1 AIN_0 DE

0x06h SPEAKER 3D RESERVE LS_3DAT LS_3DFREQ LS_3DFRE LS_3DGAIN LS_3DGAI LS_3D_MO LS_3DEN

CONTROL D TN _1 Q_0 _1 N_0 DE

HEADPHONE RESERVE RESERVE

0x07h VOLUME RESERVED HP4 HP3 HP2 HP1 HP0

D D

CONTROL

SPEAKER RESERVE RESERVE

0x08h VOLUME RESERVED LS4 LS3 LS2 LS1 LS0

D D

CONTROL

0x09h CMP_0_LSB C0_7 C0_6 C0_5 C0_4 C0_3 C0_2 C0_1 C0_0

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Table 1. CONTROL REGISTERS — Register Map (continued)

Addess Name

0x0Ah CMP_0_MSB C0_15 C0_14 C0_13 C0_12 C0_111 C0_10 C0_09 C0_08

0x0Bh CMP_1_LSB C1_7 C1_6 C1_5 C1_4 C1_3 C1_2 C1_1 C1_0

0x0Ch CMP_1_MSB C1_15 C1_14 C1_13 C1_12 C1_11 C1_10 C1_09 C1_08

0x0Dh CMP_2_LSB C2_7 C2_6 C2_5 C2_4 C2_3 C2_2 C2_1 C2_0

0x0Eh CMP_2_MSB C2_15 C2_14 C2_13 C2_12 C2_11 C2_10 C2_09 C2_08

MODE CONTROL REGISTER (0x00h)

Default value is 0x00h.

Table 2. Mode Control Register

Bit Name Value Description

0 Internal reference selected

B7 EXT_REF External reference selected. See External Reference

1section.

B6 B5 Select DAC over sampling Rate

0 0 125

DAC_MODE_1 (B6)

B6:B5 0 1 128

DAC_MODE_0 (B5) 1 0 64

1 1 32

0 Default DAC compensation filter selected

B4 COMP Programmable DAC compensation filter selected. See DAC

1Compensation Filter section.

0 Fixed frequency oscillator selected

B3 SS 1 Spread spectrum oscillator selected

0 Un-mute device

B2 MUTE 1 Mute device

0 Device shutdown. Default state during a POR event

B0 ENABLE 1 Device enabled.

CLOCK CONTROL REGISTER (0x01h)

Default value is 0x00h.

Table 3. Clock Control Register

Bit Name Value Description

0 Default DAC state

B7 DAC_DITHER_OFF 1 Permanently disables DAC dither

0 Default DAC state

B6 DAC_DITHER_ON 1 Permanently enables DAC dither

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Clock

Decode

I2S Interface Stereo DAC

MCLK

DAC_MODE[1:0] CP_CLOCK_C

ANALOG_CLOCK_C

I2S_CLK

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Table 3. Clock Control Register (continued)

Bit Name Value Description

B5 B4 B3 B2 B1 B0 Sets MCLK divider ratio

0 0 0 0 0 0 Bypass divider

0 0 0 0 0 1 1

0 0 0 0 1 0 1.5

RDIV_5 (B5)

RDIV_4 (B4) 0 0 0 0 1 1 2

RDIV_3 (B3)

B5:B0 0 0 0 1 0 0 2.5

RDIV_2 (B2) 0 0 0 1 0 1 5

RDIV_1 (B1)

RDIV_0 (B0) TO In 0.5 increments

1 1 1 1 0 1 31

1 1 1 1 1 0 31.5

1 1 1 1 1 1 32

CLK NETWORK

Figure 72. CLK Network Diagram

LM49450 Clock Structure

The MCLK input is first divided by the R divider to product the clock at point B; this is then decoded according to

the DAC_MODE to produce a signal which goes to both the DAC digital and the I2S interface, and a signal which

goes to the DAC analog.

This table describes the relationship between the clocks, for each of the four possible DAC modes in terms of

audio input sampling frequency fs.

Table 4. Relationship between clocks for each of the four DAC modes

DAC MODE Description

OSR CLK at B DAC Digital CLK DAC Analog CLK

00 125 250fs 250fs 125fs

01 128 256fs 128fs 128fs

10 64 128fs 128fs 64fs

11 32 128fs 128fs 32fs

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Common Clock Settings for the DAC

In DAC_MODE 0, the DAC has an oversampling rate (OSR) of 125 but requires a 250xfs clock at point B. This

allows a simple clocking solution as it will work from 12.000MHz (common in most systems with Bluetooth or

USB) at 48kHz exactly. In the other DAC modes, the DAC requires a conventional 2^Nxfs clock for conversation.

The following table describes the clock required at point B for various clock sample rates in the different DAC

modes:

Table 5. Common DAC Clock Frequencies

Sample Rate Clock Required at B (MHz)

DAC MODE = 2b00 (OSR DAC MODE = 2b01 (OSR DAC MODE = 2b10 (OSR DAC MODE = 2b11 (OSR

= 125fs, Clock Required = = 128fs, Clock Required = = 64fs, Clock Required = = 32fs, Clock Required =

250fs) 256fs) 128fs) 128fs)

8 2 2.048 — —

11.025 2.75625 2.8224 — —

12 3 3.072 — —

16 4 4.096 — —

22.05 5.5125 5.6448 — —

24 6 6.144 — —

32 8 8.192 — —

44.1 11.025 11.2896 — —

48 — 12.288 — —

88.2 — — 11.2896 —

96 — — 12.288 —

176.4 — — — 22.5792

192 — — — 24.576

CHARGE PUMP CLOCK REGISTER (0x02h)

The charge pump clock register sets the charge pump frequency derived from MCLK when the LM49450 is in

DAC mode. Default value is for register 02h is 0x49h.

Table 6. Charge Pump Clock Register

Bit Name Value Description

B7 B6 B5 B4 B3 B2 B1 B0 Sets charge pump oscillator

CPDIV_7(B frequency in DAC mode (derived

7) from MCLK).

CPDIV_6 0 0 0 0 0 0 0 0 Bypass divider

(B6)

CPDIV_5 00000001 1

(B5) 00000010 1.5

CPDIV_4

(B4) 00000011 2

B7:B0 CPDIV_3 00000100 2.5

(B3) 00000101 3

CPDIV_2

(B2) TO In 0.5 increments

CPDIV_1 11111101 127

(B1)

CPDIV_0 11111110 127.5

(B0) 11111111 128

CP_DIV REGISTER

LM49450 Clock Structure

This register is used to control the charge pump clock when the register field LINE_IN_ENABLE is low i.e. DAC

mode. When the register field LINE_IN_ENABLE is high, the Clocks module is held in reset and as a result no

CP_CLOCK_C is produced.

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Table 7. CP_DIV Default Value 0x49h

Bits Field Description

7:0 CP_DIV Programs the CP divider (devides from an expected 12.000MHz

input).

CP_DIV Divide Value

0 Bypass

1 1

2 1.5

3 2

4 2.5

5 to 253 3 to 127

254 127.5

255 128

Examples of CP_DIV Values one might use for various sample rates and DAC modes

Table 8. Typical CP_DIV Values for DAC Mode 00

MCLK (MHZ) CP_DIV Nominal Frequency (Hz)

2 11 333333

2.75625 16 324265

3 17 333333

4 23 333333

5.5125 33 324264

6 36 324324

8 48 326530

11.025 67 324265

12 73 324324

Table 9. Typical CP_DIV Values for DAC Mode 01

MCLK (MHZ) CP_DIV Nominal Frequency (Hz)

2.048 11 341333

2.8224 17 313600

3.072 18 323368

4.096 24 327680

5.6448 33 332047

6.144 37 323368

8.192 49 327680

11.2896 68 327234

12.288 75 323368

Table 10. Typical CP_DIV Values for DAC Mode 10

MCLK (MHZ) CP_DIV Nominal Frequency (Hz)

11.2896 68 327234

12.288 75 323368

Table 11. Typical CP_DIV Values for DAC Mode 11

MCLK (MHZ) CP_DIV Nominal Frequency (Hz)

22.5792 138 324881

24.576 150 325510

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I2S MODE CONTROL REGISTER (0x03h)

Default value is 0x00h.

Table 12. I2S Mode Control Register

Bit Name Value Description

B7 RESERVED X Unused

B6 B5 B4 Sets I2S word size in Right Justified Mode

0 0 0 16

0 0 1 18

0 1 0 20

I2S_WRD_2 (B6)

B6:B4 I2S_WRD_1 (B5) 0 1 1 22

I2S_WRD_0 (B5) 1 0 0 24

1 0 1 25

1 1 0 26

1 1 1 32

Normal mode.

0 Left channel data goes to left channel output

Right channel data goes to right channel output.

I2S_STEREO

B3 _REVERSE Reverse mode.

1 Left channel data goes to right channel output

Right channel data goes to left channel output

Normal mode.

0 I2S_WS = 0 indicates left channel audio

I2S_WS = 1 indicates right channel audio

I2S_WORD_ORDE

B2 RReverse mode.

1 I2S_WS = 0 indicates right channel audio

I2S_WS = 1 indicates left channel audio.

B1 B0 Sets I2S operating mode

0 0 Normal Mode

I2S_MODE_1 (B1)

B1:B0 0 1 Left Justified Mode

I2S_MODE_0 (B0) 1 0 Right Justified Mode

1 1 Unused

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I2S CLOCK REGISTER (0x04h)

Default value is 0x00h.

Table 13. I2S Clock Register

Bit Name Value Description

Sets divider ratio to derive the I2S clock from the divided MCLK in I2S

master mode

B7 B6 B5 B4 DIVIDE BY RATIO

0 0 0 0 1 —

0 0 0 1 2 —

0 0 1 0 4 —

0 1 1 1 6 —

I2S_CLK_3 0 0 0 0 8 —

(B7) 0 0 1 1 10 —

I2S_CLK_2

(B6) 0 1 0 0 16 —

B7:B4 I2S_CLK_1 0 1 1 1 20 —

(B5)

I2S_CLK_0 1 0 0 0 2.5 2.5

(B4) 1 0 0 1 3 1:3

1 0 1 0 3.90625 32:125

1 0 1 1 5 1:5

1 1 0 0 7.8125 16:125

1 1 0 1 — —

1 1 1 0 — —

1 1 1 1 — —

B3 B2 Determines the bit length per data word of I2S_WS in I2S master mode

I2S_WS_1 0 0 16

(B3)

B3:B2 0 1 25

I2S_WS_0( 1 0 32

B2) 1 1 —

I2S WS slave mode. The LM49450 drives the I2S WS signal from the

0I2S_WS line.

I2S_WS_M

B1 SI2S WS master mode. The LM49450 generates the I2S WS signal.

1I2S_WS line is driven by the LM49450

I2S clock slave mode. The LM49450 derives its I2S clock from the

0I2S_CLK line.

I2S_CLK_M

B0 SI2S clock master mode. The LM49450 generates the I2S clock signal.

1I2S_CLK line is driven by the LM49450.

HEADPHONE 3D CONFIGURATION REGISTER (0x05h)

Default value is 0x00h.

Table 14. Headphone 3D Configuration Register

Bit Name Value Description

B7 RESERVED X UNUSED

0 No Attenuation

B6 HP_3DATTN 1 Output signals are attenuated by 6dB

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Table 14. Headphone 3D Configuration Register (continued)

Bit Name Value Description

B5 B4 Sets 3D high pass filter -3dB (roll-off) frequency

0 0 0

HP_3DFREQ_1 (B5)

B5:B4 0 1 300Hz

HP_3DFREQ_0 (B4) 1 0 600Hz

1 1 900Hz

Sets the 3D mix level, ie the amount of the left channel

B3 B2 signal that appears on the right channel and visa versa.

0 0 25%

HP_3DFREQ_1 (B3)

B3:B2 HP_3DFREQ_0 (B2) 0 1 37.5%

1 0 50%

1 1 75%

0 Narrow 3D effect

B1 HP_3D 1 Wide 3D effect

0 Headphone 3D disabled

B0 HP_3DEN 1 Headphone 3D enabled

LOUDSPEAKER 3D CONFIGURATION REGISTER (0x06h)

Default value is 0x00h.

Table 15. Loudspeaker 3D Configuration Register

Bit Name Value Description

B7 RESERVED X UNUSED

0 No Attenuation

B6 LS_3DATTN 1 Output signals are attenuated by 6dB

B5 B4 Sets 3D high pass filter -3dB (roll-off) frequency

0 0 0

LS_3DFREQ_1 (B5)

B5:B4 0 1 300Hz

LS_3DFREQ_0 (B4) 1 0 600Hz

1 1 900Hz

Sets the 3D mix level, ie the amount of the left channel

B3 B2 signal that appears on the right channel and visa versa.

0 0 25%

LS_3DFREQ_1 (B3)

B3:B2 LS_3DFREQ_0 (B2) 0 1 37.5%

1 0 50%

1 0 75%

0 Narrow 3D effect

B1 HP_3D 1 Wide 3D effect

0 Loudspeaker 3D disabled

B0 HP_3DEN 1 Loudspeaker 3D enabled

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HEADPHONE VOLUME CONTROL REGISTER (0x07h)

Default value is 0x00h.

Table 16. Headphone Volume Control Register

Bit Name Value Description

B7:B5 RESERVED X UNUSED

HP4 (B4)

HP3 (B3) See Headphone Volume Control Controls gain/attenuation of the audio signal in the

B4:B0 HP2 (B2) Table headphone path.

HP1 (B1)

HP0 (B0)

VOLUME HP4 HP3 HP2 HP1 HP0 HP GAIN (dB)

STEP

100000–59

200001–48

3 0 0 0 1 0 –40.5

4 0 0 0 1 1 –34.5

500100–30

600101–27

700110–24

800111–21

901000–18

10 0 1 0 0 1 –15

11 0 1 0 1 0 –13.5

12 0 1 0 1 1 –12

13 0 1 1 0 0 –10.5

14 0 1 1 0 1 –9

15 0 1 1 1 0 –7.5

16 0 1 1 1 1 –6

17 1 0 0 0 0 –4.5

18 1 0 0 0 1 –3

19 1 0 0 1 0 –1.5

20100110

21 1 0 1 0 0 1.5

22101013

23 1 0 1 1 0 4.5

24101116

25 1 1 0 0 0 7.5

26110019

27 1 1 0 1 0 10.5

28 1 1 0 1 1 12

29 1 1 1 0 0 13.5

30 1 1 1 0 1 15

31 1 1 1 1 0 16.5

32 1 1 1 1 1 18

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LOUDSPEAKER VOLUME CONTROL REGISTER (0x08h)

Default value is 0x00h.

Table 17. Loudspeaker Volume Control Register

Bit Name Value Description

B7:B5 RESERVED X UNUSED

LS4 (B4)

LS3 (B3) See Headphone Volume Control Controls gain/attenuation of the audio signal in the

B4:B0 LS2 (B2) Table loudspeaker path.

LS1 (B1)

LS0 (B0)

VOLUME LS4 LS3 LS2 LS1 LS0 LS GAIN (dB)

STEP

100000–53

200001–42

3 0 0 0 1 0 –34.5

4 0 0 0 1 1 –28.5

500100–24

600101–21

700110–18

800111–15

901000–12

10 0 1 0 0 1 –9

11 0 1 0 1 0 –7.5

12 0 1 0 1 1 –6

13 0 1 1 0 0 –4.5

14 0 1 1 0 1 –3

15 0 1 1 1 0 –1.5

16011110

17 1 0 0 0 0 1.5

18100013

19 1 0 0 1 0 4.5

20100116

21 1 0 1 0 0 7.5

22101019

23 1 0 1 1 0 10.5

24 1 0 1 1 1 12

25 1 1 0 0 0 13.5

26 1 1 0 0 1 15

27 1 1 0 1 0 16.5

28 1 1 0 1 1 18

29 1 1 1 0 0 19.5

30 1 1 1 0 1 21

31 1 1 1 1 0 22.5

32 1 1 1 1 1 24

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DAC COMPENSATION FILTER REGISTERS (0x09h to 0x0Eh)

DAC Compensation Filter

The LM49450 DAC features a 5 band FIR filter that can be used as an equalizer for the digital audio path.

Registers 0x09h, 0x0Ah, 0x0Bh, 0x0Ch, 0x0Dh, and 0x0Eh provide an 8-bit control for each individual FIR filter.

EXTERNAL COMPONENT SELECTION

The LM49450 uses different supplies for each portion of the device, allowing for the optimum combination of

headroom, power dissipation and noise immunity. The speaker amplifier gain stage is powered from VDD, while

the output stage is powered from LSVDD. The headphone amplifiers, input amplifiers and volume control stages

are powered from HPVDD. The separate power supplies allow the speakers to operate from a higher voltage for

maximum headroom, while the headphones operate from a lower voltage, improving power dissipation. HPVDD

may be driven by a linear regulator to further improve performance in noisy environments. The I2C portion if

powered from I2CVDD, allowing the I2C portion of the LM49450 to interface with lower voltage digital controllers.

PROPER SELECTION OF EXTERNAL COMPONENTS

Power Supply Bypassing and Filtering

Proper power supply bypassing is critical for low noise performance and high PSRR. Place the supply bypass

capacitors as close to the device as possible. Typical applications employ a voltage regulator with 10µF and

0.1µF bypass capacitors that increase supply stability. These capacitors do not eliminate the need for bypassing

of the LM49450 supply pins. A 1µF ceramic capacitor placed close to each supply pin is recommended.

Bypass Capacitor Selection

The LM49450 internally generates a VDD/2 common-mode bias voltage. The BYPASS capacitor CBYPASS,

improves PSRR and THD+N by reducing noise at the BYPASS node. Use a 2.2µF ceramic placed as close to

the device as possible.

REF Capacitor Selection

The LM49450 generates an internal low noise reference voltage used by the DAC. For best THD+N

performance, bypass REF with 10µF and 0.1µF ceramic capacitors.

Charge Pump Capacitor Selection

Use low ESR ceramic capacitors (less than 100mΩ) for optimum performance.

Charge Pump Flying Capacitor (C1)

The flying capacitor (C1) affects the load regulation and output impedance of the charge pump. A C1 value that

is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C1 improves

load regulation and lowers charge pump output impedance to an extent. Above 2.2µF, the RDS(ON) of the charge

pump switches and the ESR of C1 and C2 dominate the output impedance. A lower value capacitor can be used

in systems where low maximum output power requirements.

Charge Pump Hold Capacitor (C2)

The value and ESR of the hold capacitor (C2) directly affects the ripple on CPVSS. Increasing the value of C2

reduces output ripple. Decreasing the ESR of C2 reduces both output ripple and charge pump output impedance.

A lower value capacitor can be used in systems where low maximum output power requirements.

Input Capacitor Selection

The LM49450 analog inputs require input coupling capacitors. Input capacitors block the DC component of the

audio signal, eliminating any conflict between the DC component of the audio source and the bias voltage of the

LM49450. The input capacitors create a high-pass filter with the input resistors RIN. The -3dB point of the high

pass filter is found using Equation 1 below.

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f = 1 / 2πRINCIN

where

• the value of RIN is typically 20kΩ(1)

The input capacitors can also be used to remove low frequency content from the audio signal. Small speakers

cannot reproduce, and may even be damaged by low frequencies. High pass filtering the audio signal helps

protect the speakers. When the LM49450 is using a single-ended source, power supply noise on the ground is

seen as an input signal. Setting the high-pass filter point above the power supply noise frequencies, 217Hz in a

GSM phone, for example, filters out the noise such that it is not amplified and heard on the output. Capacitors

with a tolerance of 10% or better are recommended for impedance matching and improved CMRR and PSRR.

PCB Layout Guidelines

Minimize trace impedance of the power, ground and all output traces for optimum performance. Voltage loss due

to trace resistance between the LM49450 and the load results in decreased output power and efficiency. Trace

resistance between the power supply and ground has the same effect as a poorly regulated supply, increased

ripple and reduced peak output power. Use wide traces for power supply inputs and amplifier outputs to minimize

losses due to trace resistance, as well as route heat away from the device. Proper grounding improves audio

performance, minimizes crosstalk between channels and prevents switching noise from interfering with the audio

signal. Use of power and ground planes is recommended.

Place all digital components and route digital signal traces as far as possible from analog components and

traces. Do not run digital and analog traces in parallel on the same PCB layer. If digital and analog signal lines

must cross either over or under each other, ensure that they cross in a perpendicular fashion.

Exposed DAP Mounting Considerations

The LM49450 WQFN package features an exposed die-attach (thermal) pad on its backside. The exposed pad

provides a direct heat conduction path from the die to the PCB, reducing the thermal resistance of the package.

Connect the exposed pad to GND with a large pad and via to a large GND plane on the bottom of the PCB for

best heat distribution.

Revision Table

Rev Date Description

1.0 12/18/07 Initial release.

1.01 09/26/08 Corrected the package drawing.

On Table 5 (Common DAC Clock..., col DAC MODE = 2b01... sample 8...), changed

1.02 08/04/11 2.084 to 2.048.

D 05/03/13 Changed layout of National Data Sheet to TI format.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Top-Side Markings

(4)

Samples

LM49450SQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L49450

LM49450SQX/NOPB ACTIVE WQFN RTV 32 4500 Green (RoHS

& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 L49450

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a

continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM49450SQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

LM49450SQX/NOPB WQFN RTV 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 11-Oct-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM49450SQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0

LM49450SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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PACKAGE OUTLINE

5.15

4.85

5.15

4.85

0.8

0.7

0.05

0.00

2X 3.5

28X 0.5

2X 3.5

32X 0.5

0.3

32X 0.30

0.18

3.1 0.1

(0.1) TYP

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/A 06/2018

0.08 C

0.1 C A B

0.05

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMM

EXPOSED

THERMAL PAD

SYMM

916

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

28X (0.5)

(1.3)

(R0.05) TYP

0.07 MAX

ALL AROUND

0.07 MIN

ALL AROUND

32X (0.6)

32X (0.24)

(4.8)

(3.1)

( 0.2) TYP

VIA

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/A 06/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature

number SLUA271 (www.ti.com/lit/slua271).

5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown

on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SEE SOLDER MASK

DETAIL

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 15X

916

METAL EDGE

SOLDER MASK

OPENING

EXPOSED METAL

METAL UNDER

SOLDER MASK

OPENING

EXPOSED

METAL

NON SOLDER MASK

DEFINED

(PREFERRED) SOLDER MASK DEFINED

SOLDER MASK DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.24)

28X (0.5)

(4.8)

(0.775) TYP

4X (1.35)

(R0.05) TYP

WQFN - 0.8 mm max heightRTV0032A

PLASTIC QUAD FLATPACK - NO LEAD

4224386/A 06/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 33

76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

916

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