M69AW048B 32 Mbit (2M x16) 3V Asynchronous PSRAM FEATURES SUMMARY SUPPLY VOLTAGE: 2.7 to 3.3V ACCESS TIMES: 70ns LOW STANDBY CURRENT: 100A DEEP POWER-DOWN CURRENT: 10A BYTE CONTROL: UB/LB PROGRAMMABLE PARTIAL ARRAY COMPATIBLE WITH STANDARD LPSRAM TRI-STATE COMMON I/O 8 WORD PAGE ACCESS CAPABILITY: 18ns WIDE OPERATING TEMPERATURE - TA = -30 to +85C Figure 1. Package FBGA TFBGA48 (ZB) 6x8 mm POWER-DOWN MODES - Deep Power-Down - 4 Mbit Partial Array Refresh - 8 Mbit Partial Array Refresh - 16 Mbit Partial Array Refresh November 2004 1/29 M69AW048B TABLE OF CONTENTS FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Upper Byte Enable (UB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Description of Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 3. Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 5. Power-Down Configuration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Table 6. Power-Down Configuration Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 8. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/29 M69AW048B Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 11. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 8. Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. UB/LB Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10.Page Address and Chip Enable Controlled, Read Mode AC Waveforms . . . . . . . . . . . . 16 Figure 11.Random and Page Address Controlled, Read Mode AC Waveforms . . . . . . . . . . . . . . . 17 Table 12. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13.Write Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . . 20 Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . 20 Figure 16.Write Enable and LB/UB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . . 21 Figure 17.Write Enable and LB/UB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . . 21 Figure 18.Chip Enable Controlled, Read Followed by Write Mode AC Waveforms . . . . . . . . . . . . 22 Figure 19.E1, W, G Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . 22 Figure 20.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . . 23 Figure 21.Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms 23 Table 13. Standby/Power-Down Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 22.Power Down Program AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 23.Power-Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 24.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 25.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 26.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 26 Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 26 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3/29 M69AW048B SUMMARY DESCRIPTION The M69AW048B is a 32 Mbit (33,554,432 bit) CMOS memory, organized as 2,097,152 words by 16 bits, and is supplied by a single 2.7V to 3.3V supply voltage range. M69AW048B is a member of STMicroelectronics PSRAM memory family. These devices are manufactured using dynamic random access memory cells, to minimize the cell size, and maximize the amount of memory that can be implemented in a given area. However, through the use of internal control logic, the device is fully static in its operation, requiring no external clocks or timing strobes, and has a standard Asynchronous SRAM Interface. The internal control logic of the M69AW048B handles the periodic refresh cycle, automatically, and without user involvement. Write cycles can be performed on a single byte by using Upper Byte Enable (UB) and Lower Byte Enable (LB). The device can be put into standby mode using Chip Enable (E1) or in Power-Down mode by using Chip Enable (E2). The device features various kinds of Power-Down modes for power saving as a user configurable option: The Partial Array Refresh (PAR) performs a limited refresh of the part of the PSRAM array (4 Mbits, 8 Mbits, 16Mbits) that contains essential data. Deep Power-Down mode: this mode achieves a very low current consumption by halting all the internal activities. Since the refresh circuitry is halted, the duration of the powerdown should be less than the maximum period for refresh. Figure 2. Logic Diagram Table 1. Signal Names A0-A20 Address Input DQ0-DQ15 Data Input/Output E1, E2 Chip Enable, Power Down G Output Enable W Write Enable W UB Upper Byte Enable E1 LB Lower Byte Enable VCC Supply Voltage VSS Ground NC Not Connected (no internal connection) VCC 21 16 A0-A20 E2 DQ0-DQ15 M69AW048B G UB LB VSS AI05844c 4/29 M69AW048B Figure 3. TFBGA Connections (Top view through package) 1 2 3 4 5 6 A LB G A0 A1 A2 E2 B DQ8 UB A3 A4 E1 DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 W DQ7 H A18 A8 A9 A10 A11 A20 AI07242 5/29 M69AW048B SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram, and Table 1., Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A20). The Address Inputs select the cells in the memory array to access during Read and Write operations. Data Inputs/Outputs (DQ8-DQ15). The Upper Byte Data Inputs/Outputs carry the data to or from the upper part of the selected address during a Write or Read operation, when Upper Byte Enable (UB) is driven Low. Data Inputs/Outputs (DQ0-DQ7). The Lower Byte Data Inputs/Outputs carry the data to or from the lower part of the selected address during a Write or Read operation, when Lower Byte Enable (LB) is driven Low. Chip Enable (E1). When asserted (Low), the Chip Enable, E1, activates the memory state machine, address buffers and decoders, allowing Read and Write operations to be performed. When de-asserted (High), all other pins are ignored, and the device is put, automatically, in low-power Standby mode. Chip Enable (E2). The Chip Enable, E2, puts the device in Power-down mode (Deep Power-Down, PAR and Standby) when it is driven Low. One of 6/29 these, Deep Power-Down mode, is the lowest power mode. Output Enable (G). The Output Enable, G, provides a high speed tri-state control, allowing fast read/write cycles to be achieved with the common I/O data bus. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory's Command Interface. Upper Byte Enable (UB). The Upper Byte Enable, UB, gates the data on the Upper Byte Data Inputs/Outputs (DQ8-DQ15) to or from the upper part of the selected address during a Write or Read operation. Lower Byte Enable (LB). The Lower Byte Enable, LB, gates the data on the Lower Byte Data Inputs/Outputs (DQ0-DQ7) to or from the lower part of the selected address during a Write or Read operation. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Write, etc.) and for driving the refresh logic, even when the device is not being accessed. VSS Ground. The VSS Ground is the reference for all voltage measurements. M69AW048B Figure 4. Block Diagram ARBITRATION LOGIC INTERNAL CLOCK GENERATOR E2 W DYNAMIC MEMORY ARRAY INPUT/OUTPUT BUFFER E1 G ROW DECODER ADDRESS REFRESH CONTROLLER CONTROL LOGIC COLUMN DECODER DQ0-DQ7 DQ8-DQ15 LB UB VCC VSS POWER CONTROLLER ADDRESS AI07221b 7/29 M69AW048B OPERATION Operational modes are determined by device control inputs W, E1, E2, LB and UB as summarized in the Operating Modes table (see Table 2., Operating Modes). Power-Up Sequence Because the internal control logic of the M69AW048B needs to be initialized, the following Power-Up procedure must be followed before the memory is used: - Apply power and wait for VCC to stabilize, - Wait 300s while driving both Chip Enable signals (E1 and E2) High. See also Figure 24. for details on the Power-Up AC waveforms. Read Mode The device is in Read mode when: - Write Enable (W) is High and - Output Enable (G) Low and - the two Chip Enable signals are asserted (E1 is Low, and E2 is High). The time taken to enter Read mode (tELQV, tGLQV or tBLQV) depends on which of the above signals was the last to reach the appropriate level. Data out (DQ15-DQ0) may be indeterminate during tELQX, tGLQX and tBLQX but data will always be valid during tAVQV. See Figures 7, 8, 9, 10 and 11 and Table 11., Read Mode AC Characteristics, for details of when the outputs become valid. Write Mode The device is in Write mode when - Write Enable (W) is Low and - Chip Enable (E1) is Low and E2 is High - at least one of Upper Byte Enable (UB) and Lower Byte Enable (LB) is Low. The Write cycle begins just after the event (the falling edge) that causes the last of these conditions to become true (tAVWL or tAVEL or tAVBL). The Write cycle is terminated by the rising edge of Write Enable (W) or Chip Enable (E1), whichever occurs first. If the device is in Write mode (Chip Enable (E1) is Low, Output Enable (G) is Low, Upper Byte Enable (UB) and/or Lower Byte Enable (LB) is Low, then Write Enable (W) will return the outputs to high impedance within tWHDZ of its rising edge. Care must be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before the rising edge of Write Enable (W), or for tDVEH before the rising edge of Chip Enable (E1), whichever occurs first, and remain valid for tBHDZ, tWHDZ, tEHDZ. 8/29 See Figures 12, 13, 14, 15, 16 and 17 and Table 12., Write Mode AC Characteristics, for details of when the outputs become valid. Standby Mode The device is in Standby mode when: - Chip Enable (E1) is High and - Chip Enable (E2) is High The input/output buffers and the decoding/control logic are switched off, but the dynamic array continues to be refreshed. In this mode, the memory current consumption, ISB, is reduced, and the data remains valid. See Figures 17 and Table 13., Standby/PowerDown Mode AC Characteristics, for details of when the outputs become valid. Power-down Modes Description of Power-Down Modes. The M69AW048B has four Power-down modes, Deep Power-Down, 4 Mbit Partial Array Refresh, 8 Mbit Partial Array Refresh, and 16 Mbit Partial Array Refresh (see Table 4. and Figure 22.). These can be entered using a series of read and write operations. Each mode has following features. The default state is Deep Power-Down and it is the lowest power consumption but all data will be lost once E2 is brought Low for Power-down. No sequence is required to put the device in Deep Power-Down mode after Power-up. The device is in one of the Power-down modes when: - Chip Enable (E2) is Low All the device logic is switched off and all internal operations are suspended. This gives the lowest power consumption. In this operating mode, no refresh is performed, and data is lost if the duration is longer than 10ns. This mode is useful for those applications where the data contents are no longer needed, and can be lost, but where reduced current consumption is of major importance. Power-Down Program Sequence. The PowerDown Program sequence is used to program the Power-Down Configuration. It requires a total of six read and write operations, with specific addresses and data. Between each read or write operation the device must be in Standby mode. Table 4. shows the sequence. In the first cycle, the Byte at the highest memory address (MSB) is read. In the second and third cycles, the data (RDa) read by first cycle are written back. If the third cycle is written into a different address, the sequence is aborted, and the data written by the third cycle is valid as in a normal write operation. In the fourth and fifth cycles, the Power-Down Configuration data is written. The data of the fourth cycle must be M69AW048B and address must correspond, otherwise the sequence is aborted. When this sequence is performed to take the device from one PAR mode to another, the write data may be lost. So, if a PAR mode is used, this sequence should be performed prior to any normal read or write operations. set to `0000h', and the data of the fifth cycle is the Power-Down Configuration data (see Table 5., Power-Down Configuration Data). If the fourth cycle is written into a different address, the sequence is aborted. In the last cycle, a read is made from the specific Power-Down Configuration address (see Table 6., Power-Down Configuration Addresses). The Power-Down Configuration data Table 2. Operating Modes Operation E1 E2 W G LB UB DQ0-DQ7 DQ8-DQ15 Power VIH VIH X X X X Hi-Z Hi-Z Standby (ISB) X VIL X X X X Hi-Z Hi-Z Power-Down (ICCPD, ICCP4, ICCP8, ICCP16) No Read (1) VIL VIH VIH VIL VIH VIH Hi-Z Hi-Z Output Disable Lower Byte Read (1) VIL VIH VIH VIL VIL VIH Data Output Hi-Z Active (ICC) Lower Byte Write (1) VIL VIH VIL VIH VIL VIH Data Input Hi-Z Active (ICC) No Write VIL VIH VIL VIH VIH VIH Hi-Z Hi-Z Output Disable Upper Byte Read (1) VIL VIH VIH VIL VIH VIL Hi-Z Data Output Active (ICC) Upper Byte Write (1) VIL VIH VIL VIH VIH VIL Hi-Z Data Input Active (ICC) Word Read (1) VIL VIH VIH VIL VIL VIL Data Output Data Output Active (ICC) Word Write (1) VIL VIH VIL VIH(3) VIL VIL Data Input Data Input Active (ICC) Standby (Deselected) Power-Down (2) Note: X = VIH or VIL. 1. Should not be kept in this logic condition for a period longer than 1s. 2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data retention depend on the selection of Power-Down programming. 3. G can be VIL during the Write operation if the following conditions are satisfied: a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied; b. G stays VIL during the entire Write cycle. Table 3. Power-Down Modes Mode Data Retention Retention Address No N/A 4Mb PAR 4 Mbit 00000h - 3FFFFh 8Mb PAR 8 Mbit 00000h - 7FFFFh 16Mb PAR 16 Mbit 00000h - FFFFFh Deep Power-Down (Default) 9/29 M69AW048B Table 4. Power-Down Program Sequence Cycle # Operation Address Data 1st Read 1FFFFFh (MSB) Read Data (RDa) 2nd Write 1FFFFFh RDa 3rd Write 1FFFFFh RDa 4th Write 1FFFFFh 0000h 5th Write 1FFFFFh PDC Data(1) 6th Read PDC Address(1) Read Data (RDb) Note: 1. PDC Power-Down Configuration. Table 5. Power-Down Configuration Data Power-Down Configuration Data Power-Down Modes DQ15-DQ9 DQ8-DQ2 DQ1 DQ0 Deep Power-Down (default) 0 0 1 1 4Mb PAR 0 0 1 0 8Mb PAR 0 0 0 1 16Mb PAR 0 0 0 0 Table 6. Power-Down Configuration Addresses Power-Down Configuration Addresses Power-Down Modes A20 A19 A18-A0 Binary Deep Power-Down (default) 1 1 1 1FFFFFh 4Mb PAR 0 1 1 0FFFFFh 8Mb PAR 1 0 1 17FFFFh 16Mb PAR 0 0 1 07FFFFh 10/29 M69AW048B MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 7. Absolute Maximum Ratings Symbol Parameter Min Max Unit IO Output Current -50 50 mA TA Ambient Operating Temperature -30 85 C TSTG Storage Temperature -55 125 C VCC Core Supply Voltage -0.5 3.6 V VIO Input or Output Voltage -0.5 3.6 V 11/29 M69AW048B DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 8., Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 8. Operating and AC Measurement Conditions M69AW048B Parameter 70 Unit Min Max VCC Supply Voltage1 2.7 3.3 V Ambient Operating Temperature -30 85 C Load Capacitance (CL) 50 pF Output Circuit Protection Resistance (R1) 50 Input Pulse Voltages VCC 0 V Input and Output Timing Ref. Voltages VCC/2 V Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC V Input Transition Time2 (t) between VIL and VIH 5 ns Note: 1. All voltages are referenced to VSS. 2. The Input Transition Time used in AC measurements is 5ns. For other input transition times, see Table 8. Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit VCC/2 I/O Timing Reference Voltage R1 VCC VCC/2 0V DEVICE UNDER TEST OUT CL Output Timing Reference Voltage VCC 0V 0.7VCC 0.3VCC AI04831 CL includes JIG capacitance AI07222c 12/29 M69AW048B Table 9. Capacitance Symbol CIN COUT Test Condition Parameter Max Unit VIN = 0V 5 pF VOUT = 0V 8 pF Input Capacitance on all pins (except DQ) Output Capacitance Min Table 10. DC Characteristics Symbol Parameter ICC1 VCC Active Current ICC2 ICC3 VCC Page Read Current Test Condition VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA Max Unit tRC / tWC = minimum 30 mA tRC / tWC = 1 s 3 mA 10 mA Deep PowerDown 10 A 4 Mb PAR 40 A 8 Mb PAR 50 A 16 Mb PAR 65 A VCC = 3.3V, VIN = VIH or VIL, E1 = VIL and E2 = VIH, IOUT = 0mA, tPRC = min. ICCPD ICCP4 VCC Power Down Current ICCP8 VCC = 3.3V, VIN = VIH or VIL, E2 0.2V ICCP16 ILI Input Leakage Current ILO Output Leakage Current ISB Standby Supply Current CMOS Min 0V VIN VCC -1 1 A 0V VOUT VCC -1 1 A 100 A VCC = 3.3V, VIN 0.2V or VIN VCC -0.2V, E1 = E2 VCC -0.2V VIH (1) Input High Voltage 0.8VCC VCC + 0.2 V VIL (2) Input Low Voltage -0.3 0.2VCC V VOH Output High Voltage VCC = 2.7V, IOH = -0.5mA VOL Output Low Voltage IOL = 1mA 2.4 V 0.4 V Note: 1. Maximum DC voltage on input and I/O pins is VCC + 0.2V. During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns. 2. Minimum DC voltage on input or I/O pins is -0.3V. During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns. 13/29 M69AW048B Table 11. Read Mode AC Characteristics Symbol Alt. tAVAX (1,2) tRC tAVAX2 (1,6,7) Parameter M69AW048B Unit Min Max Address Valid Time 70 1000 ns tPRC Page Read Cycle Time 25 1000 ns tAVEH2 (1,6,7) tPRC Page Read Cycle Time 25 1000 ns tAVEL tASC Address Valid to Chip Enable Low -5 ns tAVGL tASO Address Valid to Output Enable Low 10 ns tAVQV (3,5) tAA Address Valid to Output Valid 70 ns tAVQV2 (3,6) tPAA Page Address Access Time 18 ns tAXAV (5,8) tAX Address Invalid Time 10 ns tAXAV2 (6,8) tAXP Page Address Invalid Time 10 ns tAXQX (3) tOH Data hold from address change 3 ns tBHQX (3) tOH Upper/Lower Byte Enable High to Output Transition 3 ns tBHQZ (4) tBHZ Upper/Lower Byte Enable High to Output Hi-Z 20 ns tBLQV (3) tBA Upper/Lower Byte Enable Low to Output Valid 30 ns tBLQX (4) tBLZ Upper/Lower Byte Enable Low to Output Transition 0 ns tEHAX (9) tCHAH Chip Enable High to Address Invalid -5 ns tEHEL tCP Chip Enable High to Chip Enable Low 15 ns (3) tOH Chip Enable High to Output Transition 3 ns tEHQZ (4) tCHZ Chip Enable High to Output Hi-Z tELAX (1,2) tRC Read Cycle Time tELEH (1,2) tRC Read Cycle Time tELQV (3) tCE Chip Enable Low to Output Valid tELQX (4) tCLZ Chip Enable Low to Output Transition 3 ns tGHAX tOHAH Output Enable High to Address Invalid -5 ns tOH Output Data Hold Time 3 ns tGHQZ (4) tOHZ Output Enable High to Output Hi-Z 20 ns tGLQV (3) tOE Output Enable Low to Output Valid 40 ns tGLQX (4) tOLZ Output Enable Low to Output Transition tEHQX tGHQX (3) 20 ns 70 1000 ns 70 1000 ns 70 ns 0 ns Note: 1. Maximum value is applicable if E1 is kept Low without change of address input of A3 to A20. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Address should not be changed within minimum Read Cycle Time. 3. The output load 50pF with 50 termination to VCC*0.5 V. 4. The output load 5pF without any other load. 5. Applicable to A3 to A20 when E1 is kept Low. 6. Applicable only to A0, A1 and A2 when E1 is kept Low for the page address access. 7. In case Page Read Cycle is continued with keeping E1 stays Low, E1 must be brought to High within 4s. In other words, Page Read Cycle must be closed within 4s. 8. Applicable when at least two of address inputs among applicable are switched from previous state. 9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied. 14/29 M69AW048B Figure 7. Read Mode AC Waveforms tELEH A0-A20 ADDRESS VALID VALID tAVEL tAVEL tEHAX tELQV E1 tEHEL tGLQV tEHQZ G tGHQZ tBLQV LB, UB tBHQZ tBLQX tGLQX tEHQX tELQX DQ0-DQ15 VALID DATA OUTPUT AI08986 Note: E2 = High, W = High. Figure 8. Output Enable Controlled, Read Mode AC Waveforms tAXAV tAVAX tAVAX A0-A20 ADDRESS VALID ADDRESS VALID tAVQV tAVQV tAXAV tAXAV E1 tGLQV tAVGL tGHAX G tGHQX UB, LB tGLQX DQ0-DQ15 tAXQX DATA OUT tGHQZ DATA OUT AI08987 Note: Write Enable (W) = High, E2 = High. 15/29 M69AW048B Figure 9. UB/LB Controlled, Read Mode AC Waveforms tAXAV tAXAV tAVAX A0-A20 ADDRESS VALID tAVQV E1 Low tBLQV tBLQV LB tBHQZ UB tBLQX tBLQX tBHQX VALID DATA OUT DQ0-DQ7 tBHQZ tBLQV tBHQX VALID DATA OUT tBHQZ tBLQX tBHQX DQ8-DQ15 VALID DATA OUTPUT ai08990 Note: E1 = Low, E2 = High, G = Low, W = High. Figure 10. Page Address and Chip Enable Controlled, Read Mode AC Waveforms tELEH ADDRESS VALID A20-A3 A2-A0 tAVEL tAVQV tAVAX tAVAX2 tAVAX2 ADDRESS VALID ADDRESS VALID ADDRESS VALID tELAX tAVQV2 tAXAV2 tAVQV2 tAXAV2 tAVEH ADDRESS VALID tAVQV2 tEHAX tAXAV2 E tEHQZ tELQV G LB, UB tELQX DQ0-DQ15 tAXQX VALID DATA OUTPUT tAXQX VALID DATA OUTPUT tAXQX VALID DATA OUTPUT tEHQX VALID DATA OUTPUT AI08991 Note: Write Enable (W) = High, E2 = High. 16/29 M69AW048B Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms tAVAX tAXAV A20-A3 tAVAX A2-A0 tAXAV tAXAV2 tAVAX tAVAX2 tAVAX tAVAX2 ADDRESS VALID ADDRESS VALID ADDRESS VALID ADDRESS VALID tAVQV E ADDRESS VALID ADDRESS VALID tAXAV2 tAXAV tAVQV2 tAVQV tAVQV2 Low tGLQV G tBLQV LB, UB tGLQX tBLQX DQ0-DQ15 tAXQX DATA OUT (Normal Access) tAXQX DATA OUT (Page Access) tAXQX DATA OUT (Normal Access) tAXQX DATA OUT (Page Access) AI08992 Note: E2 = High. 17/29 M69AW048B Table 12. Write Mode AC Characteristics M69AW048B Symbol Alt. Parameter Unit Min Max 1000 tAVAX (1,2) tWC Write Cycle Time 70 tAVBL (2) tAS Address Valid to LB, UB Low 0 ns tAVEL (2) tAS Address Valid to Chip Enable Low 0 ns tAVWL (2) tAS Address Valid to Write Enable Low 0 ns tAXAV (5) tAXW tBHAX (4) tBR LB, UB High to Address Transition 15 tBHDZ tDH LB, UB High to Input High-Z 0 ns tBLBH (3) tBW LB, UB Low to LB, UB High 45 ns tBLBH2 tBWO LB, UB Low to LB, UB High for Page Access 20 ns tBLWH (3) tBW LB, UB Low to Write Enable High 45 ns tDVBH tDS Input Valid to LB, UB High 20 ns tDVEH tDS Input Valid to Chip Enable High 20 ns tDVWH tDS Input Valid to Write Enable High 20 ns tEHAX (4) tWRC Chip Enable High to Address Transition 15 ns tEHDZ tDH Chip Enable High to Input High-Z 0 ns tEHEL tCP Chip Enable High to Chip Enable Low 15 ns tELAX (1,2) tWC Write Cycle Time 70 tELEH (3) tCW Chip Enable Low to Chip Enable High 45 ns tGHAV (7) tOES Output Enable High to Address Valid 0 ns tGHEL (6) tOHCL Output Enable High to Chip Enable Low -5 ns tGHDZ (4) tOHZ Output Enable High to Output Hi-Z tWHAX (4) tWR Write Enable High to Address Transition 15 tWHDZ tDH Write Enable High to Input High-Z 0 ns tWLBH (3) tWP Write Enable Low to LB, UB High 45 ns tWLWH (3) tWP Write Enable Low to Write Enable High 45 ns Address Invalid Time for Write ns 10 ns 1000 ns 1000 ns 20 ns 1000 ns Note: 1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your local ST representative for relaxation of the 1000ns limitation. 2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLBH or tBLBH) and write recovery time (tEHAX, tWHAX or tBHAX). 3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last. 4. Write recovery is defined from Write pulse is defined from the rising edge of E1, W, or LB/UB, whichever occurs first. 5. Applicable to any address change when E1 stays Low. 6. If G is Low after minimum tGHEL, the read cycle is initiated. In other words, G must be brought High within 5ns after E1 is brought Low. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. 7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before new address valid. Once the read cycle is initiated, new write pulse should be input after minimum Read Cycle Time is met. 18/29 M69AW048B Figure 12. Chip Enable Controlled, Write AC Waveforms tELAX A0-A20 ADDRESS VALID ADDRESS VALID tEHAX tAVEL tELEH tAVEL E1 tWHAX tAVWL tWLWH tAVWL W tBHAX tAVBL tBLWH tAVBL LB, UB tGHEL G tDVEH tDVWH tDVBH tEHDZ tWHDZ tBHDZ VALID DATA INPUT DQ0-DQ15 ai08993 Note: E2 = High. Figure 13. Write Enable Controlled, Write AC Waveforms A0-A20 E1 tAVAX tAVAX tAXAV ADDRESS VALID ADDRESS VALID tWHAX Low tAVWL tWLWH tAVWL tWLWH tWHAX W LB, UB tGHAV G tDVWH tGHDZ DQ0-DQ15 tWHDX VALID DATA INPUT tDVWH tWHDZ VALID DATA INPUT AI08994b Note: E2 = High. 19/29 M69AW048B Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1 tAVAX tAVAX A0-A20 ADDRESS VALID ADDRESS VALID tAXAV E1 Low tAVWL tWLBH tWLBH tAVWL W tBHAX LB tBHAX UB tDVBH tBHDZ VALID DATA INPUT DQ0-DQ7 tDVBH tBHDZ VALID DATA INPUT DQ8-DQ15 AI08995b Note: E2 = High. Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2 tAXAV A0-A20 tAVAX tAVAX ADDRESS VALID ADDRESS VALID tAXAV E1 Low tAVBL tBLWH tBLWH W LB tWHAX tWHAX tAVBL UB tDVWH DQ0-DQ7 tWHDZ VALID DATA INPUT tDVWH DQ8-DQ15 tWHDZ VALID DATA INPUT AI08996b Note: E2 = High. 20/29 M69AW048B Figure 16. Write Enable and LB/UB Controlled, Write AC Waveforms 3 tAVAX tAVAX tAXAV A0-A20 E1 ADDRESS VALID tAXAV Low tAVBL ADDRESS VALID tBLBH tBLBH W tBHAX LB tBHAX tAVBL UB tDVBH tBHDZ VALID DATA INPUT DQ0-DQ7 tBVWH tBHDZ VALID DATA INPUT DQ8-DQ15 AI08997b Note: E2 = High. Figure 17. Write Enable and LB/UB Controlled, Write AC Waveforms 4 tAXAV A0-A20 E1 tAVAX tAVAX ADDRESS VALID ADDRESS VALID tAXAV Low W tBHAX LB tAVBL tBLBH tBLBH tAVBL tBLBH2 tAVBL tDVBH tBHDZ tDVBH VALID DATA INPUT tBHAX tBLBH tBLBH2 tAVBL tDVBH DQ8-DQ15 tBHDZ VALID DATA INPUT DQ0-DQ7 UB tBHAX tBLBH tBHDZ tDVBH VALID DATA INPUT tBHAX tBHDZ VALID DATA INPUT AI08998b Note: E2 = High. 21/29 M69AW048B Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms tELAX(read) tELAX A0-A20 WRITE ADDRESS tEHAX (read) tAVEL READ ADDRESS tAVEL (read) tEHAX tEHAX(read) E1 tEHEL tELEH tEHEL tELQV W UB, LB tGHEL G tEHQZ tELQX tEHQX DQ0-DQ15 tDVEH tEHDZ READ DATA OUTPUT tEHQX WRITE DATA INPUT READ DATA OUTPUT ai08999b Note: Write address is valid from either E1 or W of last falling edge. Figure 19. E1, W, G Controlled, Read and Write Mode AC Waveforms tELAX(read) tELAX A0-A20 WRITE ADDRESS tEHAX (read) tAVEL READ ADDRESS tAVEL (read) tWHAX tEHAX(read) E1 tEHEL tELEH tEHEL tELQV W tWLWH UB, LB tGHEL tGHQV G tEHQZ tEHQX DQ0-DQ15 READ DATA OUTPUT tGLQX tDVWH tGHQX tWHDZ WRITE DATA INPUT READ DATA OUTPUT ai09400b Note: G can be Low fixed in write operation under E1 control read-write-read operation. 22/29 M69AW048B Figure 20. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms tAXAV A0-A20 tAVAX tAVAX(read) WRITE ADDRESS READ ADDRESS tAXAV E1 tAVQV Low tWLWH tWHAX W tAVWL UB, LB tAVGL tGLQV G tGHQZ tGHQX DQ0-DQ15 tDVWH DATA OUT tGLQX tGHQZ tWHDZ tGHQX DATA OUT DATA IN ai09401b Note: E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G. Figure 21. Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms tAXAV tAVAX A0-A20 tAVAX(read) WRITE ADDRESS READ ADDRESS tAXAV E1 tAVQV Low W tAVBL tBLBH tBHAX tBLQV UB, LB tAVGL G tBHQZ tBHQX DQ0-DQ15 DATA OUT tDVBH DATA IN tBLQX tBHQZ tBHDZ tBHQX DATA OUT ai09402b Note: E1 can be tied to Low for W and G controlled operation. When E1 is tied to Low, output is exclusively controlled by G. 23/29 M69AW048B Table 13. Standby/Power-Down Mode AC Characteristics M69AW048B Symbol Alt. tCLEX tCSP E2 Low Setup Time for Power Down Entry 10 ns tEXCH tC2LP E2 Low Hold Time after Power Down Entry 70 ns tEHEV (1) tCHH E1 High Hold Time following E2 High after PowerDown Exit (Deep Power-Down Mode only) 300 s tCHEL (2) tCHHP E1 High Hold Time following E2 High after PowerDown Exit (not in Deep Power-Down Mode) 1 s tEHCH tCHS E1 High Setup Time following E2 High after PowerDown Exit 0 s tEHGL tCHOX E1 High to G Invalid Time for Standby Entry 10 ns tCHWX E1 High to W Invalid Time for Standby Entry 10 ns Input Transition Time 1 tEHWL (3) t (4) Note: 1. 2. 3. 4. t Parameter Min Max 25 Unit ns Applicable also to Power-up. Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed Some data might be written into any address location if tEHWL (min) is not satisfied. The Input Transition Time (t) at AC testing is 5ns as shown below. If actual t is longer than 5ns, it may violate AC specification of some timing parameters. Figure 22. Power Down Program AC Waveforms tAVAX A0-A20 MSB 2 MSB 2 MSB 2 MSB 2 MSB 2 PDCADD3 tAXAVL 4 tAXAV E1 G W LB, UB DQ0-DQ15 RDa Cycle 1 RDa Cycle 2 RDa Cycle 3 00 Cycle 4 PDCD4 Cycle 5 RDb Cycle 6 AI07225c Note: 1. E2 = High. 2. All address inputs must be High from Cycle 1 to Cycle 5. 3. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherwise the data programmed during the Power-Down Program sequence may be incorrect. 4. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwise the data programmed during the Power-Down Program sequence may be incorrect. 5. tEHEL after the end of Cycle 6, the Power Down Program is completed and the device returns to normal operation. 24/29 M69AW048B Figure 23. Power-Down Mode AC Waveforms E1 tEHCH E2 tCLEX tCHEL tEXCH Hi-Z DQ0-D15 Power-Down Power-Down Mode Entry Power-Down Exit AI09403 Figure 24. Power-Up Mode AC Waveforms E1 tEHEL E2 VDDmin VDD AI09404 Figure 25. Standby Mode Entry AC Waveforms, After Read E1 tEHWL tEHGL G W Read Active Standby Write Active Standby AI09405 Note: E2 = High. 25/29 M69AW048B PACKAGE MECHANICAL Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View D D1 FD FE SD SE BALL "A1" E E1 ddd e e b A A2 A1 BGA-Z26 Note: Drawing is not to scale. Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Typ Min 1.200 A1 0.0102 0.900 b Max 0.0472 0.260 A2 0.350 0.450 0.0354 0.0138 0.0177 D 6.000 5.900 6.100 0.2362 0.2323 0.2402 D1 3.750 - - 0.1476 - - ddd 26/29 Max 0.100 0.0039 E 8.000 7.900 8.100 0.3150 0.3110 0.3189 E1 5.250 - - 0.2067 - - e 0.750 - - 0.0295 - - FD 1.125 - - 0.0443 - - FE 1.375 - - 0.0541 - - SD 0.375 - - 0.0148 - - SE 0.375 - - 0.0148 - - M69AW048B PART NUMBERING Table 15. Ordering Information Scheme Example: M69AW048 B L 70 ZB 8 Device Type M69 = PSRAM Mode A = Asynchronous Operating Voltage W = 2.7 to 3.3V Array Organization 048 = 32 Mbit (2M x16) Option 1 B = 2 Chip Enable Option 2 L = Low Leakage Speed Class 70= 70 ns Package ZB = TFBGA48, 0.75mm pitch Operative Temperature 8 = -30 to 85 C The notation used for the device number is as shown in Table 15.. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest STMicroelectronics Sales Office. 27/29 M69AW048B REVISION HISTORY Table 16. Document Revision History Date Version 07-Oct-2002 -01 First Issue 10-Mar-2003 2.0 Document completely revised 9-Mar-2004 3.0 Data Key and Address Key renamed Power-Down Configuration data and Power-Down Configuration Address respectively. Sleep mode renamed Deep Power-Down mode. ICCS removed and IPD renamed ICCPD in Table 10., DC Characteristics. Partial mode renamed Partial Array Refresh. Table 12. Write Mode AC Characteristics: tGHDZ added and Note 2 updated. tGHQZ changed to tGHDZ in Figure 13.Write Enable Controlled, Write AC Waveforms. AC Waveforms converted to ST standard. 21-Sep-2004 4.0 tELQZ, tGLQZ, tBLQZ changed into tELQX, tGLQX, tBLQX in Table 11., Read Mode AC Characteristics. 15-Nov-2004 5.0 VOH value updated in Table 10., DC Characteristics. 28/29 Revision Details M69AW048B Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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