1/29Novemb er 200 4
M69AW048B
32 Mbit (2M x16) 3V Asynchronous PSRAM
FEATURES SUMMARY
■SUPPLY VOLTAGE: 2.7 to 3.3V
■ACCESS TIMES: 70ns
■LOW STANDBY CURRENT: 100µA
■DEEP POWER-DOWN CURRENT: 10µA
■BYTE CONTROL: UB/LB
■PROGRAMMABLE PARTIAL ARRAY
■COMPATIBLE WITH STANDARD LPSRAM
■TRI-STATE COMMON I/O
■8 WORD PAGE ACCESS CAPABILITY: 18ns
■WIDE OPERATING TEMPERATURE
–T
A = –30 to +85°C
■POWER-DOWN MODES
– Deep Power-Down
– 4 Mbit Partial Array Refresh
– 8 Mbit Partial Array Refresh
– 16 Mbit Partial Array Refresh
Figure 1. Package
FBGA
TFBGA48 (ZB)
6x8 mm
M69AW048B
2/29
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Address Inputs (A0-A20). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ8-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Chip Enable (E1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Chip Enable (E2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Write En abl e (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Upper Byte Enable (UB).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Lower Byte Enable (LB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VCC Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Standby Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-down Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Description of Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 3. Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 4. Power-Down Program Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 5. Power-Down Configuration Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6. Power-Down Configuration Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 8. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. AC Measurement Load Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
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M69AW048B
Table 9. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 10. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. Read Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 7. Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 8. Output Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. UB/LB Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10.Page Address and Chip Enable Controlled, Read Mode AC Waveforms. . . . . . . . . . . . 16
Figure 11.Random and Page Address Controlled, Read Mode AC Waveforms. . . . . . . . . . . . . . . 17
Table 12. Write Mode AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.Chip Enable Controlled, Write AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13.Write Enable Controlled, Write AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14.Write Enable and UB/LB Controlled, Write AC Waveforms 1 . . . . . . . . . . . . . . . . . . . . . 20
Figure 15.Write Enable and UB/LB Controlled, Write AC Waveforms 2 . . . . . . . . . . . . . . . . . . . . . 20
Figure 16.Write Enable and LB/UB Controlled, Write AC Waveforms 3 . . . . . . . . . . . . . . . . . . . . . 21
Figure 17.Write Enable and LB/UB Controlled, Write AC Waveforms 4 . . . . . . . . . . . . . . . . . . . . . 21
Figure 18.Chip Enable Controlled, Read Followed by Write Mode AC Waveforms . . . . . . . . . . . . 22
Figure 19.E1, W, G Controlled, Read and Write Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . 22
Figure 20.Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms . . . 23
Figure 21.Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC Waveforms
23
Table 13. Standby/Power-Down Mode AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 22.Power Down Program AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 23.Power-Down Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24.Power-Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25.Standby Mode Entry AC Waveforms, After Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26.TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View . . . . 26
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data. . . . . . . . 26
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 15. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 16. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
M69AW048B
4/29
SUMMARY D ESCRIPTION
The M69AW048B is a 32 Mbit (33,554,432 bit)
CMOS memory, organized as 2,097,152 words by
16 bits, and is supplied by a single 2.7V to 3.3V
supply voltage range.
M69AW048B is a member of STMicroelectronics
PSRAM memory family. These devices are manu-
factured using dynamic random access memory
cells, to minimize the cell size, and maximize the
amount of memory that can be implemented in a
given area.
However, through the use of internal control logic,
the device is fully static in its operation, requiring
no external clocks or timing strobes, and has a
standard Asynchronous SRAM Interface.
The internal control logic of the M69AW048B han-
dles the p eriod ic refr esh cyc le, au tomati call y, and
without user involv eme nt.
Write cycles can be performed on a single byte by
using Upper Byte Enable (UB) and Lower Byte En-
able (LB).
The device can be put into standby mode using
Chip En able (E1) or in Power-Down mode by us-
ing Chip Enable (E2).
The device features various kinds of Power-Down
modes for power saving as a user configurable op-
tion:
■The Partial Array Refresh (PAR) performs a
limited refresh of the part of the PSRAM array
(4 Mb its, 8 Mbits, 16Mbits) that contains
essential data.
■Deep Power-Down mode: this mode achieves
a very low current consumption by halting all
the internal activities. Since the refresh
circuitry is halted, the duration of the power-
down should be less than the maximum period
for refre sh.
Figure 2. Logic Diagram Table 1. Signal Names
AI05844c
21
A0-A20
W
DQ0-DQ15
VCC
M69AW048B
G
16
E1
UB
LB
VSS
E2
A0-A20 Address Input
DQ0-DQ15 Data Input/Output
E1, E2 Chip Enable, Power Down
GOutput Enable
WWrite Enable
UB Upper Byte Enable
LB Lower Byte Enable
VCC Supply Voltage
VSS Ground
NC Not Conn ect ed
(no internal connection)
5/29
M69AW048B
Figure 3. TFBGA Connections (Top view through package)
AI07242
A
654321
E
B
F
A1
A0G
LB
A17
DQ7WA12
A20A11A8A18
DQ0A3
A6A5
A4 E1
A10
A9
A13
A7
A2 E2
C
DQ4
D
DQ5
A14 A15
G
H
DQ11
A19
UB
DQ10
DQ12
DQ13
VSS
DQ15
DQ8
DQ9
DQ14
DQ3
DQ2DQ1
VCC
VCC NC VSS
DQ6
A16
M69AW048B
6/29
SIGNAL DESCRIPTIONS
See Figure 2., Logic Diagram, and Table
1., Signal Names, for a brief overview of the sig-
nals connected to this device.
Address Inputs (A0-A20). The Address Inputs
select the cells in the memory array to access dur-
ing Read and Write operations.
Data Inputs/Outputs (DQ8-DQ15). The Upper
Byte Data Inputs/Outputs carry the data to or from
the upper part of the selected address during a
Write or Read operation, when Upper Byte Enable
(UB) is driven Low.
Data Inputs/Outputs (DQ0-DQ7). The Lower
Byte Data Inputs/Outputs carry the data to or from
the lower part of the selected address during a
Write or Read operation, when Lower Byte Enable
(LB) is driven Low.
Chip Enable (E1). When asserted (Low), the
Chip En able, E1, activates t he memory state ma-
chine, address buffers and decoders, allowing
Read and Write operations to be performed. When
de-asserted (High), all other pins are ignored, and
the device is put, automatically, in low-power
Standby mode.
Chip Enable (E2). The Ch ip En abl e, E2, put s the
device in P ower-dow n mode (Dee p Pow er-Down,
PAR and Standby) when it is driven Low. One of
these, Deep Power-Down mode, is the lowest
power mode.
Output Enable (G). The Output Enable, G, pro-
vides a high speed tri-state control, allowing fast
read/write cycles to be achieved with the common
I/O data bus.
Write Enable (W). The Writ e En a bl e, W, controls
the Bus Write operation of the memory’s Com-
mand Interface.
Upper By te E nab le ( UB). The Upper Byte En-
able, UB, gates the data on th e Upper Byte Data
Inputs/Outputs (DQ8-DQ15) to or from the upper
part of the selected address during a Write or
Read operation.
Lower Byte Enable (LB). The Lower Byte En-
able, LB, gates the data on the Lower Byte Data
Inputs/Outputs (DQ0-DQ7) to or from the lower
part of the selected address during a Write or
Read operation.
VCC Supply Voltage. The VCC Supply Voltage
supplies the power for all operations (Read, Write,
etc.) and for driving the refresh logic, even when
the device is not being accessed.
VSS Ground. The VSS Ground is the reference for
all voltage measurements.
7/29
M69AW048B
Figure 4. Block Diagram
AI07221b
DYNAMIC
MEMORY
ARRAY
ROW DECODER
COLUMN
DECODER
CONTROL
LOGIC
E1
REFRESH
CONTROLLER
ARBITRATION
LOGIC
INTERNAL
CLOCK
GENERATOR
INPUT/OUTPUT
BUFFER
ADDRESS
UB
E2
G
W
LB
POWER
CONTROLLER
VCC
VSS
ADDRESS
DQ0-DQ7
DQ8-DQ15
M69AW048B
8/29
OPERATION
Operational modes are determined by device con-
trol inputs W, E1, E2, LB and UB as summarized
in the Operating Modes table (see Table
2., Operating Modes).
Power-Up Sequence
Because the internal control logic of the
M69AW048 B needs to b e i ni tia li ze d, th e following
Power-Up procedure mus t be followed before the
memory is used:
– Apply power and wait for VCC to stabilize,
– Wait 300µs while driving both Chip Enable
signals (E1 and E2) High.
See also Figure 24. for details on the Power-Up
AC waveforms.
Read Mode
The device is in Read mode when:
– Write Enable (W) is High and
– Output Enable (G) Low and
– the two Chip Enable signals are asserted
(E1 is Low, and E2 is High).
The time ta ken to e nter Read m ode (tELQV, tGLQV
or tBLQV) depends on which of the above signals
was the last to reach the appropriate level.
Data out ( DQ15-DQ0) may be indetermi nate dur-
ing tELQX, tGLQX and tBLQX but data will always be
valid dur in g tAVQV. See Fi gur es 7, 8, 9, 10 an d 11
and Table 11., Read Mode AC Characteristics, for
details of when the outputs become valid.
Write Mode
The device is in Write mode when
– Write Enable (W) is Low and
– Chip Enable (E1) is Low and E2 is High
– at least one of Upper Byte Enable (UB)
and Lower Byte Enable (LB) is Low.
The Write cycle begins just after the event (the fall-
ing edge) that cau ses the las t of thes e condit ions
to become true (tAVWL or tAVEL or tAVBL).
The Write cycle is terminated by the rising edge of
Write Enable (W) or Chip En able (E 1), whichever
occurs first.
If the device is in Write mode (Chip Enable (E1) is
Low, Output Enable (G) is Low, Upper Byte En-
able (UB ) and/or Lowe r Byte Enab le (LB) is Low,
then Write Enable (W) will return the outputs to
high impedance within tWHDZ of its rising edge.
Care must be taken to avoid bus contention in this
type of o peration. Data inpu t must be vali d for tD-
VWH before the rising edge of Write Enable (W), or
for tDVEH before the rising edge of Chip Enable
(E1), whichever occurs first, and remain valid for
tBHDZ, tWHDZ, tEHDZ.
See Figu res 12, 13, 14, 15, 16 and 17 and Table
12., Write Mode AC Characteristics, for details of
when the outputs become valid.
Standby Mode
The device is in Standby mode when:
– Chip Enable (E1)isHigh and
– Chip Enable (E2) is High
The inpu t/output bu ffers and th e decoding/c ontrol
logic are swi tched off, bu t the dynamic ar ray con-
tinues to be refreshed. In this mode , the memory
current consumption, ISB, is reduced, and the data
remains valid.
See Figures 17 and Table 13., Standby/Power-
Down Mode AC Characteristics, for details of
when the outputs become valid.
Power-down Modes
Description of Power-Down Modes. The
M69AW048 B has four P ower-do wn mod es, De ep
Power-Down, 4 Mbit Partial Array Refresh, 8 Mbit
Partial Array Refresh, and 16 Mbit Partial Array
Refresh (see Table 4. and Figure 22.).
These can be entered using a series of read and
write operations. Each mode has following fea-
tures. The de fault st ate is Deep P ower-Down and
it is the lowest power consumption but all data will
be lost once E2 is brought Low for Power-down.
No sequence is required to put the device in Deep
Power-Down mode after Power-up.
The device is in one of the Power-down modes
when:
– Chip Enable (E2) is Low
All the device logic is switch ed off an d all i nternal
operations are suspended. This gives the lowest
power consumption. In this operating mode, no re-
fresh is per formed, and d ata is los t if the durati on
is longer than 10 ns. This mode i s useful for thos e
applications where the data contents are no longer
needed, and can be lost, but where reduced cur-
rent consumption is of major importance.
Power-Down Program Sequence. The Power-
Down Program sequence is used to program the
Power-Down Configuration. It requires a total of
six read and write operations, with specific ad-
dresses and data. Between each read or write op-
eration the device must be in Standby mode.
Table 4. shows the sequence. In the first cycle, the
Byte at the highest memory address (MSB) is read.
In the second and third cycles, the data ( RDa) read
by first cycle are written back. If the third cycle is
written into a different address, the sequence is
aborted, and the data written by the third cycle is
valid as in a normal write operation. In the fourth
and fifth cycles, the Power-Down Configuration
data is written. T he data of the fourth cycle must be
9/29
M69AW048B
set to ‘0000h’, and the data of the fifth cycle is the
Power-Down Configuration data (see Table
5., Power-Down Configuration Data). If the fourth
cycle is written into a different address, the se-
quence is aborted. In t he last cycle, a read is made
from the specific Power-Down Configuration ad-
dress (see Table 6., Power-Down Configuration
Addresses). The Power-Down Configuration data
and address must correspond, otherwise the se-
quence is aborted.
When this sequence is performed to take the de-
vice from one PAR mode to another, the write data
may be lost. So, if a PAR mode is used, this se-
quence should be performed prior to any normal
read or write operation s.
Table 2. Operating Modes
Note: X = VIH or VIL.
1. Should not be kept in this logic condition for a period longer than 1µs.
2. Power-Down mode can be entered from Standby state and all DQ pins are in High-Z state. The Power-Down current and data re-
tention depend on the selection of Power-Down programming.
3. G can be VIL during the Write operation if the following conditions are satisfied:
a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;
b. G stays VIL dur i ng the ent ire Wr i te cycle.
Table 3. Power-Down Modes
Operation E1 E2 W GLB UB DQ0-DQ7 DQ8-DQ15 Power
Standby (Dese lec te d) VIH VIH X X X X Hi-Z Hi-Z Standby (ISB)
Power-Down (2) XVIL X X X X Hi-Z Hi-Z Power-Down
(ICCPD, ICCP4,
ICCP8, ICCP16)
No Read (1) VIL VIH VIH VIL VIH VIH Hi-Z Hi-Z Output Dis able
Lower Byte Read (1) VIL VIH VIH VIL VIL VIH Data Output Hi-Z Active (ICC)
Lower Byte Write (1) VIL VIH VIL VIH VIL VIH Data Input Hi-Z Active (ICC)
No Write VIL VIH VIL VIH VIH VIH Hi-Z Hi-Z Output Dis able
Upper Byte Read (1) VIL VIH VIH VIL VIH VIL Hi-Z Data Output Active (ICC)
Upper Byte Write (1) VIL VIH VIL VIH VIH VIL Hi-Z Data Input Active (ICC)
Wor d R ead (1) VIL VIH VIH VIL VIL VIL Data Output Data Output Active (ICC)
Wor d Wr i te (1) VIL VIH VIL VIH(3) VIL VIL Data Input Data Input Active (ICC)
Mode Data Retention Retention Address
Deep Power-Down (Default) No N/A
4Mb PAR 4 Mbit 00000h – 3FFFFh
8Mb PAR 8 Mbit 00000h – 7FFFFh
16Mb PAR 16 Mbit 00000h – FFFFFh
M69AW048B
10/29
Table 4. Power-Dow n Program Sequence
Note: 1. PDC Power-Down Configuration.
Table 5. Power-Down Configuration Data
Table 6. Power-Down Configuration Addresses
Cycle # Operation Address Data
1st Read 1FFFFFh (MSB) Read Data (RDa)
2nd Write 1FFFFFh RDa
3rd Write 1FFFFFh RDa
4th Write 1FFFFFh 0000h
5th Write 1FFFFFh PDC Da ta(1)
6th Read PDC Address(1) Read Data (RDb)
Power-Down Modes Power-Down Configuration Data
DQ15–DQ9 DQ8-DQ2 DQ1 DQ0
Deep Power-Down
(default) 0011
4Mb PAR 0 0 1 0
8Mb PAR 0 0 0 1
16Mb PAR 0000
Power-Down Modes Power-Down Configuration Addresses
A20 A19 A18–A0 Binary
Deep Power-Down
(default) 1 1 1 1FFFFFh
4Mb PAR 0 1 1 0FFFFF h
8Mb PAR 1 0 1 17 FF FF h
16Mb PAR 0 0 1 07FFFFh
11/29
M69AW048B
MAXIMUM RATING
Stressing the dev ice above the ratin g lis ted in the
Absolute Maximum Ratin gs table ma y cause pe r-
manent damage to the device. Ex posur e to Ab so -
lute Maximum Rating conditions for extended
periods may affect device reliability. These are
stress ratings only and operation of th e device at
these or any other conditions above those indicat-
ed in the Operating sections of this specification is
not implied. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 7. Absolute Maximum Ratings
Symbol Parameter Min Max Unit
IOOutput Current –50 50 mA
TAAmbie nt Op era tin g Tem p era tur e –30 85 °C
TSTG Storage Temperature –55 125 °C
VCC Core Supply Voltage –0.5 3.6 V
VIO Input or Output Voltage –0.5 3.6 V
M69AW048B
12/29
DC AND AC PARA METERS
This section summarizes the operating measure-
ment condi tions, an d the DC and AC characteri s-
tics of the device. The parameters in the DC and
AC characteristics Tables that follow, are derived
from tests performed under the Measurement
Conditions summarized in Table 8., Operating and
AC Measurement Conditions. Designers should
check that the operating conditions in their circuit
match the operating conditions when relying on
the quoted parameters.
Table 8. Operating and AC Measurement Conditions
Note: 1. All voltages are referenced to VSS.
2. The Input Tra nsition Time used in AC measurements is 5ns. For other input transition times, see Table 8.
Figure 5. AC Measurement I/O Waveform Figure 6. AC Measurement Load Circuit
Parameter
M69AW048B
Unit70
Min Max
VCC Supply Voltage12.7 3.3 V
Ambient Operating Temperature –30 85 °C
Load Capacitance (CL)50 pF
Output Circuit Protection Resistance (R1)50 Ω
Input Pulse Voltages 0 VCC V
Input and Output Timing Ref. Voltages VCC/2 V
Output Transition Timing Ref. Voltages VRL = 0.3VCC; VRH = 0.7VCC V
Input Transition Time2 (tτ) between VIL an d
VIH 5ns
AI04831
VCC
I/O Timing Reference Voltage
0V
VCC/2
VCC
Output Timing Reference Voltage
0V
0.7VCC
0.3VCC
AI07222c
VCC/2
OUT
CL includes JIG capacitance
DEVICE
UNDER
TEST
CL
R1
13/29
M69AW048B
Table 9. Capacitance
Table 10. DC Characteristics
Note: 1. Maximum DC voltage on i nput and I/O pins is VCC +0.2V.
During voltage transitions, input may positive overshoot to VCC + 1.0V for a period of up to 5ns .
2. Minimum DC voltage on input or I/O pins is –0.3V.
During voltage transitions, input may positive overshoot to VSS + 1.0V for a period of up to 5ns.
Symbol Parameter Test
Condition Min Max Unit
CIN Input Capacitance on all pins (except DQ) VIN = 0V 5pF
COUT Output Ca pacitanc e VOUT = 0V 8pF
Symbol Parameter Test Condition Min Max Unit
ICC1 VCC Active Curr en t
VCC = 3.3V,
VIN = VIH or VIL,
E1 = VIL and E2 = VIH,
IOUT = 0mA
tRC / tWC =
minimum 30 mA
ICC2 tRC / tWC =
1 µs 3mA
ICC3 VCC Page Read Current
VCC = 3.3V,
VIN = VIH or VIL,
E1 = VIL and E2 = VIH,
IOUT = 0mA, tPRC = min.
10 mA
ICCPD
VCC Power Down Current VCC = 3.3V,
VIN = VIH or VIL,
E2 ≤ 0.2V
Deep
Power-
Down 10 µA
ICCP4 4 Mb PAR 40 µA
ICCP8 8 Mb PAR 50 µA
ICCP16 16 Mb PAR 65 µA
ILI Input Leakage Current 0V ≤ VIN ≤ VCC –1 1 µA
ILO Output Le aka ge Curr en t 0V ≤ VOUT ≤ VCC –1 1 µA
ISB Standby Supply Current CMOS VCC = 3.3V,
VIN ≤ 0.2V or VIN ≥ VCC –0.2V,
E1 = E2 ≥ VCC –0.2V 100 µA
VIH (1) Input High Voltage 0.8VCC VCC + 0.2 V
VIL (2) Input Low Voltage –0.3 0.2VCC V
VOH Output Hig h Voltage VCC = 2.7V, IOH = –0.5mA 2.4 V
VOL Output Lo w Voltage IOL = 1mA 0.4 V
M69AW048B
14/29
Table 11. Read Mode AC Characteristics
Note: 1. Maximum value is applic able if E1 is kept Low without ch ange of addres s input of A3 to A20. If nee ded by syst em operati on, please
contact y our local ST representative for relaxation of the 1000ns limitation.
2. Address should not be changed withi n minimum Read Cycle Time.
3. The output load 50pF with 50Ω terminati o n to VCC*0.5 V.
4. The output load 5pF without any other load.
5. Applicable to A3 to A20 when E1 is kept Low.
6. Applicable only to A0, A1 and A2 when E1 is ke pt Low for the page address access.
7. In case Page Read Cycle is continued with keeping E1 stays Low , E1 must be brought to High within 4µs. In other words, Page
Read Cycle must be closed within 4µs.
8. Applicable when at least two of address inputs among applicable are switched from previous state.
9. Minimum Read Cycle TIme and minimum Page Read Cycle Time must be satisfied.
Symbol Alt. Parameter M69AW048B Unit
Min Max
tAVAX (1,2) tRC Address Valid Time 70 1000 ns
tAVAX2 (1,6,7) tPRC Page Read Cycle Time 25 1000 ns
tAVEH2 (1,6,7) tPRC Page Read Cycle Time 25 1000 ns
tAVEL tASC Address Valid to Chip Enable Low –5 ns
tAVGL tASO Address Valid to Output Enable Low 10 ns
tAVQV (3,5) tAA Address Valid to Output Valid 70 ns
tAVQV2 (3,6) tPAA Page Address Access Time 18 ns
tAXAV (5,8) tAX Address Invalid Time 10 ns
tAXAV2 (6,8) tAXP Page Address Invalid Time 10 ns
tAXQX (3) tOH Data hold from ad dre ss chan ge 3 ns
tBHQX (3) tOH Up pe r/L ow er Byte Enab le Hig h to Ou tpu t Transition 3 n s
tBHQZ (4) tBHZ Up pe r/L ow er Byte Enab le Hig h to Ou tpu t Hi-Z 20 ns
tBLQV (3) tBA Upper/Lower Byte Enable Low to Output Valid 30 ns
tBLQX (4) tBLZ Upper/Lower Byte Enable Low to Output Transition 0 ns
tEHAX (9) tCHAH Chip Enable Hig h to Ad dre ss Inval id –5 ns
tEHEL tCP Ch ip Enab le Hig h to Ch ip En ab le Low 15 ns
tEHQX (3) tOH Ch ip Enable Hig h to Ou tpu t Transition 3 ns
tEHQZ (4) tCHZ Chip Enab le Hig h to Ou tpu t Hi-Z 20 ns
tELAX (1,2) tRC Read Cycle Time 70 1000 ns
tELEH (1,2) tRC Read Cycle Time 70 1000 ns
tELQV (3) tCE Chip Enable Low to Output Valid 70 ns
tELQX (4) tCLZ Chip Enable Low to Output Transition 3 ns
tGHAX tOHAH Outp ut En ab le Hig h to Add re ss Inv ali d –5 ns
tGHQX (3) tOH Outp ut Da ta Hold Time 3 ns
tGHQZ (4) tOHZ Output Enab le Hig h to Ou tpu t Hi-Z 20 ns
tGLQV (3) tOE Output Enable Low to Output Valid 40 ns
tGLQX (4) tOLZ Output Enable Low to Output Transition 0 ns
15/29
M69AW048B
Figure 7. Read Mode AC Waveforms
Note: E2 = High, W = High.
Figure 8. Output Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W) = High, E2 = High.
A0-A20
E1
G
LB, UB
VALID DATA OUTPUT
DQ0-DQ15
tAVEL
tELQV
ADDRESS VALID VALID
tEHAX
tAVEL
tEHEL
tEHQZ
tGHQZ
tBHQZ
tEHQX
tGLQV
tBLQV
tBLQX
tGLQX
tELQX
AI08986
tELEH
ADDRESS VALID ADDRESS VALIDA0-A20
E1
G
UB, LB
DATA OUT DATA
OUT
DQ0-DQ15
tAVAX
tAXAV tAVAX
tAXAV tAXAVtAVQV tAVQV
tGLQV
tGLQX tAXQX tGHQZ
tGHQX
AI08987
tAVGL tGHAX
M69AW048B
16/29
Figure 9. UB/LB Controlled, Read Mode AC Waveforms
Note: E1 = Low, E2 = High, G = Low, W = High.
Figure 10. Page Address and Chip Enable Controlled, Read Mode AC Waveforms
Note: Write Enable (W) = High, E2 = High.
A0-A20 ADDRESS VALID
E1
LB
UB
DQ0-DQ7
DQ8-DQ15 VALID DATA OUTPUT
VALID DATA OUT VALID DATA OUT
tAVAX tAXAVtAXAV
tAVQV
tBLQV
tBLQX tBHQX
tBHQZ
tBLQX
tBLQV
tBLQV
tBLQX tBHQX
tBHQZ
tBHQX
tBHQZ
ai08990
Low
A20-A3
A2-A0 ADDRESS VALID ADDRESS VALID
ADDRESS
VALID
E
G
LB, UB
tELEH
tAVEL tELAX
tAVQV2
tAXQX
tAVAX2
tAXQX tAXQX
tAVQV2 tAVQV2
tEHQX
tEHQZ
tEHAX
tAVEH
tELQX
tELQV
ADDRESS VALID
ADDRESS
VALID
AI08991
DQ0-DQ15
tAVAX2
tAVAX
tAVQV tAXAV2 tAXAV2 tAXAV2
VALID DATA
OUTPUT VALID DATA
OUTPUT
VALID DATA
OUTPUT
VALID DATA
OUTPUT
17/29
M69AW048B
Figure 11. Random and Page Address Controlled, Read Mode AC Waveforms
Note: E2 = High.
A20-A3
A2-A0 ADDRESS
VALID
E
G
LB, UB
tAVAX
tAXAV
tAXAV2
tAVAX
tAVQV2
tAXQX
tAVQV
tGLQX
tBLQX
tGLQV
ADDRESS VALID
ADDRESS
VALID
AI08992
DQ0-DQ15
ADDRESS
VALID ADDRESS
VALID
ADDRESS VALID
DATA
OUT
(Normal Access)
DATA
OUT
(Normal Access)
DATA
OUT
(Page Access)
DATA
OUT
(Page Access)
tAVAX tAXAV
tAXAV
tAVAX2
tAXAV2
tAVAX tAVAX2
tAVQV
tAVQV2
Low
tBLQV
tAXQX tAXQX tAXQX
M69AW048B
18/29
Table 12. Write Mode AC Characteristics
Note: 1. Maximum value is applicable if E1 is kept Low without any address change. If needed by system operation, please contact your
local ST representative for relaxation of the 1000ns limitation.
2. Minimum value must be equal to or greater than the sum of write pulse (tELEH, tWLBH or tBLBH) and write recovery time (tEHAX,
tWHAX or tBHAX).
3. Write pulse is defined from the falling edge of E1, W, or LB/UB, whichever occurs last .
4. Write recovery is defined from Write puls e is defined from th e rising edge of E1 , W, or LB/UB, whichever occurs first.
5. Applicable to any address change when E1 stays Low.
6. If G is Low after minimum tGHEL, the read cycl e is in itia te d. In ot her wor ds, G must be brought High within 5ns after E1 is brought
Low. Once the read cycle is initiated, new write pulse shou ld be input after minimum Read Cycl e T i me is met.
7. If G is Low after new address input, the read cycle is initiated. In other words, G must be brought High at the same time or before
new address valid. Once the read cycle is initiated, new write puls e s hould be input afte r minimum Read Cycle Time is met.
Symbol Alt. Parameter M69AW048B Unit
Min Max
tAVAX (1,2) tWC Write Cycle Time 70 1000 ns
tAVBL (2) tAS Address Val id to LB, UB Low 0 ns
tAVEL (2) tAS Address Valid to Chip Enable Low 0 ns
tAVWL (2) tAS Address Valid to Write Enable Low 0 ns
tAXAV (5) tAXW Addre ss Inv ali d Time for Write 10 ns
tBHAX (4) tBR LB, UB High to Address Transition 15 1000 ns
tBHDZ tDH LB, UB High to Input High-Z 0 ns
tBLBH (3) tBW LB, UB Low to LB, UB High 45 ns
tBLBH2 tBWO LB, UB Low to LB, U B High for Page Access 20 ns
tBLWH (3) tBW LB, UB Low to Write Enable High 45 ns
tDVBH tDS Input Valid to LB, UB High 20 ns
tDVEH tDS Input Valid to Chip Enable High 20 ns
tDVWH tDS Input Valid to Write Enable High 20 ns
tEHAX (4) tWRC Chip Enable High to Address Transition 15 ns
tEHDZ tDH Chip Enable High to Input High-Z 0 ns
tEHEL tCP Chip Enable High to Chip Enable Low 15 ns
tELAX (1,2) tWC Write Cycle Time 70 1000 ns
tELEH (3) tCW Chip Enable Low to Chip Enable High 45 ns
tGHAV (7) tOES Output Enable High to Address Valid 0 ns
tGHEL (6) tOHCL Output Enable High to Chip Enable Low –5 ns
tGHDZ (4) tOHZ Output Enable High to Output Hi-Z 20 ns
tWHAX (4) tWR Write Enable High to Address Transition 15 1000 ns
tWHDZ tDH Write Enable High to Input High-Z 0 ns
tWLBH (3) tWP Write Enable Low to LB, UB High 45 ns
tWLWH (3) tWP Write Enable Low to Write Enable High 45 ns
19/29
M69AW048B
Figure 12. Chip Enable Controlled, Write AC Waveforms
Note: E2 = High.
Figure 13. Write Enable Controlled, Write AC Waveforms
Note: E2 = High.
ADDRESS VALID
A0-A20
E1
W
LB, UB
G
DQ0-DQ15
tELAX
tELEH
tWLWH
tAVEL tAVEL
tEHAX
tAVWL tAVWL
tWHAX
tBHAX
tBLWHtAVBL tAVBL
tGHEL
VALID DATA INPUT
tDVEH
tDVWH
tDVBH
tEHDZ
tWHDZ
tBHDZ
ai08993
ADDRESS VALID
A0-A20 ADDRESS V ALID ADDRESS V ALID
Low
tAVAX tAVAX
tAVWL tWLWH tAVWL tWLWH
tGHAV
tGHDZ
DQ0-DQ15
tWHDX
tDVWH
tWHDZtDVWH
AI08994b
E1
W
LB, UB
G
VALID DATA
INPUT VALID DATA
INPUT
tWHAX
tWHAX
tAXAV
M69AW048B
20/29
Figure 14. Write Enable and UB/LB Controlled, Write AC Waveforms 1
Note: E2 = High.
Figure 15. Write Enable and UB/LB Controlled, Write AC Waveforms 2
Note: E2 = High.
A0-A20 ADDRESS V ALID ADDRESS V ALID
Low
tAXAV
tAVAX tAVAX
tAVWL tWLBH
tBHAX
tAVWL
tBHAX
E1
W
VALID DATA
INPUT
VALID DATA
INPUT
tWLBH
DQ0-DQ7
DQ8-DQ15
LB
UB
tDVBH tBHDZ
tDVBH tBHDZ
AI08995b
A0-A20 ADDRESS V ALID ADDRESS V ALID
Low
tAVAX tAVAX
tAVBL tBLWH
tWHAX
tAVBL
tWHAX
E1
W
VALID DATA
INPUT
VALID DATA
INPUT
tBLWH
DQ0-DQ7
DQ8-DQ15
LB
UB
tDVWH tWHDZ
tDVWH tWHDZ
AI08996b
tAXAV
tAXAV
21/29
M69AW048B
Figure 16. Write Enable and LB/UB Controlled, Write AC Waveforms 3
Note: E2 = High.
Figure 17. Write Enable and LB/UB Controlled, Write AC Waveforms 4
Note: E2 = High.
A0-A20
Low
tAVAX tAVAX
tAVBL tBLBH
tBHAX
tAVBL
tBHAX
E1
W
VALID DATA
INPUT
VALID DATA
INPUT
tBLBH
DQ0-DQ7
DQ8-DQ15
LB
UB
tDVBH tBHDZ
tBVWH tBHDZ
AI08997b
ADDRESS V ALID ADDRESS V ALID
tAXAV
tAXAV
A0-A20
Low
tAVAX tAVAX
tAVBL tBLBH
E1
W
VALID DATA
INPUT
VALID DATA
INPUT
DQ0-DQ7
DQ8-DQ15
LB
tDVBH tBHDZ
AI08998b
tBHAX
tDVBH tBHDZ
VALID DATA
INPUT
UB
VALID DATA
INPUT
tAVBL
tBLBH
tBHAX
tDVBH tBHDZ
tBLBH2
tBLBH
tBLBH2
tBLBH
tDVBH tBHDZ
tAVBL tBHAX
tAVBL
tBHAX
ADDRESS V ALID ADDRESS V ALID
tAXAV
tAXAV
M69AW048B
22/29
Figure 18. Chip Enable Controlled, Read Followed by Write Mode AC Waveforms
Note: Write address is valid from either E1 or W of last falling edge.
Figure 19. E1, W, G Controlled, Read and Write Mode AC Waveforms
Note: G can be Low fixed in write operation under E1 control read-write-read operation.
WRITE ADDRESS READ ADDRESS
A0-A20
READ DATA
OUTPUT WRITE DATA
INPUT
DQ0-DQ15
E1
W
UB, LB
G
tEHAX
(read)
tELAX tELAX(read)
tEHAX(read)tEHAXtAVEL tAVEL
(read)
tELEH tELQVtEHEL tEHEL
tGHEL
tEHQX
tEHQZ
tEHQX
tELQX
tDVEH tEHDZ
ai08999b
READ DATA
OUTPUT
WRITE ADDRESS READ ADDRESS
A0-A20
READ DATA
OUTPUT WRITE DATA
INPUT
DQ0-DQ15
E1
W
UB, LB
G
tEHAX
(read)
tELAX tELAX(read)
tEHAX(read)tAVEL tAVEL
(read)
tELEH tELQVtEHEL tEHEL
tGHEL
tEHQX
tEHQZ tGHQX
tGLQX
tDVWH tWHDZ
ai09400b
tWHAX
tWLWH
tGHQV
READ DATA
OUTPUT
23/29
M69AW048B
Figure 20. Output Enable and Write Enable Controlled, Read and Write Mode AC Waveforms
Note: E1 can be tied to Low for W and G controlled operation.
When E1 is tied to Low, output is exclusively controlled by G.
Figure 21. Output Enable, Write Enable and UB/LB Controlled, Read and Write Mode AC
Waveforms
Note: E1 can be tied to Low for W and G controlled operation.
When E1 is tied to Low, output is exclusively controlled by G.
WRITE ADDRESS READ ADDRESS
A0-A20
DATA
OUT DATA
IN
DQ0-DQ15
E1
W
UB, LB
G
tWHAXtWLWH
tGHQX
tGHQZ
tGHQX
tGLQX
tDVWH tWHDZ
ai09401b
DATA
OUT
tGLQV
tAVAX tAVAX(read)
tAVQV
tAVGL
tGHQZ
Low
tAVWL
tAXAV
tAXAV
A0-A20
DATA
OUT DATA
IN
DQ0-DQ15
E1
W
UB, LB
G
tBHAXtBLBH
tBHQX
tBHQZ
tBHQX
tBLQX
tDVBH tBHDZ
ai09402b
DATA
OUT
tBLQV
tAVAX tAVAX(read)
tAVBL
tAVQV
tAVGL
tBHQZ
Low
WRITE ADDRESS READ ADDRESS
tAXAV
tAXAV
M69AW048B
24/29
Table 13. Standby/Power-Down Mode AC Characteristics
Note: 1. Applicable also to Power-up.
2. Applicable when 4Mb, 8Mb and 16Mb PAR mode is programmed
3. Some data might be written into any address location if tEHWL (min ) is no t sa tisf ie d.
4. The Input Transition Time (tτ) at AC testing is 5ns as shown below. If actual tτ is longer th an 5ns, it may violat e AC specific ation of
some timing parameters.
Figure 22. Power Down Program AC Waveforms
Note: 1. E2 = High.
2. All address input s must be High from Cycle 1 to Cycle 5.
3. PDCADD stands for Power-Down Configuration Address. It must be compliant with the format specified in Table 6 otherw ise th e
data programmed during the Power-Down Program sequence may be incorrect.
4. PDCDAT stands for Power-Down Configuration Data. It must be compliant with the format specified in Table 5 otherwis e the data
programmed during the Power-Down Program sequence may be incorrect.
5. tEHEL after the end of Cycle 6, the Power Down Program is completed and the device ret urns to normal operation.
Symbol Alt. Parameter M69AW048B Unit
Min Max
tCLEX tCSP E2 Low Setup Time for Power Down Entry 10 ns
tEXCH tC2LP E2 Low Hold Time after Power Down Entry 70 ns
tEHEV (1) tCHH E1 High Hold Time following E2 High after Power-
Down Exit (Deep Power-Down Mode only) 300 µs
tCHEL (2) tCHHP E1 High Hold Time following E2 High after Power-
Down Exit (not in Deep Power-Down Mode) 1µs
tEHCH tCHS E1 High Setup T ime following E2 High after Power-
Down Exit 0µs
tEHGL tCHOX E1 High to G Invalid Time for Standby Entry 10 ns
tEHWL (3) tCHWX E1 High to W Invalid Time for Standby Entry 10 ns
tτ (4) tτInput Transition Time 1 25 ns
AI07225c
A0-A20
E1
W
DQ0-DQ15
MSB 2
G
MSB 2MSB 2MSB 2MSB 2PDCADD3
LB, UB
tAXAV tAXAVL
4
tAVAX
RDaRDa RDa 00 PDCD
4
RDb
Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6
25/29
M69AW048B
Figure 23. Power-Down Mode AC Waveforms
Figure 24. Power-Up Mode AC Waveforms
Figure 25. Standby Mode Entry AC Waveforms, After Read
Note: E2 = High.
E2
E1
AI09403
Power-Down
Entry Power-Down Mode
DQ0-D15
tEHCH
tCLEX tEXCH tCHEL
Power-Down
Exit
Hi-Z
AI09404
VDD
tEHEL
VDDmin
E1
E2
G
E1
AI09405
W
tEHGL
Read Active Standby
tEHWL
Write Active Standby
M69AW048B
26/29
PACKAGE MECHANICAL
Figure 26. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Outline, Bottom View
Note: Drawing is not to scale.
Table 14. TFBGA48 6x8mm - 6x8 ball array, 0.75 mm pitch, Package Mechanical Data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.260 0.0102
A2 0.900 0.0354
b 0.350 0.450 0.0138 0.0177
D 6.000 5.900 6.100 0.2362 0.2323 0.2402
D1 3.750 – – 0.1476 – –
ddd 0.100 0.0039
E 8.000 7.900 8.100 0.3150 0.3110 0.3189
E1 5.250 – – 0.2067 – –
e 0.750 – – 0.0295 – –
FD 1.125 – – 0.0443 – –
FE 1.375 – – 0.0541 – –
SD 0.375 – – 0.0148 – –
SE 0.375 – – 0.0148 – –
E1E
D1
D
eb
A2
A1
A
BGA-Z26
ddd
FD
FE SD
SE
e
BALL "A1"
27/29
M69AW048B
PART NUMBERING
Table 15. Ordering Information Scheme
The nota tion u sed fo r the de vi ce nu mber is as s hown i n Table 15.. For a list of available opti ons (spe ed,
package, etc.) or for further infor mation on any aspec t of thi s devic e, ple ase con tact y our near est S TMi-
croelectron ics Sales Office.
Example: M69AW048 B L 70 ZB 8
Device Type
M69 = PSRAM
Mode
A = Asynchronous
Operatin g Voltage
W = 2.7 to 3.3V
Array Organization
048 = 32 Mbit (2M x16)
Option 1
B = 2 Chip Enable
Option 2
L = Low Leakage
Speed Class
70= 70 ns
Package
ZB = TFBGA4 8, 0.7 5m m pitch
Operative Temperature
8 = –30 to 85 °C
M69AW048B
28/29
REVISION HISTORY
Table 16. Document Revision History
Date Version Revision Details
07-Oct-2002 -01 First Issue
10-Mar-2 00 3 2.0 Do cu me nt co mp let ely revis ed
9-Mar-2004 3.0
Data Key and Address Key renamed Power-Down Configuration data and Power-Down
Configuration Address respectively. Sleep mode renamed Deep Power-Down mode.
ICCS removed and IPD renamed ICCPD in Table 10., DC Characteristics.
Partial mode renamed Partial Array Refresh.
Table 12. Write Mode AC Characteristics: tGHDZ added and Note 2 updated.
tGHQZ changed to tGHDZ in Figure 13.Write Enable Controlled, Write AC Waveforms.
AC Waveforms conve r ted to ST standard.
21-Sep-2004 4.0 tELQZ, tGLQZ, tBLQZ changed into tELQX, tGLQX, tBLQX in Table 11., Read Mode AC
Characteristics.
15-Nov-2004 5.0 VOH value updated in Tab le 10 ., D C Ch ara cte ris tic s.
29/29
M69AW048B
Informatio n furnis hed is believ ed to be a ccurate and reli able. Howe ver, STMic roelectr onics assumes no r esponsib ility for th e consequences
of use of such informat ion nor for any inf ringement of pate nts or other rights of third p arties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change wi thout notic e. T his pub licat ion su persed es and repl aces all info rmat ion previou sly su pplie d. STMicroele ctro nics prod ucts ar e not
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