TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com 7-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE Check for Samples: TUSB2077A * * * * * * * PT PACKAGE (TOP VIEW) SUSPND DP0PUR DP0 DM0 GND RESET EECLK EEDATA/GANGED VCC BUSPWR PWRON1 OVRCUR1 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 PWRON7 DP6 DM6 OVRCUR6 PWRON6 DP5 DM5 OVRCUR5 PWRON5 DP4 DM4 OVRCUR4 DM1 DP1 PWRON2 OVRCUR2 DM2 DP2 PWRON3 OVRCUR3 DM3 DP3 PWRON4 GND * * 46 45 44 43 42 41 40 39 38 37 * MODE EXTMEM VCC XTAL1/CLK48 XTAL2 GND PORTDIS PORTPWR HUBCFG DP7 DM7 OVRCUR7 * * * Fully Compliant With the USB Specification as a Full-Speed Hub: TID #20240226 Integrated USB Transceivers 3.3-V Low Power ASIC Logic Two Power Source Modes - Self-Powered Mode Supporting Seven Downstream Ports - Bus-Powered Mode Supporting Four Downstream Ports All Downstream Ports Support Full-Speed and Low-Speed Operations Power Switching and Overcurrent Reporting Is Provided Ganged or Per Port Supports Suspend and Resume Operations Suspend Status Terminal Available for External Logic Power Down Supports Custom Vendor ID and Product ID With External Serial EEPROM 3-State EEPROM Interface Allows EEPROM Sharing Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes Supports 6-MHz Operation Through a Crystal Input or a 48-MHz Input Clock New Functional Terminals Introduced to Reduce the Board Material Cost - 3 LED Indicator Control Outputs Enable Visualized Monitoring of 6 Different Hub/Port Status (HUBCFG, PORTPWR, PORTDIS) - Output Terminal Available to Disable External Pullup Resistor on DP0 for 15 ms After Reset or After Change on BUSPWR and Enable Easy Implementation of Onboard Bus/Self- Power Dynamic Switching Circuitry Available in 48-Terminal LQFP Package (1) 48 47 * * 13 14 15 16 17 18 19 20 21 22 23 24 FEATURES 1 NC - No internal connection (1) JEDEC descriptor S-PQFP-G for low-profile quad flatpack (LQFP). xxx 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA ORDERABLE PART NUMBER Reel of 250 0C to 70C (1) (2) LQFP - PT Reel of 1000 TOP-SIDE MARKING TUSB2077APT TUSB2077APTR TUSB2077A TUSB2077APTRG4 Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. DESCRIPTION The TUSB2077A hub is a 3.3-V CMOS device that provides up to seven downstream ports in compliance with the USB 2.0 specification. Because this device is implemented with a digital state machine instead of a microcontroller, no software programming is required. Fully-compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR terminal selects either the bus-powered or self-powered mode. The introduction of the DP0 pullup resistor disable terminal, DP0PUR, makes it much easier to implement an onboard bus/self-power dynamic-switching circuitry. The three LED indicator control output terminals also enable the implementation of visualized status monitoring of the hub and its downstream ports. With these new function terminals, the end equipment vendor can considerably reduce the total board cost while adding additional product value. The EXTMEM (terminal 47) enables or disables the optional EEPROM interface. When EXTMEM is high, the vendor and product IDs (VID and PID) use defaults, such that the message displayed during enumeration is General Purpose USB Hub. For this configuration, terminal 8 functions as the GANGED input terminal and EECLK (terminal 7) is unused. If custom VID and PID descriptors are desired, the EXTMEM must be tied low (EXTMEM = 0) and a SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID, PID, and GANGED values. For this configuration, terminals 7 and 8 function as the EEPROM interface signals with terminal 7 as EECLK and terminal 8 as EEDATA, respectively. The TUSB2077A supports both bus-powered and self-powered modes. External power-management devices, such as the TPS2044, are required to control the 5-V power source switching (on/off) to the downstream ports and to detect an overcurrent condition from the downstream ports individually or ganged. Outputs from external power devices provide overcurrent inputs to the TUSB2077A OVRCUR terminals in case of an overcurrent condition, the corresponding PWRON terminals are disabled by the TUSB2077A. In the ganged mode, all PWRON signals transition simultaneously, and any OVRCUR input can be used. In the nonganged mode, the PWROR outputs and OVRCUR inputs operate on a per-port basis. The TUSB2077A provides the flexibility of using either a 6-MHz or a 48-MHz clock. The logic level of the MODE terminal controls the selection of the clock source. When MODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the chip. When MODE is high, the XTAL1 input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while MODE is high. For 6-MHz operation, TUSB2077A requires a 6-MHz clock signal on XTAL1 terminal (with XTAL2 for a crystal) from which its internal APLL circuitry generates a 48-MHz internal clock to sample the data from the upstream port. For 48-MHz operation, the clock cannot be generated with a crystal, using the XTAL2 output, since the internal oscillator cell only supports the fundamental frequency. If low-power suspend and resume are desired, a passive crystal or resonator must be used, although the hub supports the flexibility of using any device that generates a 6-MHz clock. Because most oscillators cannot be stopped while power is on, their use prohibits low-power suspend, which depends on disabling the clock. When the oscillator is used, by connecting its output to the XTAL1 terminal and leaving the XTAL2 terminal open, its TTL output level can not exceed 3.6 V. If a 6-MHz oscillator is used, it must be stopped at logic low whenever SUSPND is high. For crystal or resonator implementations, the XTAL1 terminal is the input and the XTAL2 terminal is used as the feedback path. A sample crystal tuning circuit is shown in Figure 7. 2 Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM DP0 3 DM0 4 USB Transceiver 1 SUSPND 1 Hub Repeater M U X Suspend /Resume Logic and Frame Timer 45 0 OSC/PLL 44 SIE 48 6 2 47 SIE Interface Logic 8 Serial EEPROM Interface 7 XTAL1/CLK48 XTAL2 MODE RESET DP0PUR EXTMEM EEDATA/GANGED EECLK Port 1 Logic 40 Hub /Device Command Decoder 42 41 10 Port 4 Logic USB Transceiver 39 38 USB Transceiver 14 Hub Power Logic HUBCFG PORTDIS PORTPWR BUSPWR 12, 16, 20, 25, 29, 33, 37 OVRCUR1 - OVRCUR7 13 11, 15, 19, 23,28, 32, 36 DP7 DM7 DP1 DM1 Copyright (c) 2000-2011, Texas Instruments Incorporated PWRON1 - PWRON7 3 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com TERMINAL FUNCTIONS TERMINAL NAME BUSPWR DM0 DM1-DM7 DP0 NO. I/O 10 I DESCRIPTION Power source indicator. BUSPWR is an active-low input that indicates whether the downstream ports source their power from the USB cable or a local power supply. For the bus-power mode, this terminal must be pulled low, and for the self-powered mode, this terminal must be pulled to 3.3 V. Input must not change dynamically during operation. 4 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port. 13, 17, 21, 26, 30, 34, 38 I/O USB differential data minus. DM1-DM7 paired with DP1-DP7 support up to four downstream USB ports. 3 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port. DP1-DP7 14, 18, 22, 27, 31, 35, 39 I/O USB differential data plus. DP1-DP7 paired with DM1-DM7 support up to four downstream USB ports. DP0PUR 2 O Pullup resistor connection. When a system reset happens (RESET being driven to low, but not USB reset) or any logic level change on BUSPWR terminal, DP0PUR output is inactive (floating) until the internal counter reaches a 15-ms time period. After the counter expires, DP0PUR is driven to the VCC (3.3 V) level thereafter until the next system reset event occurs or there is a BUSPWR logic level change. EECLK 7 O EEPROM serial clock. When EXTMEM is high, the EEPROM interface is disabled. The EECLK terminal is disabled and must be left floating (unconnected). When EXTMEM is low, EECLK acts as a 3-state serial clock output to the EEPROM with a 100-A internal pulldown. EEDATA/ GANGED 8 I/O EEPROM serial data/power-management mode indicator. When EXTMEM is high, EEDATA/GANGED selects between ganged or per-port power overcurrent detection for the downstream ports. When EXTMEM is low, EEDATA/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100-A pulldown. This standard TTL input must not change dynamically during operation. EXTMEM 47 I GND 5, 24, 43 When EXTMEM is high, the serial EEPROM interface of the device is disabled. When EXTMEM is low, terminals 7 and 8 are configured as the clock and data terminals of the serial EEPROM interface, respectively. GND terminals must be tied to ground for proper operation. HUBCFG (1) 40 O Hub configured. Used to control LED indicator. When the hub is configured, HUBCFG is high, which can be used to turn on a green LED. When the hub is not configured, HUBCFG is low, which can be used to turn on a red LED. MODE 48 I Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core of the chip and 6-MHz crystal or oscillator can used. When MODE is high, the clock on XTAL1/CLK48 is selected as the clock source and 48-MHz oscillator or other onboard clock source can be used. OVRCUR1 - OVRCUR7 12, 16, 20, 25, 29, 33, 37 I Overcurrent input. OVRCUR1-OVRCUR7 are active low. For per-port overcurrent detection, one overcurrent input is available for each of the seven downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR terminals must be tied together. OVRCUR terminals are active low inputs with noise filtering logic. PORTPWR (1) 41 O Any port powered. Used to control LED indicator. When any port is powered on, PORTPWR is high, which can be used to turn on a green LED. When all ports are off, PORTPWR is low, which can be used to turn on a red LED. PORTDIS (1) 42 O No ports disabled. PORTDIS is used for LED indicator control. When no port is disabled, PORTDIS is high, which can be used to turn on a green LED. When any port is disabled, PORTDIS is low, which can be used to turn on a red LED. PWRON1 - PWRON7 11, 15, 19, 23, 28, 32, 36 O Power-on/-off control signals. PWRON1-PWRON7 are active low, push-pull outputs that enables the external power switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these terminals must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals. RESET 6 I RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 s and 1 ms is recommended after 3.3-V VCC reaches its 90%. Clock signal has to be active during the last 60 s of the reset window. SUSPND 1 O Suspend status. SUSPND is an active high output available for external logic power-down operations. During the suspend mode, SUSPND is high. SUSPND is low for normal operation. VCC 9, 46 3.3-V supply voltage XTAL1/CLK48 45 I Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high, XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed. XTAL2 44 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal must be left open when using an oscillator. (1) 4 All LED controls are 3-stated during low-power suspend. Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN (2) MAX UNIT VCC Supply voltage range -0.5 3.6 V VI Input voltage range -0.5 VCC + 0.5 V VO Output voltage range -0.5 VCC + 0.5 IIK Input clamp current VI < 0 V or VI < VCC IOK Output clamp current VO < 0 V or VO < VCC Tstg Storage temperature range TA Operating free-air temperature range (1) (2) V 20 mA 20 mA -65 150 C 0 70 C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage levels are with respect to GND. RECOMMENDED OPERATING CONDITIONS PARAMETER MIN NOM 3.3 MAX UNIT VCC Supply voltage 3 3.6 V VI Input voltage, TTL/LVCMOS (1) 0 VCC V VO Output voltage, TTL/LVCMOS (2) 0 VCC V VIH(REC) High-level input voltage, signal-ended receiver 2 VCC V VIL(REC) Low-level input voltage, signal-ended receiver 0.8 V VIH(TTL) High-level input voltage, TTL/LVCMOS (1) 2 VCC V VIL(TTL) Low-level input voltage, TTL/LVCMOS (1) 0 0.8 V TA Operating free-air temperature 0 70 C R(DRV) External series, differential driver resistor f(OPRH) Operating (dc differential driver) high speed mode 12 Mb/s f(OPRL) Operating (dc differential driver) low speed mode 1.5 Mb/s VICR Common mode, input range, differential receiver tt TJ (1) (2) (3) 22 0.8 2.5 V Input transition times, TTL/LVCMOS (1) 0 25 ns Junction temperature range (3) 0 115 C Applies for input and bidirectional buffers. Applies for output and bidirectional buffers. These junction temperatures reflect simulated conditions. Absolute maximum junction temperature is 150C. The customer is responsible for verifying junction temperature. Copyright (c) 2000-2011, Texas Instruments Incorporated 5 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted) PARAMETER TEST CONDITIONS TTL/LVCMOS VOH High-level output voltage USB data lines TTL/LVCMOS VOL Low-level output voltage USB data lines IOH = -4 mA MIN MAX VCC - 0.5 R(DRV) = 15 k to GND 2.8 IOH = -12 mA (without R(DRV)) V VCC - 0.5 IOL = 4 mA 0.5 R(DRV) = 1.5 k to 3.6 V 0.3 IOL = 12 mA (without R(DRV)) 0.5 TTL/LVCMOS VIT+ Positive input threshold VIT- Negative-input threshold Vhys Input hysteresis (1) (VT+ - VT-) IOZ High-impedance output current IIL IIH Single-ended UNIT V 1.8 0.8 V VICR 2.5 V V 1.8 TTL/LVCMOS 0.8 V 0.8 V VICR 2.5 V 1 0.3 0.7 Single-ended 0.8 V VICR 2.5 V 300 500 TTL/LVCMOS V = VCC or GND (2) 10 USB data lines 0 V VO VCC 10 Low-level input current TTL/LVCMOS VI = GND -1 A High-level input current TTL/LVCMOS VI = VCC 1 A z0(DRV) Driver output impedance USB data lines Static VOH or VOL 7.1 19.9 VID Differential input voltage USB data lines 0.8 V VICR 2.5 V 0.2 ICC (1) (2) Single-ended TTL/LVCMOS A V Normal operation Input supply current mV Suspend mode 40 mA 1 A Applies for input buffers with hysteresis. Applies for open drain buffers. DIFFERENTIAL DRIVER SWITCHING CHARACTERISTICS Full Speed Mode over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted) PARAMETER TEST CONDITIONS tr Transition rise time for DP or DM See Figure 1 and Figure 2 tf Transition fall time for DP or DM See Figure 1 and Figure 2 t(RFM) Rise/fall time matching (1) (tr/tf) x 100 VO(CRS) Signal crossover output voltage (1) (1) MIN MAX 4 20 UNIT ns 4 20 ns 90 110 % 1.3 2.0 V Characterized only. Limits are approved by design and are not production tested. DIFFERENTIAL DRIVER SWITCHING CHARACTERISTICS Low Speed Mode over recommended ranges of operating free-air temperature and supply voltage, CL = 50 pF (unless otherwise noted) PARAMETER TEST CONDITIONS (1) MIN MAX UNIT tr Transition rise time for DP or DM CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns tf Transition fall time for DP or DM (1) CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns t(RFM) Rise/fall time matching (1) (tr/tf) x 100 80 120 % CL = 200 pF to 600 pF 1.3 2.0 V VO(CRS) (1) 6 Signal crossover output voltage (1) Characterized only. Limits are approved by design and are not production tested. Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com 22 1.5 k 15 k 22 15 k Figure 1. Differential Driver Switching Load V ID - Diff erential Receiver Input Sensitivity - V Figure 2. Differential Driver Timing Waveforms 1.5 1.3 1 0.5 0.2 0 0 3 1 2 3.6 0.8 2.5 VICR - Common Mode Input Rang e - V 4 Figure 3. Differential Receiver Input Sensitivity vs Common Mode Input Range Vhys Logic high VCC VIH VIT+ VIT- VIL Logic low 0V Figure 4. Single-Ended Receiver Input Signal Parameter Definitions Copyright (c) 2000-2011, Texas Instruments Incorporated 7 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com APPLICATION INFORMATION A major advantage of USB is the ability to connect 127 functions configured in up to 6 logical layers (tiers) to a single personal computer (see Figure 5). PC With Root Hub Monitor With 4-Port Hub (Self-Powered) Printer With 4-Port Hub (Self-Powered) Scanner Digital Scanner Figure 5. USB-Tiered Configuration Example Another advantage of USB is that all peripherals are connected using a standardized four-wire cable that provides both communication and power distribution. The power configurations are bus-powered and self-powered modes. The maximum current that may be drawn from the USB 5-V line during power up is 100 mA. For the bus-powered mode, a hub can draw a maximum of 500 mA from the 5-V line of the USB cable. A bus-powered hub must always be connected downstream to a self-powered hub unless it is the only hub connected to the PC and there are no high-powered functions connected downstream. In the self-powered mode, the hub is connected to an external power supply and can supply up to 500 mA to each downstream port. High-powered functions may draw a maximum of 500 mA from each downstream port and may only be connected downstream to self-powered hubs. Per the USB specification, in the bus-powered mode, each downstream port can provide a maximum of 100 mA of current, and in the self-powered mode, each downstream port can provide a maximum of 500 mA of current. Both bus-powered and self-powered hubs require overcurrent protection for all downstream ports. The two types of protection are individual-port management (individual-port basis) or ganged-port management (multiple-port basis). Individual-port management requires power-management devices for each individual downstream port, but adds robustness to the USB system because, in the event of an overcurrent condition, the USB host only powers down the port that has the condition. The ganged configuration uses fewer power management devices and thus has lower system costs, but in the event of an overcurrent condition on any of the downstream ports, all the ganged ports are disabled by the USB host. Using a combination of the BUSPWR and EEDATA/GANGED inputs, the TUSB2077A supports four modes of power management: bus-powered hub with either individual-port power management or ganged-port power management, and the self-powered hub with either individual-port power management or ganged-port power management. Texas Instruments supplies the complete hub solution because we offer this TUSB2077A along with the power-management devices needed to implement a fully USB compliant system. 8 Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com USB Design Notes The following sections provide block diagram examples of how to implement the TUSB2077A device. Note, even though no resistors are shown, pullup, pulldown, and series resistors must be used to properly implement this device. Figure 6 is a block diagram example of how to connect the external EEPROM if a custom product ID and vendor ID are desired. Figure 7 is an example of how to generate the 6-MHz clock signal. Figure 8 shows the EEPROM read operation timing diagram. Figure 9, Figure 10, and Figure 11 illustrate how to connect the TUSB2077A device for different power source and port power-management combinations. TUSB2077A USB Hub 6-MHz Clock Signal Bus or Local Power 5 V GND 45 XTAL1 44 XTAL2 9, 46 VCC Regulator 3.3 V 6 System Power-On Reset RESET GND 5, 24, 43 47 EXTMEM 3 DP0 4 EEPROM 6 D ORG 8 5 VCC Q EEDATA VSS C 4 13, 17, 21, 26, 30, 34, 38 7 12, 16, 20, 25, 29, 33, 37 8 1 k 7 DM1 - DM7 DM0 3 14, 18, 22, 27, 31, 35, 39 DP1 - DP7 7 EECLK OVRCUR1 - OVRCUR7 PWRON1 - PWRON7 11, 15, 19, 23, 28, 32, 36 7 Power Switching 7 GND USB Data lines and Power to Downstream Ports Vbus 2 S 1 Figure 6. Typical Application of the TUSB2077A USB Hub CL XTAL1 XTAL2 C1 C2 NOTE: This figure assumes a 6-MHz fundamental crystal that is parallel loaded. The component values of C1, C2, and Rd are determined using a crystal from Fox Electronics - part number HC49U-6.00MHz 30\50\070\20, which means 30 ppm at 25C and 50 ppm from 0C to 70C. The characteristics for the crystal include a load capacitance (CL) of 20 pF, maximum shunt capacitance (Co) of 7 pF, and the maximum ESR of 50 . In order to insure enough negative resistance, use C1 = C2 = 27 pF. The resistor Rd is used to trim the gain, and Rd = 1.5 k is recommended. Figure 7. Crystal Tuning Circuit Copyright (c) 2000-2011, Texas Instruments Incorporated 9 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com Programming the EEPROM An SGS Thompson M93C46 EEPROM, or equivalent, stores the programmable VID and PID. When the EEPROM interface is enabled (EXTMEM = 0), the EECLK and EEDATA are internally pulled down (100 A) inside the TUSB2077A. The internal pulldowns are disabled when the EEPROM interface is disabled (EXTMEM = 1). The EEPROM is programmed with the three 16-bit locations as shown in Table 1. Connecting terminal 6 of the EEPROM high (ORG = 1) organizes the EEPROM memory into 64x16-bit words. Table 1. EEPROM Memory Map ADDRESS D15 D14 D13 D12-D8 D7-D0 00000 0 GANGED 00000 00000 00000000 00001 VID High-byte VID Low-byte 00010 PID High-byte PID Low-byte XXXXXXXX The D and Q signals of the EEPROM must be tied together using a 1-k resistor with the common I/O operations forming a single-wire bus. After system power-on reset, the TUSB2077A performs a one-time access read operation from the EEPROM if the EXTMEM terminal is pulled low and the chip select(s) of the EEPROM is connected to the system power-on reset. Initially, the EEDATA terminal is driven by the TUSB2077A to send a start bit (1) which is followed by the read instruction (10) and the starting-word address (00000). Once the read instruction is received, the instruction and address are decoded by the EEPROM, which then sends the data to the output shift register. At this point, the hub stops driving the EEDATA terminal and the EEPROM starts driving. A dummy (0) bit is then output and the first three 16-bit words in the EEPROM are output with the most significant bit (MSB) first. The output data changes are triggered by the rising edge of the clock provided by the TUSB2077A on the EECLK terminal. The SGS-Thompson M936C46 EEPROM is recommended because it advances to the next memory location by automatically incrementing the address internally. Any EEPROM used must have the automatic internal address advance function. After reading the three words of data from the EEPROM, the TUSB2077A puts the EEPROM interface into a high-impedance condition (pulled down internally) to allow other logic to share the EEPROM. The EEPROM read operation is summarized in Figure 8. For more details on EEPROM operation, refer to SGS-Thompson Microelectronics M93C46 Serial Microwire Bus EEPROM data sheet. 10 Copyright (c) 2000-2011, Texas Instruments Incorporated Copyright (c) 2000-2011, Texas Instruments Incorporated D C S Start A5 Hub Driving Data Line Read OP Code(10) Other Address Bits A1 6 Bit Address (000000) A0 Dummy Bit MSB of The First Word D15 Other LSB of Data Bits Third Word D0 EEPROM Driving Data Line D14 48 Data Bits MSB of Fourth Word XX Don't Care 3-Stated With Internal Pulldown TUSB2077A www.ti.com SLLS414D - MARCH 2000 - REVISED AUGUST 2011 Figure 8. EEPROM Read Operation Timing Diagram 11 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com Bus-Powered Hub, Ganged-Port Power Management When used in bus-powered mode, the TUSB2077A supports up to four downstream ports by controlling a TPS2041 device which is capable of supplying 100 mA of current to each downstream port. Bus-powered hubs must implement power switching to ensure current demand is held below 100 mA when the hub is hot-plugged into the system. Utilizing the TPS2041 for ganged-port power management provides overcurrent protection for the downstream ports. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. The OVRCUR signals must be tied together for a ganged operation. TUSB2077A BUSPWR DP0PUR EEDATA/GANGED Upstream Port 1.5 k DP0 D+ D- DM0 SN75240 A C B D 4.7 mF 0.1 mF GND DP1 D+ D- DM1 15 k 15 k A C B D DP2 4.7 mF GND 5V 100 mF 15 k 15 k 5V 3.3 V Ferrite Beads SN75240 DM2 3.3 V LDO 5V Downstream Ports VCC GND D+ D- DP3 Ferrite Beads DM3 GND 15 k XTAL1 15 k A C B D 5V SN75240 6-MHz Clock Signal DP4 100 mF DM4 15 k XTAL2 15 k MODE DP5 - DP7 DM5 - DM7 3.3 V EXTMEM System Power-On Reset RESET PWRON1 EN Ferrite Beads GND IN IN 5V 1 mF PWRON3 100 mF PWRON4 GND D- TPS2041 PWRON2 D+ PWRON5 -7 NC OVRCUR1 OUT OUT OC OUT D+ Ferrite Beads OVRCUR2 DGND OVRCUR3 OVRCUR4 OVRCUR5 -7 5V 3.3 V 100 mF NOTES: TPS2041 and SN75240 are Texas Instruments devices. 120 F per hub is the minimum required per the USB specification. However, TI recommends a 100-F, low ESR, tantalum capacitor per port for immunity to voltage droop. LDO is a 5-V-to-3.3-V voltage regulator All USB DP, DM signal pairs require series resistors of approximately 27 to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 9. TUSB2077A Bus-Powered Hub, Ganged-Port Power-Management Application 12 Copyright (c) 2000-2011, Texas Instruments Incorporated TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com Self-Powered Hub, Individual-Port Power Management In a self-powered configuration, the TUSB2077A can be implemented for individual-port power management when used with two TPS2044 because it is capable of supplying 500 mA of current to each downstream port and can provide current limiting on a per port basis. When the hub detects a fault on a downstream port, power is removed from only the port with the fault and the remaining ports continue to operate normally. Self-powered hubs are required to implement overcurrent protection and report overcurrent conditions. The SN75240 transient suppressors reduce inrush current and voltage spikes on the data lines. TUSB2077A EEDATA/GANGED DP0PUR Upstream Port DP0 D- A C B D 0.1 mF GND D+ D- DM1 15 k 15 k DP2 5V 100 mF 15 k 15 k 4.7 mF GND SN75240 5V 3.3 V A C B D DM2 3.3 V LDO 4.7 mF DM0 SN75240 5V Downstream Ports 3.3 V DP1 1.5 k D+ BUSPWR VCC D+ DP6 GND D- DM6 15 k 15 k A C B D GND SN75240 5V DP7 DM7 XTAL1 6-MHz Clock Signal XTAL2 MODE 3.3 V 100 mF 15 k 15 k PWRON1 EN1 PWRON2 EN2 TPS2044 D+ D- EN3 EXTMEM GND EN4 System Power-On Reset PWRON6 OUT1 PWRON7 OUT2 OVRCUR1 OC1 OUT4 OVRCUR2 OC2 5V OUT3 RESET GND OC3 100 mF D+ IN1 D- IN2 GND OC4 OVRCUR6 0.1 mF 5V OVRCUR7 100 mF 5-V Board Power Supply NOTES: TPS2042 and SN75240 are Texas Instruments devices. Two TPS2042 devices can be substituted for the TPS2044. 120 F per hub is the minimum required per the USB specification. However, TI recommends a 100-F, low ESR, tantalum capacitor per port for immunity to voltage droop. LDO is a 5-V-to-3.3-V voltage regulator. TPS76333 from Texas Instruments can be used. All USB DP, DM signal pairs require series resistors of approximately 27 to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 10. TUSB2077A Self-Powered Hub, Individual-Port Power-Management Application Copyright (c) 2000-2011, Texas Instruments Incorporated 13 TUSB2077A SLLS414D - MARCH 2000 - REVISED AUGUST 2011 www.ti.com Self-Powered Hub, Ganged-Port Power Management The TUSB2077A can also be implemented for ganged-port power management in a self-powered configuration. The implementation is very similar to the bus-powered example with the exception that a self-powered port supplies 500 mA of current to each downstream port. The overcurrent protection can be provided by a TPS2044 quad device or a TPS2024 single power switch. TUSB2077A DP0PUR Upstream Port DP0 D+ D- BUSPWR EEDATA/GANGED 1.5 k DM0 SN75240 3.3 V Downstream Ports DP1 D+ D- DM1 15 k 15 k A C B D 5V A C B D 3.3 V LDO 4.7 mF 0.1 mF GND 3.3 V 4.7 mF VCC GND SN75240 DP2 5V Ferrite Beads 5V DM2 15 k 15 k GND 100 mF D+ DP6 D- DM6 XTAL1 15 k 15 k 6-MHz Clock Signal XTAL2 Ferrite Beads A C B D GND SN75240 DP7 5V DM7 MODE 15 k 15 k 100 mF TPS2044 PWRON1 3.3 V EXTMEM EN1 EN2 RESET GND PWRON7 EN4 OVRCUR1 OC1 OC2 D- IN2 EN3 System Power-On Reset D+ IN1 Ferrite Beads GND 0.1 mF 5V 100 mF OC3 OVRCUR7 OC4 D+ D- OUT1 OUT2 Ferrite Beads GND OUT3 OUT4 5V 100 mF 5 V Board Power Supply NOTES: TPS2044, TPS2042, and SN75240 are Texas Instruments devices. The TPS2024 can be substituted for the TPS2044. 120 F per hub is the minimum required per the USB specification. However, TI recommends a 100-F, low ESR, tantalum capacitor per port for immunity to voltage droop. LDO is a 5-V-to-3.3-V voltage regulator. TPS76333 from Texas Instruments can be used. All USB DP, DM signal pairs require series resistors of approximately 27 to ensure proper termination. An optional filter capacitor of about 22 pF is recommended for EMI suppression. This capacitor, if used, must be placed between the hub terminal and the series resistor, as per section 7.1.6 of the USB specification. Figure 11. TUSB2077A Self-Powered Hub, Ganged-Port Power-Management Application 14 Copyright (c) 2000-2011, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 19-Aug-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) TUSB2077APT ACTIVE LQFP PT 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TUSB2077APTR ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TUSB2077APTRG4 ACTIVE LQFP PT 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. 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Addendum-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TUSB2077APTR Package Package Pins Type Drawing LQFP PT 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.9 12.0 16.0 Q2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB2077APTR LQFP PT 48 1000 367.0 367.0 38.0 Pack Materials-Page 2 MECHANICAL DATA MTQF003A - OCTOBER 1994 - REVISED DECEMBER 1996 PT (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 1,45 1,35 Seating Plane 1,60 MAX 0- 7 0,75 0,45 0,10 4040052 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. 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