TDA9109A - STMicroelectronics

Version 4.2

September 2003 1/47

TDA9109A

LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR

FOR MULTISYNC MONITOR

FEATURES

General

■SYNC PROCESSOR

■12V SUPPLY VOLTAGE

■8V REFERENCE VOLTAGE

■HORIZONTAL LOCK/UNLOCK OUTPUT

■READ/WRITE I2C INTERFACE

■VERTICAL MOIRE

■B+ REGULATOR

- Inter nal PWM ge nerator for B+ current mo de

step-up converter

- Switchable to step-down converter

-I

C ad justable B+ refere nce voltage

- Output Pulses Synchronized on Horizontal

Frequency

- Internal Maximum Current Limitation

Horizontal

■Self-adaptative

■Dual PLL concept

■150kHz max im um fr eque nc y

■X-ray protection input

■I2C controls:

Horizontal duty-cycle, H-position

Vertical

■Vertical ramp generator

■50 to 185Hz AGC loop

■Geometry tracking with Vpos & Vamp

■I2C controls:

Vamp, Vpos, S-corr, C-corr

■DC breathing compensation

I2C Geometry corrections

■Vertical parabola generator

(Pin Cushion - E/W, Keystone, Corner

Correction)

■Horizontal dynamic phase

(Side Pin Balance & Parallelogram)

■Horizontal and vertical dynamic focus

(Horizontal focus amplitude, Horizontal focus

symmetry, Vertical focus amplitude)

DESCRIPTION

The TDA9109A is a monolithic integrated circuit

assembled in a 32-pin shrink dual in line plastic

package . This IC contr ols all the funct ions rel ated

to the horizontal and vertical deflection in multi-

mode or multi-frequency computer display moni-

tors.

The internal sync processor, combined with the

very powerful geometry correction block, make

the TDA9109A suitable for very high performance

monitors, using very few external components.

The horizontal jitter level is very low. It is particu-

larly well-suited to high-end 15" and 17" monitors.

Combined with the ST7275 Microcontroller family,

TDA9206 ( Vide o preamp lifie r) and STV94 2x (O n-

Screen Display controller), the TDA9109A allows

fully I2C bus-controlled computer display monitors

to be built with a reduced number of external com-

ponents.

ORDERING INFORMATION

Ordering code Package

TDA9109A Shrink 32 (plastic)

TABLE OF CONTENTS

2/47

PIN CONNECTIONS 4

PIN CONNECTIONS 5

QUICK REFERENCE DATA 6

BLOCK DIAGRAM 8

ABSOLUTE MAXIMUM RATINGS 9

THERMAL DATA 9

I2C READ/WRITE 10

SYNC PROCESSOR 10

HORIZONTAL SECTION 11

VERTICAL SECTION 13

DYNAMIC FOCUS SECTION 15

GEOMETRY CONTROL SECTION 16

B+ SECTION 18

TYPICAL OUTPUT WAVEFORMS 20

I2C BUS ADDRESS TABLE 24

I2C BUS ADDRESS TABLE 25

OPERATING DESCRIPTION 27

1 GENERAL CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.1Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.2I2C Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.3Write Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.4Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.5Sync Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

1.6Sync Identification Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.7IC status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.8Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.9Sync Processor Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2 HORIZONTAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.1Internal Input Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

2.2PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.3PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2.4Output Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.5X-RAY Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2.6Horizontal and Vertical Dynamic Focus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3 VERTICAL PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.1Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.2I2C Control Adjustments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.3Vertical Moiré . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.4Basic Equations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.5E/W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.6Dynamic Horizontal Phase Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

TABLE OF CONTENTS

3/47

4 DC/DC CONVERTER PART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.1Step-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.2Step-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3Step-up and Step-down Mode Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

INTERNAL SCHEMATICS 39

PACKAGE MECHANICAL DATA 46

TDA9109A

4/47

PIN CONNECTIONS

H/HVIN

VSYNCIN

HLOCKOUT

PLL2C

PLL1F

HPOSITION

HFOCUSCAP

FOCUS-OUT

HGND

HFLY

HREF

COMP

REGIN

ISENSE

SDA

SCL

VCC

BOUT

GND

HOUT

XRAY

EWOUT

VOUT

VCAP

VREF

VAGCCAP

VGND

BREATH

B+GND17

TDA9109A

5/47

PIN CONNECTIONS

Pin Name Function

1 H/HVIN TTL compatible Horizontal sync Input (separate or composite)

2 VSYNCIN TTL compatible Vertical sync Input (for separated H&V)

3 HLOCKOUT First PLL Lock/Unlock Output (0 V: Unlocked - 5 V: Locked)

4 PLL2C Second PL L Loo p Filt er

5 C0 Horizont al Os cilla to r Cap ac itor

6 R0 Horizont al Os cilla to r Res isto r

7 PLL1F First PLL Loop Filter

8 HPOSI TIO N Horizont al Po siti on Fil ter (ca pa cit or to be co nn ect ed to HGN D)

9 HFOCUSCAP Horizontal Dynamic Focus Oscillator Capacitor

10 FOCUS OUT Mixed Horizontal and Vertical Dynamic Focus Output

11 HGND Horizont al Se ctio n Gro un d

12 HFLY Horizont al Fly ba ck Inp ut (po sit ive pola rity )

13 HREF Horizont al Se ctio n Re fer enc e Vo lta ge (to be filter ed )

14 COMP B+ Error Amplifier Output for frequency compensation and gain setting

15 REGIN Regulation Input of B+ control loop

16 ISENSE Sensing of external B+ switching transistor current,or switch for step-down converter

17 B+GND Ground (re late d to B+ refer en ce ad jus tm en t)

18 BREATH DC Breathing Input Control (compensation of vertical amplitude against EHV variation)

19 VGND Vertical Se ctio n Gro un d

20 VAGCCAP Memory Capacitor for Automatic Gain Control Loop in Vertical Ramp Generator

21 VREF Vertical Se ctio n Refer en ce Vo lta ge (to be filter ed )

22 VCAP Vertical Sawtooth Generator Capacitor

23 VOUT Vertical Ra mp Outp ut (w ith fre qu en cy ind ep en da nt am plit ud e and S or C Corre ctio ns if

any). It is mixed with vertical position voltage and vertical moiré.

24 EWOUT Pin Cushion - E/W Correction Parabola Output

25 XRAY X-RAY protection input (with internal latch function)

26 HOUT Horizont al Driv e Ou tpu t (NP N op en co llec to r)

27 GND General Ground (referenced to VCC)

28 BOUT B+ PWM Regulator Output

29 VCC Supply Voltage(12V typ)

30 SCL I2C Clock Input

31 SDA I2C Data Input

32 5V Supply Voltage (5V typ.)

TDA9109A

6/47

QUICK REFERENCE DATA

Parameter Value Unit

Horizontal Frequency 15 to 150 kHz

Autosynch Frequency (for given R0 and C0. Can be easily increased by application) 1 to 4.5 f0

± Ho riz ont al Sy nc Po lar ity Inp ut YES

Polarity Detection (on both Horizontal and Vertical Sections) YES

TTL Composite Sync YES

Lock/Unlock Identification (on both Horizontal 1st PLL and Vertical Section) YES

I2C Control for H-Position ±10 %

XRAY Protection YES

I2C Horizontal Duty Cycle Adjustment 30 to 65 %

I2C Free Running Frequency Adjustment NO

Stand-by Function YES

Dual Polarity H-Drive Outputs NO

Supply Voltage Monitoring YES

PLL1 Inhibition Possibility NO

Blanking Outputs NO

Vertical Frequency 35 to 200 Hz

Vertical Autosync (for 150nF on Pin 22 and 470nF on Pin 20) 50 to 185 Hz

Vertical S-Correction (optimized for super flat tube) YES

Vertical C-Correction YES

Vertical Amplitude Adjustment YES

DC Breathing Control on Vertical Amplitude YES

Vertical Position Adjustment YES

East/West (E/W) Parabola Output (also known as Pin Cushion Output) YES

E/W Correction Amplitude Adjustment YES

Keystone Adjustment YES

Corner Correction with Amplitude Adjustment YES

Internal Dynamic Horizontal Phase Control YES

Side Pin Balance Amplitude Adjustment YES

Parallelogram Adjustment YES

Tracking of Geometric Corrections with Vertical Amplitude and Position YES

Reference Voltage (both on Horizontal and Vertical) YES

Dynamic Focus (both Horizontal and Vertical) YES

I2C Horizontal Dynamic Focus Amplitude Adjustment YES

I2C Horizontal Dynamic Focus Symmetry Adjustment YES

I2C Vertical Dynamic Focus Amplitude Adjustment YES

TDA9109A

7/47

Detection of Input Sync (biased from 5V alone) YES

Vertical Moiré YES

Controlle d V-M oi ré Am pli tud e YES

Frequency Generator for Burn-in NO

Fast I2C Read/Write 400 kHz

B+ Regulation adjustable by I2CYES

Horizontal Size Control NO

Parameter Value Unit

TDA9109A

8/47

BLOCK DIAGRAM

PLL1F POSITION R0 C0 HFLY PLL2C HOUT

7865124 26

Phase/Frequency

Comparator

H-Pha se (7bits) VCO Phase

Comparator Phase

Shifter H-Duty

(7bits) Hout

Buffer

Safety

Processor

Controller

SPin bal

7bits

Paral

7bits

B+

Lock/Unlock

Identification

Sync

Processor

Sync Input

Select

(1bit)

Geometry

Tracking

VDFAMP

7bits Internal

reference

(7bits)

Amp

Symmetry

2x7bits x

Corner

7bits

E/Wpcc

7bits

Keyst.

7 bits

Vertical Moire

Cancel

7bits+ON/OFF

TDA9109A

VSYNC

VPOS

7bits

VAMP

7bits

7 bits

Vertical

Oscillator

Ramp Genera tor

S and C

Correction

C Interface

ref

HGND

VGND

VCC

XRAY

BOUT

SENSE

COMP

REGIN

BGND

FOCUS

HFOCUS-

EWOUT

23182022 V

OUT

BREATHV

AGCCAP

CAP

H/HVIN

SYNCIN

HLOCKOUT

SDA

SCL

GND

HREF

VREF

CAP

TDA9109A

9/47

ABSOLUTE MAXIMUM RATINGS

THERM AL DATA

Symbol Parameter Value Unit

VCC Supply Voltage (Pin 29) 13.5 V

VDD Supply Voltage (Pin 32) 5.7 V

VIN

Max Voltage on Pin 4

Pin 9

Pin 5

Pins 6, 7, 8, 14, 15, 16, 20, 22

Pins 10, 18, 23, 24, 25, 26, 28

Pins 1, 2, 3, 30, 31

4.0

5.5

6.4

8.0

VCC

VDD

VESD ESD susceptibility Human Body Model, 100pF Discharge

through 1.5kΩ

EIAJ Norm, 200pF Discharge through 0Ω2

300 kV

Tstg Storage Temperature -40, +150 °C

TjJunctio n Te mp era tu re +150 °C

Toper Operating Temperature 0, +70 °C

Symbol Parameter Value Unit

Rth(j-a) Max. Junction-Ambient Thermal Resistance 65 °C/W

TDA9109A

10/47

I2C READ/WRITE

Electrical Characteristics (VDD = 5V, Tamb = 25°C)

Note: 1 See also I2C Bus Address Table.

SYNC PROCESSOR

Operating Conditions (VDD = 5V, Tamb = 25°C)

Electrical Characteristics (VDD = 5V, Tamb = 25°C)

Note: 2 TH is the Horizontal period.

Symbol Parameter Test Conditions Min. Typ. Max. Units

I2C PROCESSOR (See 1)

Fscl Maximum Clock Frequency Pin 30 400 kHz

Tlow Low period of the SCL Clock Pin 30 1.3 µs

Thigh High period of the SCL Clock Pin 30 0.6 µs

Vinth SDA and SCL Input Threshold Pins 30, 31 2.2 V

VACK Acknowledge Output Voltage on SDA

input with 3mA Pin 31 0.4 V

I2C leak Leakage current into SDA and SCL

with no logic supply VDD = 0

Pins 30, 31 = 5 V 20 µA

Symbol Parameter Test Conditions Min. Typ. Max. Units

HsVR Voltage on H/HVIN Input Pin 1 0 5 V

MinD Minimum Ho rizo nt al Inp ut Pu lse s Du-

ration Pin 1 0.7 µs

Mduty Maximum Horizontal Input Signal Duty

Cycle Pin 1 25 %

VsVR Voltage on VSYNCIN Pin 2 0 5 V

VSW Mini mum Ve rtic al Sy nc Pu lse Widt h Pin 2 5 µs

VSmD Maximum Vertical Sync Input Duty Cy-

cle Pin 2 15 %

VextM Maximum Vertical Sync Width on TTL

H/Vcomposite Pin 1 750 µs

Symbol Parameter Test Conditions Min. Typ. Max. Units

VINTH Horizontal and Vertical Input Logic

Level (Pins 1, 2) High Level

Low Level 2.2 0.8 V

RIN Horizontal and Vertical Pull-Up Resis-

tor Pins 1, 2 250 kΩ

VoutT Extracted Vsync Integration Time (%

of TH) on H/V Composite (see 2)C0 = 820pF 26 35 %

TDA9109A

11/47

HORIZONTAL SECTION

Operating Conditions

Electrical Characteristics (VDD = 12V, Tamb = 25°C))

Symbol Parameter Test Conditions Min. Typ. Max. Units

VCO

I0max Max Current from Pin 6 Pin 6 1.5 mA

F(max.) Maximum Oscillator Frequency 150 kHz

OUTPUT SECTION

I12m Maximum Input Peak Current Pin 12 5 mA

HOI Horizontal Drive Output Maximum

Current Pin 26, Sunk current 30 mA

Symbol Parameter Test Conditions Min. Typ. Max. Units

SUPPLY AND REFERENCE VOLTAGES

VCC Supply Voltage Pin 29 10.8 12 13.2 V

VDD Supply Voltage Pin 32 4.5 5 5.5 V

ICC Supply Current Pin 29 50 mA

IDD Supply Current Pin 32 5 mA

VREF-H Horizontal Reference Voltage Pin 13, I = -2mA 7.6 8.2 8.8 V

VREF-V Vertical Reference Voltage Pin 21, I = -2mA 7.6 8.2 8.8 V

IREF-H Max. Sourced Current on VREF-H Pin 13 5 mA

IREF-V Max. Sourced Current on VREF-V Pin 21 5 mA

1st PLL SECTION

HpoIT D el ay Tim e for dete ctin g pol ari ty

change (see 3)Pin 1 0.75 ms

Vvco VCO Control Voltage (Pin 7) VREF-H = 8.2V fo

fH(Max.) 1.4

6.4 V

Vcog VCO Gain (Pin 7) R0 = 6.49kΩ,

C0 =820pF 15.9 kHz/V

Hph Horizontal Phase Adjustment

(see 4)% of Ho rizo nt al

Period ±10 %

Vbmi

Vbtyp

Vbmax

Horizontal Phase Setting Value (Pin 8)

(see 4)

Minimum Value

Typical Value

Maximum Value

Sub-Add re ss 01

Byte x1111 11 1

Byte x1000 00 0

Byte x0000 00 0

2.9

3.5

4.2

IPII1U

IPII1L P LL 1 Filt er Cu rre nt Ch arg e PLL1 is Unlocked

PLL1 is Locked ±140

±1µA

foFree Running Frequency R0 = 6.49kΩ,

C0 = 820pF 22.8 kHz

dfo/dT Free Running Frequency Thermal Drift

(No drift on external components)

(see 5)-150 ppm/

CR PLL1 Capture Range fH(Min.)

fH(Max.) (See Note 6) fo+0.5

4.5fo

kHz

HUnlock DC level pin 3 when PLL1 is locked 5 V

TDA9109A

12/47

Note: 3 This delay is mandatory to avoid a wrong detection of polarity change in the case of a composite sync.

Note: 4 See Figure 10 for explanation of reference phase.

Note: 5 These param e ters are not teste d on ea ch unit. Th ey are meas ure d dur in g our int ernal qua lifi ca tion .

Note: 6 A larger range may be obtained by application.

Note: 7 Hjit = 106 x (Standard deviation/Horizontal period)

Note: 8 Duty Cycle is the ratio between the output transistor OFF time and the period. The power transistor is

controll ed OF F wh en the outp ut transis tor is OF F.

Note: 9 Initial Condition for Safe Operation Start Up.

2nd PLL SECTION AND HORIZONTAL OUTPUT SECTION

FBth Flyback Input Threshold Voltage (Pin

12) 0.65 0.75 V

Hjit Horizontal Jitter (See 7) At 31.4kHz 70 ppm

HDmin

HDmax

Horizontal Drive Output Duty-Cycle

(Pin 26) (see 8) Sub-Add re ss 00

Byte x1111 11 1

Byte x0000000 (see 9)30

65 %

XRAYth X-RAY Protection Input Threshold

Voltage, Pin 25, see Figure 14 7.6 8.2 8.8 V

Vphi2 Internal Clamping Levels on 2nd PLL

Loop Filter (Pin 4) Low Level

High Level 1.6

4.2 V

VSCinh Threshold Voltage to Stop H-Out, V-

Out, B- Out and Reset XRAY when VCC

< VSCinh (see Figure14) Pin 29 7.5 V

HDvd Horizontal Drive Output (low level) Pin 26, IOUT = 30mA 0.4 V

Symbol Parameter Test Conditions Min. Typ. Max. Units

TDA9109A

13/47

VERTICAL SECTION

Operating Conditions

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol Parameter Test Conditions Min. Typ. Max. Units

OUTPUTS SECTION

RLOAD Minimum Load for less than 1% Verti-

cal Amplitude Drift Pin 20 65 MΩ

Symbol Parameter Test Conditions Min. Typ. Max. Units

VERTICAL RAMP SECTION

VRB Voltage at Ramp Bottom Point Pin 22 2.1 V

VRT Voltage at Ramp Top Point (with Sync) Pin 22 5.1 V

VRTF Voltage at Ramp Top Point (without

Sync) Pin 22 VRT-

0.1 V

VSTD Vertical Sawtooth Discharge Time Pin 22, C22 = 150nF 70 µs

VFRF Vertical Free Running Frequency

(See 11)C22 = 150nF 100 Hz

ASFR AUTO-SYNC Frequency (See 12)C

22 = 150nF ±5% 50 185 Hz

RAFD Ramp Amplitude Drift Versus

Frequency at Maximum Vertical

Amplitude (see 10)

C22 = 150nF

50Hz< f < 185Hz 200 ppm/

Rlin Ramp Linearity on Pin 22 (See 11) 2.5V < V27 < 4.5V 0.5 %

VPOS Vertical Position Adjustment Voltage

(Pin 23 - VOUT mean value)

Sub Address 06

Byte 00000000

Byte 01000000

Byte 01111111

3.2

3.6

4.0

VOR Vertical Output Voltage

(peak-to-peak on Pin 23)

Sub Address 05

Byte 10000000

Byte 11000000

Byte 11111111

2.15

3.0

3.9

VOI Vertical Output Maximum Current

(Pin 23) ±5mA

dVS

Max Vertical S-Correction Amplitude

(See 13)

0xxxxxxx inhibits S-CORR

11111111 gives max S-CORR

Sub Address 07

Byte 11111111

∆V/VPP at TV/4

∆V/VPP at 3TV/4 -3.5

3.5 %

Ccorr Vertical C-Corr Amplitude

0xxxxxxx inhibits C-CORR

Sub Address 08

∆V/VPP at TV/2

Byte 10000000

Byte 11000000

Byte 11111111

-3

VMOIRE Vertical Moiré Sub Address 0C

Byte 01X11111 6mV

TDA9109A

14/47

Note: 10 These parameters are not tested on each unit. They are measured during our internal qualification procedure.

Note: 11 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction

is inhibited), the vertical sawtooth has a linear shape.

Note: 12 This is the frequency range for which the vertical oscillator will automatically synchronize, using a single

capacitor value on Pin22 and Pin 20, and with a constant ramp amplitude.

Note: 13 TV is the vertical period.

Note: 14 When not used, the DC breathing control pin must be connected to 12V.

BREATH IN G CO M PE NS AT IO N

BRRANG DC Breathing Voltage Range

(See 14)V18 112V

BRADj Vertical Output Variation versus DC

Breathing Control (Pin 23) V18 > VREF-V

1V<V18< VREF-V

-2.5 %/V

%/V

Symbol Parameter Test Conditions Min. Typ. Max. Units

TDA9109A

15/47

DYNAMIC FOCUS SECTION

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Note: 15 These param e ters are not tested on ea ch unit. Th ey are meas ure d du r in g our int ernal qua lifi ca tion .

Note: 16 S and C correction are inhibited so the vertical output sawtooth has a linear shape.

Symbol Parameter Test Conditions Min. Typ. Max. Units

HORIZONTAL DYNAMIC FOCUS FUNCTION

HDFst Horizontal Dynamic Focus Sawtooth

Minimu m Le vel

Maximum Level

Pin 9, capacitor on

HFOCUSCAP and

C0 = 820pF, TH =

20µs

2.2

4.9 V

HDFdis Horizontal Dynamic Focus Sawtooth

Discharge Width Start by HDFs tar t 400 ns

HDFstart Internal Fixed Phase Advance versus

HFLY middle Independe nt of

frequency 1µs

HDFDC Bottom DC Output Level RLOAD = 10kΩ, Pin 10 2.1 V

TDFHD DC Output Voltage Thermal Drift

(see 15)200 ppm/

HDFamp

Horizontal Dynamic Focus Amplitude

Min Byte xxx11111

Typ Byte xxx10000

Max Byte xxx00000

Sub-Add re ss 03 ,

Pin 10, fH = 50kHz,

Symmetr ic Wa ve

Form

1.5

3.5

VPP

HDFKeyst Horizontal Dynamic Focus Position

Advance for Byte xxx11111

Delay for Byte xxx00000

Sub-address 04

For time reference

see Figure 15 16

16 %

VERTICAL DYNAMIC FOCUS FUNCTION (positive parabola)

AMPVDF

Vertical Dynamic Focus Parabola

(added to horizontal) Amplitude with

VAMP and VPOS Typical

Min. Byte xx000000

Typ. Byte xx100000

Max. Byte xx111111

Sub-Add re ss 0F

0.5

VPP

VDFAMP Parabola Amplitude Function of VAMP

(tracking between VAMP and VDF)

with VPOS Typ. (see Figure 1 and 16)

Sub-Add re ss 05

Byte x0000000

Byte x1000000

Byte x1111111

0.6

1.5

VPP

VHDFKeyt

Parabola Asymmetry Function of

VPOS Co ntr ol (tra ck ing betw ee n

VPOS and VDF) with VAMP Max.

A/B Ratio

B/A Ratio

Sub-Add re ss 06

Byte x0000000

Byte x1111111 0.52

0.52

TDA9109A

16/47

GEOMETRY CONTROL SECTION

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Symbol Parameter Test Conditions Min. Typ. Max. Units

East/West E/W FUNCTION

EWDC

DC Output Voltage with:

- typical VPOS

- Keyston e inhi bite d Pin 24, see Figure 2 2.5 V

TDEWDC DC Output Voltage Thermal Drift See 15 100 ppm/

EWpara

Parabola Amplitude with:

- Max. VAMP ,

- Typ. VPOS,

- Keystone and Corner inhibited

Subaddress 0A

Byte 11111111

Byte 11000000

Byte 10000000

2.5

1.25

VPP

EWtrack

Parabola Amplitude Function of VAMP

Control (tracking between VAMP and

E/W) with:

- Typ. VPOS,

- Typ. E/W Amplitude,

- Corner and Keystone inhibited (17)

Subaddress 05

Byte 10000000

Byte 11000000

Byte 11111111

0.45

0.80

1.45

VPP

KeyAdj

Keystone Adjustment Capability with: -

- Typ. VPOS,

- E/W inhibit ed ,

- Corner inhibited and

- Max. Vertic al Am pli tud e

(see 17 and Figure 4)

Subaddress 09

Byte 10000000

Byte 11111111 1

1VPP

VPP

Corner

Corner Adjustment Capability with:

- Typ. VPOS,

- E/W inhibit ed ,

- Keyston e inh ibit ed

- Max. Vertic al Am pli tud e

Subaddress 10

Byte 11111111

Byte 11000000

Byte 10000000

−3

VPP

KeyTrack

Intrinsic Keystone Function of VPOS

Control (tracking between VPOS and

E/W) with:

- Max. E/W Am plit ud e

- Max. Vertical Amplitude

A/B Ratio

B/A Ratio

Subaddress 06

Byte 00000000

Byte 01111111 0.52

0.52

TDA9109A

17/47

Note: 17 With Register 07 at Byte 0xxxxxxx (S correction is inhibited) and Register 08 at Byte 0xxxxxxx (C correction

is inhibited), the vertical sawtooth has a linear shape.

Note: 18 TH is the horizontal period.

Note: 19 When not used, the DC breathing control pin must be connected to 12V.

INTERNAL DYNAMIC HORIZONTAL PHASE CONTROL

SPBpara

Side Pin Balance Parabola Amplitude

(Figure 3) with:

- Max. VAMP ,

- Typ. VPOS

- Parallelogram inhibited (see 17 & 19)

Subaddress 0D

Byte 11111111

Byte 10000000 +2.8

-2.8 %TH

%TH

SPBtrack

Side Pin Balance Parabola Amplitude

function of VAMP Control (tracking be-

tween VAMP and SPB) with

- Max. SPB,

- Typ. VPOS

- Parallelogram inhibited (see 17 & 19)

Subaddress 05

Byte 10000000

Byte 11000000

Byte 11111111

1.8

2.8

%TH

ParAdj

Parallelogram Adjustment Capability

with:

- Max. VAMP ,

- Typ. VPOS

- Max. SPB (se e 17 & 19)

Subaddress 0E

Byte 11111111

Byte 11000000 +2.8

-2.8 %TH

%TH

Partrack

Intrinsic Parallelogram Function of

VPOS Co ntr ol (tra ck ing betw ee n

VPOS and DHPC) with:

- Max. VAMP ,

- Max. SPB

- Parallelogram inhibited (see 17 & 19)

A/B Ratio

B/A Ratio

Subaddress 06

Byte x0000000

Byte x1111111 0.52

0.52

Symbol Parameter Test Conditions Min. Typ. Max. Units

TDA9109A

18/47

B+ SECTION

Operating Conditions

Electrical Characteristics (VCC = 12V, Tamb = 25°C)

Note: 20 0.5mA are sunk when B+ section is disabled. the purpose is to discharge the soft-start capacitor.

Note: 21 The external power transistor is OFF during 400ns of the HFOCUSCAP discharge

Symbol Parameter Test Conditions Min. Typ. Max. Units

FeedRe s Mini mu m Fe ed bac k Re sis tor Re sis tor be twe en

Pins 15 and 14 5kΩ

Symbol Parameter Test Conditions Min. Typ. Max. Units

OLG Error Amplifier Open Loop Gain At low frequency (15)85dB

UGBW Unity Gain Bandwidth (see 15)6MHz

IRI Regula tio n Inp ut Bia s Cu rre nt Current sourced by

Pin 15 (PNP base) 0.2 µA

EAOI Error Amplifier Output Current

Current sourced by

Pin 14

Current sunk by Pin 14

(See 20)2

1.4 mA

CSG Current Sense Input Voltage Gain Pin 16 3

MCEth Max Current Sense Input Threshold

Voltage Pin 16 1.3 V

ISI Current Sense Input Bias Current Current sunk by Pin 16

(PNP base) 1µA

Tonmax Maximum ON Time of the external

power transistor % of horizont al per iod

fo = 27kHz (See 21)100 %

B+OSV B+Output Saturation Voltage V28 with I28 = 10mA 0.25 V

IVREF Internal Reference Voltage On error amp (+) input

for Subaddress OB

Byte 1000 000 5V

REFADJ Internal Reference Voltage Adjustment

Range Byte 01111111

Byte 0000 000 0 +20

-20 %

PWMSEL Threshold for step-up/step-down

selection Pin 16 6 V

tFB+ Fall Time Pin 28 100 ns

TDA9109A

19/47

Figure 1. Vertical Dynamic Focus Function

Figure 2. E/W Output

Figure 3. Dynamic Horizontal Phase Control Output

Figure 4. Keystone Effect on E/W Output (PCC Inhibited)

TDA9109A

20/47

TYPICAL OUTPUT WAVEFORMS

Function Sub

Address Pin Byte Specification Effect on Screen

Vertical

Size 05 23

10000000

11111111

Vertical

Position

DC Con-

trol

06 23

00000000 VOUTDC = 3.2V

01000000 VOUTDC = 3.6V

01111111 VOUTDC = 4.0V

Vertical

Linearity 07 23

0xxxxxxx:

Inhibited

11111111 =

TDA9109A

21/47

Vertical

Linearity 08 23

0xxxxxxx :

Inhibited

10000000

11111111

Horizon-

tal

Dynamic

Focus

with:

Ampli-

tude

03 10 X000 0000

—

X111 1111 -

Horizon-

tal

Dynamic

Focus

with:

Symme-

try

04 10

X000 00 00

—

X111 1111 -

Function Sub

Address Pin Byte Specification Effect on Screen

= -3%

=+3%

TDA9109A

22/47

Keystone

(Trape-

zoid)

Control

09 24

(E/W + Cor-

ner

Inhibited)

10000000

11111111

E/W

(Pin

Cushion)

Control

0A 24

(Keystone

+ Corner

Inhibited)

10000000

11111111

Corner

Control 10 24

(Keystone+E/W Inhibited)

11111111

10000000

Parallel-

ogram

Control 0E

(SPB Inhibited)

10000000

11111111

Function Sub

Address Pin Byte Specification Effect on Screen

0.4V EWDC

EWDC 0V

EWDC

1.4V

1.25V

EWDC

1.25V

Internal

2.8% T

TDA9109A

23/47

Side Pin

Balance

Control 0D

(Parallelogram Inhibited)

10000000

11111111

Vertical

Dynamic

Focus

with

Horizon-

tal

0F 10 X111 1111

—X000

0000 ---

Function Sub

Address Pin Byte Specification Effect on Screen

Internal

2.8% T

TDA9109A

24/47

I2C BUS ADDRESS TABLE

Slave Address (8C): Write Mode

Sub Address Definition

Slave Address (8D): Read Mode

No sub address needed.

D8 D7 D6 D5 D4 D3 D2 D1

000000000Horizontal Drive Selection/Horizontal Duty Cycle

100000001X-ray Reset/Horizontal Position

200000000

3 0 - - 1 0 0 1 1 Sync. Priority/Horizontal Focus Amplitude

4 0 - - 1 0 1 0 0 Refresh/Horizontal Focus Keystone

500000101Vertical Ramp Amplitude

600000110Vertical Position Adjustment

700000111S Correction

800001000C Correction

900001001E/W Keystone

A00001010E/W Amplitude

B00001011B+ Reference Adjustment

C00001000Vertical Moiré

D00001001Side Pin Balance

E00001010Parallelogram

F00001011Vertical Dynamic Focus Amplitude

1000010000E/W Corner

TDA9109A

25/47

I2C BUS ADDRESS TABLE

D8 D7 D6 D5 D4 D3 D2 D1

WRITE MODE

00 [HDrive

0, off

[1], on0] [0] Horizontal Duty Cycle

[0] [0] [0] [0] [0]

01 Xray

1, reset

[0]

Horizontal Phase Adjustment

[1] [0] [0] [0] [0] [0] [0]

03 Sync

0, Comp

[1], Sep

Horizontal Focus Amplitude

[1] [0] [0] [0] [0]

04 Detect

Refresh

[0], off

Horizontal Focus Time Position

[1] [0] [0] [0] [0]

05 Vramp

0, off

[1], on

Vertical Ramp Amplitude Adjustment

[1] [0] [0] [0] [0] [0] [0]

06 Vertical Position Adjustment

[1] [0] [0] [0] [0] [0] [0]

07 S Select

1, on

[0]

S Correction

[1] [0] [0] [0] [0] [0]

08 C Select

1, on

[0]

C Correction

[1] [0] [0] [0] [0] [0]

09 E/W Key

0, off

[1]

E/W Keystone

[1] [0] [0] [0] [0] [0]

0A E/W Sel

0, off

[1]

E/W Amplitude

[1] [0] [0] [0] [0] [0] [0]

0B Test H

1, on

[0], off

B + Reference Adjustment

[1] [0] [0] [0] [0] [0] [0]

0C Test V

1, on

[0], off

Moiré

1, on [0]

Vertical Moiré

[0] [0] [0] [0] [0]

0D SPB Sel

0, off

[1]

Side Pin Balance

[1] [0] [0] [0] [0] [0]

0E Parallelo

0, off

[1]

Parallelogram

[1] [0] [0] [0] [0] [0]

TDA9109A

26/47

[x] Initial value

Data is transferred with vertical sawtooth retrace.

We recommend setting the unspecified bit to [0] in order to ensure compatibility with future devices.

0F Eq. Pulse

1, on

[0], off

Vertical Dynamic Focus Amplitude

[1] [0] [0] [0] [0] [0]

10 Corner

1, on

[0], off

Corner Amplitude Adjustment

[1] [0] [0] [0] [0] [0]

READ MODE

Hlock

0, on

[1], no

Vlock

0, on

[1], no

Xray

1, on

[0], off

Polarity Detection Sync Detec tio n

H/V pol

[1], nega-

tive

V pol

[1], nega-

tive

Vext det

[0], no det H/V det

[0], no det V det

[0], no det

D8 D7 D6 D5 D4 D3 D2 D1

TDA9109A

27/47

OPERATING DESCRIPTION

1 GENERAL CONSIDERATIONS

1.1 Power Supply

The typical values of the power supply voltages

VCC an d VDD are 12 V a nd 5 V respe ctiv ely. Opti -

mum operation is obtained for VCC between 10.8

and 13.2 V and VDD between 4.5 and 5.5 V.

In order to avoid erratic operation of the circuit dur-

ing the transient phase of VCC switching on, or off,

the value of VCC is monitored: if VCC is less than

7.5 V typ., the outputs of the circuit are inhibited.

Similar ly, before VDD rea ches 4 V, all t he I2C re g-

ister are rese t to their defau lt value (see I2C Con-

trol Table).

In order to have very good power supply rejection,

the circui t is inte rnally supp lied b y sever al vol tage

references (typ. value: 8.2 V). Two of these volt-

age references are externally accessible, one for

the vertical and one for the horizontal part. They

can be used to bias external circuitry (if ILOAD is

less than 5 mA). It is necessary to filter the voltage

references by external capacitors connected to

ground, i n o rder to mi ni mize the noise a nd conse-

quently the “jitter” on vertical and horizontal output

signals.

1.2 I2C Control

TDA9109A belongs to the I2C controlled device

family. Ins tea d o f b ein g co ntr ol led by DC vol tag es

on dedicated control pins, each adjustment can be

done via the I2C Interface.

The I2C bus is a serial bus with a clock and a data

input. The general function and the bus protocol

are specified in the Philips-bus data sheets.

The interface (Data and Clock) is a comparator

whose threshold is 2.2 V with a 5 V supply. Spikes

of up to 50 ns ar e f il tered by a n i nte gr ator and the

maximum clock speed is limited to 400 kHz.

The data line (SDA) can be used bidirectionally. In

read-mode the IC sends reply information

(1 byte) to the micro-processor.

The bus protocol prescribes a full-byte transmis-

sion in all c ases. The first by te after the start co n-

dition is u se d t o tran smit the IC-ad dr es s (h ex a 8 C

for write, 8D for read).

1.3 Write Mode

In write mode the second byte sent contains the

subaddress of the selected function to adjust (or

controls to affect) and the third byte the corre-

sponding data byte. It is possible to send more

than one dat a byte to t he IC. If afte r the thi rd byte

no stop or start condition is detected, the circuit in-

crements automatically by one the momentary

subaddress in the subaddress counter (auto-incre-

ment mode). So it is possible to transmit immedi-

ately th e following d ata bytes without sending the

IC address or subaddress. This can be useful to

reinitialize all the controls very quickly (flash man-

ner). This procedure can be finished by a stop con-

dition.

The circuit has 18 adjustment capabilities: 3 for the

horizontal part, 4 for the vertical, 3 for the

E/W correction, 2 for the dynamic horizontal phase

contro l, 2 for the vertical and h orizontal Moir é op-

tions, 3 for the horizontal and the vertical dynamic

focus and 1 for the B+ reference adjustment.

18 bits are also dedicated to several controls (ON/

OFF, Horizo ntal Forced Frequ ency, Sync P riority,

Detection Refresh and XRAY reset).

1.4 Read Mode

During the read mode the second byte transmits

the reply information.

The reply byte c ont ain s th e ho rizo ntal and ve rti c al

lock/unlock status, the XRAY activation status

and, the horizontal and vertical polarity detection.

It also c ontains the sync de tection statu s which i s

used by the MCU to assign the sync priority. A

stop condition always stops all the activities of the

bus decoder and switches to high impedance both

the data and clock line (SDA and SCL).

See I2C subaddress and control tables.

1.5 Sync Processor

The internal sync processor allows the TDA9109A

to accept:

•separated hor i zontal & vertical TTL-

compatible sync signal

•composite horizontal & vertical TTL-

compatible sync signal

TDA9109A

28/47

1.6 Sync Identification Status

The MCU can read (address read mode: 8D) the

status register via the I2C bus, and then select the

sync priority depending on this status.

Among other data this reg ister indic ates the pres -

ence of sync pulses on H/HVIN, VSYNCIN and

(when 12 V is su pplied) whether a Vext has been

extracted from H/HVIN. Both horizontal and verti-

cal sync are detected even if only 5 V is supplied.

In order to choo se the rig ht sync prio rity the MCU

may proceed as follows (see I2C Address Table):

•refresh the status register

•wait at least for 20ms (Max. vertical period)

•read this status register

Sync priority choice should be:

Of course, when the choice is made, we can re-

fresh the sync detections and verify that the ex-

tracted Vsync is present and that no sync type

change has occurred. The sync processor also

gives sync polarity information.

1.7 IC status

The IC can inform the MCU about the 1st horizon-

tal PLL and vertical section status (locked or not)

and about the XRAY protection (activated or

not).Resetting the XRAY internal latch can be

done either by decreasing the VCC supply or di-

rectly resetting it via the I2C interface.

1.8 Sync Inputs

Both H/HVIN and VSYNCIN inputs are TTL com-

patible tr i ggers w ith hy st eres is t o a vo id er rati c de -

tect ion. Both i nputs inc lude a pu ll up resis tor con-

nected to VDD.

1.9 Sync Processor Output

The sync processor in dicates on the D 8 bit of the

status regi ster whet her 1s t PLL is loc ked to an in -

coming horizontal sync. Its level goes to low when

locked. This information is also av ailable on pin 3

when sub-address 02 D8 is equal to 1. When PLL1

is unlocked, pin 3 output voltage goes to 5V.

2 HORIZONTAL PART

2.1 Internal Input Conditions

A digital signal (horizontal sync pulse or TTL com-

posite) is sent by the sync processor to the hori-

zontal input. It may be positive or negative (see

Figure 5).

Using i nternal integrati on, both signa ls are recog-

nized if Z/T < 25%. Sync hron iz ati on oc cu rs on the

leading edge of the internal sync signal.

The minimum value of Z is 0.7 µs.

Another integration is able to extract the vertical

pulse from composite sync if the duty cycle is high-

er than 25% (typically d = 35%),

(see Figure 6).

Vextd

et HV

det V

det

Sync

priority

Subaddress

03 (D8)

Comment

Sync type

No Yes Yes 1 Sepa rat ed H& V

Yes Yes No 0 Composite TTL H&V

TDA9109A

29/47

Figure 5.

Figure 6.

The last feature performed is the removal of equal-

ization pulses to avoid parasitic pulses on the

phase comparator (which would be disturbed by

missing or extrane ous pulse s). This last feat ure is

switched on/off by sub -addres s 0F D8. By default

[0], equalization pulses will not be removed.

2.2 PLL1

The PLL1 consi sts of a phase comp arator, an ex-

ternal filter and a voltage-controlled oscillator

(VCO).The phase comparator is a “phase frequen-

cy” typ e designed in CMOS tech nology . This kind

of phase detector avoids locking on wrong fre-

quenci es. It is foll owed by a “charge pump” , com-

posed of two current sources : sunk and sourced

(typically I =1 mA when locked and I = 140 µA

when u nlocked ). This differe nce between lock /un-

lock allows smooth catching of the horizontal fre-

quency by PLL1. This effect is reinforced by an in-

ternal original slow down system when PLL1 is

locked, avoiding the horizontal frequency chang-

ing too quickly. The dynamic behavior of PLL1 is

fixed by an ex ter n al fi lte r whic h in tegr a tes the cur -

rent of the charge pump. A “CRC” filter is generally

used (see Figure 7)

Figure 7.

Ω

.7µF

PLL1F

10nF

1.8k

TDA9109A

30/47

The PLL1 is internally inhibited during extracted

vertical sync (if any) to avoid taking in account

missing pulses or wrong pulses on phase

comparator. Inhibition is obtained by stopping high

and low signals at the entry of the charge pump

block (see Figure 8).

Figure 8.

Figure 9.

The VCO uses an external RC network. It delivers

a linear sawto oth obtained by the charge and the

discharge of the capacitor, with a current propor-

tional to the current in the resistor. The typical

thresholds of the sawtooth are 1.6 V and 6.4 V.

The control voltage of the VCO is between 1.4 V

and 6.4 V (see Figur e 9 ). The theo retical fre quen-

cy range of this VCO is in the ratio of 1 to 4.5. The

effective frequency range has to be smaller (1 to

4.2) due to clamp intervention on the filter lowest

value.

The sync frequency must always be higher than

the free running frequency. For example, when us-

ing a sync ran ge bet ween 24.8 kHz and 100 kHz,

the suggested free running frequency is 23 kHz.

PLL1 ensures the coincidence between the lead-

ing edge of the sync signal and a phase reference

obtained by comparison between the sawtooth of

the VCO and an internal DC voltage which is I2C

adjustable between 2.9 V and 4.2 V (correspond-

ing to ±10 %) (see Figure 10).

TDA9109A

31/47

The TDA910 9A a lso i nc lud es a Lo ck /Unl oc k ide n-

tification block which senses in real time whether

PLL1 is locked or not on the incoming horizontal

sync signal.

The lock/unlock information is available through

the I2C read and the pin 3 voltage level

PLL1 Timing Diagram

Figure 10.

2.3 PLL2

PLL2 ensures a constant position of the shaped

flyback signal in comparison with the sawtooth of

the VCO, taking into account the saturation time

Ts (see Figure 11)

Figure 11. PLL2 Timing Diagram

The phas e compa rator of P LL2 (ph ase type c om-

parator) is followed by a charge pump (typical out-

put current: 0.5 mA).

The flyback input consists of an NPN transistor.

This input must be current driven. The maximum

recommended input current is 5 mA

(see Figure 12).

Figure 12. Flyback Input Electrical Diagram

The duty cycle is adjustable through I2C from 30 %

to 65 %. For a safe start-up operation, the initial

duty cycle (after power-on reset) is 65% in order to

avoid having too long a conduction period of the

horizontal scanning transistor.

The max imum storage time (Ts Max.) is ( 0.44TH-

TFLY/2). Typically, TFLY/TH is around 20 % which

means that Ts max is around 34 % of TH.

The PLL1 ensures the exact coincidence between the

signal phase REF and HSYNC. A ±10% TH phase

adjustment is possible around the 3.4V point.

Phase REF1 is obtained by comparison between

the sawtooth and a DC voltage adjustable between

2.9 V and 4.2 V.

Sawtooth 7/8 TH

1/8 T

6.4V

Ref. for H Position

(2.9V<Vb<4.2V)

1.6V

REF1

HSync

HOsc

Sawtooth 7/8TH

1/8 T

Flyback

Internally

shaped Flyback

HDrive Ts

Duty Cycle

1.6V

4.0V

6.4V

500Ω

HFly 12 Q1

GND 0V

20kΩ

TDA9109A

32/47

2.4 Output Section

The H-dri ve signal is s ent to the out put through a

shaping stage which also controls the H-drive duty

cycle (I 2C adjustab le) (see Figure 11). In order to

secure the scanning power part operation, the out-

put is inhibited in the following cases:

•when VCC or VDD are too low

•when the XRAY protection is activated

•during the Horizontal flyback

•when the HDrive I2C bit control is off

The output stage consists of a NPN bipolar tran-

sistor. Only the collector is accessible

(see Figure 13).

Figure 13.

This output stage is intended for “reverse” base

control, where setting the output NPN in off-state

will control the power scanning transistor in off-

state.

The maximum output current is 30mA, and the

corresponding voltage drop of the output VCEsat is

0.4V Max.

Obviously the power scanning transistor cannot be

directly driven by the integrated circuit. An inter-

face has to be added betwe en the circuit and the

power transistor either of bipolar or MOS type.

2.5 X-RAY Protection

The X-Ray protection is activated by application of

a high level on the X-Ray input (8.2V on Pin 25). It

inhibits the H-Drive and B+ outputs.

This activation is internally delayed by 2 lines to

avoid erratic detection (short parasitics).

This protection is latched; it may be reset either by

VCC switch off or by I2C (see Figure 14).

Figure 14. Safety Functions Block Diagram

TDA9109A

33/47

2.6 Horizontal and Vertical Dynamic Focus

The TDA9109A delivers a horizontal parabola

which is added on a vertical parabola waveform on

Pin 10. This horizontal parabola comes from a

sawtooth in phase advance with flyback pulse mid-

dle. The time advance versus horizontal flyback

middle is kept constant versus frequency (about

1µs).

Symmetry and amplitude are I2C adjustable (see

Figure 15). The vertical dynamic focus is tracked

with VPOS and VAMP. Its amplitude can be ad-

justed. It is also affected by S and C corrections.

This posi tiv e s i gnal once am pli fied i s to b e s en t to

the CRT focusing grids.

Figure 15. Phase of HFocus Parabola

TDA9109A

34/47

3 VERTICAL PART

3.1 Function

When the synchronization pulse is not present, an

internal current source sets the free running fre-

quency. For an external capacitor, COSC = 150nF,

the typical free running frequency is 100Hz.

The typical free running frequency can be calculat-

ed by:

fo(Hz) = 1.5 . 10-5 .

A negative or positive TTL level pulse applied on

Pin 2 (VSYNC) as well as a TTL composite sync

on Pin 1 can synchronize the ramp in the range

[fmin, fmax] (See Figure 16). This frequency range

depends on the external capacitor connected on

Pin 22. A 150nF (± 5%) capacitor is recommended

for 50Hz to 185Hz applications.

If a synchronization pulse is applied, the internal

oscillator is synchronized immediately but with

wrong amplitude. An internal correction then ad-

justs it in less than half a second. The top value of

the ramp (P in 22) is sam pled on the AG C capaci -

tor (Pin 20) at each clock pulse and a transcon-

ductance amplifier modifies the charge current of

the capacitor in such a way to make the amplitude

constant agai n.

The read status register provides the vertical Lock-

Unlock and the vertical sync polarity information.

We rec omm end the us e of a n A GC c ap aci tor with

low leakage current. A value lower than 100nA is

mandatory.

A good stability of the internal closed loop is

reached by a 470nF ± 5% capacitor value on Pin

20 (VAGC).

3.2 I2C Control Adjustments

S and C correction shapes can then be added to

this r amp. These fr equency- independen t S and C

corrections are generated internally. Their ampli-

tudes ar e adjus table by their respec tive I2C regis-

ters. They can also be inhibited by their "select"

bits.

Finally, the amplitude of this S and C corrected

ramp ca n be adjusted by the vertical ramp ampli-

tude control register.

The adjusted ramp is available on Pin 23 (V OUT) to

drive an external power stage.

The ga in o f this stage can b e adj ust ed (± 25%) de-

pending on its register value.

The mean value of this ramp is driven by its own

I2C register (vertical position). Its value is

VPOS = 7/16 . VREF-V ± 400mV.

Usually VOUT is sen t thro ugh a resi stiv e divid er to

the inverting input of the booster. Since VPOS de-

rives fr om VREF-V, the bias voltage sent to the non-

inverting input of the booster should also derive

from VREF-V to optimize the accuracy (see Appli-

cation Dia gram) .

3.3 Vertical Moiré

By using the vertical moiré, VPOS can be modulat-

ed from frame to frame. This function is intended

to cancel the fringes which appear when the line to

line interval is very close to the CRT vertical pitch.

The amplitude of the modulation is controlled by

switched-off via the control bit D8.

COSC

TDA9109A

35/47

Figure 16. AGC Loop Block Diagram

3.4 Basic Equations

In first approximation, the amplitude of the ramp

on Pin 23 (VOUT) is:

VOUT - VPOS = (VOSC - VDCMID) . (1 + 0. 3 (VAMP))

where:

VDCMID = 7/16 VREF (middle va lue o f the ramp on

Pin 22, typically 3.6V)

VOSC = V22 (ramp with fixed amplitude)

VAMP = -1 for minimum vertical amplitude register

va lue and +1 f or maximum

VPOS is calculated by:

VPOS = VDCMID + 0.4 VP

where VP = -1 for mi nimum vert ical p osition r egis -

ter value and +1 for maximum.

The current available on Pin 22 is:

IOSC = . VREF . COSC . f

where COSC = capa ci tor c onn ec ted o n Pi n 22 and

f = synchronization frequency.

Geometric Corrections

The principle is represented in Figure 17.

Starting from the vertical ramp, a parabola-shaped

current is generated for E/W correction (also

known as Pin Cushion correction), dynamic hori-

zontal phase control correction, and vertical dy-

namic focus correction.

The parabola generator is made by an analog mul-

tiplier, the output current of which is equal to:

∆I = k . (VOUT - VDCMID)2

where VOUT is the vertical output ramp (typically

between 2 and 5V) and VDCMID is 3.6V

(for VREF-V = 8.2V). The VOUT sawtooth is typical-

ly centered on 3.6V. By changing the vertical posi-

tion, the sawtooth shifts by ±0.4V.

To provide good screen geometry for any end user

adjustment, the TDA9109A has the “geometry

tracking” feature which allows generation of a dis-

symetri c parabola d epending on th e vertical posi-

tion.

Due to the lar ge output stage voltag e range (E/W

Pin Cushion, Keystone, E/W Corner), the combi-

nation of the tracking function, maximum vertical

amplitu de, maxim um or minim um vertica l position

and maximum gain on the DAC control may lead

to output stage saturation. This must be avoided

by limi ting the output volta ge with appropriate I2C

VSYNCIN 2 Synchro

Polarity

Oscillator

Discharge.

OSC

CAP

Sampling Sampling

Capacitance

S Correction

VS Amp

sub-add 07/7bits

Cor_C

sub-add 08/7bits

C Correcti on

BREATH

VOut

Vert. Amp

sub-.05/7bits

VMoiré

sub.0C/7bits

V Position

sub.06/7bits

Vlow

sawth

disch.

REF

Charge Current Transconductance Amplifier

TDA9109A

36/47

For the E/W part and the dynamic horizontal

phase con trol part, a s awtooth-sha ped differenti al

current in the following form is generated:

∆I’ = k’ . (VOUT - VDCMID)

Then ∆I and ∆I’ are added and converted into volt-

age for the E/W part.

Each of the two E/W components or the two dy-

namic horizontal phase control components may

be inhibited by their own I2C select bit.

The E/W parabola is available on Pin 24 via an

emitter follower output stage which has to be bi-

ased by an external resistor (10kΩ to ground).

Since stable in temperature, the device can be DC

coupled with external circuitry.

The vertical dynamic focus is combined with the

horizontal focus on Pin 10.

The dynamic horizontal phase control drives inter-

nally the H- position , moving the HFLY pos ition on

the horizont al sawtooth in the range of ± 2.8 %TH

both for side pin balance and parallelogram.

Figure 17. Geometric Corrections Principle

3.5 E/W

EWOUT = EWDC + K1 (VOUT - VDCMID) +

K2 (VOUT - VDCMID)2+ K3 (VOUT - VDCMID)4

K1 is adjustable by the keystone I2C register.

K2 is adjustable by the E/W amplitude I2C register.

K3 is adjustable by the E/W corner I2C register.

3.6 Dynamic Horizontal Phase Control

IOUT= K4 (VOUT - VDCMID) + K5 (VOUT - VDCMID)2

K4 is adjustable by the parallelogram I2C register.

K5 is adjustable by the side pin balance I2C regis-

ter.

TDA9109A

37/47

4 DC/DC CONVERTER PART

This unit controls the switch-mode DC/DC con-

verter. It converts a DC constant voltage into the

B+ voltage (roughly proportional to the horizontal

frequency) necessary for the horizontal scanning.

This DC/DC con verter can be configured either in

step-up or step-down mode. In both cases it oper-

ates very similarly to the well known UC3842.

4.1 Step-up Mode

Operating Description

•The power MOS is switched-on during the

flyback (at the beginning of the positive slope

of the horizontal focus sawtooth).

•The power MOS is switched-off when its

current reaches a predetermined value. For

this pu rpose , a sens e resis tor is ins erted in it s

source. The voltage on this resistor is sent to

Pin16 (ISENSE).

•The feedback (coming either from the EHV or

from the flyback) is divided to a voltage close

to 5.0V and compared to the internal 5.0V

reference (IVREF). The difference is amplified

by an error amplifier, the output of which

controls the power MOS switch-off current.

Main Features

•Switching synchronized on the horizontal

frequency

•B+ voltage always higher than the DC source

•Current limited on a pulse-by-pulse basis

The DC/DC converter is disabled:

•when VCC or VDD are too low

•when X-Ray protection is latched

•directly through I2C bus

When disabled, BOUT is driven to GND by a

0.5mA current source. This feature allows to im-

plement externally a soft start circuit.

4.2 Step-down Mode

In step-down mode, the ISENSE information is not

used any more and therefore not sent to the

Pin16. This mode is selected by connecting Pin16

to a DC voltage higher than 6V (for example VREF-

V).

Operating Description

•The power MOS is switched-on as for the

step-up mode

•The feedback to the error amplifier is done as

for the step-up mode

•The power MOS is switched-off when the

HFOCUSCAP voltage get higher than the

error amplifier output voltage

Main Features

•Switching synchronized on the horizontal

frequency

•B+ voltage always lower than the DC source

•No current limitation

4.3 Step-up and Step-down Mode Comparison

In step-down mode the control signal is inverted

compared with the step-up mode.

The reason for this, is the following:

•In step-up mode, the switch is a N-channel

MOS referenced to ground and made

conductive by a high level on its gate.

•In step-down, a high-side switch is necessary.

It can be either a P- or a N-channel MOS .

– For a P-channel MOS, the gate is controlled

directly from Pin 28 through a capacitor (this

allows to spare a Transformer). In this case, a

negative-going pulse is needed to make the

MOS conductive. Therefore it is necessary to

invert the control signal.

– For a N-channel MOS, a transformer is

needed to control the gate. The polarity of the

transformer can be easily adapted to the neg-

ative-going control pulse.

TDA9109A

38/47

Figure 18. DC/DC Convertor

I2CDAC

7bits

6.2V

5V±20% 85dB

inhibit

Soft

start

Σ1/3

1.3V

8V 6V C4

down

HDF Disc

400ns

inhibit

down

BOUT

12V

TDA9109A

REGIN COMP

15 14 16

22kΩ1MΩ

EHV

Feedback VB+

Command step-up/down

ISENSE

Horizont al Dy nam ic

Focus Sawtooth

±Iadjust

TDA9109A

39/47

INTERNAL SCHEMATICS

Figure 19.

Figure 20.

Figure 21.

Figure 22.

Figure 23.

Figure 24.

12V

HREF

TDA9109A

40/47

Figure 25.

Figure 26.

Figure 27.

Figure 28.

Figure 29.

Figure 30.

TDA9109A

41/47

Figure 31.

Figure 32.

Figure 33.

Figure 34.

Figure 35.

Figure 36.

TDA9109A

42/47

Figure 37.

Figure 38.

Figure 39.

TDA9109A

43/47

Figure 40. Demonstration Board

16 17

H/HVIN

VSYNCIN

HLock out

PLL2C

PLL1F

HFOCUS-

CAP

FOCUS

OUT

HGND

HFLY

HREF

COMP

REGIN

ISENSE

+5V

SDA

SCL

VCC

B+OUT

GND

HOUT

XRAY

EWOUT

VOUT

VCAP

VREF

VAGCCAP

VGND

BREATH

B+GND

POSITION

TP1

J11

TP13

TP17 J12 TP16

TP10

C7 22nF

C28

820pF 5%

R23

(***)

C13 10nF

C31 4.7µF

R36

C17 470nF

C34

820pF 5%

HREFC33

100nF

C27

47µF

C46

1nF

R50

1MΩ

C51

22µF

JP1

R89

33kΩ

R51

1kΩ

ISENSE

GND

B+OUT

REGIN

C47

100pF

R58

10Ω

+12V

C60

100nF

R77

15kΩ

R74

10kΩ

R73

1MΩ

R75

10kΩ

TP8

EHT

COMP R76

47kΩP1

10kΩ

CON4

J19

DYN

FOCUS R24

10kΩL

47µH

R25

1kΩ

HFLY

J8 C22

33pF R8

10kΩ

HOUT

C25

33pF

R10

10kΩ

R35

10kΩ

+12V

PC2

47kΩ

CC4

47pF +12V

CC1

100nF

CC2

10µF

+12V

CC3

47pF

PC1

47kΩ

-12V

1 234 5678

910111213141516

VCC

TB1

TB2

CDB

TA1

TA2

CDA

GND

ICC1

MC1 4528

C50

10µF

22µH

BC557

BC547

100nF

47µF

470nF

C15

C12

150nF

+12V

R52

3.9kΩ

R45 33kΩ

R7 10kΩ

C49

100nF

HOUT C48

10µF

R53

1kΩ

+12V R56

560kΩ

1N4148

+12V

100µF

100nF

C30

100µFC32

100nF

22µH

+5V

J16 J15

+5V

R39

4.7kΩR29

4.7kΩR42

100Ω

J14

1234

C39

22pF

C40

22pF

R41

100ΩSCL

SDA

C38

33pF

C45

10µFR49

22kΩ

+5V

IC3-STV9422

TILT

J13

R43

10kΩ

C42

1µF

R30

10kΩ

+5V

C43

47µF

C37

33pF

8MHz

123456789101112

13 14 15 16 17 18 19 20 21 22 23 24

PWM4

PWM5

SCL

SDA

RST

GND

TEST

PWM6

PWM7

PWM3

PWM2

XTALIN

XTALOUT

CKOUT

PXCK

VDD

HSYNC

VSYNC

FBLK

PWM1

PWM0

E/W POWER STAGE

R38

2.2Ω

3W J1

E/W

R19

270kΩ

C11220pF

TIP122

R18

10kΩ

R33

4.7kΩ

470Ω

R34

1kΩQ1

BC557 Q2

BC557

R37

27kΩR15

1kΩR17

43kΩ

C36

1µF

+12V

J18

VYOKE

R11

220Ω

0.5W

1Ω

0.5W

5.6Ω

+12V

-12V

TP3

TP4

TP6

TP7

100nF

C14

470µF

C10

100µF

35V

1n4004

-12V C10

470µFC8

100nF

220nF R3

1.5Ω

100nF

5.6kΩ

IC1

TDA8172

R40

36kΩ

12kΩ

C41

470pF

VERTICAL DEFLECTION STAGE

J17

HOUT

C16 (*)

IC4

TDA9109A

TP14

D10

1N4148

1N4148 D8

1N4148

R90

10k

R78

10Ω

(∗∗)

R31

27k (**)

(**)

(**) see table

9109A 9111

R78 Shorted Mounted

R90 Removed Mounted

R31 Mounted Removed

R17 270kΩ43kΩ

R18 39kΩ10kΩ

(*) optional

+12V

TP22

1.8kΩ

(***)

For R23=6.49kΩf0=22.8kHz typ

For R23=5.23kΩf0=28.3kHz typ

TDA9109A

44/47

Figure 41. PCB Layout

TDA9109A

45/47

Figure 42. Components Layout

TDA9109A

46/47

PACKAGE MECHANICAL DATA

32 PINS - PLASTIC SHRINK

Dimensions Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 3.556 3.759 5.080 0.140 0.148 0.200

A1 0.508 0.020

A2 3.048 3.556 4.572 0.120 0.140 0.180

B 0.356 0.457 0.584 0.014 0.018 0.023

B1 0.762 1.016 1.397 0.030 0.040 0.055

C .203 0.254 0.356 0.008 0.010 0.014

D 27.43 27.94 28.45 1.080 1.100 1.120

E 9.906 10.41 11.05 0.390 0.410 0.435

E1 7.620 8.890 9.398 0.300 0.350 0.370

e 1.778 0.070

eA 10.16 0.400

eB 12.70 0.500

L 2.540 3.048 3.810 0.100 0.120 0.150

32 17

Stand-off

B1B

TDA9109A

47/47

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responsibility for the consequences of use of such information nor for any infringement of patents or other

rights of third parties which may result from its use. No license is granted by implication or otherwise under

any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject

to change without notice. This publication supersedes and replaces all information previously supplied.

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