FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• PERFORMANCE (1850 MHz)
♦ 25 dBm Output Power (P1dB)
♦ 18 dB Small-Signal Gain (SSG)
♦ 0.6 dB Noise Figure
♦ 39 dBm Output IP3
♦ 55% Power-Added Efficiency
♦ Evaluation Boards Available
♦ Available in Lead Free Finish: FPD750SOT89E
• DESCRIPTION AND APPLICATIONS
The FPD750SOT89 is a packaged depletion mode AlGaAs/InGaAs pseudomorphic High Electron
Mobility Transistor (pHEMT). It utilizes a 0.25 µm x 750 µm Schottky barrier Gate, defined by
high-resolution stepper-based photolithography. The recessed and offset Gate structure minimizes
parasitics to optimize performance, with an epitaxial structure designed for improved linearity over a
range of bias conditions and input power levels. The FPD750 is available in die form and in other
packages.
Typical applications include drivers or output stages in PCS/Cellular base station high-intercept-
point LNAs, WLL and WLAN systems, and other types of wireless infrastructure systems.
• ELECTRICAL SPECIFICATIONS AT 22°C
Parameter Symbol Test Conditions Min Typ Max Units
RF SPECIFICATIONS MEASURED AT f = 1850 MHz USING CW SIGNAL
Power at 1dB Gain Compression P1dB V
DS = 5 V; IDS = 50% IDSS 23 25 dBm
Small-Signal Gain SSG VDS = 5 V; IDS = 50% IDSS 16.5 18 dB
Power-Added Efficiency PAE VDS = 5 V; IDS = 50% IDSS;
POUT = P1dB
50 %
Noise Figure NF VDS = 5 V; IDS = 50% IDSS
VDS = 5 V; IDS = 25% IDSS
1.0
0.6
dB
Output Third-Order Intercept Point
(from 15 to 5 dB below P1dB)
IP3 VDS = 5V; IDS = 50% IDSS
Matched for optimal power
Matched for best IP3
36
38
39
dBm
Saturated Drain-Source Current IDSS V
DS = 1.3 V; VGS = 0 V 185 230 280 mA
Maximum Drain-Source Current IMAX VDS = 1.3 V; VGS ≅ +1 V 375 mA
Transconductance GM VDS = 1.3 V; VGS = 0 V 200 mS
Gate-Source Leakage Current IGSO V
GS = -5 V 1 15 µA
Pinch-Off Voltage |VP| VDS = 1.3 V; IDS = 0.75 mA 0.7 1.0 1.3 V
Gate-Source Breakdown Voltage |VBDGS| IGS = 0.75 mA 12 16 V
Gate-Drain Breakdown Voltage |VBDGD| IGD = 0.75 mA 12 16 V
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• ABSOLUTE MAXIMUM RATINGS1
Parameter Symbol Test Conditions Min Max Units
Drain-Source Voltage VDS -3V < VGS < +0V 8 V
Gate-Source Voltage VGS 0V < VDS < +8V -3 V
Drain-Source Current IDS For VDS > 2V IDSS mA
Gate Current IG Forward or reverse current 7.5 mA
RF Input Power2 P
IN Under any acceptable bias state 175 mW
Channel Operating Temperature TCH Under any acceptable bias state 175 ºC
Storage Temperature TSTG Non-Operating Storage -40 150 ºC
Total Power Dissipation PTOT See De-Rating Note below 1.8 W
Gain Compression Comp. Under any bias conditions 5 dB
Simultaneous Combination of Limits3 2 or more Max. Limits 80 %
1TAmbient = 22°C unless otherwise noted 2Max. RF Input Limit must be further limited if input VSWR > 2.5:1
3Users should avoid exceeding 80% of 2 or more Limits simultaneously
Notes:
• Operating conditions that exceed the Absolute Maximum Ratings will result in permanent damage to the device.
• Total Power Dissipation defined as: PTOT ≡ (PDC + PIN) – POUT, where:
P
DC: DC Bias Power
PIN: RF Input Power
POUT: RF Output Power
• Total Power Dissipation to be de-rated as follows above 22°C:
PTOT= 1.8W – (0.012W/°C) x TPACK
where TPACK = source tab lead temperature above 22
°
C
(coefficient of de-rating formula is the Thermal Conductivity)
Example: For a 65°C source lead temperature: PTOT = 1.8W – (0.012 x (65 – 22)) = 1.28W
• HANDLING PRECAUTIONS
To avoid damage to the devices care should be exercised during handling. Proper Electrostatic
Discharge (ESD) precautions should be observed at all stages of storage, handling, assembly, and
testing. These devices should be treated as Class 1A per ESD-STM5.1-1998, Human Body Model.
Further information on ESD control measures can be found in MIL-STD-1686 and MIL-HDBK-263.
• APPLICATIONS NOTES & DESIGN DATA
Applications Notes are available from your local Filtronic Sales Representative or directly from the
factory. Complete design data, including S-parameters, noise data, and large-signal models are
available on the Filtronic web site. Evaluation Boards available upon request.
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• BIASING GUIDELINES
¾ Active bias circuits provide good performance stabilization over variations of operating
temperature, but require a larger number of components compared to self-bias or dual-biased.
Such circuits should include provisions to ensure that Gate bias is applied before Drain bias,
otherwise the pHEMT may be induced to self-oscillate. Contact your Sales Representative for
additional information.
¾ Dual-bias circuits are relatively simple to implement, but will require a regulated negative
voltage supply for depletion-mode devices such as the FPD750SOT89.
¾ Self-biased circuits employ an RF-bypassed Source resistor to provide the negative Gate-Source
bias voltage, and such circuits provide some temperature stabilization for the device. A nominal
value for circuit development is 4.8 Ω for a 50% of IDSS operating point.
¾ For standard Class A operation, a 50% of IDSS bias point is recommended. A small amount of
RF gain expansion prior to the onset of compression is normal for this operating point. Note that
pHEMTs, since they are “quasi- E/D mode” devices, exhibit Class AB traits when operated at
50% of IDSS. To achieve a larger separation between P1dB and IP3, an operating point in the 25%
to 33% of IDSS range is suggested. Such Class AB operation will not degrade the IP3
performance.
• PACKAGE OUTLINE
(dimensions in mm)
All information and specifications subject to change without notice.
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• TYPICAL TUNED RF PERFORMANCE
Typical power and efficiency is shown above. The devices were biased nominally at VDS = 5V, IDS
= 50% of IDSS, at a test frequency of 1.85 GHz. The test devices were tuned (input and output
tuning) for maximum output power at 1dB gain compression.
Power Transfer Characteristic
VDS = 5V IDS = 50% IDSS at f = 1.85 GHz
22.0
22.5
23.0
23.5
24.0
24.5
25.0
25.5
26.0
456789101112
Input Power (dBm)
Output Power (dBm)
-0.50
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
Gain Compression (dB)
Pout (dBm) Comp Point
Drain Efficiency and PAE
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
1357911
Input Power (dBm)
PAE (%)
10.0%
20.0%
30.0%
40.0%
50.0%
60.0%
Drain Efficiency (%)
PAE Eff.
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
Note: pHEMT devices exhibit non-classical intermodulation performance, with equivalent IP3 values
exceeding 14 dB above P1dB. This IMD enhancement is affected by the quiescent bias current, the
Drain-Source voltage, and the tuning or matching applied to the device.
Maximum Stable Gain & S21
0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8
Frequency (GHz)
FPD750SOT89 5V / 50%IDSS
0
5
10
15
20
25
30
35
Mag S21 & MSG
MSG
S21
Typical Intermodulation Performance
VDS = 5V IDS = 50% IDSS at f = 1.85GHz
10
12
14
16
18
20
-7.1 -6.0 -5.0 -4.0 -3.0 -2.1 -1.0 0.0 1.0 1.9
Input Power (dBm)
Output Power (dBm)
-43.00
-38.00
-33.00
-28.00
-23.00
3rd Order IM Products (dBc)
Pout (dBm) 3rds (dBc)
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• TYPICAL OUTPUT PLANE POWER CONTOURS (VDS = 5V, IDS = 50%IDSS)
1850 MHz
Contours swept with a constant input
power, set so that nominal P1dB is
achieved at the point of optimum output
match.
Input (Source plane) Γs:
0.50 ∠ 142.8º
0.37 + j0.35 (normalized)
18.5 + j17.5 Ω
Nominal IP3 per
f
ormance is obtained
with this input plane match, and the
output plane match as shown.
900 MHz
Contours swept with a constant input
power, set so that nominal P1dB is
achieved at the point of optimum output
match.
Input (Source plane) Γs:
0.79 ∠ 36.9º
1.0 + j 2.6(normalized)
50 + j130 Ω
Nominal IP3 per
f
ormance is obtained
with this input plane match, and the
output plane match as shown.
0
1.
0
1.
0
-
1.
10
.0
10.
-
5.
0
5.
-
2.
0
2.
0
-
2.
3.
0
3.
-
4.
0
4.
-
0.
2
0.
-
0.
4
0.
-
0.
6
0.
6
-
0.
0.
8
0.
8
-
0.
Swp Max
145
Swp Min
1
24dBm
23dBm 22dBm
21dBm
20dBm
19dBm
25dBm
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• TYPICAL SCATTERING PARAMETERS (50Ω SYSTEM)
See Website “More Info” for S-parameter design files.
0
1.0 1.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
FPD750SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0.5GHz
S11
1 GHz
1.5 GHz
2 GHz
2.5 GHz
3 GHz
3.5 GHz
4 GHz
5 GHz 6 GHz
7 GHz
0
1.0 1.0-1.0
10.0
10.0
-10.0
5.0
5.0
-5.0
2.0
2.0
-2.0
3.0
3.0
-3.0
4.0
4.0
-4.0
0.2
0.2
-0.2
0.4
0.4
-0.4
0.6
0.6
-0.6
0.8
0.8
-0.8
FPD750SOT89 5V / 50%IDSS
Swp Max
8GHz
Swp Min
0.5GHz
S22
1 GHz
2 GHz
3 GHz
4 GHz
5 GHz
6 GHz 7 GHz
FPD750SOT89
LOW NOISE, HIGH LINEARITY PACKAGED PHEMT
Phone: +1 408 850-5790 http://www.filtronic.co.uk/semis Revised: 01/05/05
Fax: +1 408 850-5766 Email: sales@filcsi.com
• TYPICAL I-V CHARACTERISTICS
Note: The recommended method for measuring IDSS, or any particular IDS, is to set the Drain-Source
voltage (VDS) at 1.3V. This measurement point avoids the onset of spurious self-oscillation which
would normally distort the current measurement (this effect has been filtered from the I-V curves
presented above). Setting the VDS > 1.3V will generally cause errors in the current measurements,
even in stabilized circuits.
Recommendation: Traditionally a device’s IDSS rating (IDS at VGS = 0V) was used as a predictor of
RF power, and for MESFETs there is a correlation between IDSS and P1dB (power at 1dB gain
compression). For pHEMTs it can be shown that there is no meaningful statistical correlation
between IDSS and P1dB; specifically a linear regression analysis shows r2 < 0.7, and the regression
fails the F-statistic test. IDSS is sometimes useful as a guide to circuit tuning, since the S22 does vary
with the quiescent operating point IDS.
DC IV Curves FPD750SOT89
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Drain-Source Voltage (V)
Drain-Source Current (A)
VG=-1.50
VG=-1.25V
VG=-1.00V
VG=-0.75V
VG=-0.50V
VG=-0.25V
VG=0V
