DATA SHEET
Caution Observe precautions when handling because these devices are sensitive to electrostatic discharge.
The information in this document is subject to change without notice. Before using this document, please confirm that
this is the latest version.
Not all devices/types available in every country. Please check with local NEC Compound Semiconductor Devices
representative for availability and additional information.
GaAs FET
NES1823M-240
240 W L, S-BAND PUSH-PULL POWER GaAs FET
Document No. PG10117EJ02V0DS (2nd edition)
Date Published June 2003 CP(K)
Printed in Japan
NEC Compound Semiconductor Devices 2002, 2003
The mark •
••
• shows major revised poi nts.
DESCRIPTION
The NES1823M-240 is a 240 W push-pull type GaAs FET designed for high power transmitter applications for
IMT-2000 base station systems. It is capable of delivering 240 W of output power (CW) with high linear gain, high
efficiency and excellent distortion under the condition of 12 V operation. Its primary band is 1.8 to 2.3 GHz. The
device employs 0.7
µ
m Tungsten Silicide gates, via holes, plated heat sink, and silicon dioxide passivation for
superior performance, thermal characteristics, and reliability.
FEATURES
• Push-pull type GaAs FET
•V
DS = 12.0 V operation
• High output power: Pout = 240 W TYP.
• High linear gain: GL = 12.0 dB TYP.
• High power added efficiency:
η
add = 45% TYP. @ VDS = 12.0 V, IDset = 2.0 A (total), f = 2.17 GHz
• Hollow plastic package
ORDERING INFORMATION
Part Number Package Supplyi ng Form
NES1823M-240 T-92M ESD protec tive t ray
Remark To order evaluation samples, contact your neaby sales office.
Data Sheet PG10117EJ02V0DS
2
NES1823M-240
ABSOLUTE MAXIMUM RATINGS (TA = +25°
°°
°C)
Operation in excess of any one of these parameters may result in permanent damage.
Parameter Symbol Ratings Unit
Drain to Sourc e Voltage VDS 19 V
Gate to Source Voltage VGSO −7V
Gate to Drain V ol tage VGDO −26 V
Gate C urrent IG900 mA
Total Power Dissipation Ptot 250 W
Channel Temperature Tch 175 °C
Storage Temperat ure Tstg −65 to +150 °C
Gain Compression(CW) Gcomp 3.0 dB
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Test Condit i ons MIN. TYP. MAX. Unit
Drain to Sourc e Voltage VDS −12.0 12.0 V
Channel Temperature Tch −−
+150 °C
Set Drain Current IDset VDS = 12.0 V, RF OFF −2.0 6.0 A
Gate Resistance RgNote −0.6 1.2 Ω
Note Rg is the series resistance between the gate supply and the FET gate.
Rg =
ELECTRICAL CHARACTERISTICS (TA = +25°
°°
°C)
Parameter Symbol Test Condit i ons MIN. TYP. MAX. Unit
Pinch-of f Volt age VpVDS = 2.5 V, ID = 650 mA −0.8 −0.5 −0.2 V
Thermal Resistance Rth Channel to Case −0.30 0.40 °C/W
Output Power Pout f = 2.17 GHz, VDS = 12.0 V, 52.8 53.4 −dBm
Drain Current IDPin = 44.0 dBm, Rg = 0. 6 Ω,−38.5 −A
Power Added Ef fici enc y
η
add IDset = 2.0 A Total (RF OFF) Note1 −45 −%
Linear Gain GL Note2 11.0 12.0 −dB
Notes1. IDset = 1.0 A each drain
2. Pin = 33 dBm
R
g1
R
g2
G
1
G
2
D
1
D
2
S
V
GS
V
GS
Rg1 × Rg2
Rg1 + Rg2
Data Sheet PG10117EJ02V0DS 3
NES1823M-240
TYPICAL CHARACTERISTICS (TA = +25°
°°
°C)
V
DS
= 12 V, I
Dset
= 2.0 A
R
g
= 0.6 Ω
CW-signal, f = 2.14 GHz
OUTPUT POWER,
add
P
out
14
11
12
13
8
10
2.2 2.42.32.12.01.9
Gain G
L
(dB)
Frequency f (GHz)
9
GAIN vs. FREQUNCY RESPONSE
V
DS
= 12 V, I
Dset
= 2.0 A
R
g
= 0.6 Ω
CW, P
in
= 33 dBm
55
40
45
50
30
35
100
0
20
40
60
80
35 4540302520
Output Power P
out
(dBm)
Input Power P
in
(dBm)
Power Added Efficiency
add
(%)
η
add
η
−20
−50
−30
−25
−60
−55
40 5045353025
3rd/5th Order Inter Modulation Distortion IM
3
/IM
5
(dBc)
Average Output Power P
out
(dBm)
−35
−40
−45
V
DS
= 12 V,
R
g
= 0.6 Ω,
W-CDMA,
3 GPP test model 1, 64 DPCH,
2 carriers, Clipping 100%
f
1
= 2.135 GHz
f
2
= 2.145 GHz
(∆f = 10 MHz)
IM
3
, I
Dset
= 2 A
IM
3
, I
Dset
= 3 A
IM
3
, I
Dset
= 4 A
IM
5
, I
Dset
= 2 A
IM
5
, I
Dset
= 3 A
IM
5
, I
Dset
= 4 A
IM
5
@Bandwidth = 3.84 MHz
IM
3
@Bandwidth = 3.84 MHz
10 MHz 10 MHz
10 MHz 10 MHz
10 MHz
(SET I
DS
DEPENDENCE)
IM
3
/IM
5
vs. AVERAGE OUTPUT POWER
η
vs. INPUT POWER
(SET I
DS
DEPENDENCE)
V
DS
= 12 V,
R
g
= 0.6 Ω,
W-CDMA,
3 GPP test model 1, 64 DPCH,
2 carriers, Clipping 100%
f
1
= 2.135 GHz
f
2
= 2.145 GHz
(∆f = 10 MHz)
I
Dset
= 2 A
I
Dset
= 3 A I
Dset
= 4 A
40
10
30
35
0
5
40 5045353025
Power Added Efficiency
add
(%)
Average Output Power P
out
(dBm)
25
20
15
η
add
vs. AVERAGE OUTPUT POWER
η
Data Sheet PG10117EJ02V0DS
4
NES1823M-240
−25
−55
−35
−30
−65
−60
40 5045353025
Adjacent Channel Leakage Power Ratio ACPR (dBc)
Average Output Power P
out
(dBm)
−40
−45
−50
V
DS
= 12 V,
R
g
= 0.6 Ω,
W-CDMA,
3 GPP test model 1, 64 DPCH,
1 carriers, Clipping 100%
f = 2.14 GHz
5 MHz, I
Dset
= 2 A
(SET I
DS
DEPENDENCE)
A CPR
vs. AVERAGE OUTPUT POWER
5 MHz, I
Dset
= 3 A
5 MHz, I
Dset
= 4 A
10 MHz, I
Dset
= 4 A
10 MHz, I
Dset
= 2 A
10 MHz, I
Dset
= 3 A
5 MHz
10 MHz
5 MHz
10 MHz
∆f = 5 MHz, 10 MHz
@Bandwidth = 3.84 MHz
−70
Remark The graphs indicate nominal characteristics.
Data Sheet PG10117EJ02V0DS 5
NES1823M-240
LARGE SIGNAL IMPEDANCES
(HALF (EACH SIDE) DEVICE OPTIMAL INPUT AND OUTPUT IMPEDANCE)
50 Ω
termination 50 Ω
termination
Zsource Zload
Input side matching
network of the
attached text fixture
Output side matching
network of the
attached text fixture
Zsource Zload
G
1
D
1
G
2
D
2
S
Remarks1. Zin = Rin + jXin (Conjugate of Zsource for single ended device)
Zout = Rout + jXout (Conjugate of Zload for single ended device)
2. Zout was chosen based on tradeoffs between gain, PAE and IM.
f (GHz) Zin (Ω)Z
out (Ω)f (GHz)Z
in (Ω)Z
out (Ω)
2.10 1.063 − j7. 204 3.862 − j5.151 2.20 1.268 − j3.319 4.441 − j3.539
2.11 1.060 − j6.685 3.994 − j4.854 2.21 1.283 − j2.838 4.463 − j3.350
2.12 1.111 − j6.233 4.114 − j4.653 2.22 1.315 − j2.518 4.462 − j3.257
2.13 1.129 − j5.839 4.218 − j4.519 2.23 1.401 − j2.172 4.451 − j3.102
2.14 1.135 − j5.403 4.296 − j4.400 2.24 1.458 − j1.777 4.429 − j2.921
2.15 1.173 − j5.161 4.368 − j4.304 2.25 1.544 − j1.408 4.452 − j2.755
2.16 1.176 − j4.735 4.402 − j4.083 2.26 1.622 − j1.129 4.454 − j2.614
2.17 1.188 − j4.384 1.382 − j3.948 2.27 1.711 − j0.773 4.456 − j2.431
2.18 1.184 − j4.013 4.442 − j3.780 2.28 1.794 − j0.482 4.399 − j2.184
2.19 1.201 − j3.694 4.457 − j3.726 2.29 1.899 − j0.180 4.454 − j2.074
2.30 1.971 + j0.174 4.493 − j1.836
S-PARAMETERS
S-parameters/Noise parameters are provided on the NEC Compound Semiconductor Devices Web site in a form
(S2P) that enables direct import to a microwave circuit simulator without keyboard input.
Click here to download S-parameters.
[RF and Microwave] → [Device Parameters]
URL http://www.csd-nec.com/
Test fixture tuning condition
VDS = 12 V, IDset = 2.0 A
Rg = 0.6 Ω, PIN = 44 dBm
Data Sheet PG10117EJ02V0DS
6
NES1823M-240
EVALUATION PWB CIRCUIT
OUTPUT
(50 Ω)
STB out
C25
C23 +
C3 C11
R3
R4
C1 C4
R1
L1 L3
BALUN in (gnd)
INPUT
(50 Ω)
STB in
C7
C8 C9
C10
C12
STB in (R)
C26
C24
+
C6 C13
R6
R5
C2 C5
R2
L2 L4
BALUN in (sig)
STB in (L)
Device in
V
GS
V
GS
C29 C27
+
C21
C17
C15
BALUN out (sig)
C18
C19
C14
STB out (R)
C32 C28
+
C16
L6
BALUN out (gnd)
STB out (L)
Device out
V
DS
(12 V)
V
DS
(12 V)
L5
L7
C31
C20
L8
C22
C30
G
1
D
1
G
2
D
2
Data Sheet PG10117EJ02V0DS 7
NES1823M-240
EVALUATION PWB PARTS LAYOUT
B1 B2
Gate Bias
Gate Bias Drain Bias (12 V)
Drain Bias (12V)
INPUT
(50 Ω)
C26
Note
C25
Note
C29
Note
C31
Note
C32
Note
C30
Note
C6
C24
C2
R2
C5
R5
R6
C13
C23
C1
R1
C4
C3
R3
R4
C11
C7
C8
C9
C10
C12
C14
C15
C17
C21
C27
C18
C19
OUTPUT
(50 Ω)
C20
C16
C22
C28
60 mm
69 mm 69 mm
Note Feed-through capacitor
Parts Name Parts Value
C12, C14 1 pF chip capacitor
C4, C5, C11, C13 4 pF chip capacitor
C18, C19 10 pF chip capacitor
C7, C8, C9, C10 12 pF chip capacitor
C15, C16 22 pF chip capacitor
C1, C2, C3, C6 1 000 pF chip capacitor
C25, C26, C29, C30, C31, C32 1 000 pF feed-through capacitor
C17, C20 0.1
µ
F chip capac i t or
C21, C22 10
µ
F chip capac i t or (25 V )
C23, C24, C27, C28 100
µ
F Elect rol ytic capacit or (25 V )
R3, R4, R5, R6 2.2 Ω chip resistor (1/4 W)
R1, R2 10 Ω chip resistor (1/4 W)
B1, B2 BALUN
Circuit B oard Material ; Teflon, E r = 2.6,
PWB Thickness : 0.8 mm,
Cu-Pattern Thickness : 18
µ
m
BALUN
(An example of Assembly)
24.5 mm
7 mm
7 mm
Data Sheet PG10117EJ02V0DS
8
NES1823M-240
PACKAGE DIMENSIONS
T-92M (UNIT: mm)
PIN CONNECTIONS
G1, G2
D1, D2
S
: Gate
: Drain
: Source
4.0±0.3 1.4±0.3
30.4±0.25
S
8.0±0.20.6±0.3 17.4±0.15
9.7±0.2
35.2±0.25
23.9±0.3
2.6±0.3
S
4–R1.3
4–C1.5
D1 D2
G1 G2
45˚
2.4±0.2
6.0 MAX.
2.1±0.3
2.7 MIN.2.7 MIN.
Data Sheet PG10117EJ02V0DS 9
NES1823M-240
RECOMMENDED MOUNTING CONDITIONS FOR CORRECT USE
(1) Fix to a heat sink or mount surface completely with screws at the four holes of the flange.
(2) The recommended torque strength of the screws is 29.4 N⋅cm typical using M2.3 type screws.
(3) The recommended flatness of the mount surface is less than ±10
µ
m (roughness of surface is ∇∇∇).
RECOMMENDED SOLDERING CONDITIONS
This product should be soldered and mounted under the following recommended conditions. For soldering
methods and conditions other than those recommended below, contact your nearby sales office.
Soldering Method Soldering Condit i ons Condition Symbol
Partial Heating Peak temperat ure (pi n t emperature) : 350°C or below
Soldering ti me (per pin of dev i ce) : 3 sec onds or l ess
Maximum chlorine content of rosin flux (% mass) : 0.2%(Wt.) or below
HS350-P3
Caution Do not use different soldering methods together (except for partial heating).
DEFINIITON OF THERMAL RESISTANCE
This thermal resistance (Rth : channel to case) guaranteed in the electrical characteristics shows the value
between chip surface and the backside surface of the package.
The thermal resistance between chip surface and mount surface is 0.2 (MAX.) °C/W larger than the thermal
resistance value guaranteed in the electrical characteristics, when the package is under the above-mentioned
recommendation mounting condition screwed down.
Data Sheet PG10117EJ02V0DS
10
NES1823M-240
M8E 00. 4 - 0110
The information in this document is current as of June, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
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•
•
•
•
•
•
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TEL: +1-408-988-3500 FAX: +1-408-988-0279
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5th Sales Group, Sales Division TEL: +81-44-435-1588 FAX: +81-44-435-1579 E-mail: salesinfo@csd-nec.com
For further information, please contact
NES1823M-240
Caution GaAs Products This product us es gallium arsenide (GaAs).
GaAs vapor and powder are hazardous to human health if i nhal ed or i ngested, so please obs erve
the foll owi ng poi nt s.
• Follow related l aws and ordinances when di sposing of the product. If there are no appl i cable laws
and/or ordinances, dis pose of the produc t as recom m ended bel ow.
1. Commission a di s posal com pany able to (wit h a l i cense to) collect, transport and dis pos e of
materials that contain ars eni c and other suc h i ndustrial waste mat eri al s.
2. Exclude the produc t from general i ndustrial waste and househol d garbage, and ensure that the
product is control l ed (as indust rial waste subj ect to special control) up unt i l f i nal di sposal.
• Do not burn, destroy, cut, crush, or c hem i cally di s solve t he product.
• Do not lic k the product or i n any way all ow i t to enter the m outh.
