LPC8N04FHI24E - NXP SEMICONDUCTORS

1. General description

The NXP LPC8N04 is an IC optimized for an entry level Cortex-M0+ MCU with built-in

NFC interface. LPC8N04 supports an ef fective system solution with a minimal number of

external components for NFC related applications.

The embedded ARM Cortex-M0+ offers flexibility to the users of this IC to implement their

own dedicated solution . The LPC8N04 contains multiple features, including multiple

power-down modes and a selectable CPU frequency of up to 8 MHz, for ultra-low power

consumption.

Users can program this LPC8N04 with the industry-wide standard solutions for ARM

Cortex-M0+ processors.

LPC8N04

32-bit ARM Cortex®-M0+ microcontroller; 32 kB flash and 8 kB

SRAM; NFC/RFID ISO 14443 type A interface

Rev. 1.4 — 8 June 2018 Product data sheet

CAUTION

This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling

electrostatic sensitive devices.

Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or

equivalent standards.

CAUTION

Semiconductors are light sensitive. Exposure to light sources can cause the IC to

malfunction. The IC must be protected against light. The protection must be applied to all

sides of the IC.

Product data sheet Rev. 1.4 — 8 June 2018 2 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

2. Features and benefits

System

ARM Cortex-M0+ processor running at frequencies of up to 8 MHz

ARM Cortex-M0+ built-in Nested Vectored Interrupt Controller (NVIC)

ARM Serial Wire Debug (SWD)

System tick timer

IC reset input

Memory

32 kB on-chip flash programming memory

4 kB on-chip EEPROM of which 256 byte can be write protected

8 kB SRAM

Digital peripherals

Up to 12 General Purpose Input Output (GPIO) pins with configurable

pull-up/pull-down resistors and repeater mode

GPIO pins which can be used as edge and level sensitive interrupt sources

High-current drivers/sinks (20 mA) on four GPIO pins

High-current drivers/sinks (20 mA) on two I2C-bus pins

Programmable Wa tchDog Timer (WDT)

Analog peripherals

Temperat ur e se ns or with 1.5 C absolute temperature accuracy between 40 C

and +85 C

Communication interfaces

NFC/RFID ISO 14443 type A interface

I2C-bus interface supporting full I2C-bus specification and fast mode with a data

rate of 400 kbit/s, with multiple addre ss re co gn itio n an d mon i to r mo de

Energy harves ting fu nct i ona lity to po we r th e LPC 8N0 4 .

OTA firmware update using Secondary Bootloader (SBL) library (See TN00040:

LPC8N04: Encrypted Over the Air (OTA) Firmware update using NFC). OTA firmware

update available on Boot ROM version 0.14.

Clock generation

8 MHz internal RC oscillator, trimmed to 2 % accuracy, which is used for the

system clock

Timer oscillator operating at 32 kHz linked to the RTC timer unit

Power control

Support for 1.72 V to 3.6 V external voltages

The LPC8N04 can also be powered from the NFC field

Activation via NFC possible

Integrated Power Management Unit (PMU) for versatile control of power

consumption

Four reduced power modes for ARM Cortex-M0+: sleep, deep sleep , deep

power-down and battery off

Power gating for each analog peripheral for ultra-low power operation

< 50 nA IC current consumption in battery off mode at 3.0 V

Power-On Reset (POR)

Product data sheet Rev. 1.4 — 8 June 2018 3 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

Unique device serial number for identification

3. Applications

Configurable LED strip/christmas tree LEDs via NFC

Smart toy/interactive robot data logger

Buttonless/contactless control panel

Contactle ss diagnostic

NFC e-locker

Smart manufacturing

NFC OTA

4. Ordering information

5. Marking

The LPC8N04 HVQFN24 package has the following top-side marking:

•First line: Syww

–yww: Date code with y = year and ww = week.

•Second line: xxxx

•Third line: LPC8N04

Table 1. Ordering information

Type number Package

Name Description Version

LPC8N04FHI24 HVQFN24 plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4  4  0.85 mm SOT616-3

Fig 1. HVQFN24 package marking

aaa-014382

Terminal 1 index area

NXP

Product data sheet Rev. 1.4 — 8 June 2018 4 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

6. Block diagram

The internal block diagram of the LPC8N04 is shown in Figure 2. It consists of a Power

Management Unit (P MU), clocks, timer s, a digital computation and control cluster (ARM

Cortex-M0+ and memories) and AHB-APB slave modules.

Fig 2. LPC8N04 block diagram

POWER

PADS

WAKE-UP

TIMER

32 kHz FRO

CLOCK

SHOP

EXTERNAL

POWER

SWITCH

INTERNAL

POWER

SWITCHES

POR

LDO (1.6 V)

LDO (1.2 V)

8 MHz FRO

MFIO

(DIGITAL)

HIGH

DRIVE

DIGITAL

SWITCH

MATRIX I2C-BUS SPI GPIO

32 kB FLASH

4 kB EEPROM

ARM M0+

AHB-APB BRIDGE

8 kB SRAM

PMU

NFC/RFID

FLASH

CONTROL

EEPROM

CONTROL

TIMERS WATCHDOG SYSCONFIG

IOCONFIG

TEMPERATURE

SENSOR

I2C-BUS

aaa-015348

Product data sheet Rev. 1.4 — 8 June 2018 5 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

7. Pinning information

7.1 Pinning

7.1.1 HVQFN24 package

Figure 3 shows the pad layout of the LPC8N04 in the HVQFN24 package.

[1] High source current pads; see Section 8.6.3.

[2] These pads must be tied to ground.

Fig 3. Pad co nfiguration HVQFN24

Table 2. Pad allocation table of the HVQFN24 package

Pad Symbol Pad Symbol

1 PIO0_0/WAKEUP 13[1] PIO0_7/CT16B_M1

2 PIO0_1/CLKOUT 14[1] PIO0_3/CT16B_M0

3 PIO0_2/SSEL 15[1] PIO0_10/CT32B_M0/SWCLK

4 PIO0_6/SCLK 16[1] PIO0_11/CT32B_M1/SWDIO

5 PIO0_8/MISO 17[2] RESERVED

6 PIO0_9/MOSI 18[2] RESERVED

7VDDBAT 19LB

8VSS 20LA

9 RESETN 21[2] RESERVED

10 RESERVED 22[2] RESERVED

11 PIO0_4/SCL 23[2] RESERVED

12 PIO0_5/SDA 24[2] RESERVED

aaa-015349

Transparent top view

PIO0_7/CT16B_M1

PIO0_8/MISO

PIO0_9/MOSI

PIO0_3/CT16B_M0

PIO0_6/SCLK PIO0_10/CT32B_M0/SWCLK

PIO0_2/SSEL PIO0_11/CT32B_M1/SWDIO

PIO0_1/CLKOUT (reserved)

PIO0_0/WAKEUP (reserved)

25 VSS

VDDBAT

VSS

RESETN

(reserved)

PIO0_4/SCL

PIO0_5/SDA

(reserved)

terminal 1

index area

613

514

415

316

217

118

Product data sheet Rev. 1.4 — 8 June 2018 6 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

[1] The GPIO port is a 12-bit I/O port with individual direction and function controls for each bit. The operation

of port 0 pads depends on the function selected through the IOCONFIG register block.

[2] If external wake-up is enabled on this pad, it must be pulled HIGH before entering deep power-down mode

and pulled LOW for a minimum of 100 s to exit deep power-down mode.

[3] A LOW on this pad resets the device. This reset causes I/O ports and peripherals to take on their default

states, and processor execution to begin at address 0. It has weak pull-up to VDDBAT.

Table 3. Pad description of the HVQFN24 package

Pad Symbol Type Description

Supply

7 VDDBAT supply positive supply voltage

8 VSS supply ground

GPIO[1]

1 PIO0_0 I/O GPIO

WAKEUP I deep power-down mode wake-up pin[2]

2 PIO0_1 I/O GPIO

CLKOUT O clock output

3 PIO0_2 I/O GPIO

SSEL I SPI/SSP serial select line

14 PIO0_3 I/O GPIO

CT16B_M0 O 16-bit timer match output 0

11 PIO0_4 I/O GPIO

SCL I/O I2C-bus SCL clock line

12 PIO0_5 I/O GPIO

SDA I/O I2C-bus SDA data line

4 PIO0_6 I/O GPIO

SCLK I/O SPI/SSP serial clock line

13 PIO0_7 I/O GPIO

CT16B_M1 O 16-bit timer match output 1

5 PIO0_8 I/O GPIO

MISO O SPI/SSP master-in slave-out line

6 PIO0_9 I/O GPIO

MOSI I SPI/SSP master-out slave-in line

15 PIO0_10 I/O GPIO

CT32B_M0 O 32-bit timer match output 0

SWCLK I ARM SWD clock

16 PIO0_11 I/O GPIO

CT32B_M1 O 32-bit timer match output 1

SWDIO I/O ARM SWD I/O

Radio

20 LA A NFC antenna/coil terminal A

19 LB A NFC antenna/coil terminal B

Reset

9 RESETN I external reset input[3]

Product data sheet Rev. 1.4 — 8 June 2018 7 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8. Functional description

8.1 ARM Cortex-M0+ core

Refer to the Cortex-M0+ Devices Technical Reference Manual (Ref. 1) for a detailed

description of the ARM Cortex-M0+ processor.

The LPC8N04 ARM Cortex-M0+ core has the following configuration:

•System options

–Nested Vectored Interrupt Controller (NVIC)

–Fast (single-cycle) multiplier

–System tick timer

–Support for wake-up interrupt controller

–Vector table remapping register

–Reset of all registers

•Debug options

–Serial Wire Debug (SWD) with two watchpoint comparators and four breakpoint

comparators

–Halting debug is supp orted

8.2 Memory map

Figure 4 shows the memory and peripheral address space of the LPC8N04.

The only AHB peripheral device on the LPC8N04 is the GPIO module. The APB

peripheral area is 512 kB in size. Each peripheral is allocated 16 kB of space.

All peripheral register addresses are 32-bit word aligned. Byte and half-word addre ssing is

not possible. All read ing an d writing are done per full word.

Product data sheet Rev. 1.4 — 8 June 2018 8 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.3 System configuration

The system configuration APB block controls oscillators, start logic and clock generation

of the LPC8N04. Also included in this block is a register for remapping the interrupt vector

table.

8.3.1 Clock generation

The LPC8N04 Clock Generator Unit (CGU) includes two independent RC oscillators.

These oscillators are the System Free-Running Oscillator (SFRO) and the Timer

Free-Running Oscillator (TFRO).

Fig 4. LPC8N04 me mory map

aaa-017231

0x4000 0000

0x4000 4000

0x4000 C000

0x4003 4000

0x4001 4000

0x4003 C000

0x4003 8000

0x4004 0000

0x4004 4000

0x4004 8000

0x4005 4000

0x4005 8000

0x4006 0000

l2C-bus

watchdog timer

(reserved)

16-bit timer

(reserved)

32-bit timer

(reserved)

EEPROM controller

PMU

flash controller

SPI/SSP

IOCONFIG

system configuration

(reserved)

RTC timer

(reserved)

RFID/NFC

(reserved)

temperature sensor

0x0000 7FFF

0x0000 0000

0x0FFF FFFF

0x0000 8000

0x2FFF FFFF

0x1000 2000

0x1000 1FFF

0x1000 0000

0x3000 0FFF

0x3000 0000

0x3000 1000

0x3FFF FFFF

0x4007 FFFF

0x4000 0000

0x4FFF FFFF

0x4008 0000

0x501F FFFF

0x5000 0000

0x5020 0000

0xE01F FFFF

0xE000 0000

0xFFFF FFFF

0xE020 0000

0xDFFF FFFF

(reserved)

private peripheral bus

AHB peripherals

APB peripherals

4 kB EEPROM

8 kB SRAM

32 kB on-chip flash

0x5001 0000

0x5000 FFFF

0x5000 0000

0x501F FFFF

GPIO PIO0

(reserved)

AHB peripherals

APB peripherals

Product data sheet Rev. 1.4 — 8 June 2018 9 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

The SFRO runs at 8 MHz. The system clock is derived from it and can be set to 8 MHz,

4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz or 62.5 kHz (Note: some features are

not available when using the lower clock speeds). The TFRO runs at 32.768 kHz and is

the clock source for the timer unit. The TFRO cannot be disabled.

Following reset, the LPC8N04 starts operating at th e defau lt 500 kHz system clock

frequency to minimize dynamic current consumption during the boot cycle.

The SYSAHBCLKCTRL register gates the system clock to the various peripherals and

memories. The temperature sensor receives a fixed clock frequency, irrespective of the

system clock divider settings, while the digital part uses the system clock (AHB clock 0).

8.3.2 Reset

Reset has three sources on the LPC8N04: the RESETN pin, watchdog reset and a

software reset.

Fig 5. LPC8N04 clock generator block diagram

aaa-015352

SYSTEM FRO

(8 MHz)

SYSTEM CLOCK

DIVIDER

SYSCLKTRIM

fixed-frequency taps

system clock (AHB clock 0)

peripheral clocks

analog peripheral clocks

SPI/SSP

WDT_PCLK

wake-up timer

PMU/always-on-domain

SYSCLKDIV[2:0]

SPI/SSP CLOCK

DIVIDER

SSPCLKDIV

WDTCLKDIV

SYSAHBCLKCTRL

TIMER FRO

(32 kHz)

TMRCLKTRIM

TMRUEN

WATCHDOG CLOCK

DIVIDER

WDTSEL

Product data sheet Rev. 1.4 — 8 June 2018 10 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.4 Power management

The Power Management Unit (PMU) controls the switching between available power

sources and the powering of the different voltage domains in the IC.

8.4.1 System power architecture

The LPC8N04 ac cep ts power from tw o different sour ce s: fro m the exte rn al po we r su pp ly

pin VDDBAT, or from the built-in NFC/RFID rectifier.

The LPC8N04 has a small automatic source selector that monitors the power inputs

(VBAT and VNFC, see Figure 6) as well as pin RESETN. The PSWBAT switch is kept

open until a trigger is given on pin RESETN or via the NFC field. If the trigger is given, the

always-on domain, VDD_ALON, itself is powered via the PSWBAT or the PSWNFC

switch: via VBAT, if VBAT > 1.72 V, or VNFC. Priority is given to VBAT when both VBAT

and VNFC are pres en t.

The automatic source selector unit in the PMU decides on the powering of the internal

domains based on the power source.

•If a voltage > 1.72 V is detected on VBAT and not VNFC, VBAT powers the internal

domains after a trigger on pin RESETN or via NFC.

•If a voltage  1.72 V is detected on VBAT, and a higher voltage is detected on VNFC,

the internal domains are powered from VNFC.

•If a voltage > 1.72 V is detected at both VBAT and VNFC, the internal domains are

powered from VBAT.

•Switch over between power sources is possible. If initially both VBAT and VNFC are

available, the system is powered from VBAT. If VBAT then becomes unavailable

(because it is switched off externally, or by a PSWBAT/PSWNFC power switch

override), the internal domains are immediately powered from VNFC. Switch over is

supported in both directions.

•The user can force the selection of the VBAT input by disab ling the automatic power

switch, which disables the automatic source selector voltage comparator.

When on NFC power only (passive operation), connecting one or more 100 nF external

capacitors in parallel to a GPIO pad, and se tting that pad as an output driven to logi c 1 , is

advised. Preferably a high-dr ive pin should be chosen and se veral pins can be con nected

in parallel.

PSWNFC and PSWBAT are the power switches. PSWNFC connects power to the

VDD_ALON power net when an RF field is present. PSWBAT connects power from the

battery when a positive edge is detected on RESETN. If no RF power is available, the

PMU can open this PSWBAT switch, effectively switching off the device. After connecting

VDDBAT to a power source, the PSWBAT switch is open until a rising edge is detected on

RESETN or RF power is applied.

Each component of the LPC8N04 resides in one of several internal power domains, as

indicated in Figure 6. The domains ar e VBAT, VNFC, VDD_ALON, VDD1V2 and

VDD1V6. The domains VDD_ALON, VDD1V2 and VDD1V6 are powered, or not,

depending on the mo de of the LPC8N04. There are five modes: active, sleep, deep sle ep,

deep power-down and battery off.

Product data sheet Rev. 1.4 — 8 June 2018 11 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

The VDD_ALON domain contains BrownOut Detection (BOD). When enabled, if the

VDD_ALON voltage drops below 1.8 V it raises a BOD interrupt.

The PMU controls the active, sleep, deep sleep and deep power -down modes, and thus

the power flow to the different internal components.

The PMU has two LDOs powering the internal VDD1V2 and VDD1V6 voltage domains.

LDO1V2 converts voltages in the range 1.72 V to 3.6 V into 1.22 V. LDO1V6 converts

voltages in the range 1.72 V to 3.6 V into 1.6 V. Each LDO can be enab led separately. A

1.2 nF buffer capacitor is included at the input of the LDOs when powered via VNFC.

The trigger detector (not shown in Figure 6) and power gate have a leakage of less than

50 nA to allow for long shelf life before activation.

The PMU states and settings of the LDOs are summarized in Table 4, and the state

transitions are shown in Figure 7.

Table 5 and Table 6 summarize the events that can influence wake-up from deep

power-down or deep sleep modes (DEEPPDN or DEEPSLEEP to ACTIVE state

transition).

Fig 6. LPC8N0 4 po we r a rchi te ctu re

aaa-019962

AUTOMATIC SOURCE SELECTOR UNIT

< 1.85 V

1.72 V to 3.6 V

1.2 V

75 kΩ

PMU

32 kHz FRO

ALWAYS-ON DOMAIN

pin mode override if PCON.WAKEUP set,

when entering Deep power-down mode

DIGITAL CORE

PERIPHERALS

VDD_ALON

PSWNFC

PSWBAT

VNFC

VBAT

RESETN

VDDBAT

PIO0_0

WAKEUP

ANALOG

PERIPHERALS,

FLASH MEMORY

EEPROM MEMORY

NFC core

RTC

BOD

LDO1V2

SFRO

LDO1V6

GPREGx

1.6 V

Product data sheet Rev. 1.4 — 8 June 2018 12 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

[1] DPDN indicates whether the system is in deep power-down mode.

[2] X = don’t care.

The power-up sequence is shown in Figure 8. Applying batte ry powe r wh en th e PSWBAT

switch is closed, or NFC power becomes available, provides the always-on part with a

Power-On Reset (POR) signal. The TFRO is initiated which starts a state machine in the

PMU. In the first state, the LDO1V2 powering the digital domain is started. In the second

state, the LDO1 V6 powering the analog domain is started which starts the flash memory.

Enabling the LDO1V2, and the SFRO stabilizing, triggers the system_por. The system is

now considered to be ‘on’. The system can boot when the flash memory is fully

operational.

The total start-up time from trigger to active mode/boot is about 2.5 ms.

If there is no battery power, but there is RF power, the same procedure is followed except

that PSWNFC connects power to the LDOs.

The user cannot disable the TFRO as it is used by the PMU.

Remark: When running without a battery, energ y harvesting is limited to 2 MHz system

clock.

Table 4. IC power states

State VDD_ALON DPDN[1] Sleep or

Deep-sleep LDO1

1.2 V LDO2

1.6 V

NOPOWER no X[2] X[2] off off

ACTIVE yes 0 0 on on

DEEPPDN yes 1 0 off off

SLEEP/DEEPSLEEP yes 0 1 on on

Fig 7. PMU state transition diagram

aaa-019373

BATTERY-OFF

ACTIVE

DEEP

POWER-DOWN

SLEEP OR

DEEP-SLEEP

Product data sheet Rev. 1.4 — 8 June 2018 13 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.4.1.1 Applying power to the PCB/system with battery for the first time

To support long shelf life without draining the battery, the LPC8N04 is not connecte d to an

external supply pin until RESET pin is asserted and de-asserted or the NFC field is

present. Once the RESET or the NFC field is applied, the LPC8N04 is powered.

8.4.2 Power Management Unit (PMU)

The Power Management Unit (PMU) partly resides in the digital power domain and partly

in the always-on domain. Th e PMU controls the slee p, deep sleep and deep power-down

modes and the power flow to the different internal circuit blocks. Five general-purpose

registers in the PMU can be used to retain data during deep power-down mode. These

registers are located in the always-on domain. The PMU also raises a BOD interrupt, if

necessary, if VDD_ALON drops below 1.8 V.

The power to the different APB analog slaves is controlled through a power-down

configuration register.

Table 5. State transition events for DEEPSLEEP to ACTIVE

Event Description

RESETN reset asserted

RTC event if the timer reaches preset value

Watchdog watchdog issues interrupt or reset

WAKEUP signal on WA KEUP pin

RF field RF field is detected, potential NFC command input (if set in PMU)

Start logic interrupt one of the enabled start logic interrupts is asserted

Table 6. State transition events for DEEPPDN to ACTIVE

Event Description

RESETN reset asserted

RTC event if the timer reaches preset value

WAKEUP signal on WAKEUP pin (when enabled)

RF field RF field is detected, potential NFC command input (if set in PMU)

Fig 8. LPC8N04 power-up seque nce

aaa-016479

VDD_ALON

start TFRO enable 1.2 V LDO

enable 1.6 V LDO

for analog domain

and flash memory

POR always-on

domain

SFRO starts running

power

flash and

digital

power

analog

off

SFRO stable (64 μs)

system_por

Product data sheet Rev. 1.4 — 8 June 2018 14 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

The power control register selects whethe r an ARM Cortex-M0+ controlled power-down

mode (sleep mode or de ep sleep m ode) o r the deep p ower-down mo de is entere d. It also

provides the flags for sleep or deep-sleep modes and deep power-down mode

respectively. In addition, it contains the overrides for the power source selection.

8.5 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is a part of the ARM Cortex-M0+. The

tight integration of the processor core and NVIC enables fast processing of interrupts,

dramatically reducing the interrupt latency.

8.5.1 Features

•NVIC that is a part of the ARM Cortex-M0+

•Tightly coupled interr u pt co nt ro ller provides low interrupt latency

•Controls system exceptions and peripheral interrupts

•Four programmable interrupt priority levels with hardware priority level masking

•Software interrupt generation

8.5.2 Interrupt sources

Table 7 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lin es to the NVIC. Each line may r epresent more than one

interrupt source. There is no significance or priority about which line is connected where,

except for certain standards from ARM.

Table 7. Connection of interrupt source to the NVIC

Exception

number Vector

offset Function Flags

0 to 12 - start logic wake-up

interrupts each interrupt connected to a PIO0 input pin serves as

wake-up from deep-sleep mode[1]

13 - RFID/NFC RFID/NFC access detected /command

received/read acknowledge

14 - RTC on/off timer RTC on/off timer event interrupt

15 - I2C-bus Slave Input (SI) (state change)

16 - CT16B 16-bit timer

17 - PMU power from NFC field detected

18 - CT32B 32-bit timer

19 - BOD brownout detection (power drop)

20 - SPI/SSP TX FIFO half empty/RX FIFO half full/

RX time-out/RX overrun

21 - TSENS temperature sensor end of conversion/low threshold/

high threshold

22 to 25 - - RESERVE D

26 - WDT watchdog interrupt (WDINT)

27 - flash flash memory

28 - EEPROM EEPROM memory

29 to 30 - - RESERVE D

31 - PIO0 GPIO interrupt status of port 0

Product data sheet Rev. 1.4 — 8 June 2018 15 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

[1] Interrupt 0 to 10 correspond to PIO0_0 to PIO0_10; interrupt 11 corresponds to RFID/NFC external access;

interrupt 12 corresponds to the RTC on/off timer.

8.6 I/O configuration

The I/O configura tio n re gis t ers co nt ro l the el ectrical characteristics of the pads. The

following features are progr ammable:

•Pin function

•Internal pull-up/pull-down resistor or bus keeper function

•Low-pass filter

•I2C-bus mode for pads hosting the I2C-bus function

The IOCON register s con tr ol th e fu nct ion (GPI O or peripheral function), the input mode,

and the hysteresis of all PIO0_m pins. In addition, the I2C-bus pins can be configured for

different I2C-bus modes.

The FUNC bits in the IOCON registers can be set to GPIO (FUNC = 000) or to a

peripheral function. If the pins are GPIO pins, the GPIO0DIR registers determine whether

the pin is configured as an inp ut or outpu t. For any per iph eral function, the pin dir ection is

controlled automatically depending on th e functionality of the pin. The GPIO0DIR

registers have no effect on peripheral functions.

8.6.1 PIO0 pin mode

The MODE bits in the IOCON register allow the selection of on-chip pull-up or pull-down

resistors for each pin, or to select the repeater mode. The possible on-chip resistor

configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The

default value is no pull-up or pull- down enabled. The repeater mode enables the pull-up

resistor when the pin is at logic 1, and enables the pull-down resistor when the pin is at

logic 0. This mode causes the pin to retain its last known state if it is configured as an

input and is not driven externally. The state retention is not applicable to the deep

power-down mode. Repeater mode is typically used to prevent a pin fr om floating whe n it

is temporarily not driven. Allowing it to float could potentially use significant power.

8.6.2 PIO0 I2C-bus mode

If the FUNC bits of registers PIO0_4 and PIO0_5 select the I2C-bus function, the I2C-bus

pins can be configured for different I2C-bus modes:

•Standard mode/fast mode I2C-bus with input glitch filter (including an open-drain

output according to the I2C-bus specification)

•Standard open-drain I/O functionality without input filter

8.6.3 PIO0 current source mode

PIO0_3, PIO0_7, PIO0_10 and PIO0_11 are high-source pads that can deliver up to

20 mA to the load. These PIO pins can be set to either digital mode or analog current sink

mode. In digital mode, the output voltage of the pad switches between VSS and VDD. In

analog curr ent drive mode , the output cu rrent sink switches between the values set by the

ILO and IHI bits. The maximum pad voltage is limited to 5 V.

Product data sheet Rev. 1.4 — 8 June 2018 16 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.7 Fast general-purpose p a rallel I/O

The GPIO registers control device pins that are not connected to a specific peripheral

function. Pins may be dynamically configured as inputs or outputs. Multiple outputs can be

set or cleared in one write operation.

LPC8N04 uses accelerated GPIO functions:

•GPIO registers are on the ARM Cortex-M0+ I/O bus for fastest possible single-cycle

I/O timing

•An entire port value can be written in one instruction

•Mask, set, and clear operations are supported for the entire port

All GPIO port pins are fixed-pin functions that are enabled or disabled on the pins by the

switch matrix. Therefore e ach GPIO port pin is assigned to one specific pin and canno t be

moved to another pin.

8.7.1 Features

•Bit level port registers allow a single instruction to set and clear any number of bits in

one write operation

•Direction control of individual bits

•After reset, all I/Os default to GPIO inputs without pull-up or pull-down resistors. The

I2C-bus true open-drain pins PIO0_4 and PIO0_5 and the SWD pins PIO0_10 and

PIO0_11 are exceptions

•Pull-up/pull-down configuration, re peater, and open-drain modes can be pro grammed

through the IOCON block for each GPIO pin

•Direction (input/output) can be set and cleared individually

•Pin direction bits can be toggled

Fig 9. Pin configuration with current so urc e mode

aaa-015353

repeater mode

enable

configured

as output

configured

as input

data input

data output

CDRIVE

IHI[7:0]

ILO[7:0]

CURRENT

SINK

pull-up enable

ESD

Product data sheet Rev. 1.4 — 8 June 2018 17 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.8 I2C-bus controller

8.8.1 Features

Standard I2C-bus compliant interfaces may be configured as master, slave, or

master/slave.

•Arbitration is handled between simultaneously transmitting masters without corruption

of serial data on the bus

•Programmable clock allows adjustment of I2C-bus transfer rates

•Data transfer is bidirectional between masters and slaves

•Serial clock synchronization allows devices with different bit rates to communicate via

one serial bus

•Serial clock synchronization is used as a handsha ke mechanism to suspend and

resume serial transfer

•Supports standard mode (100 kbit/s) and fast mode (400 kbit/s)

•Optional recognition of up to four slave addresses

•Monitor mode allows observing all I2C-bus traffic, regardless of slave address

•The I2C-bus can be used for test and diagnostic purposes

•The I2C-bus contains a standard I2C-bus compliant interface with two pins

•Possibility to wake up LPC8N04 on matching I2C-bus slave address

8.8.2 General description

Two types of data transfers are possible on the I2C-bus, depending on the state of the

direction bit (R/W) :

1. Data transfer from a master transmitter to a slave receiver. The first byte transmitted

by the master is the slave address. Next follows a number of data bytes. The slave

returns an acknowledge bit after each received byte.

2. Data transfer from a slave transmitter to a master receiver. The master transmits the

first byte (the slave address). The slave then returns an acknowledge bit. The slave

then transmits the data bytes to the master. The master returns an acknowledge bit

after all received bytes other than the last byte. At the end of the last received byte, a

not-acknowledge is returned. The master device generates all of the serial clock

pulses and the START and STOP conditions. A transfer is ended with a STOP

condition or with a repeated START condition. As a repeated START condition is also

the beginning of the next serial transfer, the I2C-bus is not released.

The I2C-bus interface is byte orie n te d an d ha s four operating modes: master transmitter

mode, maste r re ceiv er mo de , slav e tran s m itte r mo d e an d sl a ve re ce ive r mo de .

The I2C-bus interface is completely I2C-bus compliant, supporting the ability to power off

the LPC8N04 independent of other devices on the same I2C-bus.

The I2C-bus interface requires a m inimum 2 MHz system clock to operate in normal

mode, and 8 MHz for fast mode.

Product data sheet Rev. 1.4 — 8 June 2018 18 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.8.3 I2C-bus pin description

The I2C-bus pins must be configured through the PIO0_4 and PIO0_5 registers for

standard mode or fast mode. The I2C-bus pins are open-drain outputs and fully

compatible with the I2C-bus specification.

8.9 SPI controller

8.9.1 Features

•Compatible with Motorola SPI, 4-wire Texas Instruments Synchronous Ser ial Interface

(SSI), and National Semiconductor Microwire buses

•Synchronous serial communication

•Supports master or slave operation

•Eight-frame FIFOs for both transmit and receive

•4-bit to 16-bit frame

8.9.2 General description

The SPI/SSP is a Synchronous Serial Port (SSP) controller capable of operation on an

SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the

bus. Only a single maste r and a sin gle slav e can communicate on the bus during a given

data transfer. Data transfers are in principle full duplex, with frames of 4 bits to 16 bits of

bidirectional data flowing between master and slave. In practice, often only one of these

two data flows carries meaningful data.

8.9.3 Pin description

Pin detailed descriptions

Serial clock — SCK/CLK/SK is a clock signal used to synchronize the transfer of data.

The master drives the clock signal and the slave receives it. When SPI/SSP interface is

used, the clock is programmable to be active HIGH or active LOW, otherwise it is always

active HIGH. SCK only switches during a data transfer. At any other time, the SPI/SSP

interface either stays in its inactive state or is not driven (remains in high-impedance

state).

Table 8. I2C-bus pin description

Pin Type Description

SDA I/O I2C-bus seri al data

SCL I/O I2C-bus serial clock

Table 9. SPI pin description

name Type Interface

pin SPI SSI Microwire Description

SCLK I/O SCLK CLK SK serial clock

SSEL I/O SSEL FS CS frame sync/slave select

MISO I/O MISO DR (M)

DX (S) SI (M)

SO (S) master input slave output

MOSI I/O MOSI DX (M)

DR (S) SO (M)

SI (S) master output slave input

Product data sheet Rev. 1.4 — 8 June 2018 19 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

Frame sync/slave select — When the SPI/SSP interface is a bus master, it drives this

signal to an active state before the start of serial data. It then releases it to an inactive

state af ter the da ta has been sen t. The active state can be HIGH or LOW dependin g upon

the selected bus and mode. When the SPI/SSP interface is a bus slave, this signal

qualifies the presence of data from the master according to the protocol in use.

When there is only one master and slave, the master signals, frame sync or slave select,

can be connected directly to the corresponding slave input. When there are multiple

slaves, further qualification of frame sync/slave select inputs is normally necessary to

prevent more than one slave fr om responding to a transfer.

Master Input Slave Output (MISO) — The MISO signal transf er s s eri al da ta from the

slave to the master. When the SPI/SSP is a slave, it outputs serial data on this signal.

When the SPI/SSP is a master, it clocks in serial data from this signal. It does not drive

this signal and leaves it in a high-impedance state when the SPI/SSP is a slave and not

selected by FS/SSEL.

Master Output Slave Input (MOSI) — The MOSI signal transfer s s eri al da ta from the

master to the slave. When the SPI/SSP is a master, it outputs serial data on this signal.

When the SPI/SSP is a slave, it clocks in serial data from this signal.

8.10 RFID/NFC communication unit

8.10.1 Features

•ISO/IEC14443A part 1 to part 3 compatible

•MIFARE (Ultralight) EV1 compatible

•NFC Forum Type 2 compatible

•Easy interfacing with standard user memory space READ/WRITE commands

•Passive operation possible

8.10.2 General description

The RFID/NFC interface allows communication using 13.56 MHz proximity signa ling.

Fig 10. Block diagram of the RFID/NFC interface

aaa-015354

RFID

ANALOG

INTERFACE

EEPROM

SUBSYSTEM

SRAM

APB

INTERFACE

CMDIN

DATAOUT

SR Register

APB SLAVE SUBSYSTEM irq

APB

RFID DIGITAL SUBSYSTEM

VDD_RFID

EEPROM

INTERFACE

RFID

MAIN

CONTROLLER

RFID

ANALOG

SUBSYSTEM

Product data sheet Rev. 1.4 — 8 June 2018 20 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

The CMDIN, DATAOUT, Status Register (SR) and SRAM are mapped in the user

memory space of the RFID core. The RFID READ and WRITE commands allow wireless

communication to this shared memory.

Messages can be in raw mod e (user proprietary pr otocol) or formatted according to NFC

forum type 2 NDEF mess ag in g and ISO/IEC 11073.

8.11 16-bit timer

8.11.1 Features

One 16-bit timer with a progra mmable 16-bit prescaler.

•Timer operation

•Four 16-bit ma tc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match

–Stop timer on match with optional interr upt generation

–Reset timer on match with optional interrupt generation

•Up to two CT16B external outputs cor responding to the match registers with the

following capabilities:

–Set LOW on match

–Set HIGH on match

–Toggle on match

–Do nothing on match

•Up to two match registers can be configured as Pulse Width Modulation (PWM)

allowing the use of up to two mat ch out p uts as single edge controlled PWM outputs

8.11.2 General description

The peripheral clock (PCLK), which is derived from the system clock, clocks the timer.

The timer can optionally generate interru pts or perform other actions at specified timer

values based on four match registers. The peripheral clock is provided by the system

clock.

Each timer also includes one capture input to trap the timer value when an input signal

transitions, optionally generating an interrupt.

In PWM mode, four match reg isters can be used to provide a single-ed ge controlled PWM

output on the match output pins. The use of the match registers that are not pin ned out to

control the PWM cycle length is recommended.

8.12 32-bit timer

8.12.1 Features

One 32-bit timer with a progra mmable 32-bit prescaler.

•Timer operation

•Four 32-bit matc h re gist er s tha t allo w:

–Continuous operation with optional interrupt generation on match

Product data sheet Rev. 1.4 — 8 June 2018 21 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

–Stop timer on match with optional interrupt generation

–Reset timer on match with optional inter rupt generation

•Up to two CT32B external outputs corresponding to the match registers with the

following capabilities:

–Set LOW on match

–Set HIGH on match

–Toggle on match

–Do nothing on match

•Up to two match registers can be configured as PWM allowing the use of up to two

match outputs as single edge controlled PWM outputs

8.12.2 General description

The peripheral clock (PCLK), which is derived from the system clock, clocks the timer.

The timer can optionally generate interru pts or perform other actions at specified timer

values based on four match registers. The peripheral clock is provided by the system

clock.

Each timer also includes one capture input to trap the timer value when an input signal

transitions, optionally generating an interrupt.

In PWM mode, four match reg isters can be used to provide a single-ed ge controlled PWM

output on the ma tc h ou tp ut pins. Use of the match re gisters that are no t pin ned out to

control the PWM cycle length is recommended.

8.13 WatchDog Timer (WDT)

If the microcontroller enters an erroneous state, the purpose of the WatchDog Timer

(WDT) is to reset it within a reasonable amount of time.

When enabled, if the user program fails to feed (or reload) the WDT within a

predetermined amount of time, the WDT generates a system reset.

8.13.1 Features

•If not periodically reloaded, it internally resets the microcontr oller

•Debug mode

•Enabled by software but requires a hardware reset or a WDT reset/interrupt to be

disabled

•If enabled, incorrect/incomplete feed sequence causes reset/interrupt

•Flag to indicate WDT reset

•Programmable 24-bit tim er with internal prescaler

•Selectable time period from (TWDCLK  256  4) to (TWDCLK  224  4) in multiples

of TWDCLK  4

•The WDT clock (WDCLK) source is a 2 MHz clock derived from the SFRO, or the

external clock as set by the SYSCLKCTRL register

Product data sheet Rev. 1.4 — 8 June 2018 22 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.13.2 General description

The WDT consists of a divide by 4 fixed prescaler and a 24-bit co unter. The clock is fed to

the timer via a prescaler. The tim er decrements when clocked. The minimum value by

which the counter is decremented is 0xFF. Setting a value lower than 0xFF causes 0xFF

to be loaded in the counter. Hence the minimum WDT interval is ( TWDCLK  256  4) and

the maximum is (TWDCLK  224  4), in multiples of (TWDCLK  4).

8.14 System tick timer

8.14.1 Features

•Simple 24-bit timer

•Uses dedicated exception vector

•Clocked internally by the system clock or the system clock divided by two

8.14.2 General description

The SYSTICK timer is a part of the Cortex-M0+. The SYSTICK timer can be used to

generate a fixed periodic interrupt for use by an operating system or other system. Since

the SYSTICK timer is a part of the Cortex-M0+, it facilitates porting of software by

providing a standard timer available on Cortex-M0+ based devices. The SYSTICK timer

can be used for management software.

Refer to the Cortex-M0+ Devices - Generic User Guide (Ref. 2) for details.

8.15 Real-Time Clock (RTC) timer

8.15.1 Features

The Real-Time Clock (RTC) block two counters:

1. A countdown timer generating a wake-up signal when it expires

2. A continuous counter that counts seconds since power-up or th e last system reset

The count down timer runs on a low sp eed clock and run s in an always- on power doma in.

The delay, as well as a clock tuning prescaler, can be configured via the APB bus. The

RTC countdown timer generates both the deep power-down wake- up signa l an d the RTC

interrupt signal (wake-up interrupt 12). The deep power-down wake-up signal is always

generated, while the interrupt can be masked according to the settings in the RTCIMSC

8.15.2 General description

The RTC module consists of two parts:

1. The RTC core module, implementing the RTC tim ers themselves. This module runs in

the always-on VDD_ALON domain.

2. The AMBA APB slave inte rface. This module allows configu ration of the RTC core via

an APB bus. This module runs in the switched power domain.

Product data sheet Rev. 1.4 — 8 June 2018 23 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.16 Temperature sensor

8.16.1 Features

The temperature sensor block measures the chip temperature, and outputs a raw value or

a calibrated value in Kelvin.

8.16.2 General description

The temperature is measured using a high-precision, zoom-ADC. The analog part is able

to measure a highly temperature-dependent X = Vbe / Vbe1. It determines the value of X

by first applying a coarse se arch (successive approximation), and then a sigma-delta in a

limited range.

8.17 Serial Wire Debug (SWD)

The debug functions are integr ated into the ARM Cortex-M0+. Serial Wire Debug (SWD)

functions are supported. The ARM Cortex- M0+ is configured to support up to four

breakpoints and two watchpoints.

•Supports ARM SWD mode

•Direct debug access to all memories, registers, and peripherals

•No target resources are required for the debugging session

•Four breakpoints. Four instruction breakpoints that can also be used to remap

instruction addresses for code patches. Two data comparators that can be used to

remap addresses for patches to literal values

•Two data watchpoints that can also be used as triggers

8.18 On-chip flash memory

The LPC8N04 contains a 32 kB flash memory of which 30 kB can be used as program

and data memory.

The flash is organized in 32 sectors of 1 kB. Each sector consists of 16 rows of 16  32-bit

words.

8.18.1 Reading from flash

Reading is done via the AHB inter face. The memor y is mapped on the bus addr ess sp ace

as a contiguous address space. Memory data words are seen on the bus using a little

endian arrangement.

8.18.2 Writing to flash

Writing to flash means copying a word of data over the AHB to the page buffer of the flash.

It does not actually program the data in the memory array. This programming is done by

subsequent erase and pro gram cycles.

1. Vbe is the base-emitter voltage of a bipolar transistor. Basically, the temperature sensor measures the voltage drop over a diode

formed by the base-emitter junction of a bipolar transistor. It compares the Vbe at different current levels (from which follows the

Vbe).

Product data sheet Rev. 1.4 — 8 June 2018 24 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

8.18.3 Erasing/programming flash

Erasing and programming are separate operations. Both are possible only on memory

sectors that are unprotected and unlocked. Protect/lock information is stored inside the

memory itself, so the controller is not aware of protection status. Therefore, if a

program/erase operation is performed on a protected or locked sector, it does not flag an

error.

Protection — At exit from reset, all sectors are pr otected against accident al modificatio n.

To allow modification, a sector must be unprotected. It can then be protected again after

that the modification is performed.

Locking — Each flash sector has a lock bit. Lo ck bits can be set bu t ca nn ot be clear ed .

Locked sectors cannot be erased and reprogrammed.

8.19 On-chip SRAM

The LPC8N04 contains a total of 8 kB on-chip SRAM memory configured as

256 2432 bit.

8.20 On-chip EEPROM

The LPC8N04 contains a 4 kB EEPROM. This EEPROM is organized in 64 rows of

32 16-bit words. Of these rows, the last four contain calibration and test data and are

locked. This data is either used by the bootloa der after reset, or made accessible to the

application via firmware Application Programming Interface (API).

8.20.1 Reading from EEPROM

Reading is done via the AHB interface. The memory is mapped on the bus address

space, as a contiguous address space. Memory data words are seen on the bus using a

little endian arrangement.

8.20.2 Writing to EEPROM

Erasing and programming is performed, as a single operation, on one or more words

inside a single page.

Previous write operations have transferre d the data to be programmed into the memory

page buffer. The page buffer tracks which words were written to (offset within the page

only). Words not written to, retain their previous content.

Product data sheet Rev. 1.4 — 8 June 2018 25 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

9. Limiting values

Table 10. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol Parameter Conditions Min Max Unit

VDD supply voltage 0.5 +3.6 V

VIinput voltage normal PIO pads (VDD = 0.6 V) 0.5 +3.6 V

high-source PIO pads 0.5 +5.5 V

LA/LB pads 0.5 +5.5 V

IDD supply current per supply pin - 100 mA

ISS ground supply current per supply pin - 100 mA

Ilu latch-up current I/O; 0.5VDD < VI < +1.5VDD;

Tj< 125 C- 100 mA

Tstg storage temperature 40 +125 C

Tjjunction temperature - 125 C

Ptot total power dissipation - 1 W

VESD electrostatic discharge voltage human body model; all pins 2000 +2000 V

charged device mo del; all pins 500 +500 V

LPC8N04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.4 — 8 June 2018  26 of 39
NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
10. Static characteristics
 
[1] See Figure 11.
[2] PIO0_0, PIO0_1, PIO0_2, PIO0_6, PIO0_8, PIO0_9.
[3] PIO0_3, PIO0_7, PIO0_10, PIO0_11.
[4] PIO0_4, PIO0_5.
Table 11. Static characteristics
Tamb = 

40 

C to +85 

C, unless otherwise stated.
Symbol Parameter Conditions Min Typ Max Unit
Supply pins
VDD supply voltage 1.72 3.0 3.60 V
IDD supply current voltage and clock frequency 
dependent [1] ---A
IL(off) off-state leakage current - - 50 nA
IDD(pd) power-down mode supply current  deep power-down mode - 3 - A
Standard GPIO pins
VIH HIGH-level input voltage 0.7 
VDD
-- V
VIL LOW-level input voltage - - 0.3 
VDD
V
Vhys hysteresi s vol tage 0.4 - - V
Rpd pull-down resistance - 72 - k
Rpu pull-up resistance - 73 - k
ISsource current HIGH-level VDD = 1.8 V [2] -2-mA
HIGH-level VDD = 3.6 V [2] -8-mA
LOW-level VDD = 1.8 V [2] -4-mA
LOW-level VDD = 3.6 V [2] -16-mA
High-drive GPIO pins
ISsource current HIGH-level VDD = 1.8 V [3] 4-6mA
HIGH-level VDD = 3.6 V [3] 13 - 18 mA
LOW-level VDD = 1.8 V [3] 5.5 - 8 mA
LOW-level VDD = 3.6 V [3] 22 - 32 mA
I2C-bus pins
ISsource current LOW-level VDD = 1.8 V [4] 2-8.5mA
LOW-level VDD = 3.6 V [4] 9.5 - 38 mA
Brownout detect
Vtrip(bo) brownout trip voltage falling VDD -1.8-V
rising VDD -1.875-V
Vhys hysteresi s vol tage - 75 - mV
General
Rpu(int) internal pull-up re sistance on pin RESETN - 100 - k
Cext external capacitance on pin RESETN - - 1 nF

Product data sheet Rev. 1.4 — 8 June 2018 27 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

Note: The absolute accura cy is valid for th e fa ct ory calib ra tion of the te mpe rature sensor.

The sensor can be user-calibrated to reach higher accuracy.

[1] Tamb = 22 C, f = 13.56 MHz, RMS voltage between LA and LB = 1.5 V.

Plot of IDD / VDD when ARM running a while-1 loop in normal mode, no NFC field present.

(1) System clock = 250 kHz

(2) System clock = 500 kHz

(3) System clock = 1 MHz

(4) System clock = 2 MHz

(5) System clock = 4 MHz

(6) System clock = 8 MHz

Fig 11. Active cur re n t consumption

VDD (V)

1.5 43.52.5 32

aaa-022790

400

600

200

800

1000

IDD

(μA)

(3)

(2)

(1)

(4)

(5)

(6)

Table 12 . Temperature senso r characteristics

Symbol Parameter Conditions Min Typ Max Unit

ICC(pd) power-down mo de supply current TSENS disabled - - 1 nA

Istb standby current TSENS enabled - 6 7 A

ICC(oper) operating supply current TSENS converting - 10 12 A

Tacc temperature acc ura cy 1.5 - +1.5 C

Table 13 . Antenna input characteristics

Symbol Parameter Conditions Min Typ Max Unit

Ciinput capacitance [1] -50-pF

fiinput frequency - 13.56 - MHz

Table 14. EEPROM characteristics

Symbol Parameter Conditions Min Typ Max Unit

tret(data) data retention time Tamb = 22 C 10--year

LPC8N04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.4 — 8 June 2018  28 of 39
NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
11. Dynamic characteristics
11.1 I/O pins
 
11.2 I2C-bus
 
[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] A device must internally provide a hold time of at least 300 ns for the SDA signal (regarding the VIH(min) of the SCL signal). The hold time 
is to bridge the undefined region of the falling edge of SCL.
[3] Cb = total capacitance of one bus line in pF.
[4] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage tf is specified at 
250 ns. It allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without 
exceeding the maximum specified tf.
[5] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[6] The maximum tHD;DAT could be 3.45 s and 0.9 s for standard mode and fast mode. However, it must be less than the maximum of 
tVD;DAT or tVD;ACK by a transition time (see Ref. 3). Only meet this maximum if the device does not stretch the LOW period (tLOW) of the 
SCL signal. If the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[7] tSU;DAT is the data set-up time that is measured against the rising edge of SCL; applies to data in transmission and the acknowledge.
[8] A fast mode I2C-bus device can be used in a standard-mode I2C-bus system but it must meet the requirement tSU;DAT = 250 ns. This 
requirement is automatically the case if the device does not stretch the LOW period of the SCL signal. If it does, it must output the next 
data bit to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is released. This procedure is in accordance with the 
standard-mode I2C-bus specification. Also, the acknowledge timing must meet this set-up time.
Table 15 . I/O dynamic ch aracteristics
These characteristics apply to standard port pins and RESETN pin.
Tamb = 

40 

C to +85 

C.
Symbol Parameter Conditions Min Typ Max Unit
trrise time  pin configured as output 3.0 - 5.0 ns
tffall time  pin configured as output 2.5 - 5.0 ns
Table 16. I 2C-bus dynamic characteristics
See UM10204 - I2C-bus specification and user manual (Ref. 3) for details.
Tamb = 

40 

C to +85 

C[1]; see the timing diagram in  Figure 12.
Symbol Parameter Conditions Min Typ Max Unit
fSCL SCL clock frequency standard mode 0 - 100 kHz
fast mode 0 - 400 kHz
tffall time of both SDA and SCL 
signals standard mode [2][3][4] --300ns
fast mode [2][3][4] 20 + 0.1  Cb-300ns
tLOW LOW period of the SCL clock standard mode 4.7 - - s
fast mode 1.3 - - s
tHIGH HIGH period of the SCL clock standard mode 4.0 - - s
fast mode 0.6 - - s
tHD;DAT data hold time  standard mode [2][5][6] 0--s
fast mode [2][5][6] 0--s
tSU;DAT data set-up time  standard mode [7][8] 250 --ns
fast mode [7][8] 100 --ns

LPC8N04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.4 — 8 June 2018  29 of 39
NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
 
11.3 SP I interfaces
 
[1] tcy(clk) = (SSPCLKDIV  (1 + SCR)  CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate tcy(clk) is a function of:
a) the main clock frequency fmain 
b) the SPI peripheral clock divider (SSPCLKDIV)
c) the SPI SCR parameter (specified in the SSP0CR0 register)
d) the SPI CPSDVSR parameter (specified in the SPI clock prescale register)
[2] Tamb = 40 C to +105C.
[3] tcy(clk) = 12  Tcy(PCLK).
[4] Tamb = 25 C for normal voltage supply: VDD = 3.3 V.
S = START condition
Fig 12. I2C-bus pins clock timing
002aaf425
tf
70 %
30 %
SDA
tf
70 %
30 %
S
70 %
30 %
70 %
30 %
tHD;DAT
SCL
1 / fSCL
70 %
30 %
70 %
30 %
tVD;DAT
tHIGH
tLOW
tSU;DAT
Table 17. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Unit
SPI master
tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns
when only  tran smi tting [1] 40 - - ns
tSU;DAT data set-up time 2.4 V  VDD < 3.6 V [2] 15 - - ns
2.0 V  VDD < 2.4 V [2] 20 - - ns
1.8 V  VDD < 2.0 V [2] 24 - - ns
tHD;DAT data hold  time [2] 0-- ns
tv(Q) data out pu t val i d  time [2] - - 10 ns
th(Q) data output hold time [2] 0-- ns
SPI slave
Tcy(PCLK) PCLK cycle time [3][4] 0-- ns
tHD;DAT data hold  time [3][4] 3  Tcy(PCLK) + 4 - - n s
tv(Q) data out pu t val i d  time [3][4] --3  Tcy(PCLK) + 11 ns
th(Q) data output hold time [3][4] --2  Tcy(PCLK) + 5 ns

Product data sheet Rev. 1.4 — 8 June 2018 30 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

Fig 13. SPI master timing in SPI mode

Fig 14. SPI slave timing in SPI mode

SCK (CPOL = 0)

MOSI

MISO

tcy(clk)

tSU;DAT tHD;DAT

tv(Q)

DATA VALID DATA VALID

th(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

tSU;DAT tHD;DAT

DATA VALID DATA VALID

th(Q)

DATA VALID DATA VALID

tv(Q)

CPHA = 1

CPHA = 0

aaa-024226

SCK (CPOL = 0)

MOSI

MISO

cy(clk)

v(Q)

DATA VALID DATA VALID

h(Q)

SCK (CPOL = 1)

DATA VALID DATA VALID

MOSI

MISO

v(Q)

DATA VALID DATA VALID

h(Q)

DATA VALID DATA VALID

CPHA = 1

CPHA = 0

SU;DAT

HD;DAT

SU;DAT

HD;DAT

aaa-024227

Product data sheet Rev. 1.4 — 8 June 2018 31 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

12. Package outline

Fig 15. HVQFN24 package outline

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT616-3 MO-220

sot616-3_po

16-02-17

16-07-14

Unit(1)

max

nom

min

1 0.05 4.1 2.75 4.1

0.5 2.5

A(1)

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 4 x 4 x 0.85 mm SOT616-3

A1b

0.30

(1) DhE(1) Ehee

1e2

2.5

0.1

0.2 0.10.05 0.05

0.32.45

0.00 3.9 2.45 3.90.18

0.52.75

0 2.5 5 mm

scale

AA1

detail X

y1C

712

24 19

terminal 1

index area

terminal 1

index area

1/2 e

Product data sheet Rev. 1.4 — 8 June 2018 32 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

13. Abbreviations

Table 18. Abbreviations

Acronym Description

ADC Analog-to-Digital Converter

AHB Advanced High-performance Bus

AMBA Advanced Microcontroller Bus Architecture

APB Advanced Peripheral Bus

API Application Programming Interface

ARM Advanced RISC Machine

BOD BrownOut Detection

CGU Clock Generator Unit

EEPROM Electrically Erasable Programmable Read-Only Memory

GPIO General Purpose Input Output

I2C Inter-Integrated Circuit

LDO Low DropOut

MISO Master Input Slave Output

MOSI Master Output Slave Input

NDEF NFC Data Exchange Format

NFC Near Field Communication

NVIC Nested Vectored Inte rrupt Controller

PMU Power Management Unit

POR Power-On Reset

PWM Pulse Width Modulation

RFID Radio Frequency Identification

RISC Reduced Instruction Set Compute r

RTC Real-Time Clock

SFRO System Free-Running Oscillator

SI Slave Input

SO Slave Output

SPI Serial Peripheral Interface

SR Status Register

SSI Synchronous Serial Interface

SSP Synchronous Serial Port

SWD Serial Wire Debug

TFRO Timer Free-Running Oscillator

WDT WatchDog Timer

Product data sheet Rev. 1.4 — 8 June 2018 33 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

14. References

[1] DDI0484C_cortex_m0p_r0p1_trm — Cortex-M0+ Devices - Technical Refe rence

Manual

[2] DUI0662B_cortex_m0p_r0p1 _dgug — Cortex-M0+ Devices - Generic User Guide

[3] UM10204 — I2C-bus specification and user manual

Product data sheet Rev. 1.4 — 8 June 2018 34 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

15. Revision history

Table 19. Revision history

Document ID Release date Data sheet status Ch ange notice Supersedes

LPC8N04 v.1.4 20180608 Product data sheet - LPC8N04 v.1.3

Modification: •Updated Section 2 “Features and benefits”: Added text: OTA firmware update usi ng

Secondary Bootloader (SBL) li brary (See TN00040: LPC8N04: Encrypted Over the Air

(OTA) Firmware update using NFC). OTA firmware update available on Boot ROM version

0.14.

•Updated Section 5 “Marking”.

LPC8N04 v.1.3 20180301 Product data sheet - LPC8N04 v.1.2

Modification: •Changed title to Cortex-M0+.

LPC8N04 v.1.2 20180301 Product data sheet - LPC8N04 v.1.1

Modification: •Added a remark to Section 8.4.1 “System power architecture ”: When running without a

battery, energy harvesting is limited to 2 MHz system clock.

LPC8N04 v.1.1 20171211 Product data sheet - LPC8N04 v.1.0

Modification: •Added text to Section 2 “Features and benefits”: Energy harvesting functionality to power

the LPC8N04.

LPC8N04 v.1.0 20171012 Product data sheet - -

Product data sheet Rev. 1.4 — 8 June 2018 35 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warrant ies as to t he accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not b e relied u pon to cont ain det ailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semicond uctors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre va il.

Product specificat io n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

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Limited warr a nty and liability — Information in this document is believed to

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representations or warrant ies, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an information

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In no event shall NXP Semiconductors be liable for any indirect, incidental,

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Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

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with the Terms and conditions of commercial sale of NXP Semicondu ctors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

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notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

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authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipme nt, nor in applications where failure or

malfunction of an NXP Semiconductors product can reasonably be expect ed

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconductors products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for il lustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Custo mers should provide appropriate

design and operating safeguards to minimize the risks associate d with t heir

applications and products.

NXP Semiconductors does not accept any liabil i ty related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the appl ication or use by customer’s

third party custo mer(s). Customer is responsible for doing all necessar y

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter m s and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or the gr ant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objective specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.

Product [short] data sheet Production This document contains the product specifica tion.

Product data sheet Rev. 1.4 — 8 June 2018 36 of 39

NXP Semiconductors LPC8N04

32-bit ARM Cortex-M0+ microcontroller

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors prod uct is automotive qualified,

the product is not suitable for automotive use. It is neither qua lified nor test ed

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standards, custome r

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such au tomotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive appl ications beyond NXP Semiconductors’

standard warrant y and NXP Semiconductors’ product specifications.

Translations — A non-English (translated ) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Licenses

16.5 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respective ow ners.

MIFARE — is a trademark of NXP B.V.

I2C-bus — logo is a trademark of NXP B.V.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Purchase of NXP ICs with NFC technology

Purchase of an NXP Semiconductors IC that co mplies with one of the Near

Field Communication (NFC) standards ISO/IEC 18092 and IS O/IEC 21481

does not convey an implied license under any patent right infringed by

implementation of any of those standards. Purchase of NXP

Semiconductors IC does not include a license to any NXP patent (or other

IP right) covering combinations of those products with other produ cts,

whether hardware or software.

LPC8N04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.4 — 8 June 2018  37 of 39
NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
18. Tables
Table 1.  Ordering information  . . . . . . . . . . . . . . . . . . . . .3
Table 2.  Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .3
Table 3.  Pad alloca tion table of th e HVQFN24 package .5
Table 4.  Pad description of the HVQFN24 package. . . . .6
Table 5.  IC power states. . . . . . . . . . . . . . . . . . . . . . . . .12
Table 6.  State transition events for DEEPSLEEP to 
ACTIVE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 7.  State transition events for DEEPPDN to ACTIVE
 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 8.  Connectio n of interrupt source to the NVIC . . .14
Table 9.  I2C-bus pin description . . . . . . . . . . . . . . . . . . .18
Table 10.  SPI pin description . . . . . . . . . . . . . . . . . . . . . .18
Table 11.  Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .25
Table 12.  Static characteristics. . . . . . . . . . . . . . . . . . . . .26
Table 13.  Temperature sensor characteristics . . . . . . . . .27
Table 14.  Antenna input characteristics . . . . . . . . . . . . . .27
Table 15.  EEPROM characteristics . . . . . . . . . . . . . . . . .27
Table 16.  I/O dynamic characteristics  . . . . . . . . . . . . . . .28
Table 17.  I2C-bus dynamic characteristics  . . . . . . . . . . .28
Table 18.  Dynamic characteristics of SPI pins in SPI mode
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 19.  Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 20.  Revision history . . . . . . . . . . . . . . . . . . . . . . . .33

LPC8N04 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
Product data sheet Rev. 1.4 — 8 June 2018  38 of 39
NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
19. Figures
Fig 1.  LPC8N04 block diagram . . . . . . . . . . . . . . . . . . . .4
Fig 2.  Pad configuration HVQFN24. . . . . . . . . . . . . . . . .5
Fig 3.  LPC8N04 memory map. . . . . . . . . . . . . . . . . . . . .8
Fig 4.  LPC8N04 clock generator block diagram  . . . . . . .9
Fig 5.  LPC8N04 power architecture. . . . . . . . . . . . . . . .11
Fig 6.  PMU state transition diagram. . . . . . . . . . . . . . . .12
Fig 7.  LPC8N04 power-up sequence. . . . . . . . . . . . . . .13
Fig 8.  Pin configuration with current source mode. . . . .16
Fig 9.  Block diagram of the RFID/NFC interface . . . . . .19
Fig 10.  Active current consumption . . . . . . . . . . . . . . . . .27
Fig 11.  I2C-bus pins clock timing . . . . . . . . . . . . . . . . . . .29
Fig 12.  SPI master timing in SPI mode . . . . . . . . . . . . . .30
Fig 13.  SPI slave timing in SPI mode  . . . . . . . . . . . . . . .30
Fig 14.  HVQFN24 package outline . . . . . . . . . . . . . . . . .31

NXP Semiconductors LPC8N04
32-bit ARM Cortex-M0+ microcontroller
© NXP Semiconductors N.V. 2018. All rights reserv ed.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 June 2018
Document identifie r: LPC8N04
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’. 
Contents
General description. . . . . . . . . . . . . . . . . . . . . .  1
Features and benefits . . . . . . . . . . . . . . . . . . . .  2
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Ordering information. . . . . . . . . . . . . . . . . . . . .  3
Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . .  4
Pinning information. . . . . . . . . . . . . . . . . . . . . .  5
1  Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  5
1.1  HVQFN24 package. . . . . . . . . . . . . . . . . . . . . .  5
Functional description . . . . . . . . . . . . . . . . . . .  7
1  ARM Cortex-M0+ core . . . . . . . . . . . . . . . . . . .  7
2  Memory map. . . . . . . . . . . . . . . . . . . . . . . . . . .  7
3  System configuration . . . . . . . . . . . . . . . . . . . .  8
3.1  Clock generation. . . . . . . . . . . . . . . . . . . . . . . .  8
3.2  Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  9
4  Power management . . . . . . . . . . . . . . . . . . . .  10
4.1  System power architecture. . . . . . . . . . . . . . .  10
4.1.1  Applying power to the PCB/system with battery for 
the first time . . . . . . . . . . . . . . . . . . . . . . . . . .  13
4.2  Power Management Unit (PMU) .  . . . . . . . . . .  13
5  Nested V ectored Interrupt Controller (NVIC) .  14
5.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  14
5.2  Interrupt sources. . . . . . . . . . . . . . . . . . . . . . .  14
6  I/O configuration. . . . . . . . . . . . . . . . . . . . . . .  15
6.1  PIO0 pin mode . . . . . . . . . . . . . . . . . . . . . . . .  15
6.2 PIO0 I2C-bus mode  . . . . . . . . . . . . . . . . . . . .  15
6.3  PIO0 current source mode . . . . . . . . . . . . . . .  15
7  Fast general-purpose parallel I/O. . . . . . . . . .  16
7.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  16
8 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . .  17
8.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  17
8.2  General description  . . . . . . . . . . . . . . . . . . . .  17
8.3 I2C-bus pin description . . . . . . . . . . . . . . . . . .  18
9  SPI controller . . . . . . . . . . . . . . . . . . . . . . . . .  18
9.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  18
9.2  General description  . . . . . . . . . . . . . . . . . . . .  18
9.3  Pin description . . . . . . . . . . . . . . . . . . . . . . . .  18
Pin detailed descriptions . . . . . . . . . . . . . . . . . .18
10  RFID/NFC communication unit. . . . . . . . . . . .  19
10.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  19
10.2  General description  . . . . . . . . . . . . . . . . . . . .  19
11  16-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
11.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
11.2  General description  . . . . . . . . . . . . . . . . . . . .  20
12  32-bit timer . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
12.1  Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  20
12.2  General description  . . . . . . . . . . . . . . . . . . . .  21
13  WatchDog Timer (WDT).  . . . . . . . . . . . . . . . .   21
13.1  Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .   21
13.2  General description . . . . . . . . . . . . . . . . . . . .   22
14  System tick timer . . . . . . . . . . . . . . . . . . . . . .   22
14.1  Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .   22
14.2  General description . . . . . . . . . . . . . . . . . . . .   22
15  Real-Time Clock (RTC) timer. . . . . . . . . . . . .   22
15.1  Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .   22
15.2  General description . . . . . . . . . . . . . . . . . . . .   22
16  Temperature sensor. . . . . . . . . . . . . . . . . . . .   23
16.1  Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . .   23
16.2  General description . . . . . . . . . . . . . . . . . . . .   23
17  Serial Wire Debug (SWD) . . . . . . . . . . . . . . .   23
18  On-chip flas h me mory . . . . . . . . . . . . . . . . . .   23
18.1  Reading from flash. . . . . . . . . . . . . . . . . . . . .   23
18.2  Writing to flash . . . . . . . . . . . . . . . . . . . . . . . .   23
18.3  Erasing/programming flash . . . . . . . . . . . . . .   24
19  On-chip SRAM. . . . . . . . . . . . . . . . . . . . . . . .   24
20  On-chip EEPROM . . . . . . . . . . . . . . . . . . . . .   24
20.1  Reading from EEPROM. . . . . . . . . . . . . . . . .   24
20.2  Writing to EEPROM . . . . . . . . . . . . . . . . . . . .   24
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .   25
Static characteristics  . . . . . . . . . . . . . . . . . . .   26
Dynamic characteristics. . . . . . . . . . . . . . . . .   28
1  I/O pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   28
2 I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   28
3  SPI interfaces. . . . . . . . . . . . . . . . . . . . . . . . .   29
Package outline. . . . . . . . . . . . . . . . . . . . . . . .   31
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .   32
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .   33
Revision history . . . . . . . . . . . . . . . . . . . . . . .   34
Legal information . . . . . . . . . . . . . . . . . . . . . .   35
1  Data sheet status. . . . . . . . . . . . . . . . . . . . . .   35
2  Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .   35
3  Disclaimers  . . . . . . . . . . . . . . . . . . . . . . . . . .   35
4  Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . .   36
5  Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .   36
Contact information . . . . . . . . . . . . . . . . . . . .   36
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   37
Figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   38
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   39