(R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter PRODUCT OVERVIEW The ADC-674 A/D converters are single chip monolithic CMOS versions of the industry standard devices. These units include a reference, clock, threestate outputs, and digital interface circuit which allows direct connection to the microprocessor PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 FEATURES Complete 12-Bit A/D converters with reference and clock Pin-to-pin compatible with industry standard HI574A/674A No missing codes over temperature 8 Sec. Conversion time 150 mW maximum power dissipation address bus and control lines. The ADC-674 completes a 12-bit conversion in 8 microseconds. Four user selectable input ranges are provided: 0 to +10V, 0 to +20V, +/-5V, and +/-10V dc. Laser trimming ensures specified linearity, gain and offset accuracy. INPUT/OUTPUT CONNECTIONS FUNCTION PIN FUNCTION Vlogic, +5V 15 DGND 12/8, DATA MODE SELECT 11 DB0 (LSB) 17 DB1 CS, CHIP SELECT 18 DB2 A0, BYTE ADDRESS/SHORT CYCLE 19 DB3 R/C, READ/CONVERT CE, CHIP ENABLE 20 DB4 Vcc 21 DB5 REFERENCE OUT 22 DB6 AGND 23 DB7 REFERENCE IN 23 DB8 Vee 25 DB9 BIPOLAR OFFSET 26 DB10 10V IN 27 DB11 (MSB) 20V IN 28 STS BLOCK DIAGRAM VCC VEE AGND 7 11 9 COMP 28 STS BIPOLAR 12 OFFSET 27 DB11 (MSB) 26 DB10 10V IN 13 25 DB9 24 DB8 CAPACITANCE DAC 20V IN 14 THREE STATE BUFFERS S.A.R 23 DB7 22 DB6 21 DB5 20 DB4 19 DB3 18 DB2 17 DB1 16 DB0 (LSB) V logic 1 D GND 15 10V REF 10 8 REF IN REF OUT OSCILLATOR CONTROL LOGIC 2 3 4 5 6 12/8 CS A0 R/C CE Figure 1. ADC-674 Functional Block Diagram 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 1 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter ABSOLUTE MAXIMUM RATINGS Vcc TO GND Vee TO GND Logic Supply Voltage (Pin 1) Analog Common (Pin 9) to Digital Common (Pin 15) Digital Control Inputs (Pins 2-6) to Digital Common Analog Inputs (Pins 10,12,13) to Analog Common 20V Input (Pin 14) to Analog Common Ref. Out (Pin 8) Short Circuit Duration Chip Temperature Package Dissipation Lead Temperature, soldering Thermal Resistance, Junction-to-Ambient 0 to +16.5V 0 to -16.5V OV to +7V 0.5V to + 1V -0.5V to Vlogic +0.5V 16.5V 24V Indefinite to common momentary to Vs -55C to 125C 1000 mW 300C, 10 Sec. 48C/W FUNCTIONAL SPECIFICATIONS Typical at 25C, 15V, and +5V dc supply ranges, unless otherwise noted. ANALOG INPUTS Input Voltage Range Input Impedance ANALOG OUTPUTS Internal Reference DIGITAL INPUTS Logic Levels: Loading: unipolar 5V, 10V 10V range 5K 25% 20V range 10K 25% voltage +10.00V 0.1 max. current 2.0 mA max. logic "1" +2.0 min. to +5.5V max. logic "0" -0.5V min. to +0.8V max. logic current 1 A max. +5 A Capacitance DIGITAL OUTPUTS Logic Levels: 0 to +10V, O to +20V bipolar 5pF logic "0" (I sink, 1.6 mA) logic "1" (I source, 500 A) Leakage (high impedance state) +0.4V max. +2.4V min. -5 A min. to +5 A max. Capacitance 5pF POWER REQUIREMENTS Analog Supply Voltage Range 11.4V to 16.5V Logic Supply Voltage Range Supply-Current max. Power Consumption +4.5V to +5.5V Analog Supply +7mA Logic Supply +6mA (+VS = +15V), max. 250 mW PHYSICAL/ENVIRONMENTAL Operating Temperature Range 55C to +125C Storage Temperature Range -65C to +150C Package Type 28 pin LCC ceramic PERFORMANCE (TYPICAL) Resolution 12 Bits Unipolar Offset, max. Conversion Time, max. 0.5% of FSR 8 Sec Full Scale Calibration Error at 25C max 0.6% of FSR over temp. over temp. 10 ppm/C Linearity Error, max. 0.75 LSB 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 2 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter PERFORMANCE (TYPICAL, CONT.) Differential Linearity Error 0.5LSB Bipolar Offset, max. Tempco: 0.1% of FSR Unipolar Offset max. 20 ppm/C Bipolar Offset max. 20 ppm/C Full Scale Calibration max. Power Supply Rejection: 25 ppm/C +Vs = 13.5V to 16.5V or +11.4V to +12.6V max. Vlogic = +4.5V to +5.5V max 0.001%FSR/%V Footnotes: Available for external loads. External load should not change during conversion. When supplying an external load using a +12V supply, a buffer amplifier must be provided for the reference output. Logic Inputs - CE, CS, R/C, A0, 12/8. Logic Outputs - DB11-DBO, STS. Over temperature. TECHNICAL NOTES 1. The ADC-674 may interface directly to a microprocessor which can take full control of each conversion, or the device can be operated in the "stand alone" mode (controlled only by the R/C input). Full control consists of selecting an 8- or 12-bit conversion cycle, initiating the conversion and reading the output data when ready. The data may be read 12 bits at once or 8 followed by 4 in a left-justified format. There are five control inputs (12/8, CS, A0, R/C: and CE) and all are TTL/CMOS compatible. (See Control Input Truth Table.) 2. A conversion is initiated by a logic transition on any of the three inputs: CE, CS, R/C. One, two, or all three may be dynamically controlled. The nominal delay for each of the three inputs is the same and if necessary, all three may change states simultaneously. If it is required that a particular input controls the start of conversion, the other two should be set up at least 50 nanoseconds earlier. (See Start Convert Timing, Figure 3). 3. To read the output data, four conditions must be met (or the output buffers will remain in high impedance state): R/C taken high, STS low, CE high and CS low. When this is accomplished, the data lines are activated according to the state of the 12/8 and A0 inputs. (See TIMING DIAGRAM on Figure 4). 4. The analog signal source driving the ADC-674's input will see a nominal load of 5 K (10V range) or 20 K (20V range). However, the other end of Adjustable to zero. With 50 fixed resistor from REF OUT to REF IN. Adjustable to zero. No adjustment at 25*C. Guaranteed maximum change, Tmin to Tmax (using internal reference). Maximum change in full scale calibration. these input resistors may change 400 mV with each bit decision, causing sudden changes in current at the analog input. Therefore, the signal source must maintain its output voltage while supplying these step changes in load current which occur at 1.6 microsecond intervals. This requires low output impedance and fast settling by the signal source. 5. The power supply used should be low noise and well regulated. Voltage spikes can affect accuracy. If a switching supply is used, the outputs should be carefully filtered to assure "noise free" dc voltage to the converter. Decoupling capacitors should be used on all power supply pins; the +5V dc supply decoupling capacitor should be connected directly from +Vlogic (Pin 1) to digital common (Pin 15). Vcc (Pin 7) should be decoupled directly to AGND (Pin 9). It is recommended that a 10 F tantalum type in parallel with a 0.1 F ceramic type be used for decoupling. 6. The use of good circuit board layout techniques is required for rated performance. It is recommended that a double sided printed circuit board with a ground plane on the component side be used. Other techniques, such as wirewrapping or point-to-point wiring on vectorboard will have an unpredictable effect on accuracy. Sensitive analog signals should be routed between ground traces and kept away from digital lines. If analog and digital lines must cross, they should do so at right angles. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 3 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter TYPICAL CONNECTIONS UNIPOLAR CONFIGURATION BIPOLAR CONFIGURATION Vcc NC Vlog STATUS Vcc NC Vlog STATUS 7 11 1 28 7 11 1 28 2 12/8 27 DB11 (MSB) 2 12/8 27 DB11 (MSB) 3 CS 26 DB10 3 CS 26 DB10 25 DB9 4 5 R/C 24 DB8 5 R/C 6 CE 23 DB7 6 CE 4 A0 ADC-674 A0 25 DB9 24 DB8 23 DB7 ADC-674 22 DB6 22 DB6 R2 R2 10 REF IN 21 DB5 8 REF OUT 20 DB4 12 BIP OFF 19 DB3 10 REF IN 21 DB5 8 REF OUT 20 DB4 100 100 100 +15V 12 BIP OFF 19 DB3 13 10V IN 18 DB2 13 10V IN 18 DB2 14 20V IN 17 DB1 14 20V IN 17 DB1 16 DB0 (LSB) 9 AGND R1 100 100k R1 9 AGND 100k 16 DB0 (LSB) DGND DGND 15 15 -15V NOTES: The trimpots shown are for calibration of offset and gain. If adjustment is not required in unipolar, replace R2 with a 50, 1% metal film resistor, omit the network on Pin 12 and connect Pin 12 to Pin 9. In bipolar, either R1 or R2 or both can be replaced by 50, 1% metal film resistors. CODING TABLES INPUT RANGE OUTPUT CODING 0 to + 10V O to +20V MSB +10.000 +20.0000 1111 +9.9963 +19.9927 1111 +5.0012 +10.0024 1000 +4.9988 +9.9976 OOOO +4.9963 +9.9927 0111 +0.0012 +0.0024 0000 0.0000 +0.0000 0000 INPUT RANGE OUTPUT CODING LSB 5V 10V LSB 1111 1111 +5.0000 +10.0000 1111 1111 1111 1111 111O* +4.9963 +9.9927 1111 1111 111O* 0000 000O* +0.0012 +0.0024 1000 0000 000O* 0000 OOOO* -0.0012 -0.0024 OOOO 0000 OOOO* 1111 111O* -0.0037 -0.0073 0111 1111 111O* 0000 O00O* -4.9988 -9.9976 0000 0000 O00O* 0000 0000 -5.0000 -10.0000 0000 0000 0000 * Voltages shown are theoretical values for the transitions indicated. Ideally, In the continuous conversion mode, the output bits indicated as O will change from "1" to "0" or "0" to "1" as the input voltage passes through the level indicated. Output coding is straight binary for unipolar and offset binary for bipolar. CALIBRATION UNIPOLAR CALIBRATION Offset Adjust BIPOLAR CALIBRATION Offset Adjust Apply an input of +1/2 LSB (+1.22 mV for the 10V range; +2.44 mV for the 20V range). Adjust the offset trimpot (R1) until the first code transition flickers between 0000 0000 0000 and 0000 0000 0001. Apply 1/2 LSB above negative full-scale (-4.9988V for the 5V range; -9.9976V for the 10V range.) Adjust the offset trimpot (R1) so that the output flickers between 0000 0000 0000 and 0000 0000 0001. Gain Adjust Gain Adjust Apply 11/2 LSB's below the nominal full-scale (+9.9963V for the 10V range; +19.9927V for the 20V range). Adjust the gain-trimpot (R2) so that the output flickers between 1111 1111 1110 and 1111 1111 1111. Apply 11/2 LSB's below positive full scale (+4.9963V for the 5V range; +9.9927V for the 10V range). Adjust the gain trimpot (R2) so that the output flickers between 1111 1111 1110 and 1111 1111 1111. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 4 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter TIMING CONTROL The variety of the ADC-674's control modes (as shown in the "CONTROL INPUTS TRUTH TABLE") allow for simple interface in most system applications. The output signal STS indicates the status of the device; high during a conversion, and low at the completion of a conversion. During a conversion (STS output high), the output buffers remain in the high impedance state and data cannot be read. A start convert during conversion will not reset the converter or reinitiate a conversion. However, if A0 changes state after a conversion begins, an additional start convert pulse will latch the new state of A0, causing a wrong cycle length for that conversion. Control Inputs Truth Table CE 0 X 0-1 0-1 1 1 1 1 1 1 1 CS x 1 0 0 1-0 1-0 0 0 0 0 0 R/C X X 0 0 0 0 1-0 1-0 1 1 1 12/8 X X X X X X X X 1 0 0 A0 X X 0 1 0 1 0 1 X 0 1 OPERATION None None Initiate 12-bit conversion Initiate a-bit conversion Initiate 12-bit conversion Initiate a-bit conversion Initiate 12-bit conversion Initiate a-bit conversion Enable 12-bit Output Enables 8 MSB's only Enables 4 LSB's plus 4 trailing zeroes TIMING AND OPERATION Stand-Alone Mode Timing For stand-alone operation, all that is required is a single control line to R/C, CE and 12/8 are tied high, CS and A0 are tied low, and the output appears in words of 12 bits The R/C signal may have any duty cycle within the limits shown in the diagrams below The data may be read when R/C is high unless STS is also high indicating a conversion is in progress. 50 ns MIN R/C 13 ns MIN 200 ns MAX 25 ns MAX STS 25 ns MIN DB11-DB0 30 ns MIN 1000 ns MAX DATA VALID DATA VALID Figure 1. Outputs Enabled After Conversion CE CS tHEC tSSC tSRC tHSC R/C tHRC A0 tSAC STS R/C 150 ns MIN 200 ns MAX DB11-DB0 HIGH-Z tC HIGH IMPEDANCE Figure 3. Start Convert Timing 25 ns MIN DATA VALID tDSC DB11-DB0 STS 150 ns MAX tHAC HIGH-Z A read operation in most applications begins after the conversion is complete and STS is low. For earliest access to the data, however, the read should begin no later than (tDD + tHS) before STS goes low. (See Technical Note 3.) Figure 2. Outputs Enabled With R/C High 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 5 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter Interface To An 8-Bit Data Bus CE CS tSSR The 12/8 input will be tied either high or low in most applications. With 12/8 high, all 12 output lines become active simultaneously for interface to a 12- or 16-bit data bus. A0 is ignored. Taking 12/8 low organizes the output in two 8-bit bytes, which are selected one at a time by A0. This allows an 8-bit data bus to be connected as shown below. A0 is normally tied to the LSB of the address bus for storing the converter's output in two consecutive memory locations. This two byte format is called "left justified data" for which a decimal point is assumed to the left of byte 1. In addition, A0 may be toggled at any time without damage to the converter. Break-before-make switching is guaranteed between two data bytes, which assures that the outputs strapped together as shown are never enabled at the same time. tHSR tHRR R/C tSRR A0 tSAR tHAR STS DB11-DB0 HIGH IMPEDANCE tHS tHD DATA VALID tDO tHL Figure 4. Read Cycle Timing ADDRESS BUS ADC-674 TIMING Symbol tDD tHD tHL tSSR tSRR tSAR tHSR tHRR tHAR tHS Parameter, Read Mode Access Time from CE Data Valid after CE low Output Float Delay CS to CE Setup R/C to CE Setup A0 to CE Setup CS Valid after CE Low RIC High after CE Low A0 Valid after CE Low STS Delay after Data Valid Min. 25 nS 50 nS 0 50 nS 0 0 0 nS 30 nS Typ. 0 0 0 0 - Max. 150 nS 120 nS 0 0 300 nS Symbol tDSC tHEC tSSC tHSC tSRC tHRC tSAC tHAC tC Parameter, Read Mode STS Delay From CE CE Pulse Width CS to CE Setup CS Low during CE High R/C to CE Setup R/C Low during CE High A0 to CE Setup A0 Valid during CD High Conversion Time: 12-bit cycle 8-bit cycle Min. 50 nS 50 nS 50 nS 50 nS 50 nS 0 50 nS Typ. - Max. 200 nS 0 - 6 S 4 S - 8 S 6 S 4 3 5 6 28 CS R/C CE STS A0 DB11 (MSB) 27 DB10 26 DB9 25 2 12/8 DB8 24 DB7 23 ADC-674 DATA BUS DB6 22 DB5 21 DB4 20 DB3 19 DB2 18 DB1 17 DB0 (LSB) 16 DGND 15 Figure 5. 8-Bit Data Bus Interface 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA * Tel: (508) 339-3000 * www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 6 of 7 (R) ADC-674 (R) 12-Bit, P-Compatible A/D Converter MECHANICAL DIMENSIONS - INCHES (mm) 0.070 0.007 (1.78 0.18) 0.050 0.002 (1.27 0.51) 0.300 0.004 (7.62 0.10) Pin 26 Pin 27 0.008R (0.20) Pin 28 BOTTOM VIEW Pin 1 Pin 2 0.025 0.004 (0.64 0.10) Pin 3 Pin 4 0.450 0.008 (1.143 0.20) 0.013 (0.33) ORDERING INFORMATION Murata Power Solutions, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1151 USA MODEL NUMBER OPERATING TEMP. RANGE ADC-674MC 0C TO 70C ADC-674ME -40C TO +85C ADC-674MM -55C TO +125C Datel, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of licenses to make, use, or sell equipment constructed in accordance therewith. Specifications are subject to change without notice. (c) 2011 Datel, Inc. ITAR and ISO 9001/14001 REGISTERED http://www.murata-ps.com/itar www.datel.com * e-mail: data.acquisition@datel.com 13 Jan 2011 MDA_ADC-674.A02 Page 7 of 7