Figure 1. ADC-674 Functional Block Diagram
COMP
OSCILLATOR CONTROL
LOGIC
10V
REF
S.A.R
THREE
STATE
BUFFERS
CAPACITANCE
DAC
BIPOLAR
OFFSET
10V IN
20V IN
V logic
D GND
DB11 (MSB)
STS
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0 (LSB)
12
13
14
1
15
27
28
26
25
24
23
22
21
20
19
18
17
16
5 6432810
REF IN REF OUT 12/8 CS A
0
9117
V
CC
V
EE
A
GND
R/C CE
BLOCK DIAGRAM
The ADC-674 A/D converters are single chip
monolithic CMOS versions of the industry standard
devices.
These units include a reference, clock, three-
state outputs, and digital interface circuit which
allows direct connection to the microprocessor
address bus and control lines. The ADC-674 com-
pletes a 12-bit conversion in 8 microseconds.
Four user selectable input ranges are provided:
0 to +10V, 0 to +20V, +/-5V, and +/-10V dc. Laser
trimming ensures specifi ed linearity, gain and
offset accuracy.
PRODUCT OVERVIEW
FEATURES
■ Complete 12-Bit A/D converters with reference
and clock
■ Pin-to-pin compatible with industry standard
HI574A/674A
■ No missing codes over temperature
■ 8 Sec. Conversion time
■ 150 mW maximum power dissipation
INPUT/OUTPUT CONNECTIONS
PIN FUNCTION PIN FUNCTION
1Vlogic, +5V 15 DGND
2 12/8, DATA MODE SELECT 11 DB0 (LSB)
3CS
, CHIP SELECT 17 DB1
4A
0, BYTE ADDRESS/SHORT CYCLE 18 DB2
5R/C
, READ/CONVERT 19 DB3
6 CE, CHIP ENABLE 20 DB4
7V
cc 21 DB5
8 REFERENCE OUT 22 DB6
9A
GND 23 DB7
10 REFERENCE IN 23 DB8
11 Vee 25 DB9
12 BIPOLAR OFFSET 26 DB10
13 10V IN 27 DB11 (MSB)
14 20V IN 28 STS
ADC-674
12-Bit, P-Compatible A/D Converter
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
®®
13 Jan 2011 MDA_ADC-674.A02 Page 1 of 7
ABSOLUTE MAXIMUM RATINGS
Vcc TO GND 0 to +16.5V
Vee TO GND 0 to -16.5V
Logic Supply Voltage (Pin 1) OV to +7V
Analog Common (Pin 9) to Digital Common (Pin 15) 0.5V to + 1V
Digital Control Inputs (Pins 2-6) to Digital Common -0.5V to Vlogic +0.5V
Analog Inputs (Pins 10,12,13) to Analog Common ±16.5V
20V Input (Pin 14) to Analog Common ±24V
Ref. Out (Pin 8) Short Circuit Duration Indefi nite to common momentary to Vs
Chip Temperature -55°C to 125°C
Package Dissipation 1000 mW
Lead Temperature, soldering 300°C, 10 Sec.
Thermal Resistance, Junction-to-Ambient 48°C/W
ANALOG INPUTS
Input Voltage Range unipolar 0 to +10V, O to +20V
bipolar ±5V, ±10V
Input Impedance 10V range 5K ±25%
20V range 10K ±25%
ANALOG OUTPUTS ➀
Internal Reference voltage +10.00V ±0.1 max.
current 2.0 mA max.
DIGITAL INPUTS ➁
Logic Levels: logic "1" +2.0 min. to +5.5V max.
logic "0" -0.5V min. to +0.8V max.
Loading: logic current ±1 A
max. +5 A
Capacitance 5pF
DIGITAL OUTPUTS ➂
Logic Levels: logic "0" (I sink, 1.6 mA) +0.4V max.
logic "1" (I source, 500 A) +2.4V min.
Leakage (high impedance state) -5 A min. to +5 A max.
Capacitance 5pF
POWER REQUIREMENTS
Analog Supply Voltage Range ±11.4V to ±16.5V
Logic Supply Voltage Range +4.5V to +5.5V
Supply-Current max. Analog Supply +7mA
Logic Supply +6mA
Power Consumption (+VS = +15V), max. 250 mW
PHYSICAL/ENVIRONMENTAL
Operating Temperature Range 55°C to +125°C
Storage Temperature Range -65°C to +150°C
Package Type 28 pin LCC ceramic
PERFORMANCE (TYPICAL)
Resolution 12 Bits
Unipolar Offset, max. ➄±0.5% of FSR
Conversion Time, max. 8 Sec
Full Scale Calibration Error at 25°C max ±0.6% of FSR
over temp. ➆±10 ppm/°C
Linearity Error, max. over temp. ±0.75 LSB
FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ±15V, and +5V dc supply ranges, unless otherwise noted.
ADC-674
12-Bit, P-Compatible A/D Converter
®®
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
13 Jan 2011 MDA_ADC-674.A02 Page 2 of 7
TECHNICAL NOTES
Footnotes:
1. The ADC-674 may interface directly to a microprocessor which can take
full control of each conversion, or the device can be operated in the "stand
alone" mode (controlled only by the R/C input). Full control consists of
selecting an 8- or 12-bit conversion cycle, initiating the conversion and
reading the output data when ready. The data may be read 12 bits at once
or 8 followed by 4 in a left-justifi ed format. There are fi ve control inputs
(12/8, CS, A0, R/C: and CE) and all are TTL/CMOS compatible. (See Control
Input Truth Table.)
2. A conversion is initiated by a logic transition on any of the three inputs: CE,
CS, R/C. One, two, or all three may be dynamically controlled. The nominal
delay for each of the three inputs is the same and if necessary, all three
may change states simultaneously. If it is required that a particular input
controls the start of conversion, the other two should be set up at least 50
nanoseconds earlier. (See Start Convert Timing, Figure 3).
3. To read the output data, four conditions must be met (or the output buffers
will remain in high impedance state): R/C taken high, STS low, CE high and
CS low. When this is accomplished, the data lines are activated according
to the state of the 12/8 and A0 inputs. (See TIMING DIAGRAM on Figure 4).
4. The analog signal source driving the ADC-674's input will see a nominal
load of 5 K (10V range) or 20 K (20V range). However, the other end of
these input resistors may change 400 mV with each bit decision, causing
sudden changes in current at the analog input. Therefore, the signal source
must maintain its output voltage while supplying these step changes in load
current which occur at 1.6 microsecond intervals. This requires low output
impedance and fast settling by the signal source.
5. The power supply used should be low noise and well regulated. Voltage
spikes can affect accuracy. If a switching supply is used, the outputs should
be carefully fi ltered to assure "noise free" dc voltage to the converter.
Decoupling capacitors should be used on all power supply pins; the +5V dc
supply decoupling capacitor should be connected directly from +Vlogic (Pin
1) to digital common (Pin 15). Vcc (Pin 7) should be decoupled directly to
AGND (Pin 9). It is recommended that a 10 F tantalum type in parallel with
a 0.1 F ceramic type be used for decoupling.
6. The use of good circuit board layout techniques is required for rated
performance. It is recommended that a double sided printed circuit board
with a ground plane on the component side be used. Other techniques,
such as wirewrapping or point-to-point wiring on vectorboard will have an
unpredictable effect on accuracy. Sensitive analog signals should be routed
between ground traces and kept away from digital lines. If analog and
digital lines must cross, they should do so at right angles.
PERFORMANCE (TYPICAL, CONT.)
Differential Linearity Error ➃±0.5LSB
Bipolar Offset, max. ➄±0.1% of FSR
Tempco: ➇Unipolar Offset max. ±20 ppm/°C
Bipolar Offset max. ±20 ppm/°C
Full Scale Calibration max. ±25 ppm/°C
Power Supply Rejection: ➈+Vs = 13.5V to 16.5V or +11.4V to +12.6V max. ±0.001%FSR/%V
±Vlogic = +4.5V to +5.5V max
➀ Available for external loads. External load should not change during conversion.
When supplying an external load using a +12V supply, a buffer amplifi er must be
provided for the reference output.
➁ Logic Inputs - CE, CS, R/C, A0, 12/8.
➂ Logic Outputs - DB11-DBO, STS.
➃ Over temperature.
➄ Adjustable to zero.
➅ With 50 fi xed resistor from REF OUT to REF IN. Adjustable to zero.
➆ No adjustment at 25°·C.
➇ Guaranteed maximum change, Tmin to Tmax (using internal reference).
➈ Maximum change in full scale calibration.
ADC-674
12-Bit, P-Compatible A/D Converter
®®
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
13 Jan 2011 MDA_ADC-674.A02 Page 3 of 7
TYPICAL CONNECTIONS
CODING TABLES
CALIBRATION
12
13
14
17
15
DB11 (MSB)
27
2811
DB10
26
DB9
25
DB8
24
DB7
23
DB6
22
DB5
21
DB4
20
DB3
19
DB2
18
DB1
17
DB0 (LSB)
16
5
6
4
3
2
8
9
10
Vcc NC STATUS
ADC-674
CE
REF IN
100Ω
+15V
-15V
100Ω
100kΩ
100kΩ
R2
R1
REF OUT
BIP OFF
10V IN
20V IN
AGND
DGND
A0
Vlog
12/8
R/C
CS
12
13
14
17
15
DB11 (MSB)
27
2811
DB10
26
DB9
25
DB8
24
DB7
23
DB6
22
DB5
21
DB4
20
DB3
19
DB2
18
DB1
17
DB0 (LSB)
16
5
6
4
3
2
8
9
10
Vcc NC STATUS
ADC-674
CE
REF IN
100Ω
100Ω
R2
R1
REF OUT
BIP OFF
10V IN
20V IN
AGND
DGND
A0
Vlog
12/8
R/C
CS
NOTES: The trimpots shown are for calibration of offset and gain. If adjustment is not required in unipolar, replace R2 with a 50, 1% metal fi lm resistor, omit the network on
Pin 12 and connect Pin 12 to Pin 9. In bipolar, either R1 or R2 or both can be replaced by 50, 1% metal fi lm resistors.
* Voltages shown are theoretical values for the transitions indicated. Ideally, In the continuous conversion mode, the output bits indicated as Ø will change from "1" to "0" or "0" to
"1" as the input voltage passes through the level indicated.
Output coding is straight binary for unipolar and offset binary for bipolar.
UNIPOLAR CALIBRATION
Offset Adjust
Apply an input of +½ LSB (+1.22 mV for the 10V range; +2.44 mV for the
20V range). Adjust the offset trimpot (R1) until the fi rst code transition fl ickers
between 0000 0000 0000 and 0000 0000 0001.
Gain Adjust
Apply 1½ LSB's below the nominal full-scale (+9.9963V for the 10V range;
+19.9927V for the 20V range). Adjust the gain-trimpot (R2) so that the output
fl ickers between 1111 1111 1110 and 1111 1111 1111.
BIPOLAR CALIBRATION
Offset Adjust
Apply ½ LSB above negative full-scale (-4.9988V for the ±5V range; -9.9976V
for the ±10V range.) Adjust the offset trimpot (R1) so that the output fl ickers
between 0000 0000 0000 and 0000 0000 0001.
Gain Adjust
Apply 1½ LSB's below positive full scale (+4.9963V for the ±5V range;
+9.9927V for the ±10V range). Adjust the gain trimpot (R2) so that the output
fl ickers between 1111 1111 1110 and 1111 1111 1111.
UNIPOLAR CONFIGURATION BIPOLAR CONFIGURATION
INPUT RANGE OUTPUT CODING
0 to + 10V O to +20V MSB LSB
+10.000 +20.0000 1111 1111 1111
+9.9963 +19.9927 1111 1111 111Ø*
+5.0012 +10.0024 1000 0000 000Ø*
+4.9988 +9.9976 ØOOO 0000 OOOØ*
+4.9963 +9.9927 0111 1111 111Ø*
+0.0012 +0.0024 0000 0000 O00Ø*
0.0000 +0.0000 0000 0000 0000
INPUT RANGE OUTPUT CODING
±5V ±10V LSB
+5.0000 +10.0000 1111 1111 1111
+4.9963 +9.9927 1111 1111 111Ø*
+0.0012 +0.0024 1000 0000 000Ø*
-0.0012 -0.0024 ØOOO 0000 OOOØ*
-0.0037 -0.0073 0111 1111 111Ø*
-4.9988 -9.9976 0000 0000 O00Ø*
-5.0000 -10.0000 0000 0000 0000
ADC-674
12-Bit, P-Compatible A/D Converter
®®
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
13 Jan 2011 MDA_ADC-674.A02 Page 4 of 7
TIMING CONTROL
The variety of the ADC-674's control modes (as shown in the "CONTROL INPUTS TRUTH TABLE") allow for simple interface in most system applications.
The output signal STS indicates the status of the device; high during a conversion, and low at the completion of a conversion. During a conversion (STS output
high), the output buffers remain in the high impedance state and data cannot be read. A start convert during conversion will not reset the converter or reinitiate a
conversion. However, if A0 changes state after a conversion begins, an additional start convert pulse will latch the new state of A0, causing a wrong cycle length for
that conversion.
Stand-Alone Mode Timing
For stand-alone operation, all that is required is a single control line to R/C, CE and 12/8 are tied high, CS and A0 are tied low, and the output appears in words of
12 bits
The R/C signal may have any duty cycle within the limits shown in the diagrams below
The data may be read when R/C is high unless STS is also high indicating a conversion is in progress.
TIMING AND OPERATION
Control Inputs Truth Table
CE CS R/C 12/8 A0OPERATION
0 x X X X None
X 1 X X X None
0-1 0 0 X 0 Initiate 12-bit conversion
0-1 0 0 X 1 Initiate a-bit conversion
1 1-0 0 X 0 Initiate 12-bit conversion
1 1-0 0 X 1 Initiate a-bit conversion
1 0 1-0 X 0 Initiate 12-bit conversion
1 0 1-0 X 1 Initiate a-bit conversion
1 0 1 1 X Enable 12-bit Output
1 0 1 0 0 Enables 8 MSB's only
1 0 1 0 1 Enables 4 LSB's plus 4 trailing zeroes
STS
DB11-DB0 DATA
VALID
DATA
VALID
R/C
50 ns
MIN
25 ns
MIN
30 ns MIN
1000 ns MAX
13 ns MIN
25 ns MAX
200 ns
MAX
Figure 1. Outputs Enabled After Conversion
STS
DB11-DB0 HIGH-Z HIGH-Z
DATA
VALID
R/C
150 ns
MIN
150 ns
MAX
25 ns
MIN
200 ns
MAX
Figure 2. Outputs Enabled With R/C High
Figure 3. Start Convert Timing
STS
DB11-DB0 HIGH IMPEDANCE
tHEC
tSSC
tHSC
tHRC
tSRC
tHAC
tC
tSAC
tDSC
CE
A0
R/C
CS
A read operation in most applications begins after the
conversion is complete and STS is low. For earliest access to
the data, however, the read should begin no later than (tDD +
tHS) before STS goes low. (See Technical Note 3.)
ADC-674
12-Bit, P-Compatible A/D Converter
®®
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
13 Jan 2011 MDA_ADC-674.A02 Page 5 of 7
STS
DB11-DB0 HIGH
IMPEDANCE
tSSR
tSRR
tSAR tHAR
tHSR
tHRR
tHD
tHS
tHL
tDO
CE
A0
R/C
CS
DATA
VALID
Figure 4. Read Cycle Timing
ADC-674 TIMING
Symbol Parameter, Read Mode Min. Typ. Max.
tDD Access Time from CE - - 150 nS
tHD Data Valid after CE low 25 nS - -
tHL Output Float Delay - - 120 nS
tSSR CS to CE Setup 50 nS 0 -
tSRR R/C to CE Setup 0 0 -
tSAR A0 to CE Setup 50 nS - -
tHSR CS Valid after CE Low 0 0 0
tHRR RIC High after CE Low 0 0 0
tHAR A0 Valid after CE Low 0 nS - -
tHS STS Delay after Data Valid 30 nS - 300 nS
Symbol Parameter, Read Mode Min. Typ. Max.
tDSC STS Delay From CE - - 200 nS
tHEC CE Pulse Width 50 nS - -
tSSC CS to CE Setup 50 nS - -
tHSC CS Low during CE High 50 nS - -
tSRC R/C to CE Setup 50 nS - -
tHRC R/C Low during CE High 50 nS - -
tSAC A
0 to CE Setup 0 - 0
tHAC A
0 Valid during CD High 50 nS - -
tCConversion Time:
12-bit cycle 6 S - 8 S
8-bit cycle 4 S - 6 S
Interface To An 8-Bit Data Bus
The 12/8 input will be tied either high or low in most applications. With 12/8
high, all 12 output lines become active simultaneously for interface to a 12- or
16-bit data bus. A0 is ignored. Taking 12/8 low organizes the output in two 8-bit
bytes, which are selected one at a time by A0. This allows an 8-bit data bus to
be connected as shown below. A0 is normally tied to the LSB of the address
bus for storing the converter's output in two consecutive memory locations.
This two byte format is called "left justifi ed data" for which a decimal point
is assumed to the left of byte 1. In addition, A0 may be toggled at any time
without damage to the converter. Break-before-make switching is guaranteed
between two data bytes, which assures that the outputs strapped together as
shown are never enabled at the same time.
Figure 5. 8-Bit Data Bus Interface
15
DB11 (MSB) 27
28
DB10 26
DB9 25
DB8 24
DB7 23
DB6 22
DB5 21
DB4 20
DB3 19
DB2 18
DB1 17
DB0 (LSB) 16
56
4
3
2
STS
ADC-674
ADDRESS BUS
DATA
BUS
CE
DGND
A0
12/8
R/CCS
ADC-674
12-Bit, P-Compatible A/D Converter
®®
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA • Tel: (508) 339-3000 • www.datel.com • e-mail: data.acquisition@datel.com
13 Jan 2011 MDA_ADC-674.A02 Page 6 of 7
http://www.murata-ps.com/itar
http://www.murata-ps.com/itar
MECHANICAL DIMENSIONS - INCHES (mm)
ORDERING INFORMATION
MODEL NUMBER OPERATING TEMP. RANGE
ADC-674MC 0°C TO 70°C
ADC-674ME -40°C TO +85°C
ADC-674MM -55°C TO +125°C
0.070 ±0.007
(1.78 ±0.18)
0.050 ±0.002
(1.27 ±0.51)
0.008R
(0.20)
0.300 ±0.004
(7.62 ±0.10)
BOTTOM
VIEW
Pin 26
Pin 27
Pin 28
Pin 1
Pin 2
Pin 3
Pin 4
0.025 ±0.004
(0.64 ±0.10)
0.450 ±0.008
(1.143 ±0.20)
0.013
(0.33)
ADC-674
12-Bit, P-Compatible A/D Converter
Datel, Inc. makes no representation that the use of its products in the circuits described herein, or the use of other technical information
contained herein, will not infringe upon existing or future patent rights. The descriptions contained herein do not imply the granting of
licenses to make, use, or sell equipment constructed in accordance therewith. Specifi cations are subject to change without notice.
© 2011 Datel, Inc.
www.datel.com • e-mail: data.acquisition@datel.com
®®
Murata Power Solutions, Inc.
11 Cabot Boulevard, Mansfi eld, MA 02048-1151 USA
ITAR and ISO 9001/14001 REGISTERED
13 Jan 2011 MDA_ADC-674.A02 Page 7 of 7
