General Description
The MAX17043/MAX17044 are ultra-compact, low-cost,
host-side fuel-gauge systems for lithium-ion (Li+) batter-
ies in handheld and portable equipment. The MAX17043
is configured to operate with a single lithium cell and the
MAX17044 is configured for a dual-cell 2S pack.
The MAX17043/MAX17044 use a sophisticated Li+ bat-
tery-modeling scheme, called ModelGauge™ to track
the battery’s relative state-of-charge (SOC) continuously
over a widely varying charge/discharge profile. Unlike
traditional fuel gauges, the ModelGauge algorithm elim-
inates the need for battery relearn cycles and an exter-
nal current-sense resistor. Temperature compensation
is possible in the application with minimal interaction
between a µC and the device.
A quick-start mode provides a good initial estimate of
the battery’s SOC. This feature allows the IC to be
located on system side, reducing cost and supply
chain constraints on the battery. Measurement and esti-
mated capacity data sets are accessed through an I2C
interface. The MAX17043/MAX17044 are available in
either a 0.4mm pitch 9-bump UCSP™ or 2mm x 3mm,
8-pin TDFN lead-free package.
Applications
Features
oHost-Side or Battery-Side Fuel Gauging
1 Cell (MAX17043)
2 Cell (MAX17044)
oPrecision Voltage Measurement
±12.5mV Accuracy to 5.00V (MAX17043)
±30mV Accuracy to 10.00V (MAX17044)
oAccurate Relative Capacity (RSOC) Calculated
from ModelGauge Algorithm
oNo Offset Accumulation on Measurement
oNo Full-to-Empty Battery Relearning Necessary
oNo Sense Resistor Required
oExternal Alarm/Interrupt for Low-Battery Warning
o2-Wire Interface
oLow Power Consumption
oTiny, Lead(Pb)-Free, 8-Pin, 2mm x 3mm TDFN
Package or Tiny 0.4mm Pitch 9-Bump UCSP
Package
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
1
Ordering Information
Li+
PROTECTION
CIRCUIT
MAX17043
MAX17044
CELL
1µF
1kΩ
10nF
150Ω
GND EP
CTG
SCL
SDA
QSTRT
VDD
ALRT
SYSTEM
µP
I2C BUS
MASTER
INTERRUPT
4.7kΩ
Simplified Operating Circuit
19-4811; Rev 6; 8/12
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE
MAX17043G+U -20°C to +70°C 8 TDFN-EP*
MAX17043G+T -20°C to +70°C 8 TDFN-EP*
MAX17043X+ -20°C to +70°C 9 UCSP
MAX17043X+T10
-20°C to +70°C 9 UCSP
MAX17044G+U -20°C to +70°C 8 TDFN-EP*
MAX17044G+T -20°C to +70°C 8 TDFN-EP*
MAX17044X+ -20°C to +70°C 9 UCSP
MAX17044X+T10
-20°C to +70°C 9 UCSP
+
Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*
EP = Exposed pad.
Smartphones
MP3 Players
Digital Still Cameras
Digital Video Cameras
Portable DVD Players
GPS Systems
Handheld and Portable
Applications
ModelGauge is a trademark of Maxim Integrated Products, Inc.
UCSP is a trademark of Maxim Integrated Products, Inc.
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
2
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(2.5V ≤VDD ≤4.5V, TA= -20°C to +70°C, unless otherwise noted. Contact Maxim for VDD greater than 4.5V.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on CTG Pin Relative to VGND ....................-0.3V to +12V
Voltage on CELL Pin Relative to VGND...................-0.3V to +12V
Voltage on All Other Pins Relative to VGND..............-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range
(TA= 0°C to +70°C (Note 10))........................-55°C to +125°C
Lead Temperature (TDFN soldering only, 10s) ...............+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Active Current IACTIVE 50 75 µA
VDD = 2.0V 0.5 1.0
Sleep-Mode Current (Note 2) ISLEEP 1 3
µA
VDD = 3.6V at +25°C -1 +1
TA = 0°C to +70°C (Note 10) -2 +2
Time-Base Accuracy tERR
TA = -20°C to +70°C -3 +3
%
TA = +25°C, VIN = VDD -12.5 +12.5
MAX17043 Voltage-
Measurement Error -30 +30
mV
TA = +25°C, 5.0V < VIN < 9.0V -30 +30
MAX17044 Voltage-
Measurement Error
VGERR
5.0 < VIN < 9.0 -60 +60 mV
CELL Pin Input Impedance RCELL 15 M
Input Logic-High:
SCL, SDA, QSTRT VIH (Note 1) 1.4 V
Input Logic-Low:
SCL, SDA, QSTRT VIL (Note 1) 0.5 V
Output Logic-Low: SDA VOL IOL = 4mA (Note 1) 0.4 V
Output Logic-Low: ALRT V
OL-ALRT I
OL-ALRT = 2mA (Note 1) 0.4 V
Pulldown Current: SCL, SDA IPD V
DD = 4.5V, VPIN = 0.4V 0.2 µA
Input Capacitance: SCL, SDA CBUS 50 pF
Bus Low Timeout tSLEEP (Note 3) 1.75 2.5 s
Mode Transition tTRAN (Note 4) 1 ms
ELECTRICAL CHARACTERISTICS RECOMMENDED DC OPERATING CONDITIONS
(2.5V ≤VDD ≤4.5V, TA= -20°C to +70°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Supply Voltage VDD (Note 1) +2.5 +4.5 V
Data I/O Pins
SCL, SDA,
QSTRT,
ALRT
(Note 1) -0.3 +5.5 V
MAX17043 CELL Pin VCELL (Note 1) -0.3 +5.0 V
MAX17044 CELL Pin VCELL (Note 1) -0.3 +10.0 V
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
3
Note 1: All voltages are referenced to GND.
Note 2: SDA, SCL = GND; QSTRT, ALRT idle.
Note 3: The MAX17043/MAX17044 enter Sleep mode 1.75s to 2.5s after (SCL < VIL) AND (SDA < VIL).
Note 4: Time to enter sleep after Sleep command is sent. Time to exit sleep on rising edge of SCL or SDA.
Note 5: fSCL must meet the minimum clock low time plus the rise/fall times.
Note 6: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL signal.
Note 7: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 8: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
Note 9: CB—total capacitance of one bus line in pF.
Note 10: Applies to 8-pin TDFN-EP package type only.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Frequency fSCL (Note 5) 0 400 kHz
Bus Free Time Between a STOP
and START Condition tBUF 1.3 µs
Hold Time (Repeated)
START Condition tHD:STA (Note 5) 0.6 µs
Low Period of SCL Clock tLOW 1.3 µs
High Period of SCL Clock tHIGH 0.6 µs
Setup Time for a Repeated
START Condition tSU:STA 0.6 µs
Data Hold Time tHD:DAT (Notes 6, 7) 0 0.9 µs
Data Setup Time tSU:DAT (Note 6) 100 ns
Rise Time of Both SDA
and SCL Signals tR20 +
0.1CB 300 ns
Fall Time of Both SDA
and SCL Signals tF20 +
0.1CB 300 ns
Setup Time for STOP Condition tSU:STO 0.6 µs
Spike Pulse Widths Suppressed
by Input Filter tSP (Note 8) 0 50 ns
Capacitive Load for Each
Bus Line CB(Note 9) 400 pF
SCL, SDA Input Capacitance CBIN 60 pF
ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(2.5V ≤VDD ≤4.5V, TA= -20°C to +70°C.)
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
4
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
QUIESCENT CURRENT vs. SUPPLY VOLTAGE
MAX17043/4 toc01
VDD (V)
QUIESCENT CURRENT (µA)
32451
20
40
60
80
100
0
0
TA = +70°C
TA = +25°C
TA = -20°C
SIMPLE C/2 RATE CYCLES*
SOC ACCURACY
MAX17043/4 toc02
TIME (h)
STATE OF CHARGE (%)
SOC ERROR (%)
12106842
10
20
30
40
50
60
70
80
90
100
0
-8
-6
-4
-2
0
2
4
6
8
10
-10
0
ERROR (%)
MAX17043/
MAX17044 SOC:
DASHED LINE
REFERENCE SOC:
SOLID LINE
C/2 RATE ZIGZAG PATTERN*
SOC ACCURACY
MAX17043/4 toc05
TIME (hr)
STATE OF CHARGE (%)
SOC ERROR (%)
1281622204
10
20
30
40
50
60
70
80
90
100
0
-8
-6
-4
-2
0
2
4
6
8
10
-10
0
ERROR (%)
MAX17043/MAX17044 SOC:
DASHED LINE
REFERENCE SOC:
SOLID LINE
SIMPLE C/4 RATE CYCLES*
SOC ACCURACY
MAX17043/4 toc03
TIME (hr)
STATE OF CHARGE (%)
SOC ERROR (%)
121068 1816 22201442
10
20
30
40
50
60
70
80
90
100
0
-8
-6
-4
-2
0
2
4
6
8
10
-10
0
ERROR (%)
MAX17043/
MAX17044 SOC:
DASHED LINE
REFERENCE SOC:
SOLID LINE
MAX17043 VOLTAGE ADC ERROR
vs. TEMPERATURE
MAX17043/4 toc04
TEMPERATURE (°C)
VOLTAGE ADC ERROR (mV)
3510 60 85-15
-15
-10
-5
0
5
10
15
20
-20
-40
VCELL = 3.0V
VCELL = 4.2V
VCELL = 3.6V
*
Sample accuracy with custom configuration data programmed into the IC.
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
5
TOP VIEW
(BUMPS ON BOTTOM)
SDA SCL CTG
QSTRT N.C. CELL
ALRT VDD GND
+
UCSP
123
B
C
A
MAX17043
MAX17044
1
+
34
865
SDA
QSTRT ALRT
2
7
SCL
CTG VDD GNDCELL
TDFN
(2mm × 3mm)
TOP VIEW
MAX17043
MAX17044
Pin Configurations
Pin Description
PIN NAME FUNCTION
UCSP TDFN
A1 8 SDA Serial Data Input/Output. Open-drain 2-wire data line. Connect this pin to the DATA signal of the 2-
wire interface. This pin has a 0.2µA typical pulldown to sense disconnection.
A2 7 SCL Serial Clock Input. Input only 2-wire clock line. Connect this pin to the CLOCK signal of the 2-wire
interface. This pin has a 0.2µA typical pulldown to sense disconnection.
A3 1 CTG Connect to Ground. Connect to VSS during normal operation.
B1 6 QSTRT Quick-Start Input. Allows reset of the device through hardware. Connect to GND if not used.
B2 N.C. No connect. Do not connect.
B3 2 CELL Battery Voltage Input. The voltage of the cell pack is measured through this pin.
C1 5 ALRT Alert Output. Active-low interrupt signaling low state of charge. Connect to interrupt input of the
system microprocessor.
C2 3 VDD Power-Supply Input. 2.5V to 4.5V input range. Connect to system power through a decoupling
network. Connect a 10nF typical decoupling capacitor close to pin.
C3 4 GND Ground. Connect to the negative power rail of the system.
— — EP Exposed Pad (TDFN only). Connect to ground.
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
6
SDA
SCL
tF
tLOW
tHD:STA
tHD:DAT
tSU:STA tSU:STO
tSU:DAT tHD:STA
tSP tRtBUF
tR
tF
SSr
PS
Figure 1. 2-Wire Bus Timing Diagram
Detailed Description
Figure 1 shows the 2-wire bus timing diagram, and
Figure 2 is the MAX17043/MAX17044 block diagram.
ModelGauge Theory of Operation
The MAX17043/MAX17044 use a sophisticated battery
model that determines the SOC of a nonlinear Li+
battery. The model effectively simulates the internal
dynamics of a Li+ battery and determines the SOC. The
model considers the time effects of a battery caused by
the chemical reactions and impedance in the battery.
The MAX17043/MAX17044 SOC calculation does not
accumulate error with time. This is advantageous
compared to traditional coulomb counters, which suffer
from SOC drift caused by current-sense offset and cell
self-discharge. This model provides good performance
for many Li+ chemistry variants across temperature
and age. To achieve optimum performance, the
MAX17043/MAX17044 must be programmed with con-
figuration data custom to the application. Contact the
factory for details.
Fuel-Gauge Performance
The classical coulomb-counter-based fuel gauges suf-
fer from accuracy drift due to the accumulation of the
offset error in the current-sense measurement. Although
the error is often very small, the error increases over
time in such systems, cannot be eliminated, and
requires periodic corrections. The corrections are usu-
ally performed on a predefined SOC level near full or
empty. Some other systems use the relaxed battery
voltage to perform corrections. These systems deter-
mine the true SOC based on the battery voltage after a
long time of no activity. Both have the same limitation: if
the correction condition is not observed over time in the
actual application, the error in the system is boundless.
In some systems, a full-charge/discharge cycle is
required to eliminate the drift error. To determine the
true accuracy of a fuel gauge, as experienced by end
users, the battery should be exercised in a dynamic
manner. The end-user accuracy cannot be understood
with only simple cycles. MAX17043/MAX17044 do not
suffer from the drift problem since they do not rely on
the current information.
STATE
MACHINE
(SOC, RATE)
2-WIRE
INTERFACE
IC
GROUND
TIME BASE
(32kHz)
ADC (VCELL)
VOLTAGE
REFERENCE
BIAS
GND
CELL
VDD
SCL
SDA
ALRT
QSTRT
CTG
MAX17043
MAX17044
Figure 2. Block Diagram
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
7
IC Power-Up
When the battery is first inserted into the system, there
is no previous knowledge about the battery’s SOC. The
IC assumes that the battery has been in a relaxed state
for the previous 30min. The first A/D voltage measure-
ment is translated into a best “first guess” for the SOC.
Initial error caused by the battery not being in a relaxed
state fades over time, regardless of cell loading follow-
ing this initial conversion. Because the SOC determina-
tion is convergent rather than divergent (as in a
coulomb counter), this initial error does not have a long-
lasting impact.
Quick-Start
A quick-start allows the MAX17043/MAX17044 to restart
fuel-gauge calculations in the same manner as initial
power-up of the IC. For example, if an application’s
power-up sequence is exceedingly noisy such that
excess error is introduced into the IC’s “first guess” of
SOC, the host can issue a quick-start to reduce the
error. A quick-start is initiated by a rising edge on the
QSTRT pin, or through software by writing 4000h to the
MODE register.
ALERT Interrupt
The MAX17043/MAX17044 have an interrupt feature
that alerts a host microprocessor whenever the cell's
state of charge, as defined by the SOC register, falls
below a predefined alert threshold set at address 0Dh
of the CONFIG register.
When an alert is triggered, the IC drives the ALRT pin to
logic-low and sets the ALRT bit in the CONFIG register
to logic 1. The ALRT pin remains logic-low until the host
software writes the ALRT bit to logic 0 to clear the inter-
rupt. Clearing the ALRT bit while SOC is below the alert
threshold does not generate another interrupt. The SOC
register must first rise above and then fall below the alert
threshold value before another interrupt is generated.
Note that the alert function is not disabled at IC power-
up. If the first SOC calculation is below the threshold
setting, an interrupt is generated. Entering Sleep mode
does not clear the interrupt.
Sleep Mode
Holding both SDA and SCL logic-low forces the
MAX17043/MAX17044 into Sleep mode. While in Sleep
mode, all IC operations are halted and power drain of
the IC is greatly reduced. After exiting Sleep mode,
fuel-gauge operation continues from the point it was
halted. SDA and SCL must be held low for at least 2.5s
to guarantee transition into Sleep mode. Afterwards, a
rising edge on either SDA or SCL immediately transi-
tions the IC out of Sleep mode.
Alternatively, Sleep mode can be entered by setting the
SLEEP bit in the CONFIG register to logic 1 through I2C
communication. If the SLEEP bit is set to logic 1, the
only way to exit Sleep mode is to write SLEEP to logic 0
or power-on reset the IC.
Power-On Reset (POR)
Writing a value of 0054h to the COMMAND register caus-
es the MAX17043/MAX17044 to completely reset as if
power had been removed. The reset occurs when the last
bit has been clocked in. The IC does not respond with an
I2C ACK after this command sequence.
Registers
All host interaction with the MAX17043/MAX17044 is
handled by writing to and reading from register loca-
tions. The MAX17043/MAX17044 have six 16-bit regis-
ters: SOC, VCELL, MODE, VERSION, CONFIG, and
COMMAND. Register reads and writes are only valid if
all 16 bits are transferred. Any write command that is
terminated early is ignored. The function of each regis-
ter is described as follows. All remaining address loca-
tions not listed in Table 1 are reserved. Data read from
reserved locations is undefined.
ADDRESS
(HEX) REGISTER DESCRIPTION READ/
WRITE
DEFAULT
(HEX)
02h–03h VCELL Reports 12-bit A/D measurement of battery voltage. R —
04h–05h SOC Reports 16-bit SOC result calculated by ModelGauge algorithm. R —
06h–07h MODE Sends special commands to the IC. W —
08h–09h VERSION Returns IC version. R —
0Ch–0Dh CONFIG
Battery compensation. Adjusts IC performance based on
application conditions. R/W 971Ch
FEh–FFh COMMAND Sends special commands to the IC. W —
Table 1. Register Summary
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
8
VCELL Register
Battery voltage is measured at the CELL pin input with
respect to GND over a 0 to 5.00V range for the
MAX17043 and 0 to 10.00V for the MAX17044 with reso-
lutions of 1.25mV and 2.50mV, respectively. The A/D
calculates the average cell voltage for a period of
125ms after IC POR and then for a period of 500ms for
every cycle afterwards. The VCELL register requires
500ms to update after exiting Sleep mode. The result is
placed in the VCELL register at the end of each conver-
sion period. Figure 3 shows the VCELL register format.
SOC Register
The SOC register is a read-only register that displays
the state of charge of the cell as calculated by the
ModelGauge algorithm. The result is displayed as a
percentage of the cell’s full capacity. This register
automatically adapts to variation in battery size since
the MAX17043/MAX17044 naturally recognize relative
SOC. Units of % can be directly determined by observ-
ing only the high byte of the SOC register. The low byte
provides additional resolution in units 1/256%. The
reported SOC also includes residual capacity, which
might not be available to the actual application because
of early termination voltage requirements. When SOC()
= 0, typical applications have no remaining capacity.
The first update occurs within 250ms after POR of the
IC. Subsequent updates occur at variable intervals
depending on application conditions. ModelGauge cal-
culations outside the register are clamped at minimum
and maximum register limits. Figure 4 shows the SOC
register format.
MODE Register
The MODE register allows the host processor to send
special commands to the IC (Table 2). Valid MODE reg-
ister write values are listed as follows. All other MODE
register values are reserved.
VERSION Register
The VERSION register is a read-only register that con-
tains a value indicating the production version of the
MAX17043/MAX17044.
CONFIG Register
The CONFIG register compensates the ModelGauge
algorithm, controls the alert interrupt feature, and forces
the IC into Sleep mode through software. The format of
CONFIG is shown in Figure 5.
CONFIG
CONFIG is an 8-bit value that can be adjusted to opti-
mize IC performance for different lithium chemistries or
different operating temperatures. Contact Maxim for
instructions for optimization. The power-up default
value for CONFIG is 97h.
MSB—ADDRESS 02h LSB—ADDRESS 03h
211 2
10 2
9 2
8 2
7 2
6 2
5 2
4 2
3 2
2 2
1 2
0 0 0 0 0
MSB LSB MSB LSB
0: BITS ALWAYS READ LOGIC 0 UNITS: 1.25mV FOR MAX17043
2.50mV FOR MAX17044
Figure 3. VCELL Register Format
MSB—ADDRESS 04h LSB—ADDRESS 05h
27 2
6 2
5 2
4 2
3 2
2 2
1 2
0 2
-1 2
-2 2
-3 2
-4 2
-5 2
-6 2
-7 2
-8
MSB LSB MSB LSB
UNITS: 1.0%
Figure 4. SOC Register Format
VALUE COMMAND DESCRIPTION
4000h Quick-Start
See the Quick-Start
description section.
Table 2. MODE Register Commands
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
9
SLEEP (Sleep Bit)
Writing SLEEP to logic 1 forces the ICs into Sleep
mode. Writing SLEEP to logic 0 forces the ICs to exit
Sleep mode. The power-up default value for SLEEP is
logic 0.
X (Don't Care)
This bit reads as either a logic 0 or logic 1. This bit cannot
be written.
ALRT (ALERT Flag)
This bit is set by the IC when the SOC register value
falls below the alert threshold setting and an interrupt is
generated. This bit can only be cleared by software.
The power-up default value for ALRT is logic 0.
ATHD (Alert Threshold)
The alert threshold is a 5-bit value that sets the state of
charge level where an interrupt is generated on the
ALRT pin. The alert threshold has an LSb weight of 1%
and can be programmed from 1% up to 32%. The
threshold value is stored in two’s-complement form
(00000 = 32%, 00001 = 31%, 00010 = 30%, 11111 =
1%). The power-up default value for ATHD is 4% or 1Ch.
COMMAND Register
The COMMAND register allows the host processor to
send special commands to the IC. Valid COMMAND
register write values are listed as follows. All other
COMMAND register values are reserved. Table 3
shows COMMAND register commands.
Application Examples
The MAX17043/MAX17044 have a variety of configura-
tions, depending on the application. Table 4 shows the
most common system configurations and the proper
pin connections for each.
VALUE COMMAND DESCRIPTION
0054h POR
See the Power-On Reset
(POR) section.
Table 3. COMMAND Register Commands
SYSTEM CONFIGURATION IC VDD ALRT QSTRT
1S Pack-Side Location MAX17043 Power directly from battery Leave unconnected Connect to GND
1S Host-Side Location MAX17043 Power directly from battery Leave unconnected Connect to GND
1S Host-Side Location,
Low Cell Interrupt MAX17043 Power directly from battery Connect to system
interrupt Connect to GND
1S Host-Side Location,
Hardware Quick-Start MAX17043 Power directly from battery Leave unconnected Connect to rising-edge
reset signal
2S Pack-Side Location MAX17044 Power from +2.5V to +4.5V
LDO in pack Leave unconnected Connect to GND
2S Host-Side Location MAX17044 Power from +2.5V to +4.5V
LDO or PMIC Leave unconnected Connect to GND
2S Host-Side Location,
Low Cell Interrupt MAX17044 Power from +2.5V to +4.5V
LDO or PMIC
Connect to system
interrupt Connect to GND
2S Host-Side Location,
Hardware Quick-Start MAX17044 Power from +2.5V to +4.5V
LDO or PMIC Leave unconnected Connect to rising-edge
reset signal
Table 4. Possible Application Configurations
Figure 5. CONFIG Register Format
MSB—ADDRESS 0Ch LSB—ADDRESS 0Dh
R C OM P
27
R C OM P
26
R C OM P
25
R C OM P
24
R C OM P
23
R C OM P
22
R C OM P
21
R C OM P
20
SLEEP X ALRT
ATHD
24
ATHD
23
ATHD
22
ATHD
21
ATHD
20
MSB LSB MSB LSB
ATHD UNITS: 1 LSB = 2’S COMPLEMENT 1%
ATHD RANGE: 11111b = 1%
00000b = 32%
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
10
Figure 6 shows an example application for a 1S cell
pack. The MAX17043 is mounted on the system side
and powered directly from the cell pack. The external
RC networks on VDD and CELL provide noise filtering of
the IC power supply and A/D measurement. In this
example, the ALRT pin is connected to the micro-
processor's interrupt input to allow the MAX17043 to
signal when the battery is low. The QSTRT pin is
unused in this application, so it is tied to GND.
Figure 7 shows a MAX17044 example application using
a 2S cell pack. The MAX17044 is mounted on the sys-
tem side and powered from a 3.3V supply generated
by the system. The CELL pin is still connected directly
to PACK+ through an external noise filter. The ALRT pin
is left unconnected because the interrupt feature is not
used in this application. After power is supplied, the
system watchdog generates a low-to-high transition on
the QSTRT pin to signal the MAX17044 to perform a
quick-start.
PACK-
PACK+
PROTECTION IC
(Li+/POLYMER)
SYSTEM GND
SYSTEM VDD
BATTERY SYSTEM
MAX17043
CELL
EP
1µF
1kΩ
10nF
150Ω
GND
CTG
SCL
SDA
QSTRT
VDD
ALRT
SYSTEM µP
I2C BUS
MASTER
INTERRUPT
INPUT
4.7kΩ
Figure 6. MAX17043 Application Example with Alert Interrupt
PACK-
PACK+
PROTECTION IC
(Li+/POLYMER)
SYSTEM GND
SYSTEM VDD
BATTERY SYSTEM
MAX17044
CELL
1µF
1kΩ
GND
CTG SCL
SDA
QSTRT
VDD
SYSTEM PMIC
SYSTEM µP
I2C BUS
MASTER
3.3V OUTPUT
WATCHDOG
ALRT
EP
Figure 7. MAX17044 Application Example with Hardware Reset
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
11
2-Wire Bus System
The 2-wire bus system supports operation as a slave-
only device in a single or multislave, and single or multi-
master system. Slave devices can share the bus by
uniquely setting the 7-bit slave address. The 2-wire
interface consists of a serial-data line (SDA) and serial-
clock line (SCL). SDA and SCL provide bidirectional
communication between the MAX17043/MAX17044
slave device and a master device at speeds up to
400kHz. The MAX17043/MAX17044s’ SDA pin operates
bidirectionally; that is, when the MAX17043/MAX17044
receive data, SDA operates as an input, and when the
MAX17043/MAX17044 return data, SDA operates as an
open-drain output, with the host system providing a
resistive pullup. The MAX17043/MAX17044 always
operate as a slave device, receiving and transmitting
data under the control of a master device. The master
initiates all transactions on the bus and generates the
SCL signal, as well as the START and STOP bits, which
begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock
cycle, with the cycle defined by SCL transitioning low-
to-high and then high-to-low. The SDA logic level must
remain stable during the high period of the SCL clock
pulse. Any change in SDA when SCL is high is inter-
preted as a START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condi-
tion (S) by forcing a high-to-low transition on SDA while
SCL is high. The master terminates a transaction with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high. A Repeated START condition (Sr)
can be used in place of a STOP then START sequence
to terminate one transaction and begin another without
returning the bus to the idle state. In multimaster sys-
tems, a Repeated START allows the master to retain
control of the bus. The START and STOP conditions are
the only bus activities in which the SDA transitions
when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an
acknowledge bit (A) or a no-acknowledge bit (N). Both
the master and the MAX17043 slave generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low until SCL returns low. To generate a no-
acknowledge (also called NAK), the receiver releases
SDA before the rising edge of the acknowledge-related
clock pulse and leaves SDA high until SCL returns low.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer can occur if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication.
Data Order
A byte of data consists of 8 bits ordered most signifi-
cant bit (MSb) first. The least significant bit (LSb) of
each byte is followed by the acknowledge bit. The
MAX17043/MAX17044 registers composed of multibyte
values are ordered MSb first. The MSb of multibyte reg-
isters is stored on even data-memory addresses.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address (SAddr) and the read/write (R/W) bit.
When the bus is idle, the MAX17043/MAX17044 contin-
uously monitor for a START condition followed by its
slave address. When the MAX17043/MAX17044
receive a slave address that matches the value in the
slave address register, they respond with an acknowl-
edge bit during the clock period following the R/W bit.
The 7-bit slave address is fixed to 6Ch (write)/
6Dh (read):
Read/Write Bit
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W
= 0 selects a write transaction, with the following bytes
being written by the master to the slave. R/W = 1
selects a read transaction, with the following bytes
being read from the slave by the master. (Table 5).
MAX17043/MAX17044
SLAVE ADDRESS 0110110
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
12
Bus Timing
The MAX17043/MAX17044 are compatible with any bus
timing up to 400kHz. No special configuration is
required to operate at any speed.
2-Wire Command Protocols
The command protocols involve several transaction for-
mats. The simplest format consists of the master writing
the START bit, slave address, R/W bit, and then moni-
toring the acknowledge bit for presence of the
MAX17043/MAX17044. More complex formats, such as
the Write Data and Read Data, read data and execute
device-specific operations. All bytes in each command
format require the slave or host to return an acknowl-
edge bit before continuing with the next byte. Table 5
shows the key that applies to the transaction formats.
Basic Transaction Formats
A write transaction transfers 2 or more data bytes to the
MAX17043/MAX17044. The data transfer begins at the
memory address supplied in the MAddr byte. Control of
the SDA signal is retained by the master throughout the
transaction, except for the acknowledge cycles:
A read transaction transfers 2 or more bytes from the
MAX17043/MAX17044. Read transactions are com-
posed of two parts, a write portion followed by a read
portion, and are therefore inherently longer than a write
transaction. The write portion communicates the starting
point for the read operation. The read portion follows
immediately, beginning with a Repeated START, slave
address with R/W set to a 1. Control of SDA is assumed
by the MAX17043/MAX17044, beginning with the slave
address acknowledge cycle. Control of the SDA signal
is retained by the MAX17043/MAX17044 throughout the
transaction, except for the acknowledge cycles. The
master indicates the end of a read transaction by
responding to the last byte it requires with a no
acknowledge. This signals the MAX17043/MAX17044
that control of SDA is to remain with the master following
the acknowledge clock.
Write Data Protocol
The write data protocol is used to write to register to the
MAX17043/MAX17044 starting at memory address
MAddr. Data0 represents the data written to MAddr,
Data1 represents the data written to MAddr + 1, and
DataN represents the last data byte, written to MAddr +
N. The master indicates the end of a write transaction
by sending a STOP or Repeated START after receiving
the last acknowledge bit:
The MSB of the data to be stored at address MAddr
can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically
incremented after the LSB of each byte is received by
the MAX17043/MAX17044, the MSB of the data at
address MAddr + 1 can be written immediately after
the acknowledgment of the data at address MAddr. If
the bus master continues an autoincremented write
transaction beyond address 4Fh, the MAX17043/
MAX17044 ignore the data. A valid write must include
both register bytes. Data is also ignored on writes to
read-only addresses. Incomplete bytes and bytes that
are not acknowledged by the MAX17043/MAX17044
are not written to memory.
SAddr W. A. MAddr. A. Data0. A. Data1. A... DataN. A
Read: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. N. P
Write Portion Read Portion
Write: S. SAddr W. A. MAddr. A. Data0. A. Data1. A. P
KEY DESCRIPTION KEY DESCRIPTION
S START bit Sr Repeated START
SAddr Slave address (7 bit) W R/W bit = 0
MAddr Memory address byte P STOP bit
Data Data byte written by master Data Data byte returned by slave
A Acknowledge bit—master A Acknowledge bit—slave
N No acknowledge—master N No acknowledge—slave
Table 5. 2-Wire Protocol Key
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
13
Read Data Protocol
The read data protocol is used to read to register from
the MAX17043/MAX17044 starting at the memory
address specified by MAddr. Both register bytes must
be read in the same transaction for the register data to
be valid. Data0 represents the data byte in memory loca-
tion MAddr, Data1 represents the data from MAddr + 1,
and DataN represents the last byte read by the master:
Data is returned beginning with the MSB of the data in
MAddr. Because the address is automatically incre-
mented after the LSB of each byte is returned, the MSB
of the data at address MAddr + 1 is available to the
host immediately after the acknowledgment of the data
at address MAddr. If the bus master continues to read
beyond address FFh, the MAX17043/MAX17044 output
data values of FFh. Addresses labeled Reserved in the
memory map return undefined data. The bus master
terminates the read transaction at any byte boundary
by issuing a no acknowledge followed by a STOP or
Repeated START.
S. SAddr W. A. MAddr. A. Sr. SAddr R. A.
Data0. A. Data1. A... DataN. N. P
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
8 TDFN T823+1 21-0174 90-0091
9 UCSP W91C1+1 21-0459 Refer to
Application Note 1891
MAX17043/MAX17044
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
14
_______________Maxim Integrated Products, Inc. 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/09 Initial release —
1 4/10
Updated soldering temperature information; updated CTG pin voltage range to from 0.3V
to +12V to -0.3V to +12V in Absolute Maximum Ratings section; removed future
asterisks in ordering table; changed update time for SOC and VCELL; changed registers
from 110ms/440ms to 125ms/500ms
1, 2, 8
2 9/10 Added description and ordering information for UCSP package type 1, 2, 3, 5,
13, 14
3 10/10 Updated Ordering Information table 1, 2, 13,14
4 8/11
Corrected time from start up until SOC valid; added text indicating accurate results
require custom configuration for each application 4, 6, 8, 14
5 6/12 Corrected soldering temperature in Absolute Maximum Ratings 2
6 8/12 Changed Soft POR command from 5400h to 0054h to avoid possible memory corruption 7, 9, 14
