CDR31BX102BKWSTR - AVX - Datasheet.Live

Features

•Low-voltage and Standard-voltage Operation

– 2.7 (VCC = 2.7V to 5.5V)

– 1.8 (VCC = 1.8V to 3.6V)

•Internally Organized 65,536 x 8

•Two-wire Serial Interface

•Schmitt Triggers, Filtered Inputs for Noise Suppression

•Bidirectional Data Transfer Protocol

•1 MHz (5V), 400 kHz (2.7V) and 100 kHz (1.8V) Compatibility

•Write Protect Pin for Hardware and Software Data Protection

•128-byte Page Write Mode (Partial Page Writes Allowed)

•Self-timed Write Cycle (5 ms Max)

•High Reliability

– Endurance: 100,000 Write Cycles

– Data Retention: 40 Years

•Automotive Devices Available

•8-lead PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP,

8-lead LAP, 8-lead SAP and 8-ball dBGA2 Packages

•Die Sales: Wafer Form, Waffle Pack and Bumped Die

Description

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable

read only memory (EEPROM) organized as 65,536 words of 8 bits each. The device’s

cascadable feature allows up to four devices to share a common two-wire bus. The

device is optimized for use in many industrial and commercial applications where low-

power and low-voltage operation are essential. The devices are available in space-

saving 8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC SOIC, 8-lead TSSOP, 8-lead

Leadless Array (LAP), and 8-lead SAP packages. In addition, the entire family is avail-

able in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V) versions.

Table 1. Pin Configurations

Pin Name Function

A0–A1 Address Inputs

SDA Serial Data

SCL Serial Clock Input

WP Write Protect

NC No Connect

Rev. 1116O–SEEPR–1/07

Two-wire Serial

EEPROM

512K (65,536 x 8)

AT24C512

Note: Not recommended for new

design; please refer to

AT24C512B datasheet.

8-lead PDIP

GND

VCC

SCL

SDA

8-lead Leadless Array

Bottom View

SCL

8-lead TSSOP

8-lead SAP

Bottom View

SCL

8-lead SOIC

GND

VCC

SCL

SDA

8-ball dBGA2

Bottom View

VCC

SCL

SDA

GND

2AT24C512

1116O–SEEPR–1/07

Figure 1. Block Diagram

Absolute Maximum Ratings*

Operating Temperature..................................–55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature .....................................–65°C to +150°C

Voltage on Any Pin

with Respect to Ground ....................................–1.0V to +7.0V

Maximum Operating Voltage .......................................... 6.25V

DC Output Current........................................................ 5.0 mA

AT24C512

1116O–SEEPR–1/07

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each

EEPROM device and negative edge clock data out of each device.

SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is

open-drain driven and may be wire-ORed with any number of other open-drain or open

collector devices.

DEVICE/ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that are

hardwired or left not connected for hardware compatibility with other AT24Cxx devices.

When the pins are hardwired, as many as four 512K devices may be addressed on a

single bus system (device addressing is discussed in detail under the Device Address-

ing section. If the pins are left floating, the A1 and A0 pins will be internally pulled down

to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the address pins to GND.

WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-

mal write operations. When WP is connected high to VCC, all write operations to the

memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down

to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is

>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a

write operation creates a software write protect function.

Memory Organization AT24C512, 512K SERIAL EEPROM: The 512K is internally organized as 512 pages of

128-bytes each. Random word addressing requires a 16-bit data word address.

4AT24C512

1116O–SEEPR–1/07

Note: 1. This parameter is characterized and is not 100% tested.

Note: 1. VIL min and VIH max are reference only and are not tested.

Table 2. Pin Capacitance(1)

Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V

Symbol Test Condition Max Units Conditions

CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V

CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

Table 3. DC Characteristics

Applicable over recommended operating range from: TAI = –40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,

VCC = +1.8V to +5.5V (unless otherwise noted)

Symbol Parameter Test Condition Min Typ Max Units

VCC1 Supply Voltage 1.8 3.6 V

VCC2 Supply Voltage 2.7 5.5 V

VCC3 Supply Voltage 4.5 5.5 V

ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA

ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

ISB1

Standby Current

(1.8V option)

VCC = 1.8V

VIN = VCC or VSS

1.0 µA

VCC = 3.6V 3.0

ISB2

Standby Current

(2.7V option)

VCC = 2.7V

VIN = VCC or VSS

2.0 µA

VCC = 5.5V 6.0

ISB3

Standby Current

(5.0V option) VCC = 4.5 - 5.5V VIN = VCC or VSS 6.0 µA

ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA

ILO

Output Leakage

Current VOUT = VCC or VSS 0.05 3.0 µA

VIL Input Low Level(1) –0.6 VCC x 0.3 V

VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V

VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V

VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

AT24C512

1116O–SEEPR–1/07

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:

RL (connects to VCC): 1.3 kΩ (2.7V, 5V), 10 kΩ (1.8V)

Input pulse voltages: 0.3VCC to 0.7VCC

Input rise and fall times: ≤50 ns

Input and output timing reference voltages: 0.5VCC

3. The Write Cycle Time of 5 ms only applies to the AT24C512 devices bearing the process letter “A” on the package (the mark

is located in the lower right corner on the top side of the package).

Table 4. AC Characteristics

Applicable over recommended operating range from TA = –40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-

erwise noted) Test conditions are listed in Note 2.

Symbol Parameter

1.8 Volt 2.7 Volt 5.0 Volt

UnitsMin Max Min Max Min Max

fSCL Clock Frequency, SCL 100 400 1000 kHz

tLOW Clock Pulse Width Low 4.7 1.3 0.4 µs

tHIGH Clock Pulse Width High 4.0 1.0 0.4 µs

tAA Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs

tBUF

Time the bus must be free before a

new transmission can start(1) 4.7 1.3 0.5 µs

tHD.STA Start Hold Time 4.0 0.6 0.25 µs

tSU.STA Start Set-up Time 4.7 0.6 0.25 µs

tHD.DAT Data In Hold Time 0 0 0 µs

tSU.DAT Data In Set-up Time 200 100 100 ns

tRInputs Rise Time(1) 1.0 0.3 0.3 µs

tFInputs Fall Time(1) 300 300 100 ns

tSU.STO Stop Set-up Time 4.7 0.6 0.25 µs

tDH Data Out Hold Time 100 50 50 ns

tWR Write Cycle Time 20 or 5(3) 10 or 5(3) 10 or 5(3) ms

Endurance(1) 5.0V, 25°C, Page Mode 100K 100K 100K Write Cycles

6AT24C512

1116O–SEEPR–1/07

Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-

nal device. Data on the SDA pin may change only during SCL low time periods (see

Figure 4 on page 7). Data changes during SCL high periods will indicate a start or stop

condition as defined below.

START CONDITION: A high-to-low transition of SDA with SCL high is a start condition

which must precede any other command (see Figure 5 on page 8).

STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.

After a read sequence, the stop command will place the EEPROM in a standby power

mode (see Figure 5 on page 8).

ACKNOWLEDGE: All addresses and data words are serially transmitted to and from

the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to

acknowledge that it has received each word.

STANDBY MODE: The AT24C512 features a low power standby mode which is

enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion

of any internal operations.

MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-

wire part can be reset by following these steps:

(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then

AT24C512

1116O–SEEPR–1/07

Figure 2. Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Figure 3. Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

Figure 4. Data Validity

twr

(1)

STOP

CONDITION START

CONDITION

WORDn

ACK

8th BIT

8AT24C512

1116O–SEEPR–1/07

Figure 5. Start and Stop Definition

Figure 6. Output Acknowledge

AT24C512

1116O–SEEPR–1/07

Device Addressing The 512K EEPROM requires an 8-bit device address word following a start condition to

enable the chip for a read or write operation (see Figure 7 on page 10). The device

address word consists of a mandatory “1”, “0” sequence for the first five most significant

bits as shown. This is common to all two-wire EEPROM devices.

The 512K uses the two device address bits A1, A0 to allow as many as four devices on

the same bus. These bits must compare to their corresponding hardwired input pins.

The A1 and A0 pins use an internal proprietary circuit that biases them to a logic low

condition if the pins are allowed to float.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a “0”. If a compare is

not made, the device will return to a standby state.

DATA SECURITY: The AT24C512 has a hardware data protection scheme that allows

the user to Write Protect the whole memory when the WP pin is at VCC.

Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a “0” and then clock in the first 8-bit data word. Following receipt

of the 8-bit data word, the EEPROM will output a “0”. The addressing device, such as a

microcontroller, then must terminate the write sequence with a stop condition. At this

time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory.

All inputs are disabled during this write cycle and the EEPROM will not respond until the

write is complete (see Figure 8 on page 11).

PAGE WRITE: The 512K EEPROM is capable of 128-byte page writes.

A page write is initiated the same way as a byte write, but the microcontroller does not

send a stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to 127

more data words. The EEPROM will respond with a “0” after each data word received.

The microcontroller must terminate the page write sequence with a stop condition (see

Figure 9 on page 11).

The data word address lower 7 bits are internally incremented following the receipt of

each data word. The higher data word address bits are not incremented, retaining the

memory page row location. When the word address, internally generated, reaches the

page boundary, the following byte is placed at the beginning of the same page. If more

than 128 data words are transmitted to the EEPROM, the data word address will “roll

over” and previous data will be overwritten. The address roll over during write is from the

last byte of the current page to the first byte of the same page.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-

ing a start condition followed by the device address word. The Read/Write bit is

representative of the operation desired. Only if the internal write cycle has completed

will the EEPROM respond with a “0”, allowing the read or write sequence to continue.

10 AT24C512

1116O–SEEPR–1/07

Read Operations Read operations are initiated the same way as write operations with the exception that

the Read/Write select bit in the device address word is set to “1”. There are three read

operations: current address read, random address read and sequential read.

CURRENT ADDRESS READ: The internal data word address counter maintains the

last address accessed during the last read or write operation, incremented by “1”. This

address stays valid between operations as long as the chip power is maintained. The

address roll over during read is from the last byte of the last memory page, to the first

byte of the first page.

Once the device address with the Read/Write select bit set to “1” is clocked in and

acknowledged by the EEPROM, the current address data word is serially clocked out.

The microcontroller does not respond with an input “0” but does generate a following

stop condition (see Figure 10 on page 11).

RANDOM READ: A random read requires a “dummy” byte write sequence to load in the

data word address. Once the device address word and data word address are clocked

in and acknowledged by the EEPROM, the microcontroller must generate another start

condition. The microcontroller now initiates a current address read by sending a device

address with the Read/Write select bit high. The EEPROM acknowledges the device

address and serially clocks out the data word. The microcontroller does not respond

with a “0” but does generate a following stop condition (see Figure 11 on page 11).

SEQUENTIAL READ: Sequential reads are initiated by either a current address read or

a random address read. After the microcontroller receives a data word, it responds with

an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to

increment the data word address and serially clock out sequential data words. When the

memory address limit is reached, the data word address will roll over and the sequential

read will continue. The sequential read operation is terminated when the microcontroller

does not respond with a “0” but does generate a following stop condition (see Figure 12

on page 12).

Figure 7. Device Address

AT24C512

1116O–SEEPR–1/07

Figure 8. Byte Write

Figure 9. Page Write

Figure 10. Current Address Read

Figure 11. Random Read

12 AT24C512

1116O–SEEPR–1/07

Figure 12. Sequential Read

AT24C512

1116O–SEEPR–1/07

Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics

tables.

2. “U” designates Green package + RoHS compliant.

3. Available in waffle pack and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please

contact Serial EEPROM marketing.

Ordering Information(1)

Ordering Code Package Operation Range

AT24C512C1-10CU-2.7(2)

AT24C512C1-10CU-1.8(2)

AT24C512-10PU-2.7(2)

AT24C512-10PU-1.8(2)

AT24C512W-10SU-2.7(2)

AT24C512W-10SU-1.8(2)

AT24C512N-10SU-2.7(2)

AT24C512N-10SU-1.8(2)

AT24C512-10TU-2.7(2)

AT24C512-10TU-1.8(2)

AT24C512Y4-10YU-1.8(2)

AT24C512U4-10UU-1.8(2)

8CN1

8P3

8S2

8S1

8A2

8Y4

8U4-1

Lead-free/Halogen-free/

Industrial Temperature

(–40°C to 85°C)

AT24C512-W1.8-11(3) Die Sale Industrial Temperature

(–40°C to 85°C)

Package Type

8CN1 8-lead, 0.300" Wide, Leadless Array Package (LAP)

8P3 8-lead, 0.300" Wide, Plastic Dual In-line Package (PDIP)

8S2 8-lead, 0.200” Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)

8S1 8-lead, 0.150” Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)

8A2 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP)

8Y4 8-lead, 6.00 mm x 4.90 mm Body, Dual Footprint, Non-leaded, Small Array Package (SAP)

8U4-1 8-ball, die Ball Grid Array Package (dBGA2)

Options

–2.7 Low-voltage (2.7V to 5.5V)

–1.8 Low-voltage (1.8V to 3.6V)

14 AT24C512

1116O–SEEPR–1/07

Packaging Information

8U4-1 — dBGA2

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

PO8U4-1 A

1/5/05

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

8U4-1, 8-ball, 2.47 x 4.07 mm Body, 0.75 mm pitch,

Small Die Ball Grid Array Package (dBGA2)

A 0.81 0.91 1.00

A10.15 0.20 0.25

A20.40 0.45 0.50

b 0.25 0.30 0.35

D 2.47 BSC

E 4.07 BSC

e 0.75 BSC

e1 0.74 REF

d 0.75 BSC

d1 0.80 REF

5. Dimension 'b' is measured at the maximum solder ball diameter.

This drawing is for general information only.

SIDE VIEW

TOP VIEW

8 SOLDER BALLS

BOTTOM VIEW

(e1)

A1 BALL PAD CORNER

(d1)

A1 BALL PAD CORNER

AT24C512

1116O–SEEPR–1/07

8CN1 – LAP

1150 E.Cheyenne Mtn Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

8CN1, 8-lead (8 x 5 x 1.04 mm Body), Lead Pitch 1.27 mm,

Leadless Array Package (LAP) B

8CN1

11/8/04

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A 0.94 1.04 1.14

A1 0.30 0.34 0.38

b 0.36 0.41 0.46 1

D 7.90 8.00 8.10

E 4.90 5.00 5.10

e 1.27 BSC

e1 0.60 REF

L 0.62 .0.67 0.72 1

L1 0.92 0.97 1.02 1

Note: 1. Metal Pad Dimensions.

2. All exposed metal area shall have the following finished platings.

Ni: 0.0005 to 0.015 mm

Au: 0.0005 to 0.001 mm

Pin1 Corner

Marked Pin1 Indentifier

0.10 mm

TYP

Top View

Side View

Bottom View

16 AT24C512

1116O–SEEPR–1/07

8P3 – PDIP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

01/09/02

8P3B

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA, for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

COMMON DIMENSIONS

(Unit of Measure = inches)

SYMBOL MIN NOM MAX NOTE

A2 A

4 PLCS

–

0.210 2

A2 0.115 0.130 0.195

b 0.014 0.018 0.022 5

b2 0.045 0.060 0.070 6

b3 0.030 0.039 0.045 6

c 0.008 0.010 0.014

D 0.355 0.365 0.400 3

D1 0.005

–

E 0.300 0.310 0.325 4

E1 0.240 0.250 0.280 3

e 0.100 BSC

eA 0.300 BSC 4

L 0.115 0.130 0.150 2

Top View

Side View

End View

AT24C512

1116O–SEEPR–1/07

8S2 – EIAJ SOIC

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

8S2, 8-lead, 0.209" Body, Plastic Small

Outline Package (EIAJ)

10/7/03

8S2C

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

5. Values b and C apply to pb/Sn solder plated terminal. The standard thickness of the solder layer shall be 0.010 +0.010/−0.005 mm.

A 1.70 2.16

A1 0.05 0.25

b 0.35 0.48 5

C 0.15 0.35 5

D 5.13 5.35

E1 5.18 5.40 2, 3

E 7.70 8.26

L 0.51 0.85

∅

0° 8°

e 1.27 BSC 4

End View

Side View

∅

Top View

18 AT24C512

1116O–SEEPR–1/07

8S1 – JEDEC SOIC

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TITLE DRAWING NO.

REV.

Note:

10/7/03

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

Small Outline (JEDEC SOIC) 8S1 B

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A1 0.10 – 0.25

These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.

A 1.35 – 1.75

B 0.31 – 0.51

C 0.17 – 0.25

D 4.80 – 5.00

E1 3.81 – 3.99

E 5.79 – 6.20

e 1.27 BSC

L 0.40 – 1.27

∅ 0° – 8°

∅

Top View

End View

Side View

AT24C512

1116O–SEEPR–1/07

8A2 – TSSOP

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

5/30/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 2.90 3.00 3.10 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A – – 1.20

A2 0.80 1.00 1.05

b0.19 – 0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

8A2, 8-lead, 4.4 mm Body, Plastic

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,

datums, etc.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the

b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between

protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

8A2 B

Side View

End View

Top View

123

Pin 1 indicator

this corner

20 AT24C512

1116O–SEEPR–1/07

8Y4 – SAP

1150 E. Cheyenne Mtn. Blvd.

Colorado Springs, CO 80817

TITLE DRAWING NO.

REV.

8Y4, 8-lead (6.00 x 4.90 mm Body) SOIC Array Package

(SAP) Y4 A

8Y4

5/24/04

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL

MIN NOM MAX NOTE

A – – 0.90

A1 0.00 – 0.05

D 5.80 6.00 6.20

E 4.70 4.90 5.10

D1 2.85 3.00 3.15

E1 2.85 3.00 3.15

b 0.35 0.40 0.45

e 1.27 TYP

e1 3.81 REF

L 0.50 0.60 0.70

EA1

PIN 1 INDEX AREA

PIN 1 ID

AT24C512

1116O–SEEPR–1/07

Revision History

Doc. Rev. Date Comments

1116O 1/2007 Revision history implemented.

Added Note to Page 1 recommending new device.

Printed on recycled paper.

1116O–SEEPR–1/07

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

Atmel Corporation Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Regional Headquarters

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Memory

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Literature Requests

www.atmel.com/literature

marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.