U62256ADK10LL - Alliance Memory, Inc.

U62256A

March 09, 2004 1 1

! 32768x8 bit static CMOS RAM

! Access times 70 ns, 100 ns

! Common data inputs and

data outputs

! Three-state outputs

! Typ. operating supply current

70 ns: 50 mA

100 ns: 40 mA

! TTL/CMOS-compatible

! Automatical reduction of power

dissipation in long Read Cycles

! Power supply voltage 5 V + 10 %

! Operating temperature ranges

0 to 70 °C

-40 to 85 °C

-40 to 125 °C

! QS 9000 Quality Standard

! ESD protection > 2000 V

(MIL STD 883C M3015.7)

! Latch-up immunity >100 mA

! Packages: PDIP28 (600 mil)

SOP28 (330 mil)

Standard 32K x 8 SRAM

Features

The U62256A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Read - Standby

- Write - Data Retention

The memory array is based on a

6-transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. In a Read cycle, the

data outputs are activated by the

falling edge of G, afterwards the

data word read will be available at

the outputs DQ0-DQ7. After the

address change, the data outputs

go High-Z until the new information

read is available. The data outputs

have not preferred state.

The Read cycle is finished by the

falling edge of W, or by the rising

edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Description

Pin Configuration

A14 VCC

A12 W

A6 A8

A5 A9

A7 A13

A4 A11

A3 G

A2 A10

DQ1 DQ5

A1 E

A0 DQ7

DQ0 DQ6

DQ2 DQ4

VSS DQ3

Top View

Signal Name Signal Description

A0 - A14 Address Inputs

DQ0 - DQ7 Data In/Out

EChip Enable

GOutput Enable

WWrite Enable

VCC Power Supply Voltage

VSS Ground

Pin Description

PDIP

SOP

U62256A

March 09, 2004

Operating Mode E W G DQ0 - DQ7

Standby/not selected H * * High-Z

Internal Read L H H High-Z

Read L H L Data Outputs Low-Z

Write L L * Data Inputs High-Z

Truth Table

Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decoder Row Decoder

Sense Amplifier/

Write Control Logic

Clock

Generator

Common Data I/O

Memory Cell

Array

512 Rows x

64 x 8 Columns

A10

A11

A12

A13

A14

*H or L

U62256A

March 09, 2004 3 3

Characteristics

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI,as well as

input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.

aStresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only,

and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect reliability

bMaximum voltage is 7 V

cNot more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Absolute Maximum Ratings aSymbol Min. Max. Unit

Power Supply Voltage VCC -0.5 7 V

Input Voltage VI-0.5 VCC + 0.5 bV

Output Voltage VO-0.5 VCC + 0.5 bV

Power Dissipation PD-1W

Operating Temperature C-Type

K-Type

A-Type

Ta0

-40

125

°C

Storage Temperature C/K-Type

A-Type

Tstg -65

-65

125

150

°C

Output Short-Circuit Current

at VCC = 5 V and VO = 0 V c| IOS | 200 mA

d-2 V at Pulse Width 10 ns

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Voltage VCC 4.5 5.5 V

Input Low Voltage d VIL -0.3 0.8 V

Input High Voltage VIH 2.2 VCC + 0.3 V

U62256A

March 09, 2004

Electrical Characteristics Symbol Conditions Min. Max. Unit

Supply Current - Operating Mode

Supply Current - Standby Mode

(CMOS level)

Supply Current - Standby Mode

(TTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

C-Type

K-Type

A-Type

VCC

= 5.5 V

= 0.8 V

=2.2 V

= 70 ns

= 100 ns

=5.5 V

= VCC - 0.2 V

= 5.5 V

= 2.2 V

µA

Output High Voltage

Output Low Voltage

VOH

VOL

VCC

IOH

VCC

IOL

= 4.5 V

= -1.0 mA

=4.5 V

=3.2 mA

2.4

0.4

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 5.5 V

= 0 V

-2

2µA

µA

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

=4.5 V

=2.4 V

=4.5 V

=0.4 V

3,2

-1 mA

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

=5.5 V

=0 V

-1

1µA

µA

U62256A

March 09, 2004 5 5

Switching Characteristics

Read Cycle

Symbol 07 10

Unit

Alt. IEC Min. Max. Min. Max.

Read Cycle Time tRC tcR 70 100 ns

Address Access Time to Data Valid tAA ta(A) 70 100 ns

Chip Enable Access Time to Data Valid tACE ta(E) 70 100 ns

Output Enable Access Time to Data Valid tOE ta(G) 35 45 ns

E HIGH to Output in High-Z tHZCE tdis(E) 25 35 ns

G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns

E LOW to Output in Low-Z tLZCE ten(E) 55ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

Output Hold Time from Address Change tOH tv(A) 55ns

Switching Characteristics

Write Cycle

Symbol 07 10

Unit

Alt. IEC Min. Max. Min. Max.

Write Cycle Time tWC tcW 70 100 ns

Write Pulse Width tWP tw(W) 55 70 ns

Write Pulse Width Setup Time tWP tsu(W) 55 70 ns

Address Setup Time tAS tsu(A) 00ns

Address Valid to End of Write tAW tsu(A-WH) 65 80 ns

Chip Enable Setup Time tCW tsu(E) 65 80 ns

Pulse Width Chip Enable to End of Write tCW tw(E) 65 80 ns

Data Setup Time tDS tsu(D) 30 35 ns

Data Hold Time tDH th(D) 00ns

Address Hold from End of Write tAH th(A) 00ns

W LOW to Output in High-Z tHZWE tdis(W) 25 35 ns

G HIGH to Output in High-Z tHZOE tdis(G) 25 35 ns

W HIGH to Output in Low-Z tLZWE ten(W) 00ns

G LOW to Output in Low-Z tLZOE ten(G) 00ns

U62256A

March 09, 2004

Data Retention Mode

E-Controlled

Data Retention

4.5 V

tDR trec

VCC

VCC(DR) ≥ 2 V

0 V

2.2 V

VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V

Data Retention

Characteristics

Symbol

Alt. IEC Conditions Min. Typ. Max. Unit

Data Retention Supply Voltage VCC(DR) 25.5V

Data Retention Supply Current ICC(DR) VCC(DR) = 3 V

VE = VCC(DR) - 0.2 V

C-Type

K-Type

A-Type

µA

Data Retention Setup Time tCDR tsu(DR) See Data Retention

Waveforms (above)

0ns

Operating Recovery Time tRtrec tcR ns

Test Configuration for Functional Check

A10

A11

A12

A13

A14

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VIH

VIL

VSS

VCC

5 V

960

30 pF1)

Input level according to the

relevant test measurement

Simultaneous measurement

of all 8 output pins

1)In measurement of tdis(E), tdis(W), tdis(G), ten(E), ten(W), ten(G) the capacitance is 5 pF.

510

U62256A

March 09, 2004 7 7

Package

D = PDIP28 (600 mil, only C/K-Type)

S2 = SOP28 (330 mil) Type 2

Example

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC

= 5.0 V

= VSS

= 1 MHz

= 25 °C

CI-7pF

Output Capacitance CO

-7pF

IC Code Numbers

S2U62256A 07K

All pins not under test must be connected with ground by capacitors.

The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digits indicating the year,

and the last 2 digits the calendar week.

Assembly location and trace code are shown in line 4.

Power Consumption

blank = Standard (only A-Type)

LL = Very Low Power (C/K-Type)

Internal Code

Access Time

07 = 70 ns

10 = 100 ns (only C/K-Type)

Operating Temperature Ranges

C = 0 to 70 °C

K = -40 to 85 °C

A = -40 to 125 °C

Type

U62256A

March 09, 2004

tdis(G)

tdis(E)

tcR

Previous Data Valid Output Data Valid

Output Data Valid

Address Valid

tsu(A)

High-Z

ten(E)

ten(G)

ta(G)

ta(E)

Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)

Read Cycle 2: G-, E-controlled (during Read Cycle: W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

DQi

Output

U62256A

March 09, 2004 9 9

Write Cycle1: W-controlled

th(D)

DQi

Input

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A)

tsu(D)

tdis(W) ten(W)

Address Valid

Input Data Valid

High-Z

tsu(A-WH)

Write Cycle 2: E-controlled

Input Data Valid

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E)

th(A)

tsu(W)

tsu(D)

tdis(W)

en(E)

High-Z

Address Valid

tdis(G)

L- to H-level undefined H- to L-level

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design reserved.

U62256A

Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de

March 09, 2004

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which the

failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum Mikro-

elektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information and shall

not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. The infor-

mation in this document describes the type of component and shall not be considered as assured characteristics.

ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This docu-

ment does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.