DM93L14 - Fairchild Semiconductor

June 1989

Revised November 1999

DM93L14 Quad Latch

DM93L14

Quad Latch

General Description

The DM93L14 is a multifunctional 4-bit latch designed for

general purpose s torage appli cations in high speed digital

systems. All outputs have active pull- up circuitry to provide

high capacitance drive and to provide low impedance in

both logic states for good noise immunity.

Features

■Can be used as single input D latches or set/reset

latches

■Active low enable gate input

■Overriding master reset

Ordering Code:

Logic Symbol

VCC = Pin 16

GND = Pin 8

Connection Diagram

Pin Descriptions

Order Num b er Packa ge Numbe r Packag e Descr ip tio n

DM93L14N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

EEnable Input (Acti ve LO W)

D0 − D3 Data Inputs

S0 − S3 Set Inputs (Active LOW)

MR Master Reset Input (Active LOW)

Q0 − Q3 Latch Outputs

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DM93L14

Functional Description

The DM93L14 consists of four latches with a common

active LOW Enable input and active LOW Master Reset

input. When the Enable goes HIGH, data present in the

latches is stored and the state of the latch is no longer

affected by the Sn and Dn inputs. the Master Reset when

activated overrides all other input conditions forcing all

latch outputs LOW. Each of the four latches can be oper-

ated in one of two modes:

D-TYPE LATCH—For D-type operation the S input of a

latch is held LOW. While the common Enable is a ctive the

latch output foll ows the D input. I nformation present a t the

latch output is stored in the latch when the Enable goes

HIGH.

SET/RE SET L ATCH —During set/rese t oper ation w hen th e

common Enable is LOW a latch is reset by a LOW on the D

input, and can be set by a LOW on the S input if the D input

is HIGH. If both S and D inputs are LOW, the D input will

dominate and the latch will be reset. When the Enable

goes H IGH, the latch re mains in the last state pr ior to d is-

able ment. The two modes of la tch operati on are shown in

the Truth Table.

Truth Table

H = HIGH Voltage Lev el

L = LOW Voltage Level

X = Immaterial

Qn−1 = Previo us Output St ate

Qn = Present Output State

Logic Diagram

MR EDSQnOperation

HLLLLD Mode

HLHLL

HHXXQ

n-1

HLLLLR/S Mode

HLHLH

HLLHL

HLHHQ

n-1

HHXXQ

n-1

L X X X L RESET

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DM93L14

Absolute Maximum Ratings(Note 1) Note 1: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be gu aranteed. Th e device shou ld not be

operated at these limits. The parametric values defined in the Electrical

Char ac teristi c s tables are not guar anteed at t he ab s olute maxi m um ratings.

The Recommended Operating Conditions table will define the conditions

for actu al device operation.

Recommended Operating Conditions

Supply Voltage 7V

Input Voltage 5.5V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.5 5 5.5 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.7 V

IOH HIGH Level Output Voltage −400 µA

IOL LOW Level Output Current 4.8 mA

TAFree Air Operating Temperature −55 125 °C

tS (H) Setup Time HIGH or LOW 10 ns

tS (L) Dn to E20

tH (H) Hold Time HIGH or LOW 0 ns

tH (L) Dn to E10

tS (H) Setup time HIGH, Dn to Sn15 ns

tH (L) Hold time LOW, Dn to Sn5ns

tW (L) E Pulse Width LOW 30 ns

tW (L) MR Pulse Width LOW 25 ns

tREC Recovery time, MR to E5ns

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DM93L14

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 2: All typical s are at VCC = 5V, TA = 25°C

Note 3: Not more tha n one out put shoul d be shorte d at a t im e, and the duration sh ould not ex c eed one s ec ond.

Note 4: ICC is measu r ed with all out puts ope n and all inpu ts grounded.

Switching Characteri stics

VCC = +5.0V, TA = +25°C (See Waveforms and Load Configurations)

Symbol Parameter Conditions Min Typ Max Units

(Note 2)

VIInput Clamp Voltage VCC = Min, II = −10 mA −1.5 V

VOH HIGH Level Output Voltage VCC = Min, IOH = Max, 2.4 V

VIL = Max, VIH = Min

VOL LOW Level Output Voltage VCC = Min, IOL = Max, 0.3 V

VIH = Min, VIL = Max

IIInput Current @ Max VCC = Max, VI = 5.5V 1mA

Input V oltag e

IIH HIGH Level Input Current VCC = Max, VI = 2.4V Inputs 20 µA

Dn30

IIL LOW Level Input Current VCC = Max, VI = 0.3V Inputs −400 µA

Dn−600

IOS Short Circuit VCC = Max −2.5 −25 mA

Output Current (Note 3)

ICC Supply Current VCC = Max (Note 4) 16.5 mA

Symbol Parameter Min Max Units

tPLH Propagation Delay 45 ns

tPHL E to Qn36

tPLH Propagation Delay 30 ns

tPHL Dn to Qn30

tPLH Propagation Delay, MR to Qn30 ns

tPHL Propagation Delay, Sn to Qn33 ns

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DM93L14 Quad Latch

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N14A

Fairchild does not assume an y responsibility for u se of any circuitry d escribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r syst ems are dev ic es or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A crit ical componen t in any com ponen t of a life s uppor t

device or system whose failure to perform can be rea-

sonabl y e xpec ted to cause th e fa i lure of the l ife s upport

device or system, or to affect its safety or effectiveness.