1/50
THE ST9 MCU FAMILY
PRODUCT OVERVIEW
The ST9 8-16/BIT MCU Family: I nnovative Solutions For Embedded Control.
The rapidly growing area of real-ti me applications represents one o f the most ex acting oper-
ating environments for today’s microcontrollers. Processors are required to execute complex
control algorithms, within a defined minimum response time. With the increasi ng complexity of
embedded control applications, a significant increase in CPU performance and peripheral
functionality over conventional 8-bit controll ers is required.
Designed to meet m arket needs for cost-effective, high performanc e MCUs, the ST9’s family
bridges the gap with the worlds of 8 and 16-bit microcontrollers and covers a l arge range of re-
quirements in the high-end 8-bit and low-end 16-bit applications . With an S T9 mi crocontroller
you hav e the 16-bit perfor mance (sophistica ted data m a nipulation, real ti me e vent handl ing)
and the 8-bit advantages (price, noise, power consumption,...).
With the ST9 family, STMicroelectronics offers si gnific ant performance and flexi bility advan-
tages over traditional 8-bit microcontrol lers: it is the unequalled solution for more performance.
It provides innovative answers to yours embedded control requirements with competitive MCU
solutions for today and tomorrow.
The ST 9 family i s one of t he mos t powerful range of 8/16-bit M CUs av ailable on the market.
You combine the performance of a 16-bit microcontroller with the cost of a 8-bit microcon-
troller, thanks to a unique set of benefits.
ST90E182 MCU with on-chip HDLC ST90E158 general purpose MCU
1
2/50
Table of Contents
ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CTRL. . . 1
1 THE ST9 REGISTER BASED CORE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.1 DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.2 BENEFITS OF THE REGISTER BASED ARCHITECTURE . . . . . . . . . . . . . . . 12
1.3 THE ST9 REGISTER F ILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3.1 Reduced code size with working register concept . . . . . . . . . . . . . . . . . . . . . . . . . . 14
1.3.2 Quick peripheral access with paging mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.3.3 Fast contex t switching thanks to working registers and re giste rs pointers . . . . . . . 15
1.4 MEMORY ORG ANISATION AND MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1 Memory description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.2 Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.3 External me mory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.5 INTERRUPT MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.1 Interrupt management description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.2 A powerful system for real t ime applica tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.5.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.5.4 Interrupt priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.6 DIR ECT MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.1 Direct Memory Access description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.6.2 High sp eed system perform ance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.3 DMA priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.6.4 The S WA P mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7 INSTRUCTIONS SET AND ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . 27
1.7.1 Overvi ew of Instructions Set and Addre ssing Modes . . . . . . . . . . . . . . . . . . . . . . . 27
1.7.2 High sp eed compu tation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.3 Effect ive high level language suppo rt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.4 Addre ssin g modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.5 A good alternative to more costly 16-bit MCUs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.8 S T9 OPERA TIN G MOD ES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2 PERIPH ERALS AN D I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.1 FLEXIBLE I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2.2 TIM ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.1 Standard Ti me r (STIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2.2.2 Watchd og T imer (WDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
2.2.3 Multifunction ti mer (MFT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1
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Table of Contents
2.3 FAST ANALOG TO DIGITAL CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . 39
2.4 S ERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
2.4.1 Un iversal Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.4.2 Comprehensive seri al communica tion Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . . 42
3 DEVELOPME NT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1 S OFTWARE TOOLS: GNU C TOOLCHAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.1.1 GNU C com pile r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1.2 Assembler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1.3 Linker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.1.4 De bugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 HARDWARE TO OLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.1 Real-time developm ent tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
3.2.2 EPR OM program ming boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2.3 Gang P rogram mer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
1
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
4/50
Figure 1. A un iqu e set of benefit for real-time embedded control
The pe rform ance of th e ST9 m icroc ontroller derives from it s arch it ecture. You h ave a Reg -
ister-File based c ore op timize d for sophisticated data mani pulation and r eal-time event han -
dling, to ge the r wi th a r a nge of app licat io n-aw are i nte llige nt perip hera ls hav ing t he po w er to
carry out most tasks with the minimum process o r overhead.
In the S T9, the intelligenc e is distribute d b etween th e core and i ts p eriphera ls . T he core in-
cludes t he Central Proc essing Unit (CPU), the Register File, the interrupt and Direct Memor y
Access ( DMA) controller, and the Memory Man ag ement Unit (MM U). The MM U allows ad-
dressi ng of up to 4 Megabytes of pr ogram and data mapped i nto a single linear space. Ins truc-
tions have been added to facilitate large program and data handling through the MMU, as well
as to i mprove the performance and code density of C Function calls. 14 addr ess ing modes are
avai lable, includ in g pow e rful i ndire ct ad dr ess ing c apabi litie s. Th e m ana gem ent of th e stack
which is divided into a system stack for interrupts and subroutine calls and a user s tack pro-
vide optimized support for C language.
16-BITPERFORMANCE
WITH 8 -BI T P R IC E
O PT IMI ZE D FOR C
LANGUAGE
MEMORY MANAGEMENT
UNIT
COMPLETE DEVELOPMENT
ENVIRONMENT
B ROAD FA MIL Y OF
STANDARD AND
APPLICATION SPECIFIC MCU
THE RIGH T DEVICE
FOR EACH
APPLICATION
REQUIREMENTS
COST EF FECTIVE
SOLU TIONS FOR
REAL-TIME
APPLICATIONS
16K TO 128K
ON-CHIP
PROGRAM
MEMORY
4 MEGA BYTES
ADDRESS
RANGE
5/50
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
When you compare different microcontrollers, you can estim ate the relative computing power
of the core, and also of the p eripher als (if they include some int ellige nce) . In some ar chi tec -
tures, th e periph erals make heavy u se of the co re an d thus ta ke up a p art of its c omput ing
pow er. Ma ny m icrocon trollers a vailab le on t he mar ket have a r elativ ely p owerf ul co re, sur-
rounded by very simple per ipherals. This approach has the advantage of making the periph-
erals easy to use and confi gure but at the expense of the overall computing power and system
management capability.
The ST9 is an example of a radi cal ly different compromise. Its core is comparable to the best
8-bit microprocessors on the market, and it boats an impressive speed, (m ore than five in-
structi ons per mic rosecond). It is assisted (rather than just surr ounded) by peripheral blocks of
which most can per form compl ex tasks without the intervention of the core. The net result is a
powerful machine that can even perform impress ive tasks just using its peripherals.
Figure 2. 16-bit performance with 8-bit cost and flexibility
8 BIT CORE
ST9 8/16 BIT CORE
16 BIT CORE
PERIPHERALS
INTERRUPT
&
DMA
SMART
PERIPHERALS
INTERRUPT
8-bit
MCU
System management
capabilities
16-bit
MCU
ST9
8/16-bit
MCU
PERIPHERALS
8-bit16-bit
Co re co mp l e x it y
INTERRUPT
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
6/50
The ST9 family covers a large range of Ma rk ets. ST 9 MCU devices fit in a range of applica-
tions from automotive to industrial, consumer and computer.
Figure 3. A broad range of applications
With their large set of peripherals and memory variants, the ST90158 and ST90135 family
members integrate every functionality needed to control a large range of real time systems.
Figure 4. The ST90135/158 family of high performance 8/16- bit M CU
CONSUMER
- TELEVISION
- CAR RADIO
INDUSTRIAL
- MOT OR CO NTROL
- MET E RING
- ALA RM
- TO LL I NG
- ACCESS CONTROL
- PO INT OF SA L ES
- IN ST RU M EN TA TI ON
AUTOMOTIVE
- SAFETY
- ANTI THEFT
- BODY ELECTRONICS
- POW ER TR AIN
COMPUTER
- PRINTER
- HUB
- MONITOR
ST90E158M9/
ST90T158M9 ST90158M9 ST90158M7 ST90135M6 ST90135M5 ST90135M4
ROM
64K
EPROM/OTP 64K 48K 32K 24K 16K
RAM
2k 2K 1.5k 1k 768 512
Timer 16b
3MFT + 1STDT 3MFT + 1STDT 3MFT + 1STDT 2MFT + 1STDT 2M FT +
1STDT 2M F T +
1STDT
Watchdog
HW/SW HW/SW HW/SW HW/SW HW/SW HW/SW
SCI
2 2 2 1 1 1
SPI
1 1 1 1 1 1
ADC
8 x 8-B IT 8 X 8-BI T 8 X8 -BIT 8 X 8-BIT 8 X 8-BI T 8 X 8-BIT
I/Os
72/67 72/67 67 67 67 67
Package
PQFP80 PQFP80 PQFP80 PQFP80 PQFP80 PQFP80
Lar
g
e peripheral set
Memor
y
sizes from 16K TO 64K
Pin-to-pin compatible devices
PQFP80 14x20mm
7/50
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
Figure 5. A growing MCU family
Other family members include or wil l s oon include multi purpose as well as appli cati on specific
devices designed for Automotive (CAN, J1850), Consumer (TV), Computer (Monitors,
USBus), Industrial (Motor Control, Electronic Tolling and Access Contro l) systems.
Figure 6. ST 9 selection list
*) S ee appl ication sp ecific product overviews
ST9 Famil y ROM RAM Periphe ral s Packag e Target Market
ST90135 16/24/32K 512/
768/
1K
SPI, SCI, 3 Timers,
Watchdog, ADC PQFP80 Consumer, Automotive,
Industrial , Telecom
ST90158 48/64K 1.5K/2K SPI, 2 SCIs, 4 Tim ers,
Watchdog, ADC PQFP80 Consumer, Automotive,
Industrial , Telecom
ST90182 6K/24K 256/768 2/3 Timers, HDLC, SPI,
SCI, A/D TQFP64 Electr onic Tolling,
Access Control
ST92 R195 *)
ST92 195 *) ROMLess
32K/64K 8K/
12K OSD, Teletext SDIP56 TV Applications
ST9216x*) 6/8/16K 256/
512/
1.5K
USB HUB, USB Func-
tions, Watchdog, PLL,
ADC, SCI, Timers
TQFP64/
SDIP56/
SDIP42/
SO34
USBus HUB
US Bu s PC Peri p hera ls
ST92175*) 60/96/128K 2/2.5/3K Timers, Sync Proces-
sor, SCI, I2C/DDC,
PWM, A/D
SDIP56,
TQFP64 Monitors
1998 1999
ST92175
MONITOR
ST9216X
USB
ST92R195/
ST92195
TV
ST90182
TOLLING/
ACCESS CONT R OL
ST90135/158
16K TO 64K ROM
MULTI PURPOSE
ST92F120
24K to 128K FLASH +
EEPROM
MULT I PURPOSE
ST92R130
ROMLESS
ST9-MC
AC MOTOR CTL
ST92F1XX
CAN 2.0B ACTIVE
ST92F1XX
J1850
Exist. Devt. Plan.
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
8/50
Thanks to the ST9’s modular architect ure and the unique core technology, you can easily up
or downgr ade withi n the same pr oduct fami ly keepin g softw are inves tment. You can choo se
the right device for the right task, at the right price fr om a broad product folio.
Figure 7. ST 9 modular architecture
In addition, the ST9 can be easily customized to speci fic requir ements of high volume appli ca-
tions
ST9 devices are manufactured using state of the art technology, allowing l ow power consump-
tion, maximum performanc e, cos t efficiency and reliability.
Figure 8. Competit ive technologies for today and tomor row
REGISTER BUS/INTERRUPT-DMA BUS
MEMORY BUS
DEDICATED
PERIPHERALS
STANDARD
PERIPHERALS
CPU
CORE
RAM
EPROM
EEPROM
ROM
16 BIT
SLICE TIMER
SCI
A/D CONVERTER
I/O PORTS
MULTI-FUNCTION
TIMER
ON-SCREEN
DISPLAY
DATA SLI CER
SPI
TIMER-WATCHDOG
EPROM
ROM
FLASH +
EEPROM
EPROM
ROM
ROM
FL ASH +
EEPROM
16 M Hz 25 MHz 40 MHz
0.6µm 0.5µm 0.35µm
2000-
1999-
1998-
1997-
9/50
THE ST9 8-16/BIT MCU FAMILY: INNOVATIVE SOLUTIONS FOR EMBEDDED CONTROL.
The ST9 family of MCUs is supported by a comprehensive range of development tools: a soft-
ware pa ckage ( C-comp iler, as se mble r, linke r, archive r, debugg er, Re al Ti me Kern el) and a
set of hardware tools (emulators, programm ers).
Figure 9. A complete development environment
HARDWARE
DEVELOPMENT
SYSTEM
HIGH LEVEL
DEVELOPMENT
SOFTWARE
COMPREHENSIVE
DOCUMENTATION
AND TECHNICAL
SUPPORT
HIGH PERFORMANCE
REAL TIME
EMULATOR
EFF EC TIVE APPLI CATION
DEVELOPMENT
MAINTA INING
OR PORTING
SECURED DEVELOPME NT
OF SOPHISTICAT ED
APPLICATIONS
THE ST9 REGISTER BASED CO RE
10/50
1 THE ST9 REGIST ER BASED CORE
1. 1 DESCRIPTION
Figure 10. ST9 cor e block diagram
The ST9 core consists of:
- the Central Processing Unit with a 8 bit Arithmetic Logi c Unit, the brai n of the sy stem that
processes all data and their movements along the bus
- the Register File, a set of 256 r egisters including:
224 general pur pose regi sters availabl e as 8 or 16- bit accumulators, i ndex r egisters or
address pointers
16 system registers (stacks point ers , flags, mode, interrupt,...)
64 pages of 16 paged regi sters each for Peripheral management (general ly , one page
for each peripheral)
- a Memory Management Unit which allows the addressing of up to 4 Mbytes of program and
data mapped into a single linear space
- 6-bit In ter rupt and D MA bus connected at each peripheral for Interrupt and to the SCI, MFT,
I2 C and USB for DMA
MMU
Memory
Management
Unit
INTERRUPT and DMA 6-BIT BUS
REGISTER
FILE AND DMA
INTERRUPT
BUS LO GIC PROGRAM
COUNTER
SYSTEM STACK
POINTER
USER STACK
POINTER
ALU
8/16 BIT
8-BIT DATA AND 16-BIT ADDRESS BUS
REGISTER DATA 8-BIT BUS
REGISTER ADDRESS 8-BIT BUS and PAGE 6-BIT BUS
INTERNAL ADDRESS 16-BIT BUS
11/50
THE ST9 REGISTER BASED CORE
The ST9 core ha s an u nique and po werfu l s tructure . Its architectur e is built aroun d a se t of
registers called Reg ister File. This al lows efficient bit, byte and word data handling and sup-
ports high level languages more efficiently than traditional accumulator machines.
Figure 11. Re gister F ile str ucture
The Direct Memor y Acces s and the multiple priority Interrupt Controller fu rth er increase
ST9 capability of effectively managing sophisticated real time, task and communication inten-
sive applications.
0
15
UP TO 64 PAGES
FOR PERIPHERALS
AND I/O PORTS
CONTROL
GENERAL
REGISTERS
PURPOSE
224
F
E
D
C
B
A
9
8
7
6
5
4
3
PAGED REGISTERS
S YSTEM REGISTERS
2
1
0
WORKI NG BANK 1
16 x 8-BIT OR 8 x 16-BIT RE GISTERS
W ORKING BANK 2
ACT I V E PA GE
PAGE AND
SYSTEM
POIN TERS
THE ST9 REGISTER BASED CO RE
12/50
1. 2 BENEFITS OF THE R EGISTER BASED ARCH ITECTURE
The usual microprocessor core structure is based on an accumulator . The accumulator is the
one register that h olds the data to work on and th e results of the ari thmetic or logica l opera-
tions appli ed to it. This st ructure has become a classic for i ts simplicity, the i nternal data paths
of the mi croprocessor all converge to the ac cumulator. The i nstruction set i s simple, since y ou
need to specify only one memory address in a data move instruction, the other being implicit:
the accumulator itse lf.
The simplicity has its own drawbacks: the accumulator is the computation bottl eneck, since to
move data fr om one place in memory to another place, you have to do it through the accumu-
lator. The s implest tr ansfer invol ves at least two instructions: one to get the data, the other one
to store it.
Registe r orie nted models, in contrast, allow you to mov e data dire ctly from one place to an-
other in a single instruction as illustrates the example below.
Figure 12. Example of 8-bit memory-memory transfer
Data can come from a r egister or from a memory address and can go to either to a regi ster or
a memory address. You can code the addresses in the instruction, or stor e them in registers
referenced by the ins truction. Th is all ows you to optimize y our code by c hoosing to store fre-
quently used data in registers, leaving l ess frequently used data in mem or y.
The register bas ed arc hitecture allow s to save execution time and code li nes bec ause there
are less s ave and resto re operati ons of data and pointers.The ex ample hereaf ter s hows the
difference between the two archi tectures when you want to add two 8-bit ope rands from
memory and to store the result in memory.
Content of rr6
Content of rr4
DATA
MEMORY
ld (rr4), (rr6) --> 3 bytes --> 0.64 µs (1) ldaa [D, x]
(2) staa [D, x] --> 4 bytes --> 1.37 µs
REGISTER BASED ARCHITECT URE
ST9, 25 MHz internal ACCUMULATOR BASED ARCH ITEC TUR E
68HC12, 8 MHz internal
MEMORY
ACCUMULATOR A
(2)
(1)
DATA
13/50
THE ST9 REGISTER BASED CORE
Figure 13. Example of two 8-bit memory oper and s add ing
The advantage of register based architectur e is ob vious in number of line and byte and in ex-
ecution time.
1.3 THE ST9 REGISTER FI LE
The ST9 has a special addressing space for registers, providing 256 different register ad-
dresse s. T his larg e amount of regi sters gives yo u consid erable flexib ility in alloca ting varia-
bles . Register addr ess es are coded using one byte. You can use any of these regi ster s to hold
data or as a pointer either to other registers or to bytes in memory.
Figure 14. ST 9 Reg ist er File organization
ST9
16-BIT
ACCUMULATOR
MACHINE
CODE BYTES EXECUTION TIME
add (rr), (rr)
(1 6-bit i ndirect) 30.56 µs
ldaa [D, x]
adda [D, y]
sta a [D, x]
MICROCONTROL LE R
68HC12
2
2
2
750 ns
750 ns
625 ns
2.12 µs
6
(16-bit indexed)
AR CHITECTURE INTE RNAL CLOCK
SPEED
8/16-BIT
REGISTER
MACHINE
8 MHz
25 MHz
PAGE REGISTERS
FOR PERIPHERAL MANAGEMENT
SYSTEM
GROUP
R223
R240
R255 PAGED
REGISTERS
GROUP 0
GROUP 1
GROUP F
GROUP E
GROUP N
R0
R15
R16
224 GENERAL PURPOSE REG ISTERS:
- Accumulator (destination of operation)
- 8 or 16-bit register
- Pointer for indirect addressing mode
- Wor ki ng regis te r
REGISTE R FILE
MULT IFUNCTION TIMER
A/D CONV ERTER
SCI
SYSTEM REGISTERS:
- St ack pointe rs (us er and s yste m)
- Working register and page pointers
- Mode register, Flag register
THE ST9 REGISTER BASED CO RE
14/50
1.3. 1 Reduced code size with workin g regist er concep t
To further improve coding effi ciency, a special mechanism has been c reated: the c oncept of
working register . This mechanism is a short di rect addressing mode which provides faster ex-
ecution and more compact c ode. It reduces to just 16 bytes the register space accessible by
the instructions in the so-called working register addressing mode. Only four bits ar e required
to addres s this space, allowing both the source and the destination of a data move to be coded
in a single byte, thus saving both code siz e and executio n time.
Figure 15. Example of working reg ister profits
Working regi ster me chanism is m andator y for bi t manipul ation in struction, to us e register as
pointer in most indir ect addressing modes, for multiply and divide instructions.
Figure 16. Example of working reg ister use
OPCODE EXECUTION TIME
CODE SIZE
3 bytes 240 ns
INSTRUCTION FORMAT
2 bytes 160 ns
CP r, r
CP R, R
[ opc ] [dst | src]
[ opc ] [ src ] [ dst ]
Re gi st er f i le
Syst em G r oup
Blo ck 3
Blo ck 2
Blo ck 1
Blo ck 0
R0
R255
R15
R7 Group 0
Gr ou p D
Block 17
Block 16 Group 8
Gr ou p 1
Blo ck 31
Blo ck 30
Blo ck 27
Blo ck 26
Group F
R224
RP0
r15
r14
r13
r12
r11
r10
r9
r8
r7
r6
r5
r4
r3
r2
r1
r0
Gro up 8
R143
R142
R141
R140
R139
R138
R137
R136
R135
R134
R133
R132
R131
R130
R129
R128
bres r4.6
ld (r3), #12
mul rr10, r5
srp #16
working
block
choice
use of any of
the 16 r egist ers
15/50
THE ST9 REGISTER BASED CORE
1.3. 2 Quick peripheral access with paging mechani sm
All internal peripherals are mapped into the register space and you can access them with a 8-
bit fast bus. Most of them have a multitude of features and can be configured in different ways.
This implies that they have a large num ber of r egister s. Since only the last gr oup of 16 regis-
ters is allocated for peripherals, a spec ial s cheme must be used to overcome this pr oblem. It
is called paging.
The last group of r egisters actually address es one pack of 16 registers that belongs to the pe-
ripheral it se lf . Which pack o f w hich peripheral depend s on t he va lu e of a register ca lled t he
Page Pointer Regi ster . There can be as many as 64 different pages, providing plenty of space
for accessing peripherals.
Though the handling of the peripheral page requires extra bytes, the 8-bit ST9 r egister fil e ad-
dress bus allows t o save overall execu tion time and keep s oftware c ompat ibilities betw een
devices with different peripheral set.
1.3.3 Fast context switching thanks t o working registers and regis ters p ointers
Another benefit of the ST9 Register File is the capability to effect ively switch context upon
asynchronous events by sim ply pointing to a new active page and bank after sav ing the cur-
rent values in the stack.
The working regist ers offer a wor kspace of 16 bytes. This is sufficient for m ost applications,
and much more convenient than a single accumulator. However, in some applications, this is
still not enough. In this case you can easil y allocate more than one register group to a partic-
ular program module. Since any register can be accessed directly, it is up to you to decide
whether you want to switc h working register gr oups or not to access the other groups of reg-
isters.
Since changing the current group involves only one instruction, t he concept of working r egis-
ters can greatly reduce con te xt switch ing t ime , for ex ample in the case of an interrupt
service routine. Doing this preserves the contents of the whole group, and the reverse opera-
tion restores them, as in the example below which shows the r ecepti on of a character from the
Serial Interface.
While the critical parameters of the event are managed in a reserved “SCI working bank”, the
key parameters of the inter rupted task (the cor e program or another i nterrupt routine of lesser
priority) are left untouched i n the “Core working bank ”. Then c ritical information for core pro-
gram or routines remain in the register file. Only register and page pointers need to be
stacked. Once the i ncoming character has been managed, the poi nter s in the sy stem bank are
restored to their previous value and the interrupted task is resumed, resulting in minimum data
manipulation and maximum execution speed.
THE ST9 REGISTER BASED CO RE
16/50
Figure 17. Example of reading one character from SCI
Supposing you could not switch working registers, you could have to push 16 bytes to the
stack to ensure that the contents of the working area have been preserved, and pop them
back before returning. O bviously the example abov e is more effi cient, both in code and data
memory size, and also in execution time.
SCI Interrupt
1.8 µs
MAX INST.
CORE PROGRAM
CORE PROGRAM
F
E
PAGED REGISTERS
SYSTEM REGISTERS
CORE W ORKING
BANK
SCI WO RKING
BANK
SCI PAGE
CORE PAGE
1
3
32
;
KEEP TRACK O F CURRENT G RO UP
PUSHW RPP ;SAVE REGISTER POINTER (1)
PUSH PPR ;SAVE PAGE POINTER REGISTER (2)
;
SWITCH TO A NEW G ROUP
SRP #SCI_BANK ;SET SCI PAGE AND BANK (3)
SPP #SCI_PG
;
BODY OF THE INTERRUP T SERVICE ROUTINE
;PERFO RM CHARA CTER
;MANAGEMENT WITHIN
;THE NEW A CTIVE
;REGIST ER BANK
;
RESTORE WHATEVER GROUP WAS ACTIVE
P0P PPR ;RESTORE REGISTER POINTER
P0PW RPP ;RESTO RE PAG E POINTER RE GISTER
IRET ;
RETUR N FRO M SU BRO UTINE
17/50
THE ST9 REGISTER BASED CORE
1.4 MEMORY ORGANISATION AND MANAGEMENT
1.4.1 Memory descripti on
The ST9 devices provides two di fferent address spaces : the Register File and a single linear
Memory Spac e acc ommodating both program and data.
Figure 18. ST9 memo ry organization
The Register File draws its power fr om its size: 256 registers of w hich 224 are unc om mitted,
and from the fact that it can hold data pointers to data that reside in any of the two spac es.
All of the physically separ ate memory areas, including the i nternal ROM, internal RAM and ex-
ternal memory are mapped in the common address space which is the Mem ory Spac e. A
total addressable memory space of 4 M bytes is available. This address space is arranged as
64 segments of 64 Kbytes. Each segment is further subdivided in to four pages of 16 Kbytes,
as illustrated in figur e hereafter.
REGISTER FILE
240 bytes + 16xN b of periph. + I/O
MEMORY SPACE
PROGRAM
AND
DATA
MEMORY
ROM
EPROM
EEPROM
FLASH
RAM
Up to 4 Megabytes
R255
R0
PAGED REGISTERS
SYSTEM GROUP
Up to 64 pages
224
REGISTERS
THE ST9 REGISTER BASED CO RE
18/50
Figure 19. Memory Space org aniz a tion
1.4.2 Memory Management Unit
1.4.2.1 4 Mbytes of add ress sp ace with the MMU
The ST9 Core includes a Memory Management Unit (MMU) which allows the addressing
space to be extended to 4 Mbytes.
The MMU is c ontrolled by 7 r egisters . These r egisters may be sub- divided into 2 mai n groups:
a first group of four 8- bit registers (DPR0-3) used to extend the address during Data Memory
access, and a second group of three 6-bit registers (CSR, DMASR, ISR ) used to manage Pr o-
gram and Dat a Memo ry ac cesse s d urin g Co de exec ution, In terrupt s, an d DM A servic e rou -
tines.
To manage 4 M bytes of ad dressing space it is necessary to have 22 address bits. The MMU
adds 6 bits t o the us ual 16 -bit add ress , thus trans lating a 16 -bit virtua l add ress i nto a 22- bit
physical address. There ar e 2 different ways to do this depending on the memory involved and
on the operation being performed.
4 Mbytes Total
Address Space
64 Kbytes
Address 16K Data Page 64K Code
Segment
Pa ge d,
managed by
4 pointer s
Se gm en te d,
managed
through
instructions
19/50
THE ST9 REGISTER BASED CORE
Figure 20. Add ressing via MMU regist ers
1.4.2.2 Interests of MMU usage
In typical microcontroller applications, less than 16 Kbytes of RAM are used, so j ust one of the
four Data space pages is normally sufficient. It may be useful however to map part of the ROM
into the data space if it contains strings, tables, bit maps, etc.
The Management Memory Unit l ets interrupt service routines ac cess the whole 4-Mby tes ad-
dress space. The drawback is that the interrupt response time is slightly increased, because of
the need to also save special register on the stack.
Thanks to M MU, a DMA which uses two different registers for Program memory and Data
memory accesses w ill alw ays find its memo ry segment(s), no matter what segment changes
the application has performed.
1.4.3 External memory interface
In the event of an appl ication requiring more ROM space than available on-chip, or for easier
program management and customization with external memory or peripherals, the ST9 mi cr o-
controller supports an ex ternal memory interface on s ome dev ices. The e xternal mem ory in-
terface provides th e memor y lines and t iming and status contr ol signals, plus enhanc ed fea -
tures including pr ogrammabl e memory wait cycles, bus request/acknowledge cycles and
shared memory bus acces s control.
The S T9 M em ory Control Unit au tom atically reco gnizes i f a m em ory location belongs to on-
chip memory or not and works accordin gly.
16-bit virtual address
22-bit physical address
6 bits
MMU registers
THE ST9 REGISTER BASED CO RE
20/50
1. 5 INTERR UPT MAN AGEME NT
1.5.1 Interrupt m anagement description
The ST 9 devices respond to, and control peripheral events and external ev ents through their
interrupt channels. W hen such an ev ent occurs, if previously enabled and according to a pri-
ority mec hanism, the current program execu tion ca n be suspend ed to allow the ST 9 to exe-
cute a specific response routine. If the event g enerates an interrupt request, the curr ent pro-
gram status is saved after the curr ent ins truction is completed and the CPU control passes to
the Interrupt Service Routine.
The S T9 CPU c an rec eive requ ests from the fo llowing typ e o f sou rces : on- chip pe ripherals,
external pins, top level non maskable interrupt.
Up to ei ght exter nal i nterrupt channels, with programmable input trigger edge, are available. In
addition, a dedicated interrupt c hannel, set to the Top- level priority , c an be devoted e ither to
the external pin NMI (to provide a Non -Ma skable-Interrupt) or to the Watchdog Tim er. In ter-
rupt service routines are addressed through a vector table mapped in Program Memory. This
Interrupt vector table, up to 128 vectors, allows additional peripheral s for m o re modularity.
1.5. 2 A powerful system for real time ap pli cation s
To achieve maximum performance, the ST9 family offers a powerful solution to the response
requirements of real time systems with its adv anced interrupt structure. The interrupt system
allows yo u to h and le v arious asy nchrono us event s and t o b uild v ery effici ent pr og rams w ith
excellent interrupt response t imes. With a ma ximum interrupt response time o f 1,88 µ s, the
ST9 family is particularly suited for real ti me applications.
Figure 21. Interrupt response time in the worst case, with MM U intersegm e nt jump
INTERRUPT
EXC. HANDLING
RESPONSE TIME 47 INTCLK CYCLES M AX
MISSED
ARBITRATION VALID
ARBITRATION
(IN ST9 + INSTRUCTION CAN BE INTERRUPTED IF THEY
HAVEN'T MODIFIED YET REGISTERS OR MEMO RY)
INSTRUCTI ON N+ 1
INSTR UCTION N
NON INTERRUPT.
SEQUENCE.
6-1 = 5
INTC LK
6 INTCLK 14
22
6 INT C LK
CORRESPONDING TO 1.88 µS AT 25 MHz
21/50
THE ST9 REGISTER BASED CORE
1.5.3 Interrupt vect ors
The ST9 implements an interrupt vector ing st ructure that allows the on-chip peri pheral to iden-
tify the location of the first instruction of the Interrupt Service Routi ne (IS R) autom atically.
When the interrupt request is acknowledged, the peripheral interrupt module provides,
through its Interrupt Vec tor Register ( IVR), a v ector to poi nt into the ve ctor table of locations
containing the start addresses of the Interrupt Service Routines (defi ned by the pr ogrammer).
Each peripheral has a specific IVR mapped with in its Register File pages.
The Inte rr upt Vecto r table, con taining the list of th e address es of t he Interru pt Servi ce Rou-
tines, is located in the first 256 locations of the Program Memory (ROM ).
Figure 22. Ve ctor t able organiza tion
1 st 256 bytes
up to 128 vectors
TO P L EVEL
ISR
RESET
ISR
Fixed
Address
0000h
0100h
MEMORY
Top Level
Divided by
Zero
Power on
reset
THE ST9 REGISTER BASED CO RE
22/50
1.5. 4 Interrupt priorities
In any microprocessor-based system, there is a tr ade-off betw een the computational power of
the main program and the interrupt latency time. Express ed simply, the less the main program
is disturbed, the sooner it finishes its job. In the other hand, the CPU often needs to serve in-
terrupt re quests generated by the peripheral s as quickly as possible. A compromise m ust be
found to give both enough power to the main program while still staying as responsive as pos-
sible to inter rupts.
A typical microcontroller will let the burden of this work almost fully on the shoulder of the pr o-
gra mmer . On t he ST 9, po werfu l interrupt mana gem ent is available to significantly help th e
programmer.
The ST9 supports a fully programmable inter rupt priority structure. N ine priority levels are
available to define the channel pri ority relationship. Each channel has a PRiority Level (PRL),
that defines i ts priori ty level among eight programmable levels for interrupt requests.The ninth
level (T op Level Priority) is reserved for the internal Watchdog Tim er or the external Non-
Maska ble -Interrup t. The on-ch ip pe ripheral chann el and the eight external interrupt so urces
can be progr ammed w ithin eight priority lev els: level 7 has the lowest pri ority, level 0 has the
highest priority.
Figure 23. Interrupt priorities for peripherals
The priority mechanism is driven by the Current Priority Level parameter. At a given time, the
part of the program being executed runs un der a cer tain lev el. Y ou ca n c hange the level by
writing a different value in the core’s Central Inter rupt Control Register (CICR). You can as si gn
pr ior ity le ve l to ea ch i nte rru pt so ur ce. A t in itia lis ati on ti me, this va lue is wr itte n in on e o f th e
control registers specific to the corresponding peripheral.
Serial Co mmuni cation Interface
priority 3 ST9
CORE
Timer
priority 4
Analog to Digital Conver ter
priority 2
first
served
23/50
THE ST9 REGISTER BASED CORE
When a peripheral requests an interrupt, the built-in inter rupt controller compares the priority
level of the interrupt request to the Current Priority Level. The interrupt is on ly acknowledged
if its priority is grea ter than the Current Priority Level. This allows you to filter out interrupt re-
quests according to their degree of importance or of ur gency according to the current activity
of the program. If several u nits ar e located at the same priority level, an internal daisy chain,
fixed for each ST9 devic e, defines the priority relations hip within that l evel. The Non-Maskable
Interrupt input (NMI) is ha rd wired with a higher priori ty tha n an y le vel , and thus is ac knowl-
edge immediately in all circumstances.
ST9 provi des two interr upt arbitration modes: Concurr ent and Nested modes. The Concurrent
mode is the standard interrupt arbitration mode whil e the Nested mode improves the effective
interrupt response time w hen a nesting of the service routines is required acc ording to the re-
quest priority levels.
Figure 24. Example of nested and concurren t arbitration mo des
MAIN PROGRAM
INT1
0
1
2
3
4
5
6
7
INT2
INT3
INT1
MAIN
PROGRAM INT4 INT6 INT7 INT4 MAIN PROGRAM
INT1
INT2 INT3
INT4
INT1
INT6/INT7
CPL set to
4
NESTED
MODE CONCURRENT
MODE
IAM bit =
0TIME
INTE RRUPT 1 HAS PRI ORITY LEVEL 5
ei
ei
CPL=2
CPL=3
CPL=5 CPL=5
CPL=4
CPL=7 CPL=7
INTE RRUPT 2 HAS PRIORITY LEVEL 2
INTE RRUPT 3 HAS PRIORITY LEVEL 3
INTE RRUPT 4 HAS PRIORITY LEVEL 2
INTE RRUPT 6 HAS PRI ORITY LEVEL 1
INTE RRUPT 7 HAS P RIORITY LEVEL 2
INTE RRUPT 5 HAS PRIORITY LEVEL 0
CURRENT
PRIORITY
LEVEL
THE ST9 REGISTER BASED CO RE
24/50
1.6 DIRECT MEMORY ACCESS
1.6.1 Direct Memory A ccess descr iption
Direct Memory Acce ss capabi lity is a feature seldom found among 8-bit MCUs. It allows the
microcontroller to handle input/output data fl ow without using core instruction cycles.This fea-
ture allows you to boost the system performance.
The Direct Memory Access consists of a transfer between memory and a peripheral, in either
direction. DMA tr ansfers are implemented by the w a y of a DMA controller w hich stops the in-
struction execution and implement t he data tr ansfer. The core can then restart the instruction
execution at the end of the transfer. The DMA controllers ar e par t of the peri pherals. They use
an indirect addressin g mechani sm to DM A P ointers (add ress pointer s w hich contain t he ad -
dress of the DMA table) and Counter Registers (registers which contain the number of by tes
to transfer) stored in the Register File.
Figure 25. DMA overview
Assuming the peripheral is c onfigured to handle externally supplied data or to provide data to
external circuits, two steps are needed for a transfer to occur:
- the transfer must be requested by som e event or condition
- a mechanism m ust handle the reading of the data from one part and the w riting to the other
part.
The term DMA transfer represents the transfer of a single byte (or wor d) of data. Usually, more
than one byte is transferred and the transfer occurs in bursts. Thus, a third step is involved:
- a mechanism that counts the transfers and stops them when the count is finished.
Memory/Register
File
Counter
Address
Peripheral
A lready trans ferred
data
Data to be
transferred
R eg ist er File
Data Register
25/50
THE ST9 REGISTER BASED CORE
1.6.2 High speed system performance
Once proper ly initialised, the D MA controller allows peripherals to exchange data either w ith
memory or the register file, with no more use of the core resources than the stolen memory cy-
cles s trictly n eeded t o t rans fer d ata. The ma ximum num ber of bytes th at ca n b e t ransfer red
per transaction by each DMA channel is 222 w ith the Register File, or 65536 (64 Kbytes ) with
Memory. The time to transfer information between mem ory or registers and peripherals is
shortened to le ss than 1 µs . A DMA transfer with the R egister file requir es 8 CPUCLK cycles
or 0.32 µs at 25 MHz and a DMA transfer with memory requires 16 CPUCLK cycles or 0.64 µs,
plus any required wait states.
DMA c an dr asti call y i mpro ve system p er form a nce in c o mmu ni cati on i nte nsiv e ap plicat ions .
For ex ample , to r ead a character every 8 µs fro m the SCI re ceived a t 1Mbit per secon d re -
quires 35% of CPU time only to manage the interrupt routine. With the DMA, up to 30% of ad-
ditional CPU is available for other control functions
Figure 26. Example of the benefit of the DMA to read a character fro m SC I
1.6.3 DMA priority levels
The 8 priori ty l evels us ed for interr upts are also used to pr ioritiz e the DMA requests, which are
arbitrated i n the s ame arbitration phase as interrupt r equests. If the event oc currence requires
a DMA transaction, this will take place at the end of the current instruction execution. When an
inte rrupt and a D MA req uest occur s imult aneously, on th e sam e prior it y level, the D MA re -
quest is serviced before the i nterrupt because D MA is faster (onl y a few cycles) compared to
interrupt.
WITH DMA WITH INT ERRUPT
Data read y
every 8µs
CPU LOAD (DMA) : 0.32/8 = 4 %
CPU LOAD (INTERRUPT): 2.8/8 = 35 %
INTERNAL CLOCK 25MHz
DMA BETWEEN
SCI AND REGISTER
(0.32 µs)
SAVE CONT EXT
SWITCH CONTEXT
READ DATA
MANAGE POINTERS
RESTORE CONT EXT
RETURN FROM INT
(2.8 µs/56 Cycles)
CO RE PROG R AM
CO RE PROG R AM
30 % O F ADDITIONAL CPU
AVAILABILITY !!
THE ST9 REGISTER BASED CO RE
26/50
DMA requests are serviced if their priority level is equal to or higher than Current Priority
Level. DMA transactions are not interruptable. Bu t DMA requ ests are not ac knowledged
during top level interrupt routine.
An interrupt pri ority request must be higher than the Curr ent Priority Level (CPL) value in or der
to be ac kno w ledge d, whe reas , fo r a DMA trans acti on re que st, it mu s t b e equ al to or h ig her
than the CPL value in order to be exec uted. Thus, only DMA transacti on requests can be ac-
knowledged when the CPL = 7.
DMA requests do not modify the C PL value, since the DMA transaction is not interruptable.
1.6.4 The SWAP mode
An extra feature w hich may be found on the DMA channels of some peripherals (i.e the Mul ti-
Function T IMER) i s the S wap m od e. This fe ature al lows transf er from two DMA tab les al ter-
natively. Al l the DMA describers in the Register Fi le are thus doubled. Two DMA transaction
count ers and tw o DMA address poi nters allow the de finition o f two fully in depend ent tab le s
(they onl y have to belong to the same space, Register File or Memory). The DMA transaction
is programmed to start on one of the tw o tables (say table 0) and, at the end of the block, the
DMA c ontroller automatic ally sw aps to the o ther table (table 1) by pointing to the other DMA
describers. In this case, the DMA mask (DM bit) control bit is not cleared, but the End Of Block
interrupt request is generated to allow the optional updating of the first data table (table 0).
Until the swap mode is disabled, the DMA controller will conti nue to swap between DMA Table
0 and DMA Table 1.
27/50
THE ST9 REGISTER BASED CORE
1. 7 INSTRU CTIONS SET AND ADDRESSING MOD ES
1.7. 1 Overview of Instruction s Set and Addressing Mo des
The ST9 is desc ribed as an 8/16-bit microcontroller. This means that although the size of the
internal registers and the width of the data bus ar e 8 bits, the instruction set includes instruc-
tions that hand le a pair of registers or a p air of bytes in memory at once. The se instructions
represent roughly one half of the total instructions, which means that the ST9 can be pro-
grammed with the same ease as if it were adverti sed as a full 16-bit machi ne. This is why it is
so well suited for C programming.
The ST9 instruction set consists of 94 inst ruct ion types which can be divided into eight groups:
Load ( two operand s), Arithm etic & l ogic (t wo o perands ), A rithmeti c Logi c an d S hift (on e op -
erand), Stack (one or two operands), Multiply & Divide (two or three operands), Boolean (one
or two operands), Pr ogram Control (zero to thr ee operands), Miscellaneous (zero to two oper -
ands). The ST9 can operate w ith a wide range of data lengths from sin gle bit s, 4-bit nibble s
which can be i n the form of Binary Coded Decimal (BCD) digits, 8-bit bytes, and 16-bit words.
A particularly notable feature is the comprehensive “Any Bit, Any Register” (ABAR) ad-
dressing capability of the Boolean instructions.
Figure 27. Example of direct bit addressing mode
Powe rf ul add ressing mode s such as indirec t, in direc t with incremen t o r dec rement, in dexed
shorten the code needed to access data even in compl ex structures or ar rays. They also facil -
itate acce ss to local v ariables created on th e s tack on e ntering func tions. This f ull set of ad -
dressing modes allows simple access to comp lex data arrays of stru ctures (hig h level lan-
guage) and less pointer calculation using ALU.
Working registers, that benefit from the most powerful instructions and addressing modes, are
heavily us ed by the c ompiler. In fac t, the GNU9 compiler does not always translate the s ource
code. There are optimization schemes that save execution time and/or memory by judic iously
all ocating the working registers, so that in many cases arguments are not pushed to the stack
but merely to an available working register.
r12 r7
bld r7.3, r12.6
thisinstruction loadsthe bit 6 of theworking
register 12 in bit 3 of working register 7.
1 1
THE ST9 REGISTER BASED CO RE
28/50
1.7.2 High speed computation
The relocatable w orking register bank of ei ther 16x 8-bit or 8x16-bit register locati ons supports
the fastest available instructions. With the extensive set of instructions and addressing modes,
the ST9 is thus able to hand le complex calcul ations (for example a large arr ay of data i n the
memory), much faster than any 8-bit accumulator machine.
For e xam ple, t he com ple x instruction b elow, w hich c an b e used t o sear ch a c hara cter i n a
table, has the following characteristics at 25 MHz:
Figure 28. Example of reduced code size and fast execution time capab ilities
1.7.3 Effective hi gh level language support
In addition, the optimizer of the ST9 GNU C Compiler make full use of the available set of in-
structi ons and addressing modes, and opti mizes the register allocation for function par ameter
within the working register bank.
The compiler generates very fast and compact code, even from s ophisticated data manipula-
tion routines.
Critical parts of the s oftware c an be furthe r o ptimiz ed by interlea ving C stat ements with as-
sembly language to benefit from the effec tive ness of the instruction set (for example, the im-
plementation of a character search in a table with a single opcode).
1.7.4 Addressing modes
The ST9 offers a wide vari ety of established and new addressing modes and combinations to
facili tate full and r apid ac cess to the address s paces whil e reducing program length. The avail-
able addressing modes are shown hereafter:
OPCODE EX ECUTION TIME CODE SIZE
CPJTI r, (rr), N
No Jump Jump
3 BY TES
0.56 µs 0.64 µs
29/50
THE ST9 REGISTER BASED CORE
Figure 29. Add ressing Modes
Sin gle ope rand arithmet ic, log ic and shift byte i nstructio ns hav e direct re gister and ind irect
register addressing modes. For a full list of the possible combinations for each instruction
type, please refer to the ST9 Programm ing Manual.
1.7.5 A good alternative to more costly 16-bit MCUs
The wide r ange of i nst ructions eas es use of the r egister file and address spaces, reducing op-
eration times, while the register pointers mechanism allows an unma tched code efficiency.
Figure 30. Example of a powerful instru ction
Oper and is In Addres sing Mode Destination
Location Notation
Instruction Immediate Byte
Word #N
#NN
Register File Direct Byte
Word r
rr
Indirect Byte/Word (r)
Indexed Byte/Word N(r)
Indirect Post-Increment Byte (r)+
Program or Data Memory Direct Byte/Word NN
Indirect Byte/Word (rr)
Indirect Post-Increment Byte/Word (rr)+
Indirect Pre-Decrement Byte/Word -(rr)
Short Indexed Byte/Word N(rr)
Long Indexed Byte/Word NN(rr)
Register Indexed Byte/Word rr(rr)
Any bit of any working register Direct Bit r.b
Any bit in program or dat a memory Indirect Bit (rr).b
CPJTI: COMPARE and JUMP if TRUE OTHERWISE POST-INCREMENT
Com par e the c ontents of des tination and s ource. If compare is TRUE,
JUMP to the JUMP address OTHERW I SE post-increment the pointer
These inst r ucti ons are us eful to perform dat a s earch in Memor
y
Sour c e poi nter ; inc re me nted if
com par e is not verif ied
CPJTI r2 , ( rr14 ) , OK_COMP
Bra nc h add re s s if co m par e is verifie d
Reference value for comparison
THE ST9 REGISTER BASED CO RE
30/50
This instruc tion set facilitates lar ge program and data handli ng through the MMU, and it im-
proves the performance and code density of C function calls. The 8 and 16-bit data manipula-
tion offered by these instructions gives a cost effective alternative to 16-bit MCUs.
Figure 31. ST9 vs 68HC12 on a 16-bit memor y-memory transfer
ST9
16-BIT
ACCUMULATOR
MACHINE
CODE BYT E S EXECU TIO N TIME
ldw (rr), (rr) 20.64 µs
MICROCONTROL LE R
68HC12 ldd [ opr16, x]
std [ opr16, x] 4
4750 ns
625 ns
1.37 µs
8
(16-bit
indexed-indirect)
ARCHITECTUR E INTERNAL CL OCK
SPEED
8/16-BIT
REGISTER
MACHINE
8 MHz
25 MHz (16-bit indirect)
31/50
THE ST9 REGISTER BASED CORE
1.8 ST9 OPERAT IN G MODES
To provide for real time management capability, the ST9 is designed to operate at a higher i n-
ternal clock speed compared to traditional 8-bit architecture.
Thanks to the PLL, a low cost 4M Hz crystal or cera m ic resonator can be used to generate up
to 25MHe of internal operating frequency.
To optimize the performa nce vers us the pow er consum ption of the application, ST9 devices
support a range of operating modes that can be dynamically selected depending on the per-
formance and functionality requirements of the application at a given moment.
Figure 32. Clock co ntrol unit simplif ied b lock diagram
RUN MODE: Th is is the full speed exec ution mode with CPU and peripherals running at the
maxim um clock speed delivered by the Pha se Locked Loop (P LL) of the Clock Con trol U nit
(CCU), or any frequency obtained from the appropriate programming of the control regis ters.
SLOW MO DE: Power consumption can be significantly reduc ed by running the CPU and the
peripherals at reduced clock speed using the CPU Prescaler and CCU Clock Divider.
In this mode, us in g a 4MHz Crystal, the ST9 oper ates down to 125 KHz and dra ws down to
1mA typical.
Quartz
1/16
1/2
oscillator CLOCK2
CLOCK1
PLL
Clock Multiplier
CPU Clock
Prescaler to
CP U Co re
to
Peripherals
CPUCLK
INTCLK
Un i t/Divider
3-5 M Hz
(0-25 MHz)
x 6, 8, 10, 14
: 1 to 7
: 1 to 8
THE ST9 REGISTER BASED CO RE
32/50
WAIT F OR INT ERRUP T MOD E: The W ait For Interrupt (WFI) instruction suspends program
execution until an interrupt request is acknowledged. During WFI, the CPU clock is halted
while the peripheral and interrupt controller keep running at a frequency depending on the
CCU programming.
HALT MODE: When executing the HALT instruction and if the Watchdog Timer is not pro-
grammed as a w atchdog, the CPU and its peripherals stop operation and the I/O ports enter
high impedance mode. A typical power consumption of less than 1µA is achieved
An external Reset is necessa ry to exi t from Ha lt mode.
Figure 33. Typical power consump tion of the ST90158 Iin RUN and Wait For Interrupt
20
10
0
30
4 8 12 16 20 24
50
40
60
28
I
DD
run 5V
I
DD
run 3V
I
DD
WFI 5V
I
DD
WFI 3V
mA
Internal Frequency (MHz)
ST90158 Power Consu mpt ion
33/50
PERIPHERALS AND I/O PORTS
2 PERIPHERALS AND I/O P ORT S
The ST9 family
core is surrounded by a range of powerful peripherals and I/O Ports.
Figure 34. Main standard peripherals:
Most peripherals of the ST9 have suf ficient built-in in tellig ence to be able to perform even
complex jobs on their own, freeing the core almost entirely from their basic management.
They includ e power ful cont rol an d data ma nage ment fu nctio ns that drasti cally re duce C PU
overhead. These capability to work independently fr om the C PU allows the core to be fully uti -
lized for very complex microprocessing tasks.
A typical example is the Analog-to-Digital Converter (A/D) that monitors automatically two
channels and interrupts the CPU when one of the inputs is out of predefined window of accept-
able voltage (for example the speed variation of a motor or the drop of the power supply).
Name Function
Multi-Function Timer
All counting and timing functions. Inc ludes auto-relo ad on con-
dition, interrupt generation, DMA transfer, two inputs for fre-
quency measurement or pulse counting, two outputs that can
change on condition.
Conditions include: overflow/underflow, comparison with one or
two c om pare registers.
Capture registers allow recording transitions on i nputs with their
time of occurrence.
Serial Communication In-
terface
Asynchronous transfer with either internal bit-rate gener ation or
an external clock. Parity generation/detection. Address recogni-
tion feature that can request an interrupt on match of an input
character. DMA transfer.
Serial Peripheral Interface Serial input or output regi ster, with internal or exter nal clock. In-
tended for I/O expans ion, or synchr onous ser ial external device
such as serial EEPROM .
Watchdog Timer Can be used either as a watc hdog or as a timer with input and
output capable of pu lse counting or waveform generation.
Input/Output port
Parallel input/output port. Each bit individually configurable as
input, output, bi-dir ectional, or alternate function. Inputs can be
high impedance or with pull-up, CMOS or TTL-level. Outputs
can have open drain or push-pull configuration.
Analog to Digital Converter
Eight-bit analog to digital c onverter. One to eight c hannels can
be converted in a row. On each of two of the eight channels, an
Analog Watchdog function allows to define two bounds. When
exceeded, an interrupt is generated.
PERIPHE RALS AND I/O POR TS
34/50
2.1 FLEXI BLE I/O PORTS
The paral lel input-outputs have a basically very straightfor ward functiona lity. O nce initiali sed,
they appear as a register that can be written or read. However in many c ases, dir ect byte-wide
I/O is not suffici ent. Bit-oriented I/O is often what is used in microcontroller systems.
A powerful feature of the ST9 devices is that y ou can address the eight bits of each port indi-
viduall y to provide digital and analog i nput/output, or to connect input/output signal s to the on-
chip peripher als as alternate pin functions. The ST9 also provides the external pins of the
other peripherals (timers, UARTs, etc.) by diverting some bits from the parallel I/O por ts. T he
flexibi lity of the ST9 I/O pins allow designers to match the MCU to the appli cation, and not the
application to the MCU.
The ST9 family devices have up to 10 parallel I/O ports which have an additi onal very flexibl e
feature. You can independently configure each bit as:
■an input with two variants (TTL or CMOS),
■an o utput with also tw o variants (open-drain or push-pull),
■a bidirectional port with either a weak pull-up or an open-drain output side,
■an alternate function output (that is th e output pi n of an internal peripheral) with al so either
open -drain or push-pull output driver.
Figure 35. ST 9 I/O ports configurations
For some peripherals (e.g. ADC), t he por t that provides the input pins has a special alternate
function mode. T his mode disconnects the i nput buffer from the pin and s horts the buffer input
to the ground. The output buffer is put in high-impedance mode. The pin is permanently con-
nected to the input of the peripheral, thus allowing its voltage to be read at any time.
OUTPUT SLAVE
LATCH
OUTPUT MASTER LATCH INPUT LATCH
INTERNAL DATA BUS
PUSH-PULL
TRI-STATE
WEAK-PULL UP
OPEN DRAIN
TTL
CMOS
ALTERNATE
FUNCTION
(IN)
I/O PIN
OUTPUT
ALTERNATE
FUNCTION
(OUT)
INPUT/OUTPUT
BIDIRECTIONAL
INPUT
BIDIRECTIONAL
ALTERNATE
FUNCTION
CMOS: Vil (max) : 0.3 Vcc Vih (min) = 0.7 Vcc
TTL: Vil (max) : 0.7 Volt Vih (min) = 2.0 Volt
Vil input low level Vih input hi gh level
INPUT Anal og In p ut
CMOS or TTL level
Schmit t Tr igger
OUTPUT Push-pull
Open Drain
BIDIRECTIONAL Weak Pull-up
Open Drain
ALTERNATE
FUNCTION Push-pull
Open Drain
35/50
PERIPHERALS AND I/O PORTS
Each port is associated with a data register and three control regi sters. These define the port
configuration a nd allow dynam ic configur ation changes d uring pro gram ex ecution. Port data
and control registers are mapped into the R egist er File and are treated just li ke any other gen-
eral purpose register. T here are no s pecial instructions for port manipulation: any instruction
that can address a register, can address th e ports. Data can be directly accessed in the port
register, without passing through other memory or “accumulator” locations.
2.2 TIMER S
The timer or timing system makes it possible to measure and ti me external and internal events
without the need to do this with time critical softw are loops.
2.2. 1 Standa rd Time r (STIM)
The standard timer includes a programmable 16-bit down counter and an associated 8-bit
prescaler wi th Single a nd C ontinuous c ounting modes capability. It uses an input pin (STIN)
and an ou tput p in (ST OUT) . Thes e pins, when avail able, may be indep ende nt pi ns or con -
nected as alternate functions of an I/O port bit.
STIN c an be use d in on e of fo ur p rogrammab le inp ut mod es : ev ent cou nte r, g ate d e xter nal
input mode, triggerable input mode, retriggerable input mode.
STOUT can be used to generate a Square Wave or Pulse Width Modulated signal.
The input clock to the pres caler can be driven either by an internal clo ck equal to INTCLK di-
vided by 4, or by CLOCK 2 derived directly from the external oscillator, divided by 64 or 128,
thus providing a stable tim e r e fer ence independent from the PLL programming.
The standard timer end of count condition is able to generate an interrupt which is connected
to one of the external interrupt channels.
PERIPHE RALS AND I/O POR TS
36/50
Figure 36. Main features of the STIM
Four registers all ow to control standard timer. You can write in timer registers at any time even
if timer is running. A Debugger option also giv es you the possibi lity to stop the timer duri ng the
Emulation Trap.
2.2.2 Watchdog Timer (WDT)
The Watchdog Tim er is similar to th e standar d timer when work ing in time r m ode. When
watchdog mode is started, only reset can e xit this mode.
The main features are almost the same as for the standard timer. Timer registers can be
written at any ti m e even if timer is running. The counter is also read at any time but wr iting to
the counter is taken in accoun t only at the timer start or at the EOC.
Functional modes - Single count down
- Continuous count down
Timer architecture - One 8-bit Prescaler
- One 16-bit Counter
- One Control Logic Register
Timer accuracy - Min.: 160 ns at 25 MHz
- Max.: 2.68 s at 25 MHz
Timer input clock - INTCLK/4
- External input clock - Max. = 25/4 MHz
Timer input pin - One configurable input pin - Not on all ST9
Input modes
- External clock
- Gated input
- Retriggerable input
- Triggerable input
Timer output pin - One output pin configurable as AF or IO - Not on all ST9
Output modes - Square wave generation
- PWM
Interrupts - Interrupt on INTA1 external interrupt channel
37/50
PERIPHERALS AND I/O PORTS
Figure 37. Main feature s of the WD T
The watchdog timer can be used to:
■gene rate periodic interrupts;
■measure input si gnal pulse widths;
■request an interrupt after a set num ber of events;
■gene rate an output signal w aveform ;
■act as a watchdog timer to monitor system integrity.
The watchdog timer prov ides a means of graceful recovery from a sys tem probl em. This could
be a software fault, usually generated by external i nterference or by unforeseen logical condi-
tion s, or a hardw are prob lem th at prevents the pro gram from op erati ng cor rectly. T his fa ult
causes the application program to abandon its normal sequence of operation.
If the pr ogram fails to reset the wat chdog at som e p redeterm ined inter val, a har dwa re res et
will be initiated. The bug m ay still exist, but at least the sys tem has a w ay to recove r. This is
especially useful for unattended systems.
Functional modes
- Watchdog
- Normal Timer
- Single count down
- Continuous count down
Timer architecture - One 8-bit Prescaler
- One 16-bit Counter
- One Control Logic Register
Timer accuracy - Min.: 250 ns at 16 MHz
- Max.: 4.19 s at 16 MHz
Timer input clock - INTCLK/4
- External input clock - If availab le
Timer input pin - One configurable input pin - If available
Input modes
- External clock
- Gated input
- Retriggerable input
- Triggerable input
Timer output pin - One output pin configurable as AF or IO
Output modes - Square wave generation
- PWM (software is needed)
Interrupts - End of count interrupt
- Top level interrupt
- Watchdog reset
Watchdog mode selection - Software
- Hardware fixed (metal option) - Only on certain devices
- By external input pin
PERIPHE RALS AND I/O POR TS
38/50
2.2. 3 Multifu nction t imer (MFT)
The Multi-Fu nction Timer is the most pow erful of the ST 9 on-chip peripherals. It offers po w-
erful timing capabi lities and features 12 operating modes, includi ng automatic PWM genera-
tion and frequenc y measurement. This gives to the S T9 devices the possibility to cover m ost
application timing requirements.
The MFT comprises a 16-bit up/down counter driven by an 8-bit programmable prescaler. The
input clock may be INTCLK/3 or an external source. The timer features two 16-bit comparison
register, and two 1 6-bit c apture/load/reload registers. Two input pins and two alte rnate func -
tion output pins are available and independently configurable.
Two input pins, programmable as external clock, gate or trigger, allow 16 modes of operati on,
including autodiscrimination of the direction of externall y generated signals.
Pulse Width Generation can easily be implemented, using the ov erflow/underflow signal and
the two 16-bit compar ison registers, ea ch of them able to independently s et, reset, togg le or
ignore two output bits.
The Multi-Function Timer outputs may also generate interrupts for system schedu ling, and
trigger DMA transactions of a data byte to or from a data table in memory through an I/O por t
with handshake.
When two timers are present in an ST9 dev ice, a combined operating mode is available.
Figure 38. An example of the ST9 Multi-Function Tim e r capabilities
With the MFT, a comp lex application such as a bar code reader can be implemente d with no
CPU intervention by us ing the DMA and the ti mer autoclear mode in order to measure sophis-
ticated wave forms.
BAR CODE READER APPLICATION
TIMEOUT (END OF SCAN)
CAPTURE WITH
AUTO-CLEAR, MAX.
RESOLUTION 250nS
START
39/50
PERIPHERALS AND I/O PORTS
2.3 FAST ANALOG TO DIGITAL CONVERTER (ADC)
The Analog to Digital Converter converts an external analog signal (typically relative to
voltage) applied to one of eight in puts into a digital representatio n using an 8-bit successive
approximation Analog to Digital Converter. The ST9 devices with this feature can be used for
instr u m entati on, environmental data logging, or any application that lives in analog world.
Figure 39. Analo g to Digital Converter
Two m acrocells are av ailab le : a simple ADC a nd one mo re sophis ticate d (ADC8). Only t he
last one is developed below.
The 8-channel An alog to D igital Converter ( ADC8) co mprises an input multiplex channel se-
lec tor feeding a successive approximation c onverter. Conv ersion requi res 138 INTCLK cycles
(of which 87,5 are required for sampling), conversion time is thus a function of the INTCLK fr e-
quency; for instance, for a 24MHz clock rate, conversion of the selected c hannel requires
5,75µs. This ti me includes the 3,64µs required by the bui lt-in Sample and Hol d ci rcuitry, which
minimizes the need for external c omponents and allows quick samp ling of the signal to mini-
mise warping and conversion error. Conversion resolution is 8 bits, w ith ±1/2 LSB max imum
non-linearity error between VSS and the analog VDD reference.
The c onverter u ses a fu lly differ ential a nalo g inpu t confi gurat ion for the bes t nois e immu nity
and precision performanc e. Two separate supply references are provided to ensure the best
possible supply noise rejection and to allow the us e of analog reference voltages low er than
the digital VDD supply. In fact, the converted digital value, is referred to the analog reference
voltage which determ ines the full scale converted value. Naturally, Analog and Digital VSS
MUST be com mon.
Up to 8 multiplex ed Analog Inputs are available, depending on the specific device type. A
group of s ignals can be converted sequentiall y by simply progr amming the starting addr ess of
the first analog channel to be converted and using the AUTOS CA N feature.
ANALOG
1
2
3
4
5
ANALOG
SIGNAL
Time
542112
DIGITAL
Voltage A / D
CONVERTER
PERIPHE RALS AND I/O POR TS
40/50
Two Analog Watchd ogs ch annels are p rovided, allowing continuo us hardware m onitoring of
two input channels. A n interr upt r equest is generated whenever the c onverted value of either
of these two analog inputs is outside the upper or lower program med threshold values, as in
the exampl e below. T he com parison resu lt is stored in a dedicated register . You have a fa st
analog data acquisition thanks to reduced CPU loading.
Figure 40. Analo g watchdogs use for monitoring
Single a nd conti nuous con version m odes are a vailable. C onversion may b e trigge red b y an
external signal or , internally, by the M u ltifunction Timer.
A Power-Down programm able bit allows the ADC to be set in low-power idle mode.
The ADC’s Interrupt Uni t provides two maskable channels (Analog Watchdog and End of Con-
version) with hardware fixed prior ity , and up to 7 pr ogrammabl e priority levels.
2.4 SER IAL INTE RFA CE
Serial interfac e are used to exchange data with the external world. The ST9 m icrocontrollers
have both asynchronous and synchronous communications peripherals built in. The asyn-
chronous interface is called Ser ial Communication Interface (SCI) and the synchronous inter-
face is called Seri al Peripheral Interface (SPI). A typical SCI application is to connect a PC for
debugging purpose while a typical SPI application is to connect an external EEPROM.
A synchronous bus includes a separate line for the clock signal which simplifies the transmitter
and receiver but is more susceptible to noise when used over long dis tanc es. With an asyn-
chronous bus the tr ansmitter and receiver cloc ks are independent, and a resynchronization is
performed for each byte at the start bit.
INPUT
VOLTAGE CONVERSION
RESULT
INTERNAL
TRIGGER
12 34 5 6
UPPER
INT INT
INT
THRESHOLD
THRESHOLD
LOWER
Analog to Digital conversion s
41/50
PERIPHERALS AND I/O PORTS
Figure 41. Synchronous and asynchrono us co mmunications
2.4.1 Universal Serial Peripheral I nterface (SPI )
The Se rial Periph eral Interface is a syn ch ronou s inpu t-ou tput port tha t yo u can confi gure in
various modes, including S-bus, many more uses, of which two are: interfacing with serial -ac-
cess EEPRO M s, and i nterfacing with a liquid-crystal display.
A universal Serial Peripheral Interface, providing basic I²C-bus, Microwire-Bus and S-Bus
functionality, allows efficient communication w ith low -cost external peripherals or serial ac-
cess memo r ies such as EEPROMs.
The main block of the SPI is an 8-bit shift register which can be read or written in parallel
through the internal data bus of the ST9, and that can shift the data in or out on two separate
pins, named SDI and SDO, respectively. The serial transfer is initiated with a write to the SPI
Data Regi ster (SPI DR ). In put and o utpu t a re do ne simul ta neously, ea ch m ost sig nificant bit
being output on SDO while the level at S DI becomes the least significant bit. Each time a bit
is transferred, a pulse is output at the SCK pi n. When eight bits are transferred, eight pulses
have b een sent on S CK, and th e p rocess stops . If the pr oper bits are set in t he S PI Cont rol
Register (SPICR), an interrupt can be requested on end of tr ansmission. To s ummarise:
- Transfers are started by writing a byte into the SPI data register
- Input and output are done at the same time
- Input and output are done most-significa nt bit first
SYNCHRONOUS ASYNCHRONOUS
0b bbbb1
CLOCK
bbb
DATA
CLOCK
+
DATA
b b Start Stop
bb
PERIPHE RALS AND I/O POR TS
42/50
2.4.2 Comprehensive serial comm unication Interface (SC I)
The SCI is t he as so ciati on of a UA R T w hi ch o ffers all th e us ual fun ctio ns f or a sync hro nou s
transfer and a complex logic that handles tasks such as character recogniti on and DMA. It can
also work as a simple serial expansion port that then resembles the SP I.
Serial comm u nica tion is ea sily imple ment ed, us ing f orm ats and faci lities offere d by t he ST 9
Serial Communication Interfac e. Thi s peripheral prov ide full flexi bility in character format (5, 6,
7, 8 databits), odd, even or no pari ty, address bit, 1, 1.5 or 2 stop bits in asynchronous mode,
and an integral baud rate generator allow ing commu nication at up to 370 kbaud in asynchro-
nous mode or 1.5 Mbytes/s in sy nchronous mode.
Industrial, t elecom and c ommu nicati on system s us ers ca n furthe rmo re benef it from th e s elf-
test and addr ess bit wake-up facili ty offered by the character search mode. Using the SCI, so-
phisticated high speed serial data communication can be implemented by simply selecting of
the built in operating modes. For example, the SCI is able to automatically s earch for a c har-
acter, or for its own address in a network environment.
43/50
DEVELOPMENT TOOLS
3 DEVELOPM ENT TOO LS
3.1 SOFTWARE TOOLS: GNU C TOOLCHAIN
The programming tools available for the ST9 are known as G NU-9 tools . T h is GN U toolchain
offers you a full set of resources for the development of code for the ST9 mi crocontroller. This
is achiev ed t hrou gh the op tim iz ed G NU C c om piler , th e ma cro- ass e mbler , t he lin ker/l oa der
and the library archiver. Progr am debugging is made easier with the C language source level
debugging which runs under Windows.
The GNU-9 is a set of MS-DOS programs that can be driven from a single program called
GCC9. This program is c apable of calling the following programs in turn:
Main block name File name Block name Action
C-compiler ccp9 C pre-processor Ex pands the macros, inserts the
include files, r emoves the disabled
conditional compilation blocks
cc9 C-compiler Translates C-code into assembly
source text.
Macro-assembler tr9 Assembler pre-
processor Expands the macros, inserts the
include files, r em oves the disabled
con d itional compilation blocks.
gas9 Assembl er Translates assembly language into
machine code.
Linker ld9 L i n ker Links the different object files, posi-
tions the code at predefined addresses
in memory.
DEVEL OPMENT TOOLS
44/50
3.1. 1 GNU C compiler
The GNU C compiler for the ST9 allows you to write C source code using traditional C
(Kernighan & Ritchie), ANSI C, or GNU extensions and to produce assembly language source
code. You can use all standard ty pes (char, int, short, long, signed or unsi gned, float and
double) in you r code . The librarie s which ar e delivered wi th, include string handling, conver-
sion, I/O routines and mathematics. You have a direct access to the Register File of the ST9,
allowing access to all registers and on-chip peripherals. It exists also some options to gen-
erate code for one or two memor y s paces, on e or two stacks and interrup t routines.
The C compiler all ows inclusion of assembly language instructions with access to C program
symb ols. Then t he generated as sembly so urce file m ay include i nterleaved C line s an d as-
sembly languages lines, and provides information for source-level debugging.
When us ed with the Assembler and Linker, it allows the generation of executabl e object code
for all members of the ST9 family.
3.1.2 Assembler
The Assem bler pre-processor allows m acro substitution, file inclusion, c ondition al assembl y,
pse udo- in st ructions an d ps eudo -mac ros. S ourc e lev el de bugg ing inf ormatio n is ge nera ted
with the object file by the assembl er.
3.1.3 Linker
The Linker combines object code files issued by the as sembler. It resolves references to ex-
ternal symbols and searches li braries for necessary modules to produc e a n output file i n a bi-
nary format, downloadable by the debugger to the ST9 emulator.
A m ap file is generated, including all mapping information on sections, files, and symbols.
Separate files are produced to support ST9 MMU mechanism.
3.1.4 Debugger
The S T9 Debugge r a llo ws so urce level debug for C langua ge and a ss embly la ngua ge pro-
grams, even with optimized C language programs.
The debugger is able to generate trace information, with hardware information interleaved
with source lines, and to display the lo cal s ymbols of the current C procedu re and the stack
based on the C language source level.
45/50
DEVELOPMENT TOOLS
Figure 42. Windows based Debugger
The Windows based debugger prov ides a user friendl y and highly flexibl e interface which may
be co nfigured to pre cise ly mat ch the u ser’s requ irem ent. B reakp oints allow th e MCU to be
halted when the ap plication s oftware ac cesse s specific addresses or addresses within a se -
lect ed range or on data fetch cycl es. You may then r ead and modify any register and memory
location. An on line assembler/disassembler is also available to ease debugging.
An important feature of the ST9 development system is that true source level d ebugging is
possible, me anin g code may be viewe d at s ource level a nd b reakpoints may be se t on high
level co de, ra the r than on dis ass embled t arget code. This is mu ch m ore mea ningf ul to th e
user and ensures a more convivial and productive development environment.
"c"
breakpoi nt
inquiry on
the "c"
variable
"buffer"
assembler
breakpoi nt
DEVEL OPMENT TOOLS
46/50
3. 2 HARDWAR E TOOLS
The Hardware Development System (HDS2) mainframe, in conjunction with various dedi-
cated probes, allows emulation and development for the ST9 device family.
The development system is controlled by a Host PC on w hich the Windows based debugger
runs. The Host PC is simply connected to the mainframe by means of a parallel port.
Once assembled, and/or c ompiled and l inked, the application softwar e may be downloaded to
the real-time emul ation mem ory, which y ou can c onfigure, m ap and modify as r equired. The
devic e probe is the n connected to the a pplicati on target hardware in place of the MCU a nd
real-t ime emulation of the target application can begin, thus allowing sophisticated testing and
debugging of both application hardware and software
3.2.1 Real-time developm ent tools
The ST9 real-time development tools consist of v arious hardware and s oftware components,
which togeth er form a fl exible and sophisticated system designed to provide com prehensive
development support for the ST9 family of MCUs.
The Emulator or Hardware Development System mainframe, in conjunction with various ded-
icated probes, allows emulation and development of spec ific devices.
Figure 43. Emul ator with its probe p lugge d in dedicated boa r d
The development system is controlled by a host P C on which the Windows based debugger
runs. The host PC is s imply connected to the Emulator Mainframe by means of a par allel port.
The WGDB9 Windows GNU Debugger software suite i s supplied with the Emulator hardw are,
47/50
DEVELOPMENT TOOLS
in addition to the c onvention al DOS ST 9 Software suite, which includes a macroassembler, a
linker/loader. The Windows based debugger pr ovi des a user friendly and highly flexible inter-
face whi ch may be conf igur ed t o p rec isely m atc h th e us er’s req uire men ts. Al l e mulat or s et -
tings are accessible via the control software.
Once assembled, and/or c ompiled and l inked, the application softwar e may be downloaded to
the real-time emulation memory, w hich can be configured, mapped and modified as required
by the user. The device probe i s then connected to the appli cation target hardware in place of
the MCU a nd rea l- ti me emulation of the target app lication can begin, thus a llow ing sophisti-
cated testing and debugging of both application hardware and software.
User definable breakpoints allow the MCU to be halted when the application s oftware ac-
cesses specific addresses, and/or addresses within a sel ected r ange, and/or on data fetc h cy-
cles. The user may then read and modify any regis ter and memory location. An on l ine assem-
bler/disassembler is also availabl e to ease debugging.
An important feature of the ST9 development system is that true source level d ebugging is
possible, me anin g code may be viewe d at s ource level a nd b reakpoints may be se t on high
level co de, ra the r than on dis ass embled t arget code. This is mu ch m ore mea ningf ul to th e
user and ensures a more convivial and productive development environment.
A completely integrated trace f acility is ava ilable. This hardware im plem ented function fea-
tures 4KByte of 44-bit wide trace m emory; sequential conditions m ay be defined on memory
even ts; one breakpoint on a da ta value m ay also b e set. On e extern al signal s i s inpu t on a
subclic connector which can generate a breakpoint.
Trace memor y events may be used as br eakpoints or to enable or di sable the trace recording
feature. Such a powerful tool enables the user to detect and tr ap virtually any patter n, and thus
rapidly debug the target application.
Log files offer the abil ity to send any screen display to a text file. In partic ular, l og files are very
usef ul t o sav e the co nte nts of the l ogi c an aly ser a nd/or th e c ontent s of dat a reg iste rs t o be
subsequently analysed or printed.
Comman d files can be used to ex ecute a set of debugger c ommands in batch mode, to sim-
plify and speed up the emulation session.
Finally, when the target program is fully debugged, the appropriate ST9 EPROM/OTP pro-
gramming board can be used to program the EPROM/OTP version of the target device to
allow stand-al one testing and evaluation.
DEVEL OPMENT TOOLS
48/50
3.2. 2 EPROM programming boards
These boards are a programming tool for EPR OM and OTP members of the ST9 family.
Figure 44. EPROM programming board
The EP ROM p rogramm ing board i s designed to progr am the EPR OM versions of microcon-
troller, inc luding both the ceramic windowed and plastic O TP pack ages. Several sockets are
provided to receive the different existing packages types.
The EPROM programming board uses a RAM in which your code is downloaded. The
EPROM device will be progr ammed from the contents of this RA M.
The board can perform three operations:
■verify the blank s tate of the m ic rocontroller EPR OM ;
■program m icrocontroller with the content of hexadec imal file;
■verify the microcontroller.
49/50
DEVELOPMENT TOOLS
3.2. 3 Gang Progr am mer
The Gang Programmer consists of tw o components: a base unit com mon to all ST9 dev ices
and a Gang Programmer Adaptor (GPA) module to suit each package type. It is capable of si -
multaneously programming up to ten EPROM or OTP MCUs. There are two colour LEDs indi-
cate pass or fail status for each device.
Figure 45. Gang programmer
DEVEL OPMENT TOOLS
50/50
NOTES:
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Pur ch ase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights t o use t hese com pone nt s i n an
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