VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 1Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
4-Line (Quad) ESD Protection Diode Array in LLP75-6L
MARKING (example only)
Dot = pin 1 marking
XX = date code
YY = type code (see table below)
DESIGN SUPPORT TOOLS
FEATURES
• Compact LLP75-6L package
• Low package height < 0.6 mm
• 4-line ESD protection (quad)
• Low leakage current < 0.1 μA
• Low load capacitance CD = 6 pF
• ESD immunity acc. IEC 61000-4-2
± 8 kV contact discharge
± 10 kV air discharge
• Surge current acc. IEC 61000-4-5 IPP > 1.5 A
• Soldering can be checked by standard vision inspection.
No X-ray necessary
• e4 - precious metal (e.g. Ag, Au, NiPd, NiPdAu) (no Sn)
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
20453 1
123
65
4
21002
21001
XX
YY
click logo to get started
Available
Models
ORDERING INFORMATION
DEVICE NAME ORDERING CODE TAPED UNITS PER REEL
(8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY
VESD09A4A-HSF VESD09A4A-HSF-GS08 3000 15 000
PACKAGE DATA
DEVICE NAME PACKAGE
NAME
TYPE
CODE WEIGHT MOLDING COMPOUND
FLAMMABILITY RATING
MOISTURE
SENSITIVITY LEVEL SOLDERING CONDITIONS
VESD09A4A-HSF LLP75-6L 49 4.2 mg UL 94 V-0 MSL level 1
(according J-STD-020) Peak temperature max. 260 °C
ABSOLUTE MAXIMUM RATINGS VESD09A4A-HSF
PARAMETER TEST CONDITIONS SYMBOL VALUE UNIT
Peak pulse current BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 1.5 A
Peak pulse power BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6);
acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 30 W
ESD immunity
Contact discharge acc. IEC 61000-4-2; 10 pulses
BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6) VESD ± 8 kV
Air discharge acc. IEC 61000-4-2; 10 pulses
BiAs-mode: each input (pin 1, 3 - 5) to ground (pin 2 and 6) VESD ± 10 kV
Operating temperature Junction temperature TJ-40 to +125 °C
Storage temperature TSTG -55 to +150 °C
VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 2Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
BiAs-MODE (4-line bidirectional asymmetrical protection mode)
With the VESD09A4A-HSF up to 4 signal- or data-lines (L1 to L4) can be protected against voltage transients. With pin 2
connected to ground and pin 1, 3, 4 and 6 connected to a signal- or data-line which has to be protected. As long as the voltage
level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the
protection diode between data line and ground offer a high isolation to the ground line. The protection device behaves like an
open switch.
As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode
becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The
clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance
(resistance and inductance) of the protection device.
Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of
the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level.
Due to the different clamping levels in forward and reverse direction the VESD09A4A-HSF clamping behaviour is bidirectional
and asymmetrical (BiAs).
Note
• BiAs mode (between pin 1 and pin 2).
If a higher surge current or peak pulse current (IPP) is needed, some protection diodes in the VESD09A4A-HSF can also be used
in parallel in order to "multiply" the performance. If two diodes are switched in parallel you get
• double surge power = double peak pulse current (2 x IPPM)
• half of the line inductance = reduced clamping voltage
• half of the line resistance = reduced clamping voltage
• double line capacitance (2 x CD)
• double reverse leakage current (2 x IR)
ELECTRICAL CHARACTERISTICS VESD09A4A-HSF (Pin 1, 3, 4, or 5 to pin 2)
(Tamb = 25 °C, unless otherwise specified)
PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. MAX. UNIT
Protection paths Number of lines which can be protected Nchannel - - 1 lines
Reverse stand-off voltage Max. reverse working voltage VRWM --9V
Reverse voltage at IR = 0.1 μA VR9--V
Reverse current at VR = VRWM = 9 V IR- < 0.01 0.1 μA
Reverse breakdown voltage at IR = 1 mA VBR 11.2 13 V
Reverse clamping voltage at IPP = 1.5 A, acc. IEC 61000-4-5 VC-23V
Forward clamping voltage at IF = 1.5 A, acc. IEC 61000-4-5 VF-2V
Capacitance at VR = 0 V; f = 1 MHz CD-6.210pF
at VR = 4.5 V; f = 1 MHz CD-3.24pF
21003
L4
L1
L3
L2
123
65
4
L1 L2
21004
123
65
4
VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 3Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified)
Fig. 1 - ESD Discharge Current Wave Form
acc. IEC 61000-4-2 (330 /150 pF)
Fig. 2 - 8/20 µs Peak Pulse Current Wave Form
acc. IEC 61000-4-5
Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR
Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF
Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR
Fig. 6 - Typical Peak Clamping Voltage VC vs.
Peak Pulse Current IPP
0 %
20 %
40 %
60 %
80 %
100 %
010203040
Time (µs)
I
PPM
20 µs to 50 %
8 µs to 100 %
20548
0
1
2
3
4
5
6
7
0246810
VR (V)
CD (pF)
20935
f = 1 MHz
0.001
0.01
0.1
1
10
100
0.5 0.6 0.7 0.80.9 1
V
F
(V)
I
F
(mA)
20936
0
2
4
6
8
10
12
14
0.01 0.1 1 10 100 1000 10000
IR (µA)
VR (V)
20937
- 5
0
5
10
15
20
25
012
IPP (A)
VC (V)
20938
VC
positive surge
negative surge
Measured
acc. IEC 61000-4-5
(8/20 µs - wave form)
VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 4Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Fig. 7 - Typical Clamping Performance at + 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 8 - Typical Clamping Performance at - 8 kV
Contact Discharge (acc. IEC 61000-4-2)
Fig. 9 - Typical Peak Clamping Voltage at ± ESD Contact Discharge
(acc. IEC 61000-4-2)
- 20
0
20
40
60
80
100
120
- 10 0 10 20 30 40 50 60 70 8090
acc. IEC 61000-4-2
+ 8 kV
contact discharge
t (ns)
V
C-ESD
(V)
20939
- 70
- 60
- 50
- 40
- 30
- 20
- 10
0
10
20
30
- 100 102030405060708090
acc. IEC 61000-4-2
- 8 kV
contact discharge
t (ns)
V
C-ESD
(V)
20940
- 80
- 60
- 40
- 20
0
20
40
60
80
100
120
0 2000 4000 6000 8000 10000
VESD (kV)
VC-ESD (V)
20941
acc. IEC 61000-4-2 contact discharge
V
C-ESD
positive discharge
negative discharge
VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 5Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
PACKAGE DIMENSIONS in millimeters (Inches): LLP75-6L
1.05 (0.041)
0.5 (0.020)
0.95 (0.037)
Heat sink
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.3 (0.012)
0.2 (0.008)
0.55 (0.022)
0.45 (0.018)
0.6 (0.024)
0.25 (0.010)
0.05 (0.002)
0 (0.000)
0.15 (0.006)
0.60 (0.023)
0.54 (0.021)
1.65 (0.065)
1.55 (0.061)
1.65 (0.065)
1.55 (0.061)
Pin 1 marking
0.5 (0.020) 0.5 (0.020)
0.3 (0.012) 0.3 (0.012)
0.15 (0.006) 0.15 (0.006)
0.5 (0.020)
0.5 (0.020)
1 (0.039)
0.25 (0.010)
Solder resist mask
Solder pad
Document no.:S8-V-3906.02-010 (4)
Rev. 4 - Date: 21. March 2006
20454
Created - Date: 04. MAY 2005
Foot print recommendation:
1 (0.039)
1 (0.039)
VESD09A4A-HSF
www.vishay.com Vishay Semiconductors
Rev. 1.7, 04-Jan-2019 6Document Number: 81834
For technical questions, contact: ESDprotection@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
LLP75-6x
F 5
S 9
Pin 1 - location
Pad layout - view from top / seen at bottom side
S8-V-3906.02-004 (4)
10.01.2005
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Revision: 01-Jan-2021 1Document Number: 91000
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