User's Manual 16 RL78/G12 User's Manual: Hardware 16-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.1.10 Sep 2012 Notice 1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. You are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. 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Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Electronics products, or if you have any other inquiries. (Note 1) "Renesas Electronics" as used in this document means Renesas Electronics Corporation and also includes its majorityowned subsidiaries. (Note 2) "Renesas Electronics product(s)" means any product developed or manufactured by or for Renesas Electronics. (2012.4) NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). (2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. (3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. (4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. (5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. (6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device. How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the RL78/G12 and design and develop application systems and programs for these devices. Purpose This manual is intended to give users an understanding of the functions described in the Organization below. Organization The RL78/G12 manual is separated into two parts: this manual and the software edition (common to the RL78/G12 family). RL78/G12 RL78 family User's Manual User's Manual Hardware Software * Pin functions * CPU functions * Internal block functions * Instruction set * Interrupts * Explanation of each instruction * Other on-chip peripheral functions * Electrical specifications How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical engineering, logic circuits, and microcontrollers. * To gain a general understanding of functions: Read this manual in the order of the CONTENTS. The mark "<R>" shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. * How to interpret the register format: For a bit number enclosed in angle brackets, the bit name is defined as a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. * To know details of the RL78/G12 Microcontroller instructions: Refer to the separate document RL78 (R01US0015E). Family Software User's Manual Conventions Data significance: Higher digits on the left and lower digits on the right Active low representations: xxx (overscore over pin and signal name) Note: Footnote for item marked with Note in the text Caution: Information requiring particular attention Remark: Supplementary information ...xxxx or xxxxB Numerical representations: Binary ...xxxx Decimal Hexadecimal Related Documents ...xxxxH The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. RL78/G12 User's Manual Hardware R01UH0200E RL78 Microcontroller Software User's Manual R01US0015E Documents Related to Flash Memory Programming Document Name PG-FP5 Flash Memory Programmer User's Manual Document No. R20UT0008E Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. Other Documents Document Name RENESAS MICROCOMPUTER GENERAL CATALOG Document No. R01CS0001E Semiconductor Device Mount Manual Note Quality Grades on NEC Semiconductor Devices C11531E NEC Semiconductor Device Reliability/Quality Control System C10983E Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E Note See the "Semiconductor Device Mount Manual" website (http://www.renesas.com/prod/package/manual/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing. All trademarks and registered trademarks are the property of their respective owners. EEPROM is a trademark of Renesas Electronics Corporation. Windows, Windows NT and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash(R) technology licensed from Silicon Storage Technology, Inc. CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Differences between R5F102 and R5F103 ................................................................................ 1 1.1.1 Data Flash .......................................................................................................................................... 1 1.1.3 Peripheral Functions .......................................................................................................................... 2 1.2 Features........................................................................................................................................... 3 1.3 List of Part Numbers ...................................................................................................................... 5 1.4 Pin Configuration (Top View) ........................................................................................................ 6 1.4.1 20-pin products................................................................................................................................... 6 1.4.2 24-pin products................................................................................................................................... 7 1.4.3 30-pin products................................................................................................................................... 8 1.5 Pin Identification............................................................................................................................. 9 1.6 Block Diagram .............................................................................................................................. 10 1.6.1 20-pin products................................................................................................................................. 10 1.6.2 24-pin products................................................................................................................................. 11 1.6.3 30-pin products................................................................................................................................. 12 1.7 Outline of Functions..................................................................................................................... 13 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 15 2.1 Port Functions .............................................................................................................................. 15 2.1.1 20-pin products................................................................................................................................. 15 2.1.2 24-pin products................................................................................................................................. 16 2.1.3 30-pin products .............................................................................................................................. 17 2.2 Functions other than port pins ................................................................................................... 19 2.2.1 Functions for each product ............................................................................................................... 19 2.2.2 Description of Functions ................................................................................................................... 20 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins ........................................... 21 CHAPTER 3 CPU ARCHITECTURE ...................................................................................................... 25 3.1 Memory Space .............................................................................................................................. 25 3.1.1 Internal program memory space....................................................................................................... 33 3.1.2 Mirror area........................................................................................................................................ 37 3.1.3 Internal data memory space ............................................................................................................. 38 3.1.4 Special function register (SFR) area ................................................................................................ 40 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 40 3.1.6 Data memory addressing ................................................................................................................. 40 3.2 Processor Registers..................................................................................................................... 47 3.2.1 Control registers ............................................................................................................................... 47 Index-1 3.2.2 General-purpose registers................................................................................................................ 49 3.2.3 ES and CS registers ......................................................................................................................... 51 3.2.4 Special function registers (SFRs) ..................................................................................................... 52 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) ........................... 57 3.3 Instruction Address Addressing................................................................................................. 63 3.3.1 Relative addressing.......................................................................................................................... 63 3.3.2 Immediate addressing ...................................................................................................................... 63 3.3.3 Table indirect addressing ................................................................................................................. 64 3.3.4 Register direct addressing................................................................................................................ 64 3.4 Addressing for Processing Data Addresses ............................................................................. 65 3.4.1 Implied addressing ........................................................................................................................... 65 3.4.2 Register addressing ......................................................................................................................... 65 3.4.3 Direct addressing ............................................................................................................................. 66 3.4.4 Short direct addressing .................................................................................................................... 67 3.4.5 SFR addressing................................................................................................................................ 68 3.4.6 Register indirect addressing ............................................................................................................. 69 3.4.7 Based addressing............................................................................................................................. 70 3.4.8 Based indexed addressing ............................................................................................................... 73 3.4.9 Stack addressing.............................................................................................................................. 74 CHAPTER 4 PORT FUNCTIONS ........................................................................................................... 77 4.1 Port Functions .............................................................................................................................. 77 4.2 Port Configuration........................................................................................................................ 77 4.2.1 20, 24-pin products........................................................................................................................... 78 4.2.2 30-pin products............................................................................................................................... 100 4.3 Registers Controlling Port Function ........................................................................................ 124 4.4 Port Function Operations .......................................................................................................... 135 4.4.1 Writing to I/O port ........................................................................................................................... 135 4.4.2 Reading from I/O port ..................................................................................................................... 135 4.4.3 Operations on I/O port .................................................................................................................... 135 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) ....................................... 136 4.5 Settings of Port Related Register When Using Alternate Function ...................................... 138 4.6 Cautions When Using Port Function........................................................................................ 145 4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) ............................................... 145 4.6.2 Notes on specifying the pin settings .............................................................................................. 146 CHAPTER 5 CLOCK GENERATOR .................................................................................................... 147 5.1 Functions of Clock Generator................................................................................................... 147 5.2 Configuration of Clock Generator ............................................................................................ 148 5.3 Registers Controlling Clock Generator.................................................................................... 150 5.3.1 Clock operation mode control register (CMC) ................................................................................ 151 Index-2 5.3.2 System clock control register (CKC)............................................................................................... 152 5.3.3 Clock operation status control register (CSC) ................................................................................ 153 5.3.4 Oscillation stabilization time counter status register (OSTC).......................................................... 154 5.3.5 Oscillation stabilization time select register (OSTS) ....................................................................... 156 5.3.6 Peripheral enable register 0 (PER0)............................................................................................... 158 5.3.7 Operation speed mode control register (OSMC) ............................................................................ 159 5.3.8 High-speed on-chip oscillator frequency selection register (HOCODIV) ........................................ 160 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) ............................................................ 160 5.4 System Clock Oscillator ............................................................................................................ 162 5.4.1 X1 oscillator.................................................................................................................................... 162 5.4.2 High-speed on-chip oscillator ......................................................................................................... 165 5.4.3 Low-speed on-chip oscillator .......................................................................................................... 165 5.5 Clock Generator Operation ....................................................................................................... 165 5.6 Controlling Clock........................................................................................................................ 167 5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 167 5.6.2 Example of setting X1 oscillation clock........................................................................................... 168 5.6.3 CPU clock status transition diagram............................................................................................... 169 5.6.4 Condition before changing CPU clock and processing after changing CPU clock ......................... 172 5.6.5 Time required for switchover of CPU clock and main system clock ............................................... 173 5.6.6 Conditions before clock oscillation is stopped ................................................................................ 173 5.7 Resonator and Oscillator Constants ......................................................................................... 174 CHAPTER 6 TIMER ARRAY UNIT...................................................................................................... 176 6.1 Functions of Timer Array Unit................................................................................................... 177 6.1.1 Independent channel operation function ........................................................................................ 177 6.1.2 Simultaneous channel operation function....................................................................................... 178 6.1.3 8-bit timer operation function (channels 1 and 3 only) .................................................................... 179 6.2 Configuration of Timer Array Unit ............................................................................................ 180 6.3 Registers Controlling Timer Array Unit.................................................................................... 189 6.3.1 Peripheral enable register 0 (PER0)............................................................................................... 190 6.3.2 Timer clock select register 0 (TPS0) .............................................................................................. 191 6.3.3 Timer mode register 0n (TMR0n) ................................................................................................... 193 6.3.4 Timer status register 0n (TSR0n) ................................................................................................... 198 6.3.5 Timer channel enable status register 0 (TE0)................................................................................. 199 6.3.6 Timer channel start register 0 (TS0)............................................................................................... 200 6.3.7 Timer channel stop register 0 (TT0) ............................................................................................... 201 6.3.8 Timer input select register 0 (TIS0) ................................................................................................ 202 6.3.9 Timer output enable register 0 (TOE0)........................................................................................... 203 6.3.10 Timer output register 0 (TO0) ....................................................................................................... 204 6.3.11 Timer output level register 0 (TOL0)............................................................................................. 205 6.3.12 Timer output mode register 0 (TOM0) .......................................................................................... 206 Index-3 6.3.13 Noise filter enable register 1 (NFEN1).......................................................................................... 207 6.3.14 Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4) ........................................................ 208 6.4 Basic Rules of Timer Array Unit ............................................................................................... 209 6.4.1 Basic Rules of Simultaneous Channel Operation Function ............................................................ 209 6.4.2 Basic rules of 8-bit timer operation function (Only Channels 1 and 3)............................................ 211 6.5 Operation of Counter ................................................................................................................. 212 6.5.1 Count clock (fTCLK) ....................................................................................................................... 212 6.5.2 Start timing of counter .................................................................................................................... 214 6.5.3 Counter Operation.......................................................................................................................... 215 6.6 Channel Output (TO0n pin) Control.......................................................................................... 220 6.6.1 TO0n pin output circuit configuration.............................................................................................. 220 6.6.2 TO0n Pin Output Setting ................................................................................................................ 221 6.6.3 Cautions on Channel Output Operation ......................................................................................... 222 6.6.4 Collective manipulation of TO0n bit................................................................................................ 226 6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start................................................................ 227 6.7 Independent Channel Operation Function of Timer Array Unit............................................. 228 6.7.1 Operation as interval timer/square wave output ............................................................................. 228 6.7.2 Operation as external event counter .............................................................................................. 234 6.7.3 Operation as frequency divider (channel 0 of unit 0 only) .............................................................. 239 6.7.4 Operation as input pulse interval measurement ............................................................................. 243 6.7.5 Operation as input signal high-/low-level width measurement........................................................ 248 6.7.6 Operation as delay counter ............................................................................................................ 252 6.8 Simultaneous Channel Operation Function of Timer Array Unit .......................................... 257 6.8.1 Operation as one-shot pulse output function .................................................................................. 257 6.8.2 Operation as PWM function............................................................................................................ 264 6.8.3 Operation as multiple PWM output function ................................................................................... 271 6.9 Cautions When Using Timer Array Unit ................................................................................... 279 6.9.1 Cautions When Using Timer output................................................................................................ 279 CHAPTER 7 12-BIT INTERVAL TIMER ................................................................................................ 281 7.1 Functions of 12-bit Interval Timer............................................................................................. 281 7.2 Configuration of 12-bit Interval Timer ...................................................................................... 281 7.3 Registers Controlling 12-bit Interval Timer.............................................................................. 282 7.3.1 Peripheral enable register 0 (PER0)............................................................................................... 282 7.3.2 Operation speed mode control register (OSMC) ............................................................................ 283 7.3.3. Interval timer control register (ITMC)............................................................................................. 284 7.4 12-bit Interval Timer Operation ................................................................................................. 285 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER................................................. 286 8.1 Functions of Clock Output/Buzzer Output Controller ............................................................ 286 8.2 Configuration of Clock Output/Buzzer Output Controller...................................................... 287 Index-4 8.3 Registers Controlling Clock Output/Buzzer Output Controller ............................................. 287 8.3.1 Clock output select registers 0, 1 (CKS0, CKS1) ........................................................................... 287 8.3.2 Port mode register 1, 3 (PM1, PM3)............................................................................................... 289 8.4 Operations of Clock Output/Buzzer Output Controller .......................................................... 290 8.4.1 Operation as output pin .................................................................................................................. 290 CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 291 9.1 Functions of Watchdog Timer................................................................................................... 291 9.2 Configuration of Watchdog Timer ............................................................................................ 292 9.3 Register Controlling Watchdog Timer...................................................................................... 293 9.3.1 Watchdog timer enable register (WDTE)........................................................................................ 293 9.4 Operation of Watchdog Timer................................................................................................... 294 9.4.1 Controlling operation of watchdog timer ......................................................................................... 294 9.4.2 Setting overflow time of watchdog timer ......................................................................................... 295 9.4.3 Setting window open period of watchdog timer .............................................................................. 296 9.4.4 Setting watchdog timer interval interrupt ........................................................................................ 297 CHAPTER 10 A/D CONVERTER ......................................................................................................... 298 10.1 Function of A/D Converter....................................................................................................... 298 10.2 Configuration of A/D Converter .............................................................................................. 300 10.3 Registers Used in A/D Converter............................................................................................ 302 10.3.1 Peripheral enable register 0 (PER0)............................................................................................. 303 10.3.2 A/D converter mode register 0 (ADM0) ........................................................................................ 304 10.3.3 A/D converter mode register 1 (ADM1) ........................................................................................ 312 10.3.4 A/D converter mode register 2 (ADM2) ........................................................................................ 313 10.3.5 10-bit A/D conversion result register (ADCR) ............................................................................... 315 10.3.6 8-bit A/D conversion result register (ADCRH) .............................................................................. 316 10.3.7 Analog input channel specification register (ADS)........................................................................ 317 10.3.8 Conversion result comparison upper limit setting register (ADUL) ............................................... 319 10.3.9 Conversion result comparison lower limit setting register (ADLL) ................................................ 319 10.3.10 A/D test register (ADTES) .......................................................................................................... 320 10.3.11 A/D port configuration register (ADPC)....................................................................................... 321 10.3.12 Port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14)... 322 10.3.13 Port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14) ............... 323 10.4 A/D Converter Conversion Operations .................................................................................. 325 10.5 Input Voltage and Conversion Results .................................................................................. 327 10.6 A/D Converter Operation Modes............................................................................................. 328 10.6.1 Software trigger mode (select mode, sequential conversion mode) ............................................. 328 10.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 329 10.6.3 Software trigger mode (scan mode, sequential conversion mode)............................................... 330 10.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 331 Index-5 10.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) ............................... 332 10.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 333 10.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) ................................. 334 10.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 335 10.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 336 10.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)..................................... 337 10.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) .................................... 338 10.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 339 10.7 A/D Converter Setup Flowchart .............................................................................................. 340 10.7.1 Setting up software trigger mode.................................................................................................. 341 10.7.2 Setting up hardware trigger no-wait mode.................................................................................... 342 10.7.3 Setting up hardware trigger wait mode ......................................................................................... 343 10.7.4 Setup when temperature sensor output/internal reference voltage output is selected (example for software trigger mode and one-shot conversion mode) ......................................... 344 10.7.5 Setting up test mode .................................................................................................................... 345 10.8 SNOOZE mode function........................................................................................................... 346 10.9 How to Read A/D Converter Characteristics Table............................................................... 349 10.10 Cautions for A/D Converter ................................................................................................... 351 CHAPTER 11 SERIAL ARRAY UNIT.................................................................................................. 355 11.1 Functions of Serial Array Unit................................................................................................ 356 11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) ........................................................................... 356 11.1.2 UART (UART0 to UART2)............................................................................................................ 357 11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20) .................................................................................... 358 11.2 Configuration of Serial Array Unit .......................................................................................... 359 11.3 Registers Controlling Serial Array Unit.................................................................................. 365 11.3.1 Peripheral enable register 0 (PER0)............................................................................................. 366 11.3.2 Serial clock select register m (SPSm) .......................................................................................... 367 11.3.3 Serial mode register mn (SMRmn) ............................................................................................... 368 11.3.4 Serial communication operation setting register mn (SCRmn) ..................................................... 369 11.3.5 Higher 7 bits of the serial data register mn (SDRmn) ................................................................... 372 11.3.6 Serial flag clear trigger register mn (SIRmn) ................................................................................ 373 11.3.7 Serial status register mn (SSRmn) ............................................................................................... 374 11.3.8 Serial channel start register m (SSm)........................................................................................... 376 11.3.9 Serial channel stop register m (STm) ........................................................................................... 377 11.3.10 Serial channel enable status register m (SEm) .......................................................................... 378 11.3.11 Serial output enable register m (SOEm)..................................................................................... 379 11.3.12 Serial output register m (SOm)................................................................................................... 380 11.3.13 Serial output level register m (SOLm) ........................................................................................ 381 11.3.14 Serial standby control register 0 (SSC0) .................................................................................... 382 11.3.15 Noise filter enable register 0 (NFEN0)........................................................................................ 383 Index-6 11.3.16 Port input mode register 0, 1 (PIM0, PIM1) ................................................................................ 384 11.3.17 Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) ........................................ 385 11.3.18 Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)......................................................... 386 11.4 Operation Stop Mode ............................................................................................................... 388 11.4.1 Stopping the operation by units .................................................................................................... 388 11.4.2 Stopping the operation by channels ............................................................................................. 389 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication ................... 390 11.5.1 Master transmission ..................................................................................................................... 391 11.5.2 Master reception........................................................................................................................... 400 11.5.3 Master transmission/reception...................................................................................................... 408 11.5.4 Slave transmission ....................................................................................................................... 417 11.5.5 Slave reception............................................................................................................................. 426 11.5.6 Slave transmission/reception........................................................................................................ 432 11.5.7 SNOOZE mode function (only CSI00) .......................................................................................... 441 11.5.8 Calculating transfer clock frequency............................................................................................. 445 11.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communication............................................................................. 447 11.6 Operation of UART (UART0 to UART2) Communication...................................................... 448 11.6.1 UART transmission ...................................................................................................................... 449 11.6.2 UART reception............................................................................................................................ 459 11.6.3 SNOOZE mode function (only UART0 reception) ........................................................................ 467 11.6.4 Calculating baud rate ................................................................................................................... 473 11.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication............................................................................................................................. 477 11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20) Communication.............................. 478 11.7.1 Address field transmission............................................................................................................ 480 11.7.2 Data transmission......................................................................................................................... 485 11.7.3 Data reception .............................................................................................................................. 488 11.7.4 Stop condition generation............................................................................................................. 492 11.7.5 Calculating transfer rate ............................................................................................................... 493 11.7.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC11, IIC20) communication ................................................................................ 495 CHAPTER 12 SERIAL INTERFACE IICA ........................................................................................... 496 12.1 Functions of Serial Interface IICA........................................................................................... 496 12.2 Configuration of Serial Interface IICA .................................................................................... 499 12.3 Registers Controlling Serial Interface IICA............................................................................ 502 12.3.1 Peripheral enable register 0 (PER0)............................................................................................. 502 12.3.2 IICA control register 00 (IICCTL00) ............................................................................................. 502 12.3.3 IICA status register 0 (IICS0)........................................................................................................ 507 12.3.4 IICA flag register 0 (IICF0)............................................................................................................ 509 Index-7 12.3.5 IICA control register 01 (IICCTL01) .............................................................................................. 511 12.3.6 IICA low-level width setting register 0 (IICWL0) ........................................................................... 513 12.3.7 IICA high-level width setting register 0 (IICWH0) ......................................................................... 513 12.3.8 Port mode register 6 (PM6) .......................................................................................................... 514 2 12.4 I C Bus Mode Functions .......................................................................................................... 515 12.4.1 Pin configuration........................................................................................................................... 515 12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers...................................................... 516 2 12.5 I C Bus Definitions and Control Methods .............................................................................. 517 12.5.1 Start conditions............................................................................................................................. 517 12.5.2 Addresses .................................................................................................................................... 518 12.5.3 Transfer direction specification..................................................................................................... 518 12.5.4 Acknowledge (ACK) ..................................................................................................................... 519 12.5.5 Stop condition............................................................................................................................... 520 12.5.6 Wait .............................................................................................................................................. 521 12.5.7 Canceling wait .............................................................................................................................. 523 12.5.8 Interrupt request (INTIICA0) generation timing and wait control................................................... 524 12.5.9 Address match detection method ................................................................................................. 525 12.5.10 Error detection............................................................................................................................ 525 12.5.11 Extension code........................................................................................................................... 526 12.5.12 Arbitration ................................................................................................................................... 527 12.5.13 Wakeup function......................................................................................................................... 529 12.5.14 Communication reservation........................................................................................................ 532 12.5.15 Cautions ..................................................................................................................................... 536 12.5.16 Communication operations......................................................................................................... 537 12.5.17 Timing of I2C interrupt request (INTIICA0) occurrence ............................................................... 545 12.6 Timing Charts ........................................................................................................................... 566 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR ......................................... 581 13.1 Functions of Multiplier and Divider/Multiply-Accumulator ................................................. 581 13.2 Configuration of Multiplier and Divider/Multiply-Accumulator .......................................... 581 13.3 Register Controlling Multiplier and Divider/Multiply-Accumulator.................................... 587 13.3.1 Multiplication/division control register (MDUC)............................................................................. 587 13.4 Operations of Multiplier and Divider/Multiply-Accumulator ............................................... 589 13.4.1 Multiplication (unsigned) operation .............................................................................................. 589 13.4.2 Multiplication (signed) operation .................................................................................................. 590 13.4.3 Multiply-accumulation (unsigned) operation................................................................................. 591 13.4.4 Multiply-accumulation (signed) operation..................................................................................... 593 13.4.5 Division operation ........................................................................................................................ 595 CHAPTER 14 DMA CONTROLLER ..................................................................................................... 597 14.1 Functions of DMA Controller .................................................................................................. 597 Index-8 14.2 Configuration of DMA Controller ............................................................................................ 598 14.3 Registers Controlling DMA Controller ................................................................................... 601 14.3.1 DMA mode control register n (DMCn) .......................................................................................... 602 14.3.2 DMA operation control register n (DRCn)..................................................................................... 604 14.4 Operation of DMA Controller................................................................................................... 605 14.4.1 Operation procedure .................................................................................................................... 605 14.4.2 Transfer mode .............................................................................................................................. 606 14.4.3 Termination of DMA transfer ........................................................................................................ 606 14.5 Example of Setting of DMA Controller ................................................................................... 607 14.5.1 CSI consecutive transmission ...................................................................................................... 607 14.5.2 Consecutive capturing of A/D conversion results ......................................................................... 609 14.5.3 UART consecutive reception + ACK transmission........................................................................ 611 14.5.4 Holding DMA transfer pending by DWAITn bit ............................................................................. 613 14.5.5 Forced termination by software .................................................................................................... 614 14.6 Cautions on Using DMA Controller ........................................................................................ 616 CHAPTER 15 INTERRUPT FUNCTIONS............................................................................................. 618 15.1 Interrupt Function Types ......................................................................................................... 618 15.2 Interrupt Sources and Configuration ..................................................................................... 618 15.3 Registers Controlling Interrupt Functions............................................................................. 625 15.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)............................................ 629 15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H) ................................. 631 15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) ...................................................................... 633 15.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) ................................................................................................................ 637 15.3.5 Program status word (PSW)......................................................................................................... 638 15.4 Interrupt Servicing Operations ............................................................................................... 639 15.4.1 Maskable interrupt request acknowledgment ............................................................................... 639 15.4.2 Software interrupt request acknowledgment ................................................................................ 642 15.4.3 Multiple interrupt servicing............................................................................................................ 643 15.4.4 Interrupt request hold ................................................................................................................... 647 CHAPTER 16 KEY INTERRUPT FUNCTION ..................................................................................... 648 16.1 Functions of Key Interrupt ...................................................................................................... 648 16.2 Configuration of Key Interrupt ................................................................................................ 649 16.3 Register Controlling Key Interrupt ......................................................................................... 649 16.3.1 Key return control register (KRCTL) ............................................................................................. 650 16.3.2 Key return mode control registers (KRM0, KRM1) ....................................................................... 650 16.3.3 Key return flag register (KRF)....................................................................................................... 652 16.3.4 Port mode registers 0, 4, 6, 12 (PM0, PM4, PM6, PM12) ............................................................ 652 Index-9 CHAPTER 17 STANDBY FUNCTION .................................................................................................. 653 17.1 Standby Function and Configuration ..................................................................................... 653 17.1.1 Standby function........................................................................................................................... 653 17.1.2 Registers controlling standby function.......................................................................................... 654 17.2 Standby Function Operation ................................................................................................... 657 17.2.1 HALT mode .................................................................................................................................. 657 17.2.2 STOP mode.................................................................................................................................. 661 17.2.3 SNOOZE mode ............................................................................................................................ 666 CHAPTER 18 RESET FUNCTION........................................................................................................ 668 18.1 Register for Confirming Reset Source ................................................................................... 675 18.1.1 Reset Control Flag Register (RESF) ............................................................................................. 675 CHAPTER 19 POWER-ON-RESET CIRCUIT ...................................................................................... 677 19.1 Functions of Power-on-reset Circuit ...................................................................................... 677 19.2 Configuration of Power-on-reset Circuit................................................................................ 678 19.3 Operation of Power-on-reset Circuit ...................................................................................... 678 19.4 Cautions for Power-on-reset Circuit....................................................................................... 682 CHAPTER 20 VOLTAGE DETECTOR ................................................................................................... 684 20.1 Functions of Voltage Detector ................................................................................................ 684 20.2 Configuration of Voltage Detector.......................................................................................... 685 20.3 Registers Controlling Voltage Detector ................................................................................. 685 20.3.1 Voltage detection register (LVIM) ................................................................................................. 686 20.3.2 Voltage detection level register (LVIS) ......................................................................................... 687 20.4 Operation of Voltage Detector ................................................................................................ 690 20.4.1 When used as reset mode............................................................................................................ 690 20.4.2 When used as interrupt mode ...................................................................................................... 692 20.4.3 When used as interrupt and reset mode ...................................................................................... 694 20.5 Cautions for Voltage Detector................................................................................................. 699 CHAPTER 21 SAFETY FUNCTIONS ..................................................................................................... 701 21.1 Overview of Safety Functions ................................................................................................. 701 21.2 Registers Used by Safety Functions ...................................................................................... 702 21.3 Operation of Safety Functions ................................................................................................ 702 21.3.1 CRC operation function (general-purpose CRC) .......................................................................... 702 21.3.2 RAM parity error detection function .............................................................................................. 705 21.3.3 RAM guard function...................................................................................................................... 706 21.3.4 SFR guard function ...................................................................................................................... 707 21.3.5 Invalid memory access detection function .................................................................................... 708 Index-10 21.3.6 Frequency detection function ....................................................................................................... 709 21.3.7 A/D test function ........................................................................................................................... 711 CHAPTER 22 REGULATOR ................................................................................................................... 715 22.1 Overview of Regulators ........................................................................................................... 715 CHAPTER 23 OPTION BYTE............................................................................................................... 716 23.1 Functions of Option Bytes ...................................................................................................... 716 23.1.1 User option byte (000C0H to 000C2H)......................................................................................... 716 23.1.2 On-chip debug option byte (000C3H) ........................................................................................... 717 23.2 Format of User Option Byte .................................................................................................... 718 23.3 Format of On-chip Debug Option Byte................................................................................... 722 23.4 Setting of Option Byte.............................................................................................................. 723 CHAPTER 24 FLASH MEMORY .......................................................................................................... 724 24.1 Writing to Flash Memory by Using Flash Memory Programmer ......................................... 725 24.1.1 Programming environment ........................................................................................................... 726 24.1.2 Communication mode .................................................................................................................. 726 24.2 Writing to Flash Memory by Using External Device (that Incorporates UART) ................. 727 24.2.1 Programming environment ........................................................................................................... 727 24.2.2 Communication mode .................................................................................................................. 728 24.3 Connection of Pins on Board.................................................................................................. 729 24.3.1 P40/TOOL0 pin ............................................................................................................................ 729 24.3.2 RESET pin.................................................................................................................................... 729 24.3.3 Port pins ....................................................................................................................................... 730 24.3.4 REGC pins ................................................................................................................................... 730 24.3.5 X1 and X2 pins ............................................................................................................................. 730 24.3.6 Power supply................................................................................................................................ 730 24.4 Data Flash ................................................................................................................................. 731 24.4.1 Data flash overview ...................................................................................................................... 731 24.4.2 Register controlling data flash memory ........................................................................................ 732 24.4.3 Procedure for accessing data flash memory ................................................................................ 733 24.5 Programming Method .............................................................................................................. 734 24.5.1 Controlling flash memory.............................................................................................................. 734 24.5.2 Flash memory programming mode............................................................................................... 735 24.5.3 Selecting communication mode.................................................................................................... 736 24.5.4 Communication commands .......................................................................................................... 737 24.5.5 Description of signature data........................................................................................................ 738 24.6 Security Settings ...................................................................................................................... 739 24.7 Flash Memory Programming by Self-Programming ............................................................. 741 Index-11 24. 7.1 Flash shield window function....................................................................................................... 743 CHAPTER 25 ON-CHIP DEBUG FUNCTION ..................................................................................... 744 25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12 ................................................. 744 25.2 On-Chip Debug Security ID ..................................................................................................... 746 25.3 Securing of User Resources ................................................................................................... 746 CHAPTER 26 BCD CORRECTION CIRCUIT ..................................................................................... 748 26.1 BCD Correction Circuit Function............................................................................................ 748 26.2 Registers Used by BCD Correction Circuit ........................................................................... 748 26.3 BCD Correction Circuit Operation .......................................................................................... 749 CHAPTER 27 INSTRUCTION SET........................................................................................................ 751 27.1 Conventions Used in Operation List ...................................................................................... 752 27.1.1 Operand identifiers and specification methods............................................................................. 752 27.1.2 Description of operation column ................................................................................................... 753 27.1.3 Description of flag operation column ............................................................................................ 754 27.1.4 PREFIX instruction ....................................................................................................................... 754 27.2 Operation List ........................................................................................................................... 755 CHAPTER 28 ELECTRICAL SPECIFICATIONS ................................................................................. 772 28.1 Absolute Maximum Ratings .................................................................................................... 773 28.2 Oscillator Characteristics........................................................................................................ 774 28.2.1 X1 clock oscillator characteristics................................................................................................. 774 28.2.2 On-chip oscillator characteristics.................................................................................................. 774 28.3 DC Characteristics ................................................................................................................... 775 28.3.1 Pin characteristics ........................................................................................................................ 775 28.3.2 Supply current characteristics ...................................................................................................... 779 28.4 AC Characteristics ................................................................................................................... 784 28.5 Serial Communication Characteristics .................................................................................. 786 28.5.1 Serial array unit ............................................................................................................................ 786 28.5.2 Serial interface IICA ..................................................................................................................... 807 28.5.3 On-chip debug (UART)................................................................................................................. 807 28.6 Analog Characteristics ............................................................................................................ 808 28.6.1 A/D converter characteristics........................................................................................................ 808 28.6.2 Temperature sensor/internal reference voltage characteristics .................................................... 811 28.6.3 POR circuit characteristics ........................................................................................................... 811 28.6.4 LVD circuit characteristics ............................................................................................................ 812 28.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics............... 814 28.8 Flash Memory Programming Characteristics........................................................................ 814 Index-12 28.9 Timing Specs for Flash Memory Programming Switching Modes...................................... 815 CHAPTER 29 PACKAGE DRAWINGS ................................................................................................ 816 29.1 20-pin products......................................................................................................................... 816 29.2 24-pin products......................................................................................................................... 817 29.3 30-pin products......................................................................................................................... 818 APPENDIX A REVISION HISTORY ......................................................................................................... 819 A.1 Major Revisions in This Edition ............................................................................................... 819 A.2 Revision History of Preceding Editions .................................................................................. 823 Index-13 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 RL78/G12 RENESAS MCU CHAPTER 1 OUTLINE <R> 1.1 Differences between R5F102 and R5F103 The following are differences between the R5F102 and R5F103. Whether the data flash memory is mounted or not High-speed on-chip oscillator oscillation frequency accuracy Number of channels in serial interface Whether the DMA function is mounted or not Whether the safety function is mounted or not 1.1.1 Data Flash The data flash memory of 2 KB is mounted on the R5F102 but not on the R5F103. Product R5F102 Data Flash 2KB R5F1026A, R5F1027A, R5F102AA, R5F10269, R5F10279, R5F102A9, R5F10268, R5F10278, R5F102A8, R5F10267, R5F10277, R5F102A7, R5F10266 Note R5F103 Not mounted R5F1036A, R5F1037A, R5F103AA, R5F10369, R5F10379, R5F103A9, R5F10368, R5F10378 R5F103A8, R5F10367, R5F10377, R5F103A7, R5F10366 Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program specification, the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. Caution When the flash memory is rewritten via a user program, the flash ROM area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 1 RL78/G12 CHAPTER 1 OUTLINE 1.1.2 On-chip oscillator characteristics (1) High-speed on-chip oscillator oscillation frequency of the R5F102 Oscillator Condition MIN MAX Unit High-speed on-chip TA = -20 to +85 C oscillator oscillation TA = -40 to -20 C -1 +1 % -1.5 +1.5 MIN MAX Unit -5 +5 % frequency accuracy (2) High-speed on-chip oscillator oscillation frequency of the R5F103 Oscillator Condition High-speed on-chip TA = -40 to + 85 C oscillator oscillation frequency accuracy 1.1.3 Peripheral Functions R5F102 RL78/G12 20, 24 pin 30 pin product product Serial interface UART CSI 2 Simplified I C DMA function Safety function R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 R5F103 20, 24 pin 30 pin product product 1 channel 3 channels 1 channel 2 channels 3 channels 1 channel 2 channels 3 channels None 2 channels None CRC operation Yes None RAM guard Yes None SFR guard Yes None 2 RL78/G12 CHAPTER 1 OUTLINE 1.2 Features Minimum instruction execution time can be changed from high speed (0.04167 s @ 24 MHz operation with high speed on-chip oscillator clock) to ultra low-speed (1 s @ 1 MHz operation) <R> General-purpose registers: (8-bit register x 8) x 4 banks ROM: 2 KB to 16 KB, RAM: 256 bytes to 2 KB, data flash memory: -/2 KB High speed on-chip oscillator : 24/16/12/8/4/1 MHz(TYP) can be selected <R> Flash memory Prohibition of block erase and writing(security function) Dual operation: Execution of instructions in the code flash memory is possible while writing the data flash memory. Self-programming On-chip debug function On-chip power-on-reset (POR) circuit and voltage detector (LVD) On-chip watchdog timer (operable with the dedicated low speed on-chip oscillator clock) On-chip multiplier and divider/multiply-accumulator * 16 bits x 16 bits = 32 bits (Unsigned or signed) * 32 bits / 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned or signed) On-chip key interrupt function On-chip clock output/buzzer output controller On-chip BCD adjustment I/O ports: 18/22/26 (N-ch open drain: 2) Timer * 16-bit timer: 4/8 channels * Watchdog timer: 1 channel * 12-bit Interval timer: 1 channel Serial interface CSI: 1/2/3 channel * UART: 1/3 channel 2 * Simplified I C: 0/2/3 channel * I2C: 1 channel Different potential interface: Can connect to a 1.8/2.5/3 V device 8/10-bit resolution A/D converter: 8/11 channels Standby function: HALT, STOP, SNOOZE mode Power supply voltage: VDD = 1.8 to 5.5 V Operating ambient temperature: TA = -40 to +85C Remark The functions mounted depend on the product. See 1.6 Outline of Functions. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 3 RL78/G12 CHAPTER 1 OUTLINE ROM, RAM capacities Flash ROM Data flash RAM 20 pins 24 pins 30 pins 16 KB 2 KB 2 KB - - R5F102AA - - - 2 KB 1.5 KB - 12 KB 2KB 1 KB - 8 KB 2 KB 768B - 4 KB 2KB 512B - 2 KB 2 KB - 256B R5F1026A Note R5F1036A Note R5F103AA R5F1027A Note - R5F1037A Note - R5F102A9 R5F10269 Note R5F10279 Note R5F10369 Note R5F10379 Note R5F103A9 R5F10268 Note R5F10278 Note R5F102A8 R5F10368 Note R5F10378 Note R5F103A8 R5F10267 R5F10277 R5F102A7 R5F10367 R5F10377 R5F103A7 R5F10266 - - R5F10366 - - Note This is about 639 byte when the self-programing function and data flash function are used (For detail, see CHAPTER 3 CPU ARCHITECTURE R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 4 RL78/G12 CHAPTER 1 OUTLINE <R> 1.3 List of Part Numbers Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 Part No. R 5 F 1 0 2 A A A x x x S P Package type: SP : SSOP, 0.65 mm pitch NA : WQFN, 0.50 mm pitch ROM number (Omitted with blank products) Classification: A : Consumer applications, operating ambient temperature : -40C to 85C D : Industrial applications, operating ambient temperature : -40C to 85C ROM capacity: 6 : 7: 8: 9 : A : 2 KB 4 KB 8 KB 12 KB 16 KB Pin count: 6 : 20-pin 7 : 24-pin A : 30-pin RL78/G12 group 102 : Data flash is povided 103 : Data flash is not provided <R> <R> Memory type: F : Flash memory Renesas MCU Renesas semiconductor product <R> Pin count Package 20 pins 20-pin plastic SSOP (4.4 x 6.5) 24 pins 30 pins 24-pin plastic WQFN (4 x 4) 30-pin plastic SSOP (7.62 mm (300) ) Fields of Applica tion Part Number Mounted A R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP Not mounted D R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP Mounted A R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA Not mounted D R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA Mounted A R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP Not mounted D R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP Data flash <R> Note For fields of application, see Figure 1-1. Part Number, Memory Size, and Package of RL78/G12. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 5 RL78/G12 CHAPTER 1 OUTLINE 1.4 Pin Configuration (Top View) 1.4.1 20-pin products * 20-pin plastic SSOP (4.4 x 6.5) P20/ANI0/AVREFP P42/ANI21/SCK01Note/SCL01Note /TI03/TO03 P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1 P40/KR0/TOOL0 P125/KR1/SI01Note/RESET P137/INTP0 P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) VSS VDD <R> 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 P21/ANI1/AV REFM P22/ANI2 P23/ANI3 P10/ANI16/PCLBUZ0/SCK00/SCL00Note P11/ANI17/SI00/RxD0/SDA00 Note/TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P13/ANI19/TI00/TO00/INTP2 P14/ANI20/TI01/TO01/INTP3 P61/KR5/SDAA0/(RxD0) P60/KR4/SCLA0/(TxD0) Note Provided in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 6 RL78/G12 CHAPTER 1 OUTLINE * 24-pin plastic WQFN (4 x 4) P23/ANI3 P10/ANI16/PCLBUZ0/SCK00/SCL00Note P11/ANI17/SI00/RxD0/SDA00Note/TOOLRxD P12/ANI18/SO00/TxD0/TOOLTxD P13/ANI19/TI00/TO00/INTP2 P14/ANI20/TI01/TO01/INTP3 1.4.2 24-pin products exposed die pad 18 17 16 15 14 13 12 19 11 20 10 21 9 22 23 8 7 24 1 2 3 4 5 6 P61/KR5/SDAA00/(RxD0) P60/KR4/SCLA0/(TxD0) P03/KR9 P02/KR8/(SCK01/SCL01)Note P01/KR7/(SO01/SDA01)Note P00/KR6/(SI01)Note P125/KR1/SI01Note/RESET P137/INTP0 P122/KR2/X2/EXCLK/(TI02)/(INTP2) P121/KR3/X1/(TI03)/(INTP3) VSS VDD P22/ANI2 P21/ANI1/AVREFM P20/ANI0/AVREFP P42/ANI21/SCK01Note/SCL01Note/TI03/TO03 P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1 P40/KR0/TOOL0 <R> Note Provided in the R5F102 products. Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 7 RL78/G12 CHAPTER 1 OUTLINE 1.4.3 30-pin products * 30-pin plastic SSOP (7.62 mm (300)) P20/ANI0/AVREFP P01/ANI16/TO00/RxD1 P00/ANI17/TI00/TxD1 P120/ANI19 P40/TOOL0 RESET P137/INTP0 P122/X2/EXCLK P121/X1 REGC VSS VDD P60/SCLA0 P61/SDAA0 P31/TI03/TO03/INTP4/PCLBUZ0 <R> 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 P21/ANI1/AVREFM P22/ANI2 P23/ANI3 P147/ANI18 P10/SCK00/SCL00Note/(TI07/TO07) P11/SI00/RxD0/TOOLRxD/SDA00Note/(TI06/TO06) P12/SO00/TxD0/TOOLTxD/(TI05/TO05) P13/TxD2Note/SO20Note/(SDAA0)/(TI04/TO04) P14/RxD2Note/SI20Note/SDA20Note/(SCLA0) /(TI03/TO03) P15/PCLBUZ1/SCK20/SCL20/(TI02/TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P51/INTP2/SO11 P50/INTP1/SI11/SDA11 P30/INTP3/SCK11/SCL11 Note Provided in the R5F102 products. Caution Connect the REGC pin to VSS via capacitor (0.47 to 1 F). Remarks 1. For pin identification, see 1.5 Pin Identification. 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 8 RL78/G12 CHAPTER 1 OUTLINE 1.5 Pin Identification ANI0 to ANI3, <R> ANI16 to ANI22: REGC: Regulator Capacitance Analog input RESET: Reset Receive Data AVREFM: Analog Reference Voltage Minus RxD0 to RxD2: AVREFP: Analog reference voltage plus SCK00, SCK01, SCK11, EXCLK: External Clock Input SCK20: (Main System Clock) SCL00, SCL01, SCL11, INTP0 to INTP5 Interrupt Request From Peripheral SCL20, SCLA0: KR0 to KR9 Key Return SDA00, SDA01, SDA11, P00 to P03: Port 0 SDA20, SDAA0: Serial Data Input/Output P10 to P17: Port 1 SI00, SI01, SI11, SI20: Serial Data Input Serial Clock Input/Output Serial Clock Input/Output P20 to P23: Port 2 SO00, SO01, SO11, P30 to P31: Port 3 SO20: Serial Data Output P40 to P42: Port 4 TI00 to TI07: Timer Input P50, P51: Port 5 TO00 to TO07: Timer Output P60, P61: Port 6 TOOL0: Data Input/Output for Tool P120 to P122, P125: Port 12 TOOLRxD, TOOLTxD: Data Input/Output for External P137: Port 13 P147: Port 14 PCLBUZ0, PCLBUZ1: Device TxD0 to TxD2: Transmit Data Programmable Clock Output/ VDD: Power supply Buzzer Output VSS: Ground X1, X2: Crystal Oscillator (Main System Clock) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 9 RL78/G12 CHAPTER 1 OUTLINE 1.6 Block Diagram 1.6.1 20-pin products TAU0 (4 ch) TI00/TO00 ch00 TI01/TO01 ch01 TI02/TO02 ch02 TI03/TO03 ch03 Port 1 5 P10 to P14 Port 2 4 P20 to P23 Port 4 3 P40 to P42 Port 6 2 P60, P61 Port 12 3 P121, P122, P125 SAU0 (2 ch) RxD0 TxD0 UART0 SCK00 SI00 SO00 CSI00 SCK01 SI01 SO01 CSI01 Note SCL00 SDA00 IIC00 Note SCL01 SDA01 IIC01 Note Code flash: 16 KB Data flash: 2 KB Port 13 Note P137 Buzzer/clock output control Key return 6 ch 6 KR0 to KR5 Interrupt control 4 ch 4 INTP0 to INTP3 9 ANI2, ANI3, ANI16 to ANI22 ANI0/AVREFP ANI1/AVREFM Note DMA 2 ch RL78 CPU core RAM 1.5 KB TOOL0 PCLBUZ0 Interrupt control TOOL TOOL TxD RxD Window watchdog timer CRC Note 12-bit Interval timer On-chip debugger RESET Clock Generator + Reset Generator BCD adjustment Multiplier & divider/ multiply accumulator SCLA0 SDAA0 IICA0 X1 X2/EXCLK Power-on reset/low voltage detector Low-speed on-chip oscillator 15 kHz VDD <R> Main OSC 1 to 20 MHz 10-bit A/D converter 11 ch High-Speed on-chip oscillator 1 to 24 MHz VSS Note Provided for the R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 10 RL78/G12 CHAPTER 1 OUTLINE 1.6.2 24-pin products TAU0 (4 ch) TI00/TO00 ch00 TI01/TO01 ch01 TI02/TO02 ch02 TI03/TO03 ch03 Port 0 4 P00 to P03 Port 1 5 P10 to P14 Port 2 4 P20 to P23 Port 4 3 P40 to P42 Port 6 2 P60, P61 Port 12 3 P121, P122, P125 SAU0 (2 ch) RxD0 TxD0 UART0 SCK00 SI00 SO00 CSI00 SCK01 SI01 SO01 CSI01Note SCL00 SDA00 IIC00Note SCL01 SDA01 Note Code flash: 16 KB Data flash: 2 KBNote Port 13 P137 Buzzer/clock output control PCLBUZ0 Interrupt control Key return 10 ch 6 KR0 to KR9 Interrupt control 4 ch 4 INTP0 to INTP3 9 ANI2, ANI3, ANI16 to ANI22 ANI0/AVREFP ANI1/AVREFM Note DMA 2 ch RL78 CPU core IIC01 RAM 1.5KB TOOL TOOL TOOL0 TxD RxD Window watchdog timer CRCNote 12-bit Interval timer On-chip debugger RESET Clock Generator + Reset Generator BCD adjustment Multiplier & divider/ multiply accumulator SCLA0 SDAA0 IICA0 X1 X2/EXCLK Power-on reset/low voltage detector Low-speed on-chip oscillator 15 kHz V DD <R> Main OSC 1 to 20 MHz 10-bit A/D converter 11 ch High-Speed on-chip oscillator 1 to 24 MHz V SS Note Provided for the R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 11 RL78/G12 CHAPTER 1 OUTLINE 1.6.3 30-pin products TAU (8ch) TI00 TO00 ch0 TI01/TO01 ch1 TI02/TO02 ch2 PORT 0 2 P00, P01 TI03/TO03 ch3 PORT 1 8 P10 to P17 (TI04/TO04) ch4 PORT 2 4 P20 to P23 (TI05/TO05) ch5 PORT 3 2 P30, P31 (TI06/TO06) ch6 (TI07/TO07) ch7 PORT 4 CODE FLASH :16KB DATA FLASH:2KBNote SAU0 (4ch) RxD0 TxD0 RxD1 TxD1 SCK00 SI00 SO00 SCK11 SI11 SO11 SCL00 SDA00 SCL11 SDA11 UART0 INTERRUPT CONTROL CSI00 CSI11 RL78 CPU CORE 2 P50, P51 PORT 6 2 P60, P61 DMA Note 2ch P120 2 P121, P122 PORT 13 P137 PORT 14 P147 Note IIC00 Note IIC11 Note RAM 2KB Clock Generator + Reset Generator UART2 SCK20 SI20 SO20 CSI20 SCL20 SDA20 IIC20 BUZZER/CLOCK OUTPUT CONTROL INTERRUPT CONTROL 6ch SAU1 (2ch) Note RxD2 TxD2 PORT 5 PORT 12 Note UART1 P40 RESET Main OSC 1 to 20 MHz X1 X2/EXCLK POWERON RESET/ VOLTAGE DETECTOR TOOL TOOL TOOL0 TxD RxD ON-CHIP DEBUG Low Speed ON-CHIP OSCILLATOR 15 kHz VDD VSS 2 PCLBUZ0, PCLBUZ1 6 INTP0 to INTP5 6 ANI2, ANI3, ANI16 to ANI19 ANI0/AVREFP ANI1/AVREFM WINDOW WATCHDOG TIMER CRCNote 12-bit INTERVAL TIMER High Speed ON-CHIP OSCILLATOR 1 to 24 MHz 10-bit A/D CONVERTER 8ch VOLTAGE REGULATOR REGC BCD ADJUSTMENT MULTIPLIER& DIVIDER MULITIPLYACCUMULATOR SCLA0 SDAA0 <R> IICA0 Note Provided for the R5F102 products. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 12 RL78/G12 CHAPTER 1 OUTLINE 1.7 Outline of Functions This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H (except <R> timer output of R5F102Ax) (1/2) Item 20-pin R5F1026x <R> Code flash memory Data flash memory RAM <R> R5F1036x 2 to 16 KB R5F1027x R5F103Ax - 2 KB 512 B to 1.5 KB 512 B to 2KB 1 MB X1, X2 (crystal/ceramic) oscillation, external main system clock input (EXCLK) 1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 5.5 V system clock R5F102Ax - 2 KB Address space High-speed system clock R5F1037x 4 to 16 KB - 2 KB 30-pin Note 1 256 B to 1.5 KB Main <R> 24-pin High-speed on-chip HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V), oscillator clock LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V) Low-speed on-chip oscillator clock 15 kHz (TYP) General-purpose register (8-bit register x 8) x 4 banks Minimum instruction execution time 0.04167 s (High-speed on-chip oscillator clock: fIH = 24 MHz operation) 0.05 s (High-speed system clock: fMX = 20 MHz operation) Instruction set * Data transfer (8/16 bits) * Adder and subtractor/logical operation (8/16 bits) * Multiplication (8 bits x 8 bits) * Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc. I/O port Total 18 22 26 CMOS I/O 12 16 21 CMOS input 4 4 3 N-ch open-drain I/O 2 (6 V tolerance) Timer 16-bit timer 4 channels Watchdog timer 1 channel 12-bit Interval timer Timer output <R> Notes 1. <R> <R> 8 channels 1 channel 4/8 Note 2 (PWM Output Note 3 : 3/7 Note 2 ) The self-programming function cannot be used in the R5F10266 and R5F10366. 2. When PIOR0 is set to 1 in R5F102Az. 3. The number of PWM outputs varies depending on the setting of channels in use (the number of masters and slaves). (see 6.8.3 Operation as multiple PWM output function). <R> Caution When the flash memory is rewritten via a user program, the flash ROM area and RAM area are used because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01 User's Manual and RL78 Family Data Flash Library Type04 User's Manual. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 13 RL78/G12 CHAPTER 1 OUTLINE (2/2) Item 20-pin R5F1026x 24-pin R5F1036x R5F1027x 30-pin R5F1037x Clock output/buzzer output R5F102Ax R5F103Ax 1 2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz operation) 8/10-bit resolution A/D converter 11 channels 8 channels 2 Serial interface 2 CSI/UART/Simplified I C + CSI/Simplified I C [Product with data flash memory (30-pin)] 2 CSI/UART/Simplified I C x 3 CSI + UART 2 I C bus 1 channel Multiplier and divider/multiply- * 16 bits x 16 bits = 32 bits (unsigned or signed) accumulator * 32 bits / 32 bits = 32 bits (unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (unsigned or signed) DMA controller Vectored interrupt Internal sources External 2 channels - 2 channels - 2 channels - 18 16 18 16 26 19 5 Key interrupt 6 6 10 - * Reset by RESET pin Reset * Internal reset by watchdog timer * Internal reset by power-on-reset * Internal reset by voltage detector * Internal reset by illegal instruction execution Note * Internal reset by RAM parity error * Internal reset by illegal-memory access Power-on-reset circuit Voltage detector * Power-on-reset: 1.51 0.03 V * Power-down-reset: 1.50 0.03 V * Rising edge : 1.88 to 4.06 V (12 stages) * Falling edge : 1.84 to 3.98 V (12 stages) On-chip debug function Provided Power supply voltage VDD = 1.8 to 5.5 V Operating ambient temperature TA = -40 to +85C Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 14 RL78/G12 CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Port Functions Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions. 2.1.1 20-pin products Function I/O Name P10 I/O P11 After Reset Alternate Function Port 1. Analog ANI16/PCLBUZ0/ 5-bit I/O port. input port SCK00/SCL00 Input/output can be specified in 1-bit units. ANI17/SI00/RxD0/ Can be set to analog input. Specify then as either digital or SDA00/TOOLRxD analog in port mode control register 0 (PMC0). This register P12 ANI18/SO00/TxD0/ can be specified in 1-bit unit. TOOLTxD Input of P10, P11 can be set to TTL input buffer. P13 ANI19/TI00/TO00/ Output of P10 to P12 can be set to N-ch open-drain output (VDD P14 P20 Function I/O P21 tolerance). INTP2 When input port use of an on-chip pull-up resistor can be ANI20/TI01/TO01/ specified by a software setting (1-bit units). INTP3 Port 2. Analog ANI0/AVREFP 4-bit I/O port. input port ANI1/AVREFM Input/output can be specified in 1-bit units. P22 P23 P40 ANI2 Can be set to analog input. Specify then as either digital or ANI3 analog in A/D port configuration register (ADPC). I/O Port 4. 3-bit I/O port. P41 Input/output can be specified in 1-bit units. Input port KR0/TOOL0 Analog ANI22/SO01/SDA01/ input port TI02/TO02/INTP1 P41 and P42 pins can be set to analog input. Specify then as P42 ANI21/SCK01/SCL01/ either digital or analog in port mode control register 4 (PMC4). TI03/TO03 This register can be specified in 1-bit unit. Output of P41 can be set to N-ch open-drain output (VDD tolerance). When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P60 I/O Port 6 Input port 2-bit I/O port. P61 KR4/SCLA0/(TxD0) KR5/SDAA0/(RxD0) Input/output can be specified in 1-bit units. Output can be set to N-ch open-drain output (6-V tolerance). P121 Input P122 Port 12 Input port 3-bit I/O port. (TI03)/(INTP3) For P125, use of an on-chip pull-up resistor can be specified by KR2/X2/EXCLK/ a software setting. (TI02)/(INTP2) P125 P137 KR3/X1/ KR1/SI01/RESET Input Port 13 Input port INTP0 1-bit input port Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 15 RL78/G12 CHAPTER 2 PIN FUNCTIONS 2.1.2 24-pin products Function I/O Name P00 I/O Function Port 0. After Reset Input port 4-bit I/O port. P01 Alternate Function KR6/(SI01) KR7/(SO01/SDA01) Input/output can be specified in 1-bit units. P02 KR8/(SCK01/SCL01) Output of P01 can be set to N-ch open-drain output (VDD P03 KR9 tolerance). When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P10 I/O P11 Port 1. Analog ANI16/PCLBUZ0/ 5-bit I/O port. input port SCK00/SCL00 Input/output can be specified in 1-bit units. ANI17/SI00/RxD0/ Can be set to analog input. Specify then as either digital or SDA00/TOOLRxD analog in port mode control register 0 (PMC0). This register P12 ANI18/SO00/TxD0/ can be specified in 1-bit unit. TOOLTxD Input of P10, P11 can be set to TTL input buffer. P13 P14 Output of P10 to P12 can be set to N-ch open-drain output (VDD ANI19/TI00/TO00/ tolerance). INTP2 When input port use of an on-chip pull-up resistor can be ANI20/TI01/TO01/ specified by a software setting (1-bit units). P20 I/O P21 INTP3 Port 2. Analog ANI0/AVREFP 4-bit I/O port. input port ANI1/AVREFM Input/output can be specified in 1-bit units. P22 ANI2 Can be set to analog input. Specify then as either digital or P23 ANI3 analog in A/D port configuration register (ADPC). This register can be specified in 1-bit unit. P40 I/O Port 4. 3-bit I/O port. P41 Input/output can be specified in 1-bit units. Input port KR0/TOOL0 Analog ANI22/SO01/SDA01/ input port TI02/TO02/INTP1 P41 and P42 pins can be set to analog input. Specify then as P42 either digital or analog in port mode control register 4 (PMC4). ANI21/SCK01/SCL01/ This register can be specified in 1-bit unit. TI03/TO03 Output of P41 can be set to N-ch open-drain output (VDD tolerance). When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P60 I/O Port 6. Input port 2-bit I/O port. Input/output can be specified in 1-bit units. P61 KR4/SCLA0/(TxD0) KR5/SDAA0/(RxD0) Output can be set to N-ch open-drain output (6-V tolerance). P121 Input P122 Port 12. Input port (TI03)/(INTP3) For P125, use of an on-chip pull-up resistor can be specified by KR2/X2/EXCLK/ a software setting. (TI02)/(INTP2) P125 P137 KR3/X1/ 3-bit I/O port. KR1/SI01/RESET Input Port 13. Input port INTP0 1-bit input port. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 16 RL78/G12 2.1.3 CHAPTER 2 PIN FUNCTIONS 30-pin products (1/2) Function I/O Name P00 I/O P01 Function After Reset Alternate Function Port 0. Analog ANI17/TI00/TxD1 2-bit I/O port. input port ANI16/TO00/RxD1 Input port SCK00/SCL00/ Input/output can be specified in 1-bit units. Can be set to analog input. Specify then as either digital or analog in port mode control register 0 (PMC0). This register can be specified in 1-bit unit. Input of P01 can be set to TTL input buffer. Output of P00 can be set to N-ch open-drain output (VDD tolerance). When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P10 I/O P11 P12 Port 1. 8-bit I/O port. (TI07/TO07) Input/output can be specified in 1-bit units. SI00/RxD0/ Input of P10, P11, P13 to P17 can be set to TTL input buffer. TOOLRxD/SDA00/ Output of P10 to P15, P17 can be set to N-ch open-drain output (TI06/TO06) (VDD tolerance). SO00/TxD0/ When input port use of an on-chip pull-up resistor can be TOOLTXD/ specified by a software setting (1-bit units). (TI05/TO05) TxD2/SO20/ P13 (SDAA0)/ (TI04/TO04) RxD2/SI20/SDA20/ P14 (SCLA0)/ (TI03/TO03) PCLBUZ1/SCK20/ P15 SCL20/(TI02/TO02) TI01/TO01/INTP5/ P16 (RxD0) P17 TI02/TO02/(TxD0) Port 2. Analog ANI0/AVREFP P21 4-bit I/O port. input port ANI1/AVREFM P22 Input/output can be specified in 1-bit units. P20 I/O ANI2 Can be set to analog input. Specify then as either digital or P23 ANI3 analog in A/D port configuration register (ADPC). This register can be specified in 1-bit unit. P30 P31 I/O Port 3. Input port INTP3/SCK11/ 2-bit I/O port. SCL11 Input/output can be specified in 1-bit units. TI03/TO03/INTP4/ When input port use of an on-chip pull-up resistor can be PCLBUZ0 specified by a software setting (1-bit units). Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 17 RL78/G12 CHAPTER 2 PIN FUNCTIONS (2/2) Function I/O Name P40 I/O Function Port 4. After Reset Alternate Function Input port TOOL0 Input port INTP1/SI11/SDA11 1-bit I/O port. Input/output can be specified in 1-bit units. When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P50 I/O Port 5. 2-bit I/O port. P51 INTP2/SO11 Output of P50 can be set to N-ch open-drain output (VDD tolerance). Input/output can be specified in 1-bit units. When input port use of an on-chip pull-up resistor can be specified by a software setting (1-bit units). P60 I/O Port 6. Input port 2-bit I/O port. P61 SCLA0 SDAA0 N-ch open-drain output (6V tolerance). Input/output can be specified in 1-bit units. P120 P121 I/O Input Port 12. Analog 1-bit I/O port and 2-bit input port. input port P120 can be set to analog input. Specify then as either digital or Input port analog in port mode control register 12 (PMC12). P122 ANI19 X1 X2/EXCLK Only for P120, input/output can be specified. Only for P120, use of an on-chip pull-up resistor can be specified by a software setting. P137 Input Input port INTP0 Port 14. Analog ANI18 1-bit I/O port. input port Port 13. Dedicated 1-bit input port. P147 I/O Can be set to analog input. Specify then as either digital or analog in port mode control register 14 (PMC14). Input/output can be specified in 1-bit units. When input port use of an on-chip pull-up resistor can be specified by a software setting. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 18 RL78/G12 CHAPTER 2 PIN FUNCTIONS 2.2 Functions other than port pins 2.2.1 Functions for each product Function 20-pin 24-pin 30-pin Function 20-pin 24-pin 30-pin Name products products products Name products products products ANI0 ANI1 SCL01 Note Note Note Note Note - Note ANI2 SCL11 - - ANI3 SCL20 - - SDA00 Note Note Note ANI16 Note Note Note ANI17 SDA01 ANI18 SDA11 - - ANI19 SDA20 - - ANI20 - SI00 ANI21 - SI01 ANI22 - SI11 - - INTP0 SI20 - - INTP1 SO00 Note Note Note - Note Note Note - Note Note INTP2 SO01 INTP3 SO11 - - INTP4 - - SO20 - - INTP5 - - TI00 KR0 - TI01 KR1 - TI02 KR2 - TI03 KR3 - TI04 - - () KR4 - TI05 - - () KR5 - TI06 - - () KR6 - - TI07 - - () KR7 - - TO00 KR8 - - TO01 KR9 - - TO02 PCLBUZ0 TO03 PCLBUZ1 - - TO04 - - () REGC - - TO05 - - () RESET TO06 - - () RxD0 TO07 - - () RxD1 - - Note X1 RxD2 - - Note X2 TxD0 TxD1 - - TxD2 - - SCK00 SCK01 SCK11 <R> SCL00 Note - - Note Note EXCLK Note VDD Note AVREFP AVREFM Note - VSS Note TOOLRxD Note TOOLTxD TOOL0 - SCK20 - - SCLA0 SDAA0 Note R5F102 products. Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 19 RL78/G12 CHAPTER 2 PIN FUNCTIONS 2.2.2 Description of Functions Function Name <R> ANI0 to ANI3, ANI16 to ANI22 I/O input Functions Analog input pins (ANI16 to ANI20) of A/D converter See, Figure 10-47. Analog Input Pin Connection) AVREFP input Inputs the A/D converter reference potential (+ side) AVREFM input Inputs the A/D converter reference potential (- side) INTP0 to INTP5 input External interrupt request input Specified available edge : rising edge, falling edge, or both rising and falling edges KR0 to KR9 PCLBUZ0 to PCLBUZ1 REGC input output - Key interrupt input Clock/buzzer output Connecting regulator output stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 F) RESET input External reset input When the external reset pin is used, design the circuit based on VDD RxD0 to RxD2 input TxD0 to TxD2 output SCK00, SCK01, SCK11, SCK20 SI00, SI01, SI11, SI20 SO00, SO01, SO11, SO20 UART0 to UART2 serial data input UART0 to UART2 serial data output I/O CSI00, CSI01, CSI11, CSI20 serial clock I/O input CSI00, CSI01, CSI11, CSI20 serial data input output CSI00, CSI01, CSI11, CSI20 serial data output 2 SCLA0 I/O I C clock I/O SDAA0 I/O I C serial data I/O SCL00, SCL01, SCL11, SCL20 output SDA00, SDA01, SDA11, SDA20 I/O TI00 to TI07 TO00 to TO07 input output 2 Simple I2C (IIC00, IIC01, IIC11, IIC20) clock I/O 2 Simple I C (IIC00, IIC01, IIC11, IIC2) serial data I/O Inputting an external count clock/capture trigger to 16-bit timers 00 to 07 Timer output pins of 16-bit timers 00 to 07 X1, X2 - Connecting a resonator for main system clock EXCLK input External clock input pin for main system clock VDD - Positive power supply VSS - Ground potential Use bypass capacitors (about 0.1 F) as noise and latch up countermeasures with relatively thick wires at the shortest distance to VDD to VSS lines. TOOLRxD input This UART serial data input pin for an external device connection is used during flash memory programming TOOLTxD output This UART serial data output pin for an external device connection is used during flash memory programming TOOL0 I/O Data I/O pin for a flash memory programmer/debugger The operation mode after start-up is determined by the status of the TOOL0 pin at the time of releasing a reset. Connect via an external resistor to VDD when normal operation or on-chip debugging (pulling it down is prohibited) TOOL0 Operation mode V DD Normal operation mode 0V Flash memory programming mode For details, see 24.5.2 Flash Memory Programming Mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 20 RL78/G12 CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 and 2-2 show the types of pin I/O circuits and the recommended connections of unused pins. Table 2-1. Connection of Unused Pins (20-, 24-pin products) Pin Name P00/KR6/(SI01) I/O Circuit Type Note P01/KR7/(SO01/SDA01) 8-R I/O Note P02/KR8/(SCK01/SCL01) P03/KR9 I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. Note Note P10/ANI16/PCLBUZ0/SCK00/ 11-V SCL00 P11/ANI17/SI00/RxD0/SDA00/ TOOLRxD P12/ANI18/SO00/TxD0/ 11-U TOOLTxD P13/ANI19/TI00/TO00/INTP2 P14/ANI20/TI01/TO01/INTP3 P20/ANI0/AVREFP 11-T P21/ANI1/AVREFM P22/ANI2 11-G P23/ANI3 P40/KR0/TOOL0 8-R Input: Independently connect to VDD via a resistor or leave open. Output: Leave open. P41/ANI22/SO01/SDA01/TI02/ 11-U Input: TO02/INTP1 Independently connect to VDD or VSS via a resistor. Output: Leave open. P42/ANI21/SCK01/SCL01/TI03/ TO03 P60/KR4/SCLA0/(TxD0) 13-R P61/KR5/SDAA0/(RxD0) Input: Independently connect to VDD or VSS via a resistor. Output: Set the port's output latch to 0 and leave the pins open, or set the port's output latch to 1 and independently connect the pins to VDD or VSS via a resistor. P121/KR3/X1/(TI03)/(INTP3) 37-C input Independently connect to VDD or VSS via a resistor. P122/KR2/X2/EXCLK/(TI02)/ (INTP2) P125/KR1/SI01/RESET 42-B PORTSELB = 0: Independently connect to VDD or VSS via a resistor. PORTSELB = 1: Independently connect to VDD via a resistor. P137/INTP0 2 Independently connect to VDD or VSS via a resistor. Note 24-pin products only Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 21 RL78/G12 CHAPTER 2 PIN FUNCTIONS Table 2-2. Connection of Unused Pins (30-pin products) Pin Name P00/ANI17/TI00/TxD1 I/O Circuit Type 11-U P01/ANI16/TO00/RxD1 11-V P10/SCK00/SCL00/ 5-AN I/O I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. (TI07/TO07) P11/SI00/RxD0/TOOLRxD/ SDA00/(TI06/TO06) P12/SO00/TxD0/TOOLTxD/ 8-R (TI05/TO05) P13/TxD2/SO20/ 5-AN (SDAA0)/(TI04/TO04) P14/RxD2/SI20/SDA20/ (SCLA0)/(TI03/TO03) P15/PCLBUZ1/SCK20/ SCL20/(TI02/TO02) P16/TI01/TO01/INTP5/(RxD0) P17/TI02/TO02/(TxD0) P20/ANI0/AVREFP 11-T P21/ANI1/AVREFM P22/ANI2 11-G P23/ANI3 P30/INTP3/SCK11/SCL11 8-R P31/TI03/TO03/INTP4/ PCLBUZ0 P40/TOOL0 P50/INTP1/SI11/SDA11 P51/INTP2/SO11 13-R P60/SCLA0 P61/SDAA0 Input: Independently connect to VDD or VSS via a resistor. Output: Set the port's output latch to 0 and leave the pins open, or set the port's output latch to 1 and independently connect the pins to VDD or VSS via a resistor. P120/ANI19 11-U Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. P121/X1 37-C input Independently connect to VDD or VSS via a resistor. P122/X2/EXCLK P137/INTP0 2 P147/ANI18 11-U I/O Input: Independently connect to VDD or VSS via a resistor. Output: Leave open. RESET Remark 2 input Directly or independently connect to VDD via a resistor. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 22 RL78/G12 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type 2 Type 5-AN VDD pull-up enable P-ch VDD data P-ch output disable N-ch IN/OUT IN VSS CMOS Schmitt-triggered input with hysteresis characteristics TTL input characteristic Type 8-R Type 13-R VDD pullup enable P-ch IN/OUT data output disable VDD data N-ch P-ch VSS IN/OUT output disable N-ch VSS Type 37-C Type 42-B VDD X2 pullup enable P-ch P-ch amp enable N-ch input enable IN X1 input enable input enable SCHMIT reset reset mask R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 23 RL78/G12 CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (2/2) Type 11-G Type 11-T VDD data P-ch VDD IN/OUT data P-ch output disable N-ch IN/OUT VSS output disable N-ch P-ch Comparator VSS + _ Comparator N-ch P-ch Series resistor string voltage + _ VSS N-ch Series resistor string voltage VSS input enable input enable P-ch AVREFP, AVREFM N-ch Type 11-U Type 11-V VDD VDD pull-up enable pull-up enable P-ch VDD P-ch data P-ch output disable N-ch VDD data IN/OUT P-ch IN/OUT output disable N-ch VSS VSS CMOS input enable P-ch Comparator TTL input characteristic + _ N-ch P-ch Comparator + _ Series resistor string voltage N-ch VSS Series resistor string voltage VSS R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 24 RL78/G12 CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space <R> Products in the RL78/G12 can access a 1 MB memory space. Figures 3-1 to 3-6 show the memory maps. Figure 3-1. Memory Map for the R5F10266 and R5F10366 007FFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNotes 1, 2 256 bytes FFE00H FFDFFH Program area Prohibited area F1800H F17FFH F1000H F0FFFH Data memory space Data flash memoryNote 4 2KB Prohibited area F0800H F07FFH 2nd SFR 2KB 000CEH 000CDH Prohibited area 000C4H 000C3H 000C0H 000BFH F0000H EFFFFH 00080H 0007FH 00800H 007FFH Program memory space <R> Notes 1 Option byte area Note 3 4 bytes CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 2KB 00000H On-chip debug Note 3 security ID setting area 10 bytes 00000H When the data flash memory is rewritten, the stack used for the data flash library should be set to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to FFE00H to FFE19H. For details, refer to RL78 Family Data Flash Library Type04 User's Manual.. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F10266 only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 25 RL78/G12 <R> CHAPTER 3 CPU ARCHITECTURE Caution 1. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.3 RAM parity error detection function. <R> 2. The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program specification, the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. For details, refer to RL78 Family Data Flash Library Type04 User's Manual. <R> 3. The self-programming function cannot be used in the R5F10266 and R5F10366 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 26 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-2. Memory Map for the R5F10x67, and R5F10x77, and R5F10xA7 (x = 2 or 3) 00FFFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNotes 1, 2 512 bytes FFD00H FFCFFH Program area Prohibited area F1800H F17FFH F1000H F0FFFH Data memory space Data flash memoryNote 4 2KB Prohibited area F0800H F07FFH F0000H EFFFFH 2nd SFR 2KB 000CEH 000CDH Prohibited area 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 01000H 00FFFH Program memory space Option byte area Note 3 4 bytes CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 4KB 00000H On-chip debug Note 3 security ID setting area 10 bytes 00000H Notes 1. Use of the area FFE20H to FFEFFH is prohibited when using the self-programming function and data flash function, because this area is used for self-programming library. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F10267, R5F10277, and R5F102A7 only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 27 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-3. Memory Map for the R5F10x68, R5F10x78, and R5F10xA8 (x = 2 or 3) 01FFFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNotes 1, 2 768 bytes FFC00H FFBFFH Program area Prohibited area Data memory space F1800H F17FFH F1000H F0FFFH Data flash memoryNote 4 2KB Prohibited area F0800H F07FFH F0000H EFFFFH 2nd SFR 2KB 000CEH 000CDH Prohibited area 000C4H 000C3H 000C0H 000BFH 00080H 0007FH 02000H 01FFFH Program memory space Option byte area Note 3 4 bytes CALLT table area 64 bytes Vector table area 128 bytes Code flash memory 8KB 00000H On-chip debug Note 3 security ID setting area 10 bytes 00000H Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the selfprogramming function and data flash function are used. In R5F10x68, R5F10x78, FFC00H to FFC80H area cannot be used. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F10268, R5F10278, and R5102A8 only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 28 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-4. Memory Map for the R5F10x69, R5F10x79, and R5F10xA9 (x = 2 or 3) 02FFFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNotes 1, 2 1KB FFB00H FFAFFH F3000H F2FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH Data memory space Prohibited area Program area Mirror 4KB Prohibited area Data flash memoryNote 4 2KB Prohibited area F0800H F07FFH F0000H EFFFFH 2nd SFR 2KB Prohibited area 000C4H 000C3H 000C0H 000BFH On-chip debug Note 3 security ID setting area 10 bytes Option byte area Note 3 4 bytes CALLT table area 64 bytes 00080H 0007FH 03000H 02FFFH Program memory space 000CEH 000CDH Vector table area 128 bytes Code flash memory 12KB 00000H 00000H Notes 1. FFE20H to FFC80H area used by the self-programming libraries cannot be used when the selfprogramming function and data flash function are used. In R5F10x69, R5F10x79, FFB00H to FFC80H area cannot be used. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F10269, R5F10279, and R5F102A9 only. <R> Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 29 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-5. Memory Map for the R5F10x6A, R5F10x7A (x = 2 or 3) 03FFFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNotes 1, 2 1.5 KB FF900H FF8FFH F4000H F3FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH Data memory space Prohibited area Program area Mirror 8KB Prohibited area Data flash memoryNote 4 2KB Prohibited area F0800H F07FFH 2nd SFR 2KB F0000H EFFFFH Prohibited area 000C4H 000C3H 000C0H 000BFH On-chip debug Note 3 security ID setting area 10 bytes Option byte area Note 3 4 bytes CALLT table area 64 bytes 00080H 0007FH 04000H 03FFFH Program memory space 000CEH 000CDH Vector table area 128 bytes Code flash memory 16KB 00000H 00000H Notes 1. FFE20H to FFEFFH and FF900H to FFC80H area used by the self-programming libraries cannot be used when the self-programming function and data flash function are used. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F1026A and R5F1027A only. <R> Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 30 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-6. Memory Map for the R5F10xAA (x = 2 or 3) 03FFFH FFFFFH SFR 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes User RAMNote 1 2 KB FF700H FF6FFH F4000H F3FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH Data memory space Prohibited area Program area Mirror 8KB Prohibited area Data flash memoryNote 3 2KB Prohibited area F0800H F07FFH 2nd SFR 2KB 000CEH 000CDH Prohibited area 000C4H 000C3H 000C0H 000BFH F0000H EFFFFH Option byte area Note 2 4 bytes CALLT table area 64 bytes 00080H 0007FH 04000H 03FFFH Program memory space On-chip debug Note 2 security ID setting area 10 bytes Vector table area 128 bytes Code flash memory 16KB 00000H 00000H Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the selfprogramming function and data flash function are used. 2. Instructions can be executed from the RAM area excluding the general-purpose register area. 3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH. 4. Provided in R5F102AA only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 31 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory. 03FFFH 03C00H 03BFFH Block 0FH 007FFH Block 01H 00400H 003FFH Block 00H 00000H 1 KB (For the R5F1026A and R5F1027A) Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory Address Value Block Number product R5F10x66 00000H to 003FFH 00H 00400H to 007FFH 01H 00800H to 00BFFH 02H R5F10x67 00C00H to 00FFFH 03H R5F10x77 01000H to 013FFH 04H R5F10x68 01400H to 017FFH 05H R5F10x78 01800H to 01BFFH 06H 01C00H to 01FFFH 07H 02000H to 023FFH 08H R5F10x69 02400H to 027FFH 09H R5F10x79 02800H to 02BFFH 0AH 02C00H to 02FFFH 0BH 03000H to 033FFH 0CH R5F10x6A 03400H to 037FFH 0DH R5F10x7A 03800H to 03BFFH 0EH R5F10xAA 03C00H to 03FFFH 0FH (x = 2, 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 32 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. The RL78/G12 products incorporate internal ROM (flash memory), as shown below. Table 3-2. Internal ROM Capacity Part Number Internal ROM Structure R5F10x66 Flash memory Capacity 2048 x 8 bits (00000H to 07FFFH) R5F10x67, R5F10x77, R5F10xA7 4096 x 8 bits (00000H to 00FFFH) R5F10x68, R5F10x78, R5F10xA8 8192 x 8 bits (00000H to 01FFFH) R5F10x69, R5F10x79, R5F10xA9 12288 x 8 bits (00000H to 02FFFH) R5F10x6A, R5F10x7A, R5F10xAA 16384 x 8 bits (00000H to 03FFFH) (x = 2 or 3) <R> The internal program memory space is divided into the following areas. (1) Vector table area The 128-byte area of 00000H to 0007FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Furthermore, the interrupt jump addresses are assigned to a 64 KB address area of 00000H to 0FFFFH, because the vector code is 2 bytes. Of 16-bit addresses, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 33 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-3. Vector Table (20-, 24-pin products) Vector Table Address <R> Note Interrupt Source 0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE 0004H INTWDTI 0006H INTLVI 0008H INTP0 000AH INTP1 000CH INTP2 000EH INTP3 0010H INTDMA0 Note 0012H INTDMA1 Note 0014H INTST0/INTCSI00/INTIIC00 0016H INTSR0/INTCSI01 0018H INTSRE0 001AH INTTM01H 001CH INTTM03H Note 001EH INTIICA0 0020H INTTM00 0022H INTTM01 0024H INTTM02 0026H INTTM03 0028H INTAD 002AH INTIT 002CH INTKR 002EH INTMD 0030H INTFL 007EH BRK Note Note /INTIIC01 R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 34 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-4. Vector Table (30-pin products) Vector Table Address Interrupt Source 0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE 0004H INTWDTI 0006H INTLVI 0008H INTP0 000AH INTP1 000CH INTP2 000EH INTP3 0010H INTP4 0012H INTP5 0014H INTST2/INTCSI20 0016H INTSR2 0018H INTSRE2 001AH INTDMA0 Note 001CH INTDMA1 Note 001EH INTST0/INTCSI00/INTIIC00 0020H INTSR0 0022H INTSRE0/INTTM01H 0024H INTST1 0026H INTSR1 0028H INTFL Note Note /INTIIC20 Note Note Note Note Note /INTCSI11 Note Note /INTIIC11 INTTM03H <R> Note 002AH INTIICA0 002CH INTTM00 002EH INTTM01 0030H INTTM02 0032H INTTM03 0034H INTAD 0038H INTIT 0042H INTTM04 0044H INTTM05 0046H INTTM06 0048H INTTM07 005EH INTMD 0062H INTFL 007EH BRK R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 35 RL78/G12 CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area of 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT). Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes). (3) Option byte area The 4-byte area of 000C0H to 000C3H can be used as an option byte area. For details, see CHAPTER 23 OPTION BYTE. (4) On-chip debug security ID setting area The 10-byte areas of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID setting area. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 36 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.1.2 Mirror area The products with 12/16 KB flash memory mirror the code flash area of 02000H to 02FFF/03FFFHH to the area of F2000H to F2FFFH/03FFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)). By reading data from F2000H to F2FFFH/03FFFH, an instruction that does not have the ES register as an operand can be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not mirrored to the SFR, extended SFR, RAM, and use prohibited areas. See 3.1 Memory Space for the mirror area of each product. The mirror area can only be read and no instruction can be fetched from this area. The following shows examples. Example R5F1026A and RF5F1027A (Flash memory: 16 KB, RAM: 1.5 KB) FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH FF900H FF8FFH F4000H F3FFFH F2000H F1FFFH F1800H F17FFH General-purpose register 32 bytes RAM 1.5 KB Use prohibited Mirror (same data as that in 02000H to 03FFFH) Use prohibited Data flash memory F1000H F0FFFH Use prohibited F0800H F07FFH Special function register (2nd SFR) 2 KB Mirror E0000H EFFFFH Use prohibited For example, 03789H is mirrored to F3789H. Data can therefore be read by MOV A, !3789H instead of MOV ES, #00H MOV A, ES:!3789H. 04000H 03FFFH 02000H 01FFFH Code flash memory Code flash memory 00000H The PMC register is described below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 37 RL78/G12 CHAPTER 3 CPU ARCHITECTURE * Processor mode control register (PMC) This register sets the flash memory space for mirroring to the area from F0000H to FFFFFH. The PMC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 3-7. Format of Configuration of Processor Mode Control Register (PMC) Address: FFFFEH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> PMC 0 0 0 0 0 0 0 MAA MAA <R> <R> Selection of flash memory space for mirroring to the area from F0000H to FFFFFH 0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH 1 Setting prohibited Caution 1. Be sure to clear bit 0 (MAA) of this register to 0 (default value). 2. After setting the PMC register, wait for at least one instruction and access the mirror area. 3.1.3 Internal data memory space The RL78/G12 products incorporate the following RAMs. Table 3-5. Internal RAM Capacity Part Number Internal RAM R5F10x66 256 x 8 bits (FFE00H to FFEFFH) R5F10x67, R5F10x77, R5F10xA7 512 x 8 bits (FFD00H to FFEFFH) R5F10x68, R5F10x78, R5F10xA8 768 x 8 bits (FFC00H to FFEFFH) R5F10x69, R5F10x79, R5F10xA9 1024 x 8 bits (FFB00H to FFEFFH) R5F10x6A, R5F10x7A 1536 x 8 bits (FF900H to FFEFFH) R5F10xAA 2048 x 8 bits (FF700H to FFEFFH) (x = 2 or 3) <R> The internal RAM can be used as a data area and a program area where instructions are fetched (it is prohibited to usethe general-purpose register area for fetching instructions). Four general-purpose register, banks consisting of eight 8-bit registers registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM area. The internal RAM is used as a stack memory. <R> Cautions 1. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching instructions or as a stack area. <R> 2. When self-programming is performed or the data flash memory is rewritten, the stack used for each library and the RAM address used for the data buffer and DMA transfer should not be set to the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User's Manual. R5F10266 : FFE20H-FFEA1HFFEE0H-FFEFFH (The stack used for the data flash library should be set to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to FFE00H to FFE19H.) R5F102mn, R5F103mn R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 :FFE20H-FFEA1H 38 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Remark m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A) <R> 3. Use ofthe RAM areas of the following products is prohibited, because these areas are used for self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map) R5F102m8, R5F103m8: FFC00H to FFC80H R5F102m9, R5F103m9: FFB00H-FFC80H R5F102mA, R5F103mA: FF900H-FFC80H Remarks m: Pin count (m = 6, 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 39 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.1.4 Special function register (SFR) area On-chip peripheral hardware special function registers (SFRs) are allocated in the area of FFF00H to FFFFFH (see Table 3-6 in 3.2.4 Special function registers (SFRs)). Caution Do not access addresses to which SFRs are not assigned. 3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area On-chip peripheral hardware special function registers (2nd SFRs) are allocated in the area of F0000H to F07FFH (see Table 3-7 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)). SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Caution Do not access addresses to which extended SFRs are not assigned. 3.1.6 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the RL78/G12, based on operability and other considerations. In particular, special addressing methods designed for the functions of the special function registers (SFR) and general-purpose registers are available for use. Figures 3-8 to 3-13 show correspondence between data memory and addressing. For details of each addressing, see 3.4 Addressing for Processing Data Addresses. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 40 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-8. Correspondence Between Data Memory and Addressing for the R5F10266 and R5F10366 SFR 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing User RAM 256 bytes Prohibited area Data flash memoryNote 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area 2nd SFR 2KB Prohibited area Code flash memory 2KB <R> Notes 1. When the data flash memory is rewritten, the stack used for the data flash library should be set to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to FFE00H to FFE19H. For details, refer to RL78 Family Data Flash Library Type04 User's Manual. 2. Provided in R5F10266 only. <R> Caution 1. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. <R> 2. The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer's program specification, the stack area to execute the data flash library may not be kept and data may not be written to or erased from the data flash memory. For details, refer to RL78 Family Data Flash Library Type04 User's Manual. <R> 3. The self-programming function cannot be used for R5F10266 and R5F10366. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 41 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-9. Correspondence Between Data Memory and Addressing for the R5F10x67, R5F10x77, R5F10xA7 (x = 2 or 3) FFFFFH SFR 256 bytes FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes FFE20H FFE1FH SFR addressing Register addressing Short direct addressing User RAM 512 bytes FFD00H FFCFFH Prohibited area F1800H F17FFH F1000H F0FFFH Data flash memoryNote 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area F0800H F07FFH 2nd SFR 2KB F0000H EFFFFH Prohibited area 01000H 00FFFH Code flash memory 4KB 00000H Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the selfprogramming function and data flash function are used. 2. Provided in R5F10267, R5F10277, and R5F102A7 only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 42 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing for the R5F10x68, R5F10x78, and R5F10xA8 (x = 2 or 3) SFR 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing User RAM Note 1 768 bytes Prohibited area Data flash memory Note 2 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area 2nd SFR 2KB Prohibited area Code flash memory 8KB Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-programming function and data flash function are used. In R5F10x68, R5F10x78, FFC00H to FFC80H area cannot be used. 2. Provided in R5F10268, R5F10278, and R5F102A8 only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 43 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-11. Correspondence Between Data Memory and Addressing for the (R5F10x69, R5F10x79, and R5F10xA9 (x = 2 or 3) FFFFFH SFR 256 bytes SFR addressing FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FFB00H FFAFFH F3000H F2FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH General-purpose register 32 bytes Register addressing Short direct addressing User RAM Note 1 1KB Prohibited area Mirror 4KB Prohibited area Data flash memory Note 2 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area F0800H F07FFH 2nd SFR 2KB F0000H EFFFFH Prohibited area 03000H 02FFFH Code flash memory 12KB 00000H Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-programming function and data flash function are used. In R5F10x69, R5F10x79, FFC00H to FFC80H area cannot be used. 2. Provided in R5F10269, R5F10279, and R5F102A9 only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 44 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Correspondence Between Data Memory and Addressing for the R5F10x6A, and R5F10x7A (x = 2 or 3) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF9C0H FF9BFH FF900H FF8FFH F4000H F3FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH SFR 256 bytes SFR addressing General-purpose register 32 bytes Register addressing Short direct addressing User RAM Note 1 1.5KB Prohibited area Mirror 8KB Prohibited area Data flash memory Note 2 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area F0800H F07FFH 2nd SFR 2KB F0000H EFFFFH Prohibited area 04000H 03FFFH Code flash memory 16KB 00000H Notes 1. FFE20H to FFEFFH and FF900H to FFC80H area used by the self-programming libraries cannot be used when the self-programming function and data flash function are used. 2. Provided in R5F1026A and R5F1027A only. <R> Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 45 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Correspondence Between Data Memory and Addressing for the R5F10xAA (x = 2 or 3) FFFFFH FFF20H FFF1FH FFF00H FFEFFH FFEE0H FFEDFH FFE20H FFE1FH FF700H FF6FFH F4000H F3FFFH F2000H F1FFFH F1800H F17FFH F1000H F0FFFH SFR 256 bytes General-purpose register 32 bytes SFR addressing Register addressing Short direct addressing RAM 2KB Prohibited area Mirror 8KB Prohibited area Data flash memoryNote 2KB Direct addressing Register indirect addressing Based addressing Based indexed addressing Prohibited area F0800H F07FFH F0000H EFFFFH 2nd SFR 2KB Prohibited area 04000H 03FFFH Code flash memory 16KB 00000H Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the selfprogramming function and data flash function are used. 2. Provided in R5F102AA only. <R> Caution While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 46 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The RL78/G12 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 20-bit register that holds the address information of the next program to be executed. In normal operation, PC is automatically incremented according to the number of bytes of the instruction to be fetched. When a branch instruction is executed, immediate data and register contents are set. <R> Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the 16 lower-order bits of the program counter. The four higher-order bits of the program counter are cleared to 0000. Figure 3-14. Format of Program Counter 0 19 PC (2) Program status word (PSW) The program status word is an 8-bit register consisting of various flags set/reset by instruction execution. Program status word contents are stored in the stack area upon acknowledgment of a vectored interrupt request or PUSH PSW instruction execution, and are restored upon execution of the RETB, RETI and POP PSW instructions. Reset signal generation sets the PSW register to 06H. Figure 3-15. Format of Program Status Word 7 PSW IE 0 Z RBS1 AC RBS0 ISP1 ISP0 CY (a) Interrupt enable flag (IE) This flag controls the interrupt request acknowledge operations of the CPU. When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable interrupt requests are disabled. <R> When 1, the IE flag is set to the interrupt enabled (EI) state, and interrupt request acknowledgment is controlled with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority specification flag. The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI instruction execution. <R> (b) Zero flag (Z) When the operation or comparison result is zero or equal, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0, RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 47 RL78/G12 CHAPTER 3 CPU ARCHITECTURE (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases. (e) In-service priority flags (ISP1, ISP0) These flags manage the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests specified lower than the value of ISP0 and ISP1 flags by the priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (see 15.3 (3)) can not be acknowledged. Actual vectored interrupt request acknowledgment is controlled by the interrupt enable flag (IE). <R> Remark n = 0, 1 (f) Carry flag (CY) This flag stores overflow and underflow upon add/subtract instruction execution. It stores the shift-out value upon rotate instruction execution and functions as a bit accumulator during bit operation instruction execution. (3) Stack pointer (SP) This is a 16-bit register to hold the start address of the memory stack area. Only the internal RAM area can be set as the stack area. Figure 3-16. Format of Stack Pointer 0 15 SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is <R> incremented after read (restore) from the stack memory. Each stack operation saves data as shown in Figure 3-17. Cautions 1. Since reset signal generation makes the SP contents undefined, be sure to initialize the SP before using the stack. <R> 2. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching <R> 3. When self-programming is performed or the data flash memory is rewritten, the stack used for instructions or as a stack area. each library and the RAM address used for the data buffer and DMA transfer should not be set to the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User's Manual. R5F10266 : FFE20H-FFEA1HFFEE0H-FFEFFH (The stack used for the data flash library should be set to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to FFE00H to FFE19H.) R5F102mn, R5F103mn :FFE20H-FFEA1H Remarks m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A) <R> 4. Use of the RAM areas of the following products is prohibited, because these areas are used for self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map) R5F102m8, R5F103m8: FFC00H to FFC80H R5F102m9, R5F103m9: FFB00H-FFC80H R5F102mA, R5F103mA: FF900H-FFC80H Remarks m: Pin count (m = 6, 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 48 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-17. Data to Be Saved to Stack Memory PUSH PSW instruction PUSH rp instruction SPSP-2 SP-2 SP-1 SP Register pair lower Register pair higher CALL, CALLT instructions (4-byte stack) SPSP-4 SP-4 SP-3 SP-2 SP-1 SP PC7 to PC0 PC15 to PC8 PC19 to PC16 00H SPSP-2 SP-2 SP-1 SP 00H PSW Interrupt, BRK instruction (4-byte stack) SPSP-4 SP-4 SP-3 SP-2 SP-1 SP PC7 to PC0 PC15 to PC8 PC19 to PC16 PSW 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FFEE0H to FFEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL). These registers can be described in terms of function names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute names (R0 to R7 and RP0 to RP3). Register banks to be used for instruction execution are set by the CPU control instruction (SEL RBn). Because of the 4register bank configuration, an efficient program can be created by switching between a register for normal processing and a register for interrupts for each bank. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 49 RL78/G12 CHAPTER 3 CPU ARCHITECTURE <R> Cautions 1. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching instructions or as a stack area. 2. When self-programming is performed or the data flash memory is rewritten, the stack used for <R> each library and the RAM address used for the data buffer and DMA transfer should not be set to the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User's Manual. R5F10266 : FFE20H-FFEA1HFFEE0H-FFEFFH (The stack used for the data flash library should be set to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to FFE00H to FFE19H.) R5F102mn, R5F103mn :FFE20H-FFEA1H Remark m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A) 3. Use of the RAM areas of the following products is prohibited, because these areas are used for <R> self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map) R5F102m8, R5F103m8: FFC00H to FFC80H R5F102m9, R5F103m9: FFB00H-FFC80H R5F102mA, R5F103mA: FF900H-FFC80H Remark m: Pin count (m = 6, 7) Figure 3-18. Configuration of General-Purpose Registers (a) Function name 16-bit processing 8-bit processing FFEFFH H Register bank 0 HL L FFEF8H D Register bank 1 DE E FFEF0H B BC Register bank 2 C FFEE8H A AX Register bank 3 X FFEE0H 15 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 0 7 0 50 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.2.3 ES and CS registers <R> The ES register is used for data access and the CS register is used to specify the higher address when a branch instruction is executed. The default value of the ES register after reset is 0FH, and that of the CS register is 00H. Figure 3-19. Configuration of ES and CS Registers ES CS 7 6 5 4 3 2 1 0 0 0 0 0 ES3 ES2 ES1 ES0 7 6 5 4 3 2 1 0 0 0 0 0 CS3 CP2 CP1 CP0 <R> Though the data area which can be accessed with 16-bit addresses is the 64 Kbytes from F0000H to FFFFFH, using the ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH. <R> Figure 3-20 Extension of Data Area Which Can Be Accessed R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 51 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.2.4 Special function registers (SFRs) Unlike a general-purpose register, each SFR has a special function. SFRs are allocated to the FFF00H to FFFFFH area. SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation <R> Describe as follows for the 1-bit manipulation instruction operand (sfr.bit). When the bit name is defined: <Bit name> When the bit name is not defined: <Register name>, <Bit number> or <Address>, <Bit number> * 8-bit manipulation <R> Describe the symbol defined by the assembler for the 8-bit manipulation instruction operand (sfr). This manipulation can also be specified with an address .* 16-bit manipulation <R> Describe the symbol defined by the assembler for the 16-bit manipulation instruction operand (sfrp). When specifying an address, describe an even address. Table 3-6 gives a list of the SFRs. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding SFR can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. Caution Do not access addresses to which extended SFRs are not assigned. Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 52 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. SFR List (1/4) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFF00H Port register 0 P0 R/W - 00H FFF01H Port register 1 P1 R/W - 00H FFF02H Port register 2 P2 R/W - 00H FFF03H Port register 3 P3 R/W - 00H FFF04H Port register 4 P4 R/W - 00H FFF05H Port register 5 P5 R/W - 00H FFF06H Port register 6 P6 R/W - 00H FFF0CH Port register 12 P12 R/W - Undefined - Undefined Note FFF0DH Port register 13 P13 R FFF0EH Port register 14 P14 R/W - 00H FFF10H Serial data register 00 TXD0/ SDR00 R/W SIO00 - 0000H - - - 0000H - FFF11H FFF12H Serial data register 01 RXD0/ SDR01 R/W SIO01 - - - R/W - - 0000H FFF1AH Timer data register 01 TDR01L TDR01 R/W - 00H FFF1BH TDR01H FFF13H FFF18H Timer data register 00 TDR00 FFF19H - FFF1EH 10-bit A/D conversion result register ADCR R - - 0000H FFF1FH ADCRH R - - 00H 8-bit A/D conversion result register 00H FFF20H Port mode register 0 PM0 R/W - FFH FFF21H Port mode register 1 PM1 R/W - FFH FFF22H Port mode register 2 PM2 R/W - FFH FFF23H Port mode register 3 PM3 R/W - FFH FFF24H Port mode register 4 PM4 R/W - FFH FFF25H Port mode register 5 PM5 R/W - FFH FFF26H Port mode register 6 PM6 R/W - FFH FFF2CH Port mode register 12 PM12 R/W - FFH FFF2EH Port mode register 14 PM14 R/W - FFH FFF30H A/D converter mode register 0 ADM0 R/W - 00H FFF31H Analog input channel specification register ADS R/W - FFF32H A/D converter mode register 1 ADM1 R/W - 00H 00H FFF34H Key return control register KRCTL R/W - 00H FFF35H Key return flag register KRF R/W - 00H FFF36H Key return mode register 1 KRM1 R/W - 00H FFF37H Key return mode register 0 KRM0 R/W - 00H FFF38H External interrupt request rising EGP0 R/W - 00H FFF39H External interrupt request falling EGN0 R/W - 00H edge enable register 0 edge enable register 0 Note Read only for 30-pin product. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 53 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. SFR List (2/4) Address Special Function Register (SFR) Name FFF44H Serial data register 02 Symbol R/W TXD1/ SDR02 R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit - 0000H - - - 0000H - - - 0000H 0000H SIO10 - FFF45H FFF46H Serial data register 03 RXD1/ SDR03 R/W SIO11 - FFF47H FFF48H Serial data register 10 TXD2/ SDR10 R/W SIO20 - FFF49H FFF4AH Serial data register 11 - - - - - R/W - - 00H RXD2/ SDR11 R/W SIO21 - FFF4BH FFF50H IICA shift register 0 IICA0 FFF51H IICA status register 0 IICS0 R - 00H FFF52H IICA flag register 0 IICF0 R/W - 00H FFF64H Timer data register 02 TDR02 R/W - - 0000H FFF66H Timer data register 03 TDR03L TDR03 R/W - 00H FFF67H TDR03H - FFF65H 00H TDR04 R/W - - 0000H TDR05 R/W - - 0000H TDR06 R/W - - 0000H TDR07 R/W - - 0000H ITMC R/W - - 0FFFH CMC R/W - - 00H CSC R/W - C0H OSTC R - 00H OSTS R/W - - 07H FFFA4H System clock control register CKC R/W - 00H FFFA5H Clock output select register 0 CKS0 R/W - 00H FFFA6H Clock output select register 1 CKS1 R/W - 00H FFF68H Timer data register 04 FFF69H FFF6AH Timer data register 05 FFF6BH FFF6CH Timer data register 06 FFF6DH FFF6EH Timer data register 07 FFF6FH FFF90H Interval timer control register FFF91H FFFA0H Clock operation mode control register FFFA1H Clock operation status control register FFFA2H Oscillation stabilization time counter status register FFFA3H Oscillation stabilization time select register R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 54 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. SFR List (3/4) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range After Reset 1-bit 8-bit 16-bit FFFA8H Reset control flag register RESF R - - Undefined FFFA9H Voltage detection register LVIM R/W - 00H FFFAAH Voltage detection level register LVIS R/W - 00H/01H/81H Note 1 Note 2 Note 3 Note 4 FFFABH Watchdog timer enable register WDTE R/W - - FFFACH CRC input register CRCIN R/W - - 00H FFFB0H DMA SFR address register 0 DSA0 R/W - - 00H FFFB1H DMA SFR address register 1 DSA1 R/W - - 00H FFFB2H DMA RAM address register 0L DRA0L DRA0 R/W - 00H FFFB3H DMA RAM address register 0H DRA0H R/W - FFFB4H DMA RAM address register 1L DRA1L DRA1 R/W - FFFB5H DMA RAM address register 1H DRA1H R/W - FFFB6H DMA byte count register 0L DBC0L DBC0 R/W - 1A/9A 00H 00H 00H 00H FFFB7H DMA byte count register 0H DBC0H R/W - FFFB8H DMA byte count register 1L DBC1L DBC1 R/W - FFFB9H DMA byte count register 1H DBC1H R/W - FFFBAH DMA mode control register 0 DMC0 R/W - 00H FFFBBH DMA mode control register 1 DMC1 R/W - 00H FFFBCH DMA operation control register 0 DRC0 R/W - 00H R/W - 00H - - - - Undefined - - - - Undefined - - - - Undefined FFFBDH DMA operation control register 1 DRC1 Note 5 FFFC0H - PFCMD FFFC2H - PFS - FFFC4H Note 5 Note 5 FLPMC FFFD0H Interrupt request flag register 2L IF2L IF2 FFFD1H Interrupt request flag register 2H IF2H FFFD4H Interrupt mask flag register 2L MK2L FFFD5H Interrupt mask flag register 2H MK2H MK2 FFFD8H Priority specification flag register PR02L PR02 R/W R/W R/W R/W R/W R/W R/W R/W 00H 00H 00H 00H 00H FFH FFH FFH 02L FFFD9H Priority specification flag register PR02H FFH 02H FFFDCH Priority specification flag register PR12L PR12 FFH 12L FFFDDH Priority specification flag register PR12H FFH 12H Notes 1. The reset value of the RESF register varies depending on the reset source. 2. The reset value of the LVIM register varies depending on the reset source. 3. The reset value of the LVIS register varies depending on the reset source and the setting of the option byte. 4. The reset value of the WDTE register is determined by the setting of the option byte. 5. Do not directly operate this SFR, because it is to be used in the self programming library. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 55 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-6. SFR List (4/4) Address Special Function Register (SFR) Name Symbol FFFE0H Interrupt request flag register 0L IF0L IF0 FFFE1H Interrupt request flag register 0H IF0H FFFE2H Interrupt request flag register 1L IF1L IF1 FFFE3H Interrupt request flag register 1H IF1H FFFE4H Interrupt mask flag register 0L MK0L FFFE5H Interrupt mask flag register 0H MK0H FFFE6H Interrupt mask flag register 1L MK1L FFFE7H Interrupt mask flag register 1H MK1H MK0 MK1 FFFE8H Priority specification flag register PR00L PR00 R/W Manipulable Bit Range 1-bit 8-bit 16-bit R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W After Reset 00H 00H 00H 00H FFH FFH FFH FFH FFH 00L FFFE9H Priority specification flag register PR00H FFH 00H FFFEAH Priority specification flag register PR01L PR01 FFH 01L FFFEBH Priority specification flag register PR01H FFH 01H FFFECH Priority specification flag register PR10L PR10 FFH 10L FFFEDH Priority specification flag register PR10H FFH 10H FFFEEH Priority specification flag register PR11L PR11 FFH 11L FFFEFH Priority specification flag register PR11H FFH 11H FFFF0H Multiplication/division data register FFFF1H A (L) MDAL R/W - - 0000H FFFF2H Multiplication/division data register FFFF3H A (H) MDAH R/W - - 0000H FFFF4H Multiplication/division data register FFFF5H B (H) MDBH R/W - - 0000H FFFF6H Multiplication/division data register FFFF7H B (L) MDBL R/W - - 0000H R/W - 00H FFFFEH Processor mode control register PMC Remark For extended SFRs (2nd SFRs), see Table 3-7 Extended SFR (2nd SFR) List. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 56 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers) Unlike a general-purpose register, each extended SFR (2nd SFR) has a special function. Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area. Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type. Each manipulation bit unit can be specified as follows. * 1-bit manipulation <R> Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This manipulation can also be specified with an address. * 8-bit manipulation Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This <R> manipulation can also be specified with an address. * 16-bit manipulation Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When <R> specifying an address, describe an even address. Table 3-7 gives a list of the extended SFRs. The meanings of items in the table are as follows. * Symbol Symbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator, symbols can be written as an instruction operand. * R/W Indicates whether the corresponding extended SFR can be read or written. R/W: Read/write enable R: Read only W: Write only * Manipulable bit units "" indicates the manipulable bit unit (1, 8, or 16). "-" indicates a bit unit for which manipulation is not possible. * After reset Indicates each register status upon reset signal generation. <R> Caution Do not access addresses to which extended SFRs are not assigned. Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 57 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Extended SFR (2nd SFR) List (1/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range 1-bit 8-bit 16-bit After Reset F0010H A/D converter mode register 2 ADM2 R/W - 00H F0011H ADUL R/W - - FFH ADLL R/W - - 00H F0013H Conversion result comparison upper limit setting register Conversion result comparison lower limit setting register A/D test register ADTES R/W - - 00H F0030H Pull-up resistor option register 0 PU0 R/W - 00H F0031H Pull-up resistor option register 1 PU1 R/W - 00H F0033H Pull-up resistor option register 3 PU3 R/W - 00H F0034H Pull-up resistor option register 4 PU4 R/W - 01H F0035H Pull-up resistor option register 5 PU5 R/W - 00H F0037H Pull-up resistor option register 7 PU7 R/W - 00H F0012H F003CH Pull-up resistor option register 12 PU12 R/W - 00H F003EH Pull-up resistor option register 14 PU14 R/W - 00H F0040H Port input mode register 0 PIM0 R/W - 00H F0041H Port input mode register 1 PIM1 R/W - 00H F0050H Port output mode register 0 POM0 R/W - 00H F0051H Port output mode register 1 POM1 R/W - 00H F0054H Port output mode register 4 POM4 R/W - 00H F0055H Port output mode register 5 POM5 R/W - 00H F0060H Port mode control register 0 PMC0 R/W - FFH F0061H Port mode control register 1 PMC1 R/W - FFH F0064H Port mode control register 4 PMC4 R/W - FFH F006CH Port mode control register 12 PMC12 R/W - FFH F006EH Port mode control register 14 PMC14 R/W - FFH F0070H Noise filter enable register 0 NFEN0 R/W - 00H F0071H Noise filter enable register 1 NFEN1 R/W - 00H F0074H Timer input select register 0 TIS0 R/W - - 00H F0076H A/D port configuration register ADPC R/W - - 00H F0077H Peripheral I/O redirection register PIOR R/W - - 00H R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 58 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Extended SFR (2nd SFR) List (2/5) Address Special Function Register (SFR) Name F0078H F0090H <R> Invalid memory access detection control register Data flash control register F00A0H High-speed on-chip oscillator trimming register F00A8H High-speed on-chip oscillator frequency selecting register F00E0H Multiplication/division data register C (L) F00E2H Multiplication/division data register C (H) F00E8H Multiplication/division control register F00F0H Peripheral enable register 0 Symbol F0100H F0102H - - DFLCTL R/W - HOTRM R/W - - HOCODIV R/W - - Undefined MDCL R/W - - 0000H MDCH R/W - - 0000H MDUC R/W - 00H PER0 R/W - 00H R/W - - 00H R/W - 00H R - - Undefined - 0000H - - - 0000H - - F0104H - - - - - - - - - - - - - - - - - - R Serial status register 01 - SSR01L SSR01 R - Serial status register 02 SSR02L SSR02 R - F0105H F0106H BCDADJ SSR00L SSR00 F0103H Serial status register 03 SSR03L SSR03 R - F0107H After Reset R/W Serial status register 00 F0101H Manipulable Bit Range 1-bit 8-bit 16-bit IAWCTL F00F3H Operation speed mode control OSMC register F00F5H RAM parity error control register RPECTL F00FEH BCD adjust result register R/W 00H 00H Undefined 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H - 0020H - - 0020H R/W - - 0020H SMR03 R/W - - 0020H Serial communication operation setting register 00 SCR00 R/W - - 0087H F011AH Serial communication operation F011BH setting register 01 SCR01 R/W - - 0087H F011CH Serial communication operation F011DH setting register 02 SCR02 R/W - - 0087H F011EH Serial communication operation F011FH setting register 03 SCR03 R/W - - 0087H Serial flag clear trigger register 00 SIR00L SIR00 R/W F010AH Serial flag clear trigger register F010BH 01 SIR01L SIR01 R/W F010CH Serial flag clear trigger register F010DH 02 SIR02L SIR02 R/W F010EH Serial flag clear trigger register F010FH 03 SIR03L SIR03 R/W F0110H Serial mode register 00 SMR00 R/W - Serial mode register 01 SMR01 R/W Serial mode register 02 SMR02 Serial mode register 03 F0108H F0109H - - - - Note F0111H F0112H F0113H F0114H F0115H F0116H F0117H F0118H F0119H <R> Note The value after a reset is adjusted at the time of shipment. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 59 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Extended SFR (2nd SFR) List (3/5) Address Special Function Register (SFR) Name Symbol Serial channel enable status register 0 SE0L F0121H F0122H Serial channel start register 0 SS0L F0120H Serial channel stop register 0 Serial clock select register 0 R/W ST0L ST0 R/W SPS0L SPS0 R/W - F0127H F0128H SS0 - F0125H F0126H R - - F0123H F0124H SE0 R/W Serial output register 0 Manipulable Bit Range 1-bit 8-bit 16-bit - - - - - - - - - After Reset 0000H 0000H 0000H 0000H SO0 R/W - - 0F0FH SOE0L SOE0 R/W 0000H - - - 0000H - - 0000H 0000H 0000H 0000H 0000H F0129H F012AH Serial output enable register 0 - F012BH F0134H Serial output level register 0 F0138H SOL0L SOL0 R/W - F0135H Serial standby control register 0 SSC0L SSC0 R/W - F0140H Serial status register 10 F0142H SSR10L SSR10 R - F0141H Serial status register 11 SSR11L SSR11 R - F0143H Serial flag clear trigger register 10 SIR10L SIR10 R/W F014AH Serial flag clear trigger register F014BH 11 SIR11L SIR11 R/W F0148H F0149H - - - - - - - - - - - - - - - - - Serial mode register 10 SMR10 R/W - - 0020H Serial mode register 11 SMR11 R/W - - 0020H Serial communication operation setting register 10 SCR10 R/W - - 0087H F015AH Serial communication operation F015BH setting register 11 SCR11 R/W - - 0087H R 0000H - - 0000H - - 0000H - - - 0000H - - F0150H F0151H F0152H F0153H F0158H F0159H Serial channel enable status register 1 SE1L F0161H F0162H Serial channel start register 1 SS1L F0160H Serial channel stop register 1 Serial clock select register 1 ST1L ST1 R/W SPS1L SPS1 R/W - F0167H F0168H R/W - F0165H F0166H SS1 - F0163H F0164H SE1 - Serial output register 1 SO1 R/W - - 0F0FH SOE1L SOE1 R/W 0000H - - - 0000H - - F0169H F016AH Serial output enable register 1 - F016BH F0174H Serial output level register 1 F0175H R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 SOL1L SOL1 - R/W 60 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Extended SFR (2nd SFR) List (4/5) Address Special Function Register (SFR) Name Symbol R/W Manipulable Bit Range 1-bit 8-bit 16-bit After Reset Timer counter register 00 TCR00 R - - FFFFH Timer counter register 01 TCR01 R - - FFFFH Timer counter register 02 TCR02 R - - FFFFH Timer counter register 03 TCR03 R - - FFFFH Timer counter register 04 TCR04 R - - FFFFH F018AH Timer counter register 05 TCR05 R - - FFFFH TCR06 R - - FFFFH TCR07 R - - FFFFH Timer mode register 00 TMR00 R/W - - 0000H Timer mode register 01 TMR01 R/W - - 0000H Timer mode register 02 TMR02 R/W - - 0000H Timer mode register 03 TMR03 R/W - - 0000H Timer mode register 04 TMR04 R/W - - 0000H F019AH Timer mode register 05 TMR05 R/W - - 0000H TMR06 R/W - - 0000H TMR07 R/W - - 0000H R - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - - 0000H - - F0180H F0181H F0182H F0183H F0184H F0185H F0186H F0187H F0188H F0189H F018BH F018CH Timer counter register 06 F018DH F018EH Timer counter register 07 F018FH F0190H F0191H F0192H F0193H F0194H F0195H F0196H F0197H F0198H F0199H F019BH F019CH Timer mode register 06 F019DH F019EH Timer mode register 07 F019FH F01A0H Timer status register 00 F01A1H F01A2H Timer status register 01 F01A3H F01A4H Timer status register 02 F01A5H F01A6H Timer status register 03 F01A7H F01A8H Timer status register 04 F01A9H F01AAH Timer status register 05 F01ABH F01ACH Timer status register 06 F01ADH F01AEH Timer status register 07 F01AFH R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 TSR00L TSR00 - TSR01L TSR01 R - TSR02L TSR02 R - TSR03L TSR03 R - TSR04L TSR04 R - TSR05L TSR06 R - TSR06L TSR07 R - TSR07L TSR03 - R 61 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Table 3-7. Extended SFR (2nd SFR) List (5/5) Address Special Function Register (SFR) Name Symbol F01B0H Timer channel enable status F01B1H register 0 TE0L F01B2H Timer channel start register 0 TS0L R/W Manipulable Bit Range 1-bit 8-bit 16-bit F01B4H Timer channel stop register 0 TT0L F01B6H Timer clock select register 0 TPS0 0000H 0000H - 0000H - 0000H - - 0000H - - - 0000H - - - 0000H 00H - - - - - R/W - R/W R/W TT0 - TS0 - R/W - F01B5H 0000H R - F01B3H TE0 After Reset F01B7H F01B8H Timer output register 0 TO0L TO0 - F01B9H F01BAH Timer output enable register 0 TOE0L TOE0 F01BCH Timer output level register 0 TOL0L TOL0 R/W - F01BDH F01BEH Timer output mode register 0 TOM0L TOM0 R/W - - - R/W - IICCTL01 R/W - 00H IICWL0 R/W - - FFH IICA high-level width setting register 0 IICWH0 R/W - - FFH Slave address register 0 SVA0 R/W - - 00H CRCD R/W - - 0000H F01BFH F0230H IICA control register 00 IICCTL00 F0231H IICA control register 01 F0232H IICA low-level width setting register 0 F0233H F0234H F02FAH CRC data register Remark R/W - F01BBH For SFRs in the SFR area, see Table 3-6 SFR List. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 62 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing 3.3.1 Relative addressing [Function] Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the instruction word (signed complement data: -128 to +127 or -32768 to +32767) to the program counter (PC)'s value (the start address of the next instruction), and specifies the program address to be used as the branch destination. Relative addressing is applied only to branch instructions. Figure 3-21. Outline of Relative Addressing <R> 3.3.2 Immediate addressing [Function] Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the program address to be used as the branch destination. For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or BR !addr16 is used to specify 16-bit addresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses. <R> Figure 3-22. Example of CALL !!addr20/BR !!addr20 Figure 3-23. Example of CALL !addr16/BR !addr16 <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 63 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit immediate data in the instruction word, stores the contents at that table address and the next address in the program counter (PC) as 16-bit data, and specifies the program address. Table indirect addressing is applied only for CALLT instructions. In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH. Figure 3-24. Outline of Table Indirect Addressing <R> 3.3.4 Register direct addressing [Function] Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair (AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and specifies the program address. Register direct addressing can be applied only to the CALL AX, BC, DE, HL, and BR AX instructions. Figure 3-25. Outline of Register Direct Addressing <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 64 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4 Addressing for Processing Data Addresses 3.4.1 Implied addressing [Function] Instructions for accessing registers (such as accumulators) that have special functions are directly specified with the instruction word, without using any register specification field in the instruction word. [Operand format] Implied addressing can be applied only to MULU X. Figure 3-26. Outline of Implied Addressing <R> 3.4.2 Register addressing [Function] Register addressing accesses a general-purpose register as an operand. The instruction word of 3-bit long is used to select an 8-bit register and the instruction word of 2-bit long is used to select a 16-bit register. [Operand format] Identifier Description r X, A, C, B, E, D, L, H rp AX, BC, DE, HL Figure 3-27. Outline of Register Addressing Instruction code <R> OP code Register Memory (register bank area) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 65 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target address. [Operand format] Identifier <R> ADDR16 Description Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable: automatically added F of higher 4-bit addresses) <R> ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register) <R> Figure 3-28. Example of ADDR16 <R> Figure 3-29. Example of ES:ADDR16 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 66 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFE20H to FFF1FH. [Operand format] Identifier SADDR SADDRP Description Label or FFE20H to FFF1FH immediate data Label or FFE20H to FFF1FH immediate data (only even address is specifiable.) Figure 3-30. Outline of Short Direct Addressing <R> Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate data (higher 4 bits of actual address are omitted), and the values of addresses FFE20H to FFF1FH with 20bit immediate data. Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH are specified for the memory. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 67 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.5 SFR addressing [Function] SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of addressing is applied only to the space from FFF00H to FFFFFH. [Operand format] Identifier SFR <R> SFRP Description SFR name 16-bit-manipulatable SFR name (even address) <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Figure 3-31. Outline of SFR Addressing 68 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register indirect addressing directly specifies the target addresses using the contents of the register pair specified with the instruction word as an operand address. [Operand format] Identifier Description - [DE], [HL] (only the space from F0000H to FFFFFH is specifiable) - ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register) Figure 3-32. Example of [DE], [HL] <R> Figure 3-33. Example of ES:[DE], ES:[HL] <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 69 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] <R> Based addressing uses the contents of a register pair specified with the instruction word as a base address, and 8bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target address. [Operand format] Identifier Description - [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable) - word[B], word[C] (only the space from F0000H to FFFFFH is specifiable) - word[BC] (only the space from F0000H to FFFFFH is specifiable) - ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register) - ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register) - ES:word[BC] (higher 4-bit addresses are specified by the ES register) Figure 3-34. Example of [SP+byte] <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 70 RL78/G12 <R> CHAPTER 3 CPU ARCHITECTURE Figure 3-35. Example of [HL + byte], [DE + byte] <R> Figure 3-36. Example of word[B], word[C] <R> Figure 3-37. Example of word[BC] R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 71 RL78/G12 <R> <R> CHAPTER 3 CPU ARCHITECTURE Figure 3-38. Example of ES:[HL + byte], ES:[DE + byte] Figure 3-39. Example of ES:word[B], ES:word[C] Figure 3-40. Example of ES:word[BC] <R> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 72 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] Based indexed addressing uses the contents of a register pair specified with the instruction word as the base address, and the content of the B register or C register similarly specified with the instruction word as offset address. The sum of these values is used to specify the target address. [Operand format] Identifier Description - [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable) - ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register) <R> Figure 3-41 Example of [HL+B], [HL+C] <R> Figure 3-42. Example of ES:[HL+B], ES:[HL+C] R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 73 RL78/G12 CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing <R> [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is saved/restored upon generation of an interrupt request. <R> <R> Stack addressing is applied only to the internal RAM area. [Operand format] Identifier <R> - Description PUSH AX/BC/DE/HL POP AX/BC/DE/HL CALL/CALLT RET BRK RETB (Interrupt request generated) RETI <R> Figure 3-43. Example of PUSH rp R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 74 RL78/G12 CHAPTER 3 CPU ARCHITECTURE Figure 3-44 Example of POP <R> <R> Figure 3-45. Example of CALL, CALLT <R> Figure 3-46. Example of RET R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 75 RL78/G12 <R> CHAPTER 3 CPU ARCHITECTURE Figure 3-47. Example of Interrupt, BRK <R> Figure 3-48. Example of RETI, RETB R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 76 RL78/G12 CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions The RL78/G12 microcontrollers are provided with digital I/O ports, which enable variety of control operations. In addition to the function as digital I/O ports, these ports have several alternate functions. For details of the alternate functions, see CHAPTER 2 PIN FUNCTIONS. 4.2 Port Configuration Ports include the following hardware. Table 4-1. Port Configuration Item Configuration Port mode registers (PM0 to PM6, PM12, PM14) Control registers Port registers (P0 to P06, P12 to P14) Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU12, PU14) Port input mode register (PIM0, PIM1) Port output mode registers (POM0, POM1, POM4, POM5) Port mode control registers (PMC0, PMC1, PMC4, PMC12, PMC14) A/D port configuration register (ADPC) Peripheral I/O redirection register (PIOR) * 20-pin products Port Total: 18 (CMOS I/O: 12, CMOS input: 4, N-ch open drain I/O: 2) * 24-pin products Total: 22 (CMOS I/O: 16, CMOS input: 4, N-ch open drain I/O: 2) * 30-pin products Total: 26 (CMOS I/O: 21, CMOS input: 3, N-ch open drain I/O: 2) Pull-up resistor <R> Caution * 20-pin products Total: 9 * 24-pin products Total: 13 * 30-pin products Total: 17 Most of the following descriptions in this chapter use the R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 77 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.2.1 20, 24-pin products (1) Port 0 Port 0 is an I/O port with an output latch (with 24-pin products). Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). Output from the P01 pin can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 0 (POM0). This port can also be used for key return input. Reset signal generation sets port 0 to input mode. Table 4-2. Settings of Registers When Using Port 0 (24-pin Products) Pin Alternate Function Note2 Buffer type I/O PM0x PIM0x POM0x PMC0x Input 1 - - - x CMOS input Output 0 - x CMOS output Input 1 - x name P00 P01 Output P02 Input P03 <R> 0 1 x 0 - 1 - - - CMOS input Note 1 ) (SO01/SDA01output = 1 CMOS output N-ch open-drain output x CMOS input Note 1 Output 0 - Input 1 - x CMOS input Output 0 - x CMOS output (SCK01/SCL01output = 1 ) CMOS output Notes 1. If P01, P02 are used as general-purpose port and PIOR3 is set to 1 in the R5F102 products, use bits 1 (SE01, SO01, SOE01) of serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enableregister 0 (SOE0) with the same setting as the initial status. 2. The descriptions in parentheses indicate the case where PIOR3 = 1. Remark x : don't care PM0 : Port mode register 0 PIM0 : Port input mode register 0 POM0 : Port output mode register 0 PMC0 : Port mode control register 0 PIOR : Peripheral I/O redirection register R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 78 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-1 to 4-3 show block diagrams of port 0. Figure 4-1. Block Diagram of P00, and P03 (24-pin Products) VDD WRPU PU0 PU00, PU03 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00, P03) WRPM P00/KR6/(SI01), P03/KR9 PM0 PM00, PM03 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 79 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 (24-pin Products) VDD WRPU PU0 PU01 P-ch Alternate function Internal bus Selector RD WRPORT P0 Output latch (P01) P01/KR7/(SO01/SDA01) WRPOM POM0 POM01 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port output mode register 0 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 80 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 (24-pin Products) VDD WRPU PU0 PU02 P-ch Alternate function Internal bus Selector RD WRPORT P0 Output latch (P02) P01/KR8/(SCK01/SCL01) WRPM PM0 PM02 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 81 RL78/G12 CHAPTER 4 PORT FUNCTIONS (2) Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P14 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). At this time, in case of P10 to P12, set 0 in a bit of port output mode register 1 (POM1) corresponding to the bit using an on-chip pull-up register. Input to the P10 and P11 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 1 (PIM1). Output from the P10 to P12 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 1 (POM1). When P10 to P14 pins are used as input, specify them as either digital or analog in port mode co troll register 1 (PMC1). This register can be specified in 1-bit unit. This port can also be used for analog input, clock/buzzer output, serial interface data I/O, clock I/O, timer I/O, and external interrupt request input. Reset signal generation sets port 1 to analog input. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 82 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-3. Settings of Registers When Using Port 1 (20-, 24-pin Products) Pin I/O PM1x PIM1x POM1x PMC1x Alternate Function Input 1 0 x 0 x 1 1 x 0 x 0 PCLBUZ0 output = 0 0 x 1 SCK00/SCL00 output = 1 1 0 x 1 1 x Buffer type name P10 Output P11 Input Output P12 Input Output P13 P14 Input 0 x 0 0 x 1 1 - x 0 0 0 1 Output 0 Input 1 Output Cautions 1. 2. 3. - 1 - x - 0 CMOS output Note 1 x N-ch open-drain output CMOS input x TTL input Note 2 SDA00 output = 1 CMOS output N-ch open-drain output 0 x CMOS input SO00/TxD0 output = 1 Note 2 CMOS output N-ch open-drain output 0 x 0 CMOS input Note 3 x TO01 output = 0 0 TTL input Note 1 TO00 output = 0 - CMOS input CMOS output CMOS input Note 3 CMOS output When using P10/ANI16/PCLBUZ0/SCK00/SCL00 as a general-purpose port, use the bit 7 (PCLOE0) of clock output select register 0 (CKS0), serial channel enable status register 0 (SE0), serial output register 0 (SO0), and use the each bit 0 (SE00, SO00, SOE00), serial channel enable status register 0 (SOE0) with the settings "0" same as the initial status. When using P11/SI00/RxD0/SDA00/TOOLRxD/ANI17, P12/SO00/TxD0/TOOLTxD/ANI18 as a general-purpose port, use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), use the each bit 0 (SE00, SO00, SOE00), serial channel enable status register 0 (SOE0) with the settings "0" same as the initial status. When using P13/ANI19/TI00/TO00/INTP2, P14/ANI20/TI01/TO01/INTP3 as a general-purpose port, use the bit 0, 1 (TO00, TO01) of timer output register 0 (TO0), and bit 0, 1 (TOE00, TOE01) of timer output enable register 0 (TOE0) with the settings "0" same as the initial status. Remaek x: don't care PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 PMC1: Port mode control register 1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 83 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-4 to 4-8 show block diagrams of port 1. Figure 4-4. Block Diagram of P10 (20-, 24-pin Products) WRPIM PIM1 VDD PIM10 WRPU PU1 PU10 P-ch WRPMC PMC1 PMC10 Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P10) P10/ANI16/ PCLBUZ0/ WRPOM POM1 SCK00/SCL00 POM10 WRPM PM1 PM10 Alternate function 1 (serial) Alternate function 2 (clock/buzzer) A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 PMC1: Port mode control register 1 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 84 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P11 (20-, 24-pin Products) WRPIM PIM1 VDD PIM11 WRPU PU1 PU11 P-ch WRPMC PMC1 PMC11 Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P11) WRPOM POM1 P11/ANI17/ SI00/RxD0/ SDA00/TOOLRxD POM11 WRPM PM1 PM11 Alternate function A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 PMC1: Port mode control register 1 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 85 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P12 (20-, 24-pin Products) VDD WRPU PU1 PU12 P-ch WRPMC PMC1 PMC12 Selector Internal bus RD WRPORT P1 Output latch P12/ANI18/SO00/ TxD0 (P12) WRPOM POM1 POM12 WRPM PM1 PM12 Alternate function A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1 PMC1: Port mode control register 1 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 86 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 (20-, 24-pin Products) VDD WRPU PU1 PU13 P-ch WRPMC PMC1 PMC13 Alternate function Selector Internal bus RD WRPORT P1 Output latch (P13) WRPM P13/ANI19/ TI00/TO00 PM1 PM13 Alternate function A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PMC1: Port mode control register 1 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 87 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P14 (20-, 24-pin Products) VDD WRPU PU1 PU14 P-ch WRPMC PMC1 PMC14 Alternate function Selector Internal bus RD WRPORT P1 Output latch P14/AN20/ TI01/TO01 (P14) WRPM PM1 PM14 Alternate function A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PMC1: Port mode control register 1 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 88 RL78/G12 CHAPTER 4 PORT FUNCTIONS (3) Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage inputs (positive and negative). To use P20/ANI0 to P23/ANI3 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P23/ANI3 as digital output pins, set them in the digital I/O mode by using the ADPC register and in the output mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P23/ANI3 as analog input pins, set them in the analog input mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit. Table 4-4. Settings of Registers When Using Port 2 (20-, 24-pin Products) Pin I/O PM2x ADPC name P2n Alternate Remark Buffer type Function input output Remark - 01 to 1 n+1H 0 To use P2n as a port, use CMOS input CMOS output PM2 : Port mode register 2 ADPC : A/D port configuration register these pins from a higher bit. Table 4-5. Setting Functions of P20/ANI0 to P23/ANI3 Pins ADPC Register PM2 Register Digital I/O selection Input mode Analog input selection Input mode ADS Register - - Output mode Output mode P20/ANI0 to P23/ANI3 Pins Digital input Digital output Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Reset signal generation sets port 2 to analog input. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 89 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-9 shows a block diagram of port 2. Figure 4-9. Block Diagram of P20 to P23 (20-, 24-pin Products) Selector Internal bus RD WRPORT P2 Output latch (P20 to P23) WRPM PM2 P20/ANI0/AVREFP, P21/ANI1/AVREFM, P22/ANI2, P23/ANI3 PM20 to PM23 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 90 RL78/G12 CHAPTER 4 PORT FUNCTIONS (4) Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P42 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). Output from the P41 pin can be specified as N-ch open-drain output (VDD tolerance) using port output mode register 4 (POM4). When P41 and P42 pins are used as input, specify them as either digital or analog in port mode control register 4 (PMC4). This register can be specified in 1-bit unit. This port can also be used for key return input, data I/O for a flash memory programmer/debugger, analog input, serial interface data I/O, clock I/O, timer I/O, and external interrupt request input. Reset signal generation sets port 4 to input mode (the P41 and P42 pins are analog input). Table 4-6. Settings of Registers When Using Port 4 (20-, 24-pin Products) Pin I/O PM4x PIM4x POM4x PMC4x Alternate Function Buffer type Input 1 - - - x CMOS input Output 0 x CMOS output Input 1 name P40 P41 Output P42 Input Output - 0 - 1 x 0 x 0 1 TO02 output = 0 - 0 Note CMOS input SCK01/SCL01 output = 1 0 CMOS output N-ch open-drain output x TO03 output = 0 Note CMOS input Note SO01, SDA01 output = 1 Note CMOS output Note When using P41/SO01/SDA01/TI02/TO02/INTP1/ANI22, P42/SCK01/SCL01/TI03/TO03/ANI21 as a generalpurpose port, use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), use the each bit 0 (SE00, SO00, SOE00), serial channel enable status register 0 (SOE0), use the each bit 1 (SE01, SO01, SOE01), bits 2, 3 (TO02, TO03) of timer output register 0 (TO0), bits 2,3 (TOE02, TOE03) of timer output enable register 0 (TOE0) with the same settings as the initial status. In addition, Set the port output mode register 4 (POM4) to 00H. Caution When a tool is connected, the P40 pin cannot be used as a port pin. Remark x: don't care PM4 : Port mode register 4 PIM4 : Port input mode register 4 POM4 : Port output mode register 4 PMC4 : Port mode control register 4 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 91 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-10 to 4-12 show block diagrams of port 4. Figure 4-10. Block Diagram of P40 (20-, 24-pin Products) VDD WRPU PU4 PU40 P-ch Alternate function Selector Internal bus RD WRPORT P4 (P40) WRPM PM4 Selector Output latch P40/KR0/TOOL0 PM40 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 92 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-11. Block Diagram of P41 (20-, 24-pin Products) VDD WRPU PU4 PU41 P-ch WRPMC PMC4 PMC41 Alternate function Selector Internal bus RD WRPORT P4 Output latch P41/ANI22/ SO01/SDA01/ TI02/TO02/INTP1 (P41) WRPOM POM4 POM41 WRPM PM4 PM41 Alternate function 1 (serial) Alternate function 2 (Timer) A/D converter P4: Port register 4 PM4: Port mode register 4 POM4: Port output mode register 4 PMC4: Port mode control register 4 PU4: Pull-up resistor option register 4 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 93 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-12. Block Diagram of P42 (20-, 24-pin Products) VDD WRPU PU4 PU42 P-ch WRPMC PMC4 PMC42 Alternate function Selector Internal bus RD WRPORT P4 Output latch (P42) P42/ANI21/SCK01/ SCL01/TI03/TO03 WRPM PM4 PM42 Alternate function 1 (serial) Alternate function 2 (Timer) A/D converter P4: Port register 4 PM4: Port mode register 4 PMC4: Port mode control register 4 PU4: Pull-up resistor option register 4 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 94 RL78/G12 CHAPTER 4 PORT FUNCTIONS (5) Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). This port can also be used for key return input, serial interface data I/O, and clock I/O. Reset signal generation sets port 6 to input mode. Table 4-7. Settings of Registers When Using Port 6 (20-, 24-pin Products) Pin name I/O P60 SCLA0 output = 0 0 (TxD0 output = 1 input 1 SDAA0 output = 0 output 0 output P61 <R> Notes 1. Note3 Note1 1 input <R> Alternate Function PM6x Note 2 Buffer type CMOS input ) Note 1 N-ch open-drain output (6 V tolerance) CMOS input N-ch open-drain output (6 V tolerance) When using P60/KR4/SCLA0, P61/KR5/SDAA0 as a general-purpose port, set the serial interface IICA to operation stop mode. 2. When using P60 as a general-purpose port and PIOR1 is set to 1, use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), serial channel enable status register 0 (SOE0), use the each bit 0 (SE00, SO00, SOE00) with the settings "0" same as the initial status. 3. Remark The descriptions in parentheses indicate the case where PIOR1 = 1. PM6 : Port mode register 6 PIOR : Peripheral I/O redirection register R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 95 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-13 shows a block diagram of port 6. Figure 4-13. Block Diagram of P60 and P61 (20-, 24-pin Products) RD Internal bus WRPORT P6 Output latch (P60, P61) WRPM PM6 Selector Alternate function P60/KR4/SCLA0/(TxD0), P61/KR5/SDAA0/(RxD0) PM60,PM61 Alternate function 1 (serial array unit) Alternate function 2 (IICA) P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 96 RL78/G12 CHAPTER 4 PORT FUNCTIONS (6) Port 12 Port 12 is an input port. Use of an on-chip pull-up resistor can be specified for P125 using pull-up resistor option register 12 (PU12) (valid after RESET input) Note . This port can also be used for key return input, connecting resonator for main system clock, external clock input for main system clock, and reset input. Note Once the power is turned on, P125 functions as RESET input until the power-on-reset (POR) is released. After the POR is released, the PORTSELB bit of the option byte (000C1H) defines whether this port is P125/KR1/SI01 or RESET. Therefore, when the port is set as P125/KR1/SI01, to avoid continuing the external reset status, do not input the low level to this pin until the POR is released. This pull-up resistor is enabled by releasing the reset. Table 4-8. Settings of Registers When Using Port 12 (20-, 24-pin Products) Pin name P121 I/O PM12x PMC12x Input - - Alternate Function OSCSEL bit = 0 of CMC register or EXCLK Buffer type CMOS input bit = 1 P122 Input - - P125 Input - - Caution OSCSEL bit = 0 of CMC register - CMOS input CMOS input The function setting on P121 and P122 is available only once after the reset release. The port once set for connection to an X1, XT1 oscillator, external clock input cannot be used as an input port unless the reset is performed. Remark PM12: Port mode register 12 PMC12: Port mode control register 12 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 97 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-14 and 4-15 show block diagrams of port 12. Figure 4-14 Block Diagram of P121 and P122 (20-, 24-pin Products) Clock generator CMC OSCSEL Alternate function Internal bus RD CMC P122/KR2/X2/EXCLK/ (TI02)/(INTP2) EXCLK,OSCSEL RD Alternate function P121/KR3/X1/ (TI03)/(INTP3) CMC: Clock operation mode control register RD: Read signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 98 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-15 Block Diagram of P125 (20-, 24-pin Products) VDD WRPU PU12 P-ch Internal bus PU125 Alternate functiom RD PORTSELB P125/KR1/ SI01/RESET PU12: Pull-up resistor option register 12 RD: Read signal WRxx: Write signal (7) Port 13 Port 13 is an input port. This port can also be used for external interrupt request input. Table 4-9. Settings of Registers When Using Port 13 (20-, 24-pin Products) Pin name P137 Remark I/O Alternate Function x Input x: Buffer type CMOS input don't care Figures 4-16 shows a block diagram of port 13. Internal bus Figure 4-16. Block Diagram of P137 (20-, 24-pin Products) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 P137/INTP0 Alternate function 99 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.2.2 30-pin products (1) Port 0 Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 and P01 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0). At this time, in case of PU00, set 0 in bit 0 of port output mode register 0 (POM0). Input to the P01 pins can be specified through a normal input buffer or a TTL input buffer using port input mode register 0 (PIM0). Input to the P00 and P01 pins can be specified as analog input or digital input in 1-bit units, using port mode control register 0 (PMC0). Output from the P00 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 1 (POM1). This port can also be used for timer I/O, analog input of A/D converter, and transmission/reception of programming UART. Reset signal generation sets port 0 to input mode. Table 4-10. Settings of Registers When Using Port 0 (30-pin Products) Pin name P00 I/O PM0x PIM0x POM0x PMC0x Alternate Function Input 1 - x 0 x Output P01 Input Output Notes 1. TxD1 output = 1 0 0 0 0 1 0 - 0 x 0 x 1 0 1 1 0 x 0 Buffer type CMOS input Note1 CMOS output N-ch open-drain output TO00 output = 0 CMOS input TTL input Note 2 CMOS output When using P00/ANI17/TI00/TxD1 as a general-purpose port, use the each bit 0 (SE00, SO00, SOE00) of serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same settings as the initial status. In addition, set the port output mode register 0 (POM0) to 00H. 2. When using P01/ANI16TO00/RxD1 as a general-purpose port, use the bit 0 (TO00) of timer output register 0 (TO0), and bit 0 (TOE00) of timer output enable register 0 (TOE0) with the settings "0" same as the initial status. Remark x: don't care PM0: Port mode register 0 PIM0: Port input mode register 0 POM0: Port output mode register 0 PMC0: Port mode control register 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 100 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-17 and 4-18 show block diagrams of port 0. Figure 4-17. Block Diagram of P00 (30-pin Products) VDD WRPU PU0 PU00 P-ch WRPMC PMC0 PMC00 Alternate function Selector Internal bus RD WRPORT P0 Output latch (P00) P00/ANI17/ WRPOM TI00/TxD1 POM0 POM00 WRPM PM0 PM00 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 POM0: Port mode output register 0 PMC0: Port mode control register 0 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 101 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P01 (30-pin Products) WRPIM PIM0 VDD PIM01 WRPU PU0 PU01 P-ch WRPMC PMC0 PMC01 CMOS RD Selector Internal bus Alternate function TTL WRPORT P0 Output latch (P01) P01/ANI16/ TO00/RxD1 WRPM PM0 PM01 Alternate function A/D converter P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 PIM0: Port input mode register 0 PMC0: Port mode control register 0 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 102 RL78/G12 CHAPTER 4 PORT FUNCTIONS (2) Port 1 Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). At this time, in case of P10 to P15, and P17, set 0 in a bit of port output mode register 1 (POM1) corresponding to the bit using an on-chip pull-up register. Input to the P10, P11, P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using port input mode register 1 (PIM1). Output from the P10 to P15, P17 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output mode register 1 (POM1). This port can also be used for serial interface data I/O, clock I/O, transmission/reception of programming UART, timer I/O, clock/buzzer output, and external interrupt request input. Reset signal generation sets port 1 to input mode. Table 4-11. Settings of Registers When Using Port 1 (30-pin Products) (1/2) Pin I/O PM1x PIM1x POM1x PMCxx Input 1 0 x - 1 1 x Alternate Function Note 8 Buffer type name P10 Output P11 Input Output P12 Input Output 0 x x 1 1 0 x 1 1 x 0 x 0 1 Input Output P14 Input Output P15 Input Output TTL input x 1 0 x 1 1 x x 1 1 0 x 1 1 x x Input Output 1 0 1 1 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 x N-ch open-drain output CMOS input TTL input Note 2 (SDAA0/TO04 output = 0 - CMOS output Note 6 ) x TTL input SDA20 output = 1 Note 2 (SCLA0/TO03 output = 0 - CMOS output Note 6 ) x TTL input PCLBUZ1 output = 0 Note 3 SCK20/SCL20 output = 1 - Note 3 x Note 1 CMOS output N-ch open-drain output ) CMOS input x TO01 output = 0 N-ch open-drain output CMOS input x 1 N-ch open-drain output CMOS input x 0 - CMOS output ) x (TO02 output = 0 P16 Note 5 TxD2/SO20 output = 1 0 0 Note 1 x 0 1 N-ch open-drain output CMOS input 1 - CMOS output ) x (TO05 output = 0 x x Note 5 SO00/TxD0 output = 1 0 x - Note 1 0 x N-ch open-drain output x x 1 ) CMOS output CMOS input - 1 Note 1 x 1 x 0 - x 0 0 (TO07 output = 0 Note 5 SDA00 output = 1 1 0 SCK00/SCL00 output = 1 (TO06 output = 0 0 0 TTL input 0 0 P13 CMOS input x 0 0 x TTL input Note 4 CMOS output 103 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-11. Settings of Registers When Using Port 1 (30-pin Products) (2/2) Pin I/O Alternate Function PM1x PIM1x POM1x PMCxx 1 0 x - 1 1 x x 0 x 0 TO02 output = 0 0 x 1 (TxD0 output = 1 Note 8 Buffer type name P17 Input Output Notes 1. x CMOS input TTL input Note 4 Note 7 CMOS output ) N-ch open-drain output When using P10/SCK00/SCL00, P11/SI00/RxD0/TOOLRxD/SDA00, P12/SO00/TxD0/TOOLTxD as a general-purpose port, use the each bit 0 (SE00, SO00, SOE00) of serial channel enable status register 0 (SE0), serial output register 0 (SO0), serial channel enable status register 0 (SOE0) with the same setting as the initial status. 2. When using P13/TxD2/SO20, P14/RxD2/SI20/SDA20 as a general-purpose port, use the each bit 0 (SE10, SO10, SOE10) of serial channel enable status register 1 (SE1), serial output register 1 (SO1), serial channel enable status register 1 (SOE1) with the same setting as the initial status. 3. When using P15/PCLBUZ1/SCK20/SCL20 as a general-purpose port, use the each bit 0 (SE10, SO10, SOE10) of serial channel enable status register 1 (SE1), serial output register 1 (SO1), serial channel enable status register 1 (SOE1), and bit 7 (PCLOE1) of clock output select register 1 (CKS1) with the same setting as the initial status. 4. When using P16/TI01/TO01/INTP5, P17/TI02/TO02 as a general-purpose port, use the bit 1, 2 (TO01, TO02) of timer output register 0 (TO0), and bit 1, 2 of (TOE01, TOE02) of timer output enable register 0 (TOE0) with the settings "0" same as the initial status. 5. If P10 to P12 is used as general-purpose port and PIOR0 is set to 1, set bits 5 to 7 (TO05 to TO07) of timer output register 0 (TO0) and bits 5 to 7 (TOE05 to TOE07) of timer output enable register 0 (TOE0) to "0", which is the same as their default status setting. 6. If P13 and P14 is used as general-purpose port and PIOR2 is set to 1, stop operate the serial interface IICA. If P13 and P14 are used as general-purpose ports and PIOR0 is set to 1, use the corresponding bits in bits 3, 4 (TO03, TO04) of timer output register 0 (TO0) and bits 3, 4 (TOE03, TOE04) of timer output enable register (TOE0) with the same setting as the initial status. 7. If P17 is used as general-purpose port and PIOR1 is set to 1, use the each bit 0 (SE00, SO00, SOE00) of serial channel enable status register 0 (SE0), serial output register 0 (SO0) and Serial output enable register 0 (SOE0) with the same setting as the initial status. 8. Remark The descriptions in parentheses indicate the case where PIORx = 1. x: don't care PM1: port mode register 1 PIM1: port input mode register 1 POM1: port output mode register 1 PMC1: port mode control register 1 PIOR: Peripheral I/O redirection register R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 104 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-19 to 4-21 show block diagrams of port 1. Figure 4-19. Block Diagram of P10, P11, P13 to P15, P17 (30-pin Products) WRPIM PIM1 VDD PIM1n WRPU PU1 PU1n P-ch Alternate function CMOS Internal bus Selector RD TTL WRPORT P1 Output latch (P1n) P10/SCK00/SCL00/ (TI07/TO07), POM1 P11/SI00/TOOLRxD/ SDA00/(TI06/TO06), POM1n P13/TxD2/SO20/ (SDAA0)/(TI04/TO04), WRPOM P14/RxD2/SI20/SDA20/ WRPM PM1 PM1n Alternate function 1 (serial) (SCLA0)/(TI03/TO03), P15/PCLBUZ1/SCK20/ SCL20/(TI02/TO02), P17/TI02/TO02 /(TxD0) Alternate function 2 (Timer, IICA, clock/ buzzer) (n = 0, 1, 3 to 5, 7) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 105 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P12 (30-pin Products) VDD WRPU PU1 PU12 P-ch Internal bus Selector RD WRPORT P1 Output latch (P12) WRPOM POM1 P12/SO00/TxD0/ TOOLTxD/ (TI05/TO05) POM12 WRPM PM1 PM12 Alternate function 1 (serial) Alternate function 2 (timer) P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 POM1: Port output mode register 1 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 106 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-21. Block Diagram of P16 (30-pin Products) WRPIM PIM1 VDD PIM16 WRPU PU1 PU16 P-ch Alternate function CMOS Selector Internal bus RD TTL WRPORT P1 Output latch (P16) P16/TI01/TO01/ INTP5/(RxD0) WRPM PM1 PM16 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 PIM1: Port input mode register 1 RD: Read signal WRxx: Write signal Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 107 RL78/G12 CHAPTER 4 PORT FUNCTIONS (3) Port 2 Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for A/D converter analog input and reference voltage inputs (positive and negative). To use P20/ANI0 to P23/ANI3 as digital input pins, set them in the digital I/O mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P23/ANI3 as digital output pins, set them in the digital I/O mode by using the ADPC register and in the output mode by using the PM2 register. Use these pins starting from the upper bit. To use P20/ANI0 to P23/ANI3 as analog input pins, set them in the analog input mode by using the A/D port configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the lower bit. Table 4-12. Settings of Registers When Using Port 2 (30-pin Products) Pin I/O PM2x ADPC name P2n Remark Buffer type Function Input Output Remark Alternate - 01 to 1 n+1H 0 CMOS input CMOS output PM2: Port mode register 2 ADPC: A/D port configuration register To use P2n as a port, use these pins from a higher bit. Table 4-13. Setting Functions of P20/ANI0 to P23/ANI3 Pins ADPC Register Digital I/O selection Analog input selection PM2 Register ADS Register P20/ANI0 to P23/ANI3 Pins Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Reset signal generation sets port 2 to analog input. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 108 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-22 shows a block diagram of port 2. Figure 4-22. Block Diagram of P20 to P23 (30-pin Products) Selector Internal bus RD Alternate P2 P20/ANI0/AVREFP, Output latch (P20 to P23) P21/ANI1/AVREFM, WRPM P22/ANI2, P23/ANI3 PM2 PM20 to PM23 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 109 RL78/G12 CHAPTER 4 PORT FUNCTIONS (4) Port 3 Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When this port is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, clock/buzzer output, and timer I/O. Reset signal generation sets port 3 to input mode. Table 4-14. Settings of Registers When Using Port 3 (30-pin Products) Pin name I/O P30 PM3x PMC3x Alternate Function 1 - x Input P31 Output 0 Input 1 Output 0 SCK11/SCL11 output = 1 - CMOS input Note 1 x TO03 output = 0 Note 2 PCLBUZ0 output = 0 Buffer type CMOS output CMOS input CMOS output Note 2 Notes 1. When using P30/SCK11/SCL11/INTP3 as a general-purpose port, use the each bit 3 (SE03, SO03, SOE00) of serial channel enable status register 1 (SE1), serial output register 1 (SO1), and serial output enable register 1 (SOE1) with the same settings as the initial status. 2. When using P31/TI03/TO03/INTP4/PCLBUZ0 as a general-purpose port, use the bit 3 (TO03) of timer output register 0 (TO0), bit 3 (TOE03) of timer output enable register 0 (TOE0), and bit 7 of clock output select register 0 (CKS0) with the same settings as the initial status. Remark x: don't care PM3: Port mode register 3 PMC3: Port mode control register 3 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 110 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-23 and 4-24 shows a block diagram of port 3. Figure 4-23. Block Diagram of P30 (30-pin Products) VDD WRPU PU3 PU30 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P30) P30/SCK11/SCL11/INTP3 WRPM PM3 PM30 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 111 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P31 (30-pin Products) VDD WRPU PU3 PU31 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P31) WRPM PM3 P31/TI03/TO03/ PCLBUZ0/INTP4 PM31 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 112 RL78/G12 CHAPTER 4 PORT FUNCTIONS (5) Port 4 Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode using port mode register 4 (PM4). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4) Note . Reset signal generation sets port 4 to input mode. Table 4-15. Settings of Registers When Using Port 4 (30-pin Products) Pin name P40 I/O PM4x PIM4x POM4x PMC4x Alternate Function Buffer type Input 1 - - - x CMOS input Output 0 x CMOS output Note When a tool is connected, the P40 pin cannot be used as a port pin. Remark x: don't care PM4: Port mode register 4 PIM4: Port input mode register 4 POM4: Port output mode register 4 PMC4: Port mode control register 4 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 113 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-25 shows a block diagram of port 4. Figure 4-25. Block Diagram of P40 (30-pin Products) VDD WRPU PU4 PU40 Alternate function Selector Internal bus RD P-ch WRPORT P4 Output latch (P40) P40/TOOL0 WRPM PM4 PM40 Alternate function P4: Port register 4 PU4: Pull-up resistor option register 4 PM4: Port mode register 4 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 114 RL78/G12 CHAPTER 4 PORT FUNCTIONS (6) Port 5 Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 5 (PU5). At this time, in case of PU50, set 0 in bit 0 of port output mode register 5 (POM5). Output from the P50 pin can be specified as N-ch open-drain output (VDD tolerance) using port output mode register 5 (POM5). This port can also be used for external interrupt request input, serial interface data I/O, and clock I/O. Reset signal generation sets port 5 to input mode. Table 4-16. Settings of Registers When Using Port 5 (30-pin Products) Pin name P50 I/O PM5x PIM5x POM5x Alternate Function 1 - x x Input Output 0 Input 1 0 0 P51 Output CMOS input SDA11 output = 1 Note 1 - - 0 Remark CMOS output N-ch open-drain output x SO11 output = 1 CMOS input Note CMOS output Note When using P50/INTP1/SI11/SDA11, P51/INTP2/SO11 as a general-purpose port, use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same settings as the initial status. Remark x: don't care PM5: Port mode register 5 PIM5: Port input mode register 5 POM5: Port output mode register 5 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 115 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-26 and 4-27 show block diagrams of port 5. Figure 4-26. Block Diagram of P50 (30-pin Products) VDD WRPU PU5 PU50 P-ch Alternate function Selector Internal bus RD WRPORT P5 Output latch (P50) WRPOM P50/SI11/SDA11/ INTP1 POM5 POM50 WRPM PM5 PM50 Alternate function P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 POM5: Port output mode register 5 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 116 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-27. Block Diagram of P51 (30-pin Products) VDD WRPU PU5 PU51 P-ch Alternate function Selector Internal bus RD WRPORT P5 Output latch (P51) P51/SO11/INTP2 WRPM PM5 PM51 Alternate function P5: Port register 5 PU5: Pull-up resistor option register 5 PM5: Port mode register 5 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 117 RL78/G12 CHAPTER 4 PORT FUNCTIONS (7) Port 6 Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). N-ch open-drain output (6 V tolerance). This port can also be used for serial interface data I/O and clock I/O. Reset signal generation sets port 6 to input mode. Table 4-17. Settings of Registers When Using Port 6 (30-pin Products) Pin name I/O P60 P61 PM6x Input 1 Output 0 Input 1 Output 0 Alternate Function Note SCLA0 output = 0 Remark CMOS input N-ch open-drain output (6 V tolerance) SDAA0 output = 0 Note CMOS input N-ch open-drain output (6 V tolerance) Note When using P60/SCLA0, P61/SDAA0 as a general-purpose port, set the serial interface IICA to operation stop mode. Remark PM6: Port mode register 6 Figure 4-28 shows a block diagram of port 6. Figure 4-28. Block Diagram of P60 and P61 (30-pin Products) Alternate function Selector Internal bus RD WRPORT P6 Output latch (P60, P61) WRPM P60/SCLA0, P61/SDAA0 PM6 PM60, PM61 Alternate function P6: Port register 6 PM6: Port mode register 6 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 118 RL78/G12 CHAPTER 4 PORT FUNCTIONS (8) Port 12 P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode using port mode register 12 (PM12). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12). P121 to P122 is a 2-bit input port. When the P120 pin is used as input, specify them as either digital or analog in Port mode control register 12 (PMC12). This port can also be used for A/D converter analog input, connecting resonator for main system clock, external clock input for main system clock, and external clock input for sub-system clock. Reset signal generation sets P120 analog input. P121, P122 to input mode. Table 4-18. Settings of Registers When Using Port 12 (30-pin Products) Pin name P120 P121 I/O PM12x PMC12x Alternate Function Input 1 0 x CMOS input Output 0 0 x CMOS output Input - - OSCSEL bit of CMC register = 0 or EXCLK Buffer type CMOS input bit = 1 P122 - Input - OSCSEL bit of CMC register = 0 CMOS input Note The function setting on P121 or P122 is available only once after the reset release. The port once set for connection to an X1 oscillator/external clock input cannot be used as an input port unless the reset is performed. Remark x: don't care PM12: Port mode register 12 PM12: Port mode control register 12 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 119 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figures 4-29 and 4-30 show block diagrams of port 12. Figure 4-29. Block Diagram of P120 (30-pin Products) VDD WRPU PU12 PU120 P-ch WRPMC PMC12 PMC120 Selector Internal bus RD WRPORT P12 Output latch (P120) WRPM P120/ANI19 PM12 PM120 A/D converter P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 PMC12: Port mode control register 12 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 120 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-30. Block Diagram of P121 and P122 (30-pin Products) Clock generator CMC OSCSEL Internal bus RD P122/X2/EXCLK CMC EXCLK, OSCSEL RD P121/X1 CMC: Clock operation mode control register RD: Read signal (9) Port 13 Port 13 is dedicated 1-bit input port. This port can also be used for external interrupt request input. Table 4-19. Settings of Registers When Using Port 13 (30-pin Products) Pin name P137 Remark I/O Alternate Function Buffer type x Input CMOS input x: don't care Figure 4-31 shows a block diagram of port 13. Internal bus Figure 4-31. Block Diagram of P137 (30-pin Products) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 P137/INTP0 Alternate function 121 RL78/G12 CHAPTER 4 PORT FUNCTIONS (10) Port 14 Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode using port mode register 14 (PM14). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). When the P147 pin is used as input, specify them as either digital or analog in Port mode control register 14 (PMC14). This port can also be used for A/D converter analog input. Reset signal generation sets port to analog input. Table 4-20. Settings of Registers When Using Port 14 (30-pin Products) Pin name I/O P147 Remark PM14x PIM14x POM14x PMC14x Alternate Function Input 1 - - 0 x CMOS input Output 0 0 x CMOS output x: don't care PM14: Port mode register 14 PIM14: Port input mode register 14 Buffer type POM14: Port output mode register 14 PMC14: Port mode control register 14 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 122 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-32 shows a block diagram of port 14. Figure 4-32. Block Diagram of P147 (30-pin Products) VDD WRPU PU14 PU147 P-ch WRPMC PMC1 RD Selector Internal bus PMC147 WRPORT P14 Output latch (P147) WRPM P147/ANI18 PM14 PM147 A/D converter P14: Port register 14 PU14: Pull-up resistor option register 14 PM14: Port mode register 14 PMC14: Port mode control register 14 RD: Read signal WRxx: Write signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 123 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following registers. * * * * * * * * Port mode registers (PMxx) Port registers (Pxx) Pull-up resistor option registers (PUxx) Port input mode registers (PIMxx) Port output mode registers (POMxx) Port mode control registers (PMCxx) A/D port configuration register (ADPC) Peripheral I/O redirection register (PIOR) Caution The undefined bits in each register vary by product and must be used with their initial value. Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx Registers and the Bits (20-, 24-pin Products) Bit name Port PMxx register Port 0 Note Port 1 Port 2 Port 4 Port 6 Port 12 Port 13 Pxx register PUxx register PIMxx register POMxx register PMCxx register - - 0 PM00 P00 PU00 - 1 PM01 P01 PU01 - 2 PM02 P02 PU02 - - - 3 PM03 P03 PU03 - - - 0 PM10 P10 PU10 PIM10 POM10 PMC10 1 PM11 P11 PU11 PIM11 POM11 PMC11 2 PM12 P12 PU12 - POM12 PMC12 3 PM13 P13 PU13 - - PMC13 4 PM14 P14 PU14 - - PMC14 0 PM20 P20 - - - - 1 PM21 P21 - - - - 2 PM22 P22 - - - - 3 PM23 P23 - - - - 0 PM40 P40 PU40 - - - 1 PM41 P41 PU41 - 2 PM42 P42 PU42 - - 0 PM60 P60 - - 1 PM61 - - POM01 POM41 PMC41 PMC42 - P61 - - - - 1 - P121 - - - - 2 - P122 - - - - 5 - P125 - - - 7 - P137 - - - PU125 - Note Provided in 24-pin products only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 124 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-22. PMxx, Pxx, PUxx, PIMx, POMx, PMCxx Registers and the Bits (30-pin Products) Bit name Port PMxx register Port 0 Port 1 Pxx register PUxx register PIMx register - POMx register POM00 PMCxx register 0 PM00 P00 PU00 PMC00 1 PM01 P01 PU01 PIM01 0 PM10 P10 PU10 PIM10 POM10 - 1 PM11 P11 PU11 PIM11 POM11 - 2 PM12 P12 PU12 POM12 - 3 PM13 P13 PU13 PIM13 POM13 - 4 PM14 P14 PU14 PIM14 POM14 - 5 PM15 P15 PU15 PIM15 POM15 - 6 PM16 P16 PU16 PIM16 7 PM17 P17 PU17 0 PM20 P20 - 1 PM21 P21 2 PM22 3 - - PMC01 - - - - - - - - - P22 - - - - PM23 P23 - - - - 0 PM30 P30 PU30 - - - 1 PM31 P31 PU31 - - - Port 4 0 PM40 P40 PU40 - - - Port 5 0 PM50 P50 PU50 - 1 PM51 P51 PU51 - - - 0 PM60 P60 - - - - 1 PM61 P61 - - - - 0 PM120 P120 - - PMC120 Port 2 Port 3 Port 6 Port 12 PIM17 PU120 - POM17 - POM50 1 - P121 - - - - 2 - P122 - - - - Port 13 7 - P137 - - - - Port 14 7 - - PMC147 PM147 P147 PU147 The format of each register is described below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 125 RL78/G12 CHAPTER 4 PORT FUNCTIONS (1) Port mode registers (PMxx) These registers specify input or output mode for the port in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function. Figure 4-33. Format of Port Mode Register 20-, 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W Note 1 1 1 1 PM03 PM02 PM01 PM00 FFF20H FFH R/W PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W PM0 Note Provided in 24-pin products only. 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W PM4 1 1 1 1 1 1 1 PM40 FFF24H FFH R/W PM5 1 1 1 1 1 1 PM51 PM50 FFF25H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W PM12 1 1 1 1 1 1 1 PM120 FFF2CH FFH R/W PM14 PM147 1 1 1 1 1 1 1 FFF2EH FFH R/W PMmn Pmn pin I/O mode selection (m = 0 to 6, 12, 14; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 126 RL78/G12 CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers set the output latch value of a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is Note read . These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the P4 register to 01H and clears the other registers to 00H. Note In the ports that are set up as analog inputs of the A/D converter, when a port is read while in the input mode, 0 is always returned, not the pin level. In addition, in the output latch that are set up as RESET pin for P125, 1 is always read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 127 RL78/G12 CHAPTER 4 PORT FUNCTIONS Figure 4-34. Format of Port Register 20-, 24-pin products <R> Symbol 7 6 5 4 3 2 1 0 Address After reset R/W P0 0 0 0 0 P03 P02 P01 P00 FFF00H 00H (output latch) R/W P1 0 0 0 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W P2 0 0 0 0 P23 P22 P21 P20 FFF02H 00H (output latch) R/W P4 0 0 0 0 0 P42 P41 P40 FFF04H 00H (output latch) R/W P6 0 0 0 0 0 0 P61 P60 FFF06H 00H (output latch) R/W P12 0 0 P125 0 0 P122 P121 0 FFF0CH Undefined R P13 P137 0 0 0 0 0 0 0 FFF0DH Undefined R After reset R/W 30-pin products <R> Symbol 7 6 5 4 3 2 1 0 Address P0 0 0 0 0 0 0 P01 P00 FFF00H 00H (output latch) R/W P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W P2 0 0 0 0 P23 P22 P21 P20 FFF02H 00H (output latch) R/W P3 0 0 0 0 0 0 P31 P30 FFF03H 00H (output latch) R/W P4 0 0 0 0 0 0 0 P40 FFF04H 00H (output latch) R/W P5 0 0 0 0 0 0 P51 P50 FFF05H 00H (output latch) R/W P6 0 0 0 0 0 0 P61 P60 FFF06H 00H (output latch) R/W P12 0 0 0 0 0 P122 P121 P120 FFF0CH Undefined R/W P13 P137 0 0 0 0 0 0 0 FFF0DH Undefined R P14 P147 0 0 0 0 0 0 0 FFF0EH Pmn Output data control (in output mode) Note 00H (output latch) R/W Input data read (in input mode) 0 Output 0 Input low level 1 Output 1 Input high level m = 0 to 6, 12, 13, 14; n = 0 to 7 Note P121 and P122 are read-only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 128 RL78/G12 CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set satisfied following three conditions which the use of an on-chip pull-up resistor has been specified in these registers. * PMmn = 1(Input mode) * PMCmn, sets the digital input of ADPC register * POMmn = 0: (POM10 to POM12 of 20-, 24-pin products and 30-pin products: Same state as the reset default value) Caution When a port with the PIMn register is input from different potential device to TTL buffer, pull up to the power supply of the different potential device via a external pull-up resistor by setting PUmn = 0. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of these registers. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PU4 to 01H, PU12 to 20H (20-, 24-pin products), and others to 00H. Figure 4-35. Format of Pull-up Resistor Option Register 20-, 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 0 0 0 PU03 PU02 PU01 PU00 F0030H 00H R/W PU1 0 0 0 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W PU4 0 0 0 0 0 PU42 PU41 PU40 F0034H 01H R/W PU12 0 0 PU125 0 0 0 0 0 F003CH 20H R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PU0 0 0 0 0 0 0 PU01 PU00 F0030H 00H R/W PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W PU3 0 0 0 0 0 0 PU31 PU30 F0033H 00H R/W PU4 0 0 0 0 0 0 0 PU40 F0034H 01H R/W PU5 0 0 0 0 0 0 PU51 PU50 F0035H 00H R/W PU12 0 0 0 0 0 0 0 PU120 F003CH 00H R/W PU14 PU147 0 0 0 0 0 0 0 F003EH 00H R/W PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 12, 14; n = 0 to 7) 0 On-chip pull-up resistor not connected (When PORTSELB = 0, P125 of 20-, 24-pin products) . 1 On-chip pull-up resistor connected R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 129 RL78/G12 CHAPTER 4 PORT FUNCTIONS (4) Port input mode register (PIMx) These registers set CMOS input or TTL input in 1-bit units. TTL input buffer can be selected during serial communication with an external device of a different potential. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 4-36. Format of Port Input Mode Register 20-, 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM1 0 0 0 0 0 0 PIM11 PIM10 F0041H 00H R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM0 0 0 0 0 0 0 PIM11 0 F0040H 00H R/W PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 F0041H 00H R/W PIMmn Pmn pin input buffer selection (m = 0, 1; n = 0, 1, 3 to 7) 0 Normal input buffer 1 TTL input buffer R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 130 RL78/G12 CHAPTER 4 PORT FUNCTIONS (5) Port output mode registers (POMx) These registers set CMOS output or N-ch open drain output in 1-bit units. N-ch open drain output (VDD tolerance) mode can be selected for the SDAxx pin during serial communication with an 2 external device of a different potential or during simplified I C communication with an external device of the same potential. When port 1 of 20-, 24-pin products or port 0, 1, 5 of 30-pin products is in input mode, POMx and PUx specifies whether to connect an on-chip pull-up resistor to port 1 along with PU1. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-37. Format of Port Output Mode Register 20-, 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM0 0 0 0 0 0 0 POM01 0 F0050H 00H R/W POM1 0 0 0 0 0 POM12 POM11 POM10 F0051H 00H R/W POM4 0 0 0 0 0 0 POM41 0 F0054H 00H R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM0 0 0 0 0 0 0 0 POM01 F0050H 00H R/W POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W POM5 0 0 0 0 0 0 0 POM50 F0055H 00H R/W POMmn 0 Pmn pin output mode selection (m = 0, 1, 4, 5; n = 0 to 7) Normal output mode When input mode, enable to the PUmn bit (POM1 of 20-, 24-pin products, and POM0, POM1, POM5 of 30pin products). 1 N-ch open-drain output (VDD tolerance) mode When input mode, disable to the PUmn bit (POM1 of 20-, 24-pin products, and POM0, POM1, POM5 of 30-pin products). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 131 RL78/G12 CHAPTER 4 PORT FUNCTIONS (6) Port mode control registers (PMCxx) These registers set the digital I/O or analog input in 1-bit units. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 4-38. Format of Port Mode Control Register 20-, 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC1 1 1 1 PMC14 PMC13 PMC12 PMC11 PMC10 F0061H FFH R/W PMC4 1 1 1 1 1 PMC42 PMC41 1 F0064H FFH R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC0 1 1 1 1 1 1 PMC01 PMC00 F0060H FFH R/W PMC12 1 1 1 1 1 1 1 PMC120 F006CH FFH R/W PMC14 PMC147 1 1 1 1 1 1 1 F006EH FFH R/W PMCmn Pmn pin digital I/O/analog input selection (m = 1, 4, 12, 14; n = 0 to 4, 7) 0 Digital I/O (alternate function other than analog input) 1 Analog input Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register m (PMm). 2. Do not set the pin set by the PMC register as digital I/O by the analog input channel specification register (ADS). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 132 RL78/G12 CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register (ADPC) This register switches the P20/ANI0 to P23/ANI3 pins to digital I/O of port or analog input of A/D converter. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 4-39. Format of A/D Port Configuration Register (ADPC) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPC0 F0076H 00H R/W ADPC2 ADPC1 ADPC0 Analog input (A)/digital I/O (D) switching ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 0 0 0 A A A A 0 0 1 D D D D 0 1 0 D D D A 0 1 1 D D A A 0 0 D A A A 1 Other than the above Setting prohibited Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2. 2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel specification register (ADS). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 133 RL78/G12 CHAPTER 4 PORT FUNCTIONS (8) Peripheral I/O redirection register (PIOR) This register is used to specify whether to enable or disable the peripheral I/O redirect function. This function is used to switch ports to which alternate functions are assigned. Use the PIOR register to assign a port to the function to redirect and enable the function. In addition, can be changed the settings for redirection until its function enable operation. The PIOR register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 4-40. Format of Peripheral I/O Redirection Register (PIOR) Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIOR 0 0 0 0 PIOR3 PIOR2 PIOR1 PIOR0 F0077H 00H R/W 20-, 24-pin products Bit PIOR3 Note 1 PIOR2 PIOR1 PIOR0 Setting value Function 0 1 SCK01 P42 P02 Note 2 SI01 P125 P00 Note 2 SO01 P41 P01 Note 2 SCL01 P42 P02 Note 2 SDA01 P41 P01 Note 2 TI02 P41 P122 TI03 P42 P121 RxD0 P11 P61 TxD0 P12 P60 INTP2 P13 P122 INTP3 P14 P121 30-pin products Bit - PIOR3 PIOR2 PIOR1 SDAA0 P61 P13 TxD2 Note 1 P13 - RxD2 Note 1 P14 - SCL20 Note 1 P15 - SDA20 Note 1 P14 - Note 1 Note 1 Note 1 TxD0 2. - (fixed) P14 SCK20 Notes 1. 1 P60 SO20 <R> 0 SCLA0 SI20 PIOR0 Setting value Function P14 - P13 - - P15 P12 P17 RxD0 P11 P16 SCL00 P10 - SDA00 P11 - SI00 P11 - SO00 P12 - SCK00 P10 - TI02/TO02 P17 TI03/TO03 P31 P15 P14 TI04/TO04 Note 1 - P13 TI05/TO05 Note 1 - P12 TI06/TO06 Note 1 - P11 TI07/TO07 Note 1 - P10 R5F102 products. Provided only in 24-pin products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 134 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not change. Therefore, byte data can be written to the ports used for both input and output. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. 4.4.2 Reading from I/O port (1) Output mode The output latch contents are read by a transfer instruction. The output latch contents do not change. (2) Input mode The pin status is read by a transfer instruction. The output latch contents do not change. 4.4.3 Operations on I/O port (1) Output mode An operation is performed on the output latch contents, and the result is written to the output latch. The output latch contents are output from the pins. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated. (2) Input mode The pin level is read and an operation is performed on its contents. The result of the operation is written to the output latch, but since the output buffer is off, the pin status does not change. Therefore, byte data can be written to the ports used for both input and output. The data of the output latch is cleared when a reset signal is generated. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 135 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) When parts of ports 0 and 1 I/O connections with an external device by serial interface or general-purpose port that operates on 1.8 V, 2.5 V, 3 V power supply voltage are possible (20-, 24-pin products is port 1 only). External device RL78/G12 3V 4.0 V VDD 5.5 V 2.5 V 3.3 V VDD 4.0 V 1.8 V 1.8 V VDD 3.3 V Regarding inputs, normal (CMOS)/TTL input buffer switching is possible on a bit-by-bit basis by the port input mode registers (PIM0, PIM1) (PIM0 is 30-pin products only). Moreover, regarding outputs, different potentials can be supported by switching the output buffer to the N-ch open drain (VDD withstand voltage) by the port output mode registers (POM0, POM1). Following, describes the connection of a serial interface. (1) Setting procedure when using I/O pins of UART0 to UART2, CSI00 and CSI20 functions (a) Use as 1.8 V, 2.5 V, 3 V input port <1> If pull-up is needed, externally pull up the pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used). Interface Pin name 20, 24-pin product UART0 RxD0 UART1 RxD1 - P01 UART2 RxD2 - P14 CSI00 SCK00 P10 P10 SI00 P11 P11 CSI20 P11 30-pin product P11 (P16) - SCK20 Note SI20 P14 P15 Note The descriptions in parentheses indicate the case where PIOR1 = 1. <2> After reset release, the port mode is the input mode (Hi-Z). <3> Set the corresponding bit of the PIM0 and PIM1 registers to 1 to switch to the TTL input buffer. <4> VIH/VIL operates on 1.8 V, 2.5 V, 3 V operating voltage. (b) Use as 1.8 V, 2.5 V, 3 V output port <1> Pull up externally the pin to be used to the power supply of the target device (on-chip pull-up resistor cannot be used). Interface Pin name 20, 24-pin product UART0 TxD0 UART1 TxD1 - P00 UART2 TxD2 - P13 CSI00 SCK00 P10 P10 SO00 P12 P12 CSI20 SCK20 SO20 P12 30-pin product Note P12 (P17) - P15 P13 Note The descriptions in parentheses indicate the case where PIOR1 = 1. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 136 RL78/G12 CHAPTER 4 PORT FUNCTIONS <2> After reset release, the port mode changes to the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM0 and POM1 registers to 1 to set the N-ch open drain output (VDD withstand voltage) mode. <5> Set the output mode by manipulating the PM0 and PM1 registers. At this time, the output data is high level, so the pin is in the Hi-Z state. <6> Can be communication by setting the serial array unit. (2) Setting procedure when using I/O pins of IIC00 and IIC20 functions <1> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used). In case of IIC00: P10, P11 (SCL00, SDA00) In case of IIC20: P14, P15 (SDA20, SCL20) (30-pin products only) <2> After reset release, the port mode is the input mode (Hi-Z). <3> Set the output latch of the corresponding port to 1. <4> Set the corresponding bit of the POM1 register to 1 to set the N-ch open drain output (VDD withstand voltage) mode. <5> Set the corresponding bit of the PIM1 registers to 1 to switch the TTL input buffer. <6> Set the corresponding bit of the PM1 register to the output mode (data I/O is possible in the output mode). At this time, the output data is high level, so the pin is in the Hi-Z state. 2 <7> Enable the operation of the serial array unit and set the mode to the simplified I C mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 137 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Related Register When Using Alternate Function To use the alternate function of a port pin, set the port associated register and output latch as shown in Table 4-23 and 4-26. Caution If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state. See 4.6.2 for details about the applicable units and how to handle such pins. Table 4-23. Settings of Port Related Register When Using Alternate Function (20-, 24-pin products) (1/3) Pin Name Alternate Function PIORx POMx PMCxx PMxx Pxx Input 0 - - 1 x Input 1 - - 1 x Input 0 - - 1 x Output 1 0/1 - 0 1 I/O 1 1 - 0 1 Input 0 - - 1 x Input 1 - - 1 x Output 1 - - 0 1 Output 1 - - 0 1 Input - - - 1 x Input - x 1 1 x Output - x 0 0 0 Input - x 0 1 x Output - 0/1 0 0 1 Output - 0/1 0 0 1 Input - x 1 1 x Input - x 0 1 x Input - x 0 1 x Function Name P00 Note1 KR6 Note 1 Note 1 (SI01) P01 Note 1 KR7 Note 1 Note 1 (SO01) Note 1 (SDA01) P02 Note 1 KR8 Note 1 Note 1 (SCK01) (SCL01) P03 P10 Note 1 KR9 Note 2 Note 1 Note 1 Note 2 ANI16 PCLBZ0 SCK00 SCL00 P11 Note 2 Note 2 Note 2 Note 2 ANI17 SI00 Note 2 Note 2 RxD0 Note 2 SDA00 Note 2 TOOLRxD P12 Note 2 Note 2 ANI18 SO00 TxD0 Note 2 Note 2 TOOLTxD Remarks 1. Note 2 Note 2 I/O I/O - 1 0 0 1 Input - x 0 1 x Input - x 1 1 x Output - 0/1 0 0 1 Output - 0/1 0 0 1 Output - 0/1 0 0 1 x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMxx: Port mode register Pxx: Port output latch PMCxx: Port mode control register 2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 138 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-23. Settings of Port Related Register When Using Alternate Function (20-, 24-pin products) (2/3) Pin Name Alternate Function PIORx POMx PMCxx PMxx Pxx Input - - 1 1 x Input - - 0 1 x Output - - 0 0 0 Input - - 0 1 x Input - - 1 1 x Input - - 0 1 x Function Name P13 Note 2 Note 2 ANI19 TI00 Note 2 TO00 Note 2 Note 2 INTP2 P14 Note 2 Note 2 ANI20 TI01 Note 2 Note 2 Output - - 0 0 0 Input - - 0 1 x Input - - - 1 x Input - - - 1 x Input - - - 1 x Input - - - 1 x Input - - - 1 x Input - - - 1 x I/O - - - x x Input - x 1 1 x Output - 0/1 0 0 1 I/O - 1 0 0 1 Input - x 0 1 x Output - 0 0 0 0 Input - x 0 1 x Input - - 1 1 x Input - - 0 1 x Output - - 0 0 1 Output - - 0 0 1 Input - - 0 1 x Output - - 0 0 0 KR4 Input 0 - - 1 x SCLA0 I/O 0 - - 0 0 (TxD0) Output 1 - - 0 1 TO01 Note 2 INTP3 P20 Note 3 ANI0 Note 3 Note 3 AVREFP P21 Note 3 ANI1 Note 3 AVREFM P22, P23 Note I/O Note 3 ANI2, AN3 Note 3 3 P40 KR0 TOOL0 P41 Note 2 Note 2 ANI22 Note 2 SO01 SDA01 TI02 Note 2 TO02 Note 2 Note 2 INTP1 P42 Note 2 ANI21 Note 2 SCK01 SCL01 TI03 Remarks 1. Note 2 Note 2 Note 2 TO03 P60 Note 2 Note 2 x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMxx: Port mode register Pxx: Port output latch PMCxx: Port mode control register 2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 139 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-23. Settings of Port Related Register When Using Alternate Function (20-, 24-pin products) (3/3) Pin Name Alternate Function Function Name PIORx POMx PMCxx PMxx Pxx I/O KR5 Input 0 - - 1 x SDAA0 I/O 0 - - 0 0 (RxD0) Input 1 - - 1 x KR3 Input 0 - - 1 x (TI03) Input 1 - - 1 x (INTP3) Input 1 - - 1 x KR2 Input 0 - - 1 x (TI02) Input 1 - - 1 x (INTP2) Input 1 - - 1 x KR1 Input - - - 1 x SI01 Input - - - 1 x P137 INTP0 Input - - - 1 x Remarks 1. x: don't care PIORx: Peripheral I/O redirection register P61 P121 P122 P125 Note 4 POMxx: Port output mode register PMxx: Port mode register Pxx: Port output latch PMCxx: Port mode control register 2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). Notes 1. 2. 24-pin products only The functions of the ANI16/P10 to ANI20/P14, ANI21/P42, and ANI22/P41 pins can be selected by using the port mode control registers 1, 4 (PMC1, PMC4), analog input channel specification register (ADS), and port mode registers 1, 4 (PM1, PM4). Table 4-24. Setting the Functions of ANI16/P10 to ANI20/P14, ANI21/P42, and ANI22/P41 Pins (20-, 24-pin Products) PMC1, PMC4 Registers Digital I/O selection Analog input selection PM1, PM4 Registers ADS Register ANI16/P10 to ANI20/P14, ANI21/P42, and ANI22/P41 Pins Input mode x Digital input Output mode x Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 140 RL78/G12 Notes 3. CHAPTER 4 PORT FUNCTIONS The functions of the ANI0/P20 to ANI3/P23 pins can be selected by using the A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode register 2. Table 4-25. Setting the functions of ANI0/P20 to ANI3/P23 Pins (20-, 24-pin products) ADPC Register PM2 Register Digital I/O selection Input mode Analog input selection Input mode Output mode Output mode ADS Register x x ANI0/P20 to ANI3/P23 Pins Digital input Digital output Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. 4. Remark Setting to PORTSELB = 0 by user option byte (0001CH) x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 141 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-26. Settings of Port Related Register When Using Alternate Function (30-pin products) (1/2) Pin name Alternate Function Neme P00 Note 1 ANI17 Note 1 P12 P13 P14 Pxx - x 1 1 x Input - x 0 1 x 0/1 0 0 1 Input - - 1 1 x Output - - 0 0 0 Input - - 0 1 x Input 0 x - 1 x Output 0 0/1 - 0 1 SCL00 Output 0 0/1 - 0 1 (TI07) Input 1 x - 1 x (TO07) Output 1 0 - 0 0 SI00 Input 0 x - 1 x RxD0 Input 0 x - 1 x TOOLRxD Input 0 x - 1 x SDA00 Output 0 1 - 0 1 (TI06) Input 1 x - 1 x (TO06) Output 1 0 - 0 0 SO00 Output 0 0/1 - 0 1 TxD0 Output 0 0/1 - 0 1 TOOLTxD Output 0 0/1 - 0 1 (TI05) Input 1 x - 1 x (TO05) Output 1 0 - 0 0 TxD2 Output 0 0/1 - 0 1 SO20 Output 0 0/1 - 0 1 (SDAA0) I/O 1 1 - 0 0 (TI04) Input 1 x - 1 x (TO04) Output 1 0 - 0 0 RxD2 Input 0 x - 1 x SI20 Input 0 x - 1 x SDA20 I/O 0 1 - 0 1 (SCLA0) Output 1 1 - 0 0 (TI03) Input 1 x - 1 x (TO03) Output 1 0 - 0 0 ANI16 RxD1 P11 PMxx - Note 1 TO00 P10 PMCxx Input TxD1 Note 1 POMx Output TI00 P01 Note 1 PIORx I/O Note 1 Note 1 Note 1 SCK00 Remarks 1. x: PIORx: don't care Peripheral I/O redirection register POMxx: Port output mode register PMxx: Port mode register Pxx: Port output latch PMCxx: Port mode control register 2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 142 RL78/G12 CHAPTER 4 PORT FUNCTIONS Table 4-26. Settings of Port Related Register When Using Alternate Function (30-pin products) (2/2) Pin name Alternate Function PIORx POMx PMCxx PMxx Pxx Output 0 0 - 0 0 Name P15 PCLBUZ1 I/O Input 0 x - 1 x Output 0 0/1 - 0 1 Output 0 0/1 - 0 1 SCK20 SCL20 P16 P17 P20 Note2 (TI02) Input 1 x - 1 x (TO02) Output 1 0 - 0 0 TI01 Input 0 - - 1 x TO01 Output 0 - - 0 0 INTP5 Input 0 - - 1 x (RxD0) Input 1 - - 1 x TI02 Input 0 x - 1 x TO02 Output 0 0 - 0 0 (TxD0) Output 1 0/1 - 0 1 Input - - - 1 x ANI0 Note 2 Note 2 AVREFP P21 Note 2 ANI1 Note 2 AVREFM P22, P23 Note 2 P30 P31 Note 2 ANI2, ANI3 Note 2 Input - - - 1 x Input - - - 1 x Input - - - 1 x Input - - - 1 x INTP3 Input - - - 1 x SCK11 Input - - - 1 x Output - - - 0 1 SCL11 Output - - - 0 1 TI03 Input - - - 1 x TO03 Output - - - 0 0 INTP4 Input - - - 1 x Output - - - 0 0 I/O - - - x x Input - x - 1 x I/O - 1 - 0 1 PCLBUZ0 P40 TOOL0 P50 SI11 SDA11 INTP1 Input - x - 1 x P51 SO11 Output - - - 0 1 INTP2 Input - - - 1 x P60 SCLA0 I/O - - - 0 0 P61 SDAA0 I/O - - - 0 0 Input - - 1 1 x Input - - - 1 x Input - - 1 1 x P120 Note 1 ANI19 P137 P147 Note 1 INTP0 Note 1 ANI18 Remarks 1. Note 1 x: don't care PIORx: Peripheral I/O redirection register POMxx: Port output mode register PMxx: Port mode register Pxx: Port output latch PMCxx: Port mode control register 2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 143 RL78/G12 CHAPTER 4 PORT FUNCTIONS Notes 1. The functions of the ANI16/P01, ANI17/P00, ANI18/P147, and ANI19/P120 pins can be selected by using the port mode control registers 0, 12, 14 (PMC0, PMC12, PMC14), analog input channel specification register (ADS), and port mode registers 0, 12, 14 (PM0, PM12, PM14). Table 4-27. Setting the functions of ANI16/P03, ANI17/P02, ANI18/P147, and ANI19/P120 Pins (30-pin products) PMC0, PMC12, and PMC14 Registers Digital I/O selection Analog input selection PM0, PM12, and PM14 Registers ADS Register ANI16/P01, ANI17/P00, ANI18/P147, and ANI19/P120 Pins Input mode x Digital input Output mode x Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. 2. The functions of the ANI0/P20-ANI3/P23, ANI8/P150-ANI14/P156 pins can be selected by using the A/D port configuration register (ADPC), analog input channel specification register (ADS), and port mode register 2 and 15 (PM2, PM15). Table 4-11. Setting the functions of ANI0/P20 to ANI3/P23 Pins (30-pin products) ADPC Register Digital I/O selection Analog input selection PM2, PM15 Registers ADS Register ANI0/P20 to ANI7/P27, ANI3/P23 Pins Input mode x Digital input Output mode x Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Remark x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 144 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.6 Cautions When Using Port Function 4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode. Example When P00 is an output port, P01 to P03 are input ports (all pin statuses are high level), and the port latch value of port 0 is 00H, if the output of output port P00 is changed from low level to high level via a 1-bit manipulation instruction, the output latch value of port 0 is FFH. Explanation: The targets of writing to and reading from the Pn register of a port whose PMmn bit is 1 are the output latch and pin status, respectively. A 1-bit manipulation instruction is executed in the following order in the RL78/G12. <1> The Pn register is read in 8-bit units. <2> The targeted one bit is manipulated. <3> The Pn register is written in 8-bit units. In step <1>, the output latch value (0) of P00, which is an output port, is read, while the pin statuses of P01 to P03, which are input ports, are read. If the pin statuses of P01 to P03 are high level at this time, the read value is EH. The value is changed to FH by the manipulation in <2>. FH is written to the output latch by the manipulation in <3>. Figure 4-41. Bit Manipulation Instruction (P00) P00 Low-level output 1-bit manipulation instruction (set1 P1.0) is executed for P00 bit. P00 to P03 P00 High-level output P00 to P03 Pin status: High Port 0 output latch Port 0 output latch x x x x Pin status: High 0 0 0 0 x x x x 1 1 1 1 1-bit manipulation instruction for P00 bit <1> Port register 0 (P0) is read in 8-bit units. * For P00, an output port, the value of the port output latch (0) is read. * For P01 to P03, input ports, the pin status (1) is read. <2> Set the P00 bit to 1. <3> Write the results of <2> to the output latch of port register 0 (P0) in 8-bit units. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 145 RL78/G12 CHAPTER 4 PORT FUNCTIONS 4.6.2 Notes on specifying the pin settings If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate output function, see 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function. No specific setting is required for input pins because the output function of their alternate functions is disabled (the buffer output is Hi-Z). Table 4-29. Handling of Unused Alternate Functions Output or I/O Pins of Affected Unit Handling of Unused Alternate Functions Unused Alternate Functions Timer array units Make sure that bit m (TOmn) of timer output register m (TOm) and bit n (TOEmn) of TO0n timer output enable register m (TOEm) are set to their initial value (0). Clock/buzzer Make sure that bit 7 (PCLOEn) of clock output select register n (CKSn) is set to its PCLBUZn output circuit initial value (0). Serial array units SCKmn, SOmn, SCLmn, SDAmn, (SOmn) of serial output register m (SOm), and bit n (SOEmn) of serial output enable register m (SOEm) are set to their initial value (1 for SOmn and 0 for others) TxDn IICA Make sure that bit n (SEmn) of serial channel enable status register m (SEm), bit n SCAA0, SDAA0 Note . Disable the IICA operation by setting bit 7 (IICE0) of the IICCTL00 register to 0. Note m = 0 for TxD0 and TxD1, and m = 1 for TxD2 Example: P41/ANI22/SO01/SDA01/TI02/TO02/INTP1 pin of 20-pin products (1) When the pin is used as SO01 output P41: Specify the output mode by setting PM41 of port mode register 4 to 0. ANI22: These are input pins, so this note does not apply for A/D converter. (Setting PM41 of port mode register 4 to 0 to digital I/O) SDA01: This note does not apply Note TI02, INTP1: These are input pins, so this note does not apply. TO02: This is an output pin, so set TO02 and TOE02 of timer array unit 0 to 0. Note Changing the operation mode does not enable alternate functions assigned to pins on the same serial channel 01 with SO01, and this note does not apply to such pins. (If the CSI function is specified (MD012 = MD011 = 0), the pin does not function as a simplified I2C pin, and therefore SDA01 I/O is invalid.) (2) When the pin is used as TO01 output P41: Specify the output mode by setting PM41 of port mode register 4 to 0. ANI22: These are input pins, so this note does not apply for A/D converter. (Setting PM41 of port mode register 4 to 0 to digital I/O) SO01/SDA01: This is an output and I/O pin, so set SE01, SO01, and SOE01 of serial array unit 0 to 0, 1, and 0, respectively. TI02: These are input pins, so this note does not apply. Disabling the unused functions, including blocks that are only used for input or do not have I/O, is recommended to lower power consumption. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 146 RL78/G12 CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock operation status control register (CSC)). <2> High-speed on-chip oscillator The frequency at which to oscillate can be selected from among fIH = 24/16/12/8/4/1 MHz (TYP.) by using the option byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-chip oscillator clock. Oscillation can be stopped by executing the STOP instruction or setting the HIOSTOP bit (bit 0 of the CSC register). The frequency specified by using an option byte can be changed by using the high-speed on-chip oscillator frequency select register (HOCODIV). For details about the frequency, see Figure 5-9. Format of Highspeed On-chip Oscillator Frequency Select Register (HOCODIV). The frequencies that can be specified for the high-speed on-chip oscillator by using the option byte and the high-speed on-chip oscillator frequency select register (HOCODIV) are shown below. Power Supply Voltage Oscillation Frequency (MHz) 1 2 3 4 6 8 12 16 24 2.7 V VDD 5.5 V 2.4 V VDD < 2.7 V - 1.8 V VDD < 2.4 V - - - An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK pin. An external main system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit. As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed onchip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)). (2) Low Speed On-chip Oscillator clock This circuit oscillates a clock of fIL = 15 kHz (TYP.). The low speed on-chip oscillator clock cannot be used as the CPU clock. Only the following peripheral hardware runs on the low speed on-chip oscillator clock. * Watchdog timer * 12-bit Interval timer This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0, oscillation of the LOCO stops if the HALT or STOP instruction is executed. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 147 RL78/G12 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fIL: Low speed on-chip oscillator clock frequency 5.2 Configuration of Clock Generator The clock generator includes the following hardware. Table 5-1. Configuration of Clock Generator Item Configuration Control registers Clock operation mode control register (CMC) System clock control register (CKC) Clock operation status control register (CSC) Oscillation stabilization time counter status register (OSTC) Oscillation stabilization time select register (OSTS) Peripheral enable register 0 (PER0) Operation speed mode control register (OSMC) High-speed on-chip oscillator frequency selection register (HOCODIV) High-speed on-chip oscillator trimming register (HIOTRM) Oscillators X1 oscillator High-speed on-chip oscillator Low-speed on-chip oscillator R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 148 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 fX fEX Crystal/ceramic oscillation External input clock High-speed system clock oscillator 2. Notes 1. fIH fMX 30-pin products only. 20-, 24-pin products only. High-speed on-chip oscillator frequency selection register (HOCODIV) MSTOP Clock operation status control register (CSC) 15 kHz (TYP.) HIOSTOP fIL STOP mode signal Low-speed on-chip oscillator Clock operation status control register (CSC) HOCODIV2 HOCODIV1 HOCODIV0 24/16/12/8/6/4/3/2/1 MHz (TYP.) High-speed on-chip oscillator Option byte (000C2H) FRQSEL0 to FRQSEL3 X2/EXCLK/ P122/KR2Note1/ (TI02/INTP02)Note1 X1/P121/KR3 (TI03/INTP03)Note1 Note1 AMPH EXCLK OSCSEL Clock operation mode control register (CMC) Internal bus high-speed on-chip oscillator trimming register(HIOTRM) HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 6 HALT/STOP mode signal Option byte (000C0H) WDTON WDSTBYON fMAIN MCS MCM0 TMKA EN ADC EN IICA0 EN 12 bits Interval timer TAU0 EN Peripheral enable register 0 (PER0) SAU1 SAU0 ENNote2 EN Watchdog timer CPU clock and peripheral hardware clock source selection System clock control register (CKC) Clock output/buzzer output Operation speed mode control register (OSMC) WUTMMCK0 Controller Main system clock source selector Oscillation stabilization time counter status register (OSTC) MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 X1 oscillation stabilization time counter 3 OSTS2 OSTS1 OSTS0 Oscillation stabilization time select register (OSTS) Internal bus fCLK CPU Normal operation mode HALT mode STOP mode Standby controller Controller Figure 5-1. Block Diagram of Clock Generator A/D converter Serial interface IICA Serial arrayry unit 1 Serial arrayry unit 0 Timer array unit RL78/G12 CHAPTER 5 CLOCK GENERATOR 149 RL78/G12 Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: High-speed on-chip oscillator clock frequency fEX: External main system clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency fCLK: CPU/peripheral hardware clock frequency fIL: Low-speed on-chip oscillator clock frequency 5.3 Registers Controlling Clock Generator The following eight registers are used to control the clock generator. * Clock operation mode control register (CMC) * System clock control register (CKC) * Clock operation status control register (CSC) * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) * Peripheral enable register 0 (PER0) * Operation speed mode control register (OSMC) * High-speed on-chip oscillator frequency selection register (HOCODIV) * High-speed on-chip oscillator trimming register (HIOTRM) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 150 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.1 Clock operation mode control register (CMC) This register is used to set the operation mode of the X1/P121 and X2/EXCLK/P122 pins, and to select a gain of the oscillator. The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This register can be read by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-2. Format of Clock Operation Mode Control Register (CMC) Address: FFFA0H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CMC EXCLK OSCSEL 0 0 0 0 0 AMPH EXCLK OSCSEL 0 0 High-speed system clock pin operation mode X1/P121/KR3 pin Input port mode Input port X2/EXCLK/P122/KR2 pin 0 1 X1 oscillation mode Crystal/ceramic resonator connection 1 0 Input port mode Input port 1 1 External clock input mode Input port AMPH Control of X1 clock oscillation frequency 0 1 MHz fX 10 MHz 1 10 MHz < fX 20 MHz Cautions 1. External clock input The CMC register can be written only once after reset release, by an 8-bit memory manipulation instruction. When using the CMC register with its initial value (00H), be sure to set the register to 00H after a reset ends in order to prevent malfunction due to a program loop. Such a malfunction becomes unrecoverable when a value other than 00H is mistakenly written. 2. After reset release, set the CMC register before X1 oscillation is started as set by the clock operation status control register (CSC). 3. Specify the settings for the AMPH bits while fIH is selected as fCLK after a reset ends (before fCLK is switched to fMX). <R> 4. Switch the operation mode of the X1/X2 pins only when MSTOP = 1. 5. Although the maximum system clock frequency is 24 MHz, the maximum frequency of the X1 oscillator is 20 MHz. Remark fX: X1 clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 151 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.2 System clock control register (CKC) This register is used to select a CPU/peripheral hardware clock and a main system clock. The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 5-3. Format of System Clock Control Register (CKC) Address: FFFA4H After reset: 00H R/W Note Symbol 7 6 <5> <4> 3 2 1 0 CKC 0 0 MCS MCM0 0 0 0 0 MCS Status of Main system clock (fMAIN) 0 High-speed on-chip oscillator clock (fIH) 1 High-speed system clock (fMX) MCM0 Main system clock (fMAIN) operation control 0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN) 1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN) Note Bit 5 is read-only. Caution Be sure to set undefined bits to 0. Remark fIH: High-speed on-chip oscillator clock frequency fMX: High-speed system clock frequency fMAIN: Main system clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 152 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.3 Clock operation status control register (CSC) This register is used to control the operations of the high-speed system clock and high-speed on-chip oscillator clock, (except the low-speed on-chip oscillator clock). The CSC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to C0H. Figure 5-4. Format of Clock Operation Status Control Register (CSC) Address: FFFA1H After reset: C0H R/W Symbol <7> 6 5 4 3 2 1 <0> CSC MSTOP 1 0 0 0 0 0 HIOSTOP MSTOP High-speed system clock operation control X1 oscillation mode External clock input mode 0 X1 oscillator operating External clock from EXCLK pin is valid 1 X1 oscillator stopped External clock from EXCLK pin is invalid HIOSTOP Input port mode Input port High-speed on-chip oscillator clock operation control 0 High-speed on-chip oscillator clock operating 1 High-speed on-chip oscillator clock stopped Cautions 1. After reset release, set the clock operation mode control register (CMC) before setting the CSC register. 2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP bit to 0 after releasing reset. Note that if the OSTS register is being used with its default settings, the OSTS register is not required to be set here. 3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization time of the X1 clock by using the oscillation stabilization time counter status register (OSTC). 4. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the CSC register. 5. The setting of the flags of the register to stop clock oscillation (invalidate the external clock input) and the condition before clock oscillation is to be stopped are as Table 5-2. Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Clock X1 clock External main system clock High-speed on-chip oscillator clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Condition Before Stopping Clock (Invalidating External Clock Input) Setting of CSC Register Flags CPU and peripheral hardware clocks operate with a highspeed on-chip oscillator clock. (MCS = 0) MSTOP = 1 CPU and peripheral hardware clocks operate with a highspeed system clock.(MCS = 1) HIOSTOP = 1 153 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.4 Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case: * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register (CSC)) = 1 clear the OSTC register to 00H. Remark The oscillation stabilization time counter starts counting in the following cases. * When oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 MSTOP = 0) * When the STOP mode is released R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 154 RL78/G12 CHAPTER 5 CLOCK GENERATOR Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC After reset: 00H 7 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status fX = 10 MHz fX = 20 MHz 0 0 0 0 0 0 0 0 2 /fX max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 /fX min. 8 8 25.6 s min. 12.8 s min. 9 51.2 s min. 25.6 s min. 1 1 0 0 0 0 0 0 2 /fX min. 1 1 1 0 0 0 0 0 2 /fX min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 /fX min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 /fX min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 /fX min. 3.27 ms min. 1.64 ms min. 1 1 1 1 1 1 1 0 2 /fX min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 /fX min. 26.21 ms min. 13.11 ms min. 10 11 13 15 17 18 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 155 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.5 Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS register after the STOP mode is released. When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using the OSTC register. The OSTS register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets the OSTS register to 07H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 156 RL78/G12 CHAPTER 5 CLOCK GENERATOR Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 0 0 0 2 /fX 0 0 1 2 /fX 0 1 0 2 /fX 0 1 1 2 /fX Oscillation stabilization time selection fX = 10 MHz 51.2 s 25.6 s 10 102.4 s 51.2 s 11 204.8 s 102.4 s 13 819.2 s 409.6 s 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.21 ms 13.11 ms 0 0 2 /fX 1 0 1 2 /fX 1 1 0 2 /fX 1 1 fX = 20 MHz 12.8 s 9 1 1 25.6 s 8 2 /fX Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before executing the STOP instruction. 2. Change the setting of the OSTS register before setting the MSTOP bit of the clock operation status control register (CSC) to 0. 3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the OSTS register. In the following cases, set the oscillation stabilization time of the OSTS register to the value greater than the count value which is to be checked by the OSTC register after the oscillation starts. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after the STOP mode is released.) 5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 157 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.6 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each function before specifying the initial settings of the peripheral functions. * 12-bit Interval timer * A/D converter * Serial interface IICA * Serial array unit 1 * Serial array unit 0 * Timer array unit 0 The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN TMKAE 0 Control of 12-bit interval timer input clock supply Stops input clock supply. * SFR used by the 12-bit interval timer cannot be written. * The 12-bit interval timer is in the reset status. 1 Enables input clock supply. * SFR used by the 12-bit interval timer can be read and written. ADCEN 0 Control of A/D converter input clock supply Stops input clock supply. * SFR used by the A/D converter cannot be written. * The A/D converter is in the reset status. 1 Enables input clock supply. * SFR used by the A/D converter can be read and written. IICA0EN 0 Control of serial interface IICA input clock supply Stops input clock supply. * SFR used by the serial interface IICA cannot be written. * The serial interface IICA is in the reset status. 1 Enables input clock supply. * SFR used by the serial interface IICA can be read and written. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 158 RL78/G12 CHAPTER 5 CLOCK GENERATOR Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN SAU1EN Control of serial array unit 1 input clock supply Stops input clock supply. (Fixed as 0 in 20-, and 24-pin products) 0 * SFR used by the serial array unit 1 cannot be written. * The serial array unit 1 is in the reset status. Enables input clock supply. 1 * SFR used by the serial array unit 1 can be read and written. SAU0EN Control of serial array unit 0 input clock supply Stops input clock supply. 0 * SFR used by the serial array unit 0 cannot be written. * The serial array unit 0 is in the reset status. Enables input clock supply. 1 * SFR used by the serial array unit 0 can be read and written. TAU0EN Control of timer array unit input clock supply Stops input clock supply. 0 * SFR used by timer array unit cannot be written. * Timer array unit is in the reset status. Enables input clock supply. 1 * SFR used by timer array unit can be read and written. Caution Be sure to clear undefined bits to 0. 5.3.7 Operation speed mode control register (OSMC) The OSMC register can be used to control supply of the operation clock for the 12-bit interval timer. When operating the 12-bit interval timer, set WUTMMCK0 = 1 beforehand and do not set WUTMMCK0 = 0 until the timer is stopped. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-8. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC 0 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Supply of operation clock for 12-bit interval timer 0 Stops Clock supply 1 Low-speed on-chip oscillator clock (fIL) supply R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 159 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.3.8 High-speed on-chip oscillator frequency selection register (HOCODIV) This register is used to change the frequency of the high-speed on-chip oscillator clock set with the option byte (000C2H). The available frequency varies depending on the value of the FRQSEL3 bit of the option byte (000C2H). HOCODIV can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to default value (undefined). Figure 5-9 Format of High-Speed On-Chip Oscillator Frequency Selection Register (HOCODIV) Address: F00A8H After reset: Undefined R/W Symbol 7 6 5 4 3 HOCODIV 0 0 0 0 0 HOCODIV 2 HOCODIV 1 HOCODIV 0 1 0 HOCODIV 2 HOCODIV 1 HOCODIV 0 High-speed on-chip oscillator clock frequency selection FRQSEL3 bit is 0 FRQSEL3 bit is 1 0 0 0 24 MHz Setting prohibited 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 1 0 1 Setting prohibited 1 MHz Other than above <R> 2 Setting prohibited Cautions 1. Set the HOCODIV register within the operable voltage range of the flash operation mode set in the option byte (000C2H) before and after the frequency change. Option byte (000C2H) value CMODE1 CMODE2 1 0 1 1 Operating frequency Operating voltage range range 1 MHz to 8 MHz 1.8 V to 5.5 V HS (high-speed main) 1 MHz to 16 MHz 2.4 V to 5.5 V mode 1 MHz to 24 MHz 2.7 V to 5.5 V Flash operation mode LS (low-speed main) mode <R> 2. Set the HOCODIV register with the high-speed on-chip oscillator clock (fIH) selected as <R> 3. After settings are changed with the HOCODIV register, the frequency is switched after the CPU/peripheral hardware clock (fCLK). the following transition time has elapsed. *Operation for three clocks at the pre-change frequency *CPU/peripheral hardware clock wait at the post-change frequency for up to three clocks 5.3.9 High-speed on-chip oscillator trimming register (HIOTRM) This register is used to adjust the accuracy of the high-speed on-chip oscillator. With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock input (timer array unit), and so on, the accuracy can be adjusted. The HIOTRM register can be set by an 8-bit memory manipulation instruction. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 160 RL78/G12 CHAPTER 5 CLOCK GENERATOR Caution The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment. When the temperature and VDD voltage change, accuracy adjustment must be executed regularly or before the frequency accuracy is required. Figure 5-10. Format of High-Speed On-chip Oscillator Trimming Register (HIOTRM) Address: F00A0H After reset: Note R/W Symbol 7 6 5 4 3 2 1 0 HIOTRM 0 0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High-speed on-chip Minimum speed oscillator 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 1 0 0 * * * 1 1 1 1 1 0 1 1 1 1 1 1 Maximum speed Note The reset value differs for each chip. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 161 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as follows. * Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1 * External clock input: EXCLK, OSCSEL = 1, 1 When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0). When the pins are not used as input port pins, either, see 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins. Figure 5-11 shows an example of the external circuit of the X1 oscillator. Figure 5-11. Example of External Circuit of X1 Oscillator (a) Crystal or ceramic oscillation (b) External clock VSS X1 X2 External clock EXCLK Crystal resonator or ceramic resonator Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the Figure 511 to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 162 RL78/G12 CHAPTER 5 CLOCK GENERATOR Figure 5-12 shows examples of incorrect resonator connection. Figure 5-12. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 VSS X1 X2 NG NG NG (c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists under the X1 and X2 wires. VSS VSS X1 X1 X2 X2 Note Power supply/GND pattern Note Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board. Do not configure a layout that will cause capacitance elements and affect the oscillation characteristics. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 163 RL78/G12 CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (e) Wiring near high alternating current (f) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current (g) Signals are fetched VSS X1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 X2 164 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.4.2 High-speed on-chip oscillator The high-speed on-chip oscillator is incorporated in the RL78/G12. The frequency can be selected from among 24, 16, 12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset release. 5.4.3 Low-speed on-chip oscillator The low-speed on-chip oscillator is incorporated in the RL78/G12. The low-speed on-chip oscillator clock is used only as the watchdog timer, and 12-bit interval timer clock. The lowspeed on-chip oscillator clock cannot be used as the CPU clock. This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed mode control register (OSMC), or both are set to 1. Unless the watchdog timer is stopped and WUTMMCK0 is a value other than zero, oscillation of the low-speed on-chip oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the program freezes. 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1). * Main system clock fMAIN * High-speed system clock fMX X1 clock fX External main system clock fEX * High-speed on-chip oscillator clock fIH * Low-speed on-chip oscillator clock fIL * CPU/peripheral hardware clock fCLK The CPU starts operation when the high-speed on-chip oscillator starts outputting after a reset release in the RL78/G12. When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-13. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 165 RL78/G12 CHAPTER 5 CLOCK GENERATOR <R> Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When voltage detector (LVD) is used) Power supply voltage (VDD) LVD release reset voltage 0V <1> Internal reset signal Switched by software Reset processingNote 3 <3> <5> High-speed on-chip oscillator clock CPU clock High-speed system clock <2> High-speed on-chip oscillator clock (fIH) Note 1 High-speed system clock (fMX) (when X1 oscillation selected) <4> X1 clock oscillation stabilization timeNote 2 Starting X1 oscillation is specified by software. <1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit. <2> When the power supply voltage exceeds detection voltage of voltage detector (LVD), the reset is released and the high-speed on-chip oscillator automatically starts oscillation. <3> The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for the voltage of the power supply or regulator to stabilize has been performed after reset release. <4> Set the start of oscillation of the X1 clock via software (see 5.6.2 Example of setting X1 oscillation clock). <5> When switching the CPU clock to the X1 clock, wait for the clock oscillation to stabilize, and then switch the clock via software. Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 2. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC). <R> 3. .For the reset processing time, see CHAPTER 19 POWER-ON-RESET CIRCUIT. Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK pin is used. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 166 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.6 Controlling Clock 5.6.1 Example of setting high-speed on-chip oscillator After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. The frequency of the high-speed on-chip oscillator can be selected by using FRQSEL0 to FRQSEL3 of the option byte (000C2H). This frequency can be changed with the high-speed on-chip oscillator frequency select register (HOCODIV). [Option byte setting] Address: 000C2H Option byte 7 6 CMODE1 CMODE0 (000C2H) 0/1 0/1 CMODE1 CMODE0 1 0 LS (low speed main) mode VDD = 1.8 V to 5.5 V @ 1 MHz to 8 MHz 1 1 HS (high speed main) mode VDD = 2.4 V to 5.5 V @ 1 MHz to 16 MHz VDD = 2.7 V to 5.5 V @ 1 MHz to 24 MHz <R> Other than above 5 4 1 3 2 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 0/1 0/1 0/1 0/1 0 Setting of flash operation mode Setting prohibited FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 1 0 1 1 4 MHz 1 0 1 1 MHz 1 Other than above Frequency of the high-speed on-chip oscillator Setting prohibited [High-speed on-chip oscillator frequency selection register (HOCODIV) setting] Address: F00A8H HOCODIV 7 6 5 4 3 0 0 0 0 0 HOCODIV 2 HOCODIV 1 HOCODIV 0 2 1 High-speed on-chip oscillator clock frequency selection FRQSEL3 bit is 0 FRQSEL3 bit is 1 0 0 0 24 MHz Setting prohibited 0 0 1 12 MHz 16 MHz 0 1 0 6 MHz 8 MHz 0 1 1 3 MHz 4 MHz 1 0 0 Setting prohibited 2 MHz 1 0 1 Setting prohibited 1 MHz Other than above R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 0 HOCODIV 2 HOCODIV 1 HOCODIV 0 Setting prohibited 167 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.6.2 Example of setting X1 oscillation clock After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time select register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control register (CKC). [Register settings] Set the register in the order of <1> to <5> below. <1> Set (1) the OSCSEL bit of the CMC register, except for the cases fX > 10 MHz, in such cases set (1) the AMPH bit, to operate the X1 oscillator. CMC 7 6 EXCLK OSCSEL 0 1 5 4 3 2 1 0 0 0 0 0 0 AMPH 1 AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less. <2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode. Example: Setting values when a wait of at least 102.4 s is set based on a 10 MHz resonator. 7 OSTS 0 6 0 5 0 4 0 3 2 1 0 OSTS2 OSTS1 OSTS0 0 1 0 0 0 <3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator. 7 CSC 6 5 4 3 2 1 0 0 0 0 0 0 MSTOP 0 HIOSTOP 0 <4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize. Example: Wait until the bits reach the following values when a wait of at least 102.4 s is set based on a 10 MHz resonator. OSTC 7 6 5 4 3 2 1 0 MOST8 MOST9 MOST10 MOST11 MOST13 MOST15 MOST17 MOST18 1 1 1 0 0 0 0 0 <5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock. CKC 7 6 0 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 5 4 MCS MCM0 0 1 3 2 1 0 0 0 0 0 168 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.6.3 CPU clock status transition diagram Figure 5-14 shows the CPU clock status transition diagram of this product. Figure 5-14. CPU Clock Status Transition Diagram Power ON (A) High-speed on-chip oscillator: Woken up X1 oscillation/EXCLK input: Stops (input port mode) VDD 1.51 V to 0.03 V > 1.51 V to 0.03 V VDD = Reset release High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops (input port mode) > 1.8 V(operation guaranteed range:Transition voltage is defined by the LVD) VDD = (B) High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Selectable by CPU CPU: Operating high-speed on-chip oscillator (F) CPU: High-speed on-chip oscillator => STOP High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops (H) CPU: High-speed on-chip oscillator => SNOOZE (D) High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Stops CPU: High-speed on-chip oscillator => HALT (C) CPU: Operating with X1 oscillation or EXCLK input High-speed on-chip oscillator: Operating X1 oscillation/EXCLK input: Oscillatable (G) High-speed on-chip oscillator: Selectable by CPU X1 oscillation/EXCLK input: Operating (E) CPU: Internal highspeed oscillation => HALT CPU: X1 oscillation/EXCLK input => STOP High-speed on-chip oscillator: Stops X1 oscillation/EXCLK input: Stops High-speed on-chip oscillator: Oscillatable X1 oscillation/EXCLK input: Operating R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 169 RL78/G12 CHAPTER 5 CLOCK GENERATOR Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/3) (1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A) Status Transition SFR Register Setting (A) (B) SFR registers do not have to be set (default status after reset release). (2) CPU operating with high-speed system clock (C) after reset release (A) (The CPU operates with the high-speed on-chip oscillator clock immediately after a reset release (B).) (Setting sequence of SFR registers) Setting Flag of SFR Register CMC Register Note1 Status Transition EXCLK OSCSEL AMPH (A) (B) (C) 0 1 0 OSTS CSC OSTC CKC Register Register Register Register MSTOP Note 2 0 (X1 clock: 1 MHz fX 10 MHz) (A) (B) (C) Must be 1 checked 0 1 1 Note 2 0 (X1 clock: 10 MHz < fX 20 MHz) (A) (B) (C) MCM0 Must be 1 checked 1 1 x Note 2 (external main clock) 0 Must not 1 be checked Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. 2. Set the oscillation stabilization time as follows. * Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. x: don't care 2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14 . R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 170 RL78/G12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/3) (3) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C) (Setting sequence of SFR registers) CMC Register Setting Flag of SFR Register Status Transition Note 1 OSTS CSC Register Register Register CKC MSTOP MCM0 OSTC Register EXCLK OSCSEL AMPH 0 1 0 Note 2 0 Must be checked 1 0 1 1 Note 2 0 Must be checked 1 1 1 x Note 2 0 Must not be checked 1 (B) (C) (X1 clock: 1 MHz fX 10 MHz) (B) (C) (X1 clock: 10 MHz < fX 20 MHz) (B) (C) (external main clock) Unnecessary if these registers Unnecessary if the CPU is operating with are already set the high-speed system clock Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation instruction after reset release. This setting is not necessary if it has already been set. 2. Set the oscillation stabilization time as follows. * Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time Oscillation stabilization time set by the oscillation stabilization time select register (OSTS) Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). (4) CPU clock changing from high-speed system clock (C) to high-speed on-chip oscillator clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register Status Transition (C) (B) CSC Register Oscillation accuracy CKC Register HIOSTOP stabilization time MCM0 0 30 s 0 Unnecessary if the CPU is operating with the high-speed on-chip oscillator clock (5) * HALT mode (D) set while CPU is operating with high-speed on-chip oscillator clock (B) * HALT mode (E) set while CPU is operating with high-speed system clock (C) Status Transition (B) (D) Setting Executing HALT instruction (C) (E) Remarks 1. x: don't care 2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 171 RL78/G12 CHAPTER 5 CLOCK GENERATOR Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/3) (6) * STOP mode (F) set while CPU is operating with high-speed on-chip oscillator clock (B) * STOP mode (G) set while CPU is operating with high-speed system clock (C) (Setting sequence) Status Transition Setting (B) (F) - Stopping peripheral Executing STOP functions that cannot (C) (G) operate in STOP mode In X1 oscillation instruction Sets the OSTS register - External main system clock (7) CPU changing from STOP mode (F) to SNOOZE mode (H) For details about the setting for switching from the STOP mode to the SNOOZE mode, see 10.8 SNOOZE Mode Function, 11.5.7 SNOOZE mode function and 11.6.3 SNOOZE mode function. Remark (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14. 5.6.4 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-4. Changing CPU Clock CPU Clock Before Change Condition Before Change Processing After Change After Change Stabilization of X1 oscillation Operating current can be reduced by chip oscillator * OSCSEL = 1, EXCLK = 0, MSTOP = 0 stopping high-speed on-chip oscillator clock * After elapse of oscillation stabilization time (HIOSTOP = 1). High-speed on- X1 clock External main Enabling external clock input from the system clock EXCLK pin * OSCSEL = 1, EXCLK = 1, MSTOP = 0 X1 clock High-speed on- Oscillation of high-speed on-chip oscillator X1 oscillation can be stopped chip oscillator * HIOSTOP = 0 (MSTOP = 1). clock * After elapse of oscillation stabilization time External main Transition not possible - system clock External main High-speed on- Oscillation of high-speed on-chip oscillator External main system clock input can system clock chip oscillator * HIOSTOP = 0 be disabled (MSTOP = 1). clock * After elapse of oscillation stabilization time X1 clock Transition not possible R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 - 172 RL78/G12 CHAPTER 5 CLOCK GENERATOR 5.6.5 Time required for switchover of CPU clock and main system clock The main system clock can be switched between the high-speed on-chip oscillator clock and the high-speed system clock by specifying bit 4 (MCM0) of the system clock control register (CKC). The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues on the pre-switchover clock for several clocks (see Table 5-5). Whether the main system clock is operating on the high-speed system clock or high-speed on-chip oscillator clock can be ascertained using bit 5 (MCS) of the CKC register. When the CPU clock is switched, the peripheral hardware is also switched. Table 5-5. Maximum Number of Clocks Required for fIH fMX Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 1 (f MAIN = f IH ) (f MAIN = f MX ) 0 f MX f IH (f MAIN = f IH ) f MX <f IH 1 f MX f IH 2fMX/fIH clock (f MAIN = f MX ) f MX <f IH 2 clock 2 clock 2fIH/fMX clock Remarks 1. Number of CPU clocks before switchover. 2. Calculate the number of clocks by rounding to the nearest whole number. Example When switching the main system clock from the high-speed system clock to the high-speed onchip oscillator clock (@ oscillation with fIH = 8 MHz selected, fMX = 10 MHz) 2 fIH/fMX = 2(10/8) = 2.5 3 clocks 5.6.6 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-6. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Clock Conditions Before Clock Oscillation Is Stopped Flag Settings of SFR (External Clock Input Disabled) Register High-speed on-chip MCS = 1 oscillator clock (The CPU is operating on the high-speed system clock.) X1 clock MCS = 0 External main system clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 HIOSTOP = 1 MSTOP = 1 (The CPU is operating on the high-speed on-chip oscillator clock.) 173 RL78/G12 <R> CHAPTER 5 CLOCK GENERATOR 5.7 Resonator and Oscillator Constants The resonators for which the operation is verified and their oscillator constants are shown below. Cautions 1. The constants for these oscillator circuits are reference values based on specific environments set up for evaluation by the manufacturers. For actual applications, request evaluation by the manufacturer of the oscillator circuit mounted on a board. Furthermore, if you are switching from a different product to this microcontroller, and whenever you change the board, again request evaluation by the manufacturer of the oscillator circuit mounted on the new board. 2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use the RL78/G12 so that the internal operation conditions are within the specifications of the DC and AC characteristics. Figure 5-15. External Circuit Example VSS X1 C1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 X2 Rd C2 174 RL78/G12 CHAPTER 5 CLOCK GENERATOR As of September, 2012 Manufacturer Resonator Part Number SMD/ Frequency Frash Lead (MHz) operation modeNote 1 Murata Ceramic Manufacturing resonator Recommended Circuit Oscillation Voltage Note 2 Range (V) Constants (reference) C1 (pF) C2 (pF) Rd (k) MIN. MAX. (47) (47) 0 1.8(LS) 5.5 (39) (39) 0 2.4(HS) (15) (15) 0 (39) (39) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (15) (15) 0 (10) (10) 0 (15) (15) 0 (10) (10) 0 (15) (15) 0 (10) (10) 0 (15) (15) 0 CSTCC2M00G56-R0 SMD 2.000 CSTCR4M00G55-R0 SMD 4.000 CSTLS4M00G53-B0 READ CSTCR4M19G55-R0 SMD CSTLS4M19G53-B0 READ CSTCR4M91G53-R0 SMD CSTLS4M91G53-B0 READ CSTCR5M00G53-R0 SMD CSTLS5M00G53-B0 READ CSTCR6M00G53-R0 SMD CSTLS6M00G53-B0 READ CSTCE8M00G52-R0 SMD CSTLS8M00G53-B0 READ CSTCE8M38G52-R0 SMD CSTLS8M38G53-B0 read CSTCE10M0G52-R0 SMD CSTLS10M0G53-B0 READ CSTCE12M0G52-R0 SMD 12.000 (10) (10) 0 CSTCE16M0V53-R0 SMD 16.000 (15) (15) 0 CSTLS16M0X51-B0 READ (5) (5) 0 CSTCE20M0V51-R0 SMD (5) (5) 0 CSTLS20M0X51-B0 READ (5) (5) 0 LSHS Co., Ltd. Notes 1. 2. Remark 4.194 4.915 5.000 6.000 8.000 8.388 10.000 20.000 HS 2.4 5.5 2.7 5.5 Set the flash operation mode by using CMODE1 and CMODE0 bits of the option byte (000C2H/010C2H). Values in parentheses in the C1, C2 columns indicate an internal capacitance. Relationship between operation voltage width, operation frequency of CPU and operation mode is as below. HS (High speed main) mode: 2.7 V VDD 5.5 V@1 MHz to 24 MHz 2.4 V VDD 5.5 V@1 MHz to 16 MHz LS (Low speed main) mode: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 1.8 V VDD 5.5 V@1 MHz to 8 MHz 175 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT CHAPTER 6 TIMER ARRAY UNIT The timer array unit has four/eight 16-bit timers. Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more "channels" can be used to create a high-accuracy timer. TIMER ARRAY UNIT channel 0 16-bit timers channel 1 channel 2 channel 3 Note channel 4 channel 7 Note Provided only in 30-pin products For details about each function, see the table below. Independent channel operation function Simultaneous channel operation function * Interval timer ( refer to 6.7.1) * One-shot pulse output( refer to 6.8.1) * Square wave output ( refer to 6.7.1) * PWM output( refer to 6.8.2) * Multiple PWM output( refer to 6.8.3) * External event counter ( refer to 6.7.2) Note ( refer to 6.7.3) * Divider * Input pulse interval measurement ( refer to 6.7.4) * Measurement of high-/low-level width of input signal ( refer to 6.7.5) * Delay counter ( refer to 6.7.6) Note Only channel 0 It is possible to use the 16-bit timer of channels 1 and 3 as two 8-bit timers (higher and lower). The functions that can use channels 1 and 3 as 8-bit timers are as follows: * Interval timer/square wave output * External event counter (lower 8-bit timer only) * Delay counter (lower 8-bit timer only) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 176 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.1 Functions of Timer Array Unit Timer array unit has the following functions. 6.1.1 Independent channel operation function By operating a channel independently, it can be used for the following purposes without being affected by the operation mode of other channels. (1) Interval timer Each timer of a unit can be used as a reference timer that generates an interrupt (INTTM0n) at fixed intervals. Compare operation Operation clock Channel n Interrupt signal (INTTM0n) (2) Square wave output A toggle operation is performed each time INTTM0n interrupt is generated and a square wave with a duty factor of 50% is output from a timer output pin (TO0n). Operation clock Compare operation Channel n Timer output (TO0n) (3) External event counter Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid edges of a signal input to the timer input pin (TI0n) has reached a specific value. Timer input (TI0n) Edge detection Compare operation Interrupt signal (INTTM0n) Channel n (4) Divider function (channel 0 only) A clock input from a timer input pin (TI00) is divided and output from an output pin (TO00). Timer input (TI00) Compare operation Channel n Timer output (TO00) (5) Input pulse interval measurement Counting is started by the valid edge of a pulse signal input to a timer input pin (TI0n). The count value of the timer is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured. Timer input (TI0n) Edge detection R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Capture operation Channel n xxH 00H Start Capture 177 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (6) Measurement of high-/low-level width of input signal Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is captured at the other edge. In this way, the high-level or low-level width of the input signal can be measured. Edge detection Timer input (TI0n) Capture operation Channel n 00H xxH Start Capture (7) Delay counter Counting is started at the valid edge of the signal input to the timer input pin (TI0n), and an interrupt is generated after any delay period. Edge detection Timer input (TI0n) Compare operation Channel n Interrupt signal (INTTM0n) Start Remark n: Channel number (n = 0 to 7) 6.1.2 Simultaneous channel operation function By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels (timers operating according to the master channel), channels can be used for the following purposes. (1) One-shot pulse output Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse width. Timer input (TI0n) Edge detection Compare operation Interrupt signal (INTTM0n) Channel n (master) Compare operation Channel p (slave) Output timing Timer output (TO0p) Toggle (Master) Start (Master) Pulse width Toggle (Slave) (2) PWM (Pulse Width Modulation) output Two channels are used as a set to generate a pulse with a specified period and a specified duty factor. Operation clock Compare operation Interrupt signal (INTTM0n) Channel n (master) Compare operation Channel p (slave) Timer output (TO0p) Duty Cycle R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 178 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (3) Multiple PWM (Pulse Width Modulation) output By extending the PWM function and using one master channel and two or more slave channels, up to three types of PWM signals that have a specific period and a specified duty factor can be generated. Operation clock Compare operation Interrupt signal (INTTM0n) Channel n (master) Compare operation Channel p (slave) Timer output (TO0p) Duty Cycle Compare operation Channel q (slave) Timer output (TO0q) Duty Cycle Caution The rules apply when using multiple channels simultaneously. For details about the rules of simultaneous channel operation function, see 6.4.1 Basic Rules of Simultaneous Channel Operation Function. Remark n: Channel number (n = 0 to 7) p, q: Slave channel number (n < p < q 7) 6.1.3 8-bit timer operation function (channels 1 and 3 only) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3. Caution There are several rules for using 8-bit timer operation function. For details, see 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 179 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.2 Configuration of Timer Array Unit Timer array unit includes the following hardware. Table 6-1. Configuration of Timer Array Unit Item Timer/counter Configuration Timer/counter register 0n (TCR0n) Register Timer data register 0n (TDR0n) Timer input TI00 to TI07 Timer output TO00 to TO07 pins, output controller Control registers <Registers of unit setting block> * Peripheral enable register 0 (PER0) * Timer clock select register 0 (TPS0) * Timer channel enable status register 0 (TE0) * Timer channel start register 0 (TS0) * Timer channel stop register 0 (TT0) * Timer input select register 0 (TIS0) * Timer output enable register 0 (TOE0) * Timer output register 0 (TO0) * Timer output level register 0 (TOL0) * Timer output mode register 0 (TOM0) <Registers of each channel> * Timer mode register 0n (TMR0n) * Timer status register 0n (TSR0n) * Noise filter enable register 1 (NFEN1) * Port mode control register 0, 1, 4 (PMC0, PMC1, PMC4) * Port mode register 0, 1, 3, 4 (PM0, PM1, PM3, PM4) * Port register (P0, P1, P3, P4) Remark n: Channel number (n = 0 to 7) Alternate port for timer I/O of the timer array unit channels varies depending on products. Table 6-2. Timer I/O Pins in the Products Timer array unit channel 30-pin products 20, 24-pin products Channel 0 P00/TI00, P01/TO00 P13/TI00/TO00 Channel 1 P16/TI01/TO01 P14/TI01/TO01 Channel 2 P17/TI02/TO02 (P15/TI02/TO02) P41/TI02/TO02 (P122/TI02) Channel 3 P31/TI03/TO03 (P14/TI03/TO03) P42/TI03/TO03 (P121/TI03) Channel 4 (P13/TI04/TO04) x Channel 5 (P12/TI05/TO05) x Channel 6 (P11/TI06/TO06) x Channel 7 (P10/TI07/TO07) x Remarks 1. If a pin is to be used for both timer input and timer output, it can be used only for timer input or timer output. 2. x: The channel is not available 3. The pin names in parentheses are for PIOR0 = 1 in 30-pin products or PIOR2 = 1 in 24-, 20-pin products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 180 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figures 6-1 to 6-3 show the block diagrams of the timer array unit. Figure 6-1. Entire Configuration of Timer Array Unit (20-, and 24-pin products) Timer clock select register 0 (TPS0) PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 2 2 4 fCLK 4 Prescaler 1 fCLK/2 , fCLK/22, fCLK/28, fCLK/210, fCLK/24,fCLK/26 fCLK/212,fCLK/214 Timer input select register 0 (TIS0) Peripheral enable register 0 (PER0) fCLK/20 - fCLK/215 Selector TAU0EN Selector Selector Selector CK03 TIS1 TIS0 CK02 CK01 CK00 Slave/master controller TO00 INTTM00 (Timer interrupt) TI00 Channel 0 TI01 Selector TO01 fIL Channel 1 Slave/master controller INTTM01 INTTM01H TO02 TI02 TI03 Remark Channel 2 INTTM02 Channel 3 TO03 INTTM03 INTTM03H fIL: Low-speed on-chip oscillator clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 181 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-2. Entire Configuration of Timer Array Unit (30-pin products) Timer clock select register 0 (TPS0) PRS031PRS030 PRS021 PRS020 PRS013 PRS012PRS011 PRS010 PRS003 PRS002 PRS001 PRS000 2 2 4 4 Prescaler fCLK fCLK/21, fCLK/22, fCLK/28, fCLK/210, fCLK/24,fCLK/26, fCLK/212,fCLK/214, Peripheral enable register 0 (PER0) Selector TAU0EN fCLK/20 - fCLK/215 Selector Selector Selector CK03 CK02 CK01 CK00 Slave/master controller TO00 INTTM00 (Timer interrupt) TI00 Channel 0 TO01 TI01 Channel 1 Slave/master controller INTTM01 INTTM01H TO02 Timer input select register 0 (TIS0) TI02 Channel 2 INTTM02 TIS2 TIS1 TIS0 TO03 TI03 Channel 3 INTTM03 INTTM03H (TO04) (TI04) (TI05) INTTM04 (TO05) Selector fIL Channel 4 Channel 5 INTTM05 Channel 6 INTTM06 (TO06) (TI06) (TO07) (TI07) Channel 7 Remark INTTM07 Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 182 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-3. Internal Block Diagram of Channel of Timer Array Unit (a) Channel 0, 2, 4, 6 Master channel Slave/master controller Operating clock selection CK00 CK01 Count clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel fMCK Timer controller Output controller Output latch (Pxx) Mode selection Trigger selection Edge detection TI0n fTCLK PMxx Interrupt controller TO00, TO02, (TO04), (TO06) INTTM0n (Timer interrupt) Timer counter register 0n (TCR0n) Timer status register 0n (TSR0n) Timer data register 0n (TDR0n) Slave/master controller Overflow OVF 0n Note CKS0n CCS0n MAS STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 MD0n3 MD0n2 MD0n1 MD0n0 TER0n Channel n Timer mode register 0n (TMR0n) Note n = 0, 2, 4, 6 only. Remarks 1. n = 0, 2, 4, or 6 2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). (b) Channel 1 for 20-pin and 24-pin product Slave channel Slave/master controller Count clock selection CK00 CK01 CK02 CK03 Operating clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel fMCK Trigger selection Edge detection fTCLK Timer input select register 0 (TIS0) Timer controller Mode selection Output controller Interrupt controller PM14 INTTM01 (Timer interrupt) Timer status register 01 (TSR01) Timer data register 01 (TDR01) Slave/master controller Selector TI01 Output latch (P14) Timer counter register 01 (TCR01) TIS1 TIS0 fIL TO01 8-bit timer controller Mode selection CKS01 CCS01 Channel 1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Overflow OVF 01 Interrupt controller INTTM01H (Timer interrupt) SPLIT STS012 STS011 STS010 CIS011 CIS010 MD013 MD012 MD011 MD010 01 Timer mode register 01 (TMR01) 183 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (c) Channel 1 for 30-pin product Slave channel Slave/master controller Count clock selection CK00 CK01 CK02 CK03 Operating clock selection Trigger signal to master channel Clock signal to master channel Interrupt signal to master channel fMCK Mode selection Trigger selection Edge detection TI01 Timer controller fTCLK Output controller Interrupt controller TO01 Output latch (P16) PM16 INTTM01 (Timer interrupt) Timer counter register 01 (TCR01) Timer status register 01 (TSR01) Timer data register 01 (TDR01) Slave/master controller Overflow 8-bit timer controller Mode selection CKS01 CCS01 OVF 01 Interrupt controller INTTM01H (Timer interrupt) SPLIT STS012 STS011 STS010 CIS011 CIS010 MD013 MD012 MD011 MD010 01 Channel 1 Timer mode register 01 (TMR01) (d) Channel 3 Slave channel Slave/master controller fMCK Edge detection fTCLK Trigger selection TI03 Count clock selection CK00 CK01 CK02 CK03 Operating clock selection Trigger signal to master channel Clock signal to master channel Interrupt signal to master channel Timer controller Mode selection Output controller Interrupt controller TO03 Output latch (Pxx) PMxx INTTM03 (Timer interrupt) Timer counter register 03 (TCR03) Timer status register 03 (TSR03) Timer data register 03 (TDR03) Slave/master controller Overflow 8-bit timer controller Mode selection CKS03 CCS03 Channel 3 Remark OVF 03 Interrupt controller INTTM03H (Timer interrupt) SPLIT STS032 STS031 STS030 CIS031 CIS030 MD033 MD032 MD031 MD030 03 Timer mode register 03 (TMR03) Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 184 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (e) Channel 5 for 30-Pin product Slave channel Slave/master controller Operating clock selection CK00 CK01 Timer input select register 0 (TIS0) fIL (TI05) fMCK TIS1 TIS0 Output controller Timer controller Mode selection Trigger selection Edge detection fTCLK TO05 Output latch (P12) Interrupt controller PM12 INTTM05 (Timer interrupt) Timer counter register 05 (TCR05) Timer status register 05 (TSR05) Selector TIS2 Count clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel Timer data register 05 (TDR05) Slave/master controller Overflow OVF 05 CKS05 CCS05 STS052 STS051 STS050 CIS051 CIS050 MD053 MD052 MD051 MD050 Timer mode register 05 (TMR05) Channel 5 (f) Channel 7 for 30-Pin product Master channel Slave/master controller CK01 Count clock selection CK00 Operating clock selection Trigger signal to slave channel Clock signal to slave channel Interrupt signal to slave channel fMCK Trigger selection Edge detection (TI07) fTCLK Timer controller Mode selection Output controller (TO07) Output latch (P10) PM10 Interrupt controller INTTM07 (Timer interrupt) Timer counter register 07 (TCR07) Timer status register 07 (TSR07) Slave/master controller Timer data register 07 (TDR07) Overflow OVF 07 CKS07 CCS07 STS072 STS072 STS071 STS070 CIS071 CIS070 MD073 MD072 MD071 MD070 Channel 7 Remark Timer mode register 07 (TMR07) Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection register (PIOR). (1) Timer/counter register 0n (TCR0n) The TCR0n register is a 16-bit read-only register and is used to count clocks. The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock. Whether the counter is incremented or decremented depends on the operation mode that is selected by the MD0n3 to MD0n0 bits of timer mode register 0n (TMR0n) (refer to 6.3 (3) Timer mode register 0n (TMR0n)). Figure 6-4. Format of Timer/Counter Register 0n (TCR0n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 185 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Address: F0180H, F0181H (TCR00) to F0186H, F0187H (TCR03) After reset: FFFFH F0181H (TCR00) 15 14 13 12 11 R F0180H (TCR00) 10 9 8 7 6 5 4 3 2 1 0 TCR0n Remark n: Channel number (n = 0 to 7) The count value can be read by reading timer counter register 0n (TCR0n). The count value is set to FFFFH in the following cases. * When the reset signal is generated * When the TAU0EN bit of peripheral enable register 0 (PER0) is cleared * When counting of the slave channel has been completed in the PWM output mode * When counting of the slave channel has been completed in the delay count mode * When counting of the master/slave channel has been completed in the one-shot pulse output mode * When counting of the slave channel has been completed in the multiple PWM output mode The count value is cleared to 0000H in the following cases. * When the start trigger is input in the capture mode * When capturing has been completed in the capture mode Caution The count value is not captured to timer data register 0n (TDR0n) even when the TCR0n register is read. The TCR0n register read value differs as follows according to operation mode changes and the operating status. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 186 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Table 6-3. Timer/counter Register 0n (TCR0n) Read Value in Various Operation Modes Operation Mode Count Mode Timer/counter register 0n (TCR0n) Read Value Value if the operation mode was changed after releasing reset Value if the count operation paused (TT0n = 1) Note Value if the operation mode was changed after count operation paused (TT0n = 1) Value when waiting for a start trigger after one count Interval timer mode Count down FFFFH Value if stop Undefined - Capture mode Count up 0000H Value if stop Undefined - Event counter mode Count down FFFFH Value if stop Undefined - One-count mode Count down FFFFH Value if stop Undefined FFFFH Capture & onecount mode Count up 0000H Value if stop Undefined Capture value of TDR0n register + 1 Note This indicates the value read from the TCR0n register when channel n has stopped operating as a timer (TE0n = 0) and has been enabled to operate as a counter (TS0n = 1). The read value is held in the TCR0n register until the count operation starts. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 187 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (2) Timer data register 0n (TDR0n) This is a 16-bit register from which a capture function and a compare function can be selected. The capture or compare function can be switched by selecting an operation mode by using the MD0n3 to MD0n0 bits of timer mode register 0n (TMR0n). The value of the TDR0n register can be changed at any time. This register can be read or written in 16-bit units. In addition, for the TDR01, TDR03 registers, while in the 8-bit timer mode (when the SPLIT bit of timer mode <R> register m1, m3 (TMR01, TMR03) is 1), it is possible to read and write the data in 8-bit units, with TDR01H, TDR03H used as the higher 8 bits, and TDR01L, TDR03L used as the lower 8 bits. Reset signal generation clears this register to 0000H. Figure 6-5. Format of Timer Data Register 0n (TDR0n) (n = 0, 2, 4 to 7) Address: FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02), After reset: 0000H R/W FFF68H, FFF69H (TDR04) to FFF6EH, FFF6FH (TDR07) FFF19H (TDR00) 15 14 13 12 11 FFF18H (TDR00) 10 9 8 7 6 5 4 3 2 1 0 2 1 0 TDR0n Figure 6-6. Format of Timer Data Register 01, 03 (TDR01, TDR03) Address: FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03) After reset: 0000H FFF1BH (TDR01) 15 14 13 12 11 R/W FFF1AH (TDR01) 10 9 8 7 6 5 4 3 TDR0n (i) When timer data register 0n (TDR0n) is used as compare register Counting down is started from the value set to the TDR0n register. When the count value reaches 0000H, an interrupt signal (INTTM0n) is generated. The TDR0n register holds its value until it is rewritten. Caution The TDR0n register does not perform a capture operation even if a capture trigger is input, when it is set to the compare function. (ii) When timer data register 0n (TDR0n) is used as capture register The count value of timer/counter register 0n (TCR0n) is captured to the TDR0n register when the capture trigger is input. A valid edge of the TI0n pin can be selected as the capture trigger. This selection is made by timer mode register 0n (TMR0n). Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 188 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3 Registers Controlling Timer Array Unit Timer array unit is controlled by the following registers. * Peripheral enable register 0 (PER0) * Timer clock select register 0 (TPS0) * Timer mode register 0n (TMR0n) * Timer status register 0n (TSR0n) * Timer channel enable status register 0 (TE0) * Timer channel start register 0 (TS0) * Timer channel stop register 0 (TT0) * Timer input select register 0 (TIS0) * Timer output enable register 0 (TOE0) * Timer output register 0 (TO0) * Timer output level register 0 (TOL0) * Timer output mode register 0 (TOM0) * Noise filter enable register 1 (NFEN1) * Port mode control register 0, 1, 4 (PMC0, PMC1, PMC4) * Port mode register 0, 1, 3, 4 (PM0, PM1, PM3, PM4) * Port register 0, 1, 3, 4 (P0, P1, P3, P4) Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 189 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.1 Peripheral enable register 0 (PER0) This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-7. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN TAU0EN 0 Control of timer array unit input clock Stops supply of input clock. * SFR used by the timer array unit cannot be written. * The timer array unit is in the reset status. 1 Supplies input clock. * SFR used by the timer array unit can be read/written. Cautions 1. When setting the timer array unit, be sure to set the TAU0EN bit to 1 first. If TAU0EN = 0, writing to a control register of timer array unit is ignored, and all read values are default values (except for the timer input select register 0 (TIS0), input switch control register (ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4 (PM0, PM1, PM3, PM4), port registers 0, 1, 3, 4 (P0, P1, P3, P4), and Port mode control register 0, 1, 4 (PMC0, PMC1, PMC4)). 2. Be sure to clear undefined bits to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 190 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.2 Timer clock select register 0 (TPS0) The TPS0 register is a 16-bit register that is used to select four types of operation clocks (CK00 to CK03) that are commonly supplied to each channel from external prescaler. Bit 7 to 4 : CK01 Bit 3 to 0 : CK00 Bit 9, 8 : CK02 (Channel 1, 3) Bit 13 to 12 : CK03 (Channel 1, 3) Rewriting of the TPS0 register during timer operation is possible only in the following cases. If the PRS000 to PRS003 bits can be rewritten (n = 0 to 7): All channels for which CK00 is selected as the operation clock (CKS0n1, CKS0n0 = 0, 0) are stopped (TE0n = 0). If the PRS010 to PRS013 bits can be rewritten (n = 0 to 7): All channels for which CK01 is selected as the operation clock (CKS0n1, CKS0n0 = 0, 1) are stopped (TE0n = 0). If the PRS020 and PRS021 bits can be rewritten (n = 1, 3): All channels for which CK02 is selected as the operation clock (CKS0n1, CKS0n0 = 1, 0) are stopped (TE0n = 0). If the PRS030 and PRS031 bits can be rewritten (n = 1, 3): All channels for which CK03 is selected as the operation clock (CKS0n1, CKS0n0 = 1, 1) are stopped (TE0n = 0). The TPS0 register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 191 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-8. Format of Timer Clock Select register 0 (TPS0) Address: F01B6H, F01B7H After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TPS0 0 0 PRS PRS 0 0 PRS PRS PRS PRS PRS PRS PRS PRS PRS PRS 031 030 021 020 013 012 011 010 003 002 001 000 PRS PRS PRS PRS 0k3 0k2 0k1 0k0 fCLK = fCLK = fCLK = fCLK = fCLK = 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz 0 0 0 fCLK 2 MHz 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz 0 0 0 1 fCLK/2 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz 0 0 1 0 fCLK/22 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz 0 0 1 1 fCLK/23 250 kHz 500 kHz 1 MHz 2 MHz 2.5 MHz 3 MHz 0 4 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz 5 62.5 kHz 125 kHz 250 kHz 500 kHz 625 kHz 6 31.25 kHz 62.5 kHz 125 kHz 250 kHz 312.5 kHz 375 kHz 7 15.62 kHz 31.2 kHz 62.5 kHz 125 kHz 156.2 kHz 187.5 kHz 8 62.5 kHz 78.1 kHz 1 0 1 0 1 0 1 0 0 1 1 0 1 1 fCLK/2 fCLK/2 fCLK/2 fCLK/2 750 kHz 1 0 0 0 fCLK/2 7.81 kHz 15.6 kHz 31.2 kHz 1 0 0 1 fCLK/29 3.91 kHz 7.8 kHz 15.6 kHz 31.2 kHz 39.1 kHz 46.88 kHz 1 0 1 0 fCLK/210 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz 1 0 1 1 fCLK/211 976 Hz 1.95 kHz 3.9 kHz 7.8 kHz 9.76 kHz 11.72 kHz 0 12 488 Hz 0.97 kHz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz 13 244 Hz 485 Hz 0.97 kHz 1.95 kHz 2.44 kHz 2.93 kHz 14 122 Hz 242 Hz 485 Hz 0.97 kHz 1.22 kHz 1.47 kHz 15 61 Hz 121 Hz 242 Hz 485 Hz 610 Hz 732 Hz 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 fCLK/2 fCLK/2 fCLK/2 fCLK/2 021 020 0 0 0 1 0 1 fCLK = 2 MHz fCLK = 4 MHz fCLK = 8 MHz fCLK = 16 MHz fCLK = 20 MHz fCLK = 24 MHz fCLK/2 1 1 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz fCLK/2 2 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz fCLK/2 4 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz fCLK/2 6 31.25 kHz 62.5 kHz 125 kHz 250 kHz 312.5 kHz 375 kHz Selection of operation clock (CK03) Note PRS PRS 031 030 0 0 0 1 1 0 1 1 93.75 kHz Selection of operation clock (CK02) Note PRS PRS Note fCLK = 2 MHz 0 0 <R> Selection of operation clock (CK0k) Note(k = 0, 1) fCLK = 2 MHz fCLK = 4 MHz fCLK = 8 MHz fCLK = 16 MHz fCLK = 20 MHz fCLK = 24 MHz fCLK/2 8 7.81 kHz 15.6 kHz 31.2 kHz 62.4 kHz 78.1 kHz 93.75 kHz fCLK/2 10 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz fCLK/2 12 488 Hz 976 Hz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz fCLK/2 14 122 Hz 244 Hz 488 Hz 976 Hz 1.22 kHz 1.47 kHz When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), stop timer array unit (TT0 = 00FFH). Cautions 1. 2. Be sure to clear bits 15, 14, 11, 10 to "0". If fCLK (undivided) is selected as the operation clock (CKmk) and TDRnm is set to 0000H (n = 0 or 1, m = 0 to 7), interrupt requests output from timer array units are not detected. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 192 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. fCLK: CPU/peripheral hardware clock frequency 2. The above selected clock , but a signal which becomes high level for one period of fCLK from its rising edge (m = 2 to 15). For details, see 6.5.1 Count clock (fTCLK). By using channels 1 and 3 in the 8-bit timer mode and specifying CK02 or CK03 as the operation clock, the interval times shown in Table 6-4 can be achieved by using the interval timer function. Table 6-4. Interval Times Available for Operation Clock CKS02 or CKS03 Note Interval time (fCLK = 20 MHz) Clock CK02 Note 100 s 1 ms 10 ms - - - fCLK/2 2 - - - fCLK/2 4 - - fCLK/2 6 - - fCLK/2 8 - - fCLK/2 10 - - - fCLK/2 12 - - - fCLK/2 14 - - - - fCLK/2 CK03 10 s The margin is within 4 %. Remarks 1. fCLK: CPU/peripheral hardware clock frequency n 2. For details of asignal of fCLK/2 selected with the TPSm register, see 6.5.1 Count clock (fTCLK). 6.3.3 Timer mode register 0n (TMR0n) The TMR0n register sets an operation mode of channel n. This register is used to select the operation clock (fMCK), select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event counter, one-count, or capture and one-count). Rewriting the TMR0n register is prohibited when the register is in operation (when TE0n = 1). However, bits 7 and 6 (CIS0n1, CIS0n0) can be rewritten even while the register is operating with some functions (when TE0n = 1) (for details, see 6.7 Independent Channel Operation Function of Timer Array Unit and 6.8 Simultaneous Channel Operation Function of Timer Array Unit). The TMR0n register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Caution The bits mounted depend on the channels in the bit 11 of TMR0n register. TMR02, TMR04, TMR06: MASTER0n bit (n = 2, 4, 6) TMR01, TMR03: SPLIT0n bit (n = 1, 3) TMR00, TMR05, TMR07: Fixed to 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 193 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (1/4) Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS MAST STS STS STS CIS CIS 0 0 (n = 2, 4, 6) 0n1 0n0 0n ER0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) 0n1 0n0 0n 0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 0n2 0n1 0n0 0n1 0n0 13 CCS Note TMR0n CKS CKS (n = 0, 5, 7) 0n1 0n0 CKS CKS 0n1 0n0 0 0 Operation clock CK00 set by timer clock select register 0 (TPS0) 0 1 Operation clock CK02 set by timer clock select register 0 (TPS0) 1 0 Operation clock CK01 set by timer clock select register 0 (TPS0) 1 1 Operation clock CK03 set by timer clock select register 0 (TPS0) 0 0n 0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 Selection of operation clock (fMCK) of channel n Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated depending on the setting of the CCS0n bit. The operation clocks CK02 and CK03 can only be selected for channels 1 and 3. CCS Selection of count clock (fTCLK) of channel n 0n 0 Operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits 1 Valid edge of input signal input from the TI0n pin In channel 1 for 20-, 24-pin product and channel 5 for 30-pin product, Valid edge of input signal selected by TIS0 Count clock (fTCLK) is used for the timer/counter, output controller, and interrupt controller. Note Bit 11 is fixed at 0 of read only, write is ignored. Cautions 1. Be sure to clear bits 13, 5, and 4 to "0". 2. The timer array unit must be stopped (TT0 = 00FFH) if the clock selected for fCLK is changed (by changing the value of the system clock control register (CKC)), even if the operating clock specified by using the CKS0n0 and CKS0n1 bits (fMCK) or the valid edge of the signal input from the TI0n pin is selected as the count clock (fTCLK). Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 194 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (2/4) Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS MAST STS STS STS CIS CIS 0 0 (n =2, 4, 6) 0n1 0n0 0n ER0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) 0n1 0n0 0n 0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 0n2 0n1 0n0 0n1 0n0 TMR0n CKS CKS (n = 0, 5, 7) 0n1 0n0 13 0 CCS 0 Note 0n 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 (Bit 11 of TMR0n (n = 2, 4, 6)) MAS Selection between using channel n independently or TER simultaneously with another channel (as a slave or master) 0n Operates in independent channel operation function or as slave channel in simultaneous channel operation 0 function. 1 Operates as master channel in simultaneous channel operation function. Only the 2, 4, 6 channel can be set as a master channel (MASTER0n = 1). Be sure to use channel 0, 5, 7 are fixed to 0 (Regardless of the bit setting, channel 0 operates as master, because it is the highest channel). Clear the MASTER0n bit to 0 for a channel that is used with the independent channel operation function. (Bit 11 of TMR0n (n = 1, 3)) SPLI Selection of 8 or 16-bit timer operation for channels 1 and 3 T0n 0 Operates as 16-bit timer. (Operates in independent channel operation function or as slave channel in simultaneous channel operation function.) 1 Operates as 8-bit timer. STS STS STS 0n2 0n1 0n0 0 0 0 Only software trigger start is valid (other trigger sources are unselected). 0 0 1 Valid edge of the TI0n pin input is used as both the start trigger and capture trigger. 0 1 0 Both the edges of the TI0n pin input are used as a start trigger and a capture trigger. 1 0 0 Interrupt signal of the master channel is used (when the channel is used as a slave channel Setting of start trigger or capture trigger of channel n with the simultaneous channel operation function). Other than above Note Setting prohibited Bit 11 is fixed at 0 of read only, write is ignored. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 195 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (3/4) Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS MAST STS STS STS CIS CIS 0 0 (n = 2, 4, 6) 0n1 0n0 0n ER0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) 0n1 0n0 0n 0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 0n2 0n1 0n0 0n1 0n0 13 CCS Note TMR0n CKS CKS (n = 0, 5, 7) 0n1 0n0 CIS CIS 0n1 0n0 0 0 Falling edge 0 1 Rising edge 1 0 Both edges (when low-level width is measured) 0 0n 0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 Selection of TI0n pin input valid edge Start trigger: Falling edge, Capture trigger: Rising edge 1 1 Both edges (when high-level width is measured) Start trigger: Rising edge, Capture trigger: Falling edge If both the edges are specified when the value of the STS0n2 to STS0n0 bits is other than 010B, set the CIS0n1 to CIS0n0 bits to 10B. Note Bit 11 is fixed at 0 of read only, write is ignored. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 196 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (4/4) Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS MAST STS STS STS CIS CIS 0 0 (n = 2, 4, 6) 0n1 0n0 0n ER0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TMR0n CKS CKS 0 CCS SPLIT STS STS STS CIS CIS 0 0 (n = 1, 3) 0n1 0n0 0n 0n 0n2 0n1 0n0 0n1 0n0 Symbol 15 14 12 11 10 9 8 7 6 5 4 STS STS STS CIS CIS 0 0 0n2 0n1 0n0 0n1 0n0 TMR0n CKS CKS (n = 0, 5, 7) 0n1 0n0 MD MD 13 CCS 0 0 Note 0n MD Setting of operation mode of channel n 0n3 0n2 0n1 0 0 0 Corresponding function Interval timer / Square wave output / Interval timer mode 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 3 2 1 0 MD MD MD MD 0n3 0n2 0n1 0n0 Count operation of TCR Down count Divider function / PWM output (master) 0 1 0 Capture mode Input pulse interval measurement Up count 0 1 1 Event counter mode External event counter Down count 1 0 0 One-count mode Delay counter / One-shot pulse Down count output / PWM output (slave) 1 1 0 Other than above Capture & one-count Measurement of high-/low-level mode width of input signal Up count Setting prohibited The operation of MD0n0 bit changes depending on the operation of each mode (refer to the table bellow) Operation mode MD (Value set by the MD0n3 to MD0n1 bits 0n0 Setting of starting counting and interrupt (see table above)) * Interval timer mode 0 * Capture mode 1 (0, 1, 0) 0 (0, 1, 1) Timer interrupt is not generated when counting is started (timer output does not change, either). * One-count mode Note 2 0 Start trigger is invalid during counting operation. At that time, interrupt is not generated, either. (1, 0, 0) 1 <R> <R> Timer interrupt is generated when counting is started (timer output also changes). * Event counter mode <R> Timer interrupt is not generated when counting is started (timer output does not change, either). (0, 0, 0) Start trigger is valid during counting operation Note 3 . At that time, interrupt is also generated. * Capture & one-count mode (1, 1, 0) 0 Timer interrupt is not generated when counting is started (timer output does not change, either). Start trigger is invalid during counting operation. At that time interrupt is not generated, either. Other than above R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting prohibited 197 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Notes 1. Bit 11 is fixed at 0 of read only, write is ignored. 2. In one-count mode, interrupt output (INTTM0n) when starting a count operation and TO0n output are not controlled. 3. If the start trigger (TS0n = 1) is issued during operation, the counter is initialaized, and recounting is started (interrupt request is not generated). n: Channel number (n = 0 to 7) Remark 6.3.4 Timer status register 0n (TSR0n) The TSR0n register indicates the overflow status of the counter of channel n. The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode (MD0n3 to MD0n1 = 110B). It will not be set in any other mode. See Table 6-4 for the operation of the OVF bit in each operation mode and set/clear conditions. The TSR0n register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the TSR0n register can be set with an 8-bit memory manipulation instruction with TSR0nL. Reset signal generation clears this register to 0000H. Figure 6-10. Format of Timer Status Register 0n (TSR0n) Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07) After reset: 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TSR0n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF OVF Counter overflow status of channel n 0 Overflow does not occur. 1 Overflow occurs. When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow. Remark n: Channel number (n = 0 to 7) Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode Timer operation mode OVF bit Set/clear conditions * Capture mode clear When no overflow has occurred upon capturing * Capture & one-count mode set When an overflow has occurred upon capturing * Interval timer mode clear * Event counter mode * One-count mode Remark set - (Use prohibited) The OVF bit does not change immediately after the counter has overflowed, but changes upon the subsequent capture. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 198 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.5 Timer channel enable status register 0 (TE0) The TE0 register is used to enable or stop the timer operation of each channel. Each bit of the TE0 register corresponds to each bit of the timer channel start register 0 (TS0) and the timer channel stop register 0 (TT0). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a bit of the TT0 register is set to 1, the corresponding bit of this register is cleared to 0. The TE0 register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the TE0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TE0L. Reset signal generation clears this register to 0000H. Figure 6-11. Format of Timer Channel Enable Status register 0 (TE0) Address: F01B0H, F01B1H After reset: 0000H R 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TE0 0 0 0 0 TEH03 0 TEH01 0 0 0 0 0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TE0 0 0 0 0 TEH03 0 TEH01 0 3 2 1 0 TE03 TE02 TE01 TE00 30-pin products 3 2 1 0 TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00 TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit 03 timer mode 0 Operation is stopped. 1 Operation is enabled. TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit 01 timer mode 0 Operation is stopped. 1 Operation is enabled. TE0n Indication of operation enable/stop status of channel n 0 Operation is stopped. 1 Operation is enabled. This bit displays whether operation of the lower 8-bit timer for TE01, TE03 is enabled or stopped when channel 1, 3 is in the 8-bit timer mode. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 199 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.6 Timer channel start register 0 (TS0) The TS0 register is a trigger register that is used to initialize timer/counter register 0n (TCR0n) and start the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is set to 1. The TS0n, TSH01, TSH03 bits are immediately cleared when operation is enabled (TE0n, TEH01, TEH03 = 1), because they are trigger bits. The TS0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TS0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TS0L. Reset signal generation clears this register to 0000H. Figure 6-12. Format of Timer Channel Start register 0 (TS0) Address: F01B2H, F01B3H After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TS0 0 0 0 0 TSH03 0 TSH01 0 0 0 0 0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TS0 0 0 0 0 TSH03 0 TSH01 0 3 2 1 0 TS03 TS02 TS01 TS00 30-pin products 3 2 1 0 TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00 TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode 03 0 No trigger operation 1 The TEH03 bit is set to 1 and the count operation becomes enabled. The TCR03 register count operation start in the interval timer mode in the count operation enabled state (see Table 6-6). TSH Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode 01 0 No trigger operation 1 The TEH01 bit is set to 1 and the count operation becomes enabled. The TCR01 register count operation start in the interval timer mode in the count operation enabled state (see Table 6-6). TS0n Operation enable (start) trigger of channel n 0 No trigger operation 1 The TE0n bit is set to 1 and the count operation becomes enabled. The TCR0n register count operation start in the count operation enabled state varies depending on each operation mode (see Table 6-6). This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TS01 and TS03 when channel 1 or 3 is in the 8-bit timer mode. Cautions 1. Be sure to clear undifined bits to "0". 2. When switching from a function that does not use TI0n pin input to one that does, the following wait period is required from when timer mode register 0n (TMR0n) is set until the TS0n (TSH01, TSH03) bit is set to 1. When the TI0n pin noise filter is enabled (TNFEN = 1): Four cycles of the operation clock (fMCK) When the TI0n pin noise filter is disabled (TNFEN = 0): Two cycles of the operation clock (fMCK) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 200 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Remarks 1. When the TS0 register is read, 0 is always read. 2. n: Channel number (n = 0 to 7) 6.3.7 Timer channel stop register 0 (TT0) The TT0 register is a trigger register that is used to stop the counting operation of each channel. When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is cleared to 0. The TT0n, TTH01, TTH03 bits are immediately cleared when operation is stopped (TE0n, TTH01, TTH03 = 0), because they are trigger bits. The TT0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TT0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TT0L. Reset signal generation clears this register to 0000H. Figure 6-13. Format of Timer Channel Stop register 0 (TT0) Address: F01B4H, F01B5H After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TT0 0 0 0 0 TTH03 0 TTH01 0 0 0 0 0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TT0 0 0 0 0 TTH03 0 TTH01 0 3 2 1 0 TT03 TT02 TT01 TT00 30-pin products TTH 3 2 1 0 TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00 Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode 03 0 No trigger operation 1 TEH03 is cleared to 0. Operation is stopped (stop trigger is generated). TTH Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode 01 0 No trigger operation 1 TEH01 is cleared to 0. Operation is stopped (stop trigger is generated). TT0n Operation stop trigger of channel n 0 No trigger operation 1 TE0n is cleared to 0. Operation is stopped (stop trigger is generated). This bit is the trigger to stop operation of the lower 8-bit timer for TT01 and TT03 when channel 1 or 3 is in the 8-bit timer mode. Caution Be sure to clear undifined bits to "0". Remarks 1. When the TT0 register is read, 0 is always read. 2. n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 201 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.8 Timer input select register 0 (TIS0) The TIS0 register is used to select the channel 1 for 20- or 24-pin product, channel 5 for 30-pin product timer input. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-14. Format of Timer Input Select register 0 (TIS0) Address: F0074H After reset: 00H R/W 20- and 24-pin products Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 0 TIS01 TIS00 TIS01 TIS00 x 0 Input signal of timer input pin (TI01) 0 1 Low-speed on-chip oscillator clock (fIL) 1 1 Setting prohibited Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 TIS2 TIS01 TIS00 TIS2 TIS01 TIS00 0 x x Input signal of timer input pin (TI05) 1 0 0 Low-speed on-chip oscillator clock (fIL) Selection of timer input used with channel 1 30-pin products Other than above Selection of timer input used with channel 5 Setting prohibited x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 202 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.9 Timer output enable register 0 (TOE0) The TOE0 register is used to enable or disable timer output of each channel. Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function through the count operation is output from the timer output pin (TO0n). The TOE0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOE0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TOE0L. Reset signal generation clears this register to 0000H. Figure 6-15. Format of Timer Output Enable register 0 (TOE0) Address: F01BAH, F01BBH After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOE0 0 0 0 0 0 0 0 0 0 0 0 0 TOE TOE TOE TOE 03 02 01 00 30-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOE0 0 0 0 0 0 0 0 0 TOE TOE TOE TOE TOE TOE TOE TOE 07 06 05 04 03 02 01 00 TOE Timer output enable/disable of channel n 0n 0 Diseble output of timer. Without reflecting on TOmn bit timer operation, to fixed the output. Writing to the TOmn bit is enabled. 1 Enable output of timer. Reflected in the TOmn bit timer operation, to generate the output waveform. Writing to the TOmn bit is disabled (writing is ignored). Caution Be sure to clear undifined bits to "0". Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 203 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.10 Timer output register 0 (TO0) The TO0 register is a buffer register of timer output of each channel. The value of each bit in this register is output from the timer output pin (TO0n) of each channel. The TO0n bit oh this register can be rewritten by software only when timer output is disabled (TOE0n = 0). When timer output is enabled (TOE0n = 1), rewriting this register by software is ignored, and the value is changed only by the timer operation. To use the TO0n alternate pin as a port function pin, set the corresponding TO0n bit to 0. The TO0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TO0 register can be set with an 8-bit memory manipulation instruction with TO0L. Reset signal generation clears this register to 0000H. Figure 6-16. Format of Timer Output register 0 (TO0) Address: F01B8H, F01B9H After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TO0 0 0 0 0 0 0 0 0 0 0 0 0 Symbol 15 14 13 12 11 10 9 8 7 6 5 4 TO0 0 0 0 0 0 0 0 0 3 2 1 0 TO03 TO02 TO01 TO00 30-pin products TO0n 3 2 1 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 Timer output of channel n 0 Timer output value is "0". 1 Timer output value is "1". Caution Be sure to clear undefined bits to 0. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 204 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.11 Timer output level register 0 (TOL0) The TOL0 register is a register that controls the timer output level of each channel. The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1). In the master channel output mode (TOM0n = 0), this register setting is invalid. The TOL0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOL0 register can be set with an 8-bit memory manipulation instruction with TOL0L. Reset signal generation clears this register to 0000H. Figure 6-17. Format of Timer Output Level register 0 (TOL0) Address: F01BCH, F01BDH After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOL0 0 0 0 0 0 0 0 0 0 0 0 0 TOL TOL TOL 0 03 02 01 30-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOL0 0 0 0 0 0 0 0 0 TOL TOL TOL TOL TOL TOL TOL 0 07 06 05 04 03 02 01 TOL Control of timer output level of channel n 0n 0 Positive logic output (active-high) 1 Negative logic output (active-low) Caution Be sure to clear undefined bits to 0. Remarks 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when the timer output signal changes next, instead of immediately after the register value is rewritten. 2. n: Channel number (n = 1 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 205 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.12 Timer output mode register 0 (TOM0) The TOM0 register is used to control the timer output mode of each channel. When a channel is used for the independent channel operation function, set the corresponding bit of the channel to be used to 0. When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave channel to 1. The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset while the timer output is enabled (TOE0n = 1). The TOM0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the TOM0 register can be set with an 8-bit memory manipulation instruction with TOM0L. Reset signal generation clears this register to 0000H. Figure 6-18. Format of Timer Output Mode register 0 (TOM0) Address: F01BEH, F01BFH After reset: 0000H R/W 20- and 24-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOM0 0 0 0 0 0 0 0 0 0 0 0 0 TOM TOM TOM 0 03 02 01 30-pin products Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TOM0 0 0 0 0 0 0 0 0 TOM TOM TOM TOM TOM TOM TOM 0 07 06 05 04 03 02 01 TOM Control of timer output mode of channel n 0n 0 Master channel output mode (to produce toggle output by timer interrupt request signal (INTTM0n)) 1 Slave channel output mode (output is set by the timer interrupt request signal (INTTM0n) of the master channel, and reset by the timer interrupt request signal (INTTM0p) of the slave channel) Caution Be sure to clear undefined bits to 0. Remark n: Channel number n = 1 to 7 (n = 0, 2, 4, or 6 for master channel) p: Slave channel number n<p7 (For details of the relation between the master channel and slave channel, refer to 6.4.1 Basic Rules of Simultaneous Channel Operation Function.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 206 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.13 Noise filter enable register 1 (NFEN1) The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel. Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal. When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the CPU/peripheral hardware clock (fMCK). When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (fMCK). For details, see 6.5.1 (2) When valid edge of input signal input from the TI0n pin is selected (CCS0n = 1) and 6.5.2 Start timing of counter. The NFEN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 6-20. Format of Noise Filter Enable Register 1 (NFEN1) Address: F0071H After reset: 00H R/W 20- and 24-pin products Symbol 7 6 5 4 3 2 1 0 NFEN1 0 0 0 0 TNFEN03 TNFEN02 TNFEN01 TNFEN00 Symbol 7 6 5 4 3 2 1 0 NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00 30-pin products TNFEN0n Enable/disable using noise filter of TI0n pin input signal 0 Noise filter OFF 1 Noise filter ON R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 207 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.3.14 Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4) These registers set input/output of ports 0, 1, 3, or 4 in 1-bit units. When using the ports that shares the pin with the timer output (such as TI00/TO00/P13) for timer output, set the port mode register (PMxx) bit, port register (Pxx) bit and port mode control register (PMCxx) bit corresponding to each port to 0. Example: When using P13/TI00/TO00 for timer output fot 20-, 24-pin product Set the PMC13 bit of port mode control register 1 to 0. Set the PM00 bit of port mode register 1 to 0. Set the P00 bit of port register 1 to 0. When using the ports (such as TI00/TO00/P13) to be shared with the timer output pin for timer input, set the port mode register (PMxx) bit corresponding to each port to 1. Also set the port mode control register (PMCxx) bit corresponding to each port to 0. At this time, the port register (Pxx) bit may be 0 or 1. Example: When using P13/TO00/TI00 for timer input fot 20-, 24-pin product Set the PMC13 bit of port mode control register 1 to 0. Set the PM00 bit of port mode register 1 to 1. Set the P00 bit of port register 1 to 0 or 1. The PM0, PM1, PM3, and PM4 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. In the 20- and 24-pin products, TI00, TO00 (P13, P14, P41, P42) and the 30-pin products TI00 (P00) Remark and TO00 (P01) pins alternate analog input pins. When using the timer I/O function, the corresponding bit of the PMCx register for switching digital I/O or analog input is sure to set to "0". Figure 6-20. Format of Port Mode Registers 0, 1, 3, 4 (PM0, PM1, PM3, or PM4) 20- and 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W PM0n P0n pin I/O mode selection (m = 0, 1, 3, 4 ; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 208 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.4 Basic Rules of Timer Array Unit 6.4.1 Basic Rules of Simultaneous Channel Operation Function When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply. (1) Only an even channel (channel 0, 2, 4, 6, 8) can be set as a master channel. (2) Any channel, except channel 0, can be set as a slave channel. (3) The slave channel must be lower than the master channel. Example: If channel 2 is set as a master channel, channel 3 or those that follow (Channel 3 to 7) can be set as a slave channel. (4) Two or more slave channels can be set for one master channel. (5) When two or more master channels are to be used, slave channels with a master channel between them may not be set. Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0. (6) The operating clock for a slave channel in combination with a master channel must be the same as that of the master channel. The CKS0n0 and CKS0n1 bits (bits 15 and 14 of timer mode register 0n (TMR0n)) of the slave channel that operate in combination with the master channel must be the same value as that of the master channel. (7) A master channel can transmit INTTM0n (interrupt), start software trigger, and count clock to the lower channels. (8) A slave channel can use INTTM0n (interrupt), a start software trigger, or the count clock of the master channel as a source clock, but cannot transmit its own INTTM0n (interrupt), start software trigger, or count clock to channels with lower channel numbers. (9) A master channel cannot use INTTM0n (interrupt), a start software trigger, or the count clock from the other higher master channel as a source clock. (10) To simultaneously start channels that operate in combination, the channel start trigger bit (TS0n) of the channels in combination must be set at the same time. (11) During the counting operation, a TS0n bit of a master channel or TS0n bits of all channels which are operating simultaneously can be set. It cannot be applied to TS0n bits of slave channels alone. (12) To stop the channels in combination simultaneously, the channel stop trigger bit (TT0n) of the channels in combination must be set at the same time. (13) CK02/CK03 cannot be selected while channels are operating simultaneously, because the operating clocks of master channels and slave channels have to be synchronized. (14) Timer mode register 0n (TMR0n) has no master bit (it is fixed as "0"). However, as channel 0 is the highest channel, it can be used as a master channel during simultaneous operation. Remark n: Channel number (n = 0 to 7) The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave channels forming one simultaneous channel operation function). If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the channel groups. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 209 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Example TAU0 CK00 Channel 0: Master Channel group 1 (Simultaneous channel operation function) Channel 1: Slave Channel 2: Slave Channel group 2 (Simultaneous channel operation function) Channel 3: Independent channel operation function CK01 CK00 Channel 4: Master Channel 5: Independent channel operation function Channel 6: Slave Channel 7: Independent channel operation function R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 * Operation clocks can be different between channel groups 1 and 2. * The channel that operates with the independent channel operation function can exist between channel groups 1 and 2. * Between the master and slave channel group 2, the channel that operates with the independent channel operation function can exist. In addition, the settings of operation clocks can be performed individually. 210 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.4.2 Basic rules of 8-bit timer operation function (Only Channels 1 and 3) The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8bit timer channels. This function can only be used for channels 1 and 3, and there are several rules for using it. The basic rules for this function are as follows: (1) The 8-bit timer operation function applies only to channels 1 and 3. (2) When using 8-bit timers, set the SPLIT bit of timer mode register 0n (TMR0n) to 1. (3) The higher 8 bits can be operated as the interval timer function. (4) At the start of operation, the higher 8 bits output INTTM01H/INTTM03H (an interrupt) (which is the same operation performed when MD0n0 is set to 1). (5) The operation clock of the higher 8 bits is selected according to the CKS0n1 and CKS0n0 bits of the lower-bit TMR0n register. (6) For the higher 8 bits, the TSH01/TSH03 bit is manipulated to start channel operation and the TTH01/TTH03 bit is manipulated to stop channel operation. The channel status can be checked using the TEH01/TEH03 bit. (7) The lower 8 bits operate according to the TMR0n register settings. The following three functions support operation of the lower 8 bits: * Interval timer function * External event counter function * Delay count function (8) For the lower 8 bits, the TS01/TS03 bit is manipulated to start channel operation and the TT01/TT03 bit is manipulated to stop channel operation. The channel status can be checked using the TE01/TE03 bit. (9) During 16-bit operation, manipulating the TSH01/TSH03/TTH01/TTH03 bits is invalid. The TS01/TS03/TT01/TT03 bits are manipulated to operate channels 1 and 3. The TEH03 and TEH01 bits are not changed. (10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM) cannot be used. Remark n: Channel number (n = 1, 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 211 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.5 Operation of Counter 6.5.1 Count clock (fTCLK) The count clock (fTCLK) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n (TMR0n). . * Operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits * Valid edge of input signal input from the TI0n pin Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK) are shown below. (1) When operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits is selected (CCS0n = 0) 15 The count clock (fTCLK) is between fCLK to fCLK /2 by setting of timer clock select register 0 (TPS0). When a divided fCLK is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for one period of fCLK from its rising edge. When a fCLK is selected, fixed to high level Counting of timer count register 0n (TCR0n) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at rising edge of the count clock", as a matter of convenience. Figure 6-21. Timing of fCLK and count clock (fTCLK) (When CCS0n = 0) fCLK fCLK/2 fCLK/4 fTCLK ( = fMCK = CK0n) fCLK/8 fCLK/16 Remarks 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter 2. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 fCLK: CPU/peripheral hardware clock 212 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (2) When valid edge of input signal via the TI0n pin is selected (CCS0n = 1) The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TI0n pin and synchronizes next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TI0n pin (when a noise filter is used, the delay becomes 3 to 4 clock). Counting of timer count register 0n (TCR0n) delayed by one period of fCLK from rising edge of the count clock, because of synchronization with fCLK. But, this is described as "counting at valid edge of input signal via the TI0n pin", as a matter of convenience. Figure 6-22. Timing of fCLK and count clock (fTCLK) (When CCS0n = 1, noise filter unused) fCLK fMCK TS0n (Write) <1> TE0n TI0n input <2> Sampling wave Edge detection <3> Edge detection Rising edge detection signal (fTCLK) <1> Setting TS0n bit to 1 enables the timer to be started and to become wait state for valid edge of input signal via the TI0n pin. <2> The rise of input signal via the TI0n pin is sampled by fMCK. <3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output. Remarks 1. : Rising edge of the count clock : Synchronization, increment/decrement of counter 2. fCLK: CPU/peripheral hardware clock fMCK: Operation clock of channel n 3. The waveform of the input signal via TI0n pin of the input pulse interval measurement, the measurement of high/low width of input signal, and the delay counter, the one-shot pulse output are the same as that shown in Figure 6-22. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 213 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.5.2 Start timing of counter Timer count register 0n (TCR0n) becomes enabled to operation by setting of TS0n bit of timer channel start register 0 (TS0). Operations from count operation enabled state to timer count Register 0n (TCR0n) count start is shown in Table 6-6. Table 6-6. Operations from Count Operation Enabled State to Timer count Register 0n (TCR0n) Count Start Timer operation mode * Interval timer mode Operation when TS0n = 1 is set No operation is carried out from start trigger detection (TS0n = 1) until count clock generation. The first count clock loads the value of the TDR0n register to the TCR0n register and the subsequent count clock performs count down operation (see 6.5.3 (1) Interval timer mode operation). * Event counter mode Writing 1 to the TS0n bit loads the value of the TDR0n register to the TCR0n register. Detection TI0n input edge, the subsequent count clock performs count down operation. (see 6.5.3 (2) Event counter mode operation). * Capture mode No operation is carried out from start trigger (TS0n = 1) detection until count clock generation. The first count clock loads 0000H to the TCR0n register and the subsequent count clock performs count up operation (see 6.5.3 (3) Capture mode operation (input pulse interval measurement)). * One-count mode The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the timer is stopped (TE0n = 0). No operation is carried out from start trigger detection until count clock generation. The first count clock loads the value of the TDR0n register to the TCR0n register and the subsequent count clock performs count down operation (see 6.5.3 (4) One-count mode operation). * Capture & one-count mode The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the timer is stopped (TE0n = 0). No operation is carried out from start trigger detection until count clock generation. The first count clock loads 0000H to the TCR0n register and the subsequent count clock performs count up operation (see 6.5.3 (5) Capture & one-count mode operation (high-level width is measured)). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 214 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.5.3 Counter Operation Here, the counter operation in each mode is explained. (1) Interval timer mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the initial value until count clock generation. <2> A start trigger is generated at the first count clock after operation is enabled. <3> When the MD0n0 bit is set to 1, INTTM0n is generated by the start trigger. <4> By the first count clock after the operation enable, the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and counting starts in the interval timer mode. <5> When the TCR0n register counts down and its count value is 0000H, INTTM0n is generatedIn the next count clock (fMCK) and the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and counting keeps on. Figure 6-23. Operation Timing (In Interval Timer Mode) fMCK (fTCLK) TS0n (Write) <1> TE0n <2> Start trigger detection signal TCR0n TDR0n Initial value <3> m 0001 m-1 <4> 0000 m m <5> INTTM0n When MD0n0 = 1 setting Caution In the first cycle operation of count clock after writing the TS0n bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MD0n0 = 1. Remark fMCK, the start trigger detection signal, and INTTM0n become active between one clock in synchronization with fCLK. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 215 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (2) Event counter mode operation <1> Timer count register 0n (TCR0n) holds its initial value while operation is stopped (TE0n = 0). <2> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <3> As soon as 1 has been written to the TS0n bit and 1 has been set to the TE0n bit, the value of timer data register 0n (TDR0n) is loaded to the TCR0n register to start counting. <4> After that, the TCR0n register value is counted down according to the count clock of the valid edge of the TI0n input. Figure 6-24. Operation Timing (In Event Counter Mode) fMCK TS0n (Write) <1> TE0n <2> TI0n input Edge detection Edge detection Count clock Start trigger detection signal <4> <1> TCR0n <3> Initial value m-1 m m-2 <3> TDR0n m Remark The timing is shown in Figure 6-24 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n input and that of the count clock (fMCK). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 216 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (3) Capture mode operation (input pulse interval measurement) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until count clock generation. <3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is loaded to the TCR0n register and counting starts in the capture mode. (When the MD0n0 bit is set to 1, INTTM0n is generated by the start trigger.) <4> On detection of the valid edge of the TI0n input, the value of the TCR0n register is captured to timer data register 0n (TDR0n) and INTTM0n is generated. However, this capture value is nomeaning. The TCR0n register keeps on counting from 0000H. <5> On next detection of the valid edge of the TI0n input, the value of the TCR0n register is captured to timer data register 0n (TDR0n) and INTTM0n is generated. Figure 6-25. Operation Timing (In Capture Mode: Input Pulse Interval Measurement) fMCK (fTCLK) TS0n(Write) <1> TE0n Note <3> TI0n input <4> Start trigger detection signal <2> TCR0n Edge detection Edge detection Rising edge Initial value TDR0n <5> <3> 0000 0001 0000 0001 Note m-1 m 0000 m INTTM0n Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a trigger is detected, even if no edge is detected. Therefore, the first captured value (<4>) does not determine a pulse interval (in the above figure, 0001 just indicates two clock cycles but does not determine the pulse interval) and so the user can ignore it. Caution In the first cycle operation of count clock after writing the TS0n bit, an error at a maximum of one clock is generated since count start delays until count clock has been generated. When the information on count start timing is necessary, an interrupt can be generated at count start by setting MD0n0 = 1. Remark The timing is shown in Figure 6-25 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n input and that of the count clock (fMCK). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 217 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (4) One-count mode operation <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation. <3> Rising edge of the TI0n input is detected. <4> On start trigger detection, the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and count starts. <5> When the TCR0n register counts down and its count value is 0000H, INTTM0n is generated and the value of the TCR0n register becomes FFFFH and counting stops . Figure 6-26. Operation Timing (In One-count Mode) fMCK (fTCLK) TS0n (Write) <1> TE0n TI0n input <3> Edge detection Rising edge <4> Start trigger detection signal <5> <2> TCR0n Initial value m 1 0 FFFF INTTM0n Start trigger input wait status Remark The timing is shown in Figure 6-26 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n input and that of the count clock (fMCK). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 218 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (5) Capture & one-count mode operation (high-level width is measured) <1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit of timer channel start register 0 (TS0). <2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation. <3> Rising edge of the TI0n input is detected. <4> On start trigger detection, the value of 0000H is loaded to the TCR0n register and count starts. <5> On detection of the falling edge of the TI0n input, the value of the TCR0n register is captured to timer data register 0n (TDR0n) and INTTM0n is generated. Figure 6-27. Operation Timing (In Capture & One-count Mode: High-level Width Measurement) fMCK (fTCLK) TS0n(Write) <1> TE0n TI0n input <3> Edge detection Edge detection Rising edge <4> Falling edge <5> Start trigger detection signal <2> TCR0n Initial value TDR0n 0000 0000 m-1 m m+1 m INTTM0n Remark The timing is shown in Figure 6-28 indicates while the noise filter is not used. By making the noise filter on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n input and that of the count clock (fMCK). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 219 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.6 Channel Output (TO0n pin) Control 6.6.1 TO0n pin output circuit configuration Figure 6-28. Output Circuit Configuration <5> TO0n register Controller Interrupt signal of the master channel (INTTM0n) Interrupt signal of the slave channel (INTTM0p) Set TO0n pin Reset/toggle <1> <2> <3> <4> TOL0n TOM0n Internal bus TOE0n TO0n write signal The following describes the TO0n pin output circuit. <1> When TOM0n = 0 (master channel output mode), the set value of timer output level register 0 (TOL0) is ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register 0 (TO0). <2> When TOM0n = 1 (slave channel output mode), both INTTM0n (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TO0 register. At this time, the TOL0 register becomes valid and the signals are controlled as follows: When TOL0n = 0: Positive logic output (INTTM0n set, INTTM0p reset) When TOL0n = 1: Negative logic output (INTTM0n reset, INTTM0p set) When INTTM0n and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal) takes priority, and INTTM0n (set signal) is masked. <3> While timer output is enabled (TOE0n = 1), INTTM0n (master channel timer interrupt) and INTTM0p (slave channel timer interrupt) are transmitted to the TO0 register. Writing to the TO0 register (TO0n write signal) becomes invalid. When TOE0n = 1, the TO0n pin output never changes with signals other than interrupt signals. To initialize the TO0n pin output level, it is necessary to set timer operation is stopped (TOE0n = 0) and to write a value to the TO0 register. <4> While timer output is disabled (TOE0n = 0), writing to the TO0n bit to the target channel (TO0n write signal) becomes valid. When timer output is disabled (TOE0n = 0), neither INTTM0n (master channel timer interrupt) nor INTTM0p (slave channel timer interrupt) is transmitted to the TO0 register. <5> The TO0 register can always be read, and the TO0n pin output level can be checked. Remark n: Channel number n = 0 to 7 (n = 0, 2, 4, or 6 for master channel) p: Slave channel number n<p7 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 220 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.6.2 TO0n Pin Output Setting The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer operation start. Figure 6-29. Status Transition from Timer Output Setting to Operation Start TCR0n Undefined value (FFFFH after reset) (Counter) Hi-Z Timer alternate-function pin Timer output signal TO0n TOE0n Write operation enabled period to TO0n <1> Set TOM0n Set TOL0n <2> Set TO0n Write operation disabled period to TO0n <3> Set TOE0n <4> Set the port to <5> Timer operation start output mode <1> The operation mode of timer output is set. * TOM0n bit (0: Master channel output mode, 1: Slave channel output mode) * TOL0n bit (0: Positive logic output, 1: Negative logic output) <2> The timer output signal is set to the initial status by setting timer output register 0 (TO0). <3> The timer output operation is enabled by writing 1 to the TOE0n bit (writing to the TO0 register is disabled). <4> The port is set to digital I/O by port mode control register (PMCxx) (see 6.3 (14) Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4)). <5> The port I/O setting is set to output (see 6.3 (14) Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4)). <6> The timer operation is enabled (TS0n = 1). Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 221 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.6.3 Cautions on Channel Output Operation (1) Changing values set in the registers TO0, TOE0, and TOL0 during timer operation Since the timer operations (operations of timer count register 0n (TCR0n) and timer data register 0n (TDR0n)) are independent of the TO0n output circuit and changing the values set in timer output register 0 (TO0), timer output enable register 0 (TOE0), timer output level register 0 (TOL0) does not affect the timer operation, the values can be changed during timer operation. To output an expected waveform from the TO0n pin by timer operation, however, set the TO0, TOE0, TOL0, and TOM0 registers to the values stated in the register setting example of each operation. When the values set to the TOE0 and TOL0 registers (but not the TO0 register) are changed close to the occurrence of the timer interrupt (INTTM0n) of each channel, the waveform output to the TO0n pin might differ, depending on whether the values are changed immediately before or immediately after the timer interrupt (INTTM0n) occurs. Remark n: Channel number (n = 0 to 7) (2) Default level of TO0n pin and output level after timer operation start The change in the output level of the TO0n pin when timer output register 0 (TO0) is written while timer output is disabled (TOE0n = 0), the initial level is changed, and then timer output is enabled (TOE0n = 1) before port output is enabled, is shown below. (a) When operation starts with master channel output mode (TOM0n = 0) setting The setting of timer output level register 0 (TOL0) is invalid when master channel output mode (TOM0n = 0). When the timer operation starts after setting the default level, the toggle signal is generated and the output level of the TO0n pin is reversed. Figure 6-30. TO0n Pin Output Status at Toggle Output (TOM0n = 0) TOEmn Hi -Z Default status TOmn bit = 0 (Default status : Low) TOLmn bit = 0 (Active high) TOmn bit = 1 (Default status : High) TOmn (output) TOmn bit = 0 (Default status : Low) TOLmn bit = 1 (Active low) TOmn bit = 1 (Default status : High) Port output is enabled Bold : Active level Toggle Remarks 1. Toggle: Toggle Toggle Toggle Toggle Reverse TO0n pin output status 2. n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 222 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output)) When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0 (TOL0p) setting. Figure 6-31. TOM0p Pin Output Status at PWM Output (TO0p = 1) TOEmp Hi -Z Default status Active Active Active TOmp bit = 0 (Default status : Low) TOmp bit = 1 (Default status : High) TOmp (output) TOLmp bit = 0 (Active high) TOmp bit = 0 (Default status : Low) TOmp bit = 1 (Default status : High) TOLmp bit = 1 (Active low) Port output is enabled Reset Set Remarks 1. Set: Reset: Reset Set Set The output signal of the TO0p pin changes from inactive level to active level. The output signal of the TO0p pin changes from active level to inactive level. 2. p: Channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 223 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (3) Operation of TO0n pin in slave channel output mode (TOM0n = 1) (a) When timer output level register 0 (TOL0) setting has been changed during timer operation When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the generation timing of the TO0n pin change condition. Rewriting the TOL0 register does not change the output level of the TO0n pin. The operation when TOM0n is set to 1 and the value of the TOL0 register is changed while the timer is operating (TE0n = 1) is shown below. Figure 6-32. Operation when TOL0 Register Has Been Changed during Timer Operation TOL0 Active Active Active Active TO0n(Output) Reset Set Remarks 1. Set: Reset: Reset Reset Set Set Reset Set The output signal of the TO0p pin changes from inactive level to active level. The output signal of the TO0p pin changes from active level to inactive level. 2. n: Channel number (n = 0 to 7) (b) Set/reset timing To realize 0%/100% output at PWM output, the TO0n pin/TO0n bit set timing at master channel timer interrupt (INTTM0n) generation is delayed by 1 count clock by the slave channel. If the set condition and reset condition are generated at the same time, a higher priority is given to the latter. Figure 6-34 shows the set/reset operating statuses where the master/slave channels are set as follows. Master channel: TOE0n = 1, TOM0n = 0, TOL0n = 0 Slave channel: TOE0p = 1, TOM0p = 1, TOL0p = 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 224 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-33. Set/Reset Timing Operating Statuses (a) Basic operation timing fTCLK INTTM0n Master channel Internal reset signal TO0n pin/ TO0n Toggle Toggle Internal set signal 1 clock delay Slave channel INTTM0p Internal reset signal TO0p pin/ TO0p Set Set Reset (b) Operation timing when 0 % duty fTCLK INTTMmn Master channel Internal reset signal TO0n pin/ TO0n Toggle Toggle Internal set signal 1 clock delay TCR0p Slave channel 0000 0001 0000 0001 INTTM0p Set Internal reset signal TO0p pin/ TO0p Reset Set Reset has priority. Reset Reset has priority. Remarks 1. Internal reset signal: TO0n pin reset/toggle signal Internal set signal: TO0n pin set signal 2. n: Channel number (n = 0 to 7) n = 0 to 7 (n = 0, 2, 4, 6 for master channel) p: Slave channel number n<p7 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 225 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.6.4 Collective manipulation of TO0n bit In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer channel start register 0 (TS0). Therefore, the TO0n bit of all the channels can be manipulated collectively. Only the desired bits can also be manipulated by enabling writing only to the TO0n bits (TOE0n = 0) that correspond to the relevant bits of the channel used to perfor0 output (TO0n). Figure 6-34 Example of TO0n Bit Collective Manipulation Before writing TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 0 TOE0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 TOE07 TOE06 TOE05 TOE04 TOE03 TOE02 TOE01 TOE00 0 0 1 0 1 1 1 1 1 1 0 0 0 0 1 1 O O x O x x x x Data to be written 0 0 0 0 0 0 0 0 After writing TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00 1 1 1 0 0 0 1 0 Writing is done only to the TO0n bit with TOE0n = 0, and writing to the TO0n bit with TOE0n = 1 is ignored. TO0n (channel output) to which TOE0n = 1 is set is not affected by the write operation. Even if the write operation is done to the TO0n bit, it is ignored and the output change by timer operation is normally done. Figure 6-35. TO0n Pin Statuses by Collective Manipulation of TO0n Bit Two or more TO0n output can be changed simultaneously TO07 Output does not change when value does not change TO06 TO05 TO04 Writing to the TO0n bit is ignored when TOE0n =1 TO03 TO02 TO01 TO00 Before writing Writing to the TO0n bit Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 226 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to generate a timer interrupt at count start. When MD0n0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTM0n) generation. In the other modes, neither timer interrupt at count operation start nor TO0n output is controlled. Figure 6-37 shows operation examples when the interval timer mode (TOE0n = 1, TOM0n = 0) is set. Figure 6-36. Operation examples of timer interrupt at count operation start and TOmn output (a) When MD0n0 is set to 1 TCR0n TE0n INTTM0n TO0n Count operation start (b) When MD0n0 is set to 0 TCR0n TE0n INTTM0n TO0n Count operation start When MD0n0 is set to 1, a timer interrupt (INTTM0n) is output at count operation start, and TO0n performs a toggle operation. When MD0n0 is set to 0, a timer interrupt (INTTM0n) is not output at count operation start, and TO0n does not change either. After counting one cycle, INTTM0n is output and TO0n performs a toggle operation. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 227 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7 Independent Channel Operation Function of Timer Array Unit 6.7.1 Operation as interval timer/square wave output (1) Interval timer The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed intervals. The interrupt generation period can be calculated by the following expression. Generation period of INTTM0n (timer interrupt) = Period of count clock x (Set value of TDR0n + 1) (2) Operation as square wave output TO0n performs a toggle operation as soon as INTTM0n has been generated, and outputs a square wave with a duty factor of 50%. The period and frequency for outputting a square wave from TO0n can be calculated by the following expressions. * Period of square wave output from TO0n = Period of count clock x (Set value of TDR0n + 1) x 2 * Frequency of square wave output from TO0n = Frequency of count clock/{(Set value of TDR0n + 1) x 2} Timer count register 0n (TCR0n) operates as a down counter in the interval timer mode. The TCR0n register loads the value of timer data register 0n (TDR0n) at the first count clock after the channel start trigger bit (TS0n, TSH01, TSH03) of timer channel start register 0 (TS0) is set to 1. If the MD0n0 bit of timer mode register 0n (TMR0n) is 0 at this time, INTTM0n is not output and TO0n is not toggled. If the MD0n0 bit of the TMR0n register is 1, INTTM0n is output and TO0n is toggled. After that, the TCR0n register count down in synchronization with the count clock. When TCR0n = 0000H, INTTM0n is output and TO0n is toggled at the next count clock. At the same time, the TCR0n register loads the value of the TDR0n register again. After that, the same operation is repeated. The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid from the next period. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 228 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Clock selection Figure 6-37. Block Diagram of Operation as Interval Timer/Square Wave Output CK01 CK00 Trigger selection Operation clockNote TS0n Timer counter register 0n (TCR0n) Output controller Timer data register 0n (TDR0n) Interrupt controller TO0n pin Interrupt signal (INTTM0n) Note When channels 1 and 3, the clock can be selected from CK00 to CK03. Figure 6-38. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MD0n0 = 1) TS0n TE0n TCR0n 0000H TDR0n a b TO0n INTTM0n a+1 a+1 a+1 b+1 b+1 b+1 Remarks 1. n: Channel number (n = 0 to 7) 2. TS0n: Bit n of timer channel start register 0 (TS0) TE0n: Bit n of timer channel enable status register 0 (TE0) TCR0n: Timer count register 0n (TCR0n) TDR0n: Timer data register 0n (TDR0n) TO0n: TO0n pin output signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 229 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (1/2) (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 1/0 12 11 CCS0n M/S 0 0 Note 0/1 10 9 8 7 6 5 4 0 0 STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 0 0 0 0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 0 0 0 0 1/0 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTM0n nor inverts timer output when counting is started. 1: Generates INTTM0n and inverts timer output when counting is started. Selection of TI0n pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 1: 8-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. 01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 1/0 1: Outputs 1 from TO0n. (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 1/0 0: Stops the TO0n output operation by counting operation. 1: Enables the TO0n output operation by counting operation. Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 230 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-39. Example of Set Contents of Registers During Operation as Interval Timer/Square Wave Output (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when master channel output mode (TOM0n = 0) 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 231 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2) Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01 (or CK02 and CK03 when using the 8-bit timer mode). Channel default setting Operation is resumed. Operation start Sets timer mode register 0n (TMR0n) (determines operation mode of channel). Sets interval (period) value to timer data register 0n (TDR0n). Channel stops operating. (Clock is supplied and some power is consumed.) To use the TO0n output Clears the TOM0n bit of timer output mode register 0 (TOM0) to 0 (master channel output mode). Clears the TOL0n bit to 0. Sets the TO0n bit and determines default level of the TO0n output. The TO0n pin goes into Hi-Z output state. Sets the TOE0n bit to 1 and enables operation of TO0n. Clears the port register and port mode register to 0. TO0n does not change because channel stops operating. The TO0n pin outputs the TO0n set level. (Sets the TOE0n bit to 1 only if using TO0n output and resuming operation.). Sets the TS0n (TSH01, TSH03) bit to 1. The TS0n (TSH01, TSH03) bit automatically returns to 0 because it is a trigger bit. The TO0n default setting level is output when the port mode register is in the output mode and the port register is 0. TE0n (TEH01, TEH03) = 1, and count operation starts. Value of the TDR0n register is loaded to timer count register 0n (TCR0n) at the count clock input. INTTM0n is generated and TO0n performs toggle operation if the MD0n0 bit of the TMR0n register is 1. During operation Set values of the TMR0n register, TOM0n, and TOL0n bits cannot be changed. Set value of the TDR0n register can be changed. The TCR0n register can always be read. The TSR0n register is not used. Set values of the TO0 and TOE0 registers can be changed. Counter (TCR0n) counts down. When count value reaches 0000H, the value of the TDR0n register is loaded to the TCR0n register again and the count operation is continued. By detecting TCR0n = 0000H, INTTM0n is generated and TO0n performs toggle operation. After that, the above operation is repeated. Operation stop The TT0n (TTH01, TTH03) bit is set to 1. The TT0n (TTH01, TTH03) bit automatically returns to 0 because it is a trigger bit. TE0n (TEH01, TEH03), and count operation stops. The TCR0n register holds count value and stops. The TO0n output is not initialized but holds current status. The TOE0n bit is cleared to 0 and value is set to the TO0n bit. The TO0n pin outputs the TO0n bit set level. (Remark is listed on the next page.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 232 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (2/2) Software Operation TAU stop To hold the TO0n pin output level Clears the TO0n bit to 0 after the value to be held is set to the port register. When holding the TO0n pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. Hardware Status The TO0n pin output level is held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO0n bit is cleared to 0 and the TO0n pin is set to port mode.) Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 233 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7.2 Operation as external event counter The timer array unit can be used as an external event counter that counts the number of times the valid input edge (external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an interrupt. The specified number of counts can be calculated by the following expression. Specified number of counts = Set value of TDR0n + 1 Timer count register 0n (TCR0n) operates as a down counter in the event counter mode. The TCR0n register loads the value of timer data register 0n (TDR0n) by setting any channel start trigger bit (TS0n, TSH01, TSH03) of timer channel start register 0 (TS0) to 1. The TCR0n register counts down each time the valid input edge of the TI0n pin has been detected. When TCR0n = 0000H, the TCR0n register loads the value of the TDR0n register again, and outputs INTTM0n. After that, the above operation is repeated. An irregular waveform that depends on external events is output from the TO0n pin. Stop the output by setting the TOE0n bit of timer output enable register 0 (TOE0) to 0. The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid during the next count period. TI0n pin Noise filter Edge detection TS0n Remark Trigger selection TNFEN0n Clock selection Figure 6-41. Block Diagram of Operation as External Event Counter Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n) Interrupt controller Interrupt signal (INTTM0n) n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 234 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-42. Example of Basic Timing of Operation as External Event Counter TS0n TE0n TI0n 3 TCR0n 0000H TDR0n 2 3 1 2 0 1 2 0 0003H 1 2 0 1 0002H INTTM0n 4 events 4 events 3 events Remarks 1. n: Channel number (n = 0 to 7) 2. TS0n: Bit n of timer channel start register 0 (TS0) TE0n: Bit n of timer channel enable status register 0 (TE0) TI0n: TI0n pin input signal TCR0n: Timer count register 0n (TCR0n) TDR0n: Timer data register 0n (TDR0n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 235 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (1/2) (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 1/0 12 11 CCS0n M/S 0 Note 0/1 1 10 9 8 7 6 5 4 0 0 STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 0 0 0 1/0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 1/0 0 1 1 0 Operation mode of channel n 011B: Event count mode Setting of operation when counting is started 0: Neither generates INTTM0n nor inverts timer output when counting is started. Selection of TI0n pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 000B: Selects only software start. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 1: 8-bit timer Count clock selection 1: Selects the TI0n pin input valid edge. Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. 01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 236 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when master channel output mode (TOM0n = 0). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 237 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-44. Operation Procedure When External Event Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01 (or CK02 and CK03 when using the 8-bit timer mode). Channel Sets timer mode register 0n (TMR0n) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting Sets number of counts to timer data register 0n (TDR0n). Sets noise filter enable register 1 (NFEN1) Clears the TOE0n bit of timer output enable register 0 (TOE0) to 0. Operation Operation is resumed. start Sets the TS0n bit to 1. TE0n = 1, and count operation starts. The TS0n bit automatically returns to 0 because it is a Value of the TDR0n register is loaded to timer count trigger bit. register 0n (TCR0n) and detection of the TI0n pin input edge is awaited. During Set value of the TDR0n register can be changed. Counter (TCR0n) counts down each time input edge of the operation The TCR0n register can always be read. TI0n pin has been detected. When count value reaches The TSR0n register is not used. 0000H, the value of the TDR0n register is loaded to the Set values of the TMR0n register, TOM0n, TOL0n, TO0n, TCR0n register again, and the count operation is and TOE0n bits cannot be changed. continued. By detecting TCR0n = 0000H, the INTTM0n output is generated. After that, the above operation is repeated. Operation stop The TTmn bit is set to 1. The TTmn bit automatically returns to 0 because it is a TE0n = 0, and count operation stops. The TCR0n register holds count value and stops. trigger bit. TAU The TAU0EN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 238 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7.3 Operation as frequency divider (channel 0 of unit 0 only) The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result from the TO00 pin. The divided clock frequency output from TO00 can be calculated by the following expression. * When rising edge/falling edge is selected: Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) x 2} * When both edges are selected: Divided clock frequency Input clock frequency/(Set value of TDR00 + 1) Timer count register 00 (TCR00) operates as a down counter in the interval timer mode. After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the value of timer data register 00 (TDR00) when the TI00 valid edge is detected. If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled. After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00. At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting. If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock period of the TO00 output. The period of the TO00 output clock includes a sampling error of one period of the operation clock. Clock period of TO00 output = Ideal TO00 output clock period Operation clock period (error) The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next count period. Figure 6-45. Block Diagram of Operation as Frequency Divider Noise filter Edge detection TS00 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Trigger selection TI00 pin Clock selection TNFEN00 Timer counter register 00 (TCR00) Output controller TO00 pin Timer data register 00 (TDR00) 239 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-46. Example of Basic Timing of Operation as Frequency Divider (MD000 = 1) TS00 TE00 TI00 2 2 1 TCR00 0000H TDR00 2 1 0 1 0 1 0 0002H 1 1 0 0 1 0 0 0001H TO00 INTTM00 Divided by 6 Remark TS00: Divided by 4 Bit n of timer channel start register 0 (TS0) TE00: Bit n of timer channel enable status register 0 (TE0) TI00: TI00 pin input signal TCR00: Timer count register 00 (TCR00) TDR00: Timer data register 00 (TDR00) TO00: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 TO00 pin output signal 240 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-47. Example of Set Contents of Registers During Operation as Frequency Divider (a) Timer mode register 00 (TMR00) 15 TMR00 14 13 CKS0n1 CKS0n0 1/0 0 0 12 11 CCS00 MAS TER00 1 0 10 9 8 7 6 5 4 0 0 STS002 STS001 STS000 CIS001 CIS000 0 0 0 1/0 3 2 1 0 MD003 MD002 MD001 MD000 1/0 0 0 0 1/0 Operation mode of channel 0 000B: Interval timer Setting of operation when counting is started 0: Neither generates INTTM00 nor inverts timer output when counting is started. 1: Generates INTTM00 and inverts timer output when counting is started. Selection of TI00 pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 000B: Selects only software start. Slave/master selection 0: Independent channel operation. Count clock selection 1: Selects the TI00 pin input valid edge. Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel 0. 10B: Selects CK01 as operation clock of channel 0. (b) Timer output register 0 (TO0) Bit 0 TO0 TO00 0: Outputs 0 from TO00. 1/0 1: Outputs 1 from TO00. (c) Timer output enable register 0 (TOE0) Bit 0 TOE0 TOE00 1/0 0: Stops the TO00 output operation by counting operation. 1: Enables the TO00 output operation by counting operation. (d) Timer output level register 0 (TOL0) Bit 0 TOL0 TOL00 0: Cleared to 0 when master channel output mode (TOM00 = 0) 0 (e) Timer output mode register 0 (TOM0) Bit 0 TOM0 TOM00 0: Sets master channel output mode. 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 241 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-48. Operation Procedure When Frequency Divider Function Is Used Software Operation TAU default setting Hardware Status Power-off status (Clock supply is stopped and writing to each register is disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel default setting Sets timer mode register 0n (TMR0n) (determines operation mode of channel and selects the detection edge). Sets interval (period) value to timer data register 00 (TDR00). Channel stops operating. (Clock is supplied and some power is consumed.) Sets noise filter enable register 1 (NFEN1) Clears the TOM00 bit of timer output mode register 0 (TOM0) to 0 (master channel output mode). Clears the TOL00 bit to 0. Sets the TO00 bit and determines default level of the TO00 output. Operation is resumed. Sets the TOE00 bit to 1 and enables operation of TO00. Clears the port register and port mode register to 0. The TO00 pin goes into Hi-Z output state. The TO00 default setting level is output when the port mode register is in output mode and the port register is 0. TO00 does not change because channel stops operating. The TO00 pin outputs the TO00 set level. Operation start Sets the TOE00 bit to 1 (only when operation is resumed). Sets the TS00 bit to 1. The TS00 bit automatically returns to 0 because it is a trigger bit. During operation Set value of the TDR00 register can be changed. The TCR00 register can always be read. The TSR00 register is not used. Set values of the TO0 and TOE0 registers can be changed. Set values of the TMR00 register, TOM00, and TOL00 bits cannot be changed. Counter (TCR00) counts down. When count value reaches 0000H, the value of the TDR00 register is loaded to the TCR00 register again, and the count operation is continued. By detecting TCR00 = 0000H, INTTM00 is generated and TO00 performs toggle operation. After that, the above operation is repeated. Operation stop The TT00 bit is set to 1. The TT00 bit automatically returns to 0 because it is a trigger bit. TE00 = 0, and count operation stops. The TCR00 register holds count value and stops. The TO00 output is not initialized but holds current status. The TOE00 bit is cleared to 0 and value is set to the TO00 bit. The TO00 pin outputs the TO00 set level. TAU stop To hold the TO00 pin output level Clears the TO00 bit to 0 after the value to be held is set to the port register. When holding the TO00 pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 TE00 = 1, and count operation starts. Value of the TDR00 register is loaded to timer count register 00 (TCR00) at the count clock input. INTTM00 is generated and TO00 performs toggle operation if the MD000 bit of the TMR00 register is 1. The TO00 pin output level is held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO00 bit is cleared to 0 and the TO00 pin is set to port mode). 242 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7.4 Operation as input pulse interval measurement The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured. The pulse interval can be calculated by the following expression. TI0n input pulse interval = Period of count clock x ((10000H x TSR0n: OVF) + (Capture value of TDR0n + 1)) Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of timer mode register 0n (TMR0n), so an error of up to one operating clock cycle occurs. Timer count register 0n (TCR0n) operates as an up counter in the capture mode. When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TCR0n register counts up from 0000H in synchronization with the count clock. When the TI0n pin input valid edge is detected, the count value of the TCR0n register is transferred (captured) to timer data register 0n (TDR0n) and, at the same time, the TCR0n register is cleared to 0000H, and the INTTM0n is output. If the counter overflows at this time, the OVF bit of timer status register 0n (TSR0n) is set to 1. If the counter does not overflow, the OVF bit is cleared. After that, the above operation is repeated. As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Set the STS0n2 to STS0n0 bits of the TMR0n register to 001B to use the valid edges of TI0n as a start trigger and a capture trigger. When TE0n = 1, a software operation (TS0n = 1) can be used as a capture trigger, instead of using the TI0n pin input. CK01 Operation clockNote CK00 TNFEN0n TI0n pin Noise filter Edge detection TS0n Trigger selection Clock selection Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement Timer counter register 0n (TCR0n) Interrupt controller Interrupt signal (INTTM0n) Timer data register 0n (TDR0n) Note When channels 1 and 3, the clock can be selected from CK00 to CK03. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 243 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0) TS0n TE0n TI0n FFFFH b a TCR0n d c 0000H TDR0n 0000H a b c d INTTM0n OVF Remarks 1. n: Channel number (n = 0 to 7) 2. TS0n: Bit n of timer channel start register 0 (TS0) TE0n: Bit n of timer channel enable status register 0 (TE0) TI0n: TI0n pin input signal TCR0n: Timer count register 0n (TCR0n) TDR0n: Timer data register 0n (TDR0n) OVF: Bit 0 of timer status register 0n (TSR0n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 244 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 0 12 11 CCS0n M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 0 0 1 1/0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 1/0 0 1 0 1/0 Operation mode of channel n 010B: Capture mode Setting of operation when counting is started 0: Does not generate INTTM0n when counting is started. 1: Generates INTTM0n when counting is started. Selection of TI0n pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Capture trigger selection 001B: Selects the TI0n pin input valid edge. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 0: 16-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. 01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops TO0n output operation by counting operation. 0 Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 245 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when master channel output mode (TOM0n = 0). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 246 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel Sets timer mode register 0n (TMR0n) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting Sets Noise filter enable register 1 (NFEN1). Operation Sets TS0n bit to 1. start TE0n = 1, and count operation starts. The TS0n bit automatically returns to 0 because it is a Timer count register 0n (TCR0n) is cleared to 0000H at trigger bit. the count clock input. When the MD0n0 bit of the TMR0n register is 1, Operation is resumed. INTTM0n is generated. During Set values of only the CIS0n1 and CIS0n0 bits of the Counter (TCR0n) counts up from 0000H. When the TI0n operation TMR0n register can be changed. pin input valid edge is detected, the count value is The TDR0n register can always be read. transferred (captured) to timer data register 0n (TDR0n). The TCR0n register can always be read. At the same time, the TCR0n register is cleared to 0000H, The TSR0n register can always be read. and the INTTM0n signal is generated. Set values of the TOM0n, TOL0n, TO0n, and TOE0n bits If an overflow occurs at this time, the OVF bit of timer cannot be changed. status register 0n (TSR0n) is set; if an overflow does not occur, the OVF bit is cleared. After that, the above operation is repeated. Operation stop TAU The TTmn bit is set to 1. TE0n = 0, and count operation stops. The TTmn bit automatically returns to 0 because it is a The TCR0n register holds count value and stops. trigger bit. The OVF bit of the TSR0n register is also held. The TAU0EN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 247 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7.5 Operation as input signal high-/low-level width measurement By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the following expression. Signal width of TI0n input = Period of count clock x ((10000H x TSR0n: OVF) + (Capture value of TDR0n + 1)) Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of timer mode register 0n (TMR0n), so an error equivalent to one operation clock occurs. Timer count register 0n (TCR0n) operates as an up counter in the capture & one-count mode. When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TE0n bit is set to 1 and the TI0n pin start edge detection wait status is set. When the TI0n pin input start edge (rising edge of the TI0n pin input when the high-level width is to be measured) is detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling edge of the TI0n pin input when the high-level width is to be measured) is detected later, the count value is transferred to timer data register 0n (TDR0n) and, at the same time, INTTM0n is output. If the counter overflows at this time, the OVF bit of timer status register 0n (TSR0n) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCR0n register stops at the value "value transferred to the TDR0n register + 1", and the TI0n pin start edge detection wait status is set. After that, the above operation is repeated. As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the captured value can be checked. If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more overflows occur. Whether the high-level width or low-level width of the TI0n pin is to be measured can be selected by using the CIS0n1 and CIS0n0 bits of the TMR0n register. Because this function is used to measure the signal width of the TI0n pin input, the TS0n bit cannot be set to 1 while the TE0n bit is 1. CIS0n1, CIS0n0 of TMR0n register = 10B: Low-level width is measured. CIS0n1, CIS0n0 of TMR0n register = 11B: High-level width is measured. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 248 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Operation clockNote Clock selection Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement CK01 CK00 Interrupt controller Timer counter register 0n (TCR0n) Interrupt signal (INTTM0n) TI0n pin Noise filter Edge detection Trigger selection TNFEN0n Timer data register 0n (TDR0n) Note For channels 1 and 3, the clock can be selected from CK00 to CK03. Figure 6-54. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement TS0n TE0n TI0n FFFFH a b TCR0n c 0000H TDR0n 0000H a b c INTTM0n OVF Remarks 1. n: Channel number (n = 0 to 7) 2. TS0n: Bit n of timer channel start register 0 (TS0) TE0n: Bit n of timer channel enable status register 0 (TE0) TI0n: TI0n pin input signal TCR0n: Timer count register 0n (TCR0n) TDR0n: Timer data register 0n (TDR0n) OVF: Bit 0 of timer status register 0n (TSR0n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 249 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 0 12 11 CCS0n M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 0 1 0 1 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 1/0 1 1 0 0 Operation mode of channel n 110B: Capture & one-count Setting of operation when counting is started 0: Does not generate INTTM0n when counting is started. Selection of TI0n pin input edge 10B: Both edges (to measure low-level width) 11B: Both edges (to measure high-level width) Start trigger selection 010B: Selects the TI0n pin input valid edge. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 0: 16-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. 01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when master channel output mode (TOM0n = 0). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 250 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel Sets timer mode register 0n (TMR0n) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting Sets noise filter enable register 1 (NFEN1) Clears the TOE0n bit to 0 and stops operation of TO0n. Operation start Sets the TS0n bit to 1. The TS0n bit automatically returns to 0 because it is a TE0n = 1, and the TI0n pin start edge detection wait status is set. trigger bit. Operation is resumed. Detects the TI0n pin input count start valid edge. Clears timer count register 0n (TCR0n) to 0000H and starts counting up. During Set value of the TDR0n register can be changed. When the TI0n pin start edge is detected, the counter operation The TCR0n register can always be read. (TCR0n) counts up from 0000H. If a capture edge of the The TSR0n register is not used. TI0n pin is detected, the count value is transferred to timer Set values of the TMR0n register, TOM0n, TOL0n, TO0n, data register 0n (TDR0n) and INTTM0n is generated. and TOE0n bits cannot be changed. If an overflow occurs at this time, the OVF bit of timer status register 0n (TSR0n) is set; if an overflow does not occur, the OVF bit is cleared. The TCR0n register stops the count operation until the next TI0n pin start edge is detected. Operation stop TAU The TTmn bit is set to 1. TE0n = 0, and count operation stops. The TTmn bit automatically returns to 0 because it is a The TCR0n register holds count value and stops. trigger bit. The OVF bit of the TSR0n register is also held. The TAU0EN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 251 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.7.6 Operation as delay counter It is possible to start counting down when the valid edge of the TI0n pin input is detected (an external event), and then generate INTTM0n (a timer interrupt) after any specified interval. It can also generate INTTM0n (timer interrupt) at any interval by making a software set TS0n = 1 and the count down start during the period of TE0n = 1. The interrupt generation period can be calculated by the following expression. Generation period of INTTM0n (timer interrupt) = Period of count clock x (Set value of TDR0n + 1) Timer count register 0n (TCR0n) operates as a down counter in the one-count mode. When the channel start trigger bit (TS0n, TSHm1, TSHm3) of timer channel start register 0 (TS0) is set to 1, the TE0n, TEHm1, TEHm3 bits are set to 1 and the TI0n pin input valid edge detection wait status is set. Timer count register 0n (TCR0n) starts operating upon TI0n pin input valid edge detection and loads the value of timer data register 0n (TDR0n). The TCR0n register counts down from the value of the TDR0n register it has loaded, in synchronization with the count clock. When TCR0n = 0000H, it outputs INTTM0n and stops counting until the next TI0n pin input valid edge is detected. The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid from the next period. CK01 CK00 TS0n TI0n pin Noise filter Edge detection Trigger selection Operation clockNote Clock selection Figure 6-57. Block Diagram of Operation as Delay Counter Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n) Interrupt controller Interrupt signal (INTTM0n) TNFEN0n Note For using channels 1 and 3 in 8-bit timer mode, the clock can be selected from CK00 to CK03. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 252 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-58. Example of Basic Timing of Operation as Delay Counter TS0n TE0n TI0n FFFFH TCR0n 0000H TDR0n a b INTTM0n a+1 b+1 Remarks 1. n: Channel number (n = 0 to 7) 2. TS0n: Bit n of timer channel start register 0 (TS0) TE0n: Bit n of timer channel enable status register 0 (TE0) TI0n: TI0n pin input signal TCR0n: Timer count register 0n (TCR0n) TDR0n: Timer data register 0n (TDR0n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 253 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2) (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 1/0 12 11 CCS0n M/S 0 0 Note 0/1 10 9 8 7 6 5 4 STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 0 0 1 1/0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. 1: Trigger input is valid. Selection of TI0n pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 001B: Selects the TI0n pin input valid edge. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 1: 8-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK02 as operation clock of channel n. 01B: Selects CK01 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). 11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3). (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 Note TMR02, TMR04, TMR06: MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 254 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-59. Example of Set Contents of Registers to Delay Counter (2/2) (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when master channel output mode (TOM0n = 0). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 255 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-60. Operation Procedure When Delay Counter Function Is Used Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01 (or CK02 and CK03 when using the 8-bit timer mode). Channel Sets timer mode register 0n (TMR0n) (determines Channel stops operating. default operation mode of channel). (Clock is supplied and some power is consumed.) setting INTTM0n output delay is set to timer data register 0n (TDR0n). Sets noise filter enable register 1 (NFEN1). Clears the TOE0n bit to 0 and stops operation of TO0n. Operation start Sets the TS0n bit to 1. The TS0n bit automatically returns to 0 because it is a TE0n = 1, and the TI0n pin input valid edge detection wait status is set. trigger bit. Operation is resumed. Detects the TI0n pin input valid edge. Value of the TDR0n register is loaded to the timer count register 0n (TCR0n). During Set value of the TDR0n register can be changed. The counter (TCR0n) counts down. When TCR0n counts operation The TCR0n register can always be read. down to 0000H, INTTM0n is output, and counting stops The TSR0n register is not used. (which leaves TCR0n at 0000H) until the next TI0n pin input. Operation stop The TTmn bit is set to 1. The TTmn bit automatically returns to 0 because it is a TE0n = 0, and count operation stops. The TCR0n register holds count value and stops. trigger bit. TAU The TAU0EN bit of the PER0 register is cleared to 0. stop Power-off status All circuits are initialized and SFR of each channel is also initialized. Remark n: Channel number (n = 0 to 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 256 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.8 Simultaneous Channel Operation Function of Timer Array Unit 6.8.1 Operation as one-shot pulse output function By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input to the TI0n pin. The delay time and pulse width can be calculated by the following expressions. Delay time = {Set value of TDR0n (master) + 2} x Count clock period Pulse width = {Set value of TDR0p (slave)} x Count clock period The master channel operates in the one-count mode and counts the delays. Timer count register 0n (TCR0n) of the master channel starts operating upon start trigger detection and loads the value of timer data register 0n (TDR0n). The TCR0n register counts down from the value of the TDR0n register it has loaded, in synchronization with the count clock. When TCR0n = 0000H, it outputs INTTM0n and stops counting until the next start trigger is detected. The slave channel operates in the one-count mode and counts the pulse width. The TCR0p register of the slave channel starts operation using INTTM0n of the master channel as a start trigger, and loads the value of the TDR0p register. The TCR0p register counts down from the value of The TDR0p register it has loaded, in synchronization with the count value. When count value = 0000H, it outputs INTTM0p and stops counting until the next start trigger (INTTM0n of the master channel) is detected. The output level of TO0p becomes active one count clock after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H. Instead of using the TI0n pin input, a one-shot pulse can also be output using the software operation (TS0n = 1) as a start trigger. Caution The timing of loading of timer data register 0n (TDR0n) of the master channel is different from that of the TDR0p register of the slave channel. If the TDR0n and TDR0p registers are rewritten during operation, therefore, an illegal waveform is output. Rewrite the TDR0n register after INTTM0n is generated and the TDR0p register after INTTM0p is generated. Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 257 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-61. Block Diagram of Operation as One-Shot Pulse Output Function CK01 Operation clock CK00 TS0n TI0n pin Noise filter Edge detection Trigger selection Clock selection Master channel (one-count mode) Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n) Interrupt controller Timer counter register 0p (TCR0p) Output controller Timer data register 0p (TDR0p) Interrupt controller Interrupt signal (INTTM0n) CK01 Operation clock Trigger selection CK00 Clock selection TNFEN0n Slave channel (one-count mode) Remark TO0p pin Interrupt signal (INTTM0p) n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 258 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function TS0n TE0n TI0n Master channel FFFFH TCR0n 0000H TDR0n a TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave channel 0000H TDR0p b TO0p INTTM0p a+2 b a+2 b Remarks 1. n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) 2. TS0n, TS0p: Bit n, p of timer channel start register 0 (TS0) TE0n, TE0p: Bit n, p of timer channel enable status register 0 (TE0) TI0n, TI0p: TI0n and TI0p pins input signal TCR0n, TCR0p: Timer count registers mn, mp (TCR0n, TCR0p) TDR0n, TDR0p: Timer data registers mn, mp (TDR0n, TDR0p) TO0n, TO0p: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 TO0n and TO0p pins output signal 259 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-63. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel) (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 0 12 CCS0n 0 0 11 10 9 8 7 6 5 MAS STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 TERmn 1 0 0 1 1/0 4 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 1/0 0 0 1 0 0 0 Operation mode of channel n 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. Selection of TI0n pin input edge 00B: Detects falling edge. 01B: Detects rising edge. 10B: Detects both edges. 11B: Setting prohibited Start trigger selection 001B: Selects the TI0n pin input valid edge. Slave/master selection Note 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channels n. 10B: Selects CK01 as operation clock of channels n. Note If n = 0, Bit 11 is fixed at 0 of read only. Even if 1 is written to bit 11, become master channel. (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when TOM0n = 0 (master channel output mode). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0, 2, 4, 6) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 260 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Slave Channel) (a) Timer mode register 0p (TMR0p) 15 TMR0p 14 13 CKS0p1 CKS0p0 1/0 0 12 11 CCS0p M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 1 0 0 0 3 2 1 0 MD0p3 MD0p2 MD0p1 MD0p0 0 1 0 0 0 Operation mode of channel p 100B: One-count mode Start trigger during operation 0: Trigger input is invalid. Selection of TI0p pin input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTM0n of master channel. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 0: 16-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel p. 10B: Selects CK01 as operation clock of channel p. * Make the same setting as master channel. (b) Timer output register 0 (TO0) Bit p TO0 TO0p 0: Outputs 0 from TO0p. 1/0 1: Outputs 1 from TO0p. (c) Timer output enable register 0 (TOE0) Bit p TOE0 TOE0p 1/0 0: Stops the TO0p output operation by counting operation. 1: Enables the TO0p output operation by counting operation. (d) Timer output level register 0 (TOL0) Bit p TOL0 TOL0p 0: Positive logic output (active-high) 1/0 1: Negative logic output (active-low) (e) Timer output mode register 0 (TOM0) Bit p TOM0 TOM0p 1: Sets the slave channel output mode. 1 Note TMR02, TMR04, TMR06: Remark MASTER0n bit TMR01, TMR03: SPLIT0n bit TMR00, TMR05, TMR07: 0 fixed n: Master channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 261 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable registers 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel Sets timer mode register 0n, mp (TMR0n, TMR0p) of two Channel stops operating. default channels to be used (determines operation mode of (Clock is supplied and some power is consumed.) setting channels). An output delay is set to timer data register 0n (TDR0n) of the master channel, and a pulse width is set to the TDR0p register of the slave channel. Sets Noise filter enable register 1 (NFEN1) of the master channel. Sets slave channel. The TO0p pin goes into Hi-Z output state. The TOM0p bit of timer output mode register 0 (TOM0) is set to 1 (slave channel output mode). Sets the TOL0p bit. Sets the TO0p bit and determines default level of the TO0p output. The TO0p default setting level is output when the port mode register is in output mode and the port register is 0. Sets the TOE0p bit to 1 and enables operation of TO0p. TO0p does not change because channel stops operating. Clears the port register and port mode register to 0. The TO0p pin outputs the TO0p set level. Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 262 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2) Software Operation Sets the TOE0p bit (slave) to 1 (only when operation is resumed). The TS0n (master) and TS0p (slave) bits of timer channel start register 0 (TS0) are set to 1 at the same time. The TS0n and TS0p bits automatically return to 0 because they are trigger bits. The TE0n and TE0p bits are set to 1 and the master channel enters the TI0n input edge detection wait status. Counter stops operating. Detects the TI0n pin input valid edge of master channel. Master channel starts counting. During operation Set values of only the CIS0n1 and CIS0n0 bits of the TMR0n register can be changed. Set values of the TMR0p, TDR0n, TDR0p registers, TOM0n, TOM0p, TOL0n, and TOL0p bits cannot be changed. The TCR0n and TCR0p registers can always be read. The TSR0n and TSR0p registers are not used. Set values of the TO0 and TOE0 registers of slave channel can be changed. Master channel loads the value of the TDR0n register to timer count register 0n (TCR0n) when the TI0n pin valid input edge is detected, and the counter starts counting down. When the count value reaches TCR0n = 0000H, the INTTM0n output is generated, and the counter stops until the next valid edge is input to the TI0n pin. The slave channel, triggered by INTTM0n of the master channel, loads the value of the TDR0p register to the TCR0p register, and the counter starts counting down. The output level of TO0p becomes active one count clock after generation of INTTM0n from the master channel. It becomes inactive when TCR0p = 0000H, and the counting operation is stopped. After that, the above operation is repeated. Operation stop The TTmn (master) and TTmp (slave) bits are set to 1 at the same time. The TTmn and TTmp bits automatically return to 0 because they are trigger bits. Operation is resumed. Operation start Hardware Status TAU stop TE0n, TE0p = 0, and count operation stops. The TCR0n and TCR0p registers hold count value and stop. The TO0p output is not initialized but holds current status. The TOE0p bit of slave channel is cleared to 0 and value is set to the TO0p bit. The TO0p pin outputs the TO0p set level. To hold the TO0p pin output level Clears the TO0p bit to 0 after the value to be held is set to the port register. The TO0p pin output level is held by port function. When holding the TO0p pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO0p bit is cleared to 0 and the TO0p pin is set to port mode.) Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 263 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.8.2 Operation as PWM function Two channels can be used as a set to generate a pulse of any period and duty factor. The period and duty factor of the output pulse can be calculated by the following expressions. Pulse period = {Set value of TDR0n (master) + 1} x Count clock period Duty factor [%] = {Set value of TDR0p (slave)}/{Set value of TDR0n (master) + 1} x 100 0% output: Set value of TDR0p (slave) = 0000H 100% output: Set value of TDR0p (slave) {Set value of TDR0n (master) + 1} Remark The duty factor exceeds 100% if the set value of TDR0p (slave) > (set value of TDR0n (master) + 1), it summarizes to 100% output. The master channel operates in the interval timer mode. If the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, an interrupt (INTTM0n) is output, the value set to timer data register 0n (TDR0n) is loaded to timer count register 0n (TCR0n), and the counter counts down in synchronization with the count clock. When the counter reaches 0000H, INTTM0n is output, the value of the TDR0n register is loaded again to the TCR0n register, and the counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop register 0 (TTm) is set to 1. If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the PWM output (TO0p) cycle. The slave channel operates in one-count mode. By using INTTM0n from the master channel as a start trigger, the TCR0p register loads the value of the TDR0p register and the counter counts down to 0000H. When the counter reaches 0000H, it outputs INTTM0p and waits until the next start trigger (INTTM0n from the master channel) is generated. If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the PWM output (TO0p) duty. PWM output (TO0p) goes to the active level one clock after the master channel generates INTTM0n and goes to the inactive level when the TCR0p register of the slave channel becomes 0000H. Caution To rewrite both timer data register 0n (TDR0n) of the master channel and the TDR0p register of the slave channel, a write access is necessary two times. The timing at which the values of the TDR0n and TDR0p registers are loaded to the TCR0n and TCR0p registers is upon occurrence of INTTM0n of the master channel. Thus, when rewriting is performed split before and after occurrence of INTTM0n of the master channel, the TO0p pin cannot output the expected waveform. To rewrite both the TDR0n register of the master and the TDR0p register of the slave, therefore, be sure to rewrite both the registers immediately after INTTM0n is generated from the master channel. Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 264 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT CK01 Operation clock CK00 TS0n Trigger selection Master channel (interval timer mode) Clock selection Figure 6-66. Block Diagram of Operation as PWM Function Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n) Interrupt controller Timer counter register 0p (TCR0p) Output controller Timer data register 0p (TDR0p) Interrupt controller Interrupt signal (INTTM0n) CK01 Operation clock Trigger selection CK00 Clock selection Slave channel (one-count mode) Remark TO0p pin Interrupt signal (INTTM0p) n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 265 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-1. Example of Basic Timing of Operation as PWM Function TS0n TE0n FFFFH Master channel TCR0n 0000H TDR0n a b TO0n INTTM0n TS0p TE0p FFFFH TCR0p Slave channel 0000H TDR0p c d TO0p INTTM0p a+1 c a+1 c b+1 d Remark 1. n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) 2. TS0n, TS0p: TE0n, TE0p: Bit n, p of timer channel start register 0 (TS0) Bit n, p of timer channel enable status register 0 (TE0) TCR0n, TCR0p: Timer count registers mn, mp (TCR0n, TCR0p) TDR0n, TDR0p: Timer data registers mn, mp (TDR0n, TDR0p) TO0n, TO0p: TO0n and TO0p pins output signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 266 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-68. Example of Set Contents of Registers When PWM Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 0 12 CCS0n 0 0 11 10 9 8 7 6 MAS STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 TERmn 1 0 0 0 0 5 4 0 0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 0 0 0 0 1 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTM0n when counting is started. Selection of TI0n pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Slave/master selection 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. Note If n = 0, Bit 11 is fixed at 0 of read only. Even if 1 is written to bit 11, become master channel. (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when TOM0n = 0 (master channel output mode). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0, 2, 4, 6) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 267 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used (a) Timer mode register 0p (TMR0p) 15 TMR0p 14 13 CKS0p1 CKS0p0 1/0 0 12 11 CCS0p M/S 0 0 Note 0 10 9 8 7 6 5 4 0 0 STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 1 0 0 0 3 2 1 0 MD0p3 MD0p2 MD0p1 MD0p0 0 1 0 0 1 Operation mode of channel p 100B: One-count mode Start trigger during operation 1: Trigger input is valid. Selection of TI0p pin input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTM0n of master channel. Setting of MASTER0p/SPLIT0p bit 0: Slave channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel p. 10B: Selects CK01 as operation clock of channel p. * Make the same setting as master channel. (b) Timer output register 0 (TO0) Bit p TO0 TO0p 0: Outputs 0 from TO0p. 1/0 1: Outputs 1 from TO0p. (c) Timer output enable register 0 (TOE0) Bit p TOE0 TOE0p 1/0 0: Stops the TO0p output operation by counting operation. 1: Enables the TO0p output operation by counting operation. (d) Timer output level register 0 (TOL0) Bit p TOL0 TOL0p 0: Positive logic output (active-high) 1/0 1: Negative logic output (active-low) (e) Timer output mode register 0 (TOM0) Bit p TOM0 TOM0p 1: Sets the slave channel output mode. 1 Note TMR01, TMR03: SPLIT0p bit TMR05, TMR07: 0 fixed Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 268 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel Sets timer mode registers mn, mp (TMR0n, TMR0p) of Channel stops operating. default two channels to be used (determines operation mode of (Clock is supplied and some power is consumed.) setting channels). An interval (period) value is set to timer data register 0n (TDR0n) of the master channel, and a duty factor is set to the TDR0p register of the slave channel. Sets slave channel. The TO0p pin goes into Hi-Z output state. The TOM0p bit of timer output mode register 0 (TOM0) is set to 1 (slave channel output mode). Sets the TOL0p bit. Sets the TO0p bit and determines default level of the TO0p output. The TO0p default setting level is output when the port mode register is in output mode and the port register is 0. Sets the TOE0p bit to 1 and enables operation of TO0p. TO0p does not change because channel stops operating. Clears the port register and port mode register to 0. The TO0p pin outputs the TO0p set level. Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 269 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-70. Operation Procedure When PWM Function Is Used (2/2) Software Operation Operation Sets the TOE0p bit (slave) to 1 (only when operation is start resumed). Hardware Status The TS0n (master) and TS0p (slave) bits of timer channel start register 0 (TS0) are set to 1 at the same time. TE0n = 1, TE0p = 1 When the master channel starts counting, INTTM0n is The TS0n and TS0p bits automatically return to 0 generated. Triggered by this interrupt, the slave because they are trigger bits. channel also starts counting. Set values of the TMR0n and TMR0p registers, TOM0n, The counter of the master channel loads the TDR0n operation TOM0p, TOL0n, and TOL0p bits cannot be changed. register value to timer count register 0n (TCR0n), and Set values of the TDR0n and TDR0p registers can be counts down. When the count value reaches TCR0n = changed after INTTM0n of the master channel is 0000H, INTTM0n output is generated. At the same time, generated. the value of the TDR0n register is loaded to the TCR0n The TCR0n and TCR0p registers can always be read. register, and the counter starts counting down again. The TSR0n and TSR0p registers are not used. At the slave channel, the value of the TDR0p register is Operation is resumed. During loaded to the TCR0p register, triggered by INTTM0n of the master channel, and the counter starts counting down. The output level of TO0p becomes active one count clock after generation of the INTTM0n output from the master channel. It becomes inactive when TCR0p = 0000H, and the counting operation is stopped. After that, the above operation is repeated. Operation The TTmn (master) and TTmp (slave) bits are set to 1 at stop the same time. TE0n, TE0p = 0, and count operation stops. The TTmn and TTmp bits automatically return to 0 The TCR0n and TCR0p registers hold count value and because they are trigger bits. stop. The TO0p output is not initialized but holds current status. The TOE0p bit of slave channel is cleared to 0 and value is set to the TO0p bit. TAU stop The TO0p pin outputs the TO0p set level. To hold the TO0p pin output level Clears the TO0p bit to 0 after the value to The TO0p pin output level is held by port function. be held is set to the port register. When holding the TO0p pin output level is not necessary Setting not required. The TAU0EN bit of the PER0 register is cleared to 0. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO0p bit is cleared to 0 and the TO0p pin is set to port mode.) Remark n: Channel number (n = 0, 2, 4, 6) p: Slave channel number (n < p 7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 270 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.8.3 Operation as multiple PWM output function By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values can be output. For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the following expressions. Pulse period = {Set value of TDR0n (master) + 1} x Count clock period Duty factor 1 [%] = {Set value of TDR0p (slave 1)}/{Set value of TDR0n (master) + 1} x 100 Duty factor 2 [%] = {Set value of TDR0q (slave 2)}/{Set value of TDR0n (master) + 1} x 100 Remark Although the duty factor exceeds 100% if the set value of TDR0p (slave 1) > {set value of TDR0n (master) + 1} or if the {set value of TDR0q (slave 2)} > {set value of TDR0n (master) + 1}, it is summarized into 100% output. Timer count register 0n (TCR0n) of the master channel operates in the interval timer mode and counts the periods. The TCR0p register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TO0p pin. The TCR0p register loads the value of timer data register 0p (TDR0p), using INTTM0n of the master channel as a start trigger, and starts counting down. When TCR0p = 0000H, TCR0p outputs INTTM0p and stops counting until the next start trigger (INTTM0n of the master channel) has been input. The output level of TO0p becomes active one count clock after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H. In the same way as the TCR0p register of the slave channel 1, the TCR0q register of the slave channel 2 operates in one-count mode, counts the duty factor, and outputs a PWM waveform from the TO0q pin. The TCR0q register loads the value of the TDR0q register, using INTTM0n of the master channel as a start trigger, and starts counting down. When TCR0q = 0000H, the TCR0q register outputs INTTM0q and stops counting until the next start trigger (INTTM0n of the master channel) has been input. The output level of TO0q becomes active one count clock after generation of INTTM0n from the master channel, and inactive when TCR0q = 0000H. When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same time. Caution To rewrite both timer data register 0n (TDR0n) of the master channel and the TDR0p register of the slave channel 1, write access is necessary at least twice. Since the values of the TDR0n and TDR0p registers are loaded to the TCR0n and TCR0p registers after INTTM0n is generated from the master channel, if rewriting is performed separately before and after generation of INTTM0n from the master channel, the TO0p pin cannot output the expected waveform. To rewrite both the TDR0n register of the master and the TDR0p register of the slave, be sure to rewrite both the registers immediately after INTTM0n is generated from the master channel (This applies also to the TDR0q register of the slave channel 2). Remark n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are consecutive integers greater than n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 271 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT CK01 Operation clock CK00 TS0n Trigger selection Master channel (interval timer mode) Clock selection Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs) Timer counter register 0n (TCR0n) Timer data register 0n (TDR0n) Interrupt controller Timer counter register 0p (TCR0p) Output controller Timer data register 0p (TDR0p) Interrupt controller Timer counter register 0q (TCR0q) Output controller Timer data register 0q (TDR0q) Interrupt controller Interrupt signal (INTTM0n) Operation clock CK01 Trigger selection CK00 Clock selection Slave channel 1 (one-count mode) TO0p pin Interrupt signal (INTTM0p) CK01 Operation clock Trigger selection CK00 Clock selection Slave channel 2 (one-count mode) Remark TO0q pin Interrupt signal (INTTM0q) n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are consecutive integers greater than n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 272 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) (1/2) TS0n TE0n FFFFH Master channel TCR0n 0000H TDR0n a b TO0n INTTM0n TS0p TE0p FFFFH Slave channel 1 TCR0p 0000H TDR0p c d TO0p INTTM0p a+1 a+1 c c b+1 d d TS0q TE0q FFFFH Slave channel 2 TCR0q 0000H TDR0q e f TO0q INTTM0q a+1 e a+1 e b+1 f f (Remark is listed on the next page.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 273 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-72. Example of Basic Timing of Operation as Multiple PWM Output Function (Output two types of PWMs) (2/2) Remarks 1. n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are consecutive integers greater than n) 2. TS0n, TS0p, TS0q: TE0n, TE0p, TE0q: Bit n, p, q of timer channel start register 0 (TS0) Bit n, p, q of timer channel enable status register 0 (TE0) TCR0n, TCR0p, TCR0q: Timer count registers mn, mp, mq (TCR0n, TCR0p, TCR0q) TDR0n, TDR0p, TDR0q: Timer data registers mn, mp, mq (TDR0n, TDR0p, TDR0q) TO0n, TO0p, TO0q: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 TO0n, TO0p, and TO0q pins output signal 274 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-73. Example of Set Contents of Registers When Multiple PWM Output Function (Master Channel) Is Used (a) Timer mode register 0n (TMR0n) 15 TMR0n 14 13 CKS0n1 CKS0n0 1/0 0 12 CCS0n 0 0 11 10 9 8 7 6 MAS STS0n2 STS0n1 STS0n0 CIS0n1 CIS0n0 TERmn 0 1 0 0 0 5 4 0 0 3 2 1 0 MD0n3 MD0n2 MD0n1 MD0n0 0 0 0 0 1 Operation mode of channel n 000B: Interval timer Setting of operation when counting is started 1: Generates INTTM0n when counting is started. Selection of TI0n pin input edge 00B: Sets 00B because these are not used. Start trigger selection 000B: Selects only software start. Slave/master selection 1: Master channel. Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel n. 10B: Selects CK01 as operation clock of channel n. (b) Timer output register 0 (TO0) Bit n TO0 TO0n 0: Outputs 0 from TO0n. 0 (c) Timer output enable register 0 (TOE0) Bit n TOE0 TOE0n 0: Stops the TO0n output operation by counting operation. 0 (d) Timer output level register 0 (TOL0) Bit n TOL0 TOL0n 0: Cleared to 0 when TOM0n = 0 (master channel output mode). 0 (e) Timer output mode register 0 (TOM0) Bit n TOM0 TOM0n 0: Sets master channel output mode. 0 Remark n: Channel number (n = 0, 2, 4) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 275 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-74. Example of Set Contents of Registers When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs) (a) Timer mode register 0p, mq (TMR0p, TMR0q) 15 TMR0p TMR0q 14 13 CKS0p1 CKS0p0 0 0 15 14 13 CKS0q1 CKS0q0 0 11 CCS0p M/S 1/0 1/0 12 0 0 12 11 CCS0q M/S 0 Note 0 Note 0 10 9 8 7 6 5 4 STS0p2 STS0p1 STS0p0 CIS0p1 CIS0p0 0 0 0 0 0 0 10 9 8 7 6 5 4 STS0q2 STS0q1 STS0q0 CIS0q1 CIS0q0 0 0 0 0 2 1 0 MD0p3 MD0p2 MD0p1 MD0p0 1 1 3 1 0 0 1 3 2 1 0 MD0q3 MD0q2 MD0q1 MD0q0 0 0 1 0 0 1 Operation mode of channel p, q 100B: One-count mode Start trigger during operation 1: Trigger input is valid. Selection of TI0p and TI0q pins input edge 00B: Sets 00B because these are not used. Start trigger selection 100B: Selects INTTM0n of master channel. Setting of MASTERmn bit (Channel 2, 4, 6) 0: Independent channel operation. Setting of SPLITmn bit (Channel 1, 3) 0: 16-bit timer Count clock selection 0: Selects operation clock (fMCK). Operation clock (fMCK) selection 00B: Selects CK00 as operation clock of channel p, q. 10B: Selects CK01 as operation clock of channel p, q. * Make the same setting as master channel. (b) Timer output register 0 (TO0) TO0 Bit q Bit p TO0q TO0p 1/0 1/0 0: Outputs 0 from TO0p or TO0q. 1: Outputs 1 from TO0p or TO0q. (c) Timer output enable register 0 (TOE0) TOE0 Bit q Bit p TOE0q TOE0p 1/0 1/0 0: Stops the TO0p or TO0q output operation by counting operation. 1: Enables the TO0p or TO0q output operation by counting operation. (d) Timer output level register 0 (TOL0) TOL0 Bit q Bit p TOL0q TOL0p 1/0 1/0 0: Positive logic output (active-high) 1: Negative logic output (active-low) (e) Timer output mode register 0 (TOM0) Bit q TOM0 Bit p TOM0q TOM0p 1 1: Sets the slave channel output mode. 1 Note TMR02, TMR04, TMR06: TMR01, TMR03: MASTER0n bit SPLIT0n bit TMR05, TMR07: 0 fixed Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are consecutive integers greater than n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 276 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (1/2) Software Operation Hardware Status Power-off status TAU default (Clock supply is stopped and writing to each register is setting disabled.) Sets the TAU0EN bit of peripheral enable register 0 (PER0) to 1. Power-on status. Each channel stops operating. (Clock supply is started and writing to each register is enabled.) Sets timer clock select register 0 (TPS0). Determines clock frequencies of CK00 and CK01. Channel Sets timer mode registers mn, mp, 0q (TMR0n, TMR0p, Channel stops operating. default TMR0q) of each channel to be used (determines (Clock is supplied and some power is consumed.) setting operation mode of channels). An interval (period) value is set to timer data register 0n (TDR0n) of the master channel, and a duty factor is set to the TDR0p and TDR0q registers of the slave channels. Sets slave channels. The TO0p and TO0q pins go into Hi-Z output state. The TOM0p and TOM0q bits of timer output mode register 0 (TOM0) are set to 1 (slave channel output mode). Sets the TOL0p and TOL0q bits. Sets the TO0p and TO0q bits and determines default level of the TO0p and TO0q outputs. The TO0p and TO0q default setting levels are output when the port mode register is in output mode and the port register is 0. Sets the TOE0p and TOE0q bits to 1 and enables operation of TO0p and TO0q. TO0p and TO0q do not change because channels stop operating. Clears the port register and port mode register to 0. The TO0p and TO0q pins output the TO0p and TO0q set levels. Remark n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are a consecutive integer greater than n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 277 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (2/2) Software Operation Operation (Sets the TOE0p and TOE0q (slave) bits to 1 only when resuming operation.) start The TS0n bit (master), and TS0p and TS0q (slave) bits of timer channel start register 0 (TS0) are set to 1 at the same time. The TS0n, TS0p, and TS0q bits automatically return to 0 because they are trigger bits. Set values of the TMR0n, TMR0p, TMR0q registers, TOM0n, TOM0p, TOM0q, TOL0n, TOL0p, and TOL0q bits cannot be changed. Set values of the TDR0n, TDR0p, and TDR0q registers can be changed after INTTM0n of the master channel is generated. The TCR0n, TCR0p, and TCR0q registers can always be read. The TSR0n, TSR0p, and TSR0q registers are not used. Operation stop The TTmn bit (master), TTmp, and TTmq (slave) bits are set to 1 at the same time. The TTmn, TTmp, and TTmq bits automatically return to 0 because they are trigger bits. Operation is resumed. During operation The TOE0p and TOE0q bits of slave channels are cleared to 0 and value is set to the TO0p and TO0q bits. TAU stop To hold the TO0p and TO0q pin output levels Clears the TO0p and TO0q bits to 0 after the value to be held is set to the port register. When holding the TO0p and TO0q pin output levels are not necessary Setting not required The TAU0EN bit of the PER0 register is cleared to 0. Remark Hardware Status TE0n = 1, TE0p, TE0q = 1 When the master channel starts counting, INTTM0n is generated. Triggered by this interrupt, the slave channel also starts counting. The counter of the master channel loads the TDR0n register value to timer count register 0n (TCR0n) and counts down. When the count value reaches TCR0n = 0000H, INTTM0n output is generated. At the same time, the value of the TDR0n register is loaded to the TCR0n register, and the counter starts counting down again. At the slave channel 1, the values of the TDR0p register are transferred to the TCR0p register, triggered by INTTM0n of the master channel, and the counter starts counting down. The output levels of TO0p become active one count clock after generation of the INTTM0n output from the master channel. It becomes inactive when TCR0p = 0000H, and the counting operation is stopped. At the slave channel 2, the values of the TDR0q register are transferred to TCR0q regster, triggered by INTTM0n of the master channel, and the counter starts counting down. The output levels of TO0q become active one count clock after generation of the INTTM0n output from the master channel. It becomes inactive when TCR0q = 0000H, and the counting operation is stopped. After that, the above operation is repeated. TE0n, TE0p, TE0q = 0, and count operation stops. The TCR0n, TCR0p, and TCR0q registers hold count value and stop. The TO0p and TO0q output are not initialized but hold current status. The TO0p and TO0q pins output the TO0p and TO0q set levels. The TO0p and TO0q pin output levels are held by port function. Power-off status All circuits are initialized and SFR of each channel is also initialized. (The TO0p and TO0q bits are cleared to 0 and the TO0p and TO0q pins are set to port mode.) n: Channel number (n = 0, 2, 4) p: Slave channel number 1, q: Slave channel number 2 n < p < q 7 (Where p and q are a consecutive integer greater than n) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 278 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT 6.9 Cautions When Using Timer Array Unit 6.9.1 Cautions When Using Timer output Depends on products, a pin is assigned atimer output and other alternate functions. In this case, outputs of the other alternate functions must be set in initial status. (1) 20-, 24-pin products (a) Using TO02 output assigned to the P41 So that the alternated SO01/SDA01 output becomes 1, not only set the port mode register (the PM41 bit) and the port register (the P41 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE01 =. 0, SO01 = 1, SOE01 = 0). (b) Using TO03 output assigned to the P42 So that the alternated SCK01/SCL01 output becomes 1, not only set the port mode register (the PM42 bit) and the port register (the P17 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE01 = 0, SO01=1, SOE01=0). (2) 30-pin products (a) Using TO03 output assigned to the P31 So that the alternated PCLBUZ0 output becomes 0, not only set the port mode register (the PM31 bit) and the port register (the P31 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting 0 as the initial status. (b) Using TO07 output assigned to the P10 (When PIOR0 = 1) So that the alternated SCK00/SCL00 output becomes 1, not only set the port mode register (the PM10 bit) and the port register (the P10 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE00 = 0, SO00=1, SOE00=0). (c) Using TO06 output assigned to the P11 (When PIOR0 = 1) So that the alternated SDA00 output becomes 1, not only set the port mode register (the PM11 bit) and the port register (the P11 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE11 = 0, SO11=1, SOE11=0). (d) Using TO05 output assigned to the P12 (When PIOR0 = 1) So that the alternated SO00/TxD0 output becomes 1, not only set the port mode register (the PM12 bit) and the port register (the P12 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE12 = 0, SO12=1, SOE12=0). (e) Using TO04 output assigned to the P13 (When PIOR0 = 1) So that the alternated TxD2/SO20 output becomes 1, not only set the port mode register (the PM13 bit) and the port register (the P13 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE13 = 0, SO13=1, SOE13=0). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 279 RL78/G12 CHAPTER 6 TIMER ARRAY UNIT (f) Using TO03 output assigned to the P14 (When PIOR0 = 1) So that the alternated SDA20 output becomes 1, not only set the port mode register (the PM14 bit) and the port register (the P14 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE14 = 0, SO14=1, SOE14=0). (g) Using TO02 output assigned to the P15 (When PIOR0 = 1) So that the alternated SCK20/SCL20 output becomes 1, not only set the port mode register (the PM15 bit) and the port register (the P15 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE15 = 0, SO15=1, SOE15=0). And that the alternated PCLBUZ1 output becomes 1, but also use the bit 7 (PCLOE1) of clock output select register 1 (CKS1) with the same setting 0 as the initial status R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 280 RL78/G12 CHAPTER 7 INTERVAL TIMER CHAPTER 7 12-BIT INTERVAL TIMER 7.1 Functions of 12-bit Interval Timer An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP mode and triggering an A/D converter's SNOOZE mode. 7.2 Configuration of 12-bit Interval Timer The 12-bit interval timer includes the following hardware. Table 7-1. Configuration of 12-bit Interval Timer Item Configuration Counter 12-bit counter Control registers Peripheral enable register 0 (PER0) Operation speed mode control register (OSMC) Interval timer control register (ITMC) Figure 7-1. Block Diagram of 12-bit Interval Timer Clear Count clock f IL 12-bit counter Interrupt signal (INTIT) Match singnal WUTMM CK0 RINTE ITMCMP11 to ITMCMP0 Operation speed mode control register (OSMC) Interval timer control register (ITMC) Internal bus R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 281 RL78/G12 CHAPTER 7 INTERVAL TIMER 7.3 Registers Controlling 12-bit Interval Timer The 12-bit interval timer is controlled by the following registers. * Peripheral enable register 0 (PER0) * Operation speed mode control register (OSMC) * Interval timer control register (ITMC) 7.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the hardware that is not used is also stopped so as to decrease the power consumption and noise. When using the 12-bit interval timer, be sure to set bit 7 (TMKAEN) to 1 at first. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-2. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN TMKAEN 0 Control of clock (fIL) for register access of 12-bit interval timer Stops input clock supply. * SFR used by the 12-bit interval timer cannot be written. * The 12-bit interval timer is in the reset status. 1 Enables input clock supply. * SFR used by the 12-bit interval timer can be read and written. Cautions 1. When using the 12-bit interval timer, first set the TMKAEN bit to 1. If TMKAEN = 0, writing to a control register of the 12-bit interval timer is ignored, and, even if the register is read, only the default value is read. 2 Be sure to clear undefined bits to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 282 RL78/G12 CHAPTER 7 INTERVAL TIMER 7.3.2 Operation speed mode control register (OSMC) The WUTMMCK0 bit can be used to control supply of the 12-bit interval timer operation clock. The OSMC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 7-3. Format of Operation Speed Mode Control Register (OSMC) Address: F00F3H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 OSMC 0 0 0 WUTMMCK0 0 0 0 0 WUTMMCK0 Supply of operation clock for 12-bit interval timer 0 Clock supply stop. 1 Low-speed on-chip oscillator clock (fIL) supply R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 283 RL78/G12 CHAPTER 7 INTERVAL TIMER 7.3.3. Interval timer control register (ITMC) This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer compare value. The ITMC register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0FFFH. Figure 7-4. Format of Interval Timer Control Register (ITMC) Address: FFF90H After reset: 0FFFH R/W Symbol 15 14 13 12 11 to 0 ITMC RINTE 0 0 0 ITCMP11 to ITCMP0 RINTE 12-bit interval timer operation control 0 Count operation stopped (count clear) 1 Count operation started ITCMP11 to ITCMP0 001H * Specification of the 12-bit interval timer compare value These bits generate an interrupt at the fixed cycle (count clock cycles x (ITCMP setting + 1)). * * FFFH1 Example interrupt cycles when 001H or FFFH is specified for ITCMP11 to ITCMP0 * ITCMP11 to ITCMP0 = 001H, count clock: when fIL = 15 kHz 1/15 [kHz] x (1 + 1) / 0.1333 [ms] = 133.3 [s] * ITCMP11 to ITCMP0 = FFFH, count clock: when fIL = 15 kHz 1/15 [kHz] x (4095 + 1) / 273 [ms] Cautions 1. When RINTE bit is changed from 0 to 1, set WUTMMCK0 bit of OSMC register to 1 before the change so that the operation clock is established. 2. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the INTIT interrupt servicing. When operation starts (0 to 1) again, clear the TMKAIF flag, and then enable the interrupt servicing. 3. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit. 4. When setting the RINTE bit after returned from standby mode and entering standby mode again, confirm that the written value of the RINTE bit is reflected, or wait that more than one clock of the count clock has elapsed after returned from standby mode. Then enter standby mode. 5. Only change the setting of the ITCMP11 to ITCMP0 bits when RINTE = 0. However, it is possible to change the settings of the ITCMP11 to ITCMP0 bits at the same time as when changing RINTE from 0 to 1 or 1 to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 284 RL78/G12 CHAPTER 7 INTERVAL TIMER 7.4 12-bit Interval Timer Operation The count value specified for the ITCMP11 to ITCMP0 bits is used as an interval to operate an 12-bit interval timer that repeatedly generates interrupt requests (INTIT). When the RINTE bit is set to 1, the 12-bit counter starts counting. When the 12-bit counter value matches the value specified for the ITCMP11 to ITCMP0 bits, the 12-bit counter value is cleared to 0, counting continues, and an interrupt request signal (INTIT) is generated at the same time. The basic operation of the 12-bit interval timer is shown in Figure 7-5. Figure 7-5. 12-bit Interval Timer Operation Timing (ITCMP11 to ITCMP0 = 0FFH, count clock: fIL = 15 kHz) Count clock RINTE After RINTE is changed from 0 to 1, counting starts at the two fall of the count clock signal. 0FFH 12-bit counter 000H When RINTE is changed from 1 to 0, the 12-bit counter is cleared without synchronization with the count clock. ITCMP11 to ITCMP0 0FFH INTIT Period (17.06 ms) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 285 RL78/G12 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER. 8.1 Functions of Clock Output/Buzzer Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs. Buzzer output is a function to output a square wave of buzzer frequency. One pin can be used to output a clock or buzzer sound. The PCLBUZ0 or PCLBUZ1 pin outputs a clock selected by clock output select register 0, 1 (CKS0, CKS1). Figure 8-1 shows the block diagram of clock output/buzzer output controller. Figure 8-1. Block Diagram of Clock Output/Buzzer Output Controller Note The PCLBUZ0 or PCLBUZ1 pin can output a frequency, refer to 28.4 AC Characteristics. PCLBUZ1 output function is available only in 30-pin products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 286 RL78/G12 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.2 Configuration of Clock Output/Buzzer Output Controller The clock output/buzzer output controller includes the following hardware. Table 8-1. Configuration of Clock Output/Buzzer Output Controller Item Control registers Configuration Clock output select registers 0, 1 (CKS0, CKS1) Port mode register 1, 3 (PM1, PM3) Port register 1, 3 (P1, P3) 8.3 Registers Controlling Clock Output/Buzzer Output Controller The following two registers are used to control the clock output/buzzer output controller. * Clock output select registers 0, 1 (CKS0, CKS1) * Port mode register 1, 3 (PM1, PM3) 8.3.1 Clock output select registers 0, 1 (CKS0, CKS1) These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZ0 or PCLBUZ1), and set the output clock. Select the clock to be output from the PCLBUZ0 pin by using the CKS0 register. The CKS0 or CKS1 register are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 287 RL78/G12 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER Figure 8-2. Format of Clock Output Select Register n (CKSn) Address: FFFA5H (CKS0), FFFA6 (CKS1) After reset: 00H Symbol CKSn R/W <7> 6 5 4 3 2 1 0 PCLOEn 0 0 0 0 CCSn2 CCSn1 CCSn0 PCLOEn PCLBUZn pin output enable/disable specification 0 Output disable (default) 1 Output enable CCSn2 CCSn1 CCSn0 PCLBUZn pin output clock selection fMAIN (MHz) 5 0 0 0 fMAIN 5 MHz 10 16 Note 10 MHz 16 0 0 1 1 1 1 Note 0 1 1 0 0 1 1 1 0 1 0 1 0 1 fMAIN/2 2.5 MHz 5 MHz 24 MHz Setting 8 MHz Setting Not Note 0 20 Note Not prohibited prohibited e e 10 MHz 12 Note Note MHz fMAIN/2 2 1.25 MHz 2.5 MHz 4 MHz 5 MHz 6 MHz fMAIN/2 3 625 kHz 1.25 MHz 2 MHz 2.5 MHz 3 MHz fMAIN/2 4 312.5 kHz 625 kHz 1 MHz 1.25 MHz 1.5 MHz fMAIN/2 11 2.44 kHz 4.88 kHz 7.81 kHz 9.77 kHz 11.72 kHz fMAIN/2 12 1.22 kHz 2.44 kHz 3.91 kHz 4.88 kHz 5.86 kHz fMAIN/2 13 610 Hz 1.22 kHz 1.95 kHz 2.44 kHz 2.93 kHz Use the output clock within a range of 10 MHz. Furthermore, when using the output clock at 2.7 V VDD < 4.0 V, use it within 8 MHz. For detail, refer to 28.4 AC characteristics. Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0). 2. To shift to STOP mode, set PCLOEn = 0 before executing the STOP instruction. Remarks 1. n = 0, 1 2. fMAIN: Main system clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 288 RL78/G12 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.3.2 Port mode register 1, 3 (PM1, PM3) This register sets input/output of port 1, 3 in 1-bit units. When using the P10/PCLBUZ0 pin (20- and 24-pin products) or P15/PCLBUZ1, P31/PCLBUZ0 (30-pin products) for clock output and buzzer output, clear PM10, PM15, or PM31 bits and the output latches of P10, P15, or P31 to 0. And the 20- and 24-pin products, set 0 to PMC10 bit for port mode control register 1. The PM1. PM3 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 8-3. Format of Port Mode Register 1, 3 (PM1, PM3) 20-, 24-pin product Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W 30-pin product PMmn Pmn pin I/O mode selection (mn = 10 to 17, 30 or 31) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 289 RL78/G12 CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER 8.4 Operations of Clock Output/Buzzer Output Controller One pin can be used to output a clock or buzzer sound. The PCLBUZ0 pin outputs a clock/buzzer selected by the clock output select register 0 (CKS0). The PCLBUZ1 pin outputs a clock/buzzer selected by the clock output select register 1 (CKS1). 8.4.1 Operation as output pin The PCLBUZn pin is output as the following procedure. <1> Select the output frequency with bits 0 to 3 (CCSn0 to CCSn2, CSELn) of the clock output select register (CKSn) of the PCLBUZn pin (output in disabled). <2> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output. Remarks 1. The controller used for outputting the clock starts or stops outputting the clock one clock after enabling or disabling clock output (PCLOEn bit) is switched. At this time, pulses with a narrow width are not output. Figure 8-5 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock. 2. n = 0 or 1 Figure 8-5. Remote Control Output Application Example PCLOEn 1 clock elapsed Clock output Narrow pulses are not recognized Caution After specifying the setting for stopping PCLBUZn output (PCLOEn = 0), if the STOP or HALT instruction is executed at high-level output, the clock width may be shorter than the selected value. Execute the STOP or HALT instruction only when 1.5 clocks of the selected clock or more elapse after specifying the setting for stopping PCLBUZn output. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 290 RL78/G12 CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer operates on the low-speed on-chip oscillator clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases. * If the watchdog timer counter overflows * If a 1-bit manipulation instruction is executed on the watchdog timer enable register (WDTE) * If data other than "ACH" is written to the WDTE register * If data is written to the WDTE register during a window close period When a reset occurs due to the watchdog timer, bit 4 (WDTRF) of the reset control flag register (RESF) is set to 1. For details of the RESF register, see CHAPTER 18 RESET FUNCTION. When 75%+1/2fIL of the overflow time is reached, an interval interrupt can be generated. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 291 RL78/G12 CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, window open period, and interval interrupt are set by the option byte. Table 9-2. Setting of Option Bytes and Watchdog Timer Setting of Watchdog Timer Option Byte (000C0H) Watchdog timer interval interrupt Bit 7 (WDTINT) Window open period Bits 6 and 5 (WINDOW1, WINDOW0) Controlling counter operation of watchdog timer Bit 4 (WDTON) Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0) Controlling counter operation of watchdog timer Bit 0 (WDSTBYON) (in HALT/STOP mode) Remark For the option byte, see CHAPTER 23 OPTION BYTE. Figure 9-1. Block Diagram of Watchdog Timer WDTINT of option byte (000C0H) Interval time controller (Count value overflow time x 3/4) Interval interrupt request WDCS2 to WDCS0 of option byte (000C0H) fIL Clock input controller 17-bit counter fIL/26 to fIL/216 Selector Reset output controller Count clear signal WINDOW1 and WINDOW0 of option byte (000C0H) WDTON of option byte (000C0H) Overflow signal Internal reset signal Window size decision signal Window size check Watchdog timer enable register (WDTE) Write detector to WDTE except ACH Internal bus R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 292 RL78/G12 CHAPTER 9 WATCHDOG TIMER 9.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). 9.3.1 Watchdog timer enable register (WDTE) Writing "ACH" to the WDTE register clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1AH or 9AHNote. Figure 9-2. Format of Watchdog Timer Enable Register (WDTE) Address: FFFABH Symbol After reset: 1AH/9AHNote R/W 7 6 5 4 3 2 1 0 WDTE Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte (000C0H). To operate watchdog timer, set the WDTON bit to 1. WDTON Bit Setting Value WDTE Register Reset Value 0 (watchdog timer count operation disabled) 1AH 1 (watchdog timer count operation enabled) 9AH Cautions 1. If a value other than "ACH" is written to the WDTE register, an internal reset signal is generated. 2. If a 1-bit memory manipulation instruction is executed for the WDTE register, an internal reset signal is generated. 3. The value read from the WDTE register is 1AH/9AH (this differs from the written value (ACH)). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 293 RL78/G12 CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer <1> When the watchdog timer is used, its operation is specified by the option byte (000C0H). * Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (000C0H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 23). WDTON Watchdog Timer Counter 0 Counter operation disabled (counting stopped after reset) 1 Counter operation enabled (counting started after reset) * Set an overflow time by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H) (for details, see 9.4.2 and CHAPTER 23). * Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for details, see 9.4.3 and CHAPTER 23). <2> After a reset release, the watchdog timer starts counting. <3> By writing "ACH" to the watchdog timer enable register (WDTE) after the watchdog timer starts counting and before the overflow time set by the option byte, the watchdog timer is cleared and starts counting again. <4> After that, write the WDTE register the second time or later after a reset release during the window open period. If the WDTE register is written during a window close period, an internal reset signal is generated. <5> If the overflow time expires without "ACH" written to the WDTE register, an internal reset signal is generated. An internal reset signal is generated in the following cases. * If a 1-bit manipulation instruction is executed on the WDTE register * If data other than "ACH" is written to the WDTE register Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. 2. If the watchdog timer is cleared by writing "ACH" to the WDTE register, the actual overflow time may be different from the overflow time set by the option byte by up to 2/fIL seconds. 3. The watchdog timer can be cleared immediately before the count value overflows. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 294 RL78/G12 CHAPTER 9 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes, and SNOOZE mode differs as follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H). WDSTBYON = 0 : Watchdog timer operation stops. WDSTBYON = 1 : Watchdog timer operation continues. If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is released. At this time, the counter is cleared to 0 and counting starts. When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt. 9.4.2 Setting overflow time of watchdog timer Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H). If an overflow occurs, an internal reset signal is generated. The present count is cleared and the watchdog timer starts counting again by writing "ACH" to the watchdog timer enable register (WDTE) during the window open period before the overflow time. The following overflow times can be set. Table 9-3. Setting of Overflow Time of Watchdog Timer WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer (fIL = 17.25 kHz (MAX.)) Remark 6 0 0 0 2 /fIL (3.71 ms) 0 0 1 2 /fIL (7.42 ms) 0 1 0 2 /fIL (14.84 ms) 0 1 1 2 /fIL (29.68 ms) 1 0 0 2 /fIL (118.72 ms) 1 0 1 2 /fIL (474.90 ms) 1 1 0 2 /fIL (949.80 ms) 1 1 1 2 /fIL (3799.19 ms) 7 8 9 11 13 14 16 fIL: Low-speed on-chip oscillator clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 295 RL78/G12 CHAPTER 9 WATCHDOG TIMER 9.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (000C0H). The outline of the window is as follows. * If "ACH" is written to the watchdog timer enable register (WDTE) during the window open period, the watchdog timer is cleared and starts counting again. * Even if "ACH" is written to the WDTE register during the window close period, an abnormality is detected and an internal reset signal is generated. Example: If the window open period is 50% Counting starts Overflow time Window close period (50%) Window close period (50%) Internal reset signal is generated if "ACH" is written to WDTE. Counting starts again when "ACH" is written to WDTE. Caution When data is written to the WDTE register for the first time after reset release, the watchdog timer is cleared in any timing regardless of the window open time, as long as the register is written before the overflow time, and the watchdog timer starts counting again. The window open period can be set is as follows. Table 9-4. Setting Window Open Period of Watchdog Timer Caution WINDOW1 WINDOW0 Window Open Period of Watchdog Timer 0 0 Setting prohibited 0 1 50% 1 0 75% 1 1 100% When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100% regardless of the values of the WINDOW1 and WINDOW0 bits. Remark 9 If the overflow time is set to 2 /fIL, the window close time and open time are as follows. Setting of Window Open Period 50% 75% 100% Window close time 0 to 20.08 ms 0 to 10.04 ms None Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms Example: When window open period is 50% * Overflow time: 9 9 2 /fIL (MAX.) = 2 /17.25 kHz (MAX.) = 29.68 ms * Window close time: 9 9 0 to 2 /fIL (MIN.) x (1 - 0.5) = 0 to 2 /12.75 kHz x 0.5 = 0 to 20.08 ms * Window open time: 9 9 9 9 2 /fIL (MIN.) x (1 - 0.5) to 2 /fIL (MAX.) = 2 /12.75 kHz x 0.5 to 2 /17.25 kHz = 20.08 to 29.68 ms R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 296 RL78/G12 CHAPTER 9 WATCHDOG TIMER 9.4.4 Setting watchdog timer interval interrupt Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be generated when 75% + 1/2 fIL of the overflow time is reached. Table 9-5. Setting of Watchdog Timer Interval Interrupt WDTINT Use of Watchdog Timer Interval Interrupt 0 Interval interrupt is used. 1 Interval interrupt is generated when 75% + 1/2 fIL of overflow time is reached. Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts operating after the oscillation stabilization time has elapsed. Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an overflow occurs during the oscillation stabilization time, causing a reset. Consequently, set the overflow time in consideration of the oscillation stabilization time when operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP mode release by an interval interrupt. Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the watchdog timer enable register (WDTE)). If ACH is not written to the WDTE register before the overflow time, an internal reset signal is generated. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 297 RL78/G12 CHAPTER 10 A/D CONVERTER CHAPTER 10 A/D CONVERTER 10.1 Function of A/D Converter Note The A/D converter is a 10-bit resolution converter that converts analog input signals into digital values, and is configured to control analog inputs, including up to 11 channels of A/D converter analog inputs (ANI0 to ANI3 and ANI16 to ANI22). The A/D converter has the following function. * 10-bit resolution A/D conversionNote 10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI3 and ANI16 to ANI22 (ANI0 to ANI3, ANI16 to ANI19 for 30-pin products). Each time an A/D conversion operation ends, an interrupt request (INTAD) is generated (when in the select mode). Note 8-bit resolution can also be selected by using the ADTYP bit of A/D converter mode register 2 (ADM2). Various A/D conversion modes can be specified by using the mode combinations below. Trigger Mode * Software trigger Channel Selection Mode * Select mode Conversion Operation Mode * One-shot conversion mode Conversion is started by specifying a A/D conversion is performed on A/D conversion is performed on software trigger. the analog input of one channel. the selected channel once. * Hardware trigger no-wait mode * Scan mode * Sequential conversion mode Conversion is started by detecting a A/D conversion is performed on A/D conversion is sequentially hardware trigger. the analog input of four channels performed on the selected in order. channels until it is stopped by * Hardware trigger wait mode The power is turned on by detecting a software. hardware trigger while the system is off and in the conversion standby state, and conversion is then started automatically after the stabilization wait time passes. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 298 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 ANI16 ANI17 ANI18 ANI19 ANI20Note ANI21Note ANI22Note ADS4 ADS3 ADS1 ADS0 Analog input channel specification register (ADS) ADS2 5 3 A/D converter mode register 1 (ADM1) ADMD Internal bus ADCS Controller FR2 Successive approximation register (SAR) ADTMD1 ADTMD0 ADSCM ADTRS1 ADTRS0 ADTYP VSS FR1 FR0 LV0 ADREFM bit ADCE A/D converter mode register 0 (ADM0) LV1 Comparison voltage generator A/D conversion result register (ADCR) INTAD Timer trigger signal (INTIT) Timer trigger signal (INTTM01) A/D conversion result upper limit/lower limit comparator VSS AVREFM/ANI1/P21 Internal reference voltage (1.45 V) VDD AVREFP/ANI0/P20 ADREFP1 and ADREFP0 bits ADCS bit 6 Conversion result comparison lower limit setting register (ADLL) Internal bus A/D voltage comparator Conversion result comparison upper limit setting register (ADUL) Sample & hold circuit ADREFP1 ADREFP0 ADREFPM ADRCK AWC 2 ADTES1 ADTES0 A/D converter mode register 2 (ADM2) Note Provided in only 20- or 24-pin products. ADISS 6 Internal reference voltage (1.45 V) Temperature sensor ANI0/AVREFP/P20 ANI1/AVREFM/P21 ANI2/P22 ANI3/P23 Digital port control 3 ADPC2 ADPC1 ADPC0 Selector A/D test register (ADTES) Selector A/D port configuration register (ADPC) Selector Figure 10-1. Block Diagram of A/D Converter RL78/G12 CHAPTER 10 A/D CONVERTER 299 RL78/G12 CHAPTER 10 A/D CONVERTER 10.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI3 and ANI16 to ANI22 pins These are the analog input pins of the 11 channels of the A/D converter. For 30-pin products, these are analog input pins of the 8 channels of ANI0 to ANI3 or ANI16 to ANI19 pins. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. (2) Sample & hold circuit The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D conversion. (3) A/D voltage comparator This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage generator with the analog input voltage. If the analog input voltage is found to be greater than the reference voltage (1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register (SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is reset. After that, bit 8 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the comparison voltage generator is selected by the value of bit 9, to which the result has been already set. Bit 9 = 0: (1/4 AVREF) Bit 9 = 1: (3/4 AVREF) The voltage tap of the comparison voltage generator and the analog input voltage are compared and bit 8 of the SAR register is manipulated according to the result of the comparison. Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 1 Analog input voltage Voltage tap of comparison voltage generator: Bit 8 = 0 Comparison is continued like this to bit 0 of the SAR register. When performing A/D conversion at a resolution of 8 bits, the comparison continues until bit 2 of the SAR register. Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. (4) Comparison voltage generator The comparison voltage generator generates the comparison voltage input from an analog input pin. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 300 RL78/G12 CHAPTER 10 A/D CONVERTER (5) Successive approximation register (SAR) The SAR register is a register that sets voltage tap data whose values from the comparison voltage generator match the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified A/D conversion operations have ended, an A/D conversion end interrupt request signal (INTAD) is generated. (6) 10-bit A/D conversion result register (ADCR) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lower 6 bits are fixed to 0). (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. (8) Controller This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller generates INTAD. (9) AVREFP pin This pin inputs an external reference voltage (AVREFP). If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D converter mode register 2 (ADM2) to 1. The analog signals input to ANI3 to ANI10 and ANI16 to ANI22 are converted to digital signals based on the voltage applied between AVREFP and the - side reference voltage (AVREFM/VSS). In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference voltage of the A/D converter. (10) AVREFM pin This pin inputs an external reference voltage (AVREFM). If using AVREFM as the - side reference voltage of the A/D converter, set the ADREFM bit of the ADM2 register to 1. In addition to AVREFM, it is possible to select VSS as the - side reference voltage of the A/D converter. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 301 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3 Registers Used in A/D Converter The A/D converter uses the following registers. * Peripheral enable register 0 (PER0) * A/D converter mode register 0 (ADM0) * A/D converter mode register 1 (ADM1) * A/D converter mode register 2 (ADM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Analog input channel specification register (ADS) * Conversion result comparison upper limit setting register (ADUL) * Conversion result comparison lower limit setting register (ADLL) * A/D test register (ADTES) * A/D port configuration register (ADPC) * Port mode control registers 0, 1, 4, 12, 14 (PMC0, PMC1, PMC4, PMC12, PMC14) * Port mode registers 0, 1, 2, 4, 12, 14 (PM0, PM1, PM2, PM4, PM12, PM14) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 302 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-2. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN ADCEN 0 Control of A/D converter input clock supply Stops input clock supply. * SFR used by the A/D converter cannot be written. * The A/D converter is in the reset status. 1 Enables input clock supply. * SFR used by the A/D converter can be read/written. <R> Cautions 1. When setting the A/D converter, be sure to set the following registers first while the ADCEN bit is set to 1. If ADCEN = 0, writing to a control register of the A/D converter is ignored, and, even if the register is read, only the default value is read (except for port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12, and PM14), port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14), and A/D port configuration register (ADPC)). * A/D converter mode register 0 (ADM0) * A/D converter mode register 1 (ADM1) * A/D converter mode register 2 (ADM2) * 10-bit A/D conversion result register (ADCR) * 8-bit A/D conversion result register (ADCRH) * Analog input channel specification register (ADS) * Conversion result comparison upper limit setting register (ADUL) * Conversion result comparison lower limit setting register (ADLL) * A/D test register (ADTES). 2. Be sure to clear the undefined bits to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 303 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.2 A/D converter mode register 0 (ADM0) This register sets the conversion time for analog input to be A/D converted, and starts/stops conversion. The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-3. Format of A/D Converter Mode Register 0 (ADM0) Address: FFF30H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> ADM0 ADCS ADMD FR2Note 1 FR1Note 1 FR0Note 1 LV1Note 1 LV0Note 1 ADCE ADCS 0 A/D conversion operation control Stops conversion operation [When read] Conversion stopped/standby status 1 Enables conversion operation [When read] While in the software trigger mode: Conversion operation status While in the hardware trigger wait mode: Stabilization wait status + conversion operation status ADMD Specification of the A/D conversion channel selection mode 0 Select mode 1 Scan mode A/D voltage comparator operation controlNote 2 ADCE 0 Stops A/D voltage comparator operation 1 Enables A/D voltage comparator operation Notes 1. For details of the FR2 to FR0, LV1, LV0 bits, and A/D conversion, see Table 10-3 A/D Conversion Time 2. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage Selection. comparator is controlled by the ADCS and ADCE bits, and it takes 1 s from the start of operation for the operation to stabilize. Therefore, when the ADCS bit is set to 1 after 1 s or more has elapsed from the time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result. Otherwise, ignore data of the first conversion. <R> Cautions 1. Change the ADMD, FR2 to FR0, LV1 and LV0 bits while conversion is stopped (ADCS = 0, ADCE = 0). <R> 2. The setting combination of the ADCS bit to 1 and the ADCE bit to 0 is prohibited. 3. Do not change the ADCS and ADCE bits from 0 to 1 at the same time by using an 8-bit manipulation instruction. Be sure to set these bits in the order described in 10.7 A/D Converter Setup Flowchart. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 304 RL78/G12 CHAPTER 10 A/D CONVERTER Table 10-1. Settings of ADCS and ADCE Bits <R> ADCS ADCE A/D Conversion Operation 0 0 Conversion stopped state 0 1 Conversion standby state 1 0 Setting prohibited 1 1 Conversion-in-progress state Note In hardware trigger wait mode, there is no DC power consumption path even during conversion standby mode. Table 10-2. Setting and Clearing Conditions for ADCS Bit A/D Conversion Mode Software Select mode trigger Set Conditions Sequential conversion When 1 is mode written to ADCS Clear Conditions When 0 is written to ADCS One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when A/D conversion ends. Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when conversion ends on the specified four channels. Hardware Select mode Sequential conversion trigger no-wait mode mode One-shot conversion When 0 is written to ADCS When 0 is written to ADCS mode Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion When 0 is written to ADCS mode Hardware Sequential conversion When a trigger wait mode hardware trigger mode One-shot conversion is input Select mode mode When 0 is written to ADCS * When 0 is written to ADCS * The bit is automatically cleared to 0 when A/D conversion ends. Scan mode Sequential conversion When 0 is written to ADCS mode One-shot conversion * When 0 is written to ADCS mode * The bit is automatically cleared to 0 when conversion ends on the specified four channels. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 305 RL78/G12 CHAPTER 10 A/D CONVERTER Figure 10-4. Timing Chart When A/D Voltage Comparator Is Used A/D voltage comparator: enables operation ADCE A/D voltage comparator Conversion start time Note 2 Conversion Conversion operation standby Conversion stopped 0 is written to ADCS. Conversion start time Note 2 Conversion Conversion operation standby Conversion stopped Hardware trigger detection 0 is written 1 is written to ADCS. to ADCS. Conversion start time Note 2 A/D power supply stabilization wait Note 2 Conversion Conversion Conversion standby operation standby Conversion stopped Conversion standby Software trigger mode ADCS Note 1 1 is written to ADCS. Conversion standby Hardware trigger no-wait mode ADCS Hardware trigger wait mode Trigger standby Note 1 ADCS Hardware trigger detection Notes 1. 0 is written to ADCS. While in the software trigger mode or hardware trigger no-wait mode, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 s or longer to stabilize the internal circuit. 2. In starting conversion, the longer will take up to following time ADM0 Conversion FR2 FR1 FR0 Clock (fAD) Conversion Start Time (Number of fCLK Clock) Software Trigger Mode/ Hardware Trigger Wait Mode Hardware Trigger No-wait Mode 0 0 0 fCLK/64 63 0 0 1 fCLK/32 31 0 1 0 fCLK/16 15 0 1 1 fCLK/8 7 1 0 0 fCLK/6 5 1 0 1 fCLK/5 4 1 1 0 fCLK/4 3 1 1 1 fCLK/2 1 Remark 1 fCLK: CPU / Peripheral hardware clock frequency However, for the second and subsequent conversion in sequential conversion mode or scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 306 RL78/G12 CHAPTER 10 A/D CONVERTER Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is automatically switched to 1 when the hardware trigger signal is detected). However, it is possible to clear the ADCS bit to 0 to specify the A/D conversion standby status. 2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained. 3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion stopped/conversion standby status). 4. To complete A/D conversion, specify at least the following time as the hardware trigger interval: Hardware trigger no wait mode: 2 fCLK clock + A/D conversion time Hardware trigger wait mode: 2 fCLK clock + stabilization wait time + A/D conversion time R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 307 RL78/G12 CHAPTER 10 A/D CONVERTER Table 10-3. A/D Conversion Time Selection (1/4) (1) Normal Mode 2.7 V VDD 5.5 V When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) <R> A/D Converter Mode Mode Conversion Number of Register 0 (ADM0) Clock (fAD) Conversion 0 1 0 0 Normal fCLK/32 1 0 0 1 1 0 608/fCLK fCLK/8 sampling clock : 7 fCLK = fCLK = fCLK = fCLK = fCLK = fCLK = 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 24 MHz Setting 304/fCLK 76 s 38 s 25.33 s 76 s 38 s 19 s 12.67 s 19 s 9.5 s 6.33 s Setting 152/fCLK 76 s 38 s 57 s 28.5 s 14.25 s 7.125 s 4.75 s fAD) 1 0 0 fCLK/6 114/fCLK 1 0 1 fCLK/5 95/fCLK 95 s 47.5 s 23.75 s 11.875 s 5.938 s 3.96 s 1 1 0 fCLK/4 76/fCLK 76 s 38 s 19 s 9.5 s 4.75 s 3.17 s 38 s 19 s 9.5 s 4.75 s 2.375 s Setting 1 0 1 0 fCLK/2 1 1 0 1 Normal fCLK/32 2 38/fCLK 17fAD 544/fCLK 0 1 0 fCLK/16 0 1 1 fCLK/8 sampling clock : 5 Setting Setting Setting 68 s Notes 1, 2 Note 1 prohibited 34 s 22.67 s prohibited prohibited prohibited (Number of 68 s 34 s 17 s 11.33 s 136/fCLK 68 s 34 s 17 s 8.5 s 5.67 s 51 s 25.5 s 12.75 s 6.375 s 4.25 s 272/fCLK fAD) 1 0 0 fCLK/6 102/fCLK 1 0 1 fCLK/5 85/fCLK 85 s 42.5 s 21.25 s 10.625 s 5.3125 s 3.54 s 1 1 0 fCLK/4 68/fCLK 68 s 34 s 17 s 8.5 s 34 s 17 s 8.5 s 4.25 s 1 1 fCLK/2 1 Other than the above Notes 1. - 34/fCLK - - 4.25 s 2.83 s 2.125 s Setting Notes 1, 2 Notes 1, 2 prohibited Setting prohibited Setting prohibited in the VDD < 3.6 V 2. This value is prohibited when using the temperature sensor 3. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution <R> <R> Setting prohibited prohibited prohibited (Number of fCLK/16 1 19 fAD Conversion Time Selection Time Clock FR2 FR1 FR0 LV1 LV0 0 Conversion is selected, the values are shorter by two cycles of the conversion clock (fAD) Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D conversion once (ADCS = 0) beforehand. 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 308 RL78/G12 CHAPTER 10 A/D CONVERTER Table 10-3. A/D Conversion Time Selection (2/4) (2) Low voltage ModeNote 1 When there is no stabilization wait time (software trigger mode/hardware trigger no-wait mode) <R> A/D Converter Mode Register 0 (ADM0) Mode Conversion Number of Conversion Time Clock (fAD) Conversion Clock FR2 FR1 FR0 LV1 LV0 0 0 1 Low 0 fCLK/32 voltage 0 1 0 0 1 1 1 19 fAD 608/fCLK (Number of fCLK/16 sampling 304/fCLK fCLK/8 clock : 7 152/fCLK Conversion Time Selection 1.8 V VDD 5.5 V Note 2 fCLK = fCLK = fCLK = fCLK = fCLK = fCLK = 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 24 MHz Setting Setting Setting 76 s prohibited prohibited prohibited 76 s 38 s 76 s 38 s 19 s 57 s 28.5 s 14.25 s 95 s 47.5 s 23.75 s 11.875 s 76 s 38 s 19 s 38 s 19 s fAD) 1 1 1 1 0 0 0 0 fCLK/6 1 1 0 1 1 1 0 0 1 1 76/fCLK 38/fCLK fCLK/2 1 Low 1 fCLK/32 voltage 0 95/fCLK fCLK/4 1 0 114/fCLK fCLK/5 2 17 fAD 544/fCLK (Number of fCLK/16 sampling 272/fCLK fCLK/8 clock : 5 136/fCLK Note 4 Note 4 9.5 s Note 4 9.5 s 1 1 1 0 0 0 fCLK/6 1 1 fCLK/5 0 1 fCLK/4 1 68/fCLK fCLK/2 Other than the above Notes 1. 85/fCLK - 34/fCLK - - 9.5 s 6.33 s 7.125s 4.75 s 5.938 s 3.96 s Note 4 Note 4 Note 4 4.75 s 2.375s Note 5 Setting prohibited 34 s 22.667 s 17 s 11.333 s 8.5 s 5.667 s 6.375 s 4.25 s 5.313 s 3.542 s 4.25 s 2.833 s 2.125 s Setting prohibited Note 4 68 s 34 s 17 s 51 s 25.5 s 12.75 s Note 4 85 s 42.5 s 21.25 s 10.625 s 68 s 34 s 34 s 17 s Note 4 8.5 s 12.67 s 3.17 s 34 s Note 4 19 s 4.75 s 68 s 17 s 25.33 s Note 4 Setting Setting Setting 68 s prohibited prohibited prohibited 102/fCLK 38 s Note 4 fAD) 1 Note 3 8.5 s Note 4 4.25 s Note 4 Note 4 Note 4 Note 4 Note 4 Note 5 Note 5 Note 5 Setting prohibited This mode is prohibited when using the temperature sensor 2. 2.4 V VDD 5.5 V 3. 2.7 V VDD 5.5 V 4. Setting prohibited in the VDD < 2.7 V 5. Setting prohibited in the VDD < 3.6 V 6. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is <R> <R> selected, the values are shorter by two cycles of the conversion clock (fAD). Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D conversion once (ADCS = 0) beforehand. 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 309 RL78/G12 CHAPTER 10 A/D CONVERTER Table 10-3. A/D Conversion Time Selection (3/4) (3) Normal Mode 2.7 V VDD 5.5 V <R> When there is stabilization wait time (hardware trigger wait mode) A/D Converter Mode Register 0 (ADM0) Mode Conversion Number of Number of Stabilization Clock Stabilization Conversion Wait Time + (fAD) FR2 FR1 FR0 LV1 LV0 Wait Clock Clock Conversion Time 0 0 1 0 0 Normal fCLK/32 8 fAD 1 19 fAD 864/fCLK (Number of Stabilization Wait Time + Conversion Time Selection fCLK = fCLK = fCLK = fCLK = fCLK = fCLK = 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 24 MHz 108 s 54 s 36 s 108 s 54 s 27 s 18 s 9 s Setting Setting Setting prohibited prohibited prohibited 0 1 0 fCLK/16 sampling 432/fCLK 0 1 1 fCLK/8 clock : 7 216/fCLK 108 s 54 s 27 s 13.5 s fAD) 162/fCLK 81 s 40.5 s 20.25 s 10.125 s 6.75 s 1 0 0 fCLK/6 1 0 1 fCLK/5 135/fCLK 135 s 67.5 s 33.75 s 16.875 s 8.438 s 5.625 s 1 1 0 fCLK/4 108/fCLK 108 s 54 s 27 s 13.5 s 6.75 s 4.5 s 54 s 27 s 13.5 s 6.75 s 3.375 s Setting prohibited Setting Setting Setting prohibited prohibited prohibited 100 s 50 s 100 s 50 s 25 s 16.67 s 1 0 1 0 fCLK/2 1 1 0 54/fCLK 1 Normal fCLK/32 17 fAD 2 800/fCLK (Number of Notes 2, 3 Note 2 33.33 s 0 1 0 fCLK/16 sampling 400/fCLK 0 1 1 fCLK/8 clock : 5 200/fCLK 100 s 50 s 25 s 12.5 s 8.33 s fAD) 150/fCLK 75 s 37.5 s 18.75 s 9.375 s 6.25 s 1 0 0 fCLK/6 1 0 1 fCLK/5 125/fCLK 125 s 62.5 s 31.25 s 15.625 s 7.8125 s 5.21 s 1 1 0 fCLK/4 100/fCLK 100 s 50 s 25 s 12.5 s 6.25 s 4.17 s 50 s 25 s 12.5 s 6.25 s 3.125 s Setting prohibited 1 1 1 Other than the above Notes 1. 50/fCLK fCLK/2 - - - - Notes 2, 3 Notes 2, 3 Setting prohibited For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 10-3 (1/4)). <R> 2. Setting prohibited in the VDD < 3.6 V 3. This value is prohibited when using the temperature sensor 4 These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is selected, the values are shorter by two cycles of the conversion clock (fAD). <R> Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D conversion once (ADCS = 0) beforehand. 2. The above conversion time does not include conversion state time. Conversion state time add in the first conversion. Select conversion time, taking clock frequency errors into consideration. 3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for stabilization after the hardware trigger is detected. Remark fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 310 RL78/G12 CHAPTER 10 A/D CONVERTER Table 10-3. A/D Conversion Time Selection (4/4) (4) Low voltage ModeNote 1 When there is stabilization wait time Note 2 (hardware trigger wait mode) <R> A/D Converter Mode Mode Conversion Number of Number of Stabilization Register 0 (ADM0) Clock (fAD) FR2 FR1 FR0 LV1 LV0 0 0 1 1 0 wait clock fCLK/32 2 fAD voltage 0 1 0 0 1 1 Clock Conversion Time Low 1 Stabilization Wait Time + Conversion Time Selection stabilization Conversion Wait Time + 19 fAD 672/fCLK (Number of fCLK/16 sampling 336/fCLK fCLK/8 clock :7 168/fCLK 1.8 V VDD 5.5 V Note3 fCLK = fCLK = fCLK = fCLK = fCLK = fCLK = 1 MHz 2 MHz 4 MHz 8 MHz 16 MHz 24 MHz 84 s 42 s 28 s 84 s 42 s 21 s 14 s 84 s 42 s 21 s 10.5 s 7 s 63 s 31.25 s 15.75 s 7.875 s 5.25 s 105 s 52.5 s 26.25 s 13.125s 6.563 s 4.38 s 84 s 42 s 21 s 42 s 21 s Setting Setting Setting prohibited prohibited prohibited fAD) 1 1 1 1 0 0 0 1 1 0 0 fCLK/6 1 0 105/fCLK fCLK/4 1 1 126/fCLK fCLK/5 84/fCLK 42/fCLK fCLK/2 1 1 Low fCLK/32 17 fAD voltage 0 0 1 1 0 2 1 608/fCLK (Number of fCLK/16 sampling clock :5 fCLK/8 10.5 s Note 5 Setting Setting Setting prohibited prohibited prohibited 76 s 304/fCLK Note 5 Note 5 10.5 s 1 1 1 0 0 1 1 0 fCLK/6 1 fCLK/5 0 fCLK/4 Other than the above <R> <R> 3. 4. 5. 6. 7. Cautions Remark 76/fCLK fCLK/2 1 Notes 1. 2. 95/fCLK - 38/fCLK - - - 3.5 s 2.625 s Note 6 Setting prohibited 76 s 38s 25.33 s 38 s 19s 57 s 28.5 s 14.25s 95 s 47.5 s 23.75 s 76 s 38 s 19 s 38 s 19 s 9.5 s 5.25 s 5.25 s Note 5 19s Note 5 Note 5 Note 6 38 s 114/fCLK Note 5 Note 5 76 s 152/fCLK Note 5 Note 5 fAD) 1 Note4 9.5 s 12.67 s Note 5 6.33 s Note 5 Note 5 7.125 s 4.75 s 11.875 s 5.938 s 3.96 s 9.5 s 4.75s Note 5 Note 6 4.75s 2.375 s Setting prohibited Note 5 Note 5 Note 5 Note 5 Note 6 3.17 s Setting prohibited This mode is prohibited when using the temperature sensor For the second and subsequent conversion in sequential conversion mode and for conversion of the channel specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabilization wait time for A/D power supply do not occur after a hardware trigger is detected (see table 10-3 (2/4)). 2.4 V VDD 5.5 V 2.7 V VDD 5.5 V Setting prohibited in the VDD < 2.7 V Setting prohibited in the VDD < 3.6 V These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is selected, the values are shorter by two cycles of the conversion clock (fAD). 1. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the current data while conversion is stopped (ADCS = 0, ADCE = 0). 2. The above conversion time does not include conversion state time. Conversion state time add in the sfirst conversion. Select conversion time, taking clock frequency errors into consideration. 3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for stabilization after the hardware trigger is detected. fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 311 RL78/G12 CHAPTER 10 A/D CONVERTER Figure 10-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode) ADCS 1 or ADS rewrite ADCS Sampling timing INTAD SAR clear Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Sampling Conversion time 10.3.3 A/D converter mode register 1 (ADM1) This register is used to specify the A/D conversion trigger, conversion mode, and hardware trigger signal. The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-6. Format of A/D Converter Mode Register 1 (ADM1) Address: FFF32H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADM1 ADTMD1 ADTMD0 ADCSM 0 0 0 ADTRS1 ADTRS0 ADTMD1 ADTMD0 0 x Software trigger mode 1 0 Hardware trigger no- wait mode 1 1 Hardware trigger wait mode Selection of the A/D conversion trigger mode ADSCM Specification of the A/D conversion mode 0 Sequential conversion mode 1 One-shot conversion mode ADTRS1 ADTRS0 0 0 Count completion of timer channel 1 or capture completion interrupt signal (INTTM01) 1 1 12-bit interval timer interrupt signal (INTIT) Other than above <R> Selection of the hardware trigger signal Settig prohibited Cautions 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0). 2. For the trigger interval in the hardware trigger wait mode, specify at least (2 fCLK clock + stabilization wait time + A/D conversion time) (Refer to Table 10-3). 3. In modes other than SNOOZE mode, input of the next INTRTC or INTIT will not be recognized as a valid hardware trigger for up to four fCLK cycles after the first INTRTC or INTIT is input. Remark x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 312 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.4 A/D converter mode register 2 (ADM2) This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D conversion result values, select the resolution, and specify whether to use the wakeup function (SNOOZE mode). The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) (1/2) Address: F0010H After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP ADREFP1 ADREFP0 0 0 Selection of the + side reference voltage source of the A/D converter Supplied from VDD 0 1 Supplied from P20/AVREFP/ANI0 1 0 Supplied from the internal reference voltage (1.45 V) (Can be used only in HS (highspeed main) mode) 1 1 Setting prohibited * When ADREFP1 or ADREFP0 bit is rewritten, this must be configured in accordance with the following procedures. (1) Set ADCE = 0 (2) Change the values of ADREFP1 and ADREFP0 (3) Stabilization wait time (A) (4) Set ADCE = 1 (5) Stabilization wait time (B) When ADREFP1 and ADREFP0 are set to 1 and 0, the setting is changed to A = 5 s, B = 1 s. When ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1, A needs no wait and B = 1 s. After wait of (5), start A/D conversion * When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the temperature sensor output and internal reference voltage output. Be sure to perform A/D conversion while ADISS = 0. Selection of the - side reference voltage source of the A/D converter ADREFM 0 Supplied from VSS 1 Supplied from P21/AVREFM/ANI1 ADRCK Checking the upper limit and lower limit conversion result values 0 The interrupt signal (INTAD) is output when the ADLL register the ADCR register the ADUL register (<1>). 1 The interrupt signal (INTAD) is output when the ADCR register < the ADLL register (<2>) or the ADUL register < the ADCR register (<3>). Figure 10-8 shows the generation range of the interrupt signal (INTAD) for <1> to <3>. <R> Cautions 1. Only rewrite the value of the ADM2 register while conversion operation is stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0). 2. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register. 3. Do not set the ADREFP1 bit to 1 when shifting to STOP mode. Also, if the internal reference voltage (ADREFP1, ADREFP0 = 1, 0) is selected, the operating current indicated in 28.4.2 Supply current characteristics (ITMPS) will be added to the current consumption when shifting to HALT mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 313 RL78/G12 CHAPTER 10 A/D CONVERTER Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2) Address: F0010H After reset: 00H R/W Symbol 7 6 5 4 <3> <2> 1 <0> ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP AWC Specification of the SNOOZE mode 0 Do not use the SNOOZE mode function. 1 Use the SNOOZE mode function. When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed without operating the CPU (the SNOOZE mode). * The SNOOZE mode function can be specified only when the high-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited. * Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited. * Using the SNOOZE mode function in the sequential conversion mode is prohibited. * When using the SNOOZE mode function, specify a hardware trigger interval of at least (shift time to SNOOZE mode Note + A/D power supply stabilization wait time + A/D conversion time+ 2 fCLK) (Refer to table 10-3). * If using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode. Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode. If the AWC bit is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal operation mode. ADTYP Selection of the A/D conversion resolution 0 10-bit resolution 1 8-bit resolution Note Refer to "From STOP to SNOOZE" in 18.2.3 SNOOZE mode Caution Only rewrite the value of the ADM2 register while conversion operation is stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0). Figure 10-8. ADRCK Bit Interrupt Signal Generation Range ADCR register value (A/D conversion result) 1111111111 <3> Area 3 (ADUL < ADCR) INTAD is generated when ADRCK = 1. ADUL register setting <1> Area 1 (ADLL ADCR ADUL) INTAD is generated when ADRCK = 0. ADLL register setting 0000000000 Remark <2> Area 2 (ADCR < ADLL) INTAD is generated when ADRCK = 1. If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 314 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.5 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to 0. Each time A/D conversion ends, the conversion result is loaded from the successive approximation register (SAR). The higher 8 bits of the conversion result are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of FFF1EH Note. The ADCR register can be read by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADUL/ADLL registers; see Figure 10-8), the result is not stored. Figure 10-9. Format of 10-bit A/D Conversion Result Register (ADCR) Address: FFF1FH, FFF1EH After reset: 0000H R FFF1FH Symbol FFF1EH ADCR 0 0 0 0 0 0 Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. 2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (ADCR1 and ADCR0). 3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result are read in order starting at bit 15. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 315 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.6 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored Note . The ADCRH register can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note If the A/D conversion result is outside the range specified by using the A/D conversion comparison function (the value specified by the ADRCK bit of the ADUL/ADLL registers; see Figure 10-8), the result is not stored. Figure 10-10. Format of 8-bit A/D Conversion Result Register (ADCRH) Address: FFF1FH Symbol 7 After reset: 00H 6 5 R 4 3 2 1 0 ADCRH Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect conversion result to be read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 316 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.7 Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-11. Format of Analog Input Channel Specification Register (ADS) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0 Select mode (ADMD = 0) ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Note1 Analog input Input source channel 0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin 0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin 0 0 0 0 1 0 ANI2 P22/ANI2 pin 0 0 0 0 1 1 ANI3 P23/ANI3 pin 0 1 0 0 0 0 ANI16 P10/ANI16 pin P01/ANI16 pin 0 1 0 0 0 1 ANI17 P11/ANI17 pin P00/ANI17 pin 0 1 0 0 1 0 ANI18 P12/ANI18 pin P147/ANI18 pin 0 1 0 0 1 1 ANI19 P13/ANI19 pin P120/ANI19 pin 0 1 0 1 0 0 ANI20 P14/ANI20 pin - 0 1 0 1 0 1 ANI21 0 1 0 1 1 0 ANI22 P42/ANI21 pin - P41/ANI22 pin - 1 0 0 0 0 - 0 Temperature sensor output Note2 1 0 0 0 0 - 1 Internal reference voltage output (1.45 V) Other than the above Notes 1. 2. Remark Note2 Setting prohibited Upper: 20- or 24-pin products, lower: 30-pin products. This setting can be used only in HS (high-speed main) mode. - : Ignore the conversion result because it is underfined. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 317 RL78/G12 CHAPTER 10 A/D CONVERTER Scan mode (ADMD = 1) ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Scan 0 Scan 1 Scan 2 Scan 3 0 0 0 0 0 ANI0 ANI1 ANI2 ANI3 0 0 0 0 1 ANI1 ANI2 ANI3 - 0 0 0 1 0 ANI2 ANI3 - - 0 0 0 1 1 ANI3 - - - Other than the above Setting prohibited Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Set a channel to be set the analog input by ADPC and PMC registers in the input mode by using port mode registers 0, 1, 2, 4, 12, or 14 (PM0, PM1, PM2, PM4 PM12, PM14). 3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O by the ADS register. 4. Do not set the pin that is set by port mode control registers 0, 1, 4, 12, 14 (PMC0, PMC1, PMC4, PMC12, PMC14) as digital I/O by the ADS register. 5. Only rewrite the value of the ADISS bit while A/D conversion comparator operation is <R> stopped(ADCS = 0, ADCE = 0) 6. If using AVREFP as the + side reference voltage source of the A/D converter, do not select ANI0 as an A/D conversion channel. 7. If using AVREFM as the - side reference voltage source of the A/D converter, do not select ANI1 as an A/D conversion channel. 8. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side reference voltage source. 9. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for stabilization after the hardware trigger is detected. 10. Ignore the conversion result if the corresponding ANI pin does not exist in the product used. Remark - : Ignore the conversion result because it is undefined. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 318 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.8 Conversion result comparison upper limit setting register (ADUL) This register is used to specify the setting for checking the upper limit of the A/D conversion results. The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 10-8). The ADUL register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Caution When 10-bit resolution A/D conversion is selected, the higher 8 bits of the 10-bit A/D conversion result register (ADCR) are compared with the ADUL register. Figure 10-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL) Address: F0011H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0 10.3.9 Conversion result comparison lower limit setting register (ADLL) This register is used to specify the setting for checking the lower limit of the A/D conversion results. The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 10-8). The ADLL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL) Address: F0012H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0 Caution When 10-bit resolution A/D conversion is selected, the higher 8 bits of the 10-bit A/D conversion result register (ADCR) are compared with the ADLL register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 319 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.10 A/D test register (ADTES) This register is used to select the + side reference voltage (AVREFP) or - side reference voltage (AVREFM) of the A/D converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function. For detail, refer to 21.3.7 A/D test function The ADTES register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-14. Format of A/D Test Register (ADTES) Address: F0013H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 0 0 A/D conversion target ANIxx / temperature sensor output / internal reference voltage output (1.45V) (This is Note specified using the analog input channel specification register (ADS).) 1 0 AVREFM 1 1 AVREFP Other than the above Setting prohibited Note Temperature sensor output/internal reference voltage (1.45V) can be used only in HS (high-speed main) mode. Caution For details of the A/D test function, see 21.3.7 A/D test function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 320 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.11 A/D port configuration register (ADPC) This register switches the ANI0/P20 to ANI3/P23 pins to analog input of A/D converter or digital I/O of port. The ADPC register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-15. Format of A/D Port Configuration Register (ADPC) Address: F0076H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPC0 Analog input (A)/digital I/O (D) switching ADPC2 ADPC1 ADPC0 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20 0 0 0 A A A A 0 0 1 D D D D 0 1 0 D D D A 0 1 1 D D A A 1 0 0 D A A A Other than above Setting prohibited Cautions 1. Set the port to analog input by ADPC register to the input mode by using port mode registers 2 (PM2). 2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel specification register (ADS). 3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the port mode register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 321 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.12 Port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14) These registers are used to set the digital I/O/analog input of ports 0, 1, 4, 12, and 14 in 1-bit units. When using the P10/ANI16/PCLBUZ0/SCK00/SCL00, P11/ANI17/SI00/RxD0/SDA00/TOOLRxD, P12/ANI18/SO00/ TxD0/TOOLTxD, P13/ANI19/TI00/TO00/INTP2, P14/ANI20/TI01/TO01/INTP3, P42/ANI21/SCK01/SCL01/TI03/TO03, or P41/ANI22/SO01/SDA01/TI02/TO02/INTP1 pin of 20- or 24-pin products as an analog input pin, set the corresponding bit (PMC10, PMC11, PMC12, PMC13, PMC14, PMC41, PMC42) to 1. When using the P01/ANI16/TO00/RxD1, P00/ANI17/TI00/TxD1, P147/ANI18, or P120/ANI19 pin of 30-pin products as an analog input pin, set the corresponding bit (PMC00, PMC01, PMC120, PMC147) to 1. The PMC0, PMC1, PMC4, PMC12, and PMC14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 10-16. Formats of Port Mode Control Registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14) 20- and 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC1 1 1 1 PMC14 PMC13 PMC12 PMC11 PMC10 F0061H FFH R/W PMC4 1 1 1 1 1 PMC42 PMC41 1 F0064H FFH R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PMC0 1 1 1 1 1 1 PMC01 PMC00 F0060H FFH R/W PMC12 1 1 1 1 1 1 1 PMC120 F006CH FFH R/W PMC14 PMC147 1 1 1 1 1 1 1 F006EH FFH R/W PMCm Pmn pin digital I/O/analog input selection (m = 0, 1, 4, 12, and 14; n = 0 to 4, and 7) 0 Digital I/O (dual-use function other than analog input) 1 Analog input Cautions 1. Set the port to analog input by PMC register to the input mode by using port mode registers x (PMx). 2. Do not set the pin set by the PMC register as digital I/O by the analog input channel specification register (ADS). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 322 RL78/G12 CHAPTER 10 A/D CONVERTER 10.3.13 Port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14) When using the P10/ANI16/PCLBUZ0/SCK00/SCL00, P11/ANI17/SI00/RxD0/SDA00/TOOLRxD, P12/ANI18/SO00/ TxD0/TOOLTxD, P13/ANI19/TI00/TO00/INTP2, P14/ANI20/TI01/TO01/INTP3, P42/ANI21/SCK01/SCL01/TI03/TO03, P41/ANI22/SO01/SDA01/TI02/TO02/INTP1P20/ANI0/AVREFP, P21/ANI1/AVREFM, P22/ANI2, or P23/ANI3 pin of 20- or 24-pin products for an analog input port, set the corresponding bit (PM10 to PM14, PM20 to PM23, PM41, PM42) to 1. At this time, the output latches of P10 to P14, P20 to P23, P41, and P42 may be 0 or 1. When using the P01/ANI16/TO00/RxD1, P00/ANI17/TI00/TxD1, P20/ANI0/AVREFM, P21/ANI1/AVREFP, P22/ANI2, P23/ANI3, P147/ANI18, P120/ANI19 pin of 30-pin products for an analog input port, set the corresponding bit (PM00, PM01, PM20 to PM23, PM120, and PM147) to 1. At this time, the output latches of P00, P01, P20 to P23, P120, and P147 may be 0 or 1. If a port mode register bit corresponding to the pin is set to 0, the pin functions as an output pin and therefore cannot be used as an analog input pin. The PM0, PM1, PM2, PM14, PM12, and PM14 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Caution If a pin is set as an analog input port, not the pin level but "0" is always read. Figure 10-17. Formats of Port Mode Registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM14, PM12, PM14) 20- and 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W PM12 1 1 1 1 1 1 1 PM120 FFF2CH FFH R/W PM14 PM147 1 1 1 1 1 1 1 FFF2EH FFH R/W PMm Pmn pin I/O mode selection (m = 0 to 2, 12, and 14; n = 0 to 4) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Caution When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify input mode by using the PM20 and PM21 bits for port mode register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 323 RL78/G12 CHAPTER 10 A/D CONVERTER The function of the ANI0/P20 to ANI3/P23 pins are set depending on the settings of the A/D port configuration register (ADPC), analog input channel specification register (ADS), and PM2 registers. Table 10-4. Functions of ANI0/P20 to ANI3/P23 Pins ADPC Digital I/O selection Analog input selection PM2 ADS Function Input mode - Digital input Output mode - Digital output Input mode Output mode Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. The function of the P10/ANI16 to P14/ANI20, P42/ANI21, and P41/ANI22 pins of 20- or 24-pin products are set depending on the settings of port mode control registers 1, 4 (PMC1, PMC4), analog input channel specification register (ADS), and port mode registers 1, 4 (PM1, PM4). The function of the P01/ANI16, P00/ANI17, P147/ANI18, and P120/ANI19 pins of 30-pin products are set depending on the settings of port mode control registers 0, 12, 14 (PMC0, PMC12, PMC14), analog input channel specification register (ADS), and port mode registers 0, 12, 14 (PM0, PM12, PM14). Table 10-5. Functions of Pins for Analog Input as Dual-use Excluding ANI0 to ANI3 PMCn Digital I/O selection Analog input selection PMn Function ADS Input mode - Digital input Output mode - Digital output Input mode Output mode Note Selects ANI. Analog input (to be converted) Does not select ANI. Analog input (not to be converted) Selects ANI. Setting prohibited Does not select ANI. Remark n = 0, 1, 4, 12, 14 Note 20- or 24-pin products: P10/ANI16-P14/ANI20, P42/ANI21, P41/ANI22 30-pin products: P01/ANI16, P00/ANI17, P147/ANI18, P120/ANI19 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 324 RL78/G12 CHAPTER 10 A/D CONVERTER 10.4 A/D Converter Conversion Operations The A/D converter conversion operations are described below. <1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit. <2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the sampled voltage is held until the A/D conversion operation has ended. <3> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2) AVREF by the tap selector. <4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the voltage comparator. If the analog input is greater than (1/2) AVREF, the MSB bit of the SAR register remains set to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0. <5> Next, bit 8 of the SAR register is automatically set to 1, and the operation proceeds to the next comparison. The series resistor string voltage tap is selected according to the preset value of bit 9, as described below. * Bit 9 = 1: (3/4) AVREF * Bit 9 = 0: (1/4) AVREF The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as follows. * Sampled voltage Voltage tap: Bit 8 = 1 * Sampled voltage < Voltage tap: Bit 8 = 0 <6> Comparison is continued in this way up to bit 0 of the SAR register. <7> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and the result value is transferred to the A/D conversion result register (ADCR, ADCRH) and then latched Note 1. At the same time, the A/D conversion end interrupt request (INTAD) can also be generated Note 1. <8> Repeat steps <1> to <7>, until the ADCS bit is cleared to 0 Note 2 . To stop the A/D converter, clear the ADCS bit to 0. Notes 1. If the A/D conversion result is outside the A/D conversion result range specified by the ADRCK bit and the ADUL and ADLL registers (see Figure 10-8), the A/D conversion result interrupt request signal is not generated and no A/D conversion results are stored in the ADCR and ADCRH registers. 2. While in the sequential conversion mode, the ADCS flag is not automatically cleared to 0. This flag is not automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode, either. Instead, 1 is retained. Remarks 1. Two types of the A/D conversion result registers are available. * ADCR register (16 bits): Store 10-bit A/D conversion value * ADCRH register (8 bits): Store 8-bit A/D conversion value 2. AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 325 RL78/G12 CHAPTER 10 A/D CONVERTER Figure 10-18. Conversion Operation of A/D Converter (Software Trigger Mode) ADCS 1 or ADS rewrite Conversion time Sampling time A/D converter operation SAR SAR clear Sampling A/D conversion Undefined ADCR Conversion result Conversion result INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software. If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the beginning. Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 326 RL78/G12 CHAPTER 10 A/D CONVERTER 10.5 Input Voltage and Conversion Results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3, ANI16 to ANI22) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF x 1024 + 0.5) ADCR = SAR x 64 or ( ADCR 64 - 0.5) x where, INT( ): AVREF 1024 VAIN < ( ADCR 64 + 0.5) x AVREF 1024 Function which returns integer part of value in parentheses VAIN: Analog input voltage AVREF: AVREF pin voltage ADCR: A/D conversion result register (ADCR) value SAR: Successive approximation register Figure 10-19 shows the relationship between the analog input voltage and the A/D conversion result. Figure 10-19. Relationship Between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 FFC0H 1022 FF80H 1021 FF40H 3 00C0H 2 0080H 1 0040H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal reference voltage (1.45 V), and VDD. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 327 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6 A/D Converter Operation Modes The operation of each A/D converter mode is described below. In addition, the procedure for specifying each mode is described in 10.7 A/D Converter Setup Flowchart. 10.6.1 Software trigger mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS). <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. <4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. Figure 10-20. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCS The trigger is not acknowledged. ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> <3> A/D conversion <3> ends and the next conversion starts. Stop Conversion status standby Data0 (ANI0) ADCR, ADCRH Data0 (ANI0) Data 0 (ANI0) Data0 (ANI0) <6> ADCS is cleared to <7> 0 during A/D conversion operation. A hardware trigger is generated (and ignored). ADS is rewritten during <5> A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) <3> Data 0 (ANI0) ADS A/D conversion status ADCS is overwritten with 1 during A/D conversion operation. Conversion is <3> interrupted and restarts. Data 0 Data0 (ANI0) (ANI0) Data0 (ANI0) Data 1 (ANI1) Data0 (ANI0) Data 1 (ANI1) Data 1 (ANI1) The trigger is not acknowledged. Conversion is interrupted. <3> Data 1 (ANI1) Conversion Stop standby status Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 328 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.2 Software trigger mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform the A/D conversion of the analog input specified by the analog input channel specification register (ADS). <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion standby status. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby status. Figure 10-21. Example of Software Trigger Mode (Select Mode, One-Shot Conversion Mode) Operation Timing ADCE is cleared to 0. <8> <1> ADCE is set to 1. ADCE The trigger is not acknowledged. ADCS is ADCS is set to <2> 1 while in the <4> automatically <2> cleared to conversion 0 after standby status. <2> conversion ends. ADCS Stop Conversion status standby Data 0 (ANI0) A/D <3> conversion ends. Conversion Data 0 standby (ANI0) ADCR, ADCRH <4> <6> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Data 0 (ANI0) ADS A/D conversion status ADCS is overwritten <4> <5> with 1 during A/D conversion operation. Data 0 (ANI0) Conversion is interrupted and restarts. Data 0 (ANI0) <2> ADCS is <7> cleared to 0 during A/D conversion operation. Conversion is interrupted. <3> <3> Conversion standby Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) The trigger is not acknowledged. Conversion Data 1 standby (ANI1) Conversion standby Stop status Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 329 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.3 Software trigger mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts (until all four channels are finished). <4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <6> Even if a hardware trigger is input during conversion operation, A/D conversion does not start. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. <R> Figure 10-22. Example of Software Trigger Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCS The trigger is not acknowledged. ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> ADCS is overwritten with 1 during A/D conversion operation. A hardware trigger is <6> generated (and ignored). ADCS is cleared <7> to 0 during A/D conversion operation. The trigger is not acknowledged. <5> ADS is rewritten during A/D conversion operation. ADS A/D conversion status ADCR, ADCRH ANI0 to ANI3 ANI1 to ANI3 A/D conversion ends and the <3> next conversion starts. Stop Conversion Data 0 status standby (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) <3> Conversion is interrupted and restarts. Data 1 (ANI1) Data 0 (ANI0) Data 1 (ANI1) Data 0 (ANI0) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Conversion is interrupted and restarts. Data 1 (ANI1) Data 1 (ANI1) Data 0 (ANI0) Conversion is interrupted. <3> Data 2 (ANI2) Data 3 (ANI3) Undefined Data 1 (ANI1) value Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Undefined value Data 2 (ANI2) Conversion standby Stop status Data 1 (ANI1) INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. The interrupt is generated four times. 330 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.4 Software trigger mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion of the four channels ends, the ADCS bit is automatically cleared to 0, and the system enters the A/D conversion standby status. <5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. <8> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D conversion does not start even if a hardware trigger is input while in the A/D conversion standby status. <R> Figure 10-23. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCS The trigger is not acknowledged. ADCE is cleared to 0. <8> <2> ADCS is set to 1 while in the conversion standby status. <4> ADCS is automatically <2> cleared to 0 after conversion ends. <5> ADCS is overwritten with 1 during A/D conversion operation. <4> ADCS is cleared <7> to 0 during A/D conversion operation. <2> The trigger is not acknowledged. <6> ADS is rewritten during A/D conversion operation. ADS ANI1 to ANI3 ANI0 to ANI3 <3> A/D conversion A/D conversion status ADCR, ADCRH Stop Conversion Data 0 status standby (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) ends. Conversion Data 0 Data 1 Data 0 (ANI0) (ANI1) (ANI0) standby Data 3 (ANI3) Conversion is interrupted and restarts. Conversion is <3> interrupted and restarts. Data 1 (ANI1) Data 0 (ANI0) Data 2 (ANI2) Data 3 Conversion (ANI3) standby Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Data 1 (ANI1) Data 0 (ANI0) Data 2 (ANI2) Data 1 (ANI1) Conversion is interrupted. Data 3 (ANI3) Undefined Conversion Stop standby status value Data 2 (ANI2) Data 3 (ANI3) INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. 331 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). <4> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not power down in this status. <9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 10-24. Example of Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing ADCE is cleared to 0. <9> <1> ADCE is set to 1. ADCE <2> ADCS is set to 1. <5> A hardware trigger is generated during A/D conversion operation. <3> A hardware trigger is generated. Hardware trigger Trigger The trigger is not standby acknowledged. status ADCS Data 0 (ANI0) <4> A/D conversion ends and the next conversion<4> starts. ADS A/D conversion status Stop status Conversion standby Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) The trigger is not acknowledged. ADCS is overwritten <7> ADCS is cleared <8> with 1 during A/D to 0 during A/D conversion operation. conversion operation. <6> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Conversion is interrupted and Conversion Conversion is Conversion is is interrupted. restarts. <4> interrupted <4> interrupted <4> and restarts. and restarts. Data 1 Data 1 Data 1 Data 0 Data 1 Conversion Data 0 (ANI1) (ANI1) (ANI1) (ANI0) (ANI1) standby (ANI0) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Stop status Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 332 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). <4> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <5> After A/D conversion ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby status. <6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not power down in this status. <10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 10-25. Example of Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing ADCE is cleared to 0. <10> <1> ADCE is set to 1. <2> ADCS is set to 1. ADCE <3>A hardware trigger <3> is generated. Hardware trigger <6> A hardware trigger is generated during A/D conversion operation. The trigger is not Trigger ADCS retains<5> acknowledged. standby the value 1. status <3> <5> ADCS <3> <3> ADCS is overwritten with 1 during <8> A/D conversion <5> operation. <5> <7>ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). <4> A/D conversion ends. A/D conversion status Stop status Conversion standby <9> ADCS is cleared to 0 during A/D conversion operation. Data 1 (ANI1) Data 0 (ANI0) ADS Trigger standby status Data 0 (ANI0) ADCR, ADCRH Conversion standby Conversion is interrupted and restarts. Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) Conversion standby Conversion is interrupted and restarts. <4> Conversion is interrupted and restarts. <4> <4> Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Conversion Data 1 standby (ANI1) Data 1 (ANI1) Data 1 (ANI1) Conversion standby Conversion is interrupted. Data 1 Conversion Stop (ANI1) standby status Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 333 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not power down in this status. <9> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. <R> Figure 10-26. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE ADCE is cleared to 0. <9> <2> ADCS is set to 1. <5> A hardware trigger is generated during A/D conversion operation. <3> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. Trigger The trigger standby is not status acknowledged. Trigger standby status ADCS is overwritten <7> with 1 during A/D conversion operation. ADCS is cleared to 0 <8> during A/D conversion operation. ADCS <6> ADS is rewritten during A/D conversion operation. A/D conversion status ADCR, ADCRH ANI1 to ANI3 ANI0 to ANI3 ADS Conversion is interrupted and restarts. A/D conversion<4> ends and the next conversion starts. Stop status Conversion Data 0 standby (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Data 0 (ANI0) Data 1 (ANI1) Data 0 (ANI0) Conversion is interrupted and restarts. <4> Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Data 1 (ANI1) Data 0 (ANI0) Conversion is interrupted and restarts. <4> Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Data 2 (ANI2) Data 1 (ANI1) Data 3 (ANI3) Data 2 (ANI2) Data 4 (ANI4) Data 3 (ANI3) Data 1 (ANI1) Data 2 (ANI2) <4> Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Data 2 (ANI2) Data 1 (ANI1) Conversion is interrupted. Conversion standby Stop status Data 3 (ANI3) INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. 334 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> After the software counts up to the stabilization wait time (1 s), the ADCS bit of the ADM0 register is set to 1 to place the system in the hardware trigger standby status (and conversion does not start at this stage). Note that, while in this status, A/D conversion does not start even if ADCS is set to 1. <3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <4> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby status. <6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the system enters the A/D conversion standby status. However, the A/D converter does not power down in this status. <10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status. When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start. <R> Figure 10-27. Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE is cleared to 0. <10> <2> ADCS is set to 1. <3> A hardware trigger is generated. ADCE Hardware trigger The trigger is not Trigger acknowledged. standby status <3> <6> A hardware trigger is generated during A/D conversion operation. <5> ADCS retains <5> the value 1. ADS is rewritten <7> during A/D conversion operation. ADS ANI0 to ANI3 ANI1 to ANI3 <4> A/D Conversion is interrupted and restarts. conversion ends. ADCR, ADCRH Stop status Conversion standby Conversion standby status <8> ADCS is overwritten <9> ADCS is cleared with 1 during A/D to 0 during A/D conversion operation. conversion operation. <5> ADCS A/D conversion status <3> <3> Data 0 Data 1 Data 2 Data 3 Conversion Data 0 (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) Data 0 Data 1 Data 2 (ANI0) (ANI1) (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is interrupted and restarts. <4> Data 0 Data 1 Data 2 Data 3 Conversion Data 0 (ANI0) (ANI1) (ANI2) (ANI3) standby (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is interrupted and restarts. <4> Data 1 Data 2 Data 3 Undefined Conversion Data 1 value (ANI1) (ANI2) (ANI3) standby (ANI1) Data 0 (ANI0) Data 1 Data 2 (ANI1) (ANI2) Data 3 (ANI3) Undefined value Data 2 (ANI2) Data 1 (ANI1) Data 2 (ANI2) Data 1 (ANI1) Data 3 (ANI3) Conversion is interrupted. Conversion Stop standby status Data 2 (ANI2) INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. The interrupt is generated four times. 335 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next A/D conversion immediately starts. (At this time, no hardware trigger is necessary.) <4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 10-28. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. ADCS Trigger standby status Data 0 (ANI0) ADS A/D conversion status <4> A hardware trigger is generated during A/D conversion operation. <3> A/D conversion ends and the next conversion<3> starts. Stop status Data 0 (ANI0) ADCR, ADCRH Data 0 (ANI0) Data 0 (ANI0) Data 0 (ANI0) Trigger The trigger standby is not status acknowledged. ADCS is overwritten <6> ADCS is cleared <7> to 0 during A/D with 1 during A/D conversion operation. conversion operation. <5> ADS is rewritten during A/D conversion operation (from ANI0 to ANI1). Data 1 (ANI1) Conversion is Conversion is Conversion is interrupted and Conversion is interrupted interrupted. restarts. interrupted <3> and restarts.<3> <3> and restarts. Data 0 Data 1 Data 1 Data 0 Data 1 Data 1 Stop status (ANI0) (ANI1) (ANI1) (ANI0) (ANI1) (ANI1) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 336 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the hardware trigger standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. <3> When A/D conversion ends, the conversion result is stored in the A/D conversion result register (ADCR, ADCRH), and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop status. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is initialized. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. Figure 10-29. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. Hardware trigger <2> <5> A hardware trigger is generated during A/D conversion operation. Trigger ADCS is automatically The trigger is not standby <4> acknowledged. status cleared to 0 after conversion ends. ADCS <2> <2> <4> <4> Trigger standby status <2> <7> ADCS is overwritten<4> with 1 during A/D conversion operation. is rewritten <6> ADS during A/D conversion <8> ADCS is cleared to 0 during A/D conversion operation. operation (from ANI0 to ANI1). Data 0 (ANI0) ADS <3> A/D conversion ends. A/D conversion status Stop status Data 0 (ANI0) ADCR, ADCRH Stop status Data 0 (ANI0) Conversion is interrupted <3> and restarts. Stop Data 0 status (ANI0) Data 0 (ANI0) Data 1 (ANI1) Conversion is interrupted and restarts.<3> Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Stop status Conversion is interrupted and restarts. <3> Data 1 (ANI1) Data 1 (ANI1) Data 1 (ANI1) Conversion is interrupted. Stop Data 1 status (ANI1) Stop status Data 1 (ANI1) INTAD R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 337 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D conversion of the channel following the specified channel automatically starts. <4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. <R> Figure 10-30. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <4> A hardware trigger is generated during A/D conversion operation. <2> A hardware trigger is generated. Hardware trigger The trigger is not acknowledged. Trigger The trigger standby is not status acknowledged. Trigger standby status ADCS is overwritten <6> with 1 during A/D conversion operation. ADCS is cleared <7> to 0 during A/D conversion operation. ADCS <5> ADS is rewritten during A/D conversion operation. ADS A/D conversion status ADCR, ADCRH ANI1 to ANI3 ANI0 to ANI3 A/D conversion <3> ends and the next conversion starts. Stop status Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) <3> Conversion is interrupted and restarts. Data 1 (ANI1) Data 0 (ANI0) Data 1 (ANI1) Data 0 (ANI0) Data 2 (ANI2) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Conversion is interrupted and restarts. Data 1 (ANI1) Data 1 (ANI1) Data 0 (ANI0) <3> Data 2 (ANI2) Data 3 Undefined (ANI3) value Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Data 1 (ANI1) Conversion is interrupted and restarts. Data 2 (ANI2) Undefined Data 1 (ANI1) value Data 3 (ANI3) Data 1 (ANI1) Data 2 (ANI2) <3> Data 2 (ANI2) Data 3 Undefined Data 1 (ANI1) (ANI3) value Data 1 (ANI1) Data 2 (ANI2) Data 3 (ANI3) Conversion is interrupted. Stop status Undefined value INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. 338 RL78/G12 CHAPTER 10 A/D CONVERTER 10.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) <1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the A/D conversion standby status. <2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that specified by scan 0. <3> A/D conversion is sequentially performed on the four analog input channels, the conversion results are stored in the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end interrupt request signal (INTAD) is generated. <4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop status. <5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and conversion restarts at the first channel. The partially converted data is discarded. <6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register. The partially converted data is discarded. <7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and conversion restarts. The partially converted data is discarded. <8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0, inputting a hardware trigger is ignored and A/D conversion does not start. <R> Figure 10-31. Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing <1> ADCE is set to 1. ADCE <2> A hardware trigger is generated. <2> Hardware trigger ADCS ADS The trigger is not Trigger acknowledged. standby ADCS is automatically <4> cleared to 0 after conversion ends. ADS is rewritten <6> during A/D conversion operation. ANI0 to ANI3 ADCR, ADCRH Stop status <7>ADCS is overwritten <8> ADCS is cleared with 1 during A/D to 0 during A/D conversion operation. conversion operation. <4> status Data 0 (ANI0) Conversion standby The trigger is not status acknowledged. <2> <2> <4> ANI1 to ANI3 <3> A/D conversion ends. A/D conversion status <5> A hardware trigger is generated during A/D conversion operation. Data 1 Data 2 (ANI1) (ANI2) Data 3 (ANI3) Data 0 Data 1 (ANI0) (ANI1) Data 2 (ANI2) Stop status Conversion is interrupted and restarts. Data 0 Data 1 Data 0 Data 1 Data 2 Data 3 (ANI0) (ANI1) (ANI0) (ANI1) (ANI2) (ANI3) Data 3 (ANI3) Data 0 (ANI0) Data 1 (ANI1) Conversion is interrupted and restarts. <3> Data 2 (ANI2) Stop status Data 0 Data 1 Data 1 Data 2 Data 3 Undifined (ANI0) (ANI1) (ANI1) (ANI2) (ANI3) value Data 3 (ANI3) Data 0 (ANI0) Data 1 Data 2 (ANI1) (ANI2) Conversion is interrupted and restarts. <3> Data 3 (ANI3) Stop status Data 1 Data 2 (ANI1) (ANI2) Undifined value Data 1 (ANI1) Data 2 (ANI2) Data 1 (ANI1) Data 3 (ANI3) Conversion is interrupted. Stop status Data 2 (ANI2) INTAD The interrupt is generated four times. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The interrupt is generated four times. The interrupt is generated four times. 339 RL78/G12 CHAPTER 10 A/D CONVERTER 10.7 A/D Converter Setup Flowchart The A/D converter setup flowchart in each operation mode is described below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 340 RL78/G12 CHAPTER 10 A/D CONVERTER 10.7.1 Setting up software trigger mode Figure 10-32. Setting up Software Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A The stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: 5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0 s ADCE bit setting Stabilization wait time count B ADCS bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Counting 1 s for the stabilization wait time After counting up to the stabilization wait time ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated.Note The conversion results are stored in the ADCR and ADCRH registers Note. End Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 341 RL78/G12 CHAPTER 10 A/D CONVERTER 10.7.2 Setting up hardware trigger no-wait mode Figure 10-33. Setting up Hardware Trigger No-Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A ADCE bit setting Stabilization wait time count B ADCS bit setting The stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: 5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0 s t The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Counting 1 s for the stabilization wait time After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and the system enters the hardware trigger standby status. Hardware trigger standby status Start of A/D conversion by generating a hardware trigger The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. End Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 342 RL78/G12 CHAPTER 10 A/D CONVERTER 10.7.3 Setting up hardware trigger wait mode Figure 10-34. Setting up Hardware Trigger Wait Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. The ports are set to analog input. ADPC and PMC register settings PM register setting ANI0 to ANI14 pins: Set using the ADPC register ANI16 to ANI26 pins: Set using the PMC register The ports are set to the input mode. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: Select mode/scan mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal. * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. AWC bit: This is used to set up the SNOOZE mode function. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADS4 to ADS0 bits: These are used to select the analog input channels. Stabilization wait time count A ADCE bit setting The stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: 5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0 s The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Hardware trigger generation Stabilization wait time count B Start of A/D conversion The system automatically counts up to the stabilization wait time for A/D power supply. After counting up to the stabilization wait time ends, A/D conversion starts The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. End Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 343 RL78/G12 <R> CHAPTER 10 A/D CONVERTER 10.7.4 Setup when temperature sensor output/internal reference voltage output is selected (example for software trigger mode and one-shot conversion mode) Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: Sequential conversion mode/one-shot conversion mode * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference voltage source. ADRCK bit: This is used to select the range for the A/D conversion result comparison value generated by the interrupt signal from AREA1, AREA3, and AREA2. ADTYP bit: 8-bit/10-bit resolution * ADUL/ADLL register These are used to specify the upper limit and lower limit A/D conversion result comparison values. * ADS register ADISS and ADS4 to ADS0 bits: These are used to select temperature sensor 0 output or internal reference voltage output. Stabilization wait time count A The stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0 s If change the ADREFP1 and ADREFP0 = 1, 0: Setting prohibited ADCE bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. First A/D conversion time Stabilization wait time count B Second A/D conversion time <R> Figure 10-35. Setup when Temperature Sensor Output/internal Reference Voltage Output is Selected ADCS bit setting Counting 1 s for the stabilization wait time After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts Start of A/D conversion End of A/D conversion ADCS bit setting The A/D conversion end interrupt (INTAD) will be generated. After ADISS is set (1), the initial conversion result cannot be used. The ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. End Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. Caution HS (high-speed main) mode can be selected R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 344 RL78/G12 CHAPTER 10 A/D CONVERTER 10.7.5 Setting up test mode Figure 10-36. Setting up Test Trigger Mode Start of setup PER0 register setting The ADCEN bit of the PER0 register is set (1), and supplying the clock starts. * ADM0 register FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time. ADMD bit: This is used to specify the select mode. * ADM1 register ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode. ADSCM bit: This is used to specify the one-shot conversion mode. * ADM0 register setting * ADM1 register setting * ADM2 register setting * ADUL/ADLL register setting * ADS register setting * ADTES register setting (The order of the settings is irrelevant.) * ADM2 register ADREFP1, ADREFP0, and ADREFM bits: These are used to select for the reference voltage source. ADRCK bit: This is used to set the range for the A/D conversion result comparison value generated by the interrupt signal to AREA2. ADTYP bit: This is used to specify 10-bit resolution. * ADUL/ADLL register These set ADUL to FFH and ADLL to 00H (initial values). * ADS register ADS4 to ADS0 bits: These are used to set to ANI0. * ADTES register ADTES1, ADTES0 bits: AVREFM/AVREFP Stabilization wait time count A ADCE bit setting Stabilization wait time count B ADCS bit setting The stabilization wait time count A is required when the value of the ADREFP1 and ADREFP0 bits is changed. If change the ADREFP1 and ADREFP0 = 1, 0: 5s If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0 s The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion standby status. Counting 1 s for the stabilization wait time After counting up to the stabilization wait time B ends, the ADCS bit of the ADM0 register is set (1), and A/D conversion starts. Start of A/D conversion The A/D conversion operations are performed. End of A/D conversion Storage of conversion results in the ADCR and ADCRH registers The A/D conversion end interrupt (INTAD) is generated. Note The conversion results are stored in the ADCR and ADCRH registers. End Note Depending on the settings of the ADRCK bit and ADUL/ADLL register, there is a possibility of no interrupt signal being generated. In this case, the results are not stored in the ADCR, ADCRH registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 345 RL78/G12 CHAPTER 10 A/D CONVERTER 10.8 SNOOZE mode function In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed without operating the CPU by inputting a hardware trigger. This is effective for reducing the operation current. If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be judged at a certain interval of time in SNOOZE mode. Using this function enables power supply voltage monitoring and input key judgment based on A/D inputs. In the SNOOZE mode, only the following two conversion modes can be used: * Hardware trigger wait mode (select mode, one-shot conversion mode) * Hardware trigger wait mode (scan mode, one-shot conversion mode) Caution SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. Figure 10-37. Block Diagram When Using SNOOZE Mode Function 12-bit interval timer (INTIT) Hardware trigger input Clock request signal (internal signal) Clock generator A/D converter A/D conversion end interrupt request signalNote 1 (INTAD) High-speed on-chip oscillator clock When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP mode (for details about these settings, see 10.7.3 Setting up hardware trigger wait mode Note 2 ). After the initial settings are specified, bit 2 (AWC) of A/D converter mode register 2 (ADM2) and bit 0 (ADCE) of A/D converter mode register 0 (ADM0) is set to 1. If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to the A/D converter. After supplying this clock, the system automatically counts up to the stabilization wait time, and then A/D conversion starts. The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt request signal is generated Note 1. Notes 1. Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL register), there is a possibility of no interrupt request signal being generated. 2. Remark Be sure to set the ADM1 register to E2H or E3H. Specify the hardware trigger by using the A/D Converter Mode Register 1 (ADM1). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 346 RL78/G12 CHAPTER 10 A/D CONVERTER (1) If an interrupt request is generated after A/D conversion ends If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison function (which is set up by using the ADRCK bit and ADUL/ADLL register, refer to Figure 10-8), the A/D conversion end interrupt request signal (INTAD) is generated. * While in the select mode After A/D conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE mode to the normal operation mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of the A/D converter mode register 2 (ADM2). If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode. * While in the scan mode If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four channels, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE mode to the normal operation mode. At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of A/D converter mode register 2 (ADM2) to 0. If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZE or normal operation mode. Figure 10-38. Operation Example When Interrupt Request Is Generated After A/D Conversion Ends (While in Scan Mode) INTIT Clock request signal (internal signal) The clock request signal remains at the high level. ADCS Conversion channels Channel 1 Channel 2 Channel 3 Channel 4 Interrupt request signal (INTAD) An interrupt request is generated when conversion on one of the channels ends. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 347 RL78/G12 CHAPTER 10 A/D CONVERTER (2) If no interrupt request is generated after A/D conversion ends If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison function (which is set up by using the ARDCK bit and ADUL/ADLL register, refer to Figure 10-8), the A/D conversion end interrupt request signal (INTAD) is not generated. * While in the select mode If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode. * While in the scan mode If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conversion of the four channels, the clock request signal (an internal signal) is automatically set to the low level after A/D conversion of the four channels ends, and supplying the high-speed on-chip oscillator clock stops. If a hardware trigger is input later, A/D conversion work is again performed in the SNOOZE mode. Figure 10-39. Operation Example When No Interrupt Request Is Generated After A/D Conversion Ends (While in Scan Mode) INTIT Clock request signal (internal signal) The clock request signal is set to the low level. ADCS Conversion channels Channel 1 Channel 2 Channel 3 Channel 4 Interrupt request signal (INTAD) No interrupt request is generated when conversion ends for any channel. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 348 RL78/G12 CHAPTER 10 A/D CONVERTER 10.9 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits. 10 1LSB = 1/2 = 1/1024 = 0.098%FSR Accuracy has no relation to resolution, but is determined by overall error. (2) Overall error This shows the maximum error value between the actual measured value and the theoretical value. Zero-scale error, full-scale error, integral linearity error, and differential linearity errors that are combinations of these express the overall error. Note that the quantization error is not included in the overall error in the characteristics table. (3) Quantization error When analog values are converted to digital values, a 1/2LSB error naturally occurs. In an A/D converter, an analog input voltage in a range of 1/2LSB is converted to the same digital code, so a quantization error cannot be avoided. Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity error, and differential linearity error in the characteristics table. Figure 10-40. Overall Error Figure 10-41. Quantization Error 1......1 1......1 Overall error Digital output Digital output Ideal line 1/2LSB Quantization error 1/2LSB 0......0 AVREF 0 Analog input 0......0 0 Analog input AVREF (4) Zero-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (1/2LSB) when the digital output changes from 0......000 to 0......001. If the actual measurement value is greater than the theoretical value, it shows the difference between the actual measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes from 0......001 to 0......010. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 349 RL78/G12 CHAPTER 10 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (full-scale - 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship. It expresses the maximum value of the difference between the actual measurement value and the ideal straight line when the zeroscale error and full-scale error are 0. (7) Differential linearity error While the ideal width of code output is 1LSB, this indicates the difference between the actual measurement value and the ideal value. Figure 10-42. Zero-Scale Error Figure 10-43. Full-Scale Error Full-scale error Ideal line 011 010 001 Zero-scale error 000 Digital output (Lower 3 bits) Digital output (Lower 3 bits) 111 111 110 101 Ideal line 000 0 1 2 3 AVREF AVREF-3 0 Analog input (LSB) AVREF-2 AVREF-1 AVREF Analog input (LSB) Figure 10-44. Integral Linearity Error Figure 10-45. Differential Linearity Error 1......1 1......1 Ideal 1LSB width Digital output Digital output Ideal line Integral linearity error 0......0 0 Analog input Differential linearity error 0......0 0 AVREF Analog input AVREF (8) Conversion time This expresses the time from the start of sampling to when the digital output is obtained. The sampling time is included in the conversion time in the characteristics table. (9) Sampling time This is the time the analog switch is turned on for the analog voltage to be sampled by the sample & hold circuit. Sampling time Conversion time R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 350 RL78/G12 CHAPTER 10 A/D CONVERTER 10.10 Cautions for A/D Converter (1) Operating current in STOP mode Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0 (ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same time. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start operation. (2) Input range of ANI0 to ANI3 and ANI16 to ANI22 pins Observe the rated range of the ANI0 to ANI3 and ANI16 to ANI22 pins input voltage. If a voltage of VDD and AVREFP or higher and VSS and AVREFM or lower (even in the range of absolute maximum ratings) is input to an analog input channel, the converted value of that channel becomes undefined. In addition, the converted values of the other channels may also be affected. When internal reference voltage (1.45 V) is selected reference voltage source for the + side of the A/D converter, do not input internal reference voltage or higher voltage to a pin selected by the ADS register. However, it is no problem that a pin not selected by the ADS register is inputed voltage greater than the internal reference voltage. Caution Internal reference voltage (1.45 V) can be used only in HS (high-speed main) mode. (3) Conflicting operations <1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register read by instruction upon the end of conversion The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to the ADCR or ADCRH registers. <2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register 0 (ADM0) write, the analog input channel specification register (ADS), or A/D port configuration register (ADPC) write upon the end of conversion The ADM0, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed, nor is the conversion end interrupt signal (INTAD) generated. (4) Noise countermeasures To maintain the 10-bit resolution, attention must be paid to noise input to the AVREFP, VDD, ANI0 to ANI3, and ANI16 to ANI22 pins. <1> Connect a capacitor with a low equivalent resistance and a good frequency response to the power supply. <2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise, connecting external C as shown in Figure 10-47 is recommended. <3> Do not switch these pins with other pins during conversion. <4> The accuracy is improved if the HALT mode is set immediately after the start of conversion. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 351 RL78/G12 CHAPTER 10 A/D CONVERTER Figure 10-46. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREFP and VDD or equal to or lower than AVREFM and VSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREFP or VDD ANI0 to ANI3, ANI16 to ANI22 C = 100 to 1,000 pF (5) Analog input (ANIn) pins <1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23). When A/D conversion is performed with any of the ANI0 to ANI3 pins selected, do not change output value to alternat port P20 to P23 while conversion is in progress; otherwise the conversion resolution may be degraded. <2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result might differ from the expected value due to a coupling noise. Be sure to prevent such a pulse from being input or output. (6) Input impedance of analog input (ANIn) pins This A/D converter charges a sampling capacitor for sampling during sampling time. Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor flows during sampling. Consequently, the input impedance fluctuates depending on whether sampling is in progress, and on the other states. To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog input source to within 1 k, and to connect a capacitor of about 100 pF to the ANI0 to ANI3 and ANI16 to ANI22 pins (see Figure 10-46). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 352 RL78/G12 CHAPTER 10 A/D CONVERTER (7) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the pre-change analog input may be set just before the ADS register rewrite. Caution is therefore required since, at this time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D conversion for the post-change analog input has not ended. When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed. Figure 10-47. Timing of A/D Conversion End Interrupt Request Generation ADS rewrite (start of ANIn conversion) A/D conversion ANIn ADCR ADS rewrite (start of ANIm conversion) ANIn ANIn ADIF is set but ANIm conversion has not ended. ANIm ANIn ANIm ANIm ANIm ADIF (8) Conversion results just after A/D conversion start While in the software trigger mode or hardware trigger no-wait mode, the first A/D conversion value immediately after A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1 s after the ADCE bit was set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first conversion result. (9) A/D conversion result register (ADCR, ADCRH) read operation When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification register (ADS), A/D port configuration register (ADPC), and port mode control register (PMC), the contents of the ADCR and ADCRH registers may become undefined. Read the conversion result following conversion completion before writing to the ADM0, ADS, ADPC, or PMC register. Using a timing other than the above may cause an incorrect conversion result to be read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 353 RL78/G12 CHAPTER 10 A/D CONVERTER (10) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 10-48. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 10-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREFP, VDD 3.6 V VDD 5.5 V 2.7 V VDD < 3.6 V 1.8 V VDD < 2.7 V ANIn Pins R1 [k] C1 [pF C2 [pF] ANI0 to ANI3 14 8 2.5 ANI16 to ANI22 18 7.0 ANI0 to ANI3 39 2.5 ANI16 to ANI22 53 7.0 ANI0 to ANI3 231 2.5 ANI16 to ANI22 321 7.0 Remark The resistance and capacitance values shown in Table 10-6 are not guaranteed values. (11) Starting the A/D converter Start the A/D converter after the AVREFP and VDD voltages stabilize. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 354 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT CHAPTER 11 SERIAL ARRAY UNIT Serial array unit 0 has two serial channels in 20- and 24-pinproducts and four serial channels in 30-pin products, and serial array unit 1 mounted 30-pin products, has two serial channels. Each channel can achieve 3-wire serial (CSI), UART, and simplified I2C communication. Function assignment of each channel supported by the RL78/G12 is as shown below. 20- or 24-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 CSI01 Note 2 Used as Simplified I C IIC00 Note IIC01 Note 30-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 - 2 - 1 <R> IIC00 Note - UART1 Note Note 3 CSI11 0 CSI20 1 2 Used as Simplified I C Note - - Note IIC11 UART2 Note IIC20 Note - Note Provided in the R5F102 products only. A single channel cannot be used under multiple communication methods. When a different communication method is to be configured, use another channel. When using CSI00, CSI20, IIC00, IIC20, UART0, UART1, or UART2, communication between devices with different voltages (1.8, 2.5, or 3 V) is possible, except when using a 20- or 24-pin product with PIOR set to 1 and UART I/O assigned to P6. For details about the settings, see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 355 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.1 Functions of Serial Array Unit Each serial interface supported by the RL78/G12 has the following features. 11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel. 3-wire serial communication is clocked communication performed by using three communication lines: one for the serial clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI). For details about the settings, see 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication. [Data transmission/reception] * Data length of 7 or 8 bits * Phase control of transmit/receive data * MSB/LSB first selectable * Level setting of transmit/receive data [Clock control] * Master/slave selection * Phase control of I/O clock * Setting of transfer period by prescaler and internal counter of each channel * Maximum transfer rate During master communication (CSI00): Max. fMCK/2 Notes 1, 2 During master communication (other than CSI00): Max. fMCK/4 During slave communication: Note 2 Max. fMCK/6 Note 2 [Interrupt function] * Transfer end interrupt/buffer empty interrupt [Error detection flag] * Overrun error Notes 1. In master communication (CSI00), maximum transfer rate become fMCK/2 when the following three conditions. * 2.7 V VDD 5.5 V * fMCK 24 MHz * PIOR1 = 0 Other cases, maximum transfer rate become fMCK/4. 2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). In addition, CSI00 (channel 0 of unit 0) supports the SNOOZE mode. When SCK00 pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only CSI00 can be specified. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 356 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.1.2 UART (UART0 to UART2) This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission (even-numbered channel) and a channel dedicated to reception (odd-numbered channel). For details about the settings, see 11.6 Operation of UART (UART0 to UART2) Communication. [Data transmission/reception] * Data length of 7, 8, or 9 bits (Only UART0 can be specified for the 9-bit data length) * Select the MSB/LSB first * Level setting of transmit/receive data and select of reverse * Parity bit appending and parity check functions * Stop bit appending [Interrupt function] * Transfer end interrupt/buffer empty interrupt * Error interrupt in case of framing error, parity error, or overrun error [Error detection flag] * Framing error, parity error, or overrun error In addition, UART0 reception (channel 1 of unit 0) supports the SNOOZE mode. When RxD0 pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 357 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20) This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM, flash memory, or A/D converter, and therefore, it functions only as a master. Make sure by using software, as well as operating the control registers, that the AC specifications of the start and stop conditions are observed. For details about the settings, see 11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20). [Data transmission/reception] * Master transmission, master reception (only master function with a single master) * ACK output functionNote and ACK detection function * Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) * Manual generation of start condition and stop condition [Interrupt function] * Transfer end interrupt [Error detection flag] * ACK error, or overrun error * [Functions not supported by simplified I2C] * Slave transmission, slave reception * Arbitration loss detection function * Wait detection functions Note When receiving the last data, 0 is written to the SOEmn bit of the serial output enable register m (SOEm) and serial communication data output is stopped, disabling ACK output. See the processing flow in 11.7.3 (2) for details. m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3), mn = 00, 01, 03, 10 Remark To use a fully functional I2C bus, see CHAPTER 12 SERIAL INTERFACE IICA. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 358 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.2 Configuration of Serial Array Unit The serial array unit includes the following hardware. Table 11-1. Configuration of Serial Array Unit Item Configuration Note 1 Shift register 8 or 9 bits Buffer register Lower 8 or 9 bits of serial data register mn (SDRmn) Serial clock I/O SCK00, SCK01, SCK11, and SCK20 pins (for 3-wire serial I/O), SCL00, SCL01, SCL11, and 2 SCL20 pins (for simplified I C) Serial data input SI00, SI01, SI11, and SI20 pins (for 3-wire serial I/O), RxD0, RxD1, and RxD2 pins (for UART) Serial data output SI00, SI01, SI11, and SI20 pins (for 3-wire serial I/O), TxD0, TxD1, and TxD2 pins (for UART), Notes 1 , 2 output control circuit 2 Serial data I/O SDA00, SDA01, SDA11 and SDA20 pins (for simplified I C) Control registers <Registers of unit setting block> * Peripheral enable register 0 (PER0) * Serial clock select register m (SPSm) * Serial channel enable status register m (SEm) * Serial channel start register m (SSm) * Serial channel stop register m (STm) * Serial output enable register m (SOEm) * Serial output register m (SOm) * Serial output level register m (SOLm) * Serial standby control register m (SSCm) * Noise filter enable register 0 (NFEN0) <Registers of each channel> * Serial data register mn (SDRmn) * Serial mode register mn (SMRmn) * Serial communication operation setting register mn (SCRmn) * Serial status register mn (SSRmn) * Serial flag clear trigger register mn (SIRmn) * Port input mode register 0, 1 (PIM0, PIM1) * Port output mode registers 1, 4, 5 (POM1, POM4, POM5) * Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4) * Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) * Port register 0, 1, 3 to 6 (P0, P1, P3 to P6) Notes 1. The number of bits used as shift register or buffer register varies depending on the unit or channel. mn = 00, 01: lower 9 bits, mn = 02, 03, 10, 11: lower 8 bits 2. The lower 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending on the communication mode. * During CSIp communication: SIOp (CSIp data register) * During UARTq reception: RXDq (UART0 receive data register) * During UARTq transmission: TXDq (UART0 transmit data register) * During IICr communication: Remark SIOr (IICr data register) m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q: UART number (q = 0 to 2), r: IIC number (r = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 359 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-1 or 11-2 shows the block diagram of the serial array unit 0. Figure 11-1. Block Diagram of Serial Array Unit 0 (20- or 24-pin products) Noise filter enable register 0 (NFEN0) Serial output register 0 (SO0) 0 Peripheral enable register 0 (PER0) 0 PRS 012 PRS 011 PRS 003 PRS 010 PRS 002 4 0 0 0 SO03 SO02 SO01 PRS 001 PRS 000 4 SE03 SE02 SE01 SE00 Serial channel enable status register 0 (SE0) SS03 SS02 SS01 SS00 Serial channel start register 0 (SS0) ST03 ST02 ST00 Serial channel stop register 0 (ST0) fCLK/20 to fCLK/215 fCLK/20 to fCLK/215 CK00 0 (Clock division setting block) Clock controller Edge detection fSCK Serial data output pin (when CSI00: SO00) (when IIC00: SDA00) (when UART0: TXD0) Shift register Output controller Mode selection CSI00 or IIC00 or UART0 (for transmission) Noise elimination enabled/ disabled Interrupt controller CKS00 CCS00 STS00 MD002 MD001 Serial mode register 00 (SMR00) DAP 00 CKP 00 When UART0 PTC 001 PTC 000 DIR 00 SLC 001 SLC 000 PECT OVCT 00 00 Clear Error controller DLS 001 DLS 000 TSF 00 BFF 00 PEF 00 OVF 00 Serial status register 00 (SSR00) CK00 Serial data output pin (when CSI01: SO01) (when IIC01: SDA01) Channel 1 Communication controller Synchronous circuit Selector R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Edge/level detection Serial transfer end interrupt (when CSI00: INTCSI00) (when IIC00: INTIIC00) (when UART0: INTST0) Error information Serial communication operation setting register 00 (SCR00) CK01 Serial data input pin (when CSI01: SI01) (when IIC01: SDA01) EOC 00 Serial flag clear trigger register 00 (SIR00) Communication status Edge/level detection SNFEN00 Serial clock I/O pin (when CSI01: SCK01) (when IIC01: SCL01) Serial output level register 0 (SOL0) PMxx fTCLK Output latch (P10) PM10 RXE 00 SOL00 Output latch (Pxx) (Buffer register block) Communication controller TXE 00 0 SOL02 fMCK Selector Selector CK01 Synchronous circuit SSEC0 SWC0 Serial data register 00 (SDR00) Channel 0 Serial data input pin (when CSI00: SI00) (when IIC00: SDA00) (when UART0: RxD0) ST01 Serial standby control register 0 (SSC0) Selector Selector Synchronous circuit SNFEN SNFEN 10 00 SO00 Serial output SOE03 SOE02 SOE01 SOE00 enable register 0 (SOE0) Prescaler fCLK Serial clock I/O pin (when CSI00: SCK00) (when IIC00: SCL00) 0 CKO03 CKO02 CKO01 CKO00 0 Serial clock select register 0 (SPS0) PRS 013 SAU0EN 0 Mode selection CSI01 or IIC01 or UART0 (for reception) Serial transfer end interrupt (when CSI01: INTCSI01) (when IIC01: INTIIC01) (when UART0: INTSR0) Error controller Serial transfer error interrupt (INTSRE0) 360 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-2. Block Diagram of Serial Array Unit 0 (30-pin products) Serial output register 0 (SO0) 0 0 Peripheral enable register 0 (PER0) SAU0EN 0 0 CKO03 CKO02 CKO01 CKO00 0 0 0 0 SO00 SE03 SE02 SE01 SE00 Serial channel enable status register 0 (SE0) SS03 SS02 SS01 SS00 Serial channel start register 0 (SS0) ST03 ST02 ST00 Serial channel stop register 0 (ST0) Serial clock select register 0 (SPS0) PRS 013 PRS 012 PRS 011 PRS 010 PRS 003 PRS 002 4 PRS 001 PRS 000 4 ST01 SOE03 SOE02 SOE01 SOE00 Prescaler fCLK 0 fCLK/20 to fCLK/215 Selector Noise filter enable register 0 (NFEN0) SO03 SO02 SO01 SOL02 0 SOL00 fCLK/20 to fCLK/215 SNFEN SNFEN 10 00 Serial standby control register 0 (SSC0) SSEC0 SWC0 Serial output enable register 0 (SOE0) Serial output level register 0 (SOL0) Selector Serial data register 00 (SDR00) CK00 (Clock division setting block) Selector CK01 Serial clock I/O pin (when CSI00: SCK00) (when IIC00: SCL00) Selector Synchronous circuit fSCK Edge detection Output latch (P1x) (Buffer register block) Serial data output pin (when CSI00: SO00) (when IIC00: SDA00) (when UART0: TXD0) fTCLK Shift register Output controller Interrupt controller Communication controller Synchronous circuit Noise elimination enabled/ disabled Edge/ level detection SNFEN00 CKS00 CCS00 STS00 MD002 MD001 Serial mode register 00 (SMR00) Serial transfer end interrupt (when CSI00: INTCSI00) (when IIC00: INTIIC00) (when UART0: INTST0) Serial flag clear trigger register 00 (SIR00) PECT OVCT 00 00 Communication status Serial data input pin (when CSI00: SI00) (when IIC00: SDA00) (when UART0: RxD0) Mode selection CSI00 or IIC00 or UART0 (for transmission) Output latch (P10) PM10 PM1x fMCK Clock controller Channel 0 Clear Error controller Error information When UART0 TXE 00 RXE 00 DAP 00 CKP 00 EOC 00 PTC 001 PTC 000 DIR 00 SLC 001 SLC 000 Serial communication operation setting register 00 (SCR00) DLS 001 DLS 000 TSF 00 BFF 00 PEF 00 OVF 00 Serial status register 00 (SSR00) CK00 CK01 Channel 1 Communication controller Edge/level detection Selector CK01 Synchronous circuit Serial transfer end interrupt (when UART0: INTSR0) Error controller Serial data output pin (when UART1: TXD1) Communication controller Noise elimination enabled/ disabled Serial transfer end interrupt (INTSRE0) CK00 Channel 2 Serial data input pin (when UART1: RxD1) Mode selection CSI01 or IIC01 or UART0 (for reception) Edge/level detection Mode selection CSI10 or IIC10 or UART1 (for transmission) Serial transfer end interrupt (when UART1: INTST1) SNFEN10 CK01 When UART1 Serial clock I/O pin (when CSI11: SCK11) (when IIC11: SCL11) Serial data input pin (when CSI11: SI11) (when IIC11: SDA11) CK00 Channel 3 Synchronous circuit R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Serial data output pin (when CSI11: SO11) (when IIC11: SDA11) Communication controller Selector Edge/level detection Mode selection CSI11 or IIC11 or UART1 (for reception) Serial transfer end interrupt (when CSI11: INTCSI11) (when IIC11: INTIIC11) (when UART1: INTSR1) Error controller Serial transfer error interrupt (INTSRE1) 361 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-3 shows the block diagram of the serial array unit 0. Figure 11-3. Block Diagram of Serial Array Unit 1 (30-pin products) Noise filter enable register 0 (NFEN0) Serial output register 1 (SO1) 0 Peripheral enable register 0 (PER0) SAU1EN 0 0 1 0 1 CKO11 CKO10 0 0 0 0 Serial clock select register 1 (SPS1) PRS 113 PRS 112 PRS 111 PRS 110 PRS 101 PRS 102 PRS 103 4 PRS 100 4 1 1 SO11 SO10 SNFEN 20 0 0 SE11 SE10 Serial standby Serial channel control register 1 enable status register 1 (SE1) (SSC0) 0 0 SS11 SS10 Serial channel start register 1 (SS1) ST10 Serial channel stop register 1 (ST1) 0 0 0 0 0 0 ST11 Serial output SOE11 SOE10 enable register 0 (SOE1) Prescaler fCLK fCLK/20 to fCLK/215 fCLK/20 to fCLK/215 Selector SSEC1 SWC1 0 SOL10 Serial output level register 0 (SOL1) Selector Serial data register 10 (SDR10) (Clock division setting block) Selector CK10 Serial clock I/O pin (when CSI20: SCK20) (when IIC20: SCL20) Synchronous circuit fSCK Edge detection Output latch (P14 or P13) (Buffer register block) Serial data output pin (when CSI20: SO20) (when IIC20: SDA20) (when UART2: TXD2) fTCLK Shift register Output controller Interrupt controller Communication controller Synchronous circuit Noise elimination enabled/ disabled Edge/ level detection SNFEN20 Serial flag clear trigger register 10 (SIR10) CKS10 CCS10 MD102 MD101 Serial mode register 10 (SMR10) Serial transfer end interrupt (when CSI20: INTCSI20) (when IIC20: INTIIC20) (when UART2: INTST2) PECT OVCT 10 10 Communication status Serial data input pin (when CSI20: SI20) (when IIC20: SDA20) (when UART2: RxD2) Mode selection CSI20 or IIC20 or UART2 (for transmission) Output latch (P15) PM15 PM14 or PM13 fMCK Clock controller CK11 Selector Channel 0 Clear Error controller Error information TXE 10 RXE 10 When UART2 DAP 10 CKP 10 EOC 10 PTC 101 DIR 10 SLC 101 SLC 100 TSF 10 DLS 100 BFF 10 PEF 10 OVF 10 Serial status register 10 (SSR10) Serial communication operation setting register 10 (SCR10) CK11 CK10 Channel 1 Communication controller Selector <R> PTC 100 Edge/level detection Mode selection CSI21 or IIC21 or UART2 (for reception) Serial transfer end interrupt (when UART2: INTSR2) Error controller Serial transfer error interrupt (INTSRE2) The serial array unit 1 is available only in the 30-pin R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 362 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Shift register This is an 8-bit register that converts parallel data into serial data or vice versa. In case of the UART communication of nine bits of data using UART0, nine bits (bits 0 to 8) are used. During reception, it converts data input to the serial pin into parallel data. When data is transmitted, the value set to this register is output as serial data from the serial output pin. The shift register cannot be directly manipulated by program. To read or write to the shift register, use the lower 8/9 bits of serial data register mn (SDRmn). 8 7 6 5 4 3 2 1 0 Shift register (2) Lower 8/9 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00 and SDR01 or Bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, and SDR11 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (fMCK, fSCK). When data is received, parallel data converted by the shift register is stored in the lower 8/9 bits. When data is to be transmitted, set transmit data to be transferred to the shift register to the lower 8/9 bits. The length of data stored in the lower 8/9 bits of this register is as follows, depending on the setting of bits 0 and 1 (DLSmn0, DLS0m1) of serial communication operation setting register mn (SCRmn), regardless of the output sequence of the data. * 7-bit data length (stored in bits 0 to 6 of SDRmn register) * 8-bit data length (stored in bits 0 to 7 of SDRmn register) * 9-bit data length (stored in bits 0 to 8 of SDRmn register (mn = 00, 01)) (settable in UART0 mode only) The SDRmn register can be read or written in 16-bit units. The lower 8/9 bits of the SDRmn register can be read or written in 8-bit units as the following SFR, depending on the communication mode. Note, however, writing in 8-bits units is prohibited when the operation is stopped (SEmn = 0). * During CSIp communication: SIOp (CSIp data register) * During UARTq reception: RXDq (UARTq receive data register) * During UARTq transmission: TXDq (UARTq transmit data register) * During IICr communication: SIOr (IICr data register) Reset signal generation clears the SDRmn register to 0000H. Remarks 1. After data is received, "0" is applied to some bits of bits 0 to 8 to make up the specified data length. 2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q: UART number (q = 0 to 2), r: IIC number (r = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 363 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-4. Format of Serial Data Register mn (SDRmn) (mn = 00, 01) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H FFF11H (SDR00) 15 14 13 12 11 10 R/W FFF11H (SDR00) 9 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0 SDR0n Shift register Remark For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial Array Unit. Figure 11-5. Format of Serial Data Register mn (SDRmn) (mn = 02, 03, 10, 11) Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) After reset: 0000H FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11) FFF45H (SDR02) 15 14 13 12 11 10 9 SDR0n 8 R/W FFF44H (SDR02) 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 0 8 Shift register Caution Remark Be sure to clear bit 8 to "0". For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial Array Unit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 364 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3 Registers Controlling Serial Array Unit Serial array unit is controlled by the following registers. * Peripheral enable register 0 (PER0) * Serial clock select register m (SPSm) * Serial mode register mn (SMRmn) * Serial communication operation setting register mn (SCRmn) * Serial data register mn (SDRmm) * Serial flag clear trigger register mn (SIRmn) * Serial status register mn (SSRmn) * Serial channel start register m (SSm) * Serial channel stop register m (STm) * Serial channel enable status register m (SEm) * Serial output enable register m (SOEm) * Serial output level register m (SOLm) * Serial output register m (SOm) * Serial standby control register m (SSCm) * Noise filter enable register 0 (NFEN0) * Port input mode registers 0, 1 (PIM0, PIM1) * Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) * Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4) * Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) * Port registers 0, 1, 3 to 6 (P0, P1, P3 to P6) Remark m: Unit number (m = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 n: Channel number (n = 0 to 3) 365 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.1 Peripheral enable register 0 (PER0) PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1. When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the PER0 register to 00H. Figure 11-6. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H Symbol PER0 After reset: 00H <7> 6 TMKAEN 0 R/W <5> ADCEN SAU1EN 0 <4> IICA0EN <3> SAU1EN Note <2> 1 <0> SAU0EN 0 TAU0EN Control of serial array unit 1 input clock supply Stops supply of input clock (fixed as "0" in 20- or 24-pin products). * SFR used by serial array unit 1 cannot be written. * Serial array unit 1 is in the reset status. 1 Enables input clock supply. * SFR used by serial array unit 1 can be read/written. SAU0EN 0 Control of serial array unit 0 input clock supply Stops supply of input clock. * SFR used by serial array unit 0 cannot be written. * Serial array unit 0 is in the reset status. 1 Enables input clock supply. * SFR used by serial array unit 0 can be read/written. Note Be sure to clear SAU1EN bit to "0" in 20- or 24-pin products. Cautions 1. When setting serial array unit m, be sure to set the SAUmEN bit to 1 first. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read (except for the noise filter enable register 0 (NFEN0), port input mode register x (PIMx), port output mode register x (POMx), port mode register xx (PMxx), port mode control register xx (PMCxx), and port register xx (Pxx)). 2. Be sure to clear the undefined bits to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 366 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.2 Serial clock select register m (SPSm) The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are commonly supplied to each channel. CKm1 is selected by bits 7 to 4 of the SPSm register, and CKm0 is selected by bits 3 to 0. Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1). The SPSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL. Reset signal generation clears the SPSm register to 0000H. Figure 11-7. Format of Serial Clock Select Register m (SPSm) Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPSm 0 0 0 0 0 0 0 0 PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 PRS PRS PRS PRS mk3 mk1 fCLK = fCLK = fCLK = fCLK = fCLK = fCLK = 2 MHz 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz 0 0 0 fCLK 2 MHz 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz 0 0 0 1 fCLK/2 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz 0 fCLK/2 2 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz fCLK/2 3 250 kHz 500 kHz 1 MHz 2 MHz 2.5 MHz 3 MHz fCLK/2 4 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz fCLK/2 5 62.5 kHz 125 kHz 250 kHz 500 kHz 625 kHz 750 kHz fCLK/2 6 31.3 kHz 62.5 kHz 125 kHz 250 kHz 313 kHz 375 kHz fCLK/2 7 15.6 kHz 31.2 kHz 62.5 kHz 125 kHz 156 kHz 187.5 kHz 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 1 1 1 0 1 0 1 1 0 0 0 fCLK/2 8 7.81 kHz 15.6 kHz 31.2 kHz 62.5 kHz 78.1 kHz 93.75 kHz 1 0 0 1 fCLK/2 9 3.91 kHz 7.8 kHz 15.6 kHz 31.2 kHz 39.1 kHz 46.88 kHz fCLK/2 10 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz fCLK/2 11 977 Hz 1.95 kHz 3.9 kHz 7.8 kHz 9.77 kHz 11.72 kHz fCLK/2 12 488 Hz 0.97 kHz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz fCLK/2 13 244 Hz 485 Hz 0.97 kHz 1.95 kHz 2.44 kHz 2.93 kHz fCLK/2 14 122 Hz 242 Hz 485 Hz 0.97 kHz 1.22 kHz 1.47 kHz fCLK/2 15 61 Hz 121 Hz 242 Hz 485 Hz 610 Hz 732 Hz 1 1 1 1 1 1 Note mk0 Note 0 0 <R> mk2 Section of operation clock (CKmk) 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Caution Be sure to clear bits 15 to 8 to "0". Remarks 1. fCLK: CPU/peripheral hardware clock frequency 2. m: Unit number (m = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 k = 0, 1 367 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.3 Serial mode register mn (SMRmn) The SMRmn register is a register that sets an operation mode of channel n. It is also used to select an operation clock (fMCK), specify whether the serial clock (fSCK) may be input or not, set a start trigger, an operation mode (CSI, UART, or I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the UART mode. Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the MDmn0 bit can be rewritten during operation. The SMRmn register can be set by a 16-bit memory manipulation instruction. Reset signal generation sets the SMRmn register to 0020H. Figure 11-8. Format of Serial Mode Register mn (SMRmn) (1/2) Address: F0110H, F0111H (SMR00), F0116H, F0117H (SMR03) After reset: 0020H R/W F0150H, F0151H (SMR10), F0152H, F0153H (SMR11) Symbol 15 14 13 12 11 10 9 SMRmn CKS CCS 0 0 0 0 0 mn mn CKS 8 7 STS 0 mn Note 6 5 4 3 SIS 1 0 0 mn0Note 2 1 0 MD MD MD mn2 mn1 mn0 Selection of operation clock (fMCK) of channel n mn 0 Operation clock CK00 set by the SPSm register 1 Operation clock CK01 set by the SPSm register Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated. CCS Selection of transfer clock (fTCLK) of channel n mn 0 Divided operation clock fMCK specified by the CKSmn bit 1 Clock input fSCK from the SCKp pin (slave transfer in CSI mode) Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the SDRmn register. STS Selection of start trigger source mn Note 2 0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I C). 1 Valid edge of the RXDq pin (selected for UART reception) Transfer is started when the above source is satisfied after 1 is set to the SSm register. Note Provided in the SMR01, SMR03, and SMR11 registers only. Caution Do not change the value of the undefined bits (fixed to 0 or 1). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q: UART number (q = 0 to 2) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 368 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-8. Format of Serial Mode Register mn (SMRmn) (2/2) Address: F0110H, F0111H (SMR00) to F0116H, F0117H (SMR03), After reset: 0020H R/W F0150H, F0151H (SMR10), F0152H, F0153H (SMR11) Symbol 15 14 13 12 11 10 9 SMRmn CKS CCS 0 0 0 0 0 mn mn 8 7 STS 0 mn SIS Note 6 5 4 3 SIS 1 0 0 mn0Note 2 1 0 MD MD MD mn2 mn1 mn0 Controls inversion of level of receive data of channel n in UART mode mn0 Note 0 Falling edge is detected as the start bit. The input communication data is captured as is. 1 Rising edge is detected as the start bit. The input communication data is inverted and captured. MD MD mn2 mn1 0 0 CSI mode 0 1 UART mode 1 0 Simplified I C mode 1 1 Setting prohibited Setting of operation mode of channel n 2 MD Selection of interrupt source of channel n mn0 0 Transfer end interrupt 1 Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.) For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has run out. Note Provided in the SMR01, SMR03, and SMR11 registers only. Caution Do not change the value of the undefined bits (fixed to 0 or 1). Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) 11.3.4 Serial communication operation setting register mn (SCRmn) The SCRmn register is a communication operation setting register of channel n. It is used to set a data transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit, start bit, stop bit, and data length. Rewriting the SCRmn register is prohibited when the register is in operation (when SEmn = 1). The SCRmn register can be set by a 16-bit memory manipulation instruction. Reset signal generation sets the SCRmn register to 0087H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 369 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2) Address: F0118H, F0119H (SCR00) to F011EH, F011FH (SCR03) After reset: 0087H R/W F0158H, F0159H (SCR10), F015AH, F015BH (SCR11) Symbol 15 14 13 12 11 10 9 8 7 6 SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 mn mn mn mn mn mn1 mn0 mn 4 SLCm SLC n1 Note 1 3 2 0 1 mn0 1 0 DLSm DLS n1 Note 2 mn0 Setting of operation mode of channel n TXEmn RXEmn 0 0 Disable communication. 0 1 Reception only 1 0 Transmission only 1 1 Transmission/reception DAPmn CKPmn 0 5 0 Selection of data and clock phase in CSI mode Type SCKp 1 SOp D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SIp input timing 0 1 SCKp 2 SOp SIp input timing 1 0 SCKp 3 D7 SOp D6 D5 D4 D3 D2 D1 D0 SIp input timing 1 1 SCKp 4 D7 SOp D6 D5 D4 D3 D2 D1 D0 SIp input timing 2 Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I C mode. Selection of masking of error interrupt signal (INTSREx (x = 0 to 3)) EOCmn 0 Masks error interrupt INTSREx (INTSR0 is not masked). 1 Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs). 2 Set EOCmn = 0 in the CSI mode, simplified I C mode, and during UART transmission Note 3 . Notes 1. Provided in the SCR00, SCR02, and SCR10 registers only. 2. Provided in the SCR00 and SCR01 registers only (others are fixed to 1). 3. If EOCmn is not cleared for CSImn, error interrupt INTSREn may be generated. Caution Be sure to set the bit 2 to "1", and clear the undefined bits to 0. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 370 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2) Address: F0118H, F0119H (SCR00), F011EH, F011FH (SCR03) After reset: 0087H R/W 5 F0158H, F0159H (SCR10), F015AH, F015BH (SCR11) Symbol 15 14 13 12 11 10 9 8 7 6 SCRmn TXE RXE DAP CKP 0 EOC PTC PTC DIR 0 mn mn mn mn mn mn1 mn0 mn PTC PTC mn1 mn0 0 0 4 SLCm SLC n1 Note 1 3 2 0 1 mn0 1 0 DLSm DLS n1 Note 2 mn0 Setting of parity bit in UART mode Transmission Reception Does not output the parity bit. Receives without parity Note 3 0 1 Outputs 0 parity . No parity judgment 1 0 Outputs even parity. Judged as even parity. 1 1 Outputs odd parity. Judges as odd parity. 2 Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I C mode. DIRmn Selection of data transfer sequence in CSI and UART modes 0 Inputs/outputs data with MSB first. 1 Inputs/outputs data with LSB first. 2 Be sure to clear DIRmn = 0 in the simplified I C mode. SLCm SLCm n1 Note 1 Setting of stop bit in UART mode n0 0 0 No stop bit 0 1 Stop bit length = 1 bit 1 0 Stop bit length = 2 bits (mn = 00, 02, 10 only) 1 1 Setting prohibited When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely transferred. 2 Set the stop bit length to 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I C mode. Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode. Setting of data length in CSI and UART modes DLSmn DLSmn 1 Note 2 0 0 1 9-bit data length (stored in bits 0 to 8 of the SDRmn register (mn = 00, 01)) (settable in UART0 mode only) 1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register) 1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register) Other than above Setting prohibited 2 Be sure to set DLSmn0 = 1 in the simplified I C mode. Notes 1. Provided in the SCR00, SCR02, and SCR10 registers only. 2. Provided in the SCR00 and SCR01 registers only (others are fixed to 1). 3. 0 is always added regardless of the data contents. Caution Be sure to set bit 2 to 1 and clear undefined bits to 0. Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 371 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.5 Higher 7 bits of the serial data register mn (SDRmn) The SDRmn register is the transmit/receive data register of channel n (16 bits). Bits 8 to 0 (lower 9 bits) of SDR00 and SDR01 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, and SDR11 function as a transmit/receive buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock (fMCK, fSCK). If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the operating clock divided by the division ratios specified by the higher 7 bits of the SDRmn register is used as the transfer clock. The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the parallel data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be transmitted to the shift register is set to the lower 8/9 bits. The SDRmn register can be read or written in 16-bit units. However, the higher 7 bits can be written or read only when the operation is stopped (SEmn = 0). During operation (SEmn = 1), a value is written only to the lower 8/9 bits of the SDRmn register. When the SDRmn register is read during operation, 0 is always read. Reset signal generation clears the SDRmn register to 0000H. Figure 11-10. Format of Serial Data Register mn (SDRmn) Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W FFF10H (SDR00) FFF11H (SDR00) Symbol 15 14 13 12 11 10 9 SDRmn 8 7 6 5 3 2 1 0 2 1 0 0 Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) After reset: 0000H R/W FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11) FFF45H (SDR02) Symbol 4 15 14 13 12 11 10 9 SDRmn FFF44H (SDR02) 8 7 6 5 4 3 0 SDRmn[15:9] Transfer clock setting by dividing the operating clock (fMCK) 0 0 0 0 0 0 0 fMCK/2, fSCK/2 (in CSI slave) 0 0 0 0 0 0 1 fMCK/4 0 0 0 0 0 1 0 fMCK/6 0 0 0 0 0 1 1 fMCK/8 * * * * * * * * * * * * * * * * * * * * * * * * 1 1 1 1 1 1 0 fMCK/254 1 1 1 1 1 1 1 fMCK/256 Cautions 1. Be sure to clear bit 8 of SDR02, SDR03, SDR10, and SDR11 registers to 0. 2. Setting SDRmn[15:9] = 0000000B to 0000001B is prohibited when UART is used. Set SDRmn[15:9] to 0000010B or greater. 3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9] to 0000001B or greater. 4. Do not write 8-bit data to the lower 8 bits if operation is stopped (SEmn = 0). Otherwise, the higher 7 bits are cleared to 0. Remarks 1. For the function of the lower 8/9 bits of the SDRmn register, see 11.2 Configuration of Serial Array Unit. 2. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 372 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.6 Serial flag clear trigger register mn (SIRmn) The SIRmn register is a trigger register that is used to clear each error flag of channel n. When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn, OVFmn) of serial status register mn (SSRmn) is cleared to 0. Because the SIRmn register is a trigger register, it is cleared immediately when the corresponding bit of the SSRmn register is cleared. The SIRmn register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL. Reset signal generation clears the SIRmn register to 0000H. Figure 11-11. Format of Serial Flag Clear Trigger Register mn (SIRmn) Address: F0108H, F0109H (SIR00), F010EH, F010FH (SIR03), After reset: 0000H R/W F0148H, F0149H (SIR10), F014AH, F014BH (SIR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 FECT PECT OVCT mn FECT 1 Note mn mn Clear trigger of framing error of channel n mn 0 Not cleared 1 Clears the FEFmn bit of the SSRmn register to 0. PECT Clear trigger of parity error flag of channel n mn 0 Not cleared 1 Clears the PEFmn bit of the SSRmn register to 0. OVCT Clear trigger of overrun error flag of channel n mn 0 Not cleared 1 Clears the OVFmn bit of the SSRmn register to 0. Note Provided in the SIR01, SIR03, SIR11 registers only. Caution Be sure to set undefined bits to 0 Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) 2. When the SIRmn register is read, 0000H is always read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 373 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.7 Serial status register mn (SSRmn) The SSRmn register indicates the communication status and error occurrence status of channel n. The errors indicated by this register are framing errors, parity errors, and overrun errors. The SSRmn register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SSRmn register can be read with an 8-bit memory manipulation instruction as SSRmnL. Reset signal generation clears the SSRmn register to 0000H. Figure 11-12. Format of Serial Status Register mn (SSRmn) (1/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03) After reset: 0000H R F0140H, F0141H (SSR10), F0142H, F0143H (SSR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn TSF 2 1 0 FEF PEF OVF mn mn mn Note Communication status indication flag of channel n mn 0 Communication is stopped or suspended. 1 Communication is in progress. <Clear conditions> * The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set to 1 (communication is suspended). * Communication ends. <Set condition> * Communication starts. BFF Buffer register status indication flag of channel n mn 0 Valid data is not stored in the SDRmn register. 1 Valid data is stored in the SDRmn register. <Clear conditions> * Transferring transmit data from the SDRmn register to the shift register ends during transmission. * Reading receive data from the SDRmn register ends during reception. * The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set to 1 (communication is enabled). <Set conditions> * Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1 (transmission or transmission and reception mode in each communication mode). * Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and reception mode in each communication mode). * A reception error occurs. Note Provided in the SSR01, SSR03, SSR11 registers only. Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the register is discarded and an overrun error (OVEmn = 1) is detected. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 374 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-12. Format of Serial Status Register mn (SSRmn) (2/2) Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03) After reset: 0000H R F0140H, F0141H (SSR10), F0142H, F0143H (SSR11) Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SSRmn 0 0 0 0 0 0 0 0 0 TSF BFF 0 0 mn mn FEF 2 1 0 FEF PEF OVF mn mn mn Note Framing error detection flag of channel n mn Note 0 No error occurs. 1 An error occurs (during UART reception). <Clear condition> * 1 is written to the FECTmn bit of the SIRmn register. <Set condition> * A stop bit is not detected when UART reception ends. PEF Parity / ACK error detection flag of channel n mn 0 No error occurs. 1 Parity error occurs (during UART reception) or ACK is not detected (during I C transmission). 2 <Clear condition> * 1 is written to the PECTmn bit of the SIRmn register. <Set condition> * The parity of the transmit data and the parity bit do not match when UART reception ends (parity error). 2 * No ACK signal is returned from the slave channel at the ACK reception timing during I C transmission (ACK is not detected). OVF Overrun error detection flag of channel n mn 0 No error occurs. 1 An error occurs <Clear condition> * 1 is written to the OVCTmn bit of the SIRmn register. <Set condition> * Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and reception mode in each communication mode). * Transmit data is not ready for slave transmission or transmission and reception in CSI mode. Note Provided in the SSR01, SSR03, SSR11 registers only. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 375 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.8 Serial channel start register m (SSm) The SSm register is a trigger register that is used to enable communication/count for each channel. When 1 is written to a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is set to 1 (operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediately when SEmn = 1. The SSm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSm register can be set with a 1-bit or 8-bit memory manipulation instruction with SSmL. Reset signal generation clears the SSm register to 0000H. Figure 11-13. Format of Serial Channel Start Register m (SSm) Address: F0122H, F0123H (SS0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SS0 0 0 0 0 0 0 0 0 0 0 0 0 Address: F0162H, F0163H (SS1) Symbol SS1 Note1 After reset: 0000H 3 2 0 SS03 SS02 SS01 SS00 Note1 Note1 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSmn 1 1 0 SS11 SS10 Operation start trigger of channel n 0 No trigger operation 1 Sets the SEmn bit to 1 and enters the communication wait status Note2 . Notes 1. 30-pin product only. 2. If set the SSmn = 1 to during a communication operation, will wait status to stop the communication. At this time, holding status value of control register and shift register, SCKmn and SOmn pins, and FEFmn, PEFmn, OVFmn flags. Cautions 1. Be sure to clear the undefined bits to 0. 2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to set SSmn to 1 after 4 or more fMCK clocks have elapsed. Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) 2. When the SSm register is read, 0000H is always read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 376 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.9 Serial channel stop register m (STm) The STm register is a trigger register that is used to enable stopping communication/count for each channel. When 1 is written to a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0. The STm register is set by a 16-bit memory manipulation instruction. The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction as STmL. Reset signal generation clears the STm register to 0000H. Figure 11-14. Format of Serial Channel Stop Register m (STm) Address: F0124H, F0125H (ST0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 ST0 0 0 0 0 0 0 0 0 0 0 0 0 Address: F0164H, F0165H (ST1) Symbol ST1 Note1 After reset: 0000H 3 2 0 ST03 ST02 ST01 ST00 Note1 Note1 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 STm 1 1 0 ST11 ST10 Operation stop trigger of channel n n 0 No trigger operation 1 Clears the SEmn bit to 0 and stops the communication operation Note2 Notes 1. 30-pin product only. 2. While holding the value of the control register and shift register, and the status of the, SCKmn, SOmn pins, FEFmn, PEFmn, OVFmn flag. Caution Be sure to clear the undefined bits to 0. Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) 2. When the STm register is read, 0000H is always read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 377 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.10 Serial channel enable status register m (SEm) The SEm register indicates whether the data transmission/reception operation of each channel is enabled or disabled. When 1 is written to a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1. When 1 is written to a bit of serial channel stop register m (STm), the corresponding bit of this register is cleared to 0. If the operation of channel n is enabled, the value of the CKOmn bit (serial clock output of channel n) of serial output register m (SOm) cannot be rewritten by software, and a value is output from the serial clock pin according to the communication operation. If the operation of channel n is disabled, the value of the CKOmn bit of the SOm register can be set by software and its value is output from the serial clock pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by software. The SEm register can be read by a 16-bit memory manipulation instruction. The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction as SEmL. Reset signal generation clears the SEm register to 0000H. Figure 11-15. Format of Serial Channel Enable Status Register m (SEm) Address: F0120H, F0121H (SE0) After reset: 0000H R Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SE0 0 0 0 0 0 0 0 0 0 0 0 0 Address: F0160H, F0161H (SE1) Symbol SE1 Note1 After reset: 0000H 3 2 0 SE03 SE02 SE01 SE00 Note Note R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SEmn 1 1 0 SE11 SE11 Indication of operation enable/disable status of channel n 0 Operation is disabled (stopped) 1 Operation is enabled. Note 30-pin product only. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 378 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.11 Serial output enable register m (SOEm) The SOEm register is used to enable or disable output of the serial communication operation of each channel. If serial output is enabled for channel n, the value of the SOmn bit of serial output register m (SOm) cannot be rewritten by software, and a value is output from the serial data output pin according to the communication operation. If serial output is disabled for channel n, the SOmn bit value of the SOm register can be set by software, and its value is output from the serial data output pin. In this way, any waveform, such as that of a start condition/stop condition, can be created by software. The SOEm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction as SOEmL. Reset signal generation clears the SOEm register to 0000H. Figure 11-16. Format of Serial Output Enable Register m (SOEm) Address: F012AH, F012BH(SOE0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SOE0 0 0 0 0 0 0 0 0 0 0 0 0 3 Symbol SOE1 Note1 After reset: 0000H 1 0 SOE0 SOE0 SOE0 SOE 3 Address: F016AH, F016BH(SOE1) 2 Note1 2 Note1 1 Note2 00 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOE 10 Serial output enable/disable of channel n SOEmn 0 Disables output by serial communication operation. 1 Enables output by serial communication operation. Notes 1. 30-pin product only. 2. 20-, 24-pin product only. Caution Be sure to clear the undefined bits to 0. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 379 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.12 Serial output register m (SOm) The SOm register is a buffer register for serial output of each channel. The value of the SOmn bit of this register is output from the serial data output pin of channel n. The value of the CKOmn bit of this register is output from the serial clock output pin of channel n. The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be changed only by a serial communication operation. The CKOmn bit of this register can be rewritten by software only when the channel operation is stopped (SEmn = 0). While channel operation is enabled (SEmn = 1), rewriting by software is ignored, and the value of the CKOmn bit can be changed only by a serial communication operation. To use the pin for serial interface as a port function pin, set the corresponding CKOmn and SOmn bit to 1. The SOm register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears the SOm register to 0F0FH. Figure 11-17. Format of Serial Output Register m (SOm) Address: F0128H, F0129H(SO0) After reset: 0F0FH R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 SO0 0 0 0 0 CKO 1 CKO CKO 0 0 0 0 01 00 03 Address: F0168H, F0169H(SO1) Symbol SO1 Note1 After reset: 0F0FH 3 SO 03 Note1 2 SO 02 Note1 1 0 SO SO 01 Note2 00 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 CKO 0 0 0 0 1 1 1 SO 10 10 Serial clock output of channel n CKOmn 0 Serial clock output value is "0". 1 Serial clock output value is "1". SOmn Serial data output of channel n 0 Serial data output value is "0". 1 Serial data output value is "1". Notes 1. 2. 30-pin product only. 20-, 24-pin product only. Caution Be sure to not change the undefined bits. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 380 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.13 Serial output level register m (SOLm) The SOLm register is used to set inversion of the data output level of each channel. This register can be set only in the UART mode. Be sure to set 0 to corresponding bit in the CSI mode and 2 simplified I C mode. Inverting channel n by using this register is reflected on pin output only when serial output is enabled (SOEmn = 1). When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is. Rewriting the SOLm register is prohibited during operation (SEmn = 1). The SOLm register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction as SOLmL. Reset signal generation clears the SOLm register to 0000H. Figure 11-18. Format of Serial Output Level Register m (SOLm) Address: F0134H, F0135H (SOL0) After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 SOL0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 SOL 0 SOL 02 Address: F0174H, F0175H (SOL1) Symbol SOL1 Note After reset: 0000H Note 00 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SOL 10 SOL Selects inversion of the level of the transmit data of channel n in UART mode mn 0 Communication data is output as is. 1 Communication data is inverted and output. Note 30-pin product only. Caution Be sure to clear the undefined bits to 0. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 381 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.14 Serial standby control register 0 (SSC0) The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when receiving CSI00 or UART0 serial data. The SSC0 register can be set by a 16-bit memory manipulation instruction. The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulation instruction as SSC0L. Reset signal generation clears the SSC0 register to 0000H. Caution The maximum transfer rate in the SNOOZE mode is as follows. * When using CSI00: 1 Mbps * When using UART0: 9600 bps Figure 11-19. Format of Serial Standby Control Register 0 (SSC0) Address: F0138H, F0139H After reset: 0000H R/W Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SSCm 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 SSEC SWC 0 SSEC 0 0 Selection of whether to enable or stop the generation of transfer end interrupts 0 0 Enable the generation of error interrupts (INTSRE0). In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared: * When the SWC0 bit is cleared to 0 * When the UART reception start bit is mistakenly detected 1 Stop the generation of error interrupts (INTSRE0). In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared: * When the SWC0 bit is cleared to 0 * When the UART reception start bit is mistakenly detected * When the transfer end interrupt generation timing is based on a parity error or framing error SWC0 Setting the SNOOZE mode 0 Do not use the SNOOZE mode function. 1 Use the SNOOZE mode function. When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed without operating the CPU (the SNOOZE mode). * The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited. * Even when using SNOOZE mode, be sure to set the SWC0 bit to 0 in normal operation mode and change it to 1 just before shifting to STOP mode. Also, be sure to change the SWC0 bit to 0 after returning from STOP mode to normal operation mode. If the SWC0 bit is left set to 1, will not transmit/receive normally in spite of the SNOOZE or normal operation mode. Caution Setting SSEC0, SWC0 = 1, 0 is prohibited. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 382 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.15 Noise filter enable register 0 (NFEN0) The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input pin to each channel. 2 Disable the noise filter of the pin used for CSI or simplified I C communication, by clearing the corresponding bit of this register to 0. Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to 1.When the noise filter is enabled, CPU/ peripheral hardware clock (fCLK) is synchronized with 2-clock match detection. When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware clock (fMCK). The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the NFEN0 register to 00H. Figure 11-20. Format of Noise Filter Enable Register 0 (NFEN0) Address: F0070H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 NFEN0 0 0 0 SNFEN20 0 SNFEN10 0 SNFEN00 SNFEN20 Use of noise filter of RxD2 pin (RxD2/P14) 0 Noise filter OFF 1 Noise filter ON Set the SNFEN20 bit to 1 to use the RxD2 pin. Clear the SNFEN20 bit to 0 to use other than the RxD2 pin. SNFEN10 Use of noise filter of RxD1 pin (RxD1/P01) 0 Noise filter OFF 1 Noise filter ON Set the SNFEN10 bit to 1 to use the RxD1 pin. Clear the SNFEN10 bit to 0 to use the other than RxD1 pin. SNFEN00 Use of noise filter of RXD0 pin (RxD0/ANI17/SI00/ SDA00 TOOLRxD/P11) 0 Noise filter OFF 1 Noise filter ON Set the SNFEN00 bit to 1 to use the RXD0 pin. Clear the SNFEN00 bit to 0 to use the other than RxD0 pin. Caution Be sure to clear undefined bits to "0". R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 383 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.16 Port input mode register 0, 1 (PIM0, PIM1) This register sets the input buffer of ports 0 and 1 in 1-bit units. The PIM0 and PIM1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the PIM0 and PIM1 registers to 00H. Figure 11-21. Format of Port Input Mode Register 0, 1 (PIM0, PIM1) 20- or 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM1 0 0 0 0 0 0 PIM11 PIM10 F0041H 00H R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PIM0 0 0 0 0 0 0 PIM01 0 F0040H 00H R/W PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 F0041H 00H R/W PIMmn Pmn pin input buffer selection (m = 0, 1; n = 0, 1, 3 to 7) 0 Normal input buffer 1 TTL input buffer R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 384 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.17 Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) These registers set the output mode of ports 1 and 4 in 1-bit units. In addition, POM0, POM1, POM4, POM5 register is set with PUxx register, whether or not to use the on-chip pullup resistor (see 4.3 (3) Pull-up resistor option registers (PUxx)). The POM1 and POM4 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears the POM1 and POM4 registers to 00H. Figure 11-22. Format of Port Output Mode Registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) 20- or 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM1 0 0 0 0 0 POM12 POM11 POM10 F0051H 00H R/W POM4 0 0 0 0 0 0 POM41 0 F0054H 00H R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W POM0 0 0 0 0 0 0 0 POM00 F0050H 00H R/W POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W POM5 0 0 0 0 0 0 0 POM50 F0055H 00H R/W POMmn Pmn pin output buffer selection (0, 1, 4, 5 ; n = 0 to 5, 7) 0 Normal output mode 1 N-ch open-drain output (VDD tolerance) mode R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 385 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.3.18 Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) These registers set input/output of ports 0, 1, and 3 to 6 in 1-bit units. When using the ports (such as P10/ANI16/PCLBUZ0/SCK00/SCL00) to be shared with the serial data output pin or serial clock output pin for serial data output or serial clock output, set the port mode register (PMxx) and port mode control register (PMCxx) bit corresponding to each port to 0. And set the port register (Pxx) bit corresponding to each port to 1 Example: Using 20, 24-pin product P10/ANI16/PCLBUZ0/SCK00/SCL00 for serial clock output Set the PMC10 bit of the port mode control register 1 to 0. Set the PM10 bit of the port mode register 1 to 0. Set the P10 bit of the port register 0 to 1. When using the ports (such as P10/ANI16/PCLBUZ0/SCK00/SCL00) to be shared with the serial data input pin or serial clock input pin for serial data input or serial clock input, set the port mode register (PMxx) bit corresponding to each port to 1. Also set the port mode control register (PMCxx) bit corresponding to each port to 0. At this time, the port register (Pxx) bit may be 0 or 1. Example: Using 20-, 24-pin product P10/ANI16/PCLBUZ0/SCK00/SCL00 for serial data input or serial clock input Set the PMC10 bit of the port mode control register 1 to 0. Set the PM10 bit of port mode register 1 to 1. Set the P10 bit of port register 1 to 0 or 1. The PM0, PM1, and PM3 to PM6 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets the PM0, PM1, and PM3 to PM6 registers to FFH. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 386 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-23. Format of Port Mode Registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) 20- or 24-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W 30-pin products Symbol 7 6 5 4 3 2 1 0 Address After reset R/W PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W PM5 1 1 1 1 1 1 PM51 PM50 FFF25H FFH R/W PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W PMmn Selection of Pmn pin I/O mode (m = 0, 1, 3 to 6; n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 387 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.4 Operation Stop Mode Each serial interface of serial array unit has the operation stop mode. In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the serial interface function alternate pins can be used as port function pins in this mode. 11.4.1 Stopping the operation by units The stopping of the operation by units is set by using peripheral enable register 0 (PER0). The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0. To stop the operation of serial array unit 1, set bit 3 (SAU1EN) to 0. Figure 11-24. Peripheral Enable Register 0 (PER0) Setting When Stopping Operation by Units (a) Peripheral enable register 0 (PER0) ... Set only the bit of SAU0 to be stopped to 0. 7 PER0 6 TMKAEN x 5 4 3 2 ADCEN IICA0EN SAU1ENNote SAU0EN x x 0/1 0/1 0 1 0 TAU0EN 0 x Control of SAUm input clock 0: Stops supply of input clock 1: Supplies input clock Note Provided only in 30-pin products. Cautions 1. If SAUmEN = 0, writing to a control register of serial array unit m is ignored, and, even if the register is read, only the default value is read Note that this does not apply to the following registers. * Noise filter enable register 0 (NFEN0) * Port input mode register 0, 1 (PIM0, PIM1) * Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) * Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) * Port registers 0, 1, 3 to 6 (P0, P1, P3 to P6) * Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4) 2. Be sure to clear the undefined bits to 0. Remark : Setting disabled (fixed by hardware) x: Bits not used with serial array units (depending on the settings of other peripheral functions) 0/1: Set to 0 or 1 depending on the usage of the user. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 388 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.4.2 Stopping the operation by channels The stopping of the operation by channels is set using each of the following registers. Figure 11-25. Each Register Setting When Stopping Operation by Channels (a) Serial channel stop register m (STm) ... This register is a trigger register that is used to enable stopping communication/count by each channel. 15 14 13 12 11 10 9 8 7 6 5 4 STm 0 0 0 0 0 0 0 0 0 0 0 0 3 2 ST03 ST02 Note1 Note1 0/1 1 0 STm1 STm0 0/1 0/1 0/1 1: Clears the SEmn bit to 0 and stops the communication operation * Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0. (b) Serial Channel Enable Status Register m (SEm) ... This register indicates whether data transmission/reception operation of each channel is enabled or stopped. 15 14 13 12 11 10 9 8 7 6 5 4 SEm 0 0 0 0 0 0 0 0 0 0 0 0 3 2 SE03 SE02 Note1 Note1 0/1 1 0 SEm1 SEm0 0/1 0/1 0/1 0: Operation stops * The SEm register is a read-only status register. Operation is stopped by using the STm register. For a channel whose operation is disabled, the value of the CKOmn bit of the SOm register can be set by software. (c) Serial output enable register m (SOEm) ... This register is a register that is used to enable or stop output of the serial communication operation of each channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 0/1 0/1 0/1 0 SOEm0 0/1 0: Stops output by serial communication operation * For channel n whose serial output is stopped, the SOmn bit value of the SOm register can be set by software. (d) Serial output register m (SOm) ...This register is a buffer register for serial output of each channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1: Serial clock output value is "1" 1 0/1 0/1 0 0 0 0 3 2 1 SO03 SO02 SO01 Note1 Note1 Note2 0/1 0/1 0/1 0 SOm0 0/1 1: Serial data output value is "1" * When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOmn bits to "1". Notes 1. Provided in the serial array unit 0 of 30-pin products only. 2. 20-, 24-pin products only. Remarks 1. 2. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3) : Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 389 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication This is a clocked communication function that uses three lines: serial clock (SCK) and serial data (SI and SO) lines. [Data transmission/reception] * Data length of 7 or 8 bits * Phase control of transmit/receive data * MSB/LSB first selectable * Level setting of transmit/receive data [Clock control] * Master/slave selection * Phase control of I/O clock * Setting of transfer period by prescaler and internal counter of each channel * Maximum transfer rate Notes1, 2 During master communication (CSI00): Max. fMCK/2 Note2 During master communication (other than CSI00): Max. fMCK/4 Note2 During slave communication: Max. fMCK/6 [Interrupt function] * Transfer end interrupt/buffer empty interrupt [Error detection flag] * Overrun error Notes 1. In master communication (CSI00), maximum transfer rate become fMCK/2 when the following three conditions. * 2.7 V VDD 5.5 V * fMCK 24 MHz * PIOR1 = 0 Other cases, maximum transfer rate become fMCK/4. 2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). In addition, CSI00 (channel 0 of unit 0) supports the SNOOZE mode. When SCK00 pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) are channels 0, 1, 3 of SAU0 and channel 0 of SAU1. 20- or 24-pin products Unit Channel Used as CSI Used as UART 0 CSI00 UART0 2 Used as Simplified I C IIC00 Note IIC01 Note 0 1 CSI01 Note 30-pin products Unit Channel Used as CSI 0 0 CSI00 Used as UART 2 Used as Simplified I C IIC00 UART0 1 - 2 - - UART1 1 Note 3 CSI11 0 CSI20 Note <R> Note - - IIC11 Note IIC20 UART2 1 Note Note Note - Provided in the R5F102 products only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 390 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 3-wire serial I/O (CSI00, CSI01, CIS10, CIS20) performs the following seven types of communication operations. * Master transmission (See 11.5.1.) * Master reception (See 11.5.2.) * Master transmission/reception (See 11.5.3.) * Slave transmission (See 11.5.4.) * Slave reception (See 11.5.5.) * Slave transmission/reception (See 11.5.6.) * SNOOZE mode function (for CSI00 only) (See 11.5.7.) 11.5.1 Master transmission Master transmission is that the RL78/G12 outputs a transfer clock and transmits data to another device. 3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SO00 SCK01, SO01 SCK11, SO11 SCK20, SO20 Interrupt INTCSI00 INTCSI01 INTCSI11 INTCSI20 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection None flag Transfer data 7 or 8 bits length Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00) 15 Min. fCLK/(2 x 2 x 128) [Hz] Data phase Note Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts at the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCR0n register * CKPmn = 0: Non-reverse (data output at the falling edge and data input at the rising edge of SCK) * CKPmn = 1: Reverse (data output at the rising edge and data input at the falling edge of SCK) Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral function characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fCLK: System clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 391 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 m 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 0 Transmit data (Transmit data setting) 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 0/1 0/1 3 2 1 SO03 SO02 SO01 Note2 SOm0 0/1 x 0/1 0/1 Note1 0 0 0 0 Note1 Communication starts when these bits are 1 if the clock phase is non-inversion (the CKPmn bit of the SCRmn = 0). If the clock phase is inverted (CKPmn = 1), communication starts when these bits are 0. (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 0/1 x 0/1 0/1 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note1 SS01 SSm0 0/1 x 0/1 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products. 2. 20-, 24-pin products only. Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 392 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-27. Initial Setting Procedure for Master Transmission Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Setting the SMRmn register Setting the SCRmn register Set the operation clock. Set an operation mode, etc. Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Setting the SOm register Set the initial output level of the serial clock (CKOmn) and serial data (SOmn). Changing setting of the SOEm register Set the SOEmn bit to 1 and enable data output of the target channel. Enable data output and clock output of Setting port the target channel by setting a port register and a port mode register. Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1 : to enable operation). Completing initial setting Setting of SAU is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 393 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-28. Procedure for Stopping Master Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 394 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-29. Procedure for Resuming Master Transmission Starting setting for resumpt Wait until stop the communication target (Essential) No Master ready? (slave) or communication operation completed Yes Disable data output and clock output of (Essential) Port manipulation the target channel by setting a port register and a port mode register. (Selective) Re-set the register to change the operation Changing setting of the SPSm register clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. Set the SOEmn bit to 0 to stop output (Selective) Changing setting of the SOEm register (Selective) Changing setting of the SOm register (Selective) from the target channel. Set the initial output level of the serial Changing setting of the SOEm register clock (CKOmn) and serial data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output and clock output of (Essential) Port manipulation the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register Completing resumption setting (SEmn = 1 : to enable operation). Setting is completed Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 395 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-30. Timing Chart of Master Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Transmit data 1 Shift register mn INTCSIp Shift operation Data transmission (8-bit length) Transmit data 2 Shift operation Data transmission (8-bit length) Transmit data 3 Shift operation Data transmission (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 396 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-31. Flowchart of Master Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 11-27. (Select Transfer end interrupt) Main routine Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmit completes When Transfer end interrupt is generated, it moves to interrupt processing routine Interrupt processing routine Transfer end interrupt No Transmitting next data? Yes Writing transmit data to SIOp (=SDRmn[7:0]) Sets communication completion flag Read transmit data, if any, from storage area and write it to SIOp. Update transmit data pointer. If not, set transmit end flag RETI Check completion of transmission by No Transmission completed? verifying transmit end flag Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 397 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-32. Timing Chart of Master Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <6> STmn SEmn SDRmn Transmit data 2 Transmit data 1 Transmit data 3 SCKp pin Transmit data 1 SOp pin Shift register mn INTCSIp Transmit data 2 Shift operation Transmit data 3 Shift operation Data transmission (8-bit length) Shift operation Data transmission (8-bit length) Data transmission (8-bit length) MDmn0 <4> TSFmn BFFmn <2><3> (Note) <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 398 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-33. Flowchart of Master Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 11-27. (Select buffer empty interrupt) Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Main routine Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to <2> SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmit completes When transfer end interrupt is generated, it moves to <3><5> interrupt processing routine. Buffer empty/transfer end interrupt Interrupt processing routine If transmit data is left, read them from storage area then write into SIOp, and update transmit data pointer and Number of communication data > 0? No number of transmit data. If no more transmit data, clear MDmn bit if it's set. If not, finish. Yes Writing transmit data to SIOp (=SDRmn[7:0]) No MDmn = 1? Yes <4> Subtract -1 from number of transmit data Clear MDmn0 bit to 0 Sets communication completion interrupt flag RETI No Check completion of transmission by Transmission completed? verifying transmit end flag Main routine Yes Write MDmn0 bit to 1 Disable interrupt (MASK) Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-32. Timing Chart of Master Transmission (in Continuous Transmission Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 399 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.2 Master reception Master reception is that the RL78/G12 outputs a transfer clock and receives data from other device. CSI00 CSI01 CSI11 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SI00 SCK01, SI01 SCK11, SI11 SCK20, SI20 Interrupt INTCSI00 INTCSI01 INTCSI11 INTCSI20 3-Wire Serial I/O Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00) 15 Note Min. fCLK/(2 x 2 x 128) [Hz] Data phase Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data input starts at the start of the operation of the serial clock. * DAPmn = 1: Data input starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-inversion * CKPmn = 1: Inverted Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fCLK: System clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 400 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 0 Receive data (Write FFH as dummy data.) 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 0/1 0/1 3 2 1 SO03 SO02 SO01 Note 2 SOm0 x x x x Note 1 0 0 0 0 Note 1 Communication starts when these bits are 1 if the clock phase is non-inversion (the CKPmn bit of the SCRmn = 0). If the clock phase is inverted (CKPmn = 1), communication starts when these bits are 0. (e) Serial output enable register m (SOEm) ... The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1 Note 1 Note 2 SOEm0 x x x x 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note 1 SSm1 SSm0 0/1 x 0/1 0/1 Note 1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products. 2. 20-, 24-pin products only. Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 401 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-35. Initial Setting Procedure for Master Reception Starting initial setting Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the transfer clock by dividing the operation Setting the SDRmn register clock (fMCK)). Set the initial output level of the serial Setting the SOm register clock (CKOmn). Enable clock output of the target channel by setting a port register and a port mode Setting port register. Set the SSmn bit of the target channel to 1 Writing to the SSm register (SEmn bit = 1: to enable operation). Setting is completed. Set dummy data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. End of initial setting Figure 11-36. Procedure for Stopping Master Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 402 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-37. Procedure for Resuming Master Reception Starting setting for resumption Wait until stop the communication target Completing master preparations? (Essential) No Yes Port manipulation (Essential) (slave) or communication operation completed Disable clock output of the target channel by setting a port register and a port mode register. (Selective) Re-set the register to change the operation Changing setting of the SPSm register clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. (Selective) Changing setting of the SOm register (Selective) Clearing error flag Set the initial output level of the serial clock (CKOmn). If the OVF flag remain set, clear this using serial flag clear trigger register mn (SIRmn). Enable clock output of the target channel Port manipulation (Essential) by setting a port register and a port mode register. (Essential) Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Setting is completed Completing resumption setting Sets dummy data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 403 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-38. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Dummy data for reception Write Receive data 1 Dummy data Write Read Receive data 2 Receive data 3 Dummy data Write Read Read SCKp pin SIp pin Shift register mn Receive data 1 Receive data 2 Reception & shift operation Reception & shift operation Receive data 3 Reception & shift operation INTCSIp Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 404 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-39. Flowchart of Master Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Setting receive data Enables interrupt Writing dummy data to SIOp (=SDRmn[7:0]) For the initial setting, refer to Figure 11-35. (Select Transfer end interrupt) Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing to SIOp makes SCKp signals out (communication starts) Wait for receive completes Interrupt processing routine When transfer end interrupt is generated, it moves to interrupt processing routine Transfer end interrupt generated? Reading receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area. Update receive data pointer and number of communication data. RETI No All reception completed? Check the number of communication data Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 405 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous reception mode) Figure 11-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn SDRmn Receive data 3 Dummy data Dummy data <2> Write <2> Write Receive data 2 Receive data 1 Dummy data <2> Write Read Read Read SCKp pin SIp pin Receive data 2 Receive data 1 Shift register mn Reception & shift operation Receive data 3 Reception & shift operation Reception & shift operation INTCSIp Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length) MDmn0 <5> TSFmn BFFmn <3> Caution <3> <4> <3> <4> <6> <7> The MDmn0 bit can be rewritten even during operation. However, rewrite it before receive of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last receive data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 11-41 Flowchart of Master Reception (in Continuous Reception Mode). 2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 406 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-41. Flowchart of Master Reception (in Continuous Reception Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 11-35. (Select buffer empty interrupt) <1> Main routine <2> Setting receive data Setting storage area of the receive data, number of communication data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing to SIOp makes SCKp signals out (communication starts) Writing dummy data to SIOp (=SDRmn[7:0]) Wait for receive completes When interrupt is generated, it moves to <3> <6> interrupt processing routine Buffer empty/transfer end interrupt BFFmn = 1? No Interrupt processing routine Yes <4> <7> Read receive data, if any, then write them to storage area, and update receive data pointer (also subtract -1 from number of transmit data) Reading receive data to SIOp (=SDRmn[7:0]) Subtract -1 from number of transmit data =0 Number of communication data? =1 <5> Clear MDmn0 bit to 0 2 <2> Writing dummy data to SIOp (=SDRmn[7:0]) RETI No Number of communication data = 0? When number of communication data becomes 0, receive completes Yes Main routine Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-40. Timing Chart of Master Reception (in Continuous Reception Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 407 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.3 Master transmission/reception Master transmission/reception is that the RL78/G12 outputs a transfer clock and transmits/receives data to/from other device. 3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK11, SI11, SO11 SCK20, SI20, SO20 INTCSI11 INTCSI20 Interrupt INTCSI00 INTCSI01 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection flag Overrun error detection flag (OVFmn) only Transfer data length 7 or 8 bits Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00) Min. fCLK/(2 x 2 Data phase 15 x 128) [Hz] Note Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data I/O starts at the start of the operation of the serial clock. * DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-inversion * CKPmn = 1: Inverted Data direction MSB or LSB first Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fCLK: System clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 408 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CK00 set by the SPS0 register 1: Prescaler output clock CK01 set by the SPS0 register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 1 0/1 0/1 10 9 8 7 6 5 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 SDRmn 14 13 12 11 10 9 Baud rate setting (Operation clock (fMCK) division setting) 8 7 6 5 4 3 2 1 0 0 Transmit data setting/receive data register 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 Om 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 0/1 0/1 3 2 1 SO03 SO02 SO01 Note2 SOm0 0/1 x 0/1 0/1 Note1 0 0 0 0 Note1 Communication starts when these bits are 1 if the clock phase is non-inversion (the CKPmn bit of the SCRmn = 0). If the clock phase is inverted (CKPmn = 1), communication starts when these bits are 0. (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 0/1 x 0/1 0/1 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note1 SSm1 SSm0 0/1 x 0/1 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products. 2. 20-, 24-pin products only. Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission/reception mode : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 409 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-43. Initial Setting Procedure for Master Transmission/Reception Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Set the initial output level of the serial Setting the SOm register clock (CKOmn) and serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output and clock output of Setting port the target channel by setting a port register and a port mode register. Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Setting is completed End of initial setting Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and start communication. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 410 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-44. Procedure for Stopping Master Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 411 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-45. Procedure for Resuming Master Transmission/Reception Starting setting for resumption (Essential) Completing slave preparations? No Yes (Selective) Port manipulation Wait until stop the communication target (slave) or communication operation completed Disable data output and clock output of the target channel by setting a port register and a port mode register. (Essential) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SDRmn register Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. (Selective) Changing setting of the SCRmn register Re-set the register to change serial communication operation setting register mn (SCRmn) setting. (Selective) Clearing error flag If the FEF, PEF, and OVF flags remain set, clear them using serial flag clear trigger register 0n (SIRmn). (Selective) Changing setting of the SOEm register (Selective) Changing setting of the SOm register (Selective) Changing setting of the SOEm register (Essential) Port manipulation (Essential) Writing to the SSm register Set the SOEmn bit to 0 to stop output from the target channel. Set the initial output level of the serial clock (CKOmn) and serial data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output and clock output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (SEmn = 1 : to enable operation). Completing resumption setting Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 412 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-46. Timing Chart of Master Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn =0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Write Receive data 1 Transmit data 2 Write Read Receive data 2 Receive data 3 Transmit data 3 Write Read Read SCKp pin SIp pin Shift register mn SOp pin Receive data 1 Reception & shift operation Transmit data 1 Receive data 2 Reception & shift operation Transmit data 2 Receive data 3 Reception & shift operation Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 413 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-47. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode) Starting CSI communication For the initial setting, refer to Figure 11-43. SAU default setting Main routine Setting transmission/reception data Enables interrupt (Select transfer end interrupt) Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing transmit data to SIOp (=SDRmn[7:0]) Wait for transmission/reception completes Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) When transfer end interrupt is generated, it moves to interrupt processing routine. Interrupt processing routine Transfer end interrupt Read receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area, update receive data pointer RETI No Transmission/reception completed? If there are the next data, it continues Yes Main routine Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 414 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Write Write Receive data 1 Transmit data 3 Write Read Receive data 3 Receive data 2 Read Read SCKp pin SIp pin Receive data 1 Shift register mn SOp pin Receive data 2 Reception & shift operation Transmit data 1 Receive data 3 Reception & shift operation Reception & shift operation Transmit data 2 Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) MDmn0 <5> TSFmn BFFmn <2><3> Note 1 <2> Note 2 <2> <4> <2> Note 2 <2> <4> <6> <7> Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. 2. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 11-49 Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). 2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 415 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting For the initial setting, refer to Figure 11-43. (Select buffer empty interrupt) Main routine Setting transmission/reception data Enables interrupt Setting storage data and number of data for transmission/reception data (Storage area, Transmission data pointer, Reception data, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Writing dummy data to <2> SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Writing to SIOp makes SOp and SCKp signals out (communication starts) Wait for transmission/reception completes When transmission/reception interrupt is generated, it moves to interrupt processing routine <3> <6> Interrupt processing routine Buffer empty/transfer end interrupt No BFFmn = 1? Yes <4> Except for initial interrupt, read data received then write them to storage area, and update receive data pointer Reading reception data to SIOp (=SDRmn[7:0]) <7> Subtract -1 from number of transmit data If transmit data is left (number of communication data is equal or grater than 2), read them from storage area then =0 Number of communication data? =1 write into SIOp, and update transmit data pointer. If it's waiting for the last data to receive (number of communication data is equal to 1), change interrupt timing to communication end 2 Writing transmit data to SIOp (=SDRmn[7:0]) <5> Clear MDmn0 bit to 0 RETI No Number of communication data = 0? Yes Disable interrupt (MASK) Main routine Write MDmn0 bit to 1 Yes Continuing Communication? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-48 Timing Chart of Master Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 416 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.4 Slave transmission Slave transmission is that the RL78/G12 transmits data to another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SO00 SCK01, SO01 SCK11, SO11 SCK20, SO20 INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection Overrun error detection flag (OVFmn) only flag Transfer data 7 or 8 bits length Notes 1, 2 Transfer rate Max. fMCK/6 [Hz] Data phase Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts at the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-inversion * CKPmn = 1: Inverted Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK11, and SCK20 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fMCK: Operation clock frequency of target channel fSCK: Serial clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 417 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-50. Example of Contents of Registers for Slave Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 1 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 13 SDRmn 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 0 Transmit data setting 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 x x 3 2 1 SO03 SO02 SO01 Note2 SOm0 0/1 x 0/1 0/1 Note1 0 0 0 0 Note1 (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 0/1 x 0/1 0/1 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note1 SSm1 SSm0 0/1 x 0/1 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products. 2. 20-, 24-pin products only. Remarks 1. mn = 00, 01, 03, 10 p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 418 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-51. Initial Setting Procedure for Slave Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Setting the SDRmn register Set bits 15 to 9 to 0000000B for baud rate setting. Setting the SOm register Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 Writing to the SSm register Completing initial setting (SEmn bit = 1 : to enable operation). Initial setting is completed. Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 419 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-52. Procedure for Stopping Slave Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 420 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-53. Procedure for Resuming Slave Transmission Starting setting for resumption (Essential) Completing master preparations? No Yes (Selective) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the operation (Selective) Changing setting of the SPSm register clock setting. Re-set the register to change serial (Selective) Changing setting of the SMRmn register mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register (Selective) Clearing error flag communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this using serial flag clear trigger register mn (SIRmn). (Selective) (Essential) Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output from the target channel. Changing setting of the SOm register Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable (Essential) Changing setting of the SOEm register output from the target channel. Enable data output of the target channel (Essential) Port manipulation (Essential) Writing to the SSm register (Essential) Starting communication by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (SEmn = 1 : to enable operation). Sets transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. Completing resumption setting Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 421 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-54. Timing Chart of Slave Transmission (in Single-Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Shift register mn INTCSIp Transmit data 1 Transmit data 2 Shift operation Shift operation Data transmission (8-bit length) Data transmission (8-bit length) Transmit data 3 Shift operation Data transmission (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 422 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-55. Flowchart of Slave Transmission (in Single-Transmission Mode) Starting CSI communication SAU default setting For the initial setting, refer to Figure 11-51. (Select transfer end interrupt) Set storage area and the number of data for transmit data Setting transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Start communication when master start providing the clock Wait for transmit completes When transmit end, interrupt is generated No Transfer end interrupt? Yes Clear interrupt request flag Yes Transmitting next data? Determine if it completes by counting number of communication data No Disable interrupt (MASK) Yes Continuing transmit? No Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 423 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> STmn <6> SEmn SDRmn Transmit data 1 Transmit data 2 Transmit data 3 SCKp pin SOp pin Transmit data 1 Shift register mn INTCSIp Transmit data 2 Shift operation Transmit data 3 Shift operation Data transmission (8-bit length) Shift operation Data transmission (8-bit length) Data transmission (8-bit length) MDmn0 <4> TSFmn BFFmn <2> <3> (Note) <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started. Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 424 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-57. Flowchart of Slave Transmission (in Continuous Transmission Mode) Starting setting <1> SAU default setting Main routine Setting transmit data For the initial setting, refer to Figure 11-51. (Select buffer empty interrupt) Set storage area and the number of data for transmit data (Storage area, Transmission data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) <2> Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data from buffer and write it to SIOp. Update transmit data pointer Start communication when master start providing the clock Wait for transmit completes When buffer empty/transfer end interrupt is generated, <3> <5> it moves to interrupt processing routine Interrupt processing routine Buffer empty/transfer end interrupt If transmit data is left, read them from storage area then write into Number of transmit data > 1? No SIOp, and update transmit data pointer. If not, change the interrupt to transmission complete Yes Reading transmit data Writing transmit data to SIOp (=SDRmn[7:0]) Subtract -1 from number of transmit data Clear MDmn0 bit to 0 <4> It is determined as follows depending on the number of communication data. [No] +2 or higher: Unwritten data to SIOp +1: Transmit data completion 0: During the last data received RETI [Yes] No -1: All data received completion Number of communication data = -1? Main routine Yes Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-56 Timing Chart of Slave Transmission (in Continuous Transmission Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 425 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.5 Slave reception Slave reception is that the RL78/G12 receives data from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 SCK00, SI00 SCK01, SI01 SCK11, SI11 SCK20, SI20 INTCSI00 INTCSI01 INTCSI11 INTCSI20 Pins used Interrupt CSI11 CSI20 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection Overrun error detection flag (OVFmn) only flag Transfer data 7 or 8 bits length Transfer rate Data phase Max. fMCK/6 [Hz] Notes 1, 2 . Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts at the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-inversion * CKPmn = 1: Inverted Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK11, and SCK20 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fMCK: Operation clock frequency of target channel fSCK: Serial clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 426 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 1 8 7 STSmn 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0 Interrupt source of channel n 0: Transfer end interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0/1 0/1 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 DLSmn1 DLSmn0 0 Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 13 SDRmn 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 3 2 1 0 SO03 SO02 SO01 Note2 SOm0 x x x x 1 0 Receive data 0 SIOp (d) Serial output register m (SOm) ...The Register that not used in this mode. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 x x Note1 0 0 0 0 Note1 (e) Serial output enable register m (SOEm) ...The Register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 x x x x 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note1 SSm1 SSm0 0/1 x 0/1 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products. 2. 20-, 24-pin products only. Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 427 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-59. Initial Setting Procedure for Slave Reception Starting initial settings Release the serial array unit from the Setting the PER0 register reset status and start clock supply. Set the operation clock. Setting the SPSm register Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set baud rate setting (bits 15 to 9) to Setting the SDRmn register 0000000B. Enable data input and clock input of the target channel by setting a port register Setting port and a port mode register. Set the SSmn bit of the target channel to 1 Writing to the SSm register (SEmn bit = 1: to enable operation). Wait for a clock from the master. Completing initial setting Caution After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial clock select register m (SPSm) after 4 or more fCLK clocks have elapsed. Figure 11-60. Procedure for Stopping Slave Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. (Essential) Changing setting of the SOEm register (Selective) Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 428 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-61. Procedure for Resuming Slave Reception Starting setting for resumption Wait until stop the communication target Completing master preparations? (Essential) No Yes (Essential) Port manipulation (Selective) Changing setting of the SPSm register (Selective) Changing setting of the SMRmn register (Selective) Changing setting of the SCRmn register (master) Disable clock output of the target channel by setting a port register and a port mode register. Re-set the register to change the operation clock setting. Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this (Selective) Clearing error flag using serial flag clear trigger register mn (SIRmn). Enable clock output of the target channel (Essential) Port manipulation by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register (SEmn bit = 1: to enable operation). Wait for a clock from the master. Completing resumption setting Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 429 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-reception mode) Figure 11-62. Timing Chart of Slave Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Receive data 1 Receive data 3 Receive data 2 Read Read Read SCKp pin SIp pin Shift register mn INTCSIp Receive data 1 Reception & shift operation Data reception (8-bit length) Receive data 2 Reception & shift operation Data reception (8-bit length) Receive data 3 Reception & shift operation Data reception (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 430 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-63. Flowchart of Slave Reception (in Single-Reception Mode) Starting CSI communication Main routine SAU default setting Ready for reception For the initial setting, refer to Figure 12-59. (Select transfer end interrupt only) Clear storage area setting and the number of receive data (Storage area, Reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Wait for recieve completes Start communication when master start providing the clock Interrupt processing routine When transmit end, interrupt is generated Transfer end interrupt Reading receive data to SIOp (=SDRmn[7:0]) Read receive data then writes to storage area, and counts up the number of receive data. Update receive data pointer. RETI No Reception completed? Check completion of number of receive data Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 431 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.6 Slave transmission/reception Slave transmission/reception is that the RL78/G12 transmits/receives data to/from another device in the state of a transfer clock being input from another device. 3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20 Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1 Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK11, SI11, SO11 SCK20, SI20, SO20 Interrupt INTCSI00 INTCSI01 INTCSI11 INTCSI20 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection Overrun error detection flag (OVFmn) only flag Transfer data 7 or 8 bits length Notes 1, 2 Transfer rate Max. fMCK/6 [Hz] Data phase Selectable by the DAPmn bit of the SCRmn register * DAPmn = 0: Data output starts at the start of the operation of the serial clock. * DAPmn = 1: Data output starts half a clock before the start of the serial clock operation. Clock phase Selectable by the CKPmn bit of the SCRmn register * CKPmn = 0: Non-inversion * CKPmn = 1: Inverted Data direction MSB or LSB first Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK11, SCK20 pins is sampled internally and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least fSCK/2 as set by the SDRmn register. 2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fMCK: Operation clock frequency of target channel fSCK: Serial clock frequency mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 432 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 1 7 STSmn CKSmn CCSmn 0/1 8 0 6 5 4 3 1 0 0 2 SISmn0 0 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 0 0 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 1 0/1 0/1 10 9 8 7 6 5 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0/1 4 3 2 0 1 SLCmn1 SLCmn0 0 0 0 0 DLSmn1 DLSmn0 Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. Selection of the data and clock phase (For details about the setting, see 11.3 Registers Controlling Serial Array Unit.) 1 1 0/1 Setting of data length 0: 7-bit data length 1: 8-bit data length (c) Serial data register mn (SDRmn) (lower 8 bits: SIOp) 15 14 13 SDRmn 12 11 10 9 0000000 Baud rate setting 8 7 6 5 4 3 2 1 0 0 Transmit data setting/receive data register 0 SIOp (d) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 x x 3 2 1 SO03 SO02 SO01 Note2 SOm0 0/1 x 0/1 0/1 Note1 0 0 0 0 Note1 (e) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 0/1 x 0/1 0/1 1 0 (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note1 SSm1 SSm0 0/1 x 0/1 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided in the serial array unit 0 of 30-pin products only. 2. 20-, 24-pin products only. Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 433 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-65. Initial Setting Procedure for Slave Transmission/Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set bits 15 to 9 to 0000000B for baud Setting the SDRmn register Setting the SOm register rate setting. Set the initial output level of the serial data (SOmn). Set the SOEmn bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Writing to the SSm register Set the SSmn bit of the target channel to 1 (SEmn bit = 1: to enable operation). Initial setting is completed. Completing initial setting Set transmit data to the SIOp register (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 434 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-66. Procedure for Stopping Slave Transmission/Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 435 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-67. Procedure for Resuming Slave Transmission/Reception Starting setting for resumption Completing master preparations? (Essential) No Yes (Essential) Port manipulation Wait until stop the communication target (master) Disable data output of the target channel by setting a port register and a port mode register. (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SMRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SCRmn register communication operation setting register mn (SCRmn) setting. If the OVF flag remain set, clear this using Clearing error flag (Selective) serial flag clear trigger register mn (SIRmn). (Selective) Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output from the target channel. Set the initial output level of the serial (Selective) Changing setting of the SOm register (Selective) Changing setting of the SOEm register (Essential) Port manipulation data (SOmn). Set the SOEmn bit to 1 and enable output from the target channel. Enable data output of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 (Essential) Writing to the SSm register (SEmn = 1 : to enable operation). Sets transmit data to the SIOp register (Essential) Starting communication (bits 7 to 0 of the SDRmn register) and wait for a clock from the master. Completing resumption setting Cautions 1. Be sure to set transmit data to the SlOp register before the clock from the master is started. 2. If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (master) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 436 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission/reception mode) Figure 11-68. Timing Chart of Slave Transmission/Reception (in Single-Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn STmn SEmn SDRmn Transmit data 1 Write Receive data 1 Transmit data 2 Write Read Receive data 2 Receive data 3 Transmit data 3 Write Read Read SCKp pin SIp pin Shift register mn SOp pin Receive data 1 Reception & shift operation Transmit data 1 Receive data 2 Reception & shift operation Transmit data 2 Receive data 3 Reception & shift operation Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) TSFmn Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 437 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-69. Flowchart of Slave Transmission/Reception (in Single- Transmission/Reception Mode) Starting CSI communication SAU default setting Setting transmission/reception data Main routine Enables interrupt Writing transmit data to SIOp (=SDRmn[7:0]) For the initial setting, refer to Figure 11-65 (Select Transfer end interrupt) Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). Read transmit data from storage area and write it to SIOp. Update transmit data pointer. Start communication when master start providing the clock Wait for transmission/reception completes Interrupt processing routine When transfer end interrupt is generated, it moves to interrupt processing routine Transfer end interrupt Reading receive data to SIOp (=SDRmn[7:0]) Read receive data and write it to storage area. receive data pointer. Update RETI No Transmission/reception completed? Yes Yes Transmission/reception next data? Update the number of communication data and confirm if next transmission/reception data is available No Disable interrupt (MASK) Main routine Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 438 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission/reception mode) Figure 11-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0) SSmn <1> <8> STmn SEmn SDRmn Transmit data 1 Transmit data 2 Write Write Receive data 1 Transmit data 3 Write Read Receive data 3 Receive data 2 Read Read SCKp pin SIp pin Receive data 1 Shift register mn SOp pin Receive data 2 Reception & shift operation Transmit data 1 Receive data 3 Reception & shift operation Reception & shift operation Transmit data 2 Transmit data 3 INTCSIp Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) MDmn0 <5> TSFmn BFFmn <2> <3> Note 1 <2> Note 2 <3> <4> <2> Note 2 <3> <4> <6> <7> Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. 2. The transmit data can be read by reading the SDRmn register during this period. At this time, the transfer operation is not affected. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it has been rewritten before the transfer end interrupt of the last transmit data. Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 11-71 Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode). 2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 439 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode) Starting setting <1> SAU default setting Main routine Setting transmission/reception data Enables interrupt For the initial setting, refer to Figure 11-65 (Select buffer empty interrupt) Setting storage area and number of data for transmission/reception data (Storage area, Transmission/reception data pointer, Number of communication data and Communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI) Start communication when master start providing the clock Wait for transmission completes When buffer empty/transfer end is generated, it moves interrupt processing routine <3> <6> Buffer empty/transfer end interrupt No Interrupt processing routine BFFmn = 1? Yes <4> Other than the first interrupt, read reception data then writes to storage area, update receive data pointer Read receive data to SIOp (=SDRmn[7:0]) <7> Subtract -1 from number of transmit data =0 Number of communication data? Yes =1 If transmit data is remained, read it from storage area and write it to SIOp. Update storage pointer. If transmit completion (number of communication data = 1), Change the transmission completion interrupt 2 <5> Writing transmit data to SIOp (=SDRmn[7:0]) Clear MDmn0 bit to 0 RETI No Number of communication data = 0? Yes Main routine Disable interrupt (MASK) Write MDmn0 bit to 1 Yes Communication continued? No <8> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0 End of communication Caution Be sure to set transmit data to the SlOp register before the clock from the master is started. Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-70 Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 440 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.7 SNOOZE mode function (only CSI00) SNOOZE mode makes CSI operate reception by SCKp pin input detection while the STOP mode. Normally CSI stops communication in the STOP mode. But, using the SNOOZE mode makes reception data unless the CPU operation. Only CSI00 can be set to the SNOOZE mode. When using the SNOOZE mode function, set the SWC0 bit of serial standby control register 0 (SSC0) to 1 before switching to the STOP mode. Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. 2. The maximum transfer rate when using CSI00 in the SNOOZE mode is 1 Mbps. (1) SNOOZE mode operation (once startup) Figure 11-72. Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAP00 = 0, CKP00 = 0) CPU operation status Normal peration <3> SS00 SNOOZE mode STOP mode Normal operation <4> <11> ST00 <1> <9> SE00 SWC0 SSEC0 <2> <10> L Receive data 2 Clock request signal (internal signal) Receive data 2 SDR00 Receive data 1 <8> Read Note 1 SCK00 pin SI00 pin Receive data 1 Shift register 00 INTCSI00 Receive data 2 Reception & shift operation Reception & shift operation Note 2 Data reception (8-bit length) Data reception (8-bit length) TSF00 <5><6> Notes 1. 2. <7> Only read received data while SWC0 = 1 and before the next edge of the SCK00 pin input is detected. The transfer end interrupt (INTCSI00) is cleared either when SWC0 is cleared to 0 or when the next edge of the SCK00 pin input is detected. Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the ST00 bit to 1 (clear the SE00 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release). Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-73. Flowchart of SNOOZE Mode Operation (once startup). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 441 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-73. Flowchart of SNOOZE Mode Operation (once startup) SNOOZE mode operation No TSF00 = 0 for all channels? Yes Normal operation <1> Write ST00 bit to 1 Become the operation STOP status (SE00 = 0) SAU default setting SMR00, SCR00 : SDR00[15:9] : <2> Setting SSCm register (SWC0 = 1, SSEC0 = 0) <3> Write SSm0 bit to 1 Enables interrupt <4> Entered the STOP mode STOP mode <5> Communication setting Setting 0000000B Setting SNOOZE mode Become the communication wait status (SE00 = 1) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). fCLK supplied to the SAU is stopped. SCK00 edge detected (Entered the SNOOZE mode) SNOOZE mode Supplying a clock to CSI00 (CSI00 is receive operation) <6> Transfer interrupt (INTCSI00) is generated (CSI00 is receive completion) <7> Normal operation <8> Reading receive data to SIOp (=SDR00[7:0]) <9> Write ST00 bit to 1 Become the operation STOP status (SE00 = 0) <10> Write SWC0 bit to 1 Reset SNOOZE mode setting <11> Write SS00 bit to 1 It becomes communication ready state (SE00 = 1) under normal operation The mode switches from SNOOZE to normal operation. End of SNOOZE mode Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-72. Timing Chart of SNOOZE Mode Operation (once startup). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 442 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (continuous startup) Figure 11-74. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAP00 = 0, CKP00 = 0) CPU operation status Normal peration <3> SS00 STOP mode SNOOZ mode Normal peration <4> <3> ST00 <1> STOP mode <4> SNOOZ mode <9> SE00 SWC0 SSEC0 <10> L Clock request signal (internal signal) Receive data 2 SDR00 Receive data 1 <8> Read Note 2 SCK00 pin SI00 pin Shift register 00 INTCSI00 Receive data 1 Receive data 2 Reception & shift operation Reception & shift operation Note 2 Data reception (8-bit length) Data reception (8-bit length) TSF00 <2> Notes 1. 2. <5><6> <7> <2> <5><6> Only read received data while SWC0 = 1 and before the next edge of the SCK00 pin input is detected. The transfer end interrupt (INTCSI00) is cleared either when SWC0 is cleared to 0 or when the next edge of the SCK00 pin input is detected. Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, set the ST00 bit to 1 (clear the SE00 bit, and stop the operation). And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE release). Remark <1> to <10> in the figure correspond to <1> to <10> in Figure 11-75. Flowchart of SNOOZE Mode Operation (continuous startup). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 443 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-75. Flowchart of SNOOZE Mode Operation (continuous startup) SNOOZE mode operatopn No TSF00 = 0 for all channels? Normal operation Yes <1> Write ST00 bit to 1 SAU default setting Become the operation STOP status (SE00 = 0) SMRm0, SCRm0 : Communication setting SDRm0[15:9] : <2> <3> Setting SSC0 register (SWC0 = 1, SSEC0 = 0) Write SS00 bit to 1 Enables interrupt STOP mode <4> Entered the STOP mode Setting SNOOZE mode Become the communication wait status (SE00 = 1) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). fCLK supplied to the SAU is stopped. SCK00 edge detected (Entered the SNOOZE mode) <5> SNOOZE mode Supplying a clock to CSI00 (CSI00 is receive operation) <6> Transfer interrupt (INTCSI00) is generated (CSI00 is receive completion) <7> Normal operation Remark Setting 0000000B <8> Reading receive data to SIOp (=SDR00[7:0]) <9> Write ST00 bit to 1 <10> Clear SWC0 bit to 0 The mode switches from SNOOZE to normal operation. Reset SNOOZE mode setting <1> to <10> in the figure correspond to <1> to <10> in Figure 11-74. Timing Chart of SNOOZE Mode Operation (continuous startup). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 444 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.5.8 Calculating transfer clock frequency The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communication can be calculated by the following expressions. (1) Master (Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} / (SDRmn[15:9] + 1) / 2 [Hz] (2) Slave (Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note [Hz] Note The permissible maximum transfer clock frequency is fMCK/6. Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to 1111111B) and therefore is 0 to 127. The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 445 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Table 11-2. Selection of Operation Clock For 3-Wire Serial I/O SMRmn Register SPS0 Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 Operation Clock (fMCK) Note fCLK = 20 MHz X X X X 0 0 0 0 fCLK X X X X 0 0 0 1 fCLK/2 20 MHz 10 MHz X X X X 0 0 1 0 fCLK/2 2 X X X X 0 0 1 1 fCLK/2 3 2.5 MHz 1.25 MHz 5 MHz X X X X 0 1 0 0 fCLK/2 4 X X X X 0 1 0 1 fCLK/2 5 625 kHz 312.5 kHz X X X X 0 1 1 0 fCLK/2 6 X X X X 0 1 1 1 fCLK/2 7 156.2 kHz 78.1 kHz X X X X 1 0 0 0 fCLK/2 8 X X X X 1 0 0 1 fCLK/2 9 39.1 kHz X X X X 1 0 1 0 fCLK/2 10 19.5kHz X X X X 1 0 1 1 fCLK/2 11 9.77 kHz X X X X 1 1 0 0 fCLK/2 12 4.88 kHz 2.44 kHz 1.22 kHz X X X X 1 1 0 1 fCLK/2 13 X X X X 1 1 1 0 fCLK/2 14 15 X X X X 1 1 1 1 fCLK/2 0 0 0 0 X X X X fCLK 1 610 Hz 20 MHz 0 0 0 1 X X X X fCLK/2 0 0 1 0 X X X X fCLK/2 2 5 MHz 10 MHz 0 0 1 1 X X X X fCLK/2 3 2.5 MHz 0 1 0 0 X X X X fCLK/2 4 1.25 MHz 625 kHz 0 1 0 1 X X X X fCLK/2 5 0 1 1 0 X X X X fCLK/2 6 312.5 kHz 0 1 1 1 X X X X fCLK/2 7 156.2 kHz 78.1 kHz 39.1 kHz 1 0 0 0 X X X X fCLK/2 8 1 0 0 1 X X X X fCLK/2 9 19.5 kHz 1 0 1 0 X X X X fCLK/2 10 1 0 1 1 X X X X fCLK/2 11 9.77 kHz 1 1 0 0 X X X X fCLK/2 12 4.88 kHz 1 1 0 1 X X X X fCLK/2 13 2.44 kHz 1.22 kHz 610 Hz 1 1 1 0 X X X X fCLK/2 14 1 1 1 1 X X X X fCLK/2 15 Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. X: don't care 2. m = unit number (m=0, 1), mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 446 RL78/G12 11.5.9 CHAPTER 11 SERIAL ARRAY UNIT Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communication The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communication is described in Figure 11-77. Figure 11-76. Processing Procedure in Case of Overrun Error Software Manipulation Hardware Status Remark Reads serial data register mn (SDRmn). The BFFmn bit of the SSRmn register is This is to prevent an overrun error if the set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn Error type is identified and the read (SSRmn). value is used to clear error flag. Writes 1 to serial flag clear trigger register mn (SIRmn). Error flag is cleared. Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Remark mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 447 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6 Operation of UART (UART0 to UART2) Communication This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception (RXD) lines. By using these two communication lines, each data frame, which consists of a start bit, data, parity bit, and stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission (an even-numbered channel) and a channel dedicated to reception (an odd-numbered channel). [Data transmission/reception] * Data length of 7, 8, or 9 bits (Only UART0 can be specified for the 9-bit data length) * Select the MSB/LSB first * Level setting of transmit/receive data and select of reverse (selecting whether to reverse the level) * Parity bit appending and parity check functions * Stop bit appending and stop bit check functions [Interrupt function] * Transfer end interrupt/buffer empty interrupt * Error interrupt in case of framing error, parity error, or overrun error [Error detection flag] * Framing error, parity error, or overrun error UART0 is compatible with SNOOZE mode. When RxD0 pin input is detected while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. 20- or 24-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 CSI01 Note 2 Used as Simplified I C IIC00 Note Note IIC01 30-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 - 2 - 1 <R> CSI11 0 CSI20 1 - Note IIC00 Note - UART1 Note 3 2 Used as Simplified I C - IIC11 UART2 Note Note IIC20 Note - Note Provided in the R5F102 products only. Caution When using a serial array unit for UART, both the transmitter side (even-numbered channel) and the receiver side (odd-numbered channel) can only be used for UART. UART performs the following four types of communication operations. * UART transmission (See 11.6.1.) * UART reception (See 11.6.2.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 448 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6.1 UART transmission UART transmission is an operation to transmit data from the RL78/G12 to another device asynchronously (start-stop synchronization). Of the two channels used for UART, the even-numbered channel is used for UART transmission. UART UART0 UART1 UART2 Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1 Pins used TxD0 TxD1 TxD2 Interrupt INTST0 INTST1 INTST2 Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode) can be selected. Error detection None flag Transfer data 7, 8, or 9 bits (UART0 only) length 15 Transfer rate Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or greater, Min. fCLK/(2 x 2 x 128) [bps] Data phase Non-inverted output (default: high level) Note Inverted output (default: low level) Parity bit The following selectable * No parity bit * Appending 0 parity * Appending even parity * Appending odd parity Stop bit The following selectable * Appending 1 bit * Appending 2 bits Data direction Note MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral function characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. fMCK: Operation clock frequency of target channel fCLK: 2. System clock frequency m: Unit number (m = 0, 1) n: Channel number (n = 0, 2), mn = 00, 02, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 449 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-77. Example of Contents of Registers for UART Transmission (UART0 to UART2) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 0 0 CKSmn CCSmn 0/1 0 2 1 0 MDmn2 MDmn1 MDmn0 Operation clock (fMCK) of channel n 0: Prescaler output clock CK00 set by the SPS0 register 1: Prescaler output clock CK01 set by the SPS0 register 0 1 0/1 Interrupt source of channel n 0: Transfer end interrupt 1: Buffer empty interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0/1 0/1 0/1 5 4 2 0 0/1 0/1 1 DLSmn1 SLCmn1 SLCmn0 0 1 0 Note1 DLSmn0 0/1 0/1 Setting of stop bit 01B: Appending 1 bit 10B: Appending 2 bits Setting of parity bit 00B: No parity 01B: Appending 0 parity 10B: Appending Even parity 11B: Appending Odd parity 3 Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. (c) Serial data register mn (SDRmn) (lower 8 bits: TXDq) 15 14 13 SDRmn 12 11 10 9 8 7 6 5 Baud rate setting 4 3 2 1 0 1 0 Transmit data setting 0 Note2 TXDq (d) Serial output level register m (SOLm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOLm2 SOLm SOLm0 Note3 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0/1 0: Non-inverted transmission 1: Inverted transmission Notes 1. 2. Provided only in SCR00 register (UART0) only. For SCR02 and SCR10 registers, fixed as 1. When performs 9-bit communication (by setting the DLS001 and DLS000 bits of the SMR00 register to 1), bits 0 to 8 of the SDR00 register are used as the transmission data specification area. 9-bit communication is available only in UART0. 3. Provided only in 30-pin product serial array unit 0. Remarks 1. q: UART number (q = 0 to 2), mn = 00, 02, 10 2. Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 450 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-77. Example of Contents of Registers for UART Transmission (UART0 to UART2) (2/2) (e) Serial output register m (SOm) ... Sets only the bits of the target channel. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 SO03 Note 1 CKOm1 CKOm0 0 0 0 0 1 1 x x 3 0 0 0 0 x 2 1 SO02 Note 1 SO01 x 0/1 Note 2 0 SOm0 0/1Note 2 0: Serial data output value is "0" 1: Serial data output value is "1" (f) Serial output enable register m (SOEm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOE03 SOE02 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 Note 1 Note 1 x 0/1 1 0 SOE01 SOEm0 x 0/1 1 0 (g) Serial channel start register m (SSm) ... Sets only the bits of the target channel to 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note 1 SSm1 SSm0 x 0/1 x 0/1 Note 1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided only in 30-pin product serial array unit 0. 2. Before transmission is started, be sure to set to 1 when the SOL00 bit of the target channel is set to 0, and set to 0 when the SOL00 bit of the target channel is set to 1. The value varies depending on the communication data during communication operation. Remarks 1. mn = 00, 02, 10 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 451 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-78. Initial Setting Procedure for UART Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Changing setting of the SOLm register Setting the SOm register Set an output data level. Set the initial output level of the serial data (SOm0). Set the SOEm0 bit to 1 and enable data Changing setting of the SOEm register output of the target channel. Enable data output of the target channel Setting port by setting a port register and a port mode register. Set the SSm0 bit of the target channel to 1 Writing to the SSm register and set the SEmn bit to 1 (to enable operation). Completing initial setting Initial setting is completed. Set transmit data to the TXDm register (bits 7 to 0 of the SDRm0 register) and start communication. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 452 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-79. Procedure for Stopping UART Transmission Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Essential) Changing setting of the SOEm register (Selective) Changing setting of the SOm register to operation stop status) Set the SOEmn bit to 0 and stop the output of the target channel. The levels of the serial clock (CKOmn) and serial data (SOmn) on the target channel can be changed if necessitated by an emergency. (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 453 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-80. Procedure for Resuming UART Transmission Starting setting for resumption Completing master preparations? (Essential) Yes (Selective) Port manipulation No Wait until stop the communication target or communication operation completed Disable data output of the target channel by setting a port register and a port mode register. Re-set the register to change the (Selective) Changing setting of the SPSmregister operation clock setting. Re-set the register to change the (Selective) Changing setting of the SDRmn register transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). (Selective) Changing setting of the SMRmn register (Selective) Changing setting of the SCRmn register Re-set the register to change serial mode register mn (SMRmn) setting. Re-set the register to change the serial communication operation setting register mn (SCRmn) setting. Re-set the register to change serial (Selective) Changing setting of the SOLmregister (Selective) Changing setting of the SOEmregister output level register m (SOLm) setting. Clear the SOEmn bit to 0 and stop output. (Selective) Changing setting of the SOmregister Set the initial output level of the serial data (SOmn). (Essential) Changing setting of the SOEmregister (Essential) Port manipulation Set the SOEmn bit to 1 and enable output. Enable data output of the target channel by setting a port register and a port mode register. (Essential) Writing to the SSm register Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Setting is completed Completing resumption setting Sets transmit data to the TXDq register (bits 7 to 0 of the SDRmn register) and start communication. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 454 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow (in single-transmission mode) Figure 11-81. Timing Chart of UART Transmission (in Single-Transmission Mode) SSmn STmn SEmn SDRmn TxDq pin Shift register mn Transmit data 1 ST Transmit data 1 Transmit data 2 P SP ST Shift operation Transmit data 2 Shift operation Transmit data 3 P SP ST Transmit data 3 P SP Shift operation INTSTq Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length) TSFmn Remark q: UART number (q = 0 to 2), mn = 00, 02, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 455 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-82. Flowchart of UART Transmission (in Single-Transmission Mode) Starting UART communication SAU default setting For the initial setting, refer to Figure 11-78. (Select transfer end interrupt) Main routine Set data for transmission and the number of data. Clear communication end flag Setting transmit data (Storage area, transmission data pointer, number of communication data and communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). When writing transmit data to (=SDRmn[7:0]), start to the transmissions operation. Wait for transmit completes When Transfer end interrupt is generated, it moves to interrupt processing routine Interrupt processing routine Transfer end interrupt No Transmitting next data? Yes Writing transmit data to SIOp (=SDRmn[7:0]) Read transmit data, if any, from storage area and write it to SIOp. Update transmit data pointer. If not, set transmit end flag Sets communication completion flag RETI Check completion of transmission by No Transmission completed? verifying transmit end flag Main routine Yes Disable interrupt (MASK) Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 456 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (4) Processing flow (in continuous transmission mode) Figure 11-83. Timing Chart of UART Transmission (in Continuous Transmission Mode) SSmn <1> <6> STmn SEmn SDRmn Transmit data 1 TxDq pin ST Shift register mn Transmit data 1 Transmit data 2 P SP ST Transmit data 3 Transmit data 2 P SP ST Shift operation Shift operation Transmit data 3 P SP Shift operation INTSTq Data transmission (7-bit length) Data transmission (7-bit length) Data transmission (7-bit length) MDmn0 <4> TSFmn BFFmn <2><3> Note <2> <3> <2> <3> <5> Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten. Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation. However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the transfer end interrupt of the last transmit data. Remark q: UART number (q = 0 to 2), mn = 00, 02, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 457 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-84. Flowchart of UART Transmission (in Continuous Transmission Mode) Starting UART communication <1> SAU default setting For the initial setting, refer to Figure 11-78. (Select buffer empty interrupt) Set data for transmission and the number of data. Setting transmit data Clear communication end flag (Storage area, Transmission data pointer, Number of communication data and Main routine Communication end flag are optionally set on the internal RAM by the software) Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI). <2> Writing transmit data to TXDq (=SDRmn[7:0]) Read transmit data from storage area and write it to TXDq. Update transmit data pointer. Communication starts by writing to SDRmn [7:0] Wait for transmit completes When transfer end interrupt is generated, it moves to interrupt processing routine. <3> Buffer empty/transfer end interrupt Interrupt processing routine If transmit data is left, read them from storage area then write into TxDq, and update transmit data pointer and No Number of communication data > 0? number of transmit data. If no more transmit data, clear MDmn bit if it's set. If not, finish. Yes <2> Writing transmit data to No MDmn = 1? TxDq (=SDRmn[7:0]) Yes <4> Subtract -1 from number of transmit data <5> Sets communication Clear MDmn0 bit to 0 completion interrupt flag RETI No Check completion of transmission by Transmission completed? verifying transmit end flag Main routine Yes Write MDmn0 bit to 1 Disable interrupt (MASK) Yes Communication continued? No <6> Write STmn bit to 1 Clear SAUmEN bit of the PER0 register to 0. End of communication Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-83 Timing Chart of UART Transmission (in Continuous Transmission Mode). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 458 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6.2 UART reception UART reception is an operation wherein the RL78/G12 asynchronously receives data from another device (start-stop synchronization). For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both the odd- and even-numbered channels must be set. UART UART0 UART1 UART2 Target channel Channel 1 of SAU0 Channel 3 of SAU0 Channel 1 of SAU1 Pins used RxD0 RxD1 RxD2 INTSR0 INTSR1 INTSR2 Interrupt Transfer end interrupt only (setting the buffer empty interrupt is prohibited) Error interrupt INTSRE0 INTSRE1 Error detection * Framing error detection flag (FEFmn) flag * Parity error detection flag (PEFmn) INTSRE2 * Overrun error detection flag (OVFmn) Transfer data 7, 8 or 9 bits (UART0 only) length 15 Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 x 2 x 128) [bps] Data phase Non-inverted output (default: high level) Note Inverted output (default: low level) Parity bit The following selectable * No parity check * No parity specified (0 parity) * Appending even parity * Appending odd parity Note Stop Bit 1 bit check Data direction MSB or LSB first Use this operation within a range that satisfies the conditions above and the peripheral characteristics in the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS). Remarks 1. 2. fMCK: Operation clock frequency of target channel fCLK: System clock frequency m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 459 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-85. Example of Contents of Registers for UART Reception (UART0 to UART2) (1/2) (a) Serial mode register mn (SMRmn) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 1 6 5 4 3 1 0 0 SISmn0 0 0/1 2 1 0 MDmn2 MDmn1 MDmn0 0: Normal reception 1: Inverted reception 0 1 0 Operation mode of channel n 0: Transfer end interrupt (b) Serial mode register mr (SMRmr) 15 SMRmr 14 13 12 11 10 9 8 7 6 5 4 3 0 0 0 0 0 0 0 0 1 0 0 CKSmr CCSmr 0/1 0 2 1 0 MDmr2 MDmr1 MDmr0 Same setting value as CKSmn bit 0 1 0/1 Operation mode of channel r 0: Transfer end interrupt 1: Buffer empty interrupt (c) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0/1 0/1 0/1 0/1 5 4 3 2 DLSmn1 SLCmn1 SLCmn0 0 0 1 1 0 Masking of error interrupt INTSREx 0: Masks INTSREx 1: Enables generation of INTSREx 1 0 Note 1 DLSmn0 0/1 0/1 Setting of data length Setting of parity bit 00B: No parity Selection of data transfer sequence 0: Inputs/outputs data with MSB first 1: Inputs/outputs data with LSB first. 01B: No parity judgment 10B: Appending Even parity 11B: Appending Odd parity (d) Serial data register mn (SDRmn) (lower 8 bits: RXDq) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SDRmn Baud rate setting 0 Note 2 Receive data register RXDq R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 460 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Notes 1. Provided only in SCR01 register (UART0) only. For SCR03 and SCR11 registers, fixed as 1. 2. When UART0 performs 9-bit communication (by setting the DLS011 and DLS010 bits of the SCR01 register to 1), bits 0 to 8 of the SDR01 register are used as the transmission data specification area. 9bit communication is available only in UART0. Caution For UART reception, be sure to set the SMRmr register of channel r that is to be paired with channel n. Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11 r: Channel number (r = n - 1) q: UART number (q = 0 to 2) 2. : Setting is fixed in the UART master transmission mode, : Setting disabled (set to the initial value) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 461 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-85. Example of Contents of Registers for UART Reception (UART0 to UART2) (2/2) (e) Serial output register m (SOm) ... The register that not used in this mode. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 x x 3 2 SO03 SO02 x Note 0 0 0 0 1 0 Note SO01 SOm0 x x x 1 0 (f) Serial output enable register m (SOEm) ...The register that not used in this mode. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 SOE03 SOE02 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 Note Note x x SOE01 SOEm0 x x 1 0 (g) Serial channel start register m (SSm) ... Sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 Note SSm1 SSm0 0/1 x 0/1 x Note 0 0 0 0 0 0 0 0 0 0 0 0 Note Provided only in 30-pin product serial array unit 0. Caution For UART reception, be sure to set the SMRmr register of channel r that is to be paired with channel 0. Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11 r: Channel number (r = n - 1) q: UART number (q = 0 to 2) 2. : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 462 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure Figure 11-86. Initial Setting Procedure for UART Reception Starting initial setting Setting the PER0 register Release the serial array unit from the reset status and start clock supply. Setting the SPSm register Set the operation clock. Set an operation mode, etc. Setting the SMRmn and SMRmr registers Set a communication format. Setting the SCRmn register Setting the SDRmn register Set a transfer baud rate (setting the transfer clock by dividing the operation clock (fMCK)). Setting port Enable data input of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection. Writing to the SSm register Completing initial setting Caution After setting the RXEmn bit of SCRmn register to 1, be sure to set SSmn to 0 after 4 or more fCLK clocks have elapsed. Figure 11-87. Procedure for Stopping UART Reception Starting setting to stop No (Selective) TSFmn = 0? If there is any data being transferred, wait for their completion. (If there is an urgent must stop, do not wait) Yes (Essential) Writing the STm register Write 1 to the STmn bit of the target channel. (SEmn = 0 : (Selective) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 to operation stop status) Setting the PER0 register To use the STOP mode, reset the serial array unit by stopping the clock supply to it. Stop setting is completed The master transmission is stopped. Go to the next processing. 463 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-88. Procedure for Resuming UART Reception Starting setting for resumption Completing master preparations? (Essential) No Stop the target for communication or wait Yes (Selective) Changing setting of the SPSm register Re-set the register to change the operation clock setting. (Selective) Changing setting of the SDRmn Re-set the register to change the transfer baud rate setting (setting the transfer clock by dividing the operation clock (fMCK)). Changing setting of the SMRmn (Selective) and SMRmr registers (Selective) Changing setting of the SCRmn register (Selective) Clearing error flag (Essential) Setting port (Essential) Writing to the SSm register (Essential) Completing resumption setting Caution Re-set the registers to change serial mode registers mn, mr (SMRmn, SMRmr) setting. Re-set the register to change serial communication operation setting register mn (SCRmn) setting. If the FEF, PEF, and OVF flags remain set, clear them using serial flag clear trigger register mn (SIRmn). Enable data input of the target channel by setting a port register and a port mode register. Set the SSmn bit of the target channel to 1 and set the SEmn bit to 1 (to enable operation). Become wait for start bit detection. After setting the RXEmn bit of SCRmn register to 1, be sure to set SSmn to 0 after 4 or more fCLK clocks have elapsed. Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the transmission target (slave) stops or transmission finishes, and then perform initialization instead of restarting the transmission. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 464 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11-89. UART Reception Timing Chart SSmn STmn SEmn Receive data 3 SDRmn RxDq pin Shift register mn INTSRq Receive data 1 ST Receive data 1 Shift operation Data reception (7-bit length) P SP ST Receive data 2 Receive data 2 P SP Receive data 3 ST Shift operation Data reception (7-bit length) P SP Shift operation Data reception (7-bit length) TSFmn Remark m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11 r: Channel number (r = n - 1) q: UART number (q = 0 to 2) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 465 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-90. Flowchart of UART Reception Starting UART communication SAU default setting Setting receive data Enables interrupt For the initial setting, refer to Figure 11-86. (setting to mask for error interrupt) Setting storage area of the rec eive data, number of communication data (storage area, reception data pointer, number of communication data and communication end flag are optionally set on the internal RAM by the software) Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set Wait for receive completes Starting reception if start bit is detected When receive complete, transfer end interrupt is generated, Transfer end interrupt Reading receive data to RXDq (=SDRmn[7:0]) Read receive data then writes to storage area. Update receive data pointer and number of communication data. Indicating normal reception? No Yes RETI Error processing No Reception completed? Yes Writing 1 to the STmn bit Clearing the SAUmEN bit of the PER0 register to 0 End of UART communication Note If the data length is 9 bits, read SDRmn[8:0] instead of the RxDq register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 466 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6.3 SNOOZE mode function (only UART0 reception) SNOOZE mode makes UART operate reception by RxD0 pin input detection while the STOP mode. Normally UART stops communication in the STOP mode. But, using the SNOOZE mode makes reception data unless the CPU operation. Only UART0 can be set to the SNOOZE mode. When using the SNOOZE mode function, set the SWC0 bit of serial standby control register 0 (SSC0) to 1 before switching to the STOP mode. Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for fCLK. 2. The maximum transfer rate when using UART0 in the SNOOZE mode is 9600 bps. (1) SNOOZE mode operation (Normal operation) Figure 11-91. Timing Chart of SNOOZE Mode Operation (Normal Operation Mode) CPU operation status Normal peration <3> SS01 Normal peration SNOOZ mode STOP mode <4> <12> <10> ST01 <1> SE01 <2> SWC0 SSEC0 <11> L Clock request signal (internal signal) Receive data 2 SDR01 Receive data 1 <9> RxD0 pin ST Shift register 01 Receive data 1 P Read SP ST Receive data 2 P SP Shift operation Shift operation INTSR0 Data reception (7-bit length) <7> INTSRE0 L Data reception (7-bit length) TSF01 <2> Note <5><6> <8> Only read received data while SWC0 = 1. Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation). And after completion the receive operation, also clearing SWC0 bit to 0 (SNOOZE mode release). Remark <1> to <12> in the figure correspond to <1> to <12> in Figure 11-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 467 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) SNOOZE mode operation (Abnormal Operation <1>) Abnormal operation <1> is the operation performed when a communication error occurs while SSEC0 = 0. Because SSEC0 = 0, an error interrupt (INTSRE0) is generated when a communication error occurs. Figure 11-92. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <1>) CPU operation status Normal peration <3> SS01 STOP mode Normal peration SNOOZ mode <4> <12> ST01 <1> <10> SE01 <2> SWC0 SSEC0 <11> L Clock request signal (internal signal) SDR01 Receive data 2 Receive data 1 RxD0 pin ST Shift register 01 Receive data 1 P SP Shift operation ST Receive data 2 P SP Shift operation INTSR0 INTSRE0 L Data reception (7-bit length) <7> Data reception (7-bit length) TSF01 <5> <6> Caution <8> Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation). And after completion the receive operation, also clearing SWC0 bit to 0 (SNOOZE mode release). Remark <1> to <12> in the figure correspond to <1> to <12> in Figure 11-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 468 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>) Setting start No Does TSF01 = 0 on all channels? Yes <1> Writing 1 to the ST01 bit SE01 = 0 Normal operation SAU default setting The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. (EOC01: set to enable error interrupt) <2> Setting SSC0 register (SWC0 = 1, SSEC0 = 0) SNOOZE mode setting <3> Writing 1 to the SS01 bit SE01 = 1 Communication wait status Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt enable (EI = 1). Enable interrupt <4> STOP mode Entered the STOP mode fCLK supplied to the SAU is stopped. SNOOZE mode <5> RxD0 edge detected (Entered the SNOOZE mode) <6> Clock supply (UART receive operation) <7> Transfer end interrupt (INTSR0) or error interrupt (INTSRE0) generated? <8> INTSRE0 INTSR0 Normal operation Reading receive data to RxD0 (=SDR01[7:0]) <9> Writing 1 to the ST01 bit <10> Writing 1 to the ST01 bit Clear SWC0 bit to 0 <11> Clear SWC0 bit to 0 Writing 1 to the SS01 bit <12> Writing 1 to the SS01 bit Error processing Remark Reading receive data to RxD0 (=SDR01[7:0]) The mode switches from SNOOZE to normal operation. To operation stop status (SE01 = 0) Reset SNOOZE mode setting To communication wait status (SE01 = 1) Normal processing <1> to <11> in the figure correspond to <1> to <11> in Figure 11-91. Timing Chart of SNOOZE Mode Operation (Normal Operation Mode) and Figure 11-92. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <1>). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 469 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) SNOOZE mode operation (Abnormal Operation <2>) Abnormal operation <2> is the operation performed when a communication error occurs while SSEC0 = 1. Because SSEC0 = 1, an error interrupt (INTSRE0) is not generated when a communication error occurs. Figure 11-94. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <2>) Normal peration CPU operation status Normal peration <3> SS01 SNOOZ mode STOP mode <4> SNOOZ mode STOP mode <10> ST01 <1> SE01 SWC0 SSEC0 Shift operation Clock request signal (internal signal) Receive data 2 SDR01 Receive data 1 Read RxD0 pin Receive data 1 ST Shift register 01 P SP Receive data 2 ST <9> P SP Shift operation Shift operation Data reception (7-bit length) Data reception (7-bit length) INTSR0 INTSRE0 L Note2 TSF01 <2> <5> <6> <7> <5> <6> <7>, <11> <8> Notes 1. Only read received data while SWC0 = 1 and before the next edge of the RxD0 pin input is detected. 2. After the reception of UART0 finishes normally in the SNOOZE mode, the normal reception operation can be performed without changing the settings. However, FEF01 or PEF01 bit cannot be set even if framing error or parity error is generated due to SSEC0 = 1. In addition, error interrupt (INTSRE0) is not generated also. Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation). And after completion the receive operation, also clearing SWC0 bit to 0 (SNOOZE mode release). 2. When using the SNOOZE mode while SSEC0 is set to 1, no overrun errors occur. Therefore, when using the SNOOZE mode, read bits 7 to 0 (RxD0) of the SDR01 register before switching to the STOP mode. Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 470 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>) Setting start Does TSF01 = 0 on all channels? No Yes SIR01 = 0007H <1> Writing 1 to the ST01 bit Normal operation SE01 = 0 SAU default setting <2> Setting SSC0 register Clear the all error flags The operation of all channels is also stopped to switch to the STOP mode. Channel 1 is specified for UART reception. (EOC01: set to enable error interrupt) SNOOZE mode setting (error interrupt generation stop) (SWC0 = 1, SSEC0 = 1) <3> Writing 1 to the SS01 bit SE01 = 1 Setting interrupt <4> Entered the STOP mode Communication wait status Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt disable (EI = 0). fCLK supplied to the SAU is stopped. STOP mode <5> SNOOZE mode STOP mode RxD0 edge detected (Entered the SNOOZE mode) <6> Clock supply (UART receive operation) <7> Reception error detected If an error occurs, because the CPU switches to the STOP status again, the error flag is not set. SNOOZE mode RxD0 edge detected (Entered the SNOOZE mode) Clock supply (UART receive operation) <7> Transfer end interrupt (INTSR0) generated <8> <9> Normal operation Reading receive data to The mode switches from SNOOZE to normal operation. RxDq (=SDR01[7:0]) <10> <11> Writing 1 to the ST01 bit Setting SSC0 register To operation stop status (SE01 = 0) Reset SNOOZE mode setting (SWC0 = 0, SSEC0 = 0) Nomarl processing R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 471 RL78/G12 Caution CHAPTER 11 SERIAL ARRAY UNIT When using the SNOOZE mode while SSEC0 is set to 1, no overrun errors occur. Therefore, when using the SNOOZE mode, read bits 7 to 0 (RxD0) of the SDR01 register before switching to the STOP mode. Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-94. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <2>). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 472 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6.4 Calculating baud rate (1) Baud rate calculation expression The baud rate for UART (UART0 to UART2) communication can be calculated by the following expressions. (Baud rate) = {Operation clock (fMCK) frequency of target channel} / (SDR0n[15:9] + 1) / 2 [bps] Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B to 0000001B) is prohibited. Remarks 1. When UART is used, the value of SDRmn0[15:9] is the value of bits 15 to 9 of the SDR00 register (0000010B to 1111111B) and therefore is 2 to 127. 2. mn = 00 to 03, 10, 11 The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 473 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Table 11-3. Selection of Operation Clock For UART SMRmn Register SPSm Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 Operation Clock (fMCK) Note fCLK = 20 MHz X X X X 0 0 0 0 fCLK X X X X 0 0 0 1 fCLK/2 20 MHz 10 MHz X X X X 0 0 1 0 fCLK/2 2 X X X X 0 0 1 1 fCLK/2 3 2.5 MHz 1.25 MHz 5 MHz X X X X 0 1 0 0 fCLK/2 4 X X X X 0 1 0 1 fCLK/2 5 625 kHz 312.5 kHz X X X X 0 1 1 0 fCLK/2 6 X X X X 0 1 1 1 fCLK/2 7 156.2 kHz 78.1 kHz X X X X 1 0 0 0 fCLK/2 8 X X X X 1 0 0 1 fCLK/2 9 39.1 kHz X X X X 1 0 1 0 fCLK/2 10 19.5 kHz X X X X 1 0 1 1 fCLK/2 11 9.77 kHz X X X X 1 1 0 0 fCLK/2 12 4.88 kHz 2.44 kHz 1.22 kHz X X X X 1 1 0 1 fCLK/2 13 X X X X 1 1 1 0 fCLK/2 14 15 X X X X 1 1 1 1 fCLK/2 0 0 0 0 X X X X fCLK 1 610 Hz 20 MHz 0 0 0 1 X X X X fCLK/2 0 0 1 0 X X X X fCLK/2 2 5 MHz 10 MHz 0 0 1 1 X X X X fCLK/2 3 2.5 MHz 1.25 MHz 0 1 0 0 X X X X fCLK/2 4 0 1 0 1 X X X X fCLK/2 5 625 MHz 312.5 kHz 0 1 1 0 X X X X fCLK/2 6 0 1 1 1 X X X X fCLK/2 7 156.2 kHz 78.1 kHz 39.1 kHz 1 0 0 0 X X X X fCLK/2 8 1 0 0 1 X X X X fCLK/2 9 19.5 kHz 1 0 1 0 X X X X fCLK/2 10 1 0 1 1 X X X X fCLK/2 11 9.77 kHz 1 1 0 0 X X X X fCLK/2 12 4.88 kHz 2.44 kHz 1 1 0 1 X X X X fCLK/2 13 1 1 1 0 X X X X fCLK/2 14 1.22 kHz fCLK/2 15 610 Hz 1 1 1 1 X X X X Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. 2. X: don't care mn = 00 to 03, 10, 11 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 474 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Baud rate error during transmission The baud rate error of UART (UART0 to UART2) communication during transmission can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. (Baud rate error) = (Calculated baud rate value) / (Target baud rate) x 100 - 100 [%] Here is an example of setting a UART baud rate at fCLK = 20 MHz. UART Baud Rate (Target Baud Rate) fCLK = 20 MHz Operation Clock (fMCK) Calculated Baud Rate Error from Target Baud Rate 64 300.48 bps +0.16 % 64 600.96 bps +0.16 % 64 1201.92 bps +0.16 % 64 2403.85 bps +0.16 % 5 64 4807.69 bps +0.16 % fCLK/2 4 64 9615.38 bps +0.16 % fCLK/2 3 64 19230.8 bps +0.16 % fCLK/2 3 39 31250.0 bps 0.0 % 38400 bps fCLK/2 2 64 38461.5 bps +0.16 % 76800 bps fCLK/2 64 76923.1 bps +0.16 % 153600 bps fCLK 64 153846 bps +0.16 % 312500 bps fCLK 31 312500 bps 0.0 % fCLK/2 9 fCLK/2 8 fCLK/2 7 2400 bps fCLK/2 6 4800 bps fCLK/2 300 bps 600 bps 1200 bps 9600 bps 19200 bps 31250 bps Remark SDRmn[15:9] mn = 00, 02, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 475 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Permissible baud rate range for reception The permissible baud rate range for reception during UART (UART0 to UART2) communication can be calculated by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate range at the reception side. 2 x k x Nfr (Maximum receivable baud rate) = x Brate 2 x k x Nfr - k + 2 2 x k x (Nfr - 1) (Minimum receivable baud rate) = x Brate 2 x k x Nfr - k - 2 Brate: Calculated baud rate value at the reception side (See 11.6.4 (1) Baud rate calculation expression.) k: SDRmn[15:9] + 1 Nfr: 1 data frame length [bits] = (Start bit) + (Data length) + (Parity bit) + (Stop bit) Remark mn = 01, 03, 11 Figure 11-96. Permissible Baud Rate Range for Reception (1 Data Frame Length = 11 Bits) Latch timing Data frame length of SAU Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit FL 1 data frame (11 x FL) Permissible minimum data frame length Start bit Bit 0 Bit 1 Parity bit Bit 7 Stop bit (11 x FL) min. Permissible maximum data frame length Start bit Bit 0 Bit 1 Bit 7 Parity bit Stop bit (11 x FL) max. As shown in Figure 11-96 the timing of latching receive data is determined by the division ratio set by bits 15 to 9 of serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this latch timing, the data can be correctly received. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 476 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication The procedure for processing errors that occurred during UART (UART0 to UART2) communication is described in Figures 11-97 and 11-98. Figure 11-97. Processing Procedure in Case of Parity Error or Overrun Error Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the (SDRmn). is set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn (SSRmn). Writes 1 to serial flag clear trigger register mn (SIRmn). Error type is identified and the read value is used to clear error flag. Error flag is cleared. Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Figure 11-98. Processing Procedure in Case of Framing Error Software Manipulation Hardware Status Remark Reads serial data register mn The BFFmn bit of the SSRmn register This is to prevent an overrun error if the (SDRmn). is set to 0 and channel n is enabled to receive data. next reception is completed during error processing. Reads serial status register mn Error type is identified and the read (SSRmn). value is used to clear error flag. Writes serial flag clear trigger register mn Error flag is cleared. (SIRmn). Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Sets the STmn bit of serial channel stop The SEmn bit of serial channel enable register m (STm) to 1. status register m (SEm) is set to 0 and channel n stops operating. Synchronization with other party of Synchronization with the other party of communication communication is re-established and communication is resumed because it is considered that a framing error has occurred because the start bit has been shifted. Sets the SSmn bit of serial channel start The SEmn bit of serial channel enable register m (SSm) to 1. status register m (SEm) is set to 1 and channel n is enabled to operate. Remark mn = 00 to 03, 10, 11 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 477 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20) Communication This is a clocked communication function to communicate with two or more devices by using two lines: serial clock (SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such as EEPROM, flash memory, and A/D converter, and therefore, can be used only by the master. Operate the control registers by software for setting the start and stop conditions while observing the specifications of the I2C bus line. [Data transmission/reception] * Master transmission, master reception (only master function with a single master) Note * ACK output function and ACK detection function * Data length of 8 bits (When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is used for R/W control.) * Generation of start condition and stop condition for software [Interrupt function] * Transfer end interrupt [Error detection flag] * ACK error * [Functions not supported by simplified I2C] * Slave transmission, slave reception * Multi master function (Arbitration loss detection function) * Wait detection function Note When receiving the last data, ACK will not be output if 0 is written to the SOEmn (SOEm register) bit and serial communication data output is stopped. See the processing flow in 11.7.3 (2) for details. Remark m: Unit number (m = 0, 1) n: Channel number (n = 0, 1, 3), mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 478 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT The channels supporting simplified I2C (IIC00, IIC01, IIC11, IIC20) are channels 0, 1, 3 of SAU0 and channel 0 of SAU1. 20- or 24-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 CSI01 Note 2 Used as Simplified I C IIC00 Note Note IIC01 30-pin products Unit Channel Used as CSI Used as UART 0 0 CSI00 UART0 1 - 2 1 <R> IIC00 Note - - UART1 Note Note 3 CSI11 0 CSI20 1 2 Used as Simplified I C Note - - IIC11 UART 2 Note Note Note IIC20 - Note Provided in the R5F102 products only. 2 Simplified I C (IIC00, IIC01, IIC11, IIC20) performs the following four types of communication operations. * Address field transmission (See 11.7.1.) * Data transmission (See 11.7.2.) * Data reception (See 11.7.3.) * Stop condition generation (See 11.7.4.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 479 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.1 Address field transmission 2 Address field transmission is a transmission operation that first executes in I C communication to identify the target for transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in one frame. 2 Simplified I C Target channel IIC00 IIC01 Channel 0 of SAU0 Pins used SCL00, SDA00 Interrupt INTIIC00 Note IIC11 Channel 1 of SAU0 SCL01, SDA01 Note INTIIC01 IIC20 Channel 3 of SAU0 SCL11, SDA11 Note INTIIC11 Channel 0 of SAU1 SCL20, SDA20 Note INTIIC20 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection ACK error detection flag (PEFmn) flag Transfer data 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as length R/W control) Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel 2 However, the following condition must be satisfied in each mode of I C. * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Note Data level Non-inversion output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (for ACK transmission/reception timing) Data direction MSB first 2 To perform communication via simplified I C, set the N-ch open-drain output (VDD tolerance) mode (POM11, POM41 = 1 for 20- or 24-pin products, POM11, POM14, POM50 = 1 for 30-pin products) for the port output mode registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD tolerance) mode (POM10 = 1 for 20- or 24-pin products, POM10, POM15 = 1 for 30-pin products) also for the clock input/output pins (SCL00, SCL20) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details) Remark mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 480 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting 2 Figure 11-99. Example of Contents of Registers for Address Field Transmission of Simplified I C (IIC00, IIC01, IIC11, IIC20) (a) Serial mode register 0n (SMR0n) 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 CKSmn CCSmn 0/1 0 8 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 2 1 0 MDmn2 MDmn1 MDmn0 0 Operation clock (fMCK) of channel n 0: Prescaler output clock CKm0 set by the SPSm register 1: Prescaler output clock CKm1 set by the SPSm register 1 0 0 Operation mode of channel n 0: Transfer end interrupt (b) Serial communication operation setting register mn (SCRmn) 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 1 Setting of parity bit 00B: No parity 1 0 DLSmn1 DLSmn0 1 1 Setting of stop bit 01B: Appending 1 bit (ACK) (c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) 15 14 SDRmn 13 12 11 10 9 Baud rate setting 8 7 6 5 14 13 12 11 10 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 1 2 1 0 SIOr SOm 0 3 Transmit data setting (address + R/W) 0 (d) Serial output register m (SOm) 15 4 1 0/1 0/1 3 2 1 SO03 SO02 SO01 Note2 SOm0 0/1 x 0/1 0/1 Note1 0 0 0 0 Note1 0 Start condition is generated by manipulating the SOmn bit. (e) Serial output enable register m (SOEm) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOE03 SOE02 SOE01 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note1 Note1 Note2 SOEm0 0/1 x 0/1 0/1 SOEmn = 0 until the start condition is generated, and SOEmn = 1 after generation. (f) Serial channel start register m (SSm) ... Sets only the bits of the target channel is 1. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SS03 SS02 0/1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Note1 SSm1 SSm0 x 0/1 0/1 SSmn = 0 until the start condition is generated, and SSmn = 1 after generation. Notes 1. Provided only in 30-pin product serial array unit 0. 2. Only for 20, 24-pin product Remarks 1. mn = 00, 01, 03, 10, r: IIC number (r = 00, 01, 11, 20) 2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 481 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Operation procedure 2 Figure 11-100. Initial Setting Procedure for simplified I C Address Field Transmission Starting initial setting Setting the PER0 register Setting the SPSm register Release the serial array unit from the reset status and start clock supply. Set the operation clock. Setting the SMRmn register Set an operation mode, etc. Setting the SCRmn register Set a communication format. Set a transfer baud rate (setting the Setting the SDRmn register transfer clock by dividing the operation clock (fMCK)). Setting the SOm register Setting port Set the initial output level (1) of the serial data (SOmn) and serial clock (CKOmn). Enable data output, clock output, and N-ch opendrain output (VDD tolerance) mode of the target channel by setting the port register, port mode register, and port output mode register. Completing initial setting Remark At the end of the initial setting, the simplified I2C (IIC00, IIC01, IIC11, IIC20) must be set so that output is disabled and operations are stopped. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 482 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (3) Processing flow Figure 11-101. Timing Chart of Address Field Transmission SSmn SEmn SOEmn Address field transmission SDRmn SCLr output CKOmn bit manipulation SDAr output D7 D6 D5 D4 D3 D2 D1 SOmn bit manipulation R/W Address D7 SDAr input D6 D5 D4 Shift register mn D0 D3 D2 D1 D0 ACK Shift operation INTIICr TSFmn Remark mn = 00, 01, 03, 10, r: IIC number (r = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 483 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-102. Flowchart of simplified I2C Address Field Transmission Transmitting address field Default setting Writing 0 to the SOmn bit For the initial setting, refer to Figure 11-100 Setting 0 ot the SOmn bit Start condition generate Wait To secure a hold time of SCL signal Writing 0 to the CKOmn bit Prepare to communicate the SCL signal is fall Writing 1 to the SOEmn bit Enable serial output Writing 1 to the SSmn bit Writing address and R/W data to SIOr (SDRmn[7:0]) To serial operation enable status Transmitting address field Wait for address field transmission Transfer end interrupt generated? No Yes Responded ACK? Yes No complete. (Clear the interrupt request flag) ACK response from the slave will be confirmed in PEFmn bit. if ACK (PEFmn = 0), to the next processing, if NACK (PEFmn = 1) to error processing. Communication error processing Address field transmission completed To data transmission flow and data reception flow R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 484 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.2 Data transmission Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field. After all data are transmitted to the slave, a stop condition is generated and the bus is released. 2 Simplified I C Target channel Pins used Interrupt IIC00 IIC01 IIC11 Channel 0 of SAU0 Channel 1 of SAU0 Note Note SCL00, SDA00 INTIIC00 SCL01, SDA01 INTIIC01 IIC20 Channel 3 of SAU0 SCL11, SDA11 Note INTIIC11 Channel 0 of SAU1 SCL20, SDA20 Note INTIIC20 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection ACK error detection flag (PEFmn) flag Transfer data 8 bits length Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel 2 However, the following condition must be satisfied in each mode of I C. * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Note Data level Non-inversion output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (for ACK reception timing) Data direction MSB first To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM11, POM41 = 1 for 20- or 24-pin products, POM11, POM14, POM50 = 1 for 30-pin products) for the port output mode registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD tolerance) mode (POM10 = 1 for 20- or 24-pin products, POM10, POM15 = 1 for 30-pin products) also for the clock input/output pins (SCL00, SCL20) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details) Remark mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 485 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting Figure 11-103. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC01, IIC11, IIC20) (a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception. 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 8 CKSmn CCSmn 0/1 0 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 0 2 1 0 MDmn2 MDmn1 MDmn0 1 0 0 (b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception. 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 1 0 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0 5 4 3 2 0 1 SLCmn1 SLCmn0 0 0 1 1 0 DLSmn1 DLSmn0 1 1 (c) Serial data register mn (SDRmn) ...During data transmission/reception, valid only lower 8-bits (SIOr) 15 14 SDRmn 13 12 11 10 9 8 Baud rate setting 7 6 5 4 3 2 1 0 0 Transmit data setting 0 SIOr (d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 CKOm1 CKOm0 SOm 0 0 0 0 1 1 0/1 Note 2 0/1 Note 2 3 2 1 SOm3 SOm2 SOm1 0/1 x 0/1 Note 1 0 0 0 0 Note 3 Note 1 Note 2 SOm0 0/1 Note 3 Note 3 (e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOEm3 SOEm2 SOEm1 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 SOEm0 Note 1 Note 1 Note 2 0/1 x 1 1 0 (f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 1 SSm3 SSm2 SSm1 Note 2 SSm0 0/1 x 0/1 0/1 Note 1 0 0 0 0 0 0 0 0 0 0 0 0 Note 1 Notes 1. Provided only in 30-pin product serial array unit 0. 2. Only for 20, 24-pin product 3. The values may change during operation, depending on the communication data. Remarks 1. mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20) 2. : Setting is fixed in the IIC master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 486 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Processing flow Figure 11-104. Timing Chart of Data Transmission SSmn SEmn SOEmn "L" "H" "H" Transmit data 1 SDRmn SCLr output SDAr output D7 D6 D5 D4 D3 D2 D1 D0 SDAr input D7 D6 D5 D4 D3 D2 D1 D0 Shift register mn ACK Shift operation INTIICr TSFmn 2 Figure 11-105. Flowchart of Simplified I C Data Transmission Address field transmission completed Starting data transmission Writing data to SIOr (SDRmn[7:0]) Transfer end interrupt generated? Transmission start by writing No Wait for transmission complete. (Clear the interrupt request flag) Yes ACK acknowledgment from the slave No Responded ACK? If ACK (PEF = 0), to the next process if NACK (PEF = 1), to error handling Yes Communication error processing No Data transfer completed? Yes Data transmission completed Stop condition generation R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 487 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.3 Data reception Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field. After all data are received to the slave, a stop condition is generated and the bus is released. 2 Simplified I C Target channel Pins used Interrupt IIC00 IIC01 Channel 0 of SAU0 SCL00, SDA00 INTIIC00 Note IIC11 Channel 1 of SAU0 SCL01, SDA01 Note INTIIC01 IIC20 Channel 3 of SAU0 SCL11, SDA11 Note INTIIC11 Channel 0 of SAU1 SCL20, SDA20 Note INTIIC20 Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.) Error detection ACK error detection flag (OVFmn) flag Transfer data 8 bits length Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target channel However, the following condition must be satisfied in each mode of I2C. * Max. 400 kHz (fast mode) * Max. 100 kHz (standard mode) Note Data level Non-inversion output (default: high level) Parity bit No parity bit Stop bit Appending 1 bit (ACK transmission) Data direction MSB first To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM11, POM41 = 1 for 20- or 24- pin products, POM11, POM14, POM50 = 1 for 30-pin products) for the port output mode registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD tolerance) mode (POM10 = 1 for 20- or 24- pin products, POM10, POM15 = 1 for 30-pin products) also for the clock input/output pins (SCL00, SCL20) (see 4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V) for details). Remark mn = 00, 01, 03, 10 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 488 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (1) Register setting 2 Figure 11-106. Example of Contents of Registers for Data Reception of Simplified I C (IIC00, IIC01, IIC11, IIC20) (a) Serial mode register mn (SMRmn) ... Do not manipulate this register during data transmission/reception. 15 SMRmn 14 13 12 11 10 9 0 0 0 0 0 8 CKSmn CCSmn 0/1 0 7 STSmn 0 6 5 4 3 1 0 0 SISmn0 0 2 1 0 MDmn2 MDmn1 MDmn0 0 1 0 0 (b) Serial communication operation setting register mn (SCRmn) ... Do not manipulate the bits of this register, except the TXEmn and RXEmn bits, during data transmission/reception. 15 SCRmn 14 13 12 11 TXEmn RXEmn DAPmn CKPmn 0 1 0 0 10 9 8 7 6 EOCmn PTCmn1 PTCmn0 DIRmn 0 0 0 0 0 5 4 3 2 SLCmn1 SLCmn0 1 0 DLSmn1 DLSmn0 0 0 1 0 1 1 1 6 5 4 3 2 1 0 (c) Serial data register mn (SDRmn) (lower 8 bits: SIOr) 15 14 SDRmn 13 12 11 10 9 8 Baud rate setting 7 Dummy transmit data setting (FFH) 0 SIOr (d) Serial output register m (SOm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 SOm 9 8 7 6 5 4 CKOm1 CKOm0 0 0 0 0 1 1 0/1 0/1 Note 2 Note 2 3 2 1 SOm3 SOm2 SOm1 0/1 x 0/1 Note 1 0 0 0 0 Note 1 Note 3 Note 2 Note 3 0 SOm0 0/1 Note 3 (e) Serial output enable register m (SOEm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SOEm3 SOEm2 SOEm1 SOEm 0 0 0 0 0 0 0 0 0 0 0 0 0 Note 1 Note 1 Note 2 SOEm0 0/1 x 0/1 0/1 1 0 (f) Serial channel start register m (SSm) ... Do not manipulate this register during data transmission/reception. 15 14 13 12 11 10 9 8 7 6 5 4 SSm 3 2 SSm3 SSm2 Note 1 SSm1 SSm0 0/1 x 0/1 0/1 Note 1 0 0 0 0 0 0 0 0 0 0 0 0 Notes 1. Provided only in 30-pin products serial array unit 0. 2. Only for 20, 24-pin products. 3. The values may change during operation, depending on the communication data. Remarks 1. mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20) 2. : Setting is fixed in the IIC master transmission mode, : Setting disabled (set to the initial value) x: Bit that cannot be used in this mode (set to the initial value when not used in any mode) 0/1: Set to 0 or 1 depending on the usage of the user R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 489 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT (2) Processing flow Figure 11-107. Timing Chart of Data Reception (a) When starting data reception SSmn STmn SEmn SOEmn "H" TXEmn, TXEmn = 1 / RXEmn = 0 RXEmn TXEmn = 0 / RXEmn = 1 SDRmn Receive data Dummy data (FFH) SCLr output SDAr output ACK D7 SDAr input D6 D5 D4 Shift register mn D3 D2 D1 D0 Shift operation INTIICr TSFmn (b) When receiving last data STmn SEmn SOEmn TXEmn, RXEmn Output is enabled by serial communication operation Output is stopped by serial communication operation TXEmn = 0 / RXEmn = 1 SDRmn Dummy data (FFH) Dummy data (FFH) Receive data Receive data SCLr output SDAr output SDAr input Shift register mn ACK D2 D1 D0 NACK D7 D6 D5 D4 D3 D2 D1 D0 Shift operation Shift operation INTIICr TSFmn Reception of last byte SOmn bit SOmn bit manipulation manipulation IIC operation stop CKOmn bit manipulation Step condition Remark mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 490 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Figure 11-108. Flowchart of Data Reception Address field transmission completed Data reception completed Stop operation for rewriting SCRmn register. Writing 1 to the STmn bit Writing 0 to the TXEmn bit, and 1 to the RXEmn bit mode of the channel. Operation restart Writing 1 to the SSmn bit Last byte received? Set to receive only the operating No Yes Disable output so that not the ACK response to the last received data. Writing 0 to the SOEmn bit Writing dummy data (FFH) to SIOr (SDRmn[7:0]) Transfer end interrupt generated? Starting reception operation No Wait for the completion of reception. (Clear the interrupt request flag) Yes Reading SIOr (SDRmn[7:0]) Reading receive data, perform processing (stored in the RAM etc.). No Data transfer completed? Yes Data reception completed Stop condition generation Caution ACK is not output when the last data is received (NACK). Communication is then completed by setting "1" to the STmn bit of serial channel stop register m (STm) to stop operation and generating a stop condition. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 491 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.4 Stop condition generation After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released. (1) Processing flow Figure 11-109. Timing Chart of Stop Condition Generation STmn SEmn SOEmn Note SCLr output SDAr output Operation stop SOmn CKOmn SOmn bit manipulation bit manipulation bit manipulation Stop condition Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before receiving the last data. Figure 11-110. Flowchart of Stop Condition Generation Completion of data transmission/data reception Starting generation of stop condition. Writing 1 to the STmn bit to clear (the SEmn bit is cleared to 0) Operation is stopped Writing 0 to the SOEmn bit Writing 0 to the SOmn bit Writing 1 to the CKOmn bit Secure a wait time so that the specifications of Wait 2 I C on the slave side are satisfied. Writing 1 to the SOmn bit End of IIC communication R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 492 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.5 Calculating transfer rate 2 The transfer rate for simplified I C (IIC00, IIC01, IIC11, IIC20) communication can be calculated by the following expressions. (Transfer rate) = {Operation clock (fMCK) frequency of target channel} / (SDRmn[15:9] + 1) / 2 Caution SDRmn[15:9] must not be set to 00000000B. Be sure to set a value of 00000001B or greater for 2 2 SDRmn[15:9]. The duty ratio of the SCL signal output by the simplified I C is 50%. The I C bus specifications define that the low-level width of the SCL signal is longer than the highlevel width. If 400 kbps (fast mode) or 1 Mbps (fast mode plus) is specified, therefore, the lowlevel width of the SCL output signal becomes shorter than the value specified in the I2C bus specifications. Make sure that the SDRmn[15:9] value satisfies the I2C bus specifications. Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to 1111111B) and therefore is 1 to 127. 2. mn = 00, 01, 03, 10 The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode register mn (SMRmn). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 493 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT Table 11-4. Selection of Operation Clock for Simplified I2C SMRmn Register SPS0 Register CKSmn PRS PRS PRS PRS PRS PRS PRS PRS m13 m12 m11 m10 m03 m02 m01 m00 0 1 Operation Clock (fMCK) Note fCLK = 20 MHz X X X X 0 0 0 0 fCLK X X X X 0 0 0 1 fCLK/2 20 MHz X X X X 0 0 1 0 fCLK/2 2 5 MHz X X X X 0 0 1 1 fCLK/2 3 2.5 MHz X X X X 0 1 0 0 fCLK/2 4 1.25 MHz 625 KHz 10 MHz X X X X 0 1 0 1 fCLK/2 5 X X X X 0 1 1 0 fCLK/2 6 312.5 kHz 156.2 kHz 78.1 kHz X X X X 0 1 1 1 fCLK/2 7 X X X X 1 0 0 0 fCLK/2 8 39.1 kHz X X X X 1 0 0 1 fCLK/2 9 X X X X 1 0 1 0 fCLK/2 10 19.5 kHz X X X X 1 0 1 1 fCLK/2 11 9.77 kHz 4.87 kHz X X X X 1 1 0 0 fCLK/2 12 X X X X 1 1 0 1 fCLK/2 13 2.44 kHz 1.22 kHz 610 Hz X X X X 1 1 1 0 fCLK/2 14 X X X X 1 1 1 1 fCLK/2 15 0 0 0 0 X X X X fCLK 0 0 0 1 X X X X fCLK/2 20 MHz 10 MHz 0 0 1 0 X X X X fCLK/2 2 0 0 1 1 X X X X fCLK/2 3 2.5 MHz 0 1 0 0 X X X X fCLK/2 4 1.25 MHz 625 KHz 5 MHz 0 1 0 1 X X X X fCLK/2 5 0 1 1 0 X X X X fCLK/2 6 312.5 KHz 156.2 kHz 78.1 kHz 0 1 1 1 X X X X fCLK/2 7 1 0 0 0 X X X X fCLK/2 8 39.1 kHz 1 0 0 1 X X X X fCLK/2 9 1 0 1 0 X X X X fCLK/2 10 19.5 kHz 1 0 1 1 X X X X fCLK/2 11 9.76 kHz 1 1 0 0 X X X X fCLK/2 12 4.87 kHz 1 1 0 1 X X X X fCLK/2 13 2.44 kHz 1.22 kHz 610 Hz 1 1 1 0 X X X X fCLK/2 14 1 1 1 1 X X X X fCLK/2 15 Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so after having stopped (serial channel stop register m(STm) = 000FH) the operation of the serial array unit (SAU). Remarks 1. X: don't care 2. mn = 00, 01, 03, 10 Here is an example of setting an IIC transfer rate where fMCK = fCLK = 20 MHz. IIC Transfer Mode (Desired Transfer Rate) fCLK = 20 MHz Operation Clock (fMCK) SDRmn[15:9] Calculated Transfer Rate Error from Desired Transfer Rate 100 kHz fCLK/2 49 100 kHz 0.0% 400 kHz fCLK 25 384.6 kHz 3.8% Note Note The error cannot be set to about 0% because the duty ratio of the SCL signal is 50%. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 494 RL78/G12 CHAPTER 11 SERIAL ARRAY UNIT 11.7.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC11, IIC20) communication The procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC11, IIC20) communication is described in Figure 11-111. Figure 11-111. Processing Procedure in Case of ACK error in Simplified I2C Mode Software Manipulation Hardware Status Reads serial status register mn (SSRmn). Writes serial flag clear trigger register mn Remark Error type is identified and the read value is used to clear error flag. Error flag is cleared. (SIRmn). Error can be cleared only during reading, by writing the value read from the SSRmn register to the SIRmn register without modification. Sets the STmn bit of serial channel stop The SEmn bit of serial channel enable Slave is not ready for reception register m (STm) to 1. status register m (SEm) is set to 0 and channel n stops operation. because ACK is not returned. Therefore, a stop condition is created, the bus is released, and communication is started again from the start condition. Or, a restart condition is generated and Creates stop condition. transmission can be redone from address transmission. Creates start condition. Sets the SSmn bit of serial channel start The SEmn bit of serial channel enable register m (SSm) to 1. status register m (SEm) is set to 1 and channel n is enabled to operate. Remark mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 495 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA CHAPTER 12 SERIAL INTERFACE IICA 12.1 Functions of Serial Interface IICA Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption. (2) I2C bus mode (multimaster supported) This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLA0) line and a serial data bus (SDAA0) line. This mode complies with the I2C bus format and the master device can generated "start condition", "address", "transfer direction specification", "data", and "stop condition" data to the slave device, via the serial data bus. The slave device automatically detects these received status and data by hardware. This function can simplify the part of application program that controls the I2C bus. Since the SCLA0 and SDAA0 pins are used for open drain outputs, serial interface IICA requires pull-up resistors for the serial clock line and the serial data bus line. (3) Wakeup mode The STOP mode can be released by generating an interrupt request signal (INTIICA0) when an extension code from the master device or a local address has been received while in STOP mode. This can be set by using the WUP0 bit of IICA control register 01 (IICCTL01). Figure 12-1 shows a block diagram of serial interface IICA. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 496 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-1. Block Diagram of Serial Interface IICA Internal bus IICA status register 0 (IICS0) WUP0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 IICA control register 00 (IICCTL00) Sub-circuit for standby IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 Filter Slave address register 0 (SVA0) SDAA0/ P61 IICA shift register 0 (IICA0) DFC0 TRC0 N-ch opendrain output PM61 Set Match signal Noise eliminator Start condition generator Clear D Q Stop condition generator SO latch IICWL0 Data hold time correction circuit ACK generator Output control Output latch (P61) Wakeup controller ACK detector Start condition detector Filter Stop condition detector SCLA0/ P60 Noise eliminator Interrupt request signal generator Serial clock counter INTIICA0 IICS0.MSTS0, EXC0, COI0 DFC0 N-ch opendrain output PM60 fCLK Output latch (P60) fCLK/2 Selector Serial clock controller Serial clock wait controller IICA shift register 0 (IICA0) IICCTL00.STT0, SPT0 Counter Bus status detector IICS0.MSTS0, EXC0, COI0 Match signal IICCTL01.PRS0 IICA low-level width setting register 0 (IICWL0) IICA high-level width setting register 0 (IICWH0) WUP0 CLD0 DAD0 SMC0 DFC0 PRS0 IICA control register 01 (IICCTL01) STCF0 IICBSY0 STCEN0 IICRSV0 IICA flag register 0 (IICF0) Internal bus R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 497 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-2 shows a serial bus configuration example. 2 Figure 12-2. Serial Bus Configuration Example Using I C Bus + VDD + VDD Master CPU1 SDAA0 Slave CPU1 Address 0 SCLA0 Serial data bus Serial clock SDAA0 Slave CPU2 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Master CPU2 Address 1 Slave CPU3 Address 2 Slave IC Address 3 Slave IC Address N 498 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 12-1. Configuration of Serial Interface IICA Item Configuration Registers IICA shift register 0 (IICA0) Slave address register 0 (SVA0) Control registers Peripheral enable register 0 (PER0) IICA control register 00 (IICCTL00) IICA status register 0 (IICS0) IICA flag register 0 (IICF0) IICA control register 01 (IICCTL01) IICA low-level width setting register 0 (IICWL0) IICA high-level width setting register 0 (IICWH0) Port mode register 6 (PM6) Port register 6 (P6) (1) IICA shift register 0 (IICA0) The IICA0 register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with the serial clock. The IICA0 register can be used for both transmission and reception. The actual transmit and receive operations can be controlled by writing and reading operations to the IICA0 register. Cancel the wait state and start data transfer by writing data to the IICA0 register during the wait period. The IICA0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears IICA0 to 00H. Figure 12-3. Format of IICA Shift Register 0 (IICA0) Address: FFF50H Symbol After reset: 00H 7 6 R/W 5 4 3 2 1 0 IICA0 Cautions 1. Do not write data to the IICA0 register during data transfer. 2. Write or read the IICA0 register only during the wait period. Accessing the IICA0 register in a communication state other than during the wait period is prohibited. When the device serves as the master, however, the IICA0 register can be written only once after the communication trigger bit (STT0) is set to 1. 3. When communication is reserved, write data to the IICA0 register after the interrupt triggered by a stop condition is detected. (2) Slave address register 0 (SVA0) This register stores seven bits of local addresses {A6, A5, A4, A3, A2, A1, A0} when in slave mode. The SVA0 register can be set by an 8-bit memory manipulation instruction. However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected). Reset signal generation clears the SVA0 register to 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 499 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-4. Format of Slave Address Register 0 (SVA0) Address: F0234H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 SVA0 A6 A5 A4 A3 A2 A1 A0 0Note Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAA0 pin's output level. (4) Wakeup controller This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the address value set to the slave address register 0 (SVA0) or when an extension code is received. (5) Serial clock counter This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify that 8-bit data was transmitted or received. (6) Interrupt request signal generator This circuit controls the generation of interrupt request signals (INTIICA0). An I2C interrupt request is generated by the following two triggers. * Falling edge of eighth or ninth clock of the serial clock (set by the WTIM0 bit) * Interrupt request generated when a stop condition is detected (set by the SPIE0 bit) Remark WTIM0 bit: Bit 3 of IICA control register 00 (IICCTL00) SPIE0 bit: Bit 4 of IICA control register 00 (IICCTL00) (7) Serial clock controller In master mode, this circuit generates the clock output via the SCLA0 pin from a sampling clock. (8) Serial clock wait controller This circuit controls the wait timing. (9) ACK generator, stop condition detector, start condition detector, and ACK detector These circuits generate and detect each status. (10) Data hold time correction circuit This circuit generates the hold time for data corresponding to the falling edge of the serial clock. (11) Start condition generator This circuit generates a start condition when the STT0 bit is set to 1. However, in the communication reservation disabled status (IICRSV0 bit = 1), when the bus is not released (IICBSY0 bit = 1), start condition requests are ignored and the STCF bit is set to 1. (12) Stop condition generator This circuit generates a stop condition when the SPT0 bit is set to 1. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 500 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit. Remark STT0 bit: Bit 1 of IICA control register 00 (IICCTL00) SPT0 bit: Bit 0 of IICA control register 00 (IICCTL00) IICRSV0 bit: Bit 0 of IICA flag register 0 (IICF0) IICBSY0 bit: Bit 6 of IICA flag register 0 (IICF0) STCF0 bit: Bit 7 of IICA flag register 0 (IICF0) STCEN0 bit: Bit 1 of IICA flag register 0 (IICF0) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 501 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.3 Registers Controlling Serial Interface IICA Serial interface IICA is controlled by the following eight registers. * Peripheral enable register 0 (PER0) * IICA control register 00 (IICCTL00) * IICA flag register 0 (IICF0) * IICA status register 0 (IICS0) * IICA control register 01 (IICCTL01) * IICA low-level width setting register 0 (IICWL0) * IICA high-level width setting register 0 (IICWH0) * Port mode register 6 (PM6) * Port register 6 (P6) 12.3.1 Peripheral enable register 0 (PER0) This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware macro that is not used is stopped in order to reduce the power consumption and noise. When serial interface IICA is used, be sure to set bit 4 (IICA0EN) of this register to 1. The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-5. Format of Peripheral Enable Register 0 (PER0) Address: F00F0H After reset: 00H R/W Symbol <7> 6 <5> <4> <3> <2> 1 <0> PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN IICA0EN 0 Control of serial interface IICA input clock supply Stops input clock supply. * SFR used by serial interface IICA cannot be written. * Serial interface IICA is in the reset status. 1 Enables input clock supply. * SFR used by serial interface IICA can be read/written. Cautions 1. When setting serial interface IICA, be sure to set the IICA0EN bit to 1 first. If IICA0EN = 0, writing to a control register of serial interface IICA is ignored, and, even if the register is read, only the default value is read (except for port mode register 6 (PM6) and port register 6 (P6)). 2. Be sure to clear the undefined bits to 0. 12.3.2 IICA control register 00 (IICCTL00) This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations. The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0, WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when the IICE0 bit is set from "0" to "1". Reset signal generation clears this register to 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 502 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register 00 (IICCTL00) (1/4) Address: F0230H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable Note 1 0 Stop operation. Reset the IICA status register 0 (IICS0) 1 Enable operation. . Stop internal operation. Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level. Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1) * Cleared by instruction * Set by instruction * Reset LREL0 Notes 2, Exit from communications 3 0 Normal operation 1 This exits from the current communications and sets standby mode. This setting is automatically cleared to 0 after being executed. Its uses include cases in which a locally irrelevant extension code has been received. The SCLA0 and SDAA0 lines are set to high impedance. The following flags of IICA control register 00 (IICCTL00) and the IICA status register 0 (IICS0) are cleared to 0. * STT0 * SPT0 * MSTS0 * EXC0 * COI0 * TRC0 * ACKD0 * STD0 The standby mode following exit from communications remains in effect until the following communications entry conditions are met. * After a stop condition is detected, restart is in master mode. * An address match or extension code reception occurs after the start condition. Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 2, WREL0 Wait cancellation 3 0 Do not cancel wait 1 Cancel wait. This setting is automatically cleared after wait is canceled. When the WREL0 bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status (TRC0 = 1), the SDAA0 line goes into the high impedance state (TRC0 = 0). Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1) * Automatically cleared after execution * Set by instruction * Reset Notes 1. The IICA status register 0 (IICS0), the STCF and IICBSY bits of the IICA flag register 0 (IICF0), and the CLD0 and DAD0 bits of IICA control register 01 (IICCTL01) are reset. 2. The signal of this bit is invalid while IICE0 is 0. 3. When the LREL0 and WREL0 bits are read, 0 is always read. Caution 2 If the operation of I C is enabled (IICE0 = 1) when the SCLA0 line is high level, the SDAA0 line is low level, and the digital filter is turned on (DFC0 bit of IICCTL01 register = 1), a start condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by 2 using a 1-bit memory manipulation instruction immediately after enabling operation of I C (IICE0 = 1). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 503 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register 00 (IICCTL00) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0 = 1. Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1) * Cleared by instruction * Reset * Set by instruction Note 1 WTIM0 0 Control of wait and interrupt request generation Interrupt request is generated at the eighth clock's falling edge. Master mode: After output of eight clocks, clock output is set to low level and wait is set. Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device. 1 Interrupt request is generated at the ninth clock's falling edge. Master mode: After output of nine clocks, clock output is set to low level and wait is set. Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device. An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) signal is issued. However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth clock. Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1, Acknowledgment control ACKE0 2 0 Disable acknowledgment. 1 Enable acknowledgment. During the ninth clock period, the SDAA0 line is set to low level. Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1) * Cleared by instruction * Set by instruction * Reset Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period. 2. The set value is invalid during address transfer and if the code is not an extension code. When the device serves as a slave and the addresses match, an acknowledgment is generated regardless of the set value. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 504 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register 00 (IICCTL00) (3/4) STT0 Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: * When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag. When set to 1, automatically generates a start condition after the bus is released. * When communication reservation function is disabled (IICRSV = 1) Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start condition is generated. In the wait state (when master device): Generates a restart condition after releasing the wait. Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and slave has been notified of final reception. * For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1 during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as stop condition trigger (SPT0). * Setting the STT0 bit to 1 and then setting it again before it is cleared condition is prohibited. Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1) * Cleared by setting the STT0 bit to 1 while * Set by instruction communication reservation is prohibited. * Cleared by loss in arbitration * Cleared after start condition is generated by master device * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Note The signal of this bit is invalid while IICE0 is 0. Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting. 2. IICRSV0: Bit 0 of IIC flag register 0 (IICF0) STCF0: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Bit 7 of IIC flag register 0 (IICF0) 505 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-6. Format of IICA Control Register 00 (IICCTL00) (4/4) SPT0 Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device's transfer). Cautions concerning set timing * For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and slave has been notified of final reception. * For master transmission: A stop condition cannot be generated normally during the acknowledge period. Therefore, set it during the wait period that follows output of the ninth clock. * Cannot be set to 1 at the same time as start condition trigger (STT0). * The SPT0 bit can be set to 1 only when in master mode. * When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM0 bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT0 bit should be set to 1 during the wait period that follows the output of the ninth clock. * Setting the SPT0 bit to 1 and then setting it again before it is cleared condition is prohibited. Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1) * Cleared by loss in arbitration * Set by instruction * Automatically cleared after stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When IICE0 = 0 (operation stop) * Reset Caution When bit 3 (TRC0) of the IICA status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0) of IICA control register 00 (IICCTL00) is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high impedance. Release the wait performed while the TRC0 bit is 1 (transmission status) by writing to the IICA shift register 0. Remark Bit 0 (SPT0) becomes 0 when it is read after data setting. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 506 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.3.3 IICA status register 0 (IICS0) 2 This register indicates the status of I C. The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICS0 register while the address match wakeup function is enabled (WUP0 = 1) in STOP mode is prohibited. When the WUP0 bit is changed from 1 to 0 (wakeup operation is stopped), regardless of the INTIICA0 interrupt request, the change in status is not reflected until the next start condition or stop condition is detected. To use the wakeup function, therefore, enable (SPIE0 = 1) the interrupt generated by detecting a stop condition and read the IICS0 register after the interrupt has been detected. Remark STT0: bit 1 of IICA control register 00 (IICCTL00) WUP0: bit 7 of IICA control register 01 (IICCTL01) Figure 12-7. Format of IICA Status Register 0 (IICS0) (1/3) Address: FFF51H After reset: 00H R Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0 MSTS0 Master status check flag 0 Slave device status or communication standby status 1 Master device communication status Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1) * When a stop condition is detected * When ALD0 = 1 (arbitration loss) * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset * When a start condition is generated ALD0 Detection of arbitration loss 0 This status means either that there was no arbitration or that the arbitration result was a "win". 1 This status indicates the arbitration result was a "loss". The MSTS0 bit is cleared. Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1) * Automatically cleared after the IICS0 register is Note read * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset * When the arbitration result is a "loss". Note This register is also cleared when a 1-bit memory manipulation instruction is executed for bits other than the IICS0 register. Therefore, when using the ALD0 bit, read the data of this bit before the data of the other bits. Remark LREL0: Bit 6 of IICA control register 00 (IICCTL00) IICE0: Bit 7 of IICA control register 00 (IICCTL00) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 507 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-7. Format of IICA Status Register 0 (IICS0) (2/3) EXC0 Detection of extension code reception 0 Extension code was not received. 1 Extension code was received. Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset * When the higher four bits of the received address COI0 data is either "0000" or "1111" (set at the rising edge of the eighth clock). Detection of matching addresses 0 Addresses do not match. 1 Addresses match. Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1) * When a start condition is detected * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset * When the received address matches the local TRC0 0 1 address (slave address register 0 (SVA0)) (set at the rising edge of the eighth clock). Detection of transmit/receive status Receive status (other than transmit status). The SDAA0 line is set for high impedance. Transmit status. The value in the SO0 latch is enabled for output to the SDAA0 line (valid starting at the falling edge of the first byte's ninth clock). Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1) <Both master and slave> <Master> * When a stop condition is detected * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) Note * Cleared by WREL0 = 1 (wait cancel) * When the ALD0 bit changes from 0 to 1 (arbitration loss) * Reset * When not used for communication (MSTS0, EXC0, COI0 = 0) <Master> * When "1" is output to the first byte's LSB (transfer direction specification bit) <Slave> * When a start condition is detected * When "0" is input to the first byte's LSB (transfer direction specification bit) * When a start condition is generated * When 0 (master transmission) is output to the LSB (transfer direction specification bit) of the first byte (during address transfer) <Slave> * When 1 (slave transmission) is input to the LSB (transfer direction specification bit) of the first byte from the master (during address transfer) Note When bit 3 (TRC0) of the IICA status register 0 (IICS0) is set to 1 (transmission status), bit 5 (WREL0) of IICA control register 00 (IICCTL00) is set to 1 during the ninth clock and wait is canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high impedance. Release the wait performed while the TRC0 bit is 1 (transmission status) by writing to the IICA shift register 0. Remark LREL0: IICE0: R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Bit 6 of IICA control register 00 (IICCTL00) Bit 7 of IICA control register 00 (IICCTL00) 508 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-7. Format of IICA Status Register 0 (IICS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected. Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1) * When a stop condition is detected * After the SDAA0 line is set to low level at the rising edge of SCLA0 line's ninth clock * At the rising edge of the next byte's first clock * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset STD0 Detection of start condition 0 Start condition was not detected. 1 Start condition was detected. This indicates that the address transfer period is in effect. Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1) * When a stop condition is detected * When a start condition is detected * At the rising edge of the next byte's first clock following address transfer * Cleared by LREL0 = 1 (exit from communications) * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset SPD0 0 1 Detection of stop condition Stop condition was not detected. Stop condition was detected. The master device's communication is terminated and the bus is released. Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1) * At the rising edge of the address transfer byte's first * When a stop condition is detected clock following setting of this bit and detection of a start condition * When the WUP0 bit changes from 1 to 0 * When the IICE0 bit changes from 1 to 0 (operation stop) * Reset Remark LREL0: Bit 6 of IICA control register 00 (IICCTL00) IICE0: Bit 7 of IICA control register 00 (IICCTL00) 12.3.4 IICA flag register 0 (IICF0) This register sets the operation mode of I2C and indicates the status of the I2C bus. The IICF0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag (STCF) and I2C bus status flag (IICBSY) bits are read-only. The IICRSV bit can be used to enable/disable the communication reservation function. The STCEN bit can be used to set the initial value of the IICBSY bit. The IICRSV and STCEN bits can be written only when the operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) = 0). When operation is enabled, the IICF0 register can be read. Reset signal generation clears this register to 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 509 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-8. Format of IICA Flag Register 0 (IICF0) Address: FFF52H After reset: 00H R/WNote Symbol <7> <6> 5 4 3 2 IICF0 STCF0 IICBSY0 0 0 0 0 STCF0 <1> <0> STCEN0 IICRSV0 STT0 clear flag 0 Generate start condition 1 Start condition generation unsuccessful: clear the STT0 flag Condition for clearing (STCF0 = 0) Condition for setting (STCF0 = 1) - Cleared by STT0 = 1 - When IICE0 = 0 (operation stop) - Reset - Generating start condition unsuccessful and the STT0 bit cleared to 0 when communication reservation is disabled (IICRSV0 = 1). I2C bus status flag IICBSY0 0 Bus release status (communication initial status when STCEN0 = 1) 1 Bus communication status (communication initial status when STCEN0 = 0) Condition for clearing (IICBSY0 = 0) Condition for setting (IICBSY0 = 1) - Detection of stop condition - When IICE0 = 0 (operation stop) - Reset - Detection of start condition - Setting of the IICE0 bit when STCEN0 = 0 STCEN0 Initial start enable trigger 0 After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of a stop condition. 1 After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting a stop condition. Condition for clearing (STCEN0 = 0) Condition for setting (STCEN0 = 1) - Cleared by instruction - Detection of start condition - Reset - Set by instruction IICRSV0 Communication reservation function disable bit 0 Enable communication reservation 1 Disable communication reservation Condition for clearing (IICRSV0 = 0) Condition for setting (IICRSV0 = 1) - Cleared by instruction - Reset - Set by instruction Note Bits 6 and 7 are read-only. Cautions 1. Write to the STCEN bit only when the operation is stopped (IICE0 = 0). 2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to verify that no third party communications are in progress in order to prevent such communications from being destroyed. 3. Write to IICRSV only when the operation is stopped (IICE0 = 0). Remark STT0: Bit 1 of IICA control register 00 (IICCTL00) IICE0: Bit 7 of IICA control register 00 (IICCTL00) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 510 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.3.5 IICA control register 01 (IICCTL01) 2 This register is used to set the operation mode of I C and detect the statuses of the SCLA0 and SDAA0 pins. The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. Set the IICCTL01 register, except the WUP0 bit, while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0). Reset signal generation clears this register to 00H. Figure 12-9. Format of IICA Control Register 01 (IICCTL01) (1/2) Address: F0231H After reset: 00H R/W Note 1 Symbol 7 6 <5> <4> <3> <2> 1 <0> IICCTL01 WUP0 0 CLD0 DAD0 SMC0 DFC0 0 PRS0 WUP0 Control of address match wakeup 0 Stops operation of address match wakeup function in STOP mode. 1 Enables operation of address match wakeup function in STOP mode. To shift to STOP mode when WUP0 = 1, execute the STOP instruction at least three clocks after setting (1) the WUP0 bit (see Figure 12-22 Flow When Setting WUP0 = 1). Clear (0) the WUP0 bit after the address has matched or an extension code has been received. The subsequent communication can be entered by the clearing (0) WUP0 bit. (The wait must be released and transmit data must be written after the WUP0 bit has been cleared (0).) The interrupt timing when the address has matched or when an extension code has been received, while WUP0 = 1, is identical to the interrupt timing when WUP0 = 0. (A delay of the difference of sampling by the clock will occur.) Furthermore, when WUP0 = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to 1. When WUP0 = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a start condition by setting (1) the STT0 bit, without waiting for the detection of the subsequent start condition or stop condition. Condition for clearing (WUP0 = 0) Condition for setting (WUP0 = 1) * Cleared by instruction (after address match or * Set by instruction (when the MSTS0, EXC0, and extension code reception) COI0 bits are "0", and the STD0 bit also "0" Note 2 (communication not entered)) Notes 1. Bits 4 and 5 are read-only. 2. The status of the IICA status register 0 (IICS0) must be checked and the WUP0 bit must be set during the period shown below. <1> <2> SCLA0 SDAA0 A6 A5 A4 A3 A2 A1 A0 R/W The maximum time from reading IICS0 to setting WUP0 is the period from <1> to <2>. Check the IICS0 operation status and set WUP0 during this period. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 511 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-9. Format of IICA Control Register 01 (IICCTL01) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) 0 The SCLA0 pin was detected at low level. 1 The SCLA0 pin was detected at high level. Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1) * When the SCLA0 pin is at low level * When the SCLA0 pin is at high level * When IICE0 = 0 (operation stop) * Reset DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1) 0 The SDAA0 pin was detected at low level. 1 The SDAA0 pin was detected at high level. Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1) * When the SDAA0 pin is at low level * When the SDAA0 pin is at high level * When IICE0 = 0 (operation stop) * Reset SMC0 Operation mode switching 0 Operates in standard mode (fastest transfer rate: 100 kbps). 1 Operates in fast mode (fastest transfer rate: 400 kbps). DFC0 Digital filter operation control 0 Digital filter off. 1 Digital filter on. Digital filter can be used only in fast mode. In fast mode, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0). The digital filter is used for noise elimination in fast mode. PRS0 Division of the operation clock 0 Selects fCLK as operation clock. 1 Selects fCLK/2 as operation clock. Caution The fastest operation frequency of the operation clock of the serial interface IICA is 20 MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRS0 bit to 1. Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 512 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.3.6 IICA low-level width setting register 0 (IICWL0) This register is used to set the low-level width (tLOW) of the SCLA0 pin signal that is output by serial interface IICA. The IICWL0 register can be set by an 8-bit memory manipulation instruction. Set the IICWL0 register while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0). Reset signal generation sets this register to FFH. For details about setting the IICWL0 register, see 12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers. Figure 12-10. Format of IICA Low-Level Width Setting Register 0 (IICWL0) Address: F0232H Symbol After reset: FFH R/W 7 6 5 4 3 2 1 0 IICWL0 12.3.7 IICA high-level width setting register 0 (IICWH0) This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA. The IICWH0 register can be set by an 8-bit memory manipulation instruction. Set the IICWH0 register while operation of I2C is disabled (bit 7 (IICE0) of IICA control register 00 (IICCTL00) is 0). Reset signal generation sets this register to FFH. Figure 12-11. Format of IICA High-Level Width Setting Register 0 (IICWH0) Address: F0233H Symbol After reset: FFH R/W 7 6 5 4 3 2 1 0 IICWH0 Remark For how to set the transfer clock by using the IICWL0 and IICWH0 registers, see 12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 513 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.3.8 Port mode register 6 (PM6) This register sets the input/output of port 6 in 1-bit units. When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and the output latches of P60 and P61 to 0. Set the IICE0 bit (bit 7 of IICA control register 00 (IICCTL00)) to 1 before setting the output mode because the P60/SCLA0 and P61/SDAA0 pins output a low level (fixed) when the IICE0 bit is 0. The PM6 register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 12-12. Format of Port Mode Register 6 (PM6) Address: FFF26H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM6 1 1 1 1 1 1 PM61 PM60 PM6n P6n pin I/O mode selection (n = 0, 1) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 514 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.4 I2C Bus Mode Functions 12.4.1 Pin configuration The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAA0 .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up resistor is required. Figure 12-13. Pin Configuration Diagram Slave device VDD Master device SCLA0 SCLA0 (Clock output) Clock output VDD VSS VSS Clock input (Clock input) SDAA0 SDAA0 Data output Data output VSS Data input R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 VSS Data input 515 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers (1) Setting transfer clock on master side fCLK Transfer clock = IICWL0 + IICWH0 + fCLK (tR + tF) At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows. (The fractional parts of all setting values are rounded up.) * When the fast mode 0.52 IICWL0 = Transfer clock x fCLK 0.48 IICWH0 = ( Transfer clock - tR - tF) x fCLK * When the normal mode 0.47 IICWL0 = Transfer clock x fCLK 0.53 IICWH0 = ( Transfer clock - tR - tF) x fCLK (2) Setting IICWL0 and IICWH0 registers on slave side (The fractional parts of all setting values are truncated.) * When the fast mode IICWL0 = 1.3 s x fCLK IICWH0 = (1.2 s - tR - tF) x fCLK * When the normal mode IICWL0 = 4.7 s x fCLK IICWH0 = (5.3 s - tR - tF) x fCLK Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK operation frequency for serial interface IICA is determined according to the mode. Fast mode: fCLK = 3.5 MHz (MIN.) Normal mode: fCLK = 1 MHz (MIN.) In addition, the fastest operation frequency of the operation clock of the serial interface IICA is 20 MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRS0 bit of IICCTL01 register to 1. Remarks 1. Calculate the rise time (tR) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because they differ depending on the pull-up resistance and wire load. 2. IICWL0: IICA low-level width setting register 0 IICWH0: IICA high-level width setting register 0 tF: SDAA0 and SCLA0 signal falling times tR: SDAA0 and SCLA0 signal rising times fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 516 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus's serial data communication format and the signals used by the I2C bus. Figure 12-14 shows the transfer timing for the "start condition", "address", "data", and "stop condition" output via the I2C bus's serial data bus. 2 Figure 12-14. I C Bus Serial Data Transfer Timing SCLA0 1-7 8 9 1-8 9 1-8 9 ACK Data ACK SDAA0 Start condition Address R/W ACK Data Stop condition The master device generates the start condition, slave address, and stop condition. The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that receives 8-bit data). The serial clock (SCLA0) is continuously output by the master device. However, in the slave device, the SCLA0 pin low level period can be extended and a wait can be inserted. 12.5.1 Start conditions A start condition is met when the SCLA0 pin is at high level and the SDAA0 pin changes from high level to low level. The start conditions for the SCLA0 pin and SDAA0 pin are signals that the master device generates to the slave device when starting a serial transfer. When the device is used as a slave, start conditions can be detected. Figure 12-15. Start Conditions SCLA0 H SDAA0 A start condition is output when bit 1 (STT0) of IICA control register 00 (IICCTL00) is set (1) after a stop condition has been detected (SPD0: Bit 0 of the IICA status register 0 (IICS0) = 1). When a start condition is detected, bit 1 (STD0) of the IICS0 register is set (1). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 517 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address. The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data matches the data values stored in the slave address register 0 (SVA0). If the address data matches the SVA0 register values, the slave device is selected and communicates with the master device until the master device generates a start condition or stop condition. Figure 12-16. Address SCLA0 1 2 3 4 5 6 7 8 SDAA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Address Note INTIICA0 Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device operation. Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in 12.5.3 Transfer direction specification are written to the IICA shift register 0 (IICA0). The received addresses are written to the IICA0 register. The slave address is assigned to the higher 7 bits of the IICA0 register. 12.5.3 Transfer direction specification In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction. When this transfer direction specification bit has a value of "0", it indicates that the master device is transmitting data to a slave device. When the transfer direction specification bit has a value of "1", it indicates that the master device is receiving data from a slave device. Figure 12-17. Transfer Direction Specification SCLA0 1 2 3 4 5 6 7 8 SDAA0 A6 A5 A4 A3 A2 A1 A0 R/W 9 Transfer direction specification INTIICA0 Note Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device operation. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 518 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued. Whether ACK has been detected can be checked by using bit 2 (ACKD0) of the IICA status register 0 (IICS0). When the master receives the last data item, it does not return ACK and instead generates a stop condition. If a slave does not return ACK after receiving data, the master outputs a stop condition or restart condition and stops transmission. If ACK is not returned, the possible causes are as follows. <1> Reception was not performed normally. <2> The final data item was received. <3> The reception side specified by the address does not exist. To generate ACK, the reception side makes the SDAA0 line low at the ninth clock (indicating normal reception). Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IICA control register 00 (IICCTL00) to 1. Bit 3 (TRC0) of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set the ACKE0 bit to 1 for reception (TRC0 = 0). If a slave can receive no more data during reception (TRC0 = 0) or does not require the next data item, then the slave must inform the master, by clearing the ACKE0 bit to 0, that it will not receive any more data. When the master does not require the next data item during reception (TRC0 = 0), it must clear the ACKE0 bit to 0 so that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any more data (transmission will be stopped). Figure 12-18. ACK SCLA0 1 2 3 4 5 6 7 8 9 SDAA0 A6 A5 A4 A3 A2 A1 A0 R/W ACK When the local address is received, ACK is automatically generated, regardless of the value of the ACKE0 bit. When an address other than that of the local address is received, ACK is not generated (NACK). When an extension code is received, ACK is generated if the ACKE0 bit is set to 1 in advance. How ACK is generated when data is received differs as follows depending on the setting of the wait timing. * When 8-clock wait state is selected (bit 3 (WTIM0) of IICCTL00 register = 0): By setting the ACKE0 bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock of the SCLA0 pin. * When 9-clock wait state is selected (bit 3 (WTIM0) of IICCTL00 register = 1): ACK is generated by setting the ACKE0 bit to 1 in advance. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 519 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 12-19. Stop Condition SCLA0 H SDAA0 A stop condition is generated when bit 0 (SPT0) of IICA control register 00 (IICCTL00) is set to 1. When the stop condition is detected, bit 0 (SPD0) of the IICA status register 0 (IICS0) is set to 1 and INTIICA0 is generated when bit 4 (SPIE0) of the IICCTL00 register is set to 1. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 520 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 12-20. Wait (1/2) (1) When master device has a nine-clock wait and slave device has an eight-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master returns to high impedance but slave is in wait state (low level). IICA0 Wait after output of ninth clock IICA0 data write (cancel wait) SCLA0 6 7 8 9 1 2 3 Slave Wait after output of eighth clock FFH is written to IICA0 or WREL0 is set to 1 IICA0 SCLA0 ACKE0 H Transfer lines Wait from slave SCLA0 6 7 8 SDAA0 D2 D1 D0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Wait from master 9 ACK 1 2 3 D7 D6 D5 521 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-20. Wait (2/2) (2) When master and slave devices both have a nine-clock wait (master transmits, slave receives, and ACKE0 = 1) Master Master and slave both wait after output of ninth clock IICA0 data write (cancel wait) IICA0 6 SCLA0 7 8 9 1 2 3 Slave FFH is written to IICA0 or WREL0 is set to 1 IICA0 SCLA0 ACKE0 H Wait from master and slave Transfer lines SCLA0 6 7 8 9 SDAA0 D2 D1 D0 ACK Wait from slave 1 D7 2 3 D6 D5 Generate according to previously set ACKE0 value Remark ACKE0: Bit 2 of IICA control register 00 (IICCTL00) WREL0: Bit 5 of IICA control register 00 (IICCTL00) A wait may be automatically generated depending on the setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00). Normally, the receiving side cancels the wait state when bit 5 (WREL0) of the IICCTL00 register is set to 1 or when FFH is written to the IICA shift register 0 (IICA0), and the transmitting side cancels the wait state when data is written to the IICA0 register. The master device can also cancel the wait state via either of the following methods. * By setting bit 1 (STT0) of the IICCTL00 register to 1 * By setting bit 0 (SPT0) of the IICCTL00 register to 1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 522 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.7 Canceling wait 2 The I C usually cancels a wait state by the following processing. * Writing data to the IICA shift register 0 (IICA0) * Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait) * Setting bit 1 (STT0) of the IICCTL00 register (generating start condition)Note * Setting bit 0 (SPT0) of the IICCTL00 register (generating stop condition)Note Note Master only 2 When the above wait canceling processing is executed, the I C cancels the wait state and communication is resumed. To cancel a wait state and transmit data (including addresses), write the data to the IICA0 register. To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IICCTL00 register to 1. To generate a restart condition after canceling a wait state, set bit 1 (STT0) of the IICCTL00 register to 1. To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of the IICCTL00 register to 1. Execute the canceling processing only once for one wait state. If, for example, data is written to the IICA0 register after canceling a wait state by setting the WREL0 bit to 1, an incorrect value may be output to SDAA0 line because the timing for changing the SDAA0 line conflicts with the timing for writing the IICA0 register. In addition to the above, communication is stopped if the IICE0 bit is cleared to 0 when communication has been aborted, so that the wait state can be canceled. If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of the IICCTL00 register, so that the wait state can be canceled. Caution If a processing to cancel a wait state is executed when WUP0 = 1, the wait state will not be canceled. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 523 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 12-2. Table 12-2. INTIICA0 Generation Timing and Wait Control WTIM0 During Slave Device Operation Address 0 1 9 Notes 1, 2 9 Notes 1, 2 Data Reception 8 Note 2 9 Note 2 During Master Device Operation Data Transmission Address Data Reception Data Transmission 8 Note 2 9 8 8 9 Note 2 9 9 9 Notes 1. The slave device's INTIICA0 signal and wait period occurs at the falling edge of the ninth clock only when there is a match with the address set to the slave address register 0 (SVA0). At this point, ACK is generated regardless of the value set to the IICCTL00 register's bit 2 (ACKE0). For a slave device that has received an extension code, INTIICA0 occurs at the falling edge of the eighth clock. However, if the address does not match after restart, INTIICA0 is generated at the falling edge of the 9th clock, but wait does not occur. 2. If the received address does not match the contents of the slave address register 0 (SVA0) and extension code is not received, neither INTIICA0 nor a wait occurs. Remark The numbers in the table indicate the number of the serial clock's clock signals. Interrupt requests and wait control are both synchronized with the falling edge of these clock signals. (1) During address transmission/reception * Slave device operation: Interrupt and wait timing are determined depending on the conditions described in Notes 1 and 2 above, regardless of the WTIM0 bit. * Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the WTIM0 bit. (2) During data reception * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (3) During data transmission * Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit. (4) Wait cancellation method The four wait cancellation methods are as follows. * Writing data to the IICA shift register 0 (IICA0) * Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait) * Setting bit 1 (STT0) of IICCTL00 register (generating start condition)Note * Setting bit 0 (SPT0) of IICCTL00 register (generating stop condition)Note Note Master only. When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be determined prior to wait cancellation. (5) Stop condition detection INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 524 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.9 Address match detection method 2 In I C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware. An interrupt request (INTIICA0) occurs when the address set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension code has been received. 12.5.10 Error detection In I2C bus mode, the status of the serial data bus (SDAA0) during data transmission is captured by the IICA shift register 0 (IICA0) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the compared data values do not match. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 525 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.11 Extension code (1) When the higher 4 bits of the receive address are either "0000" or "1111", the extension code reception flag (EXC0) is set to 1 for extension code reception and an interrupt request (INTIICA0) is issued at the falling edge of the eighth clock. The local address stored in the slave address register 0 (SVA0) is not affected. (2) The settings below are specified if 11110xx0 is transferred from the master by using a 10-bit address transfer when the SVA0 register is set to 11110xx0. Note that INTIICA0 occurs at the falling edge of the eighth clock. * Higher four bits of data match: EXC0 = 1 * Seven bits of data match: Remark COI0 = 1 EXC0: Bit 5 of IICA status register 0 (IICS0) COI0: Bit 4 of IICA status register 0 (IICS0) (3) Since the processing after the interrupt request occurs differs according to the data that follows the extension code, such processing is performed by software. If the extension code is received while a slave device is operating, then the slave device is participating in communication even if its address does not match. For example, after the extension code is received, if you do not wish to operate the target device as a slave device, set bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 to set the standby mode for the next communication operation. Table 12-3. Bit Definitions of Major Extension Codes Slave Address R/W Bit 0000 000 0 1111 0xx 0 Description General call address 10-bit slave address specification (during address authentication) 1111 0xx 1 10-bit slave address specification (after address match, when read command is issued) Remark See the I2C bus specifications issued by NXP Semiconductors for details of extension codes other than those described above. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 526 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration. When one of the master devices loses in arbitration, an arbitration loss flag (ALD0) in the IICA status register 0 (IICS0) is set (1) via the timing by which the arbitration loss occurred, and the SCLA0 and SDAA0 lines are both set to high impedance, which releases the bus. The arbitration loss is detected based on the timing of the next interrupt request (the eighth or ninth clock, when a stop condition is detected, etc.) and the ALD0 = 1 setting that has been made by software. For details of interrupt request timing, see 12.5.8 Interrupt request (INTIICA0) generation timing and wait control. Remark STD0: Bit 1 of IICA status register 0 (IICS0) STT0: Bit 1 of IICA control register 00 (IICCTL00) Figure 12-21. Arbitration Timing Example Master 1 SCLA0 SDAA0 Master 2 Hi-Z Hi-Z Master 1 loses arbitration SCLA0 SDAA0 Transfer lines SCLA0 SDAA0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 527 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Table 12-4. Status During Arbitration and Interrupt Request Generation Timing Status During Arbitration During address transmission Interrupt Request Generation Timing At falling edge of eighth or ninth clock following byte transfer Note 1 Read/write data after address transmission During extension code transmission Read/write data after extension code transmission During data transmission During ACK transfer period after data transmission When restart condition is detected during data transfer Note 2 When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1) When data is at low level while attempting to generate a restart At falling edge of eighth or ninth clock following byte transfer condition 1 When stop condition is detected while attempting to generate a When stop condition is generated (when SPIE0 = 1) Note Note 2 restart condition When data is at low level while attempting to generate a stop At falling edge of eighth or ninth clock following byte transfer condition 1 Note When SCLA0 is at low level while attempting to generate a restart condition Notes 1. When the WTIM0 bit (bit 3 of IICA control register 00 (IICCTL00)) = 1, an interrupt request occurs at the falling edge of the ninth clock. When WTIM0 = 0 and the extension code's slave address is received, an interrupt request occurs at the falling edge of the eighth clock. 2. When there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation. Remark SPIE0: Bit 4 of IICA control register 00 (IICCTL00) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 528 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.13 Wakeup function 2 The I C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has generated a start condition) to a slave device. To use the wakeup function in the STOP mode, set the WUP0 bit to 1. Addresses can be received regardless of the operation clock. An interrupt request signal (INTIICA0) is also generated when a local address and extension code have been received. Operation returns to normal operation by using an instruction to clear (0) the WUP0 bit after this interrupt has been generated. Figure 12-22 shows the flow for setting WUP0 = 1 and Figure 12-23 shows the flow for setting WUP0 = 0 upon an address match. Figure 12-22. Flow When Setting WUP0 = 1 START MSTS0 = STD0 = EXC0 = COI0 =0? No Yes WUP0 = 1 Wait Waits for 3 clocks. STOP instruction execution R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 529 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-23. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception) STOP mode state No INTIICA0 = 1? Yes WUP0 = 0 Wait Waits for 5 clocks. Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. Use the following flows to perform the processing to release the STOP mode other than by an interrupt request (INTIICA0) generated from serial interface IICA. * Master device operation: Flow shown in Figure 12-24 * Slave device operation: Same as the flow in Figure 12-23 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 530 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP0 = 1 STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0. WUP0 = 0 No INTIICA0 = 1? Yes Wait Generates a STOP condition or selects as a slave device. Waits for 5 clocks. Reading IICS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 531 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released by setting bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 and saving communication). If bit 1 (STT0) of the IICCTL00 register is set to 1 while the bus is not used (after a stop condition is detected), a start condition is automatically generated and wait state is set. If an address is written to the IICA shift register 0 (IICA0) after bit 4 (SPIE0) of the IICCTL00 register was set to 1, and it was detected by generation of an interrupt request signal (INTIICA0) that the bus was released (detection of the stop condition), then the device automatically starts communication as the master. Data written to the IICA0 register before the stop condition is detected is invalid. When the STT0 bit has been set to 1, the operation mode (as start condition or as communication reservation) is determined according to the bus status. * If the bus has been released ........................................ a start condition is generated * If the bus has not been released (standby mode)......... communication reservation Check whether the communication reservation operates or not by using the MSTS0 bit (bit 7 of the IICA status register 0 (IICS0)) after the STT0 bit is set to 1 and the wait time elapses. Use software to secure the wait time calculated by the following expression. Wait time from setting STT0 = 1 to checking the MSTS0 flag: (IICWL0 setting value + IICWH0 setting value + 4) + tF x 2 x fCLK [clocks] Remark IICWL0: IICA low-level width setting register 0 IICWH0: IICA high-level width setting register 0 tF: SDAA0 and SCLA0 signal falling times fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 532 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-25 shows the communication reservation timing. Figure 12-25. Communication Reservation Timing Program processing Write to IICA0 STT0 = 1 CommuniHardware processing cation reservation SCLA0 1 2 3 4 Set SPD0 and INTIICA0 5 6 7 8 9 Set STD0 1 2 3 4 5 6 SDAA0 Generate by master device with bus mastership Remark IICA0: IICA shift register 0 STT0: Bit 1 of IICA control register 00 (IICCTL00) STD0: Bit 1 of IICA status register 0 (IICS0) SPD0: Bit 0 of IICA status register 0 (IICS0) Communication reservations are accepted via the timing shown in Figure 12-26. After bit 1 (STD0) of the IICA status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IICA control register 00 (IICCTL00) to 1 before a stop condition is detected. Figure 12-26. Timing for Accepting Communication Reservations SCLA0 SDAA0 STD0 SPD0 Standby mode (Communication can be reserved by setting STT0 to 1 during this period.) Figure 12-27 shows the communication reservation protocol. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 533 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-27. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note 2 MSTS0 = 0? Yes Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software. Confirmation of communication reservation No (Generate start condition) Cancel communication reservation MOV IICA0, #xxH Clear user flag IICA0 write operation EI Notes 1. The wait time is calculated as follows. (IICWL0 setting value + IICWH0 setting value + 4) + tF x 2 x fCLK [clocks] 2. The communication reservation operation executes a write to the IICA shift register 0 (IICA0) when a stop condition interrupt request occurs. Remark STT0: Bit 1 of IICA control register 00 (IICCTL00) MSTS0: Bit 7 of IICA status register 0 (IICS0) IICA0: IICA shift register 0 IICWL0: IICA low-level width setting register 0 IICWH0: IICA high-level width setting register 0 tF: SDAA0 and SCLA0 signal falling times fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 534 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 1) When bit 1 (STT0) of IICA control register 00 (IICCTL00) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used. * When arbitration results in neither master nor slave operation * When an extension code is received and slave operation is disabled (ACK is not returned and the bus was released by setting bit 6 (LREL0) of the IICCTL00 register to 1 and saving communication) To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of the IICF0 register). It takes up to 5 clocks until the STCF bit is set to 1 after setting STT0 = 1. Therefore, secure the time by software. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 535 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.15 Cautions (1) When STCEN = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized regardless of the actual bus status. When changing from a mode in which no stop condition has been detected to a master device communication mode, first generate a stop condition to release the bus, then perform master device communication. When using multiple masters, it is not possible to perform master device communication when the bus has not been released (when a stop condition has not been detected). Use the following sequence for generating a stop condition. <1> Set IICA control register 01 (IICCTL01). <2> Set bit 7 (IICE0) of IICA control register 00 (IICCTL00) to 1. <3> Set bit 0 (SPT0) of the IICCTL00 register to 1. (2) When STCEN = 1 Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized regardless of the actual bus status. To generate the first start condition (STT0 = 1), it is necessary to confirm that the bus has been released, so as to not disturb other communications. (3) If other I2C communications are already in progress If I2C operation is enabled and the device participates in communication already in progress when the SDAA0 pin is low and the SCLA0 pin is high, the macro of I2C recognizes that the SDAA0 pin has gone low (detects a start condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this interferes with other I2C communications. To avoid this, start I2C in the following sequence. <1> Clear bit 4 (SPIE0) of the IICCTL00 register to 0 to disable generation of an interrupt request signal (INTIICA0) when the stop condition is detected. <2> Set bit 7 (IICE0) of the IICCTL00 register to 1 to enable the operation of I2C. <3> Wait for detection of the start condition. <4> Set bit 6 (LREL0) of the IICCTL00 register to 1 before ACK is returned (4 to 80 clocks after setting the IICE0 bit to 1), to forcibly disable detection. (4) Setting the STT0 and SPT0 bits (bits 1 and 0 of the IICCTL00 register) again after they are set and before they are cleared to 0 is prohibited. (5) When transmission is reserved, set the SPIE0 bit (bit 4 of the IICTL0 register) to 1 so that an interrupt request is generated when the stop condition is detected. Transfer is started when communication data is written to the IICA shift register 0 (IICA0) after the interrupt request is generated. Unless the interrupt is generated when the stop condition is detected, the device stops in the wait state because the interrupt request is not generated when communication is started. However, it is not necessary to set the SPIE0 bit to 1 when the MSTS0 bit (bit 7 of the IICA status register 0 (IICS0)) is detected by software. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 536 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the RL78/G12 as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup. If communication with the slave is required, prepare the communication and then execute communication processing. (2) Master operation in multimaster system 2 2 In the I C bus multimaster system, whether the bus is released or used cannot be judged by the I C bus specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a certain period (1 frame), the RL78/G12 takes part in a communication with bus released state. This flowchart is broadly divided into the initial settings, communication waiting, and communication processing. The processing when the RL78/G12 looses in arbitration and is specified as the slave is omitted here, and only the processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then, wait for the communication request as the master or wait for the specification as the slave. The actual communication is performed in the communication processing, and it supports the transmission/reception with the slave and the arbitration with other masters. (3) Slave operation An example of when the RL78/G12 is used as the I2C bus slave is shown below. When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the INTIICA0 interrupt occurrence (communication waiting). When an INTIICA0 interrupt occurs, the communication status is judged and its result is passed as a flag over to the main processing. By checking the flags, necessary communication processing is performed. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 537 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 12-28. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6)). Setting port IICWL0, IICWH0 XXH Sets a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN0, IICRSV0 = 0 Sets a start condition. Initial setting Setting IICCTL01 IICCTL00 0XX111XXB ACKE0 = WTIM0 = SPIE0 = 1 IICCTL00 1XX111XXB IICE0 = 1 2 Set the port from input mode to output mode and enable the output of the I C bus (see 12.3 (8) Port mode register 6 (PM6)). Setting port STCEN0 = 1? Yes No SPT0 = 1 INTIICA0 interrupt occurs? Prepares for starting communication (generates a stop condition). No Waits for detection of the stop condition. Yes STT0 = 1 Prepares for starting communication (generates a start condition). Writing IICA0 Starts communication (specifies an address and transfer direction). INTIICA0 interrupt occurs? No Waits for detection of acknowledge. Yes No ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Communication processing Yes Writing IICA0 Starts transmission. WREL0 = 1 INTIICA0 interrupt occurs? No Waits for data transmission. INTIICA0 interrupt occurs? Yes Yes ACKD0 = 1? No Starts reception. No Waits for data reception. Reading IICA0 Yes No End of transfer? No End of transfer? Yes Yes Restart? Yes ACKE0 = 0 WTIM0 = WREL0 = 1 No SPT0 = 1 INTIICA0 interrupt occurs? Yes No Waits for detection of acknowledge. END Note Release (SCLA0 and SDAA0 pins = high level) the I2C bus in conformance with the specifications of the product that is communicating. If EEPROM is outputting a low level to the SDAA0 pin, for example, set the SCLA0 pin in the output port mode, and output a clock pulse from the output port until the SDAA0 pin is constantly at high level. Remark Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 538 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 12-29. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6)). Setting port IICWL0, IICWH0 XXH Selects a transfer clock. SVA0 XXH Sets a local address. IICF0 0XH Setting STCEN0 and IICRSV0 Sets a start condition. Setting IICCTL01 IICCTL00 0XX111XXB ACKE0 = WTIM0 = SPIE0 = 1 Initial setting IICCTL00 1XX111XXB IICE0 = 1 2 Set the port from input mode to output mode and enable the output of the I C bus (see 12.3 (8) Port mode register 6 (PM6)). Setting port Checking bus statusNote Releases the bus for a specific period. Bus status is being checked. No No STCEN0 = 1? INTIICA0 interrupt occurs? Prepares for starting communication (generates a stop condition). SPT0 = 1 Yes Yes SPD0 = 1? INTIICA0 interrupt occurs? No Yes Yes Slave operation SPD0 = 1? No Waits for detection of the stop condition. No Yes 1 Waits for a communication Slave operation * Waiting to be specified as a slave by other master * Waiting for a communication start request (depends on user program) Master operation starts? No (No communication start request) Yes (Communication start request) SPIE0 = 0 INTIICAn interrupt occurs? SPIE0 = 1 No Waits for a communication request. Yes IICRSV0 = 0? No Slave operation Yes A B Enables reserving Disables reserving communication. communication. Note Confirm that the bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specific period (for example, for a period of one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I2C bus (SCLA0 and SDAA0 pins = high level) in conformance with the specifications of the product that is communicating. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 539 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-29. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Secure wait timeNote by software. Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIICA0 interrupt occurs? No Waits for bus release (communication being reserved). Yes No Wait state after stop condition was detected and start condition was generated by the communication reservation function. EXC0 = 1 or COI0 =1? Yes C Slave operation B Disables reserving communication. IICBSY0 = 0? No Yes D Communication processing STT0 = 1 Prepares for starting communication (generates a start condition). WaitNote STCF0 = 0? No Yes INTIICA0 interrupt occurs? No Waits for bus release Yes C EXC0 = 1 or COI0 =1? No Detects a stop condition. Yes Slave operation D Note The wait time is calculated as follows. (IICWL0 setting value + IICWH0 setting value + 4) x fCLK + tF x 2 [clocks] Remark IICWL0: IICA low-level width setting register 0 IICWH0: IICA high-level width setting register 0 tF: SDAA0 and SCLA0 signal falling times fCLK: CPU/peripheral hardware clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 540 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-29. Master Operation in Multi-Master System (3/3) C Writing IICA0 INTIICA0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IICA0 Starts transmission. INTIICA0 interrupt occurs? INTIICA0 interrupt occurs? No Waits for data transmission. Yes MSTS0 = 1? No Waits for data reception. Yes MSTS0 = 1? No No Yes Yes ACKD0 = 1? Starts reception. 2 2 Reading IICA0 No Transfer end? No Yes Yes No WTIM0 = WREL0 = 1 ACKE0 = 00 Transfer end? Yes Restart? INTIICA0 interrupt occurs? No No Waits for detection of ACK. Yes SPT0 = 1 Yes MSTS0 = 1? STT0 = 1 END Yes No 2 Communication processing C 2 EXC0 = 1 or COI0 = 1? Yes Slave operation No 1 Does not participate in communication. Remarks 1. Conform to the specifications of the product that is communicating, with respect to the transmission and reception formats. 2. To use the device as a master in a multi-master system, read the MSTS0 bit each time interrupt INTIICA0 has occurred to check the arbitration result. 3. To use the device as a slave in a multi-master system, check the status by using the IICA status register 0 (IICS0) and IICA flag register 0 (IICF0) each time interrupt INTIICA0 has occurred, and determine the processing to be performed next. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 541 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (3) Slave operation The processing procedure of the slave operation is as follows. Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication. It is also assumed that the INTIICA0 interrupt servicing only performs status transition processing, and that actual data communication is performed by the main processing. INTIICA0 Flag Interrupt servicing Setting Main processing IICA Data Setting Therefore, data communication processing is performed by preparing the following three flags and passing them to the main processing instead of INTIICA0. <1> Communication mode flag This flag indicates the following two communication statuses. * Clear mode: Status in which data communication is not performed * Communication mode: Status in which data communication is performed (from valid address detection to stop condition detection, no detection of ACK from master, address mismatch) <2> Ready flag This flag indicates that data communication is enabled. Its function is the same as the INTIICA0 interrupt for ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing. Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag being cleared (an address match is interpreted as a request for the next data). <3> Communication direction flag This flag indicates the direction of communication. Its value is the same as the TRC0 bit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 542 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the master, communication is completed. For reception, the necessary amount of data is received. When communication is completed, ACK is not returned as the next data. After that, the master generates a stop condition or restart condition. Exit from the communication status occurs in this way. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 543 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-30. Slave Operation Flowchart (1) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6)). Setting port IICWL0, IICWH0 XXH Selects a transfer clock. Initial setting SVA0 XXH Sets a local address. IICF0 0XH Sets a start condition. Setting IICRSV0 Setting IICCTL01 IICCTLn0 0XX011XXB ACKE0 = WTIM0 = 1, SPI0 = 0 IICCTL00 1XX011XXB IICE0 = 1 Set the port from input mode to output mode and enable the output of the I2C bus (see 12.3 (8) Port mode register 6 (PM6)). Setting port No Communication mode flag = 1? Yes Communication direction flag = 1? No Yes WREL0 = 1 Writing IICA0 Communication processing No Starts transmission. Communication mode flag = 1? Communication mode flag = 1? No Yes Yes No Starts reception. Communication direction flag = 1? Communication direction flag = 1? No Yes No Yes No Ready flag = 1? Ready flag = 1? Yes Yes Reading IICA0 Clearing ready flag Yes Clearing ready flag ACKD0 = 1? No Clearing communication mode flag WREL0 = 1 Remark Conform to the specifications of the product that is in communication, regarding the transmission and reception formats. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 544 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match. If the address matches, the communication mode is set, wait is cancelled, and processing returns from the interrupt (the ready flag is cleared). <3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus remaining in the wait state. Remark <1> to <3> above correspond to <1> to <3> in Figure 12-31 Slave Operation Flowchart (2). Figure 12-31. Slave Operation Flowchart (2) INTIICA0 generated Yes <1> Yes <2> SPD0 = 1? No STD0 = 1? No No <3> COI0 = 1? Yes Set ready flag Communication direction flag TRC0 Set communication mode flag Clear ready flag Clear communication direction flag, ready flag, and communication mode flag Interrupt servicing completed 2 12.5.17 Timing of I C interrupt request (INTIICA0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the IICA status register 0 (IICS0) when the INTIICA0 signal is generated are shown below. Remark ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 545 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B 3: IICS0 = 1000x000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1000xx00B (Sets the SPT0 bit to 1)Note 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B 3: IICS0 = 1000xx00B (Sets the SPT0 bit to 1) 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 546 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets the WTIM0 bit to 1)Note 1 3: IICS0 = 1000xx00B (Clears the WTIM0 bit to 0Note 2, sets the STT0 bit to 1) 4: IICS0 = 1000x110B 5: IICS0 = 1000x000B (Sets the WTIM0 bit to 1)Note 3 6: IICS0 = 1000xx00B (Sets the SPT0 bit to 1) 7: IICS0 = 00000001B Notes 1. To generate a start condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal. 2. Clear the WTIM0 bit to 0 to restore the original setting. 3. To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 SPT0 = 1 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets the STT0 bit to 1) 3: IICS0 = 1000x110B 4: IICS0 = 1000xx00B (Sets the SPT0 bit to 1) 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 547 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICS0 = 1010x110B 2: IICS0 = 1010x000B 3: IICS0 = 1010x000B (Sets the WTIM0 bit to 1)Note 4: IICS0 = 1010xx00B (Sets the SPT0 bit to 1) 5: IICS0 = 00000001B Note To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0 interrupt request signal. Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 1010x110B 2: IICS0 = 1010x100B 3: IICS0 = 1010xx00B (Sets the SPT0 bit to 1) 4: IICS0 = 00001001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 548 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 549 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0001x110B 4: IICS0 = 0001xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 550 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK 3 D7 to D0 4 ACK SP 5 6 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 0010x010B 4: IICS0 = 0010x110B 5: IICS0 = 0010xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 551 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0001x110B 2: IICS0 = 0001x000B 3: IICS0 = 00000x10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 1: IICS0 = 0001x110B 2: IICS0 = 0001xx00B 3: IICS0 = 00000x10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 552 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code. (a) Start ~ Code ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 553 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0001x110B 4: IICS0 = 0001x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0001x110B 5: IICS0 = 0001xx00B 6: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 554 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x010B 4: IICS0 = 0010x000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK 4 D7 to D0 5 ACK SP 6 7 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 0010x010B 5: IICS0 = 0010x110B 6: IICS0 = 0010xx00B 7: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 555 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICS0 = 0010x010B 2: IICS0 = 0010x000B 3: IICS0 = 00000x10B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 ST 3 AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 1: IICS0 = 0010x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010xx00B 4: IICS0 = 00000x10B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 556 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x000B 3: IICS0 = 0001x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 557 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICS0 = 0101x110B 2: IICS0 = 0001x100B 3: IICS0 = 0001xx00B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICS0 = 0110x010B 2: IICS0 = 0010x000B 3: IICS0 = 0010x000B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 558 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICS0 = 0110x010B 2: IICS0 = 0010x110B 3: IICS0 = 0010x100B 4: IICS0 = 0010xx00B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result. (a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 ACK SP 2 1: IICS0 = 01000110B 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 559 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICS0 = 0110x010B Sets LREL0 = 1 by software 2: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICS0 = 10001110B 2: IICS0 = 01000000B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 560 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICS0 = 10001110B 2: IICS0 = 01000100B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01000110B 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 561 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICS0 = 1000x110B 2: IICS0 = 01100010B Sets LREL0 = 1 by software 3: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICS0 = 10000110B 2: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care n = 6 to 0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 562 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000x100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000000B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets the STT0 bit to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 563 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000xx00B (Sets the STT0 bit to 1) 4: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 STT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3 1: IICS0 = 1000x110B 2: IICS0 = 1000xx00B (Sets the STT0 bit to 1) 3: IICS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 564 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICS0 = 1000x110B 2: IICS0 = 1000x000B (Sets the WTIM0 bit to 1) 3: IICS0 = 1000x100B (Clears the WTIM0 bit to 0) 4: IICS0 = 01000100B 5: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care (ii) When WTIM0 = 1 SPT0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 2 ACK D7 to D0 3 ACK SP 4 1: IICS0 = 1000x110B 2: IICS0 = 1000x100B (Sets the SPT0 bit to 1) 3: IICS0 = 01000100B 4: IICS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 x: Don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 565 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA 12.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)), which specifies the data transfer direction, and then starts serial communication with the slave device. Figures 12-32 and 12-33 show timing charts of the data communication. The IICA shift register 0 (IICA0)'s shift operation is synchronized with the falling edge of the serial clock (SCLA0). The transmit data is transferred to the SO latch and is output (MSB first) via the SDAA0 pin. Data input via the SDAA0 pin is captured into IICA0 at the rising edge of SCLA0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 566 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4) (1) Start condition ~ address ~ data Master side Note 1 IICA0 <2> <5> ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) H ACKE0 (ACK control) H MSTS0 (communication status) STT0 (ST trigger) SPT0 (SP trigger) WREL0 (wait cancellation) <1> L L INTIICA0 (interrupt) TRC0 (transmit/receive) Start condition Bus line SCLA0 (bus) (clock line) Note 2 SDAA0 (bus) (data line) <4> AD6 AD5 AD4 AD3 AD2 Slave address AD1 AD0 W D17 ACK <3> Slave side IICA0 ACKD0 (ACK detection) STD0 (ST detection) SPD0 (SP detection) WTIM0 (8 or 9 clock wait) H ACKE0 (ACK control) H MSTS0 (communication status) L WREL0 (wait cancellation) <6> Note 3 INTIICA0 (interrupt) TRC0 (transmit/receive) L : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a master device. 2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. For releasing wait state during reception of a slave device, write "FFH" to IICA0 or set the WREL0 bit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 567 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 12-32 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (SDAA0 = 0 and SCLA0 = 1) is generated once the bus data line goes low (SDAA0 = 0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1). The master device is ready to communicate once the bus clock line goes low (SCLA0 = 0) after the hold time has elapsed. <2> The master device writes the address + W (transmission) to the IICA shift register 0 (IICA0) and transmits the slave address. <3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 = 0) and issues an interrupt (INTIICA0: address match)Note. <5> The master device writes the data to transmit to the IICA0 register and releases the wait status that it set by the master device. <6> If the slave device releases the wait status (WREL0 = 1), the master device starts transferring data to the slave device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0 interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0 interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remark <1> to <15> in Figure 12-32 following descriptions the entire procedure for communicating data using the I2C bus. Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 568 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4) (2) Address ~ data ~ data Master side IICA0 Note 1 Note 1 <5> <9> ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) H STT0 (ST trigger) SPT0 (SP trigger) WREL0 (wait cancellation) L L L INTIICA0 (interrupt) TRC0 (transmit/receive) H Bus line SCLA0 (bus) (clock line) <4> SDAA0 (bus) (data line) <8> W ACK D 17 D16 D 15 <3> D14 D 13 D12 D 11 D 27 D10 ACK <7> Slave side IICA0 ACKD0 (ACK detection) STD0 (ST detection) SPD0 (SP detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) L H H MSTS0 (communication status) L WREL0 (wait cancellation) <6> Note 2 <10> Note 2 INTIICA0 (interrupt) TRC0 (transmit/receive) L : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a master device. 2. For releasing wait state during reception of a slave device, write "FFH" to IICA0 or set the WREL0 bit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 569 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 12-32 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave device Note , that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 = 0) and issues an interrupt (INTIICA0: address match)Note. <5> The master device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait status that it set by the master device. <6> If the slave device releases the wait status (WREL0 = 1), the master device starts transferring data to the slave device. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICA0: end of transfer). <9> The master device writes the data to transmit to the IICA0 register and releases the wait status that it set by the master device. <10> The slave device reads the received data and releases the wait status (WREL0 = 1). The master device then starts transferring data to the slave device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0 interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0 interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remark <1> to <15> in Figure 12-32 following descriptions the entire procedure for communicating data using the I2C bus. Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 570 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4) (3) Data ~ data ~ Stop condition Master side Note 1 IICA0 <9> ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) STT0 (ST trigger) L SPT0 (SP trigger) WREL0 (wait cancellation) <14> L INTIICA0 (interrupt) TRC0 (transmit/receive) Stop condition Bus line SCLA0 (bus) (clock line) <8> SDAA0 (bus) (data line) D150 ACK <7> <12> D167 D166 D165 D164 D163 D162 D161 D160 ACK <11> Slave side Note 2 <15> IICA0 ACKD0 (ACK detection) STD0 (ST detection) L SPD0 (SP detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) L WREL0 (wait cancellation) <10> Note 3 <13> Note 3 INTIICA0 (interrupt) TRC0 (transmit/receive) L : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a master device. 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. For releasing wait state during reception of a slave device, write "FFH" to IICA0 or set the WREL0 bit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 571 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 12-32 are explained below. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICA0: end of transfer). <9> The master device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait status that it set by the master device. <10> The slave device reads the received data and releases the wait status (WREL0 = 1). The master device then starts transferring data to the slave device. <11> When data transfer is complete, the slave device (ACKE0 =1) sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <12> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICA0: end of transfer). <13> The slave device reads the received data and releases the wait status (WREL0 = 1). <14> By the master device setting a stop condition trigger (SPT0 = 1), the bus data line is cleared (SDAA0 = 0) and the bus clock line is set (SCLA0 = 1). After the stop condition setup time has elapsed, by setting the bus data line (SDAA0 = 1), the stop condition is then generated (i.e. SCLA0 =1 changes SDAA0 from 0 to 1). <15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt (INTIICA0: stop condition). Remark <1> to <15> in Figure 12-32 represent the entire procedure for communicating data using the I2C bus. Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32 (2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~ stop condition shows the processing from <7> to <15>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 572 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-32. Example of Master to Slave Communication (9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4) (4) Data ~ restart condition ~ address Master side IICA0 <iii> ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) H STT0 (ST trigger) <ii> SPT0 (SP trigger) L WREL0 (wait cancellation) L INTIICA0 (interrupt) TRC0 (transmit/receive) H Bus line Restart condition SCLA0 (bus) (clock line) <8> SDAA0 (bus) (data line) D13 D12 D11 D10 <7> ACK AD6 Note 1 Slave side AD5 AD4 AD3 AD2 AD1 Slave address IICA0 ACKD0 (ACK detection) STD0 (ST detection) SPD0 (SP detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) L H H MSTS0 (communication status) L WREL0 (wait cancellation) <i> Note 2 INTIICA0 (interrupt) TRC0 (transmit/receive) L : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the start condition after a restart condition has been issued is at least 4.7 s when specifying standard mode and at least 0.6 s when specifying fast mode. 2. For releasing wait state during reception of a slave device, write "FFH" to IICA0 or set the WREL0 bit. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 573 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The following describes the operations in Figure 12-32 (4) Data ~ restart condition ~ address. After the operations in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step <3>, the data transmission step. <7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICA0: end of transfer). <i> <ii> The slave device reads the received data and releases the wait status (WREL0 = 1). The start condition trigger is set again by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus clock line goes high (SCLA0 = 1) and the bus data line goes low (SDAA0 = 0) after the restart condition setup time has elapsed. When the start condition is subsequently detected, the master device is ready to communicate once the bus clock line goes low (SCLA0 = 0) after the hold time has elapsed. <iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICA0) enables the slave address to be transmitted. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 574 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3) (1) Start condition ~ address ~ data Master side IICA0 <2> ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) <5> H MSTS0 (communication status) STT0 (ST trigger) <1> SPT0 (SP trigger) L WREL0 (wait cancellation) <7> Note 1 INTIICA0 (interrupt) TRC0 (transmit/receive) Start condition Bus line SCLA0 (bus) (clock line) Note 2 SDAA0 (bus) (data line) <4> AD6 AD5 AD4 AD3 AD2 Slave address AD1 AD0 R <3> ACK D17 Slave side Note 3 IICA0 <6> ACKD0 (ACK detection) STD0 (ST detection) SPD0 (SP detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) L WREL0 (wait cancellation) L INTIICA0 (interrupt) TRC0 (transmit/receive) : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICA0 or set the WREL0 bit. 2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a slave device. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 575 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 12-33 are explained below. <1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1 changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start condition is subsequently detected, the master device enters the master device communication status (MSTS0 = 1). The master device is ready to communicate once the bus clock line goes low (SCLA0 = 0) after the hold time has elapsed. <2> The master device writes the address + R (reception) to the IICA shift register 0 (IICA0) and transmits the slave address. <3> In the slave device if the address received matches the address (SVA0 value) of a slave device Note, that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 = 0) and issues an interrupt (INTIICA0: address match) Note. <5> The timing at which the master device sets the wait status changes to the 8th clock (WTIM0 = 0). <6> The slave device writes the data to transmit to the IICA0 register and releases the wait status that it set by the slave device. <7> The master device releases the wait status (WREL0 = 1) and starts transferring data from the slave device to the master device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0 interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0 interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using the I2C bus. Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 576 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3) (2) Address ~ data ~ data Master side IICA0 ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) <5> H MSTS0 (communication status) H STT0 (ST trigger) L SPT0 (SP trigger) L WREL0 (wait cancellation) Note 1 Note 1 <7> INTIICA0 (interrupt) TRC0 (transmit/receive) <9> L Bus line SCLA0 (bus) (clock line) <4> SDAA0 (bus) (data line) <11> <8> R ACK <3> D17 D16 D15 D14 D13 D12 D11 D10 ACK D27 <10> Slave side IICA0 <6> ACKD0 (ACK detection) Note 2 <12> Note 2 STD0 (ST detection) SPD0 (SP detection) L WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) L WREL0 (wait cancellation) L INTIICA0 (interrupt) TRC0 (transmit/receive) H : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. For releasing wait state during reception of a master device, write "FFH" to IICA0 or set the WREL0 bit. 2. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a slave device. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 577 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 12-33 are explained below. <3> In the slave device if the address received matches the address (SVA0 value) of a slave device Note , that slave device sends an ACK by hardware to the master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock. <4> The master device issues an interrupt (INTIICA0: end of address transmission) at the falling edge of the 9th clock. The slave device whose address matched the transmitted slave address sets a wait status (SCLA0 = 0) and issues an interrupt (INTIICA0: address match)Note. <5> The master device changes the timing of the wait status to the 8th clock (WTIM0 = 0). <6> The slave device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait status that it set by the slave device. <7> The master device releases the wait status (WREL0 = 1) and starts transferring data from the slave device to the master device. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer). Because of ACKE0 = 1 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WREL0 = 1). <10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock. <11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICA0: end of transfer). <12> By the slave device writing the data to transmit to the IICA0 register, the wait status set by the slave device is released. The slave device then starts transferring data to the master device. Note If the transmitted address does not match the address of the slave device, the slave device does not return an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0 interrupt (address match) and does not set a wait status. The master device, however, issues the INTIICA0 interrupt (end of address transmission) regardless of whether it receives an ACK or NACK. Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using the I2C bus. Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 578 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA Figure 12-33. Example of Slave to Master Communication (8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3) (3) Data ~ data ~ stop condition Master side IICA0 ACKD0 (ACK detection) WTIM0 (8 or 9 clock wait) <14> ACKE0 (ACK control) MSTS0 (communication status) STT0 (ST trigger) L SPT0 (SP trigger) WREL0 (wait cancellation) <15> <9> INTIICA0 (interrupt) TRC0 (transmit/receive) <17> Note 1 Note 1 L Bus line Stop conditon SCLA0 (bus) (clock line) <8> SDAA0 (bus) (data line) D150 <11> ACK <13> D167 D166 D165 D164 D163 D162 D161 D160 <16> Note 2 NACK <10> Slave side <19> IICA0 <12> Note 3 ACKD0 (ACK detection) STD0 (ST detection) L SPD0 (SP detection) WTIM0 (8 or 9 clock wait) ACKE0 (ACK control) H H MSTS0 (communication status) WREL0 (wait cancellation) L <18> Notes 1, 4 INTIICA0 (interrupt) TRC0 (transmit/receive) Note 4 : Wait state by master device : Wait state by slave device : Wait state by master and slave devices Notes 1. To cancel a wait state, write "FFH" to IICA0 or set the WREL0 bit. 2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop condition after a stop condition has been issued is at least 4.0 s when specifying standard mode and at least 0.6 s when specifying fast mode. 3. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during slave transmission. 4. If a wait state during transmission by a slave device is canceled by setting the WREL0 bit, the TRC0 bit will be cleared. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 579 RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 12-33 are explained below. <8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an interrupt (INTIICA0: end of transfer). Because of ACKE0 = 0 in the master device, the master device then sends an ACK by hardware to the slave device. <9> The master device reads the received data and releases the wait status (WREL0 = 1). <10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock. <11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device issue an interrupt (INTIICA0: end of transfer). <12> By the slave device writing the data to transmit to the IICA register, the wait status set by the slave device is released. The slave device then starts transferring data to the master device. <13> The master device issues an interrupt (INTIICA0: end of transfer) at the falling edge of the 8th clock, and sets a wait status (SCLA0 = 0). Because ACK control (ACKE0 = 1) is performed, the bus data line is at the low level (SDAA0 = 0) at this stage. <14> The master device sets NACK as the response (ACKE0 = 0) and changes the timing at which it sets the wait status to the 9th clock (WTIM0 = 1). <15> If the master device releases the wait status (WREL0 = 1), the slave device detects the NACK (ACK = 0) at the rising edge of the 9th clock. <16> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and both the master device and slave device issue an interrupt (INTIICA0: end of transfer). <17> When the master device issues a stop condition (SPT0 = 1), the bus data line is cleared (SDAA0 = 0) and the master device releases the wait status. The master device then waits until the bus clock line is set (SCLA0 = 1). <18> The slave device acknowledges the NACK, halts transmission, and releases the wait status (WREL0 = 1) to end communication. Once the slave device releases the wait status, the bus clock line is set (SCLA0 = 1). <19> Once the master device recognizes that the bus clock line is set (SCLA0 = 1) and after the stop condition setup time has elapsed, the master device sets the bus data line (SDAA0 = 1) and issues a stop condition (i.e. SCLA0 =1 changes SDAA0 from 0 to 1). The slave device detects the generated stop condition and slave device issue an interrupt (INTIICA0: stop condition). Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using the I2C bus. Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33 (2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~ stop condition shows the processing from <8> to <19>. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 580 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.1 Functions of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator has the following functions. * 16 bits x 16 bits = 32 bits (Unsigned) * 16 bits x 16 bits = 32 bits (Signed) * 16 bits x 16 bits + 32 bits = 32 bits (Unsigned) * 16 bits x 16 bits + 32 bits = 32 bits (Signed) * 32 bits / 32 bits = 32 bits, 32-bits remainder (Unsigned) 13.2 Configuration of Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator consists of the following hardware. Table 13-1. Configuration of Multiplier and Divider/Multiply-Accumulator Item Registers Configuration Multiplication/division data register A (L) (MDAL) Multiplication/division data register A (H) (MDAH) Multiplication/division data register B (L) (MDBL) Multiplication/division data register B (H) (MDBH) Multiplication/division data register C (L) (MDCL) Multiplication/division data register C (H) (MDCH) Control register Multiplication/division control register (MDUC) Figure 13-1 shows a block diagram of the multiplier and divider/multiply-accumulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 581 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 13-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator Internal bus Multiplication result (product) or multiplication result (product) while in multiply-accumulator mode Multiplyaccumulation result (accumulated) MDCH MDBL Multiplication/division control register (MDUC) Division result (quotient) Multiplication/division data register C Multiplication/division data register B MDBH Division result (remainder) Multiplication/division data register A MDAH MDCL DIVMODE MACMODE MDSM MACOF MACSF MDAL DIVST Start INTMD Multiplicand Multiplier Dividend Divisor Clear Controller Controller Counter fPRS Multiplication/division block Accition block Controller Data flow during division Data flow during multiplication and multiply-accumulation (1) Multiplication/division data register A (MDAH, MDAL) The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator mode, and set the dividend data in the division mode. Furthermore, the operation result (quotient) is stored in the MDAH and MDAL registers in the division mode. The MDAH and MDAL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 13-2. Format of Multiplication/Division Data Register A (MDAH, MDAL) Address: FFFF0H, FFFF1H, FFFF2H, FFFF3H Symbol MDAH FFFF3H FFFF2H MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH MDAH 15 14 13 12 11 10 9 8 7 6 5 FFFF1H Symbol MDAL After reset: 0000H, 0000H R/W 4 3 2 1 0 FFFF0H MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL MDAL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. Do not rewrite the MDAH and MDAL registers values during division processing (when the multiplication/division control register (MDUC) value is 81H or C1H). The operation will be executed in this case, but the operation result will be an undefined value. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 582 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 2. The MDAH and MDAL registers values read during division processing (when the MDUC register value is 81H or C1H) will not be guaranteed. 3. The data is in the two's complement format in either the multiplication mode (signed) or multiply-accumulator mode (signed). The following table shows the functions of the MDAH and MDAL registers during operation execution. Table 13-2. Functions of MDAH and MDAL Registers During Operation Execution Operation Mode Setting Operation Result - Multiplication mode (unsigned) MDAH: Multiplier (unsigned) Multiply-accumulator mode (unsigned) MDAL: Multiplicand (unsigned) Multiplication mode (signed) MDAH: Multiplier (signed) Multiply-accumulator mode (signed) MDAL: Multiplicand (signed) Division mode (unsigned) MDAH: Dividend (higher 16 bits) - MDAH: Division result (quotient) Higher 16 bits MDAL: Dividend (lower 16 bits) MDAL: Division result (quotient) Lower 16 bits (2) Multiplication/division data register B (MDBL, MDBH) The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator mode, and set the divisor data in the division mode. The MDBH and MDBL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 13-3. Format of Multiplication/Division Data Register B (MDBH, MDBL) Address: FFFF4H, FFFF5H, FFFF6H, FFFF7H Symbol MDBH FFFF6H MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH MDBH 15 14 13 Symbol MDBL After reset: 0000H, 0000H R/W FFFF7H 12 11 10 9 8 7 6 5 FFFF5H 4 3 2 1 0 FFFF4H MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBL MDBHL MDBL MDBL MDBL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. Do not rewrite the MDBH and MDBL registers values during division processing (when the multiplication/division control register (MDUC) value is 81H or C1H) or multiply-accumulation processing. The operation result will be an undefined value. 2. Do not set the MDBH and MDBL registers to 0000H in the division mode. If they are set, the operation result will be an undefined value. 3. The data is in the two's complement format in either the multiplication mode (signed) or multiply-accumulator mode (signed). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 583 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The following table shows the functions of the MDBH and MDBL registers during operation execution. Table 13-3. Functions of MDBH and MDBL Registers During Operation Execution Operation Mode Multiplication mode (unsigned) Setting Operation Result - MDBH: Multiplication result (product) (unsigned) Higher 16 bits Multiply-accumulator mode (unsigned) MDBL: Multiplication result (product) (unsigned) Lower 16 bits - Multiplication mode (signed) MDBH: Multiplication result (product) (signed) Higher 16 bits Multiply-accumulator mode (signed) MDBL: Multiplication result (product) (signed) Lower 16 bits - MDBH: Divisor (higher 16 bits) Division mode (unsigned) MDBL: Divisor (lower 16 bits) (3) Multiplication/division data register C (MDCL, MDCH) The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or the remainder of the operation result while in the division mode. These registers are not used while in the multiplication mode. The MDCH and MDCL registers can be set by a 16-bit manipulation instruction. Reset signal generation clears these registers to 0000H. Figure 13-4. Format of Multiplication/Division Data Register C (MDCH, MDCL) Address: F00E0H, F00E1H, F00E2H, F00E3H Symbol MDCH F00E3H F00E2H MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH MDCH 15 14 13 12 11 10 9 8 7 6 5 F00E1H Symbol MDCL After reset: 0000H, 0000H R/W 4 3 2 1 0 F00E0H MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL MDCL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Cautions 1. The MDCH and MDCL registers values read during division processing (when the multiplication/division control register (MDUC) value is 81H or C1H) will not be guaranteed. 2. During multiply-accumulator processing, do not use software to rewrite the values of the MDCH and MDCL registers. If this is done, the operation result will be undefined. 3. The data is in the two's complement format in the multiply-accumulator mode (signed). Table 13-4. Functions of MDCH and MDCL Registers During Operation Execution Operation Mode Multiplication mode (unsigned R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting Operation Result - - 584 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR or signed) Multiply-accumulator mode (unsigned) MDCH: Initial accumulated value (unsigned) (higher 16 bits) MDCL: Initial accumulated value (unsigned) (lower 16 bits) Multiply-accumulator mode (signed) MDCH: Initial accumulated value (signed) (higher 16 bits) MDCL: Initial accumulated value (signed) (lower 16 bits) Division mode (unsigned) - MDCH: accumulated value (unsigned) (higher 16 bits) MDCL: accumulated value (unsigned) (lower 16 bits) MDCH: accumulated value (signed) (higher 16 bits) MDCL: accumulated value (signed) (lower 16 bits) MDCH: Remainder (higher 16 bits) MDCL: Remainder (lower 16 bits) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 585 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR The register configuration differs between when multiplication is executed and when division is executed, as follows. * Register configuration during multiplication <Multiplicand A> <Multiplier B> <Product> MDAL (bits 15 to 0) x MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] * Register configuration during multiply-accumulation < Multiplicand A > <Multiplier B> < accumulated value > < accumulated result > MDAL (bits 15 to 0) x MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] (The multiplication result is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).) * Register configuration during division <Dividend> <Divisor> [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] / [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] = <Quotient> <Remainder> [MDAH (bits 15 to 0), MDAL (bits 15 to 0)] [MDCH (bits 15 to 0), MDCL (bits 15 to 0)] R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 586 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.3 Register Controlling Multiplier and Divider/Multiply-Accumulator The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control register (MDUC). 13.3.1 Multiplication/division control register (MDUC) The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator. The MDUC register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 13-5. Format of Multiplication/Division Control Register (MDUC) Address: F00E8H After reset: 00H R/W Symbol <7> <6> 5 4 <3> <2> <1> <0> MDUC DIVMODE MACMODE 0 0 MDSM MACOF MACSF DIVST DIVMODE MACMODE MDSM 0 0 0 Multiplication mode (unsigned) (default) 0 0 1 Multiplication mode (signed) 0 1 0 Multiply-accumulator mode (unsigned) 0 1 1 Multiply-accumulator mode (signed) 1 0 0 Division mode (unsigned), generation of a division completion Operation mode selection interrupt (INTMD) 1 1 0 Division mode (unsigned), not generation of a division completion interrupt (INTMD) Other than above MACOF Setting prohibited Overflow flag of multiply-accumulation result (accumulated value) 0 No overflow 1 With over flow <Set condition> * For the multiply-accumulator mode (unsigned) The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh. * For the multiply-accumulator mode (signed) The bit is set when the result of adding a positive product to a positive accumulated value exceeds 7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated value exceeds 80000000h and is positive. MACSF Sign flag of multiply-accumulation result (accumulated value) 0 The accumulated value is positive. 1 The accumulated value is negative. Multiply-accumulator mode (unsigned): The bit is always 0. Multiply-accumulator mode (signed): The bit indicates the sign bit of the accumulated value. Note DIVST Division operation start/stop 0 Division processing complete 1 Starts division/division processing in progress R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 587 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the multiplication mode, operation is automatically started by setting the multiplier and multiplicand to multiplication/division data register A (MDAH, MDAL), respectively. Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is 1). If it is rewritten, the operation result will be an undefined value. 2. The DIVST bit cannot be cleared (0) by using software during division processing (while the DIVST bit is 1). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 588 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.4 Operations of Multiplier and Divider/Multiply-Accumulator 13.4.1 Multiplication (unsigned) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 00H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>. Multiplication is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) * During operation processing <4> Wait for at least one clock. The operation will end when one clock has been issued. * Operation end <5> Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). <6> Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps <5> and <6>.) * Next operation <7> The next time multiplication, multiply-accumulation, or division is performed, start with the initial settings of each step. Remark Steps <1> to <7> correspond to <1> to <7> in Figure 13-6. Figure 13-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) Operation clock MDUC 00H MDSM <1> L MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 0003H FFFFH 0002H FFFDH 0000H 0006H <2> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 FFFFH <4> <3> <5>, <6> FFFEH 0001H <7> 589 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.4.2 Multiplication (signed) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 08H. <2> Set the multiplicand to multiplication/division data register A (L) (MDAL). <3> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2> and <3>. Multiplication operation is automatically started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.) * During operation processing <4> Wait for at least one clock. The operation will end when one clock has been issued. * Operation end <5> Read the product (lower 16 bits) from multiplication/division data register B (L) (MDBL). <6> Read the product (higher 16 bits) from multiplication/division data register B (H) (MDBH). (There is no preference in the order of executing steps <5> and <6>.) * Next operation <7> To execute multiplication (signed) operation next, start from the "Initial setting" for multiplication (signed) operation. <8> The next time multiplication, multiply-accumulation (signed), or division is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiplication mode (signed). Remark Steps <1> to <7> correspond to <1> to <7> in Figure 13-7. Figure 13-7. Timing Diagram of Multiplication (Signed) Operation (-2 x 32767 = -65534) Operation clock <1> MDUC 00H 08H MDSM MDAL 0000H MDAH 0000H MDBL MDBH 0000H 0000H FFFEH 7FFFH FFFFH FFFFH 8001H FFFFH 0002H <2> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 FFFFH <4> <3> <5>, <6> 0000H 0001H <7> 590 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.4.3 Multiply-accumulation (unsigned) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 40H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (L) (MDCL). <3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH). <4> Set the multiplicand to multiplication/division data register A (L) (MDAL). <5> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>, <3>, and <4>. Multiplication operation is automatically started when the multiplier is set to the MDAH register, respectively.) * During operation processing <6> The multiplication finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) <7> After <6>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished (<5>).) * Operation end <8> Read the accumulated value (lower 16 bits) from the MDCL register. <9> Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps <8> and <9>.) (<10> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD signal is occurred.) * Next operation <11> The next time multiplication, multiply-accumulation, or division is performed, start with the initial settings of each step. Remark Steps <1> to <10> correspond to <1> to <10> in Figure 13-8. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 591 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 13-8. Timing Diagram of Multiply-Accumulation (Unsigned) Operation (2 x 3 + 3 = 9 32767 x 2 + 429401762 = 0 (over flow generated)) Operation clock <1> MDUC 00H 44H 40H MDSM L MDCH 0000H MDCL 0000H FFFFH 0003H 0009H 0000H 0002H 0000H <8>, <9> MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H 0002H 7FFFH 0003H 0002H 0000H 0006H 0000H FFFEH INTMD <10> MACOF MACSF L <2> <3> <4> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 <5> <6> <7> <2> <3> <4> <5> <6> <7> 592 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.4.4 Multiply-accumulation (signed) operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 48H. <2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH). (<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.) <4> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL). <5> Set the multiplicand to multiplication/division data register A (L) (MDAL). <6> Set the multiplier to multiplication/division data register A (H) (MDAH). (There is no preference in the order of executing steps <2>, <4>, and <5>. Multiplication operation is automatically started when the multiplier is set to the MDAH register, respectively.) * During operation processing <7> The multiplication operation finishes in one clock cycle. (The multiplication result is stored in multiplication/division data register B (L) (MDBL) and multiplication/division data register B (H) (MDBH).) <8> After <7>, the multiply-accumulation operation finishes in one additional clock cycle. (There is a wait of at least two clock cycles after specifying the initial settings is finished (<6>).) * Operation end <9> If the accumulated value stored in the MDCL and MDCH registers is positive, the MACSF bit is cleared to 0. <10> Read the accumulated value (lower 16 bits) from the MDCL register. <11> Read the accumulated value (higher 16 bits) from the MDCH register. (There is no preference in the order of executing steps <10> and <11>.) (<12> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD signal is occurred.) * Next operation <13> The next time multiplication, multiply-accumulation, or division is performed, start with the initial settings of each step. Caution The data is in the two's complement format in multiply-accumulation (signed) operation. Remark Steps <1> to <12> correspond to <1> to <12> in Figure 13-9. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 593 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR Figure 13-9. Timing Diagram of Multiply-Accumulation (signed) Operation (2 x 3 + (-4) = 2 32767 x (-1) + (-2147483647) = -2147450882 (overflow occurs.)) Operation clock <1> MDUC 00H 48H 4CH 4AH MDSM L <3> MDCH 0000H MDCL 0000H MDAL 0000H MDAH 0000H MDBH MDBL 0000H 0000H <3> <9> 0000H FFFFH FFFCH 8000H 0002H 7FFFH 8002H 0001H <10>, <11> 0002H 7FFFH 0003H FFFFH FFFFH 8001H 0000H 0006H <12> INTMD MACOF MACSF L <9> <3> <2> <4> R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 <5> <6> <7> <8> <3> <2> <4> <5> <6> <7> <8> 594 RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 13.4.5 Division operation * Initial setting <1> Set the multiplication/division control register (MDUC) to 80H. <2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH). <3> Set the dividend (lower 16 bits) to multiplication/division data register A (L) (MDAL). <4> Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH). <5> Set the divisor (lower 16 bits) to multiplication/division data register B (L) (MDBL). <6> Set bit 0 (DIVST) of the MDUC register to 1. (There is no preference in the order of executing steps <2> to <5>.) * During operation processing <7> The operation will end when one of the following processing is completed. * A wait of at least 16 clocks (The operation will end when 16 clocks have been issued.) * A check whether the DIVST bit has been cleared (The read values of the MDBL, MDBH, MDCL, and MDCH registers during operation processing are not guaranteed.) * Operation end <8> The DIVST bit is cleared and the operation ends. At this time, an interrupt request signal (INTMD) is generated if the operation was performed with MACMODE = 0. <9> Read the quotient (lower 16 bits) from the MDAL register. <10> Read the quotient (higher 16 bits) from the MDAH register. <11> Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL). <12> Read the remainder (higher 16 bits) from multiplication/division data register C (H) (MDCH). (There is no preference in the order of executing steps <9> to <12>.) * Next operation <13> The next time multiplication, multiply-accumulation, or division is performed, start with the initial settings of each step. Remark Steps <1> to <12> correspond to <1> to <12> in Figure 13-10. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 595 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 XXXXH XXXXH MDCH, MDCL 0000H 0000H 0000H 0000H 0000H 0023H 0H <1> <2> <3> <4> <5> <6> XXXXH XXXXH MDBH, MDBL INTMD XXXXH XXXXH Undefined 80H MDAH, MDAL Counter DIVST MDUC Operation clock 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH 0000H 0006H 0000H 0000H <7> <8> 0000H 0002H 0000H 0000H 0000H 0000H 0000H 0002H 0008H 0023H 008CH 0230H 08C0H 2300H 8C00H 3000H C000H 008CH 0230H 08C0H 2300H 8C00H 3000H C000H 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0001H 1H 81H Figure 13-10. Timing Diagram of Division Operation (Example: 35 / 6 = 5, Remainder 5) <9>, <10> 0000H 0005H 0000H 0005H 0H <8> 80H <11>, <12> RL78/G12 CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR 596 RL78/G12 CHAPTER 14 DMA CONTROLLER CHAPTER 14 DMA CONTROLLER <R> The R5F102 products of the RL78/G12 have an internal DMA (Direct Memory Access) controller. Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM without via CPU. As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer between the SFR and internal RAM, and therefore, a large capacity of data can be processed. In addition, real-time control using communication, timer, and A/D can also be realized. 14.1 Functions of DMA Controller <R> Number of DMA channels: 2 channels (R5F102 products) Transfer unit: 8 or 16 bits Maximum transfer unit: 1024 times Transfer type: 2-cycle transfer (One transfer is processed in 2 clocks and the CPU stops during that processing.) Transfer mode: Single-transfer mode Transfer request: Selectable from the following peripheral hardware interrupts * A/D converter * Serial interface (CSI00, CSI01, CSI11, CSI20, UART0 to UART2) * Timer (channel 0, 1, 2, 3) Transfer target: Between SFR and internal RAM Here are examples of functions using DMA. * Successive transfer of serial interface * Batch transfer of analog data * Capturing A/D conversion result at fixed interval * Capturing port value at fixed interval R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 597 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.2 Configuration of DMA Controller The DMA controller includes the following hardware. Table 14-1. Configuration of DMA Controller Item Configuration * DMA SFR address registers 0, 1 (DSA0, DSA1) Address registers * DMA RAM address registers 0, 1 (DRA0, DRA1) Count register * DMA byte count registers 0, 1 (DBC0, DBC1) Control registers * DMA mode control registers 0, 1 (DMC0, DMC1) * DMA operation control register 0, 1 (DRC0, DRC1) (1) DMA SFR address register n (DSAn) This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA channel n. Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH. This register is not automatically incremented but fixed to a specific value. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 00H. Figure 14-1. Format of DMA SFR Address Register n (DSAn) Address: FFFB0H (DSA0), FFFB1H (DSA1) After reset: 00H 7 6 5 4 3 2 1 R/W 0 DSAn Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 598 RL78/G12 CHAPTER 14 DMA CONTROLLER (2) DMA RAM address register n (DRAn) This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA channel n. Addresses of the internal RAM area other than the general-purpose registers (see table 14-2) can be set to this register. Set the lower 16 bits of the RAM address. This register is automatically incremented when DMA transfer has been started. It is incremented by +1 in the 8bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this DRAn register. When the data of the last address has been transferred, the DRAn register stops with the value of the last address +1 in the 8-bit transfer mode, and the last address +2 in the 16-bit transfer mode. In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address. The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 0000H. Figure 14-2. Format of DMA RAM Address Register n (DRAn) Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) , After reset: 0000H DRA0H: FFFB3H DRA1H: FFFB5H 15 14 13 12 11 10 R/W DRA0L: FFFB2H DRA1L: FFFB4H 9 8 7 6 5 4 3 2 1 0 DRAn Remark n: DMA channel number (n = 0, 1) Table 14-2 Internal RAM Area other than the General-purpose Registers Part Number Internal RAM Area other than the General-purpose Registers R5F10x66 256 x 8 bits (FFE00H to FFEDFH) R5F10x67, R5F10x77, R5F10xA7 512 x 8 bits (FFD00H to FFEDFH) R5F10x68, R5F10x78, R5F10xA8 768 x 8 bits (FFC00H to FFEDFH) R5F10x69, R5F10x79, R5F10xA9 1024 x 8 bits (FFB00H to FFEDFH) R5F10x6A, R5F10x7A 1536 x 8 bits (FF900H to FFEDFH) R5F10xAA 2048 x 8 bits (FF700H to FFEDFH) (x = 2, 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 599 RL78/G12 CHAPTER 14 DMA CONTROLLER (3) DMA byte count register n (DBCn) This is a 10-bit register that is used to set the number of times DMA channel n executes transfer. Be sure to set the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times). Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn register during DMA transfer, the remaining number of times of transfer can be learned. The DBCn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA transfer. Reset signal generation clears this register to 0000H. Figure 14-3. Format of DMA Byte Count Register n (DBCn) Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1) After reset: 0000H DBC0H:FFFB7H DBC1H:FFFB9H DBCn 15 14 13 12 11 10 0 0 0 0 0 0 R/W DBC0L:FFFB6H DBC1L:FFFB8H 9 DBCn[9:0] Number of Times of Transfer (When DBCn is Written) 8 7 6 5 4 3 2 1 0 Remaining Number of Times of Transfer (When DBCn is Read) 000H 1024 Completion of transfer or waiting for 1024 times of DMA transfer 001H 1 Waiting for remaining one time of DMA transfer 002H 2 Waiting for remaining two times of DMA transfer 003H 3 Waiting for remaining three times of DMA transfer * * * * * * * * * 3FEH 1022 Waiting for remaining 1022 times of DMA transfer 3FFH 1023 Waiting for remaining 1023 times of DMA transfer Cautions 1. Be sure to clear bits 15 to 10 to 0. 2. If the general-purpose register is specified or the internal RAM space is exceeded as a result of continuous transfer, the general-purpose register or SFR space are written or read, resulting in loss of data in these spaces. Be sure to set the number of times of transfer that is within the internal RAM space. Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 600 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.3 Registers Controlling DMA Controller DMA controller is controlled by the following registers. * DMA mode control register n (DMCn) * DMA operation control register n (DRCn) Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 601 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.3.1 DMA mode control register n (DMCn) The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts DMA. Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited during operation (when DSTn = 1). The DMCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-4. Format of DMA Mode Control Register n (DMCn) (1/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 STGn Note 1 DMA transfer start software trigger 0 No trigger operation 1 DMA transfer is started when DMA operation is enabled (DENn = 1). DMA transfer is performed once by writing 1 to the STGn bit when DMA operation is enabled (DENn = 1). When this bit is read, 0 is always read. DRSn Selection of DMA transfer direction 0 SFR to internal RAM 1 Internal RAM to SFR DSn Specification of transfer data size for DMA transfer 0 8 bits 1 16 bits DWAITn Note Pending of DMA transfer 2 0 Executes DMA transfer upon DMA start request (not held pending). 1 Holds DMA start request pending if any. DMA transfer that has been held pending can be started by clearing the value of the DWAITn bit to 0. It takes 2 clocks to actually hold DMA transfer pending when the value of the DWAITn bit is set to 1. Notes 1. The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values. 2. When DMA transfer is held pending while using two or more DMA channels, be sure to hold the DMA transfer pending for all channels (by setting the DWAIT0, DWAIT1, DWAIT2, and DWAIT3 bits to 1). Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 602 RL78/G12 CHAPTER 14 DMA CONTROLLER Figure 14-4. Format of DMA Mode Control Register n (DMCn) (2/2) Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W Symbol <7> <6> <5> <4> 3 2 1 0 DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0 Note IFCn3 IFCn2 IFCn1 IFCn0 Selection of DMA start source Trigger signal - Trigger contents Disables DMA transfer by interrupt. 0 0 0 0 0 0 0 1 INTAD A/D conversion end interrupt 0 0 1 0 INTTM00 End of timer channel 0 count or capture (Only software trigger is enabled.) end interrupt 0 0 1 1 INTTM01 End of timer channel 1 count or capture end interrupt 0 1 0 0 INTTM02 End of timer channel 2 count or capture end interrupt 0 1 0 1 INTTM03 End of timer channel 3 count or capture end interrupt 0 1 1 0 INTST0/INTCSI00 UART0 transmission transfer end or buffer empty interrupt/CSI00 transfer end or buffer empty interrupt 0 1 1 1 INTSR0/INTCSI01 UART0 reception transfer end interrupt/CSI01 transfer end or buffer empty interrupt 1 0 0 0 INTST1 1 0 0 1 INTSR1/INTCSI11 UART1 transmission transfer end or buffer empty interrupt UART1 reception transfer end interrupt/CSI11 transfer end or buffer empty interrupt 1 0 1 0 INTST2/INTCSI20 UART2 transmission transfer end or buffer empty interrupt/CSI20 transfer end or buffer empty interrupt 1 0 1 Other than above 1 INTSR2 UART2 reception transfer end interrupt Setting prohibited Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values. Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 603 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.3.2 DMA operation control register n (DRCn) The DRCn register is a register that is used to enable or disable transfer of DMA channel n. Rewriting bit 7 (DENn) of this register is prohibited during operation (when DSTn = 1). The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 14-5. Format of DMA Operation Control Register n (DRCn) Address: FFFBCH (DRC0), FFFBDH (DRC1) After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> DRCn DENn 0 0 0 0 0 0 DSTn DENn DMA operation enable flag 0 Disables operation of DMA channel n (stops operating cock of DMA). 1 Enables operation of DMA channel n. DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1). DSTn DMA transfer mode flag 0 DMA transfer of DMA channel n is completed. 1 DMA transfer of DMA channel n is not completed (still under execution). DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1). When a software trigger (STGn) or the start source trigger set by the IFCn3 to IFCn0 bits is input, DMA transfer is started. When DMA transfer is completed after that, this bit is automatically cleared to 0. Write 0 to this bit to forcibly terminate DMA transfer under execution. Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set the DSTn bit to 0 and then the DENn bit to 0 (for details, refer to 14.5.5 Forced termination by software). Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 604 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.4 Operation of DMA Controller 14.4.1 Operation procedure <1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction. <2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to DMA SFR address register n (DSAn), DMA RAM address register n (DRAn), DMA byte count register n (DBCn), and DMA mode control register n (DMCn). <3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation instruction. <4> When a software trigger (STGn) or a start source trigger specified by the IFCn3 to IFCn0 bits is input, a DMA transfer is started. <5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is automatically terminated by occurrence of an interrupt (INTDMAn). <6> Stop the operation of the DMA controller by clearing the DENn bit to 0 when the DMA controller is not used. Figure 14-6. Operation Procedure DENn = 1 Set by software program Setting DSAn, DRAn, DBCn, and DMCn DSTn = 1 DMA trigger = 1? No Yes Transmitting DMA request Receiving DMA acknowledge Operation by DMA DMA transfer controller (hardware) DRAn = DRAn + 1 (or + 2) DBCn = DBCn - 1 DBCn = 0000H ? No Yes DSTn = 0 INTDMAn = 1 DENn = 0 Remark Set by software program n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 605 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.4.2 Transfer mode The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode control register n (DMCn). DRSn DSn DMA Transfer Mode 0 0 Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1) 0 1 Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2) 1 0 Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address) 1 1 Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address) By using these transfer modes, up to 1024 bytes of data can be consecutively transferred by using the serial interface, data resulting from A/D conversion can be consecutively transferred, and port data can be scanned at fixed time intervals by using a timer. 14.4.3 Termination of DMA transfer When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request (INTDMAn) is generated and transfer is terminated. When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, DMA byte count register n (DBCn) and DMA RAM address register n (DRAn) hold the value when transfer is terminated. The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated. Remark n: DMA channel number (n = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 606 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.5 Example of Setting of DMA Controller 14.5.1 CSI consecutive transmission A flowchart showing an example of setting for CSI consecutive transmission is shown below. * Consecutive transmission of CSI10 (256 bytes) * DMA channel 0 is used for DMA transfer. * DMA start source: INTCSI10 (software trigger (STG0) only for the first start source) * Interrupt of CSI10 is specified by IFC03 to IFC00 = 1000B. * Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the data register (SIO10) of CSI. Remark IFC03 to IFC00: Bits 3 to 0 of DMA mode control registers 0 (DMC0) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 607 RL78/G12 CHAPTER 14 DMA CONTROLLER Figure 14-7. Example of Setting for CSI Consecutive Transmission Start DEN0 = 1 DSA0 = 44H DRA0 = FB00H DBC0 = 0100H DMC0 = 48H Setting for CSI transfer DST0 = 1 DMA is started. STG0 = 1 INTCSI10 occurs. User program processing DMA0 transfer CSI transmission Occurrence of INTDMA0 DST0 = 0Note DEN0 = 0 RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 14.5.5 Forced termination by software). The first trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software trigger. CSI transmission of the second time and onward is automatically executed. A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 608 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.5.2 Consecutive capturing of A/D conversion results A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below. * Consecutive capturing of A/D conversion results. * DMA channel 1 is used for DMA transfer. * DMA start source: INTAD * Interrupt of A/D is specified by IFC13 to IFC10 = 0001B. * Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of FFCE0H to FFEDFH of RAM. Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 609 RL78/G12 CHAPTER 14 DMA CONTROLLER Figure 14-8. Example of Setting of Consecutively Capturing A/D Conversion Results Start DEN1 = 1 DSA1 = 1EH DRA1 = FCE0H DBC1 = 0100H DMC1 = 21H DST1 = 1 Starting A/D conversion INTAD occurs. User program processing DMA1 transfer INTDMA1 occurs. DST1 = 0Note DEN1 = 0 RETI Hardware operation End Note The DST1 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA1 (INTDMA1), set the DST1 bit to 0 and then the DEN1 bit to 0 (for details, refer to 14.5.5 Forced termination by software). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 610 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.5.3 UART consecutive reception + ACK transmission A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below. * Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception. * DMA channel 0 is used for DMA transfer. * DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.) * Transfers FFF12H of UART receive data register 0 (RXD0) to 64 bytes of FFE00H to FFE3FH of RAM. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 611 RL78/G12 CHAPTER 14 DMA CONTROLLER Figure 14-9. Example of Setting for UART Consecutive Reception + ACK Transmission Start INTSR0 interrupt routine DEN0 = 1 DSA0 = 12H STG0 = 1 DRA0 = FE00H DBC0 = 0040H DMC0 = 00H DMA0 transfer P10 = 1 Setting for UART reception P10 = 0 DST0 = 1 INTSR0 occurs. RETI User program processing INTDMA0 occurs. DST0 = 0 DEN0 = 0Note RETI Hardware operation End Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed. Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for occurrence of the interrupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details, refer to 14.5.5 Forced termination by software). Remark This is an example where a software trigger is used as a DMA start source. If ACK is not transmitted and if only data is consecutively received from UART, the UART reception end interrupt (INTSR0) can be used to start DMA for data reception. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 612 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.5.4 Holding DMA transfer pending by DWAITn bit When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred while DMA transfer was held pending is executed after the pending status is canceled. However, because only one transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the pending status, only one DMA transfer is executed after the pending status is canceled. To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the DWAITn bit to 1. After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending. Figure 14-10. Example of Setting for Holding DMA Transfer Pending by DWAITn Bit Starting DMA transfer Main program DWAITn = 1 Wait for 2 clocks P10 = 1 Wait for 9 clocks P10 = 0 DWAITn = 0 Caution When DMA transfer is held pending while using two or more DMA channels, be sure to held the DMA transfer pending for all channels (by setting DWAIT0, DWAIT1, DWAIT2, and DWAIT3 to 1). If the DMA transfer of one channel is executed while that of the other channel is held pending, DMA transfer might not be held pending for the latter channel. Remarks 1. n: DMA channel number (n = 0, 1) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 613 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.5.5 Forced termination by software After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn, therefore, perform either of the following processes. <When using one DMA channel> * Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8bit manipulation instruction). * Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after. <When using two DMA channels> * To forcibly terminate DMA transfer by software when using two DMA channels (by setting DSTn to 0), clear the DSTn bit to 0 after the DMA transfer is held pending by setting the DWAITn bits of both using channels to 1. Next, clear the DWAITn bits of both using channels to 0 to cancel the pending status, and then clear the DENn bit to 0. Figure 14-11. Forced Termination of DMA Transfer (1/2) Example 1 Example 2 DSTn = 0 DSTn = 0 No 2 clock wait DSTn = 0 ? Yes DENn = 0 DENn = 0 Remarks 1. n: DMA channel number (n = 0, 1) 2. 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 614 RL78/G12 CHAPTER 14 DMA CONTROLLER Figure 14-11. Forced Termination of DMA Transfer (2/2) Example 3 * Procedure for forcibly terminating the DMA transfer for one channel if both channels are used * Procedure for forcibly terminating the DMA transfer for both channels if both channels are used DWAIT0 = 1 DWAIT1 = 1 DWAIT0 = 1 DWAIT1 = 1 DSTn = 0 DST0 = 0 DST1 = 0 DWAIT0 = 0 DWAIT1 = 0 DWAIT0 = 0 DWAIT1 = 0 DENn = 0 DEN0 = 0 DEN1 = 0 Remarks 1. n: DMA channel number (n = 0, 1) 2. 1 clock: 1/fCLK (fCLK: CPU clock) In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In addition, the system does not have to wait two clock cycles after clearing the DSTn bit to 0, because more than two clock cycles elapse from when the DSTn bit is cleared to 0 to when the DENn bit is cleared to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 615 RL78/G12 CHAPTER 14 DMA CONTROLLER 14.6 Cautions on Using DMA Controller (1) Priority of DMA During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending DMA transfer is started after the ongoing DMA transfer is completed. If two or more DMA requests are generated at the same time, however, their priority are DMA channel 0 > DMA channel 1 > DMA channel 2 > DMA channel 3. If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence, and then interrupt servicing is executed. (2) DMA response time The response time of DMA transfer is as follows. Table 14-2. Response Time of DMA Transfer Minimum Time Response time 3 clocks Maximum Time 10 clocks Note Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles. Cautions 1. The above response time does not include the two clock cycles required for a DMA transfer. 2. When executing a DMA pending instruction (see 14.6 (4)), the maximum response time is extended by the execution time of that instruction to be held pending. 3. Do not specify successive transfer triggers for a channel within a period equal to the maximum response time plus one clock cycle, because they might be ignored. Remark 1 clock: 1/fCLK (fCLK: CPU clock) (3) Operation in standby mode The DMA controller operates as follows in the standby mode. Table 14-3. DMA Operation in Standby Mode Status DMA Operation HALT mode Normal operation STOP mode Stops operation. If DMA transfer and STOP instruction execution contend, DMA transfer may be damaged. Therefore, stop DMA before executing the STOP instruction. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 616 RL78/G12 CHAPTER 14 DMA CONTROLLER (4) DMA pending forwarding Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions. * CALL !addr16 * CALL $!addr20 * CALL !!addr20 * CALL rp * CALLT [addr5] * BRK * Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H, MK2L, MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H, PR13L, and PSW each. * Instruction for accessing the data flash memory (5) Operation if address in general-purpose register area or other than those of internal RAM area is specified The address indicated by DMA RAM address register n (DRAn) is incremented during DMA transfer. If the address is incremented to an address in the general-purpose register area or exceeds the area of the internal RAM, the following operation is performed. In mode of transfer from SFR to RAM The data of that address is lost. In mode of transfer from RAM to SFR Undefined data is transferred to SFR. In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the address is within the internal RAM area other than the general-purpose register area. FFF00H FFEFFH FFEE0H FFEDFH General-purpose registers Internal RAM DMA transfer enabled area (6) Operation if instructions for accessing the data flash area * Because DMA transfer is suspended to access to the data flash area, be sure to add the DMA pending instruction. If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait will be inserted to the next instruction. Instruction 1 DMA transfer Instruction 2 The wait of three clock cycles occurs. MOV A, ! DataFlash area R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 617 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS CHAPTER 15 INTERRUPT FUNCTIONS The interrupt function switches the program execution to other processing. When the branch processing is finished, the program returns to the interrupted processing. The number of interrupt sources differs, depending on the product. 20-, 24-pin products R5F102 <R> Maskable interrupts External 5 Internal 18 30-pin products R5F103 R5F102 R5F103 6 16 26 19 15.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated. If two or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed according to the priority of vectored interrupt servicing. For the priority order, see Table 15-1 and Table 15-2. A standby release signal is generated and STOP, HALT, and SNOOZE modes are released. External interrupt requests and internal interrupt requests are provided as maskable interrupts. (2) Software interrupt This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are disabled. The software interrupt does not undergo interrupt priority control. 15.2 Interrupt Sources and Configuration Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to seven reset sources (see Table 15-1 or 15-2). The vector codes that store the program start address when branching due to the generation of a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 618 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Note 3 (75%+1/2fIL of overflow Internal 0004H (A) R5F103 Watchdog timer interval Basic Configuration Type Trigger R5F102 Maskable INTWDTI Vector Table Address Interrupt Source Name 0 Internal/External Note 1 Default Priority Interrupt Type <R> Note 2 Table 15-1. Interrupt Source List (20-, 24-pin products) (1/2) time) 1 Note 4 INTLVI Voltage detection 0006H 2 INTP0 Pin input edge detection 3 INTP1 000AH 4 INTP2 000CH External 5 INTP3 6 INTDMA0 End of DMA0 transfer 7 INTDMA0 End of DMA1 transfer 8 INTST0/ UART0 transmission transfer end or buffer empty INTCSI00/ interrupt/CSI00 transfer end or buffer empty interrupt/IIC00 transfer end INTIIC00 9 0008H (B) - 0012H - 0014H 000EH Internal INTSR0/ UART0 reception transfer end/CSI01 transfer end or INTCSI01/ buffer empty interrupt/IIC01 transfer end 0010H (A) - 0016H - - INTIIC01 10 INTSRE0 11 INTTM01H UART0 reception communication error occurrence 0018H End of timer channel 1 count or capture (at higher 8-bit 001AH 001CH timer operation) 12 INTTM03H End of timer channel 3 count or capture (at higher 8-bit timer operation) 13 INTIICA0 End of IICA0 communication 001EH 14 INTTM00 End of timer channel 0 count or capture (16 bit/at lower 8-bit timer operation) 0020H 15 INTTM01 End of timer channel 1 count or capture (16 bit/at lower 8-bit timer operation) 0022H 16 INTTM02 End of timer channel 2 count or capture (16 bit/at lower 0024H 0026H 8-bit timer operation) 17 INTTM03 End of timer channel 3 count or capture (16 bit/at lower 8-bit timer operation) 18 INTAD End of A/D conversion 0028H 19 INTIT Interval signal detection from 12-bit Interval timer 002AH 20 INTKR Key return signal detection External 002CH (C) 21 INTMD End of division operation / overflow occurrence Internal 002EH (A) 22 Notes 1. INTFL End of sequencer interrupt Note 5 0030H The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. 0 indicates the highest priority and 22 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1. 3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1. 4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0. 5. Only for using self programming library R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 619 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS R5F102 R5F103 Basic Configuration Type Vector Table Address Internal/External Note 1 Default Priority Software - BRK Execution of BRK instruction - 007EH (D) Reset Interrupt Type <R> Note 2 Table 15-1. Interrupt Source List (20-, 24-pin products) (2/2) - RESET RESET pin input - 0000H - POR Power-on-reset Interrupt Source Name Notes 1. Trigger Note 3 LVD Voltage detection WDT Overflow of watchdog timer Note 4 TRAP Execution of illegal instruction IAW Illegal memory access RPE RAM parity error The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. Zero indicates the highest priority and 22 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1. 3. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 1. 4. When the instruction code in FFH is executed. No reset is issued even if an illegal instruction is executed during emulation with the in-circuit emulator or on-chip debug emulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 620 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS (75% + 1/2fIL of Internal 0004H R5F103 Note 3 R5F102 Watchdog timer interval Basic Configuration Note 2 Type INTWDTI Address 0 Trigger Vector Table Name Internal/External Interrupt Source Default Priority Maskable Interrupt Type <R> Note 1 Table 15-2. Interrupt Source List (30-pin products) (1/2) (A) overflow time) Note 4 1 INTLVI Voltage detection 2 INTP0 Pin input edge detection 3 INTP1 000AH 4 INTP2 000CH 5 INTP3 000EH 6 INTP4 0010H 7 INTP5 0012H 8 INTST2/ UART2 transmission transfer end, buffer empty - INTCSI20/ interrupt/CSI20 transfer end or buffer empty INTIIC20 0006H External Internal 0008H 0014H (B) (A) interrupt/IIC20 transfer end UART2 reception transfer end 0016H - INTSRE2 UART2 reception communication error occurrence 0018H - INTDMA0 DMA0 transfer end 001AH - 12 INTDMA1 DMA1 transfer end 001CH - 13 INTST0/ UART0 transmission transfer end, buffer empty 001EH INTCSI00/ interrupt/CSI00 transfer end or buffer empty 9 INTSR2 10 11 INTIIC00 interrupt/IIC00 transfer end - 14 INTSR0 UART0 reception transfer end 0020H 15 INTSRE0 UART0 reception communication error occurrence 0022H INTTM01H End of timer channel 1 count or capture (at higher 8- bit timer operation) 16 INTST1 UART1 transmission transfer end 0024H - 17 INTSR1/ UART1 reception transfer end/CSI11 transfer end or 0026H - INTCSI11/ buffer empty interrupt/IIC11 transfer end 0028H - INTIIC11 18 INTSRE1 UART1 reception communication error occurrence INTTM03H End of timer channel 3 count or capture (at higher 8bit timer operation) 19 Notes 1. INTIICA0 IICA0 communication end 002AH The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. 0 indicates the highest priority and 31 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1 respectively. 3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1. 4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 621 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS R5F103 Internal R5F102 End of timer channel 0 count or capture (16 bit / at Basic Configuration Note 2 Type INTTM00 (A) 002EH 0030H 0032H Address 20 Trigger Vector Table Name Internal/External Interrupt Source Default Priority Maskable Interrupt Type <R> Note 1 Table 15-2. Interrupt Source List (30-pin products) (2/2) 002CH lower 8-bit timer operation) 21 INTTM01 End of timer channel 1 count or capture (16 bit / at lower 8-bit timer operation) 22 INTTM02 End of timer channel 2 count or capture (16 bit / at lower 8-bit timer operation) 23 INTTM03 End of timer channel 3 count or capture (16 bit / at lower 8-bit timer operation) 24 INTAD End of A/D conversion 0034H 25 INTIT Interval signal detection from 12-bit interval timer 0038H 26 INTTM04 End of timer channel 4 count or capture (16 bit / at 0042H 0044H 0046H 0048H 005EH 0062H lower 8-bit timer operation) 27 INTTM05 End of timer channel 5 count or capture (16 bit / at lower 8-bit timer operation) 28 INTTM06 End of timer channel 6 count or capture (16 bit / at lower 8-bit timer operation) 29 INTTM07 End of timer channel 7 count or capture (16 bit / at lower 8-bit timer operation) End of division operation / overflow occurrence Note 3 31 INTFL End of sequencer interrupt Software INTMD - BRK Execution of BRK instruction - 007EH (D) Reset 30 - RESET RESET pin input - 0000H - POR Power-on-reset Notes 1. Note 4 LVD Voltage detection WDT Overflow of watchdog timer Note 5 TRAP Execution of illegal instruction IAW Illegal memory access RPE RAM parity error The default priority determines the sequence of interrupts if two or more maskable interrupts occur simultaneously. 0 indicates the highest priority and 31 indicates the lowest priority. 2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1 respectively. 3. Only for using self programming library. 4. When bit 7 (LVIMD) of the voltage detection level register (LVIS) is cleared to 0. 5. When the instruction code in FFH is executed. No reset is issued even if an illegal instruction is executed during emulation with the in-circuit emulator or on-chip debug emulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 622 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (1/2) (a) Internal maskable interrupt Internal bus MK Interrupt request IE PR1 PR0 ISP1 ISP0 Vector table address generator Priority controller IF Standby release signal (b) External maskable interrupt (INTPn) Internal bus External interrupt edge enable register (EGP, EGN) INTPn pin input Edge detector MK IF IE PR1 PR0 Priority controller ISP1 ISP0 Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1 MK: Interrupt mask flag PR0: Priority specification flag 0 PR1: Priority specification flag 1 Remark 20, 24-pin product : n = 0 to 3 30-pin product : n = 0 to 5 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 623 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-1. Basic Configuration of Interrupt Function (2/2) (c) External maskable interrupt (INTKR) Internal bus Key return mode register (KRM0, KRM1) MK IE PR1 PR0 ISP1 ISP0 KRMn KRn pin input Key interrupt detector Priority controller IF Vector table address generator Standby release signal IF: Interrupt request flag IE: Interrupt enable flag ISP0: In-service priority flag 0 ISP1: In-service priority flag 1 MK: Interrupt mask flag PR0: Priority specification flag 0 PR1: Priority specification flag 1 Remark 24-pin product : n = 0 to 9 20-pin product : n = 0 to 5 (d) Software interrupt Internal bus Interrupt request R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Vector table address generator 624 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions. * Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L , IF2H) * Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H) * Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) * External interrupt rising edge enable register (EGP0) * External interrupt falling edge enable register (EGN0) * Program status word (PSW) Tables 15-3 and 15-4 show a list of interrupt request flags, interrupt mask flags, and priority specification flags corresponding to interrupt request sources. Table 15-3. Flags Corresponding to Interrupt Request Sources (20-, 24-pin products) (1/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register R5F103 Register R5F102 <R> WDTIPR0, WDTIPR1 PR00L, LVIMK LVIPR0, LVIPR1 PR10L PIF0 PMK0 PPR00, PPR10 PIF1 PMK1 PPR01, PPR11 INTP2 PIF2 PMK2 PPR02, PPR12 INTP3 PIF3 PMK3 PPR03, PPR13 INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10 - INTDMA1 DMAIF1 INTWDTI WDTIIF INTLVI LVIIF INTP0 INTP1 INTST0 Note 1 INTCSI00 Note 1 STIF0 IF0L DMAMK1 Note 1 CSIIF00 IF0H Note STMK0 CSIMK00 IICMK00 Note 1 IICIF00 - PR00H, PR10H - - - DMAPR01, DMAPR11 Note 1 1 INTIIC00 MK0L WDTIMK MK0H Note 1 STPR00, STPR10 Note 1 CSIPR000, CSIPR100 Note 1 IICPR000, IICPR100 Note 1 Note 1 Note 1 INTSR0 Note 2 INTCSI01 Note 2 SRIF0 Note 2 CSIIF01 SRMK0 Note Note 2 CSIMK01 2 IICMK01 INTIIC01 Note 2 IICIF01 SRPR00, SRPR10 Note 2 Note 2 CSIPR001, CSIPR101 Note 2 IICPR001, IICPR101 Note 2 Note 2 Note 2 INTSRE0 SREIF0 SREMK0 SREPR00, SREPR10 INTTM01H TMIF01H TMMK01H TMPR001H, TMPR101H INTTM03H TMIF03H TMMK03H TMPR003H, TMPR103H INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10 INTTM00 TMIF00 TMMK00 TMPR000, TMPR100 INTTM01 TMIF01 TMMK01 TMPR001, TMPR101 INTTM02 TMIF02 INTTM03 TMIF03 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 IF1L TMMK02 TMMK03 MK1L TMPR002, TMPR102 PR01L, TMPR003, TMPR103 PR11L 625 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-3. Flags Corresponding to Interrupt Request Sources (20-, 24-pin products) (2/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source Register Register R5F103 Register R5F102 <R> ADPR0, ADPR1 PR01L, TMKAMK TMKAPR0, TMKAPR1 PR11L KRIF KRMK KRPR0, KRPR1 INTMD MDIF MDMK MDPR0, MDPR1 INTFL FLIF FLMK FLPR0, FLPR1 INTAD ADIF INTIT TMKAIF INTKR IF1L ADMK MK1L Notes 1. If interrupt source INTST0, INTCSI00, or INTIIC00 occurs, bit 5 of the IF0H register is set to 1. Bit 5 of the MK0H, PR00H, and PR10H registers corresponds these three interrupt sources. 2. If interrupt source INTSR0, INTCSI01, or INTIIC01 occurs, bit 6 of the IF0H register is set to 1. Bit 6 of the MK0H, PR00H, and PR10H registers corresponds these three interrupt sources. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 626 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-4. Flags Corresponding to Interrupt Request Sources (30-pin products) (1/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source INTWDTI IF0L WDTIIF Register MK0L WDTIMK Register R5F103 Register R5F102 <R> WDTIPR0, WDTIPR1 PR00L, PR10L INTLVI LVIIF LVIMK LVIPR0, LVIPR1 INTP0 PIF0 PMK0 PPR00, PPR10 INTP1 PIF1 PMK1 PPR01, PPR11 INTP2 PIF2 PMK2 PPR02, PPR12 INTP3 PIF3 PMK3 PPR03, PPR13 INTP4 PIF4 PMK4 PPR04, PPR14 - INTP5 INTST2 PIF5 Note1 INTCSI20 Note1 PMK5 Note1 STIF2 IF0H Note1 PPR05, PPR15 Note1 STMK2 MK0H Note1 STPR02, STPR12 Note1 PR00H, Note1 CSIMK20 IICIF20Note1 IICMK20Note1 IICPR020, IICPR120Note1 INTSR2 SRIF2 SRMK2 SRPR02, SRPR12 - INTSRE2 SREIF2 SREMK2 SREPR02, SREPR12 - INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10 - INTDMA1 DMAIF1 DMAMK1 DMAPR01, DMAPR11 - PR01L, - PR11L - - INTST0 Note2 INTCSI00 Note2 Note2 CSIPR020, CSIPR120 PR10H CSIIF20 INTIIC20Note1 Note2 STIF0 STMK0 Note2 STPR00, STPR10 Note2 Note2 Note2 CSIIF00 CSIMK00 INTIIC00Note2 IICIF00Note2 IICMK00Note2 IICPR000, IICPR100 Note2 INTSR0 SRIF0 SRMK0 SRPR00, SRPR10 INTSRE0 Note3 Note3 SREIF0 Note3 TMIF01H INTST1 STIF1 INTSR1 Note4 Note3 Note3 SREMK0 Note3 INTTM01H CSIPR000, CSIPR100 SREPR00, SREPR10 Note3 Note3 TMMK01H IF1L Note4 STMK1 TMPR001H, TMPR101H MK1L Note4 STPR01, STPR11 SRIF1 SRMK1 INTCSI11Note4 CSIIF11Note4 CSIMK11Note4 CSIPR011, CSIPR111 Note4 INTIIC11Note4 IICIF11Note4 IICMK11Note4 IICPR011, IICPR111 Note4 INTSRE1Note5 SREIF1Note5 SREMK1Note5 SREPR01, SREPR11 Note5 Note5 Note5 SRPR01, SRPR11 Note4 Note5 Note5 INTTM03H TMIF03H TMMK03H TMPR003H, TMPR103H INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10 INTTM00 TMIF00 TMMK00 TMPR000, TMPR100 INTTM01 TMIF01 TMMK01 TMPR001, TMPR101 INTTM02 TMIF02 TMMK02 TMPR002, TMPR102 INTTM03 TMIF03 INTAD ADIF INTIT TMKAIF INTTM04 TMIF04 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 ADPR0, ADPR1 PR01H, TMKAMK TMKAPR0, TMKAPR1 PR11H TMMK04 TMPR004, TMPR104 TMMK03 IF1H ADMK TMPR003, TMPR103 MK1H 627 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-4. Flags Corresponding to Interrupt Request Sources (30-pin products) (2/2) Interrupt Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag Source INTTM05 TMIF05 INTTM06 TMIF06 INTTM07 TMIF07 INTMD MDIF INTFL FLIF IF2L IF2H Register Register R5F103 Register R5F102 <R> TMPR005, TMPR105 PR02L, TMMK06 TMPR006, TMPR106 PR12L TMMK07 TMPR007, TMPR107 TMMK05 MDMK FLMK MK2L MK2H MDPR0, MDPR1 PR02H, FLPR0, FLPR1 PR12H Notes 1. If interrupt source INTST2, INTCSI20, or INTIIC20 occurs, bit 0 of the IF0H register is set to 1. In addition, bit 0 of the MK0H, PR00H, and PR10H registers corresponds to these three interrupt sources. 2. If interrupt source INTST0, INTCSI00, or INTIIC00 occurs, bit 5 of the IF0H register is set to 1. In addition, bit 5 of the MK0H, PR00H, and PR10H registers corresponds to these three interrupt sources. 3. Do not use channel 1 (at upper level 8-bit timer operation) of UART0 and channel (at 8-bit timer operation) 1 of TAU0at the same time because they share flags for the interrupt request sources. If interrupt source INTSRE0 or INTTM01H occurs, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H registers corresponds to both interrupt sources. 4. If interrupt source INTST1, INTCSI11, or INTIIC11 occurs, bit 1 of the IF1L register is set to 1. Bit 1 of the MK1L, PR01L, and PR11L registers corresponds to these three interrupt sources. 5. Do not use channel 3 (at upper level 8-bit timer operation) of UART1 and channel 3 of TAU0 at the same time because they share flags for the interrupt request sources. If interrupt source INTTM03H occurs, bit 2 of the IF1L register is set to 1. Bit 2 of the MK1L, PR01L and PR11L registers corresponds to these two interrupt sources. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 628 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when the interrupt request is acknowledged, a reset signal is generated, or an instruction is executed. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered. IF0L, IF0H, IF1L, IF1H, and IF2H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the IF0L and IF0H registers are combined to form 16-bit register IF0, they can be set by a 16-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. Figure 15-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L) (20-, 24-pin product) Address: FFFE0H After reset: 00H R/W Symbol IF0L <7> DMAIF1 Address: FFFE1H <6> Note DMAIF0 Note After reset: 00H <5> <4> <3> <2> <1> <0> PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF <1> <0> R/W Symbol <7> <6> <5> <4> <3> <2> IF0H TMIF01 TMIF00 IICAIF0 DMAIF1 MIF01H SREIF0 SRIF0 Note CSIIF01 IICIF01 Address: FFFE2H After reset: 00H Note IICIF00 R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> IF1L 0 FLIF MDIF KRIF TMKAIF ADIF TMIF03 TMIF02 XXIFXX <R> Note STIF0 CSIIF00 Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Note Provided in the R5F102 products only. (Cautions are listed on the next page) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 629 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (30-pin product) Address: FFFE0H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF <5> <4> <1> <0> Address: FFFE1H After reset: 00H R/W Symbol <7> <6> SREIF0 IF0H SRIF0 TMIF01H STIF0 DMAIF1 <3> Note DMAIF0 <2> Note SREIF2 Note SRIF2 Note STIF2Note CSIIF00 CSIIF20Note IICIF00Note IICIF20Note Address: FFFE2H After reset: 00H R/W Symbol <7> <6> TMIF03 IF1L TMIF02 <5> TMIF01 <4> <3> TMIF00 IICAIF0 <2> <1> Note SREIF1 TMIF03H SRIF1 Note <0> STIF1Note CSIIF11Note IICIF11Note Address: FFFE3H After reset: 00H R/W Symbol <7> 6 5 4 3 <2> 1 <0> IF1H TMIF04 0 0 0 0 TMKAIF 0 ADIF Address: FFFD0H After reset: 00H R/W Symbol 7 6 5 4 3 <2> <1> <0> IF2L 0 0 0 0 0 TMIF07 TMIF06 TMIF05 Address: FFFD1H After reset: 00H R/W Symbol 7 6 <5> 4 3 2 1 0 IF2H FLIF 0 MDIF 0 0 0 0 0 XXIFXX <R> Interrupt request flag 0 No interrupt request signal is generated 1 Interrupt request is generated, interrupt request status Note Provided in the R5F102 products only. Cautions 1. Do not change undefined bit data. 2. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as IF0L.0 = 0; or _asm("clr1 IF0L, 0"); because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1). If a program is described in C language using an 8-bit memory manipulation instruction such as IF0L &= 0xfe; and compiled, it becomes the assembler of three instructions. mov a, IF0L and a, #0FEH mov IF0L, a R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 630 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS In this case, even if the request flag of the another bit of the same interrupt request flag register (IF0L) is set to 1 at the timing between mov a, IF0L and mov IF0L, a, the flag is cleared to 0 at mov IF0L, a. Therefore, care must be exercised when using an 8-bit memory manipulation instruction in C language. 15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. TheMK0L, MK0H, MK1L, MK1H, and MK2H registers can be set by a 1-bit or 8-bit memory manipulation instruction. When the MK0L and MK0H registers are combined to form 16-bit register MK0, they can be set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. Figure 15-4. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) (20, 24-pin product) Address: FFFE4H Symbol MK0L After reset: FFH <7> DMAMK1 Address: FFFE5H <6> Note Note DMAMK0 After reset: FFH R/W <5> <4> <3> <2> <1> <0> PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0H TMMK01 TMMK00 CAMK0 TMMK03H TMMK03H SREMK0 RMK0 TMK0 CSIMK01 IICMK01 Address: FFFE6H After reset: FFH CSIMK00 IICMK00 Note R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> MK1L 1 FLMK MDMK KRMK TMKAMK ADMK TMMK03 TMMK02 XXMKXX <R> Note Note Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note Provided in the R5F102 products only. Caution Do not change undefined bit data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 631 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-5. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H) (30-pin product) Address: FFFE4H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK <4> <3> <2> <1> <0> Address: FFFE5H Symbol MK0H After reset: FFH <7> <6> SREMK0 SRMK0 TMMK01H Address: FFFE6H Symbol MK1L After reset: FFH <7> <6> TMMK03 TMMK02 R/W <5> STMK0 Note DMAMK1 Note DMAMK0 Note SREMK2 SRMK2 Note STMK2Note CSIMK01 CSIMK20Note IICMK01Note IICMK20Note R/W <5> TMMK01 <4> TMMK00 <3> IICAMK0 <2> SREMK1 <1> Note TMMK03H SRMK1 <0> Note STMK1Note CSIMK11Note IICMK11Note Address: FFFE7H After reset: FFH R/W Symbol <7> 6 5 4 3 <2> 1 <0> MK1H TMMK04 1 1 1 1 TMKAMK 1 ADMK Address: FFFD4H After reset: FFH R/W Symbol 7 6 5 4 3 <2> <1> <0> MK2L 1 1 1 1 1 TMMK07 TMMK06 TMMK05 Address: FFFD5H After reset: FFH R/W Symbol 7 6 <5> 4 3 2 1 0 MK2H FLMK 1 MDMK 1 1 1 1 1 XXMKXX <R> Interrupt servicing control 0 Interrupt servicing enabled 1 Interrupt servicing disabled Note Provided in the R5F102 products only. Caution Do not change undefined bit data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 632 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) The priority specification flag registers are used to set the priority level of the corresponding maskable interrupt. A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L). The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H L registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, and the PR10L and PR10H registers are combined to form 16-bit registers PR00 and PR10, they can be set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks increases by 2 clocks. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 633 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-6. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) (20-, 24-pin product) Address: FFFE8H Symbol PR00L After reset: FFH <7> DMAPR01 Address: FFFECH R/W <6> Note DMAPR01 Note After reset: FFH <5> <4> <3> <2> <1> <0> PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0 R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR10L DMAPR11 DMAPR10 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1 <4> <3> <2> Address: FFFE9H After reset: FFH R/W Symbol <7> <6> <5> PR00H TMPR001 TMPR000 ICAPR00 TMPR003H TMPR001H SREPR00 <1> <0> SRPR00 CSIPR001 IICPR001 Address: FFFEDH After reset: FFH <7> <6> <5> PR10H TMPR101 TMPR100 ICAPR10 After reset: FFH IICPR000 Note <4> <3> TMPR103H TMPR101H <2> SREPR10 <1> <0> SRPR10 STPR10 CSIPR101 CSIPR100 IICPR101 IICPR100 R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> PR01L 1 FLPR0 MDPR0 KRPR0 TMKAPR0 ADPR0 TMPR003 TMPR002 Address: FFFEEH <R> Note STPR00 CSIPR000 R/W Symbol Address: FFFEAH Note After reset: FFH R/W Symbol 7 <6> <5> <4> <3> <2> <1> <0> PR11L 1 FLPR1 MDPR1 KRPR1 TMKAPR1 ADPR1 TMPR001 TMPR102 XXPR1X XXPR0X 0 0 Specifying level 0 (high priority) 0 1 Specifying level 1 Priority Level Selection 1 0 Specifying level 2 1 1 Specifying level 3 (low priority) Note Provided in the R5F102 products only. Caution Do not change undefined bit data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 634 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-7. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (30-pin product) (1/2) Address: FFFE8H After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0 Address: FFFECH After reset: FFH R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1 <4> <3> <2> <1> <0> Address: FFFE9H Symbol PR00H After reset: FFH <7> SREPR00 R/W <6> SRPR00 TMPR001H <5> STPR00 Note DMAPR01 Note DMAPR00 Note SREPR02 Note SRPR02 Note Note After reset: FFH Symbol <7> <6> PR10H SREPR10 SRPR10 Note IICPR020 R/W <5> <4> STPR10 <3> Note DMAPR11 <2> Note DMAPR10 <1> Note SREPR12 <0> Note SRPR12 CSIPR120 CSPR100 Note Note IICPR120 IICPR100 Symbol PR01L After reset: FFH <7> TMPR003 Note STPR12 Note TMPR101H Address: FFFEAH Note CSIPR020 CSIPR000 IICPR000 Address: FFFEDH STPR02 R/W <6> TMPR002 <5> TMPR001 <4> TMPR000 <3> IICAPR00 <2> <1> Note <0> Note SRPR01 SREPR01 TMPR003H Note STPR01 Note CSIPR011 Note IICPR011 Address: FFFEEH After reset: FFH R/W Symbol <7> <6> <5> <4> <3> PR11L TMPR103 TMPR102 TMPR101 TMPR100 IICAPR10 <2> <1> Note SREPR11 SRPR11 <0> Note STPR11 Note Note TMPR103H CSIPR111 Note IICPR111 Address: FFFEBH R/W Symbol <7> 6 5 4 3 <2> 1 <0> PR01H TMPR004 1 1 1 1 TMKAPR0 1 ADPR0 Address: FFFEFH <R> After reset: FFH After reset: FFH R/W Symbol <7> 6 5 4 3 <2> 1 <0> PR11H TMPR104 1 1 1 1 TMKAPR1 1 ADPR1 Note Provided in the R5F102 products only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 635 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-7. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (30-pin product) (2/2) Address: FFFD8H After reset: FFH R/W Symbol 7 6 5 4 3 <2> <1> <0> PR02L 1 1 1 1 1 TMPR007 TMPR006 TMPR005 Address: FFFDCH After reset: FFH R/W Symbol 7 6 5 4 3 <2> <1> <0> PR12L 1 1 1 1 1 TMPR107 TMPR106 TMPR105 Address: FFFD9H After reset: FFH R/W Symbol 7 6 <5> 4 3 2 1 0 PR02H FLPR0 1 MDPR0 1 1 1 1 1 Address: FFFDDH After reset: FFH R/W Symbol 7 6 <5> 4 3 2 1 0 PR12H FLPR1 1 MDPR1 1 1 1 1 1 XXPR1X XXPR0X 0 0 Specifying level 0 (high priority) 0 1 Specifying level 1 1 0 Specifying level 2 1 1 Specifying level 3 (low priority) Priority Level Selection Caution Do not change undefined bit data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 636 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.3.4 External interrupt rising edge enable register (EGP0), external interrupt falling edge enable register (EGN0) These registers specify the valid edge for INTP0 to INTP3. The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 15-8. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge Enable Register (EGN0) 20-, 24-pin products Address: FFF38H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGP0 0 0 0 0 EGP3 EGP2 EGP1 EGP0 Address: FFF39H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGN0 0 0 0 0 EGN3 EGN2 EGN1 EGN0 30-pin products Address: FFF38H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGP0 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0 Address: FFF39H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 EGN0 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0 EGPn EGNn 0 0 Edge detection disabled 0 1 Falling edge 1 0 Rising edge 1 1 Both rising and falling edges INTPn pin valid edge selection (n = 0 to 5) Caution Select the port mode by clearing the EGPn and EGNn bits to 0 because an edge may be detected when the external interrupt function is switched to the port function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 637 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.3.5 Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the contents of the PSW are automatically saved into a stack and the IE flag is reset to 0. If a maskable interrupt request is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are restored from the stack with the RETI, RETB, and POP PSW instructions. Reset signal generation sets PSW to 06H. Figure 15-9. Configuration of Program Status Word PSW <7> <6> <5> <4> IE Z RBS1 AC <3> <2> <1> 0 After reset RBS0 ISP1 ISP0 CY 06H Used when normal instruction is executed ISP1 ISP0 0 0 Priority of interrupt currently being serviced Enables interrupt of level 0 (while interrupt of level 1 or 0 is being serviced). 0 1 1 0 Enables interrupt of level 0 and 1 (while interrupt of level 2 is being serviced). Enables interrupt of level 0 to 2 (while interrupt of level 3 is being serviced). 1 1 Enables all interrupts (waits for acknowledgment of an interrupt). IE R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Interrupt request acknowledgment enable/disable 0 Disabled 1 Enabled 638 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.4 Interrupt Servicing Operations 15.4.1 Maskable interrupt request acknowledgment A maskable interrupt request becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged during servicing of a higher priority interrupt request. The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in Table 15-5 below. For the interrupt request acknowledgment timing, see Figures 15-11 and 15-12. Table 15-5. Time from Generation of Maskable Interrupt Until Servicing Minimum Time Servicing time 9 clocks Maximum Time Note 16 clocks Note Maximum time does not apply when an instruction from the internal RAM area is executed. Remark 1 clock: 1/fCLK (fCLK: CPU clock) If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority level, the request with the highest default priority is acknowledged first. An interrupt request that is held pending is acknowledged when it becomes acknowledgeable. Figure 15-10 shows the interrupt request acknowledgment algorithm. If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC, the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are transferred to the ISP1 and ISP0 flags. The vector table data determined for each interrupt request is the loaded into the PC and branched. Restoring from an interrupt is possible by using the RETI instruction. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 639 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-10. Interrupt Request Acknowledgment Processing Algorithm Start No xxIF = 1? Yes (interrupt request generation) xxMK = 0? No Yes Interrupt request held pending No (Low priority) (xxPR1, xxPR0) < (ISP1, ISP0) Yes (High priority) Higher priority than other interrupt requests simultaneously generated? Interrupt request held pending No Interrupt request held pending Yes Higher default priorityNote than other interrupt requests simultaneously generated? No Interrupt request held pending Yes IE = 1? Yes No Interrupt request held pending Vectored interrupt servicing xxIF: Interrupt request flag xxMK: Interrupt mask flag xxPR0: Priority specification flag 0 xxPR1: Priority specification flag 1 IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable) ISP0, ISP1: Flag that indicates the priority level of the interrupt currently being serviced (see Figure 15-9) Note For the default priority, refer to Table 15-1 and 15-2 Interrupt Source List. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 640 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-11. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program xxIF 9 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) Figure 15-12. Interrupt Request Acknowledgment Timing (Maximum Time) CPU processing Instruction 8 clocks 6 clocks Previous interrupt instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF 16 clocks Remark 1 clock: 1/fCLK (fCLK: CPU clock) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 641 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.2 Software interrupt request acknowledgment A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled. If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH, 0007FH) are loaded into the PC and branched. Restoring from a software interrupt is possible by using the RETB instruction. Caution Can not use the RETI instruction for restoring from the software interrupt. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 642 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0). Therefore, to enable multiple interrupt servicing, it is necessary to set (1) the IE flag with the EI instruction during interrupt servicing to enable interrupt acknowledgment. Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt priority control. Two types of priority control are available: default priority control and programmable priority control. Programmable priority control is used for multiple interrupt servicing. In the interrupt enabled state, if an interrupt request with a priority equal to or higher than that of the interrupt currently being serviced is generated, it is acknowledged for multiple interrupt servicing. If an interrupt with a priority lower than that of the interrupt currently being serviced is generated during interrupt servicing, it is not acknowledged for multiple interrupt servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is acknowledged following execution of at least one main processing instruction execution. Table 15-6 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 15-13 shows multiple interrupt servicing examples. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 643 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Table 15-6. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Multiple Interrupt Request Maskable Interrupt Request Priority Level 0 (PR = 00) Priority Level 2 (PR = 10) Priority Level 3 (PR = 11) Software Interrupt Request IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 ISP1 = 0 ISP0 = 0 x x x x x x x ISP1 = 0 ISP0 = 1 x x x x x x ISP1 = 1 ISP0 = 0 x x x x x ISP1 = 1 ISP0 = 1 x x x x x x x x Interrupt Being Serviced Maskable interrupt Priority Level 1 (PR = 01) Software interrupt Remarks 1. : Multiple interrupt servicing enabled 2. x: Multiple interrupt servicing disabled 3. ISP0, ISP1, and IE are flags contained in the PSW. ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced. ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced. ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced. ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment. IE = 0: Interrupt request acknowledgment is disabled. IE = 1: Interrupt request acknowledgment is enabled. 4. PR is a flag contained in the PR00L, PR00H, PR01L, PR10L, PR10H, PR11L registers. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 644 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-13. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing IE = 0 EI INTyy servicing IE = 0 IE = 0 EI INTxx (PR = 11) INTzz servicing EI INTyy (PR = 10) INTzz (PR = 01) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place. Before each interrupt request is acknowledged, the EI instruction must always be issued to enable interrupt request acknowledgment. Example 2. Multiple interrupt servicing does not occur due to priority control Main processing EI INTxx servicing INTyy servicing IE = 0 EI INTxx (PR = 10) INTyy (PR = 11) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupt request INTyy issued during servicing of interrupt INTxx is not acknowledged because its priority is lower than that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 645 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS Figure 15-13. Examples of Multiple Interrupt Servicing (2/2) Example 3. Multiple interrupt servicing does not occur because interrupts are not enabled Main processing INTxx servicing INTyy servicing IE = 0 EI INTxx (PR = 11) INTyy (PR = 00) RETI IE = 1 1 instruction execution IE = 0 RETI IE = 1 Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is acknowledged following execution of one main processing instruction. PR = 00: Specify level 0 with xxPR1x = 0, xxPR0x = 0 (higher priority level) PR = 01: Specify level 1 with xxPR1x = 0, xxPR0x = 1 PR = 10: Specify level 2 with xxPR1x = 1, xxPR0x = 0 PR = 11: Specify level 3 with xxPR1x = 1, xxPR0x = 1 (lower priority level) IE = 0: Interrupt request acknowledgment is disabled IE = 1: Interrupt request acknowledgment is enabled. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 646 RL78/G12 CHAPTER 15 INTERRUPT FUNCTIONS 15.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. * MOV PSW, #byte * MOV PSW, A * MOV1 PSW. bit, CY * SET1 PSW. bit * CLR1 PSW. bit * RETB * RETI * POP PSW * BTCLR PSW. bit, $addr20 * EI * DI * SKC * SKNC * SKZ * SKNZ * SKH * SKNH * Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR00L, PR00H, PR01L, PR10L, PR10H, and PR11L registers Figure 15-14 shows the timing at which interrupt requests are held pending. Figure 15-14. Interrupt Request Hold CPU processing Instruction N Instruction M PSW and PC saved, jump to interrupt servicing Interrupt servicing program xxIF Remarks 1. Instruction N: Interrupt request hold instruction 2. Instruction M: Instruction other than interrupt request hold instruction R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 647 RL78/G12 CHAPTER 16 KEY INTERRUPT FUNCTION CHAPTER 16 KEY INTERRUPT FUNCTION 16.1 Functions of Key Interrupt In 20- and 24-pin products, a key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a rising edge/falling edge to the key interrupt input pins (KR0 to KR9). Table 16-1. Assignment of Key Interrupt Detection Pins Flag Description KRM00 Controls KR0 signal in 1-bit units. KRM01 Controls KR1 signal in 1-bit units. KRM02 Controls KR2 signal in 1-bit units. KRM03 Controls KR3 signal in 1-bit units. KRM04 Controls KR4 signal in 1-bit units. KRM05 Controls KR5 signal in 1-bit units. KRM06 Note Controls KR6 signal in 1-bit units. KRM07 Note Controls KR7 signal in 1-bit units. KRM08 Note Controls KR8 signal in 1-bit units. KRM09 Note Controls KR9 signal in 1-bit units. Note Provided in 24-pin products only. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 648 RL78/G12 CHAPTER 16 KEY INTERRUPT FUNCTION 16.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 16-2. Configuration of Key Interrupt Item Configuration Input KR0 to KR9 Control register Key return control register (KRCTL) Key return mode control registers (KRM0, KRM1) Key return flag register (KRF) Port mode registers 0, 4, 6, and 12 (PM0, PM4,PM6, PM12) Port register 0, 4, 6, and 12 (P0, P4, P6, P12) Figure 16-1. Block Diagram of Key Interrupt KR9 KR8 KR7 KR6 KR5 INTKR KR4 KR3 KR2 KR1 KR0 KRM9 KRM8 KRM7 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0 Key return mode registers KRM0, KRM1 16.3 Register Controlling Key Interrupt The key interrupt function is controlled by the following five registers: * Key return control register (KRCTL) * Key return mode control registers (KRM0, KRM1) * Key return flag register (KRF) * Port mode registers 0, 4, 6, and 12 (PM0, PM4, PM6, PM12) * Port registers 0, 4, 6, and 12 (P0, P4, P6, P12) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 649 RL78/G12 CHAPTER 16 KEY INTERRUPT FUNCTION 16.3.1 Key return control register (KRCTL) This register controls the usage of the key return flags (KRF0 to KRF5) and sets the detection edge. The KRCTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-2. Format of Key Return Control Register (KRCTL) Address: FFF34H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 KRCTL KRMD 0 0 0 0 0 0 KREG KRMD Usage of Key Return Flags (KRF0 to KRF5) 0 Does not use key return flags 1 Uses key return flags KREG Selection of Detection Edge (KR0 to KR9) 0 Falling edge 1 Rising edge 16.3.2 Key return mode control registers (KRM0, KRM1) These registers set the key interrupt mode. The KRM0 and KRM1 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 16-3. Format of Key Return Control Registers (KRM0, KRM1) 20-pin products Address: FFF37H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 KRM0 0 0 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00 24-pin products Address: FFF37H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 KRM0 KRM07 KRM06 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00 Address: FFF36H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 KRM1 0 0 0 0 0 0 KRM09 KRM08 KRM0n Key interrupt mode control 0 Does not detect key interrupt signal 1 Detects key interrupt signal R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 650 RL78/G12 CHAPTER 16 KEY INTERRUPT FUNCTION Cautions 1. When the bits to be used among the KRM0 to KRM9 bits are set to 1, pull up the relevant input pins to VDD by an external resistor. For the KR1, KR6 to KR9 pins, the internal pull-up resistor can be used by setting the relevant bits to 1 in the input pins PU125, PU00 to PU03 (pull-up resistor registers 12 and 0 (the bit 5 of PU12 and bits 0 to 3 of PU0)). 2. An interrupt is generated if the target bit of the KRF register is set while the low level is input to the key interrupt input pin. If no want to generate this interrupt, set the KRM register after disabling interrupt servicing by using the interrupt mask flag. After waiting for the key interrupt input low-level width (at least 250 ns), clear the interrupt request flag and enable interrupt servicing . 2. The bits not used in the key interrupt mode can be used as normal ports. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 651 RL78/G12 CHAPTER 16 KEY INTERRUPT FUNCTION 16.3.3 Key return flag register (KRF) This register controls the key return flags (KRF0 to KRF5). The KRF register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-4. Format of Key Return Flag Register (KRF) Address: FFF35H After reset: 00H R/W Note Symbol 7 6 5 4 3 2 1 0 KRF 0 0 KRF5 KRF4 KRF3 KRF2 KRF1 KRF0 KRFn Key interrupt flag 0 No key interrupt signal has been detected. 1 A key interrupt signal has been detected. Note Writing to 1 is invalid. To clear KRFn, write "0" to the target bits and write "1" to other bits, with the 8-bit memory manipulation instruction. Cautions 1. When KRMD = 0, prohibition of set to KRFn = 1. 2. When KRFn bits are 1 and input to the KR6 to KR9 pins exists, keep the input to KR6 to KR9 pins. If clearing KRFn bits is delayed, INTKR does not occur. For KR6 to KR9, identify channels by sequentially verifying the input levels. 16.3.4 Port mode registers 0, 4, 6, 12 (PM0, PM4, PM6, PM12) These registers set the input and output of Port 0, 4, 6, 12 in 1-bit units. Set 1 to the bit of port mode register (PM0) corresponding to each port when using P00/KR6 to P03/KR9 as a key input in a 24-pin product. Similarly, set 1 to the bit corresponding to each port of PM4, PM12, and PM6 to use P40/KR0, P125/KR1, P122/KR2, P121/KR3, P60/KR4, and P61/KR5 as a key input. In addition, set 1 to the bits corresponding with port registers 0, 4, 6, and 12 (P0, P4, P6, P12). The PM0, PM4, PM6, PM12 registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to FFH. Figure 16-5. Format of Port Mode Register 0 (PM0) Address: FFF20H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 PM0 1 1 1 1 PM03 PM02 PM01 PM00 PM0n I/O mode selection for P0n/KRm pin (n = 0 to 3, m = 6 to 9) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 652 RL78/G12 CHAPTER 17 STANDBY FUNCTION CHAPTER 17 STANDBY FUNCTION 17.1 Standby Function and Configuration 17.1.1 Standby function The standby function reduces the operating current of the system, and the following three modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped. If the highspeed system clock oscillator or high-speed on-chip oscillator is operating before the HALT mode is set, oscillation of each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out intermittent operations frequently. (2) STOP mode STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and high-speed on-chip oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating current. Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out. However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released when the X1 clock is selected, select the HALT mode if it is necessary to start processing immediately upon interrupt request generation. (3) SNOOZE mode In the case of CSI00 or UART0 data reception and an A/D conversion request by the timer trigger signal (the interrupt request signal (INTIT)), the STOP mode is exited, the CSI00 or UART0 data is received without operating the CPU, and A/D conversion is performed. This can only be specified when the high-speed on-chip oscillator clock is selected for the CPU/peripheral hardware clock (fCLK). In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set are held. The I/O port output latches and output buffer statuses are also held. Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating with X1 oscillation or EXCLK input before executing STOP instruction (other than SNOOZE mode setting unit). 2 When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby control register 0 (SSC0) and A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 11.3 Registers Controlling Serial Array Unit and 10.3 Registers Used in A/D Converter. 3. The following sequence is recommended for operating current reduction of the A/D converter when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP instruction. 4. It can be selected by the option byte whether the low-speed on-chip oscillator continues oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 23 OPTION BYTE. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 653 RL78/G12 CHAPTER 17 STANDBY FUNCTION 17.1.2 Registers controlling standby function The standby function is controlled by the following two registers. * Oscillation stabilization time counter status register (OSTC) * Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 654 RL78/G12 CHAPTER 17 STANDBY FUNCTION (1) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. The X1 clock oscillation stabilization time can be checked in the following case. * If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock. * If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock. And the X1 clock is oscillating. The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction. When reset is released (reset by RESET input, POR, LVD, WDT, and executing an illegal instruction), the STOP instruction and MSTOP bit (bit 7 of clock operation status control register (CSC)) = 1 clear this register to 00H. Figure 17-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFFA2H Symbol OSTC 7 After reset: 00H 6 5 R 4 3 2 1 0 MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 Oscillation stabilization time status MOST MOST MOST MOST MOST MOST MOST MOST 8 9 10 11 13 15 17 18 fX = 10 MHz fX = 20 MHz 0 0 0 0 0 0 0 0 2 /fX max. 25.6 s max. 12.8 s max. 1 0 0 0 0 0 0 0 2 /fX min. 25.6 s min. 12.8 s min. 1 1 0 0 0 0 0 0 2 /fX min. 51.2 s min. 25.6 s min. 8 8 9 1 1 1 0 0 0 0 0 2 /fX min. 102.4 s min. 51.2 s min. 1 1 1 1 0 0 0 0 2 /fX min. 204.8 s min. 102.4 s min. 1 1 1 1 1 0 0 0 2 /fX min. 819.2 s min. 409.6 s min. 1 1 1 1 1 1 0 0 2 /fX min. 3.27 ms min. 1 1 1 1 1 1 1 0 2 /fX min. 13.11 ms min. 6.55 ms min. 1 1 1 1 1 1 1 1 2 /fX min. 26.21 ms min. 13.11 ms min. 10 11 13 15 1.64 ms min. 17 18 Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit and remain 1. 2. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the oscillation stabilization time select register (OSTS). If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC register oscillation stabilization time Oscillation stabilization time set by OSTS register Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after STOP mode is released. 3. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 655 RL78/G12 CHAPTER 17 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using the OSTS register after the STOP mode is released. When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization time counter status register (OSTC) that the desired oscillation stabilization time has elapsed after the STOP mode is released. The oscillation stabilization time can be checked up to the time set using the OSTC register. The OSTS register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 07H. Figure 17-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFFA3H After reset: 07H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz fX = 20 MHz 0 0 0 2 /fX 25.6 s 12.8 s 0 0 1 2 /fX 9 51.2 s 25.6 s 10 102.4 s 51.2 s 11 204.8 s 102.4 s 13 819.2 s 409.6 s 15 3.27 ms 1.64 ms 17 13.11 ms 6.55 ms 18 26.21 ms 13.11 ms 8 0 1 0 2 /fX 0 1 1 2 /fX 1 0 0 2 /fX 1 0 1 2 /fX 1 1 0 2 /fX 1 1 1 2 /fX Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS register before executing the STOP instruction. 2. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC register is completed. 3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time. 4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by the OSTS register. If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows. * Desired OSTC register oscillation stabilization time Oscillation stabilization time set by OSTS register Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS register is set to the OSTC register after STOP mode is released. 5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation starts ("a" below). STOP mode release X1 pin voltage waveform a Remark fX: X1 clock oscillation frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 656 RL78/G12 CHAPTER 17 STANDBY FUNCTION 17.2 Standby Function Operation 17.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock or the high-speed on-chip oscillator clock. The operating statuses in the HALT mode are shown below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 657 RL78/G12 CHAPTER 17 STANDBY FUNCTION Table 17-1. Operating Statuses in HALT Mode HALT Mode Setting When CPU Is Operating on High-speed On-chip Oscillator Clock (fIH) Item System clock Main system clock When HALT Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on X1 Clock (fX) When CPU Is Operating on External Main System Clock (fEX) Clock supply to the CPU is stopped fIH Operation continues (cannot be stopped) Operation disabled fX Operation disabled Operation continues (cannot be stopped) Cannot operate Cannot operate Operation continues (cannot be stopped) fEX fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK0 = 1: Oscillates * WUTMMCK0 = 0 and WDTON = 0: Stops * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory Operation stopped Data flash memory RAM Port (latch) Status before HALT mode was set is retained Timer array unit Operable 12-bit interval timer Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H) * WDSTBYON = 0: Operation stopped * WDSTBYON = 1: Operation continues (cannot be stopped) Clock output/buzzer output Operable A/D converter Serial array unit (SAU) Serial interface (IICA) Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Voltage detection function External interrupt Key interrupt function CRC operation function In the calculation of the RAM area, operable when DMA is executed only RAM parity error detection function Operable when DMA is executed only RAM guard function SFR guard function Illegal-memory access detection function Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode. Operation disabled: Operation is stopped before switching to the HALT mode. fIH: High-speed on-chip oscillator clock Low-speed on-chip oscillator clock fIL: fX: X1 clock fEX: External main system clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 658 RL78/G12 CHAPTER 17 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 17-3. HALT Mode Release by Interrupt Request Generation HALT instruction Interrupt request Standby release signal Note 1 Status of CPU Operating mode High-speed system clock or High-speed on-chip oscillator clock Notes 1. 2. Remark Wait Note 2 HALT mode Operating mode Oscillation Refer to Figure 15-1. Basic Configuration of Interrupt Function Wait time for HALT mode release * When vectored interrupt servicing is carried out: 15 to 16 clock * When vectored interrupt servicing is not carried out: 9 to 10 clock The broken lines indicate the case when the interrupt request which has released the standby mode is acknowledged. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 659 RL78/G12 CHAPTER 17 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 17-4. HALT Mode Release by Reset (1) When high-speed system clock is used as CPU clock <R> <R> (2) When high-speed on-chip oscillator clock is used as CPU clock <R> Note For reset processing time, see CHAPTER 18 RESET FUNCTION. For reset processing time for Poweron-reset circuit (POR) and Voltage detection (LVD) circuit, see CHAPTER 19 POWER-ON-RESET CIRCUIT. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 660 RL78/G12 CHAPTER 17 STANDBY FUNCTION 17.2.2 STOP mode (1) STOP mode setting and operating statuses The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the setting was the internal high-speed oscillation clock, X1 clock, or external main system clock. <R> Cautions 1. Because the interrupt request signal is used to clear the STOP mode, if there is an interrupt source with the interrupt request flag set and the interrupt mask flag reset, the STOP mode is immediately cleared if set. Thus, when a STOP instruction is executed in this situation, the system returns to its normal operating mode as soon as the wait time set by using the oscillation stabilization time select register (OSTS) has elapsed. Note that the operating current during this period is the same as in the HALT mode because the clock is not stopped. 2. When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby control register 0 (SSC0) and A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 11.3 Registers Controlling Serial Array Unit and 10.3 Registers Used in A/D Converter. The operating statuses in the STOP mode are shown below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 661 RL78/G12 CHAPTER 17 STANDBY FUNCTION Table 17-2. Operating Statuses in STOP Mode STOP Mode Setting When STOP Instruction Is Executed While CPU Is Operating on Main System Clock When CPU Is Operating on X1 Clock (fX) Item When CPU Is Operating on High-speed On-chip Oscillator Clock (fIH) System clock Clock supply to the CPU is stopped Main system clock fIH When CPU Is Operating on External Main System Clock (fEX) Stopped fX fEX fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK = 1: Oscillates * WUTMMCK = 0 and WDTON = 0: Stops * WUTMMCK = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory <R> Data flash memory Operation stopped RAM Operation stopped Port (latch) Status before STOP mode was set is retained Timer array unit Operation disabled 12-bit interval timer Operable Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H) * WDSTBYON = 0: Operation stopped * WDSTBYON = 1: Operation continues (cannot be stopped) Clock output/buzzer output Operation disabled A/D converter Wakeup operation is enabled (switching to the SNOOZE mode) Serial array unit (SAU) Wakeup operation is enabled only for CSI00 and UART0 (switching to the SNOOZE mode) Operation is disabled for anything other than CSI00 and UART0 Serial interface (IICA) Wakeup by address match operable Multiplier and divider/multiplyaccumulator Operation disabled DMA controller Power-on-reset function Operable Voltage detection function External interrupt Key interrupt function CRC operation function Operation stopped RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remark Operation stopped: Operation disabled: Operation is automatically stopped before switching to the STOP mode. Operation is stopped before switching to the STOP mode. fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock fX: X1 clock fEX: External main system clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 662 RL78/G12 CHAPTER 17 STANDBY FUNCTION <R> Cautions 1. To stop the low-speed on-chip oscillator clock clock in the STOP mode, must previously be set an option byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of 000C0H = 0). 2. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the highspeed on-chip oscillator clock before the execution of the STOP instruction. Before changing the CPU clock from the high-speed on-chip oscillator clock to the high-speed system clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time with the oscillation stabilization time counter status register (OSTC). (2) STOP mode release The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 17-5. STOP Mode Release by Interrupt Request Generation (1/2) (1) When high-speed system clock (X1 oscillation) is used as CPU clock Interrupt request STOP instruction Standby release signal Note 1 Status of CPU High-speed system clock (X1 oscillation) Notes 1. 2. STOP mode release time Note 2 Normal operation (high-speed system clock) STOP mode Oscillates Oscillation stopped Supply of the clock is stopped Wait Normal operation (high-speed system clock) Oscillates Refer to Figure 15-1. Basic Configuration of Interrupt Function Time for STOP mode release Supply of the clock is stopped: 18.96 s to "whichever is longer 28.95 s and the oscillation stabilization time (set by OSTS)" Wait * When vectored interrupt servicing is carried out: 10 to 11 clock * When vectored interrupt servicing is not carried out: 4 to 5 clock Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 663 RL78/G12 CHAPTER 17 STANDBY FUNCTION Figure 17-5. STOP Mode Release by Interrupt Request Generation (2/2) (2) When high-speed system clock (external clock input) is used as CPU clock STOP instruction Interrupt request Standby release signalNote 1 Status of CPU STOP mode release tuime Note 2 Normal operation (high-speed system clock) STOP mode Oscillates Oscillation stopped High-speed system clock (external clock input) Supply of the clock is stopped Normal operation (high-speed system clock) Wait Oscillates (3) When high-speed on-chip oscillator clock is used as CPU clock STOP instruction Interrupt request Standby release signal Note 1 Normal operation (high-speed on-chip oscillator clock) STOP mode release tuime Note 2 Supply of the clock is stopped STOP mode Status of CPU High-speed on-chip oscillator clock Oscillates Wait Normal operation (high-speed on-chip oscillator clock) Oscillates Oscillation stopped Wait for oscillation accuracy stabilization Notes 1. 2. Refer to Figure 15-1. Basic Configuration of Interrupt Function STOP mode release time Supply of the clock is stopped:19.08 to 32.99 s Wait * When vectored interrupt servicing is carried out: 7 clock * When vectored interrupt servicing is not carried out: 1 clock Remark The broken lines indicate the case when the interrupt request that has released the standby mode is acknowledged. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 664 RL78/G12 CHAPTER 17 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 17-6. STOP Mode Release by Reset (1) When high-speed system clock is used as CPU clock <R> <R> <R> (2) When high-speed on-chip oscillator clock is used as CPU clock Note For reset processing time, see CHAPTER 18 RESET FUNCTION. For reset processing time for Poweron-reset circuit (POR) and Voltage detection (LVD) circuit, see CHAPTER 19 POWER-ON-RESET CIRCUIT. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 665 RL78/G12 CHAPTER 17 STANDBY FUNCTION 17.2.3 SNOOZE mode (1) SNOOZE mode setting and operating statuses The SNOOZE mode can only be specified for CSI00, UART0, or the A/D converter. Note that this mode can only be specified if the CPU clock is the high-speed on-chip oscillator clock. When using CSI00 or UART0 in the SNOOZE mode, set up serial standby control register 0 (SSC0) before switching to the STOP mode. For details, see 11.3 Registers Controlling Serial Array Unit. When using the A/D converter in the SNOOZE mode, set up A/D converter mode register 2 (ADM2) before switching to the STOP mode. For details, see 10.3 Registers Used in A/D Converter. In SNOOZE mode rerease, wait status to be only following time. From STOP to SNOOZE HS (high-speed main) mode : 18.96 to 28.95 s LS (low-speed main) mode : 20.24 to 28.95 s From SNOOZE to normal operation * When vectored interrupt servicing is carried out: HS (high-speed main) mode : 6.79 to 12.4 s + 7 clock <R> LS (low-speed main) mode : 2.58 to 7.8 s + 7 clock * When vectored interrupt servicing is not carried out: HS (high-speed main) mode : 6.79 to 12.4 s + 1 clock <R> LS (low-speed main) mode : 2.58 to 7.8 s + 1 clock The operating statuses in the SNOOZE mode are shown below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 666 RL78/G12 CHAPTER 17 STANDBY FUNCTION Table 17-3. Operating Statuses in SNOOZE Mode STOP Mode Setting When Inputting CSI00/UART0 Data Reception Signal or A/D Converter Timer Trigger Signal While in STOP Mode Item When CPU Is Operating on High-speed On-chip Oscillator Clock (fIH) System clock Main system clock Clock supply to the CPU is stopped fIH Operation started fX Stopped fEX fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of operation speed mode control register (OSMC) * WUTMMCK = 1: Oscillates * WUTMMCK = 0 and WDTON = 0: Stops * WUTMMCK = 0, WDTON = 1, and WDSTBYON = 1: Oscillates * WUTMMCK = 0, WDTON = 1, and WDSTBYON = 0: Stops CPU Operation stopped Code flash memory Data flash memory RAM Port (latch) Status while in STOP mode continues Timer array unit Operation disabled 12-bit interval timer Operable Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H) * WDSTBYON = 0: Operation stopped * WDSTBYON = 1: Operation continues (cannot be stopped) Clock output/buzzer output Operation stopped A/D converter Operable Serial array unit (SAU) Operable only CSI00 and UART0 only. Operation disabled other than CSI00 and UART0. Serial interface (IICA) Operation disabled Multiplier and divider/multiplyaccumulator DMA controller Power-on-reset function Operable Voltage detection function External interrupt Key interrupt function CRC operation function Operation disabled RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode. Operation disabled: Operation is stopped before switching to the STOP mode. fIH: High-speed on-chip oscillator clock fIL: Low-speed on-chip oscillator clock fX: X1 clock fEX: External main system clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 667 RL78/G12 CHAPTER 18 RESET FUNCTION CHAPTER 18 RESET FUNCTION The following seven operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit (4) Internal reset by comparison of supply voltage of the voltage detector (LVD) and detection voltage (5) Internal reset by execution of illegal instructionNote (6) Internal reset by RAM parity error (7) Internal reset by illegal-memory access External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is generated. A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD circuit voltage detection, execution of illegal instructionNote, RAM parity error or illegal-memory access, and each item of hardware is set to the status shown in Tables 18-1. When a low level is input to the RESET pin, the device is reset. It is released from the reset status when a high level is input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed on-chip oscillator clock (see Figures 18-2 to 18-4) after reset processing. Reset by POR and LVD circuit supply voltage detection is automatically released when VDD VPOR or VDD VLVD after the reset, and program execution starts using the high-speed on-chip oscillator clock (see CHAPTER 19 POWER-ON-RESET CIRCUIT and CHAPTER 20 VOLTAGE DETECTOR) after reset processing. Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Cautions 1. For an external reset, input a low level for 10 s or more to the RESET pin. (To perform an external reset upon power application, a low level of at least 10 s must be continued during the period in which the supply voltage is within the operating range (VDD 1.8 V).) 2. During reset input, the X1 clock, high-speed on-chip oscillator clock, and low-speed on-chip oscillator clock stop oscillating, and external main system clock input is invalid. <R> 3. Each of the SFRs and 2nd SFRs are initialized when a reset is applied, so port pin P125 is set for low-level output (in the case of an external reset) and P40 becomes high-impedance (in the case of an external reset or POR reset) or is pulled-up (in the case of other types of reset), and the other port pins become high impedance. Remark VPOR: POR power supply rise detection voltage R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 668 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Set Clear Clear Set WDTRF 2. LVIS: Voltage detection level register Remarks 1. LVIM: Voltage detection register Caution An LVD circuit internal reset does not reset the LVD circuit. Voltage detector reset signal Power-on reset circuit reset signal RESET RESF register read signal Reset signal by illegal-memory access Reset signal by RAM parity error Reset signal by execution of illegal instruction Watchdog timer reset signal TRAP Set Clear RPERF Internal bus Set IAWRF Clear Reset control flag register (RESF) Set LVIRF Figure 18-1. Block Diagram of Reset Function Clear Reset signal Reset signal to LVIM/LVIS register RL78/G12 CHAPTER 18 RESET FUNCTION 669 RL78/G12 CHAPTER 18 RESET FUNCTION Figure 18-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) Reset period CPU status <R> Normal operation (high-speed on-chip oscillator clock) Normal operation Reset processing for release from the external reset state Note RESET Internal reset signal Delay Hi-Z Port pin <R> Note Reset times (times for release from the external reset state) After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use. 0.399 ms (typ.), 0.519 ms (max.) when the LVD is off. After the second release of the POR: 0.531 ms (typ.), 0.675 ms (max.) when the LVD is in use. 0.259 ms (typ.), 0.362 ms (max.) when the LVD is off. After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.) is required before reset processing starts after release of the external reset. Figure 18-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow <R> Wait for oscillation accuracy stabilization High-speed on-chip oscillator clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) <R> CPU status Watchdog timer overflow Execution of Illegal Instruction/ RAM parity error detection/ Illegal-memory access detection Internal reset signal Normal operation Reset period (oscillation stop) Reset processing 0.0629 ms (typ.) 0.0701 ms (max.) Port pin Normal operation (high-speed on-chip oscillator clock) Hi-Z Caution A watchdog timer internal reset resets the watchdog timer. <R> Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 19 POWERONRESET CIRCUIT and CHAPTER 20 VOLTAGE DETECTOR. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 670 RL78/G12 CHAPTER 18 RESET FUNCTION Table 18-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped. Main system clock fIH Operation stopped fX Operation stopped (the X1 and X2 pins are input port mode) fEX Clock input invalid (the pin is input port mode) Operation stopped fIL CPU <R> Code flash memory Operation stopped Data flash memory Operation stopped RAM Operation stopped Port (latch) P125 is set to low-level output (in the case of an external reset) or high-impedance (in the case of a reset other than external reset) P40 becomes high impedance (in the case of an external reset or POR reset) or pulled-up (in the case of a reset other than external reset and POR reset) The port pins except for P125 and P40 become high impedance. Timer array unit Operation stopped 12-bit Interval timer Watchdog timer Clock output/buzzer output A/D converter Serial array unit (SAU) Serial interface (IICA) Multiplier & divider, multiplyaccumulator DMA controller Power-on-reset function Detection operation possible Voltage detection function Operation stopped External interrupt Operation stopped Key interrupt function CRC operation function RAM parity error detection function RAM guard function SFR guard function Illegal-memory access detection function Remark fIH: fX: High-speed on-chip oscillator clock X1 oscillation clock fEX: External main system clock fIL: Low-speed on-chip oscillator clock R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 671 RL78/G12 CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (1/3) After Reset Note 1 Acknowledgment Hardware Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set. Stack pointer (SP) Undefined Program status word (PSW) 06H RAM Data memory Undefined General-purpose registers Undefined Processor mode control register (PMC) <R> 00H Port registers (P0 to P6, P12 to P14 (output latches)) 00H Port mode registers (PM0 to PM6, PM12, PM14) FFH Port mode control registers 1, 4 (PMC0, PMC1, PMC4, PMC12, PMC14) FFH Port input mode registers 1 (PIM0, PIM1) 00H Port output mode registers 0, 1, 4 (POM0, POM1, POM4, POM5) 00H Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU12, PU14) 00H (PU4 is 01H PU12 of 20-, 24-pin is 20H) Peripheral I/O redirection register (PIOR) 00H Clock operation mode control register (CMC) 00H Clock operation status control register (CSC) C0H System clock control register (CKC) 00H Oscillation stabilization time counter status register (OSTC) 00H Oscillation stabilization time select register (OSTS) 07H Noise filter enable registers 0 (NFEN0) 00H Peripheral enable register 0 (PER0) 00H High-speed on-chip oscillator frequency select register (HOCODIV) Undefined High-speed on-chip oscillator trimming register (HIOTRM) Undefined Operation speed mode control register (OSMC) 00H Timer array unit Timer data registers 00 to 07 (TDR00 to TDR07) 0000H Timer mode registers 00 to 07 (TMR00 to TMR07) 0000H Timer status registers 00 to 03 (TSR00 to TSR03) 0000H Timer input select register 0 (TIS0) 00H Timer counter registers 00 to 07 (TCR00 to TCR07) FFFFH Timer channel enable status register 0 (TE0) 0000H Timer channel start register 0 (TS0) 0000H Timer channel stop register 0 (TT0) 0000H Timer clock select register 0 (TPS0) 0000H Timer output register 0 (TO0) 0000H Timer output enable register 0 (TOE0) 0000H Timer output level register 0 (TOL0) 0000H Timer output mode registers 0 (TOM0) 0000H 12-bit interval timer Control register (ITMC) 0FFFH Clock output/buzzer output Clock output select registers 0, 1 (CKS0, CKS1) 00H Watchdog timer Enable register (WDTE) 1AH/9AH Notes 1. Note 2 Note 3 During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. <R> 2. The value after a reset is adjusted at the time of shipment.. 3. The reset value of WDTE is decided by the settings of the option bite (WDTON bit). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 672 RL78/G12 CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (2/3) Hardware A/D converter Serial array unit (SAU) After Reset Note 1 Acknowledgment 10-bit A/D conversion result register (ADCR) 0000H 8-bit A/D conversion result register (ADCRH) 00H Mode registers 0 to 2 (ADM0 to ADM2) 00H Conversion result comparison upper limit setting register (ADUL) FFH Conversion result comparison lower limit setting register (ADLL) 00H A/D test register (ADTES) 00H Analog input channel specification register (ADS) 00H A/D port configuration register (ADPC) 00H Serial data registers 00 to 03, 10, 11 (SDR00 to SDR03, SDR10, SDR11) 0000H Serial status registers 00 to 03, 10, 11 (SSR00 to SSR03, SSR10, SSR11) 0000H Serial flag clear trigger registers 00 to 03, 10, 11 (SIR00 to SIR03, SIR10, SIR10) 0000H Serial mode registers 00 to 03, 10, 11 (SMR00 to SMR03, SMR10, SMR11) 0020H Serial communication operation setting registers 00 to 03, 10, 11 (SCR00 to 0087H SCR03, SCR10, SCR11) Serial interface IICA Serial channel enable status registers 0, 1 (SE0, SE1) 0000H Serial channel start registers 0, 1 (SS0, SS1) 0000H Serial channel stop registers 0, 1 (ST0, ST1) 0000H Serial clock select registers 0, 1 (SPS0, SPS1) 0000H Serial output registers 0, 1 (SO0, SO1) 0F0FH Serial output enable registers 0, 1 (SOE0, SOE1) 0000H Serial output level registers 0, 1 (SOL0, SOL1) 0000H Serial standby control register 0 (SSC0) 0000H IICA shift register 0 (IICA0) 00H IICA status register 0 (IICS0) 00H IICA flag register 0 (IICF0) 00H IICA control register 00 (IICCTL00) 00H IICA control register 01 (IICCTL01) 00H IICA low-level width setting register 0 (IICWL0) FFH IICA high-level width setting register 0 (IICWH0) FFH Slave address register 0 (SVA0) 00H Multiplier & divider, Multiplication/division data register A (L) (MDAL) 0000H multiply-accumulator Multiplication/division data register A (H) (MDAH) 0000H Multiplication/division data register B (L) (MDBL) 0000H Multiplication/division data register B (H) (MDBH) 0000H Multiplication/division data register C (L) (MDCL) 0000H Multiplication/division data register C (H) (MDCH) 0000H Multiplication/division control register (MDUC) 00H Key return control register (KRTCL) 00H Key return mode register (KRM0, KRM1) 00H Key return flag register (KRF) 00H Key interrupt Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 673 RL78/G12 CHAPTER 18 RESET FUNCTION Table 18-2. Hardware Statuses After Reset Acknowledgment (3/3) After Reset Note 1 Acknowledgment Hardware Reset function Reset control flag register (RESF) Voltage detector (LVD) Voltage detection register (LVIM) Note 2 Voltage detection level register (LVIS) Notes 2, 3 DMA controller Interrupt Safety functions Note 2 SFR address registers 0, 1 (DSA0, DSA1) 00H RAM address registers 0, 1 (DRA0, DRA1) 00H Byte count registers 0, 1 (DBC0, DBC1) 00H Mode control registers 0, 1 (DMC0, DMC1) 00H Operation control registers 0, 1 (DRC0, DRC1) 00H Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) 00H Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,MK1H, MK2L, MK2H) FFH Priority specification flag registers 00L, 00H, 01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,PR11H, PR12L, PR12H) FFH External interrupt rising edge enable register 0, 1 (EGP0, EGP1) 00H External interrupt falling edge enable register 0,1 (EGN0, EGN1) 00H Flash memory CRC control register (CRC0CTL) 00H Flash memory CRC operation result register (PGCRCL) 0000H CRC input register 00H CRC data register 0000H Invalid memory access detection control register (IAWCTL) 00H RAM parity error control register (RPECTL) 00H Flash memory Data flash control register (DFLCTL) 00H BCD correction circuit BCD correction result register (BCDAJ) Undefined Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware statuses become undefined. All other hardware statuses remain unchanged after reset. 2. These values vary depending on the reset source. Reset Source RESET Input Register RESF TRAP bit Cleared (0) WDTRF bit LVIM Reset by POR Reset by Execution of Illegal Instruction Set (1) Held Held Set (1) RPERF bit Held IAWRF bit Held LVIRF bit Held LVISEN bit Reset by WDT Reset by RAM parity error Reset by illegalmemory access Reset by LVD Held Held Set (1) Cleared (0) Held Set (1) Set (1) Held LVIOMSK bit Held LVIF bit LVIS Cleared (00H/01H/81H) 3. The generation of reset signal other than an LVD reset sets as follows. * When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H * When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H * When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 674 RL78/G12 CHAPTER 18 RESET FUNCTION 18.1 Register for Confirming Reset Source 18.1.1 Reset Control Flag Register (RESF) Many internal reset generation sources exist in the RL78/G12. The reset control flag register (RESF) is used to store which source has generated the reset request. The RESF register can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags. Figure 18-5. Format of Reset Control Flag Register (RESF) Address: FFFA8H After reset: 00H Note 1 R Symbol 7 6 5 4 3 2 1 0 RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF TRAP 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. WDTRF Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. Internal reset request t by RAM parity 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. IAWRF Internal reset request t by illegal-memory access 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. LVIRF Note 2 Internal reset request by watchdog timer (WDT) 0 RPERF Notes 1. Internal reset request by execution of illegal instruction Internal reset request by voltage detector (LVD) 0 Internal reset request is not generated, or the RESF register is cleared. 1 Internal reset request is generated. The value after reset varies depending on the reset source. 2. The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. Caution 1. <R> 2. Do not read data by a 1-bit memory manipulation instruction. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed and the RAM area + 10 bytes when instructions are fetched from RAM areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For details, see 21.3.2 RAM parity error detection function. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 675 RL78/G12 CHAPTER 18 RESET FUNCTION The status of the RESF register when a reset request is generated is shown in Table 18-3. Table 18-3. RESF Register Status When Reset Request Is Generated Reset Source RESET Input Flag Reset by Reset by Reset by Reset by Reset by Reset by POR Execution of WDT RAM parity illegal- LVD error memory Illegal Instruction TRAP bit access Set (1) Held Held Held Held WDTRF bit Held Set (1) Held Held Held RPERF bit Held Held Set (1) Held Held IAWRF bit Held Held Held Set (1) Held LVIRF bit Held Held Held Held Set (1) Cleared (0) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Cleared (0) 676 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT CHAPTER 19 POWER-ON-RESET CIRCUIT 19.1 Functions of Power-on-reset Circuit The power-on-reset circuit (POR) has the following functions. * Generates internal reset signal at power on. The reset signal is released when the supply voltage (VDD) exceeds 1.51 V 0.03 V. However, keep on the reset status until the operation voltage range shown in 28.4 AC Characteristics with the voltage detector or the external reset pin. * Compares supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.03 V), generates internal reset signal when VDD < VPDR. However, if the operation voltage drops, enter the STOP mode or execute areset with the voltage detector or the reset pin, before falling below the operation voltage range. Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and LVIRF flags of the reset control flag register (RESF) is cleared. Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that indicates the reset source is located in the reset control flag register (RESF) for when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. The RESF register is not cleared to 00H and the flag is set to 1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution, RAM parity error, or illegal-memory access. For details of the RESF register, see CHAPTER 18 RESET FUNCTION. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 677 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT 19.2 Configuration of Power-on-reset Circuit The block diagram of the power-on-reset circuit is shown in Figure 19-1. Figure 19-1. Block Diagram of Power-on-reset Circuit VDD VDD + Internal reset signal - Reference voltage source 19.3 Operation of Power-on-reset Circuit * An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPDR = 1.51 V 0.03 V), the reset status is released. However, keep on the reset status until the operation voltage range shown in 28.4 AC Characteristics with the voltage detector or the external reset pin * The supply voltage (VDD) and detection voltage (VPDR = 1.50 V 0.03 V) are compared. When VDD < VPDR, the internal reset signal is generated. However, if the operation voltage drops, enter the STOP mode or execute areset with the voltage detector or the reset pin, before falling below the operation voltage range. The timing of generation of the internal reset signal by the power-on-reset circuit and voltage detector is shown below. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 678 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (1/3) (1) When the external reset input via RESET pin is used <R> Supply voltage (VDD) Operating voltage range lower limit setting VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) 0V 10 s min. RESET signal Wait for oscillation Note 1 accuracy stabilization Wait for oscillation Note 1 accuracy stabilization High-speed on-chip oscillator clock (fIH) High-speed system clock (fMX) (when X1 oscillation is selected) CPU Starting oscillation is specified by software Reset processing time Note 3 by the external reset release Normal operation (high-speed on-chip oscillator clock)Note 2 Operation stops Starting oscillation is specified by software Reset period (oscillation stop) Voltage stabilization wait time 0.99 ms (TYP.), 2.30 ms (MAX.) Reset processing time by the external reset release Note 3 Normal operation (high-speed on-chip oscillator clock)Note 2 Operation stops Voltage stabilization wait time 0.99 ms (TYP.), 2.30 ms (MAX.) Internal reset signal Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 2. The high-speed on-chip oscillator clock can be switched to the high-speed system clock as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. <R> 3. The time until normal operation is started require the following "the reset processing time by the external reset release" required after RESET signal has been set to high-level(1), in addition to "the voltage stabilization wait time" required after the voltage has reached VPOR (1.51 V (TYP.)). Reset processing time by the external reset release: 0.672 ms (TYP.), 0.832 ms (MAX.) (When LVD is used) 0.399 ms (TYP.), 0.519 ms (MAX.) (When LVD off) Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 679 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector (2/3) (2) LVD interrupt & reset mode (option byte 000C1H/LVIMDS1, LVIMDS0 = 1, 0) <R> Supply voltage (VDD) VLVDH VLVDL Note 3 Operating voltage range lower limit setting VPOR= 1.51 V (TYP.) VPDR= 1.50 V (TYP.) 0V Wait for oscillation accuracy stabilization Note 2 High-speed on-chip oscillator clock (fIH) Starting oscillation is specified by software High-speed system clock (fMX) (when X1 oscillation is selected) CPU Wait for oscillation accuracy stabilization Note 2 Starting oscillation is specified by software Normal operation (High-speed on-chip oscillator clock)Note 1 Operation stops Reset processing time by LVD Note 4 Voltage stabilization wait time and reset processing time by POR 1.64 ms( TYP.), 3.10 msM (AX.) Reset period (oscillation stop) Normal operation (High-speed on-chip oscillator clock)Note 1 Operation stops Reset processing time by LVD Note 4 Voltage stabilization wait time and reset processing time by POR 1.64 ms( TYP.), 3.10 msM (AX.) Internal reset signal INTLVI Notes 1. The high-speed on-chip oscillator clock can be switched to the high-speed system clock as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. 2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 3. After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage detection level register (LVIS) are automatically set to 1. If the operating voltage returns to 1.8 V or higher without falling below the voltage detection level (VLVDL), after INTLVI is generated, perform the required backup processing, and then use software to specify the initial settings in order. (see Figure 20-8 Initial Setting of Interrupt and Reset Mode) <R> 4. The time until normal operation is started require the following "the reset processing time by LVD" required after the voltage has reached LVD detection level (VLVDH), in addition to "the reset processing time by POR" and "the voltage stabilization wait time" required after the voltage has reached VPOR (1.51 V (TYP.)). Reset processing time by LVD: 0 ms to 0.0701 ms (MAX.) Remark VLVDH, VLVDL: LVD detection voltage VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 680 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit <R> and Voltage Detector (3/3) (3) LVD reset mode (option byte 000C1H/LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (VDD) VLVD Operating voltage range lower limit setting VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) 0V Wait for oscillation accuracy stabilizationNote 2 Wait for oscillation accuracy stabil izationNote 2 Wait for oscillation accuracy stabilizationNote 2 High-speed on-chip oscillator clock (fIH) High-speed system clock (fMX) (when X1 oscillation is selected) CPU Normal operation (High-speed on-chip oscillator clock)Note 1 Operation stops Reset period (oscillation stop) Normal operation (High-speed on-chip oscillator clock)Note1 Reset period (oscillation stop) Reset processing time by LVD Note 3 Voltage stabilization wait time and Reset processing time by POR 1.64 ms (TYP.), 3.10 ms (MAX.) Reset processing time Note4 Normal operation (High-speed on-chip oscillator clock)Note 1 Operation stops Reset processing time by LVD Note 3 Voltage stabilization wait time and Reset processing time by POR 1.64 ms (TYP.), 3.10 ms (MAX.) Internal reset signal Notes 1. The high-speed on-chip oscillator clock can be switched to the high-speed system clock as the CPU clock. To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the lapse of the oscillation stabilization time. 2. The internal reset processing time includes the oscillation accuracy stabilization time of the high-speed onchip oscillator clock. 3. The time until normal operation is started require the following "the reset processing time by LVD" required after the voltage has reached LVD detection level (VLVD), in addition to "the reset processing time by POR" and "the voltage stabilization wait time" required after the voltage has reached VPOR (1.51 V (TYP.)). Reset processing time by LVD: 0 ms to 0.0701 ms (MAX.) 4. When supply voltage falls and returns after only an internal reset occurs by the voltage detection circuit (LVD), the following "the reset processing time by LVD" is required after the voltage has reached LVD detection level (VLVD). Reset processing time by LVD: 0.0629 ms (TYP.), 0.0701 ms (MAX.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 681 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT 19.4 Cautions for Power-on-reset Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POR detection voltage (VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action. <Action> After releasing the reset signal, wait for the supply voltage fluctuation period of each system by that uses a timer, and then initialize the ports. Figure 19-3. Example of Software Processing After Reset Release (1/2) (a) If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage Reset Initialization processing <1> ; Check the reset source, etc. Note 2 Power-on-reset Setting timer array unit (to measure 50 ms) ; fCLK = High-speed on-chip oscillator clock (4 MHz) Source: fMCK (4 MHz) /27, where comparison value = 789: Approx. 50 ms Timer starts (TS0n = 1). Clearing WDT Note 1 No 50 ms has passed? (TMIF0n = 1?) Yes Initialization processing <2> Notes 1. 2. Remark ; Initial setting for port. Setting of division ratio of system clock, such as setting of timer or A/D converter. If reset is generated again during this period, initialization processing <2> is not started. A flowchart is shown on the next page. n = 0 to 7 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 682 RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT Figure 19-3. Example of Software Processing After Reset Release (2/2) (b) Checking reset source Check reset source TRAP of RESF register = 1? Yes No Reset processing by illegal instruction execution Note WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer RPERF of RESF register = 1? Yes No Reset processing by RAM parity error IAWRF of RESF register = 1? Yes No Reset processing by illegal-memory access LVIRF of RESF register = 1? Yes No Reset processing by voltage detector Power-on-reset/external reset generated Note The illegal instruction is generated when instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 683 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR CHAPTER 20 VOLTAGE DETECTOR 20.1 Functions of Voltage Detector The voltage detector (LVD) has the following functions. * The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an internal reset or internal interrupt signal. * The detection level for the power supply detection voltage (VLVDH, VLVDL) can be selected by using the option byte as one of 12 levels (For details, see CHAPTER 23 OPTION BYTE). * Operable in STOP mode. * The following three operation modes can be selected by using the option byte. (a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0) For the two detection voltages selected by the option byte 000C1H, the high-voltage detection level (VLVDH) is used for generating interrupts and ending resets, and the low-voltage detection level (VLVDL) is used for triggering resets. (b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1) The detection voltage (VLVD) selected by the option byte 000C1H is used for triggering and ending resets. (c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1) The detection voltage (VLVD) selected by the option byte 000C1H is used for generating interrupts/reset release. Two detection voltages (VLVDH, VLVDL) can be specified in the interrupt & reset mode, and one (VLVD) can be specified in the reset mode and interrupt mode. The reset and interrupt signals are generated as follows according to the option byte (LVIMDS0, LVIMDS1) selection. Interrupt & reset mode Reset mode Interrupt mode (LVIMDS1, LVIMDS0 = 1, 0) (LVIMDS1, LVIMDS0 = 1, 1) (LVIMDS1, LVIMDS0 = 0, 1) Generates an internal interrupt signal Generates an internal reset signal when when VDD < VLVDH, and an internal reset VDD < VLVD and releases the reset signal when VDD drops lower than VLVD (VDD < when VDD < VLVDL. when VDD VLVD. VLVD) or when VDD becomes VLVD or Generates an internal interrupt signal Releases the reset signal when VDD higher VLVDH. (VDD VLVD). Releases the reset signal when VDD VLVD at power on. While the voltage detector is operating, whether the supply voltage is more than or less than the detection level can be checked by reading the voltage detection flag (LVIF: bit 0 of the voltage detection register (LVIM)). Bit 0 (LVIRF) of the reset control flag register (RESF) is set to 1 if reset occurs. For details of the RESF register, see CHAPTER 18 RESET FUNCTION. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 684 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.2 Configuration of Voltage Detector The block diagram of the voltage detector is shown in Figure 20-1. Figure 20-1. Block Diagram of Voltage Detector VDD VDD VLVDH VLVDL Option byte (000C1H) LVIS1, LVIS0 Controller Internal reset signal + Selector Voltage detection level selector N-ch - INTLVI Reference voltage source LVIF LVIOMSK LVISEN Option byte (000C1H) VPOC2 to VPOC0 Voltage detection register (LVIM) LVIMD LVILV Voltage detection level register (LVIS) Internal bus 20.3 Registers Controlling Voltage Detector The voltage detector is controlled by the following registers. * Voltage detection register (LVIM) * Voltage detection level register (LVIS) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 685 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.3.1 Voltage detection register (LVIM) This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as well as to check the LVD output mask status. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 20-2. Format of Voltage Detection Register (LVIM) Address: FFFA9H After reset: Note 1 R/W Note 2 Symbol <7> 6 5 4 3 2 <1> <0> LVIM LVISEN 0 0 0 0 0 LVIOMSK LVIF LVISEN Specification of whether to enable or disable rewriting the voltage detection level register (LVIS) 0 Disabling rewriting 1 Enabling rewriting Note 3 LVIOMSK Mask status flag of LVD output 0 Mask is invalid 1 Mask is valid Notes 3, 4 LVIF Notes 1. Voltage detection flag 0 Supply voltage (VDD) detection voltage (VLVD), or when LVD operation is disabled 1 Supply voltage (VDD) < detection voltage (VLVD) The reset value changes depending on the reset source. If the LVIS register is reset by LVD, it is not reset but holds the current value. The value of this LVISEN is reset to "0" if a reset other than by LVD is effected. 2. Bits 0 and 1 are read-only. 3. This can only be used when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the option byte (other mode is invalid). 4. LVIOMSK bit is automatically set to "1" in the following periods and reset or interruption by LVD is masked. * Period during LVISEN = 1 * Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes stable * Waiting period from the time when the value of LVILV bit changes until LVD detection voltage becomes stable R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 686 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.3.2 Voltage detection level register (LVIS) This register selects the voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H/01H/81H Note 1 . Figure 20-3. Format of Voltage Detection Level Select Register (LVIS) Address: FFFAAH After reset: 00H/01H/81H Note 1 R/W Symbol <7> 6 5 4 3 2 1 <0> LVIS LVIMD 0 0 0 0 0 0 LVILV LVIMD Note Operation mode of voltage detection 2 0 Interrupt mode 1 Reset mode LVILV Notes 1. Note 2 LVD detection level 0 High-voltage detection level (VLVDH) 1 Low-voltage detection level (VLVDL or VLVD) The reset value changes depending on the reset source and the setting of the option byte. This register is not cleared (00H) by LVD reset. The generation of reset signal other than an LVD reset sets as follows. * When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H * When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H * When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H 2. Writing "0" can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically when reset or interrupt is generated. Cautions 1. 2. Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register) to 1. Specify the LVD operation mode and detection voltage (VLVDH, VLVDL) by using the option byte (000C1H). Table 20-1 shows the option byte (000C1H) settings. For details about the option byte, see CHAPTER 23 OPTION BYTE. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 687 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (1/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0 * When used as interrupt & reset mode Detection voltage VLVDH Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 0 Rising Falling Falling edge edge edge 1.98 V 1.94 V 1.84 V 2.09 V 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.55 V 1 0 2.71 V 2.65 V 0 1 3.75 V 3.67 V 0 0 2.92 V 2.86 V 1 0 3.02 V 2.96 V 0 1 4.06 V 3.98 V 0 0 LVIMDS1 LVIMDS0 1 0 2.45 V 1 2.75 V Other than above 0 1 1 Setting prohibited * When used as reset mode Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.88 V 1.84 V 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.45 V 1 0 1 1 2.61 V 2.55 V 1 0 1 0 2.71 V 2.65 V 1 0 0 1 2.81 V 2.75 V 1 1 1 1 2.92 V 2.86 V 1 1 1 0 3.02 V 2.96 V 1 1 0 1 3.13 V 3.06 V 0 1 0 0 3.75 V 3.67 V 1 0 0 0 4.06 V 3.98 V 1 1 0 0 Other than above R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Setting prohibited 688 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (2/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0 * When used as interrupt mode Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.88 V 1.84 V 0 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.45 V 1 0 1 1 2.61 V 2.55 V 1 0 1 0 2.71 V 2.65 V 1 0 0 1 2.81 V 2.75 V 1 1 1 1 2.92 V 2.86 V 1 1 1 0 3.02 V 2.96 V 1 1 0 1 3.13 V 3.06 V 0 1 0 0 3.75 V 3.67 V 1 0 0 0 4.06 V 3.98 V 1 1 0 0 VPOC1 VPOC0 LVIS1 LVIS0 x x x x Other than above Setting prohibited * When LVDOFF Detection voltage Option byte Setting Value VLVDH Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 VPOC2 - - x 1 1 Caution To set the LVD off, execute the external reset when the power supply is turned on, and then release the reset in the operation voltage range. HS (high-speed main) mode: VDD = 2.7 to 5.5 V@1 to 24 MHz VDD = 2.4 to 5.5 V@1 to 16 MHz LS (low-speed main) mode: Remark VDD = 1.8 to 5.5 V@1 to 8 MHz x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 689 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.4 Operation of Voltage Detector 20.4.1 When used as reset mode * When starting operation Start in the following initial setting state. Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. * Clear bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H. Bit 7 (LVIMD) is 1 (reset mode). Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD). Figure 20-4 shows the timing of the internal reset signal generated by the voltage detector. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 690 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Figure 20-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) Supply voltage (VDD) VLVD VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time Cleared LVIF flag LVIMD flag H Not cleared Not cleared LVILV flag H Not cleared Not cleared Cleared LVIRF flag (RESF register) LVD reset signal Cleared by software Cleared by software POR reset signal Internal reset signal Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 691 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.4.2 When used as interrupt mode * When starting operation Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD) by using the option byte 000C1H. Start in the following initial setting state. * Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 is clear to 0 and LVIMDS0 is set to 1, the initial value of the LVIS register is set to 00H. Bit 7 (LVIMD) is 0 (interrupt mode). Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD). Figure 20-5 shows the timing of the internal interrupt signal generated by the voltage detector. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 692 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Figure 20-5. Timing of Voltage Detector Internal Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 0, 1) Supply voltage (VDD) VLVD VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time LVIMK flag HNote (set by software) Cleared by software Cleared LVIF flag LVIMD flag LILV flag H INTLVI LVIIF flag LVD reset signal POR reset signal Internal reset signal Note The LVIMK flag is set to "1" by reset signal generation. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 693 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.4.3 When used as interrupt and reset mode * When starting operation Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage (VLVDH, VLVD) by using the option byte 000C1H. Start in the following initial setting state. * Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level register (LVIS)) * When the option byte LVIMDS1 is set to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is set to 00H. Bit 7 (LVIMD) is 0 (interrupt mode). Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH). Figure 20-6 shows the timing of the internal reset signal and interrupt signal generated by the voltage detector. Perform the processing according to Figure 20-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode and Figure 20-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 694 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Figure 20-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2) If a reset is not generated after releasing the mask, determine that a condition of VDD becomes VDD VLVDH, clear LVIMD bit to 0, and the MCU shift to normal operation. Supply voltage (VDD) VLVDH VLVDL VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time LVIMK flag (set by software) H Note 1 Cleared by Normal software operation Cleared by software Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3 { Operation status RESET Normal operation Save processing Normal operation Save processing RESET RESET Cleared LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag LVIRF flag Cleared by software Note 2 Cleared LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag (Notes and Remark are listed on the next page.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 695 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR Figure 20-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2) When a condition of VDD is VDD < VLVDH after releasing the mask, a reset is generated because of LVIMD = 1 (reset mode). Supply voltage (VDD) VLVDH VLVDL VPOR = 1.51 V (TYP.) VPDR = 1.50 V (TYP.) Time LVIMK flag (set by software) H Note 1 Cleared by software Operation status RESET Save Normal operation processing Cleared by software Wait for stabilization by software (400 s or 5 clocks of fIL) Note 3 RESET Normal operation RESET Save processing Cleared LVIF flag LVISEN flag (set by software) LVIOMSK flag LVIMD flag Cleared by software Note 3 LVILV flag LVIRF flag Cleared by software Note 2 Cleared LVD reset signal POR reset signal Internal reset signal INTLVI LVIIF flag (Notes and Remark are listed on the next page.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 696 RL78/G12 Notes 1. 2. CHAPTER 20 VOLTAGE DETECTOR The LVIMK flag is set to "1" by reset signal generation. After an interrupt is generated, perform the processing according to Figure 20-7 Processing Procedure After an Interrupt Is Generated in interrupt and reset mode. 3. After a reset is released, perform the processing according to Figure 20-8 Initial Setting of Interrupt and Reset Mode in interrupt and reset mode. Remark VPOR: POR power supply rise detection voltage VPDR: POR power supply fall detection voltage Figure 20-7. Processing Procedure After an Interrupt Is Generated INTLVI generated Save processing LVISEN = 1 LVILV = 0 LVISEN = 0 No Perform required save processing. Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1). Set the LVILV bit to 0 to set the high-voltage detection level (VLVDH). Set the LVISEN bit to 0 to enable voltage detection. LVIOMSK = 0 Yes Yes LVD reset generated No Reset R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 The MCU returns to normal operation when internal reset by voltage detector (LVD) is not generated, since a condition of VDD becomes VDD VLVDH. LVISEN = 1 Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) LVIMD = 0 Set the LVIMD bit to 0 to set interrupt mode. LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection. Normal operation 697 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400 s or 5 clocks of fIL is necessary after LVD reset is released (LVIRF = 1). After waiting until voltage detection stabilizes, (0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD. Figure 20-8. shows the procedure for initial setting of interrupt and reset mode. Figure 20-8 Initial Setting of Interrupt and Reset Mode Power application Reset source determine Refer to Figure 20-9. Checking reset source. LVIRF = 1? Check internal reset generation by LVD circuit No Yes LVISEN = 1 Voltage detection stabilization Set the LVISEN bit to 1 to mask voltage detection (LVIOMSK = 1) Count 400 s or 5 clocks of fIL by software. wait time LVIMD = 0 Set the LVIMD bit to 0 to set interrupt mode. LVISEN = 0 Set the LVISEN bit to 0 to enable voltage detection. Normal operation Remark fIL: Low-speed on-chip oscillator clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 698 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR 20.5 Cautions for Voltage Detector (1) Checking reset source When a reset occurs, check the reset source by using the following method. Figure 20-9. Checking reset source Check reset source TRAP of RESF register = 1? Yes No Reset processing by illegal instruction execution Note WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer RPERF of RESF register = 1? Yes No Reset processing by RAM parity error IAWRF of RESF register = 1? Yes No Reset processing by illegal-memory access LVIRF of RESF register = 1? No Yes Power-on-reset/external reset generated Reset processing by voltage detector Note When instruction code FFH is executed. Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug emulator. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 699 RL78/G12 CHAPTER 20 VOLTAGE DETECTOR (2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has been generated. In the same way, there is also some delay from the time LVD detection voltage (VLVD) supply voltage (VDD) until the time LVD reset has been released (see Figure 20-10). Figure 20-10. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released Supply voltage (VDD) VLVD Time <1> <1> LVD reset signal <1>: Detection delay (300 s (MAX.)) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 700 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS CHAPTER 21 SAFETY FUNCTIONS 21.1 Overview of Safety Functions The following safety functions are provided in the RL78/G12 to comply with the IEC60730 and IEC61508 safety standards. These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is detected. (1) Flash memory CRC operation function This detects data errors in the flash memory by performing CRC operations. This can be used for checking various data in addition to the code flash memory area while the CPU is running. <R> <R> This function is available in the R5F102 products. (2) RAM parity error detection function This detects parity errors when reading RAM is read. (3) RAM guard function This prevents RAM data from being rewritten when the CPU freezes. <R> This function is available in the R5F102 products. (4) SFR guard function This prevents SFRs from being rewritten when the CPU freezes. <R> This function is available in the R5F102 products. (5) Invalid memory access detection function This detects illegal accesses to invalid memory areas (such as areas where no memory is allocated and areas to which access is restricted). (6) Frequency detection function This uses TAU to detect the oscillation frequency. (7) A/D test function This is used to perform a self-check of A/D conversion by performing A/D conversion on the internal reference voltage. Remark See the application note (R01AN0749) for the features required to comply with the IEC60730 standards. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 701 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.2 Registers Used by Safety Functions The safety functions use the following registers for each function. Register * CRC input register (CRCIN) * CRC data register (CRCD) Each Function of Safety Function Note CRC operation function Note (general-purpose CRC) * RAM parity error control register (RPECTL) RAM parity error detection function * Invalid memory access detection control register (IAWCTL) RAM guard function SFR guard function Invalid memory access detection function <R> * Timer input select register 0 (TIS0) Frequency detection function * A/D test register (ADTES) A/D test function Note Integrated in the R5F102 products. 21.3 Operation of Safety Functions 21.3.1 CRC operation function (general-purpose CRC) In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the CPU is operating. In the RL78/G12, a general CRC operation can be executed as a peripheral function while the CPU is operating. The general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked can be specified by using software (a user-created program). CRC calculation function in the HALT mode can be used only during the DMA transmission The CRC generator polynomial used is "X16 + X12 + X5 + 1" of CRC-16-CCITT. The data to be input is inverted in bit order and then calculated to allow for LSB-first communication. For example, if the data 12345678H is sent from the LSB, values are written to the CRCIN register in the order of 78H, 56H, 34H, and 12H, enabling a value of 08F6H to be obtained from the CRCD register. This is the result obtained by executing a CRC operation on the bit rows shown below, which consist of the data 12345678H inverted in bit order. CRCIN setting data 78H Bit representation data 0111 1000 56H 34H 12H 0101 0110 0011 0100 0001 0010 Bit reverse Bit reverse data 0001 1110 0110 1010 0010 1100 0100 1000 Operation with polynomial Result data 0110 1111 0001 0000 Bit reverse CRCD data 0000 1000 1111 0110 Obtained result (08F6H) Caution Because the debugger rewrites the software break setting line to a break instruction during program execution, the CRC operation result differs if a software break is set in the CRC operation target area. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 702 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS <Control register> (1) CRC input register (CRCIN) CRCIN register is an 8-bit register that is used to set the CRC operation data. The possible setting range is 00H to FFH. The CRCIN register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-1. Format of CRC Input Register (CRCIN) Address: FFFACH Symbol After reset: 00H 7 R/W 6 5 4 3 2 1 0 CRCIN Bits 7 to 0 Function 00H to FFH Data input. (2) CRC data register (CRCD) This register is used to store the CRC operation result. The setting range is 0000H to FFFFH. After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC operation result is stored to the CRCD register. The CRCD register can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Figure 21-2. Format of CRC Data Register (CRCD) Address: F02FAH Symbol 15 After reset: 0000H 14 13 12 R/W 11 10 9 8 7 6 5 4 3 2 1 0 CRCD Cautions 1. Read the value written to CRCD register before writing to CRCIN register. 2. If conflict between writing and storing operation result to CRCD register occurs, the writing is ignored. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 703 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS <Operation flow> Figure 21-3. CRC Operation Function (General-Purpose CRC) START ; Store the start and end addresses in a Specify the start and end addresses Write CRCD register to 0000H Read data Store data to CRCIN register ; general-purpose register. ; Initialize CRCD register ; Read 8-bit data of corresponding address ; Execute CRC calculation for 8-bit data Address+1 Last address? Yes No 1 clock wait (fCLK) Read CRCD register ; Get CRC result End R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 ; Compare the value ; with the stored ; expected value and ; make sure that the ; values match. 704 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.3.2 RAM parity error detection function The IEC60730 standard mandates the checking of RAM data. A single-bit parity bit is therefore added to all 8-bit data in the RL78/G12's RAM. By using this RAM parity error detection function, the parity bit is appended when data is written, and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error occurs. <Control register> * RAM parity error control register (RPECTL) This register is used to control parity error generation check bit and reset generation due to parity errors. The RPECTL register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-4. Format of RAM Parity Error Control Register (RPECTL) Address: F00F5H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 <0> RPECTL RPERDIS 0 0 0 0 0 0 RPEF RPERDIS Parity error reset mask flag 0 Enable parity error resets. 1 Disable parity error resets. RPEF <R> Parity error status flag 0 No parity error has occurred. 1 A parity error has occurred. Caution The parity bit is appended when data is written, and the parity is checked when the data is read. Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data access is to proceed before reading data. The RL78's CPU executes look-ahead due to the pipeline operation, the CPU might read an uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error. Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area + 10 bytes when instructions are fetched from RAM areas. When using the self-programming function while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area to overwrite + 10 bytes before overwriting. Remarks 1. The RAM parity check is always on, and the result can be confirmed by checking the PREF flag. 2. The parity error reset is enabled by default (RPERDIS = 0). Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error occurs. 3. The RPEF flag is set (1) by RAM parity errors and cleared (0) by writing 0 to it or by any reset source. When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 705 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.3.3 RAM guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important data stored in the RAM be protected, even if the CPU freezes. This RAM guard function is used to protect data in the specified memory space. If the RAM guard function is specified, writing to the specified RAM space is disabled, but reading from the space can be carried out as usual. <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. GRAM1 and GRAM0 bits are used in RAM guard function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-5. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC GRAM1 GRAM0 0 0 Disabled. RAM can be written to. 0 1 The 128 bytes starting at the beginning RAM address 1 0 The 256 bytes starting at the beginning RAM address 1 1 The 512 bytes starting at the beginning RAM address (setting prohibited for R5F10266, RAM guard space Note R5F10366) Note The RAM start address differs depending on the size of the RAM provided with the product. Furthermore, the general-purpose register area (FFEE0H to FFEFFH) is not guarded. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 706 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.3.4 SFR guard function In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from being overwritten, even if the CPU freezes. This SFR guard function is used to protect data in the control registers used by the port function, interrupt function, clock control function, voltage detection function, and RAM parity error detection function. If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be carried out as usual. <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. GPORT, GINT and GCSC bits are used in SFR guard function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-6. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC GPORT Control registers of port function guard 0 Disabled. Control registers of port function can be read or written to. 1 Enabled. Writing to control registers of port function is disabled. Reading is enabled. [Guarded SFR] PMxx, PUxx, PIMxx, POMxx, PMCxx, ADPC, PIOR GINT Note 1 Registers of interrupt function guard 0 Disabled. Registers of interrupt function can be read or written to. 1 Enabled. Writing to registers of interrupt function is disabled. Reading is enabled. [Guarded SFR] IFxx, MKxx, PRxx, EGPx, EGNx GCSC 0 Notes 2 Control registers of clock control function, voltage detector and RAM parity error detection function guard Disabled. Control registers of clock control function, voltage detector and RAM parity error detection function can be read or written to. 1 Enabled. Writing to control registers of clock control function, voltage detector and RAM parity error detection function is disabled. Reading is enabled. [Guarded SFR] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL Notes 1. 2. Pxx (Port register) is not guarded. Clear GCSC bit to 0, during self programming /serial programming. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 707 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.3.5 Invalid memory access detection function The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly. The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is accessed. The illegal memory access detection function applies to the areas indicated by NG in Figure 21-7. Figure 21-7. Invalid access detection area Possibility access Read Write Fetching instructions (execute) FFFFFH Special function register (SFR) 256 byte FFF00H FFEFFH FFEE0H FFEDFH NG General-purpose register 32 byte OK RAMNote OK yyyyyH Reserved F4000H F3FFFH OK Mirror F2000H F1FFFH NG NG Reserved F1800H F17FFH Data flash memory F1000H F0FFFH Reserved OK F0800H F07FFH OK Special function register (2nd SFR) 2 Kbyte NG F0000H EFFFFH OK EF000H EEFFFH NG Reserved NG NG 10000H 0FFFFH xxxxxH OK OK Code flash memoryNote 00000H Note Code flash memory and RAM address of each product are as follows. Products (x = 2, 3) Code flash memory RAM (00000H to xxxxxH) (yyyyyH to FFEFFH) R5F10x66 2048 x 8 bit (00000H to 007FFH) 256 x 8 bit (FFE00H to FFEFFH) R5F10x67, R5F10x77, R5F10xA7 4096 x 8 bit (00000H to 00FFFH) 512 x 8 bit (FFD00H to FFEFFH) R5F10x68, R5F10x78, R5F10xA8 8192 x 8 bit (00000H to 01FFFH) 768 x 8 bit (FFC00H to FFEFFH) R5F10x69, R5F10x79, R5F10xA9 12288 x 8 bit (00000H to 02FFFH) 1024 x 8 bit (FFB00H to FFEFFH) R5F10x6A, R5F10x7A 16384 x 8 bit (00000H to 03FFFH) 1536 x 8 bit (FF900H to FFEFFH) R5F10xAA R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 2048 x 8 bit (FF700H to FFEFFH) 708 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS <Control register> * Invalid memory access detection control register (IAWCTL) This register is used to control the detection of invalid memory access and RAM/SFR guard function. IAWEN bit is used in invalid memory access detection function. The IAWCTL register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-8. Format of Invalid Memory Access Detection Control Register (IAWCTL) Address: F0078H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC IAWEN Note Note Control of invalid memory access detection 0 Disable the detection of invalid memory access. 1 Enable the detection of invalid memory access. Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1. Remark By specifying WDTON = 1 for the option byte (watchdog timer operation enable), the invalid memory access detection function is enabled even IAWEN = 0. 21.3.6 Frequency detection function The IEC60730 standard mandates checking that the oscillation frequency is correct. The frequency detection function can detect whether the clock is operating on an abnormal frequency by comparing the internal high-speed on-chip oscillation clock or external X1 oscillation clock with the internal low-speed on-chip oscillation clock (15 kHz). Figure 21-9. Configuration of Frequency Detection Function High-speed on-chip X1 X1 oscillator X2 (fMX) Selector ossiratopr (fIH) fCLK Selector TI05 Timer array unit 0 (TAU0) Low-speed on-chip oscillator (fIL = 15 kHz) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 709 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS <Operation > Whether the clock frequency is correct or not can be judged by measuring the pulse interval under the following conditions: * The internal high-speed oscillation clock (fIH) or the external X1 oscillation clock (fMX) is selected as the CPU/peripheral hardware clock (fCLK). * The internal low-speed oscillation clock (fIL: 15 kHz) is selected as the timer input for channel 5 of timer array unit 0 (TAU0). If pulse interval measurement results in an abnormal value, it can be concluded that the clock frequency is abnormal. For how to execute pulse interval measurement, see 6.7.4 Operation as input pulse interval measurement. <Control register> * Timer input select register 0 (TIS0) This register is used to select the timer input of channel 5 by 20- and 24-pin products. By selecting the low-speed on-chip oscillation clock for the timer input, its pulse width can be measured to determine whether the proportional relationship between the low-speed on-chip oscillator clock and the timer operation clock is correct. The TIS0 register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-10. Format of Timer Input Select Register 0 (TIS0) Address: F0074H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TIS0 0 0 0 0 0 0 TIS01 TIS00 TIS01 TIS00 x 0 Input signal of timer input pin (TI01) 0 1 Low-speed on-chip oscillator clock (fIL) 1 1 Setting prohibited Remark Selection of timer input used with channel 1 x: don't care R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 710 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS 21.3.7 A/D test function The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D converter is operating normally by executing A/D conversions of an internal voltage of 0 V, the AVREF voltage, and the internal reference voltage (1.45 V). Figure 21-11. Configuration of A/D Test Function VDD ANI0/AVREFP + side reference voltage source (AVREF+) ANI1/AVREFM ANIx ANIx A/D convertor Temperature sensor - side reference voltage source (AVREF-) Internal reference voltage (1.45 V) VSS <Control register> (1) A/D test register (ADTES) This register is used to select the A/D converter's positive reference voltage AVREFP, the A/D converter's negative reference voltage AVREFM, or the analog input channel (ANIxx) as the target of A/D conversion. When using the A/D test function, specify the following settings: * Select AVREFM as the target of A/D conversion when converting the internal 0 V. * Select AVREFP as the target of A/D conversion when converting AVREF. The ADTES register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 711 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS Figure 21-12. Format of A/D Test Register (ADTES) Address: F0013H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADTES 0 0 0 0 0 0 ADTES1 ADTES0 ADTES1 ADTES0 A/D conversion target 0 0 ANIxx / temperature sensor output / internal reference voltage (1.45 V) (This is specified Note using the analog input channel specification register (ADS).) 1 0 AVREFM 1 1 AVREFP Other than the above Setting prohibited Note Temperature sensor output/internal reference voltage (1.45 V) can be used only in HS (high-speed main) mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 712 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS (2) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference voltage (1.45 V). The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 21-16. Format of Analog Input Channel Specification Register (ADS) (1/2) Address: FFF31H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0 Select mode (ADMD = 0) Note1 ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input channel Input source 0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin 0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin 0 0 0 0 1 0 ANI2 P22/ANI2 pin 0 0 0 0 1 1 ANI3 P23/ANI3 pin 0 1 0 0 0 0 ANI16 P10/ANI16 pin P01/ANI16 pin 0 1 0 0 0 1 ANI17 P11/ANI17 pin P00/ANI17 pin 0 1 0 0 1 0 ANI18 0 1 0 0 1 1 ANI19 0 1 0 1 0 0 ANI20 P12/ANI18 pin P147/ANI18 pin P13/ANI19 pin P120/ANI19 pin P14/ANI20 pin - 0 1 0 1 0 1 ANI21 P42/ANI21 pin - 0 1 0 1 1 0 ANI22 P41/ANI22 pin - 1 0 1 0 0 0 0 0 0 0 2. - 1 Other than the above Notes 1. - 0 Temperature sensor output Note 2 Internal reference voltage Note 2 output (1.45 V) Setting prohibited Upper: 20-, 24-pin products, lower: 30 pin products This setting can be used only in HS (high-speed main) mode. Cautions 1. Be sure to clear bits 5 and 6 to 0. 2. Only rewrite the value of the ADISS bit while A/D voltage comparator operation is stopped (which is indicated by the ADCE bit of A/D converter mode register 0 (ADM0) being 0). 3. If using AVREFP as the + side reference voltage source (AVREF+) of the A/D converter, do not select ANI0 as an A/D conversion channel. 4. If using AVREFM as the - side reference voltage source (AVREF-) of the A/D converter, do not select ANI1 as an A/D conversion channel. 5. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side reference voltage source (AVREF+). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 713 RL78/G12 CHAPTER 21 SAFETY FUNCTIONS < Check of analog multiplexer > The analog multiplexer can be checked using the following procedure. (1) Perform A/D conversion for the ANIx pin (conversion result 1). (2) Select AVREFM using the ADTES register, perform A/D conversion, and then set the voltage potential difference between the terminals of the sampling capacitor of the A/D converter to 0 V. (3) Perform A/D conversion for the ANIx pin (conversion result 2). (4) Select AVREFP using the ADTES register, perform A/D conversion, and then set the voltage potential difference between the terminals of the sampling capacitor of the A/D converter to AVREF. (5) Perform A/D conversion for the ANIx pin (conversion result 3). (6) Make sure that conversion results 1, 2, and 3 are equal. Using the procedure above can confirm that the analog multiplexer is selected and all wiring is connected. Remarks 1. If the analog input voltage is variable during A/D conversion in steps <1> to <5> above, use another method to check the analog multiplexer. 2. The conversion results might contain an error. Consider an appropriate level of error when comparing the conversion results. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 714 RL78/G12 CHAPTER 22 REGULATOR CHAPTER 22 REGULATOR 22.1 Overview of Regulators The 30-pin product of the RL78/G12 incorporates the circuit for constant voltage operation in the device. To stabilize the regulator output, connect the REGC pin to Vss via a capacitor (0.47 to 1 F) for regulator stabilization. Use a capacitor with good characteristics because it is used for stabilization of internal voltage. Caution Keep the wiring length as short as possible for the broken-line part in the above figure. The regulator output voltage, see table 22-1. Table 22-1. Regulator Output Voltage Conditions Mode Output Condition voltage LS (low-speed - 1.8 V main) mode HS (high-speed 1.8 V In the STOP mode main) mode 2.1 V Other than STOP mode (include during OCD mode) Note Note When it shifts to the subsystem clock operation or STOP mode during the on-chip debugging, the regulator output voltage is kept at 2.1 V (not decline to 1.8 V). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 715 RL78/G12 CHAPTER 23 OPTION BYTE CHAPTER 23 OPTION BYTE 23.1 Functions of Option Bytes Addresses 000C0H to 000C3H of the flash memory of the RL78/G12 form an option byte area. Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H). Upon power application or resetting and starting, an option byte is automatically referenced and a specified function is set. When using the product, be sure to set the following functions by using the option bytes. <R> For the bits to which no function is allocated, be sure to set the value specified in this manual. 23.1.1 User option byte (000C0H to 000C2H) (1) 000C0H Operation of watchdog timer * Operation is stopped or enabled in the HALT or STOP mode. Setting of interval time of watchdog timer Operation of watchdog timer * Operation is stopped or enabled. Setting of window open period of watchdog timer Setting of interval interrupt of watchdog timer * Used or not used (2) 000C1H Setting of LVD operation mode * Interrupt & reset mode. * Reset mode. * Interrupt mode. Setting of LVD detection level (VLVDH, VLVDL, VLVD) Controlling of P125/RESET pin * P125/KR1/SI01 or RESET (3) 000C2H Setting of flash operation mode * LS (low speed main) mode * HS (high speed main) mode Setting of the frequency of the high-speed on-chip oscillator * Select from 1 to 24 MHz. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 716 RL78/G12 CHAPTER 23 OPTION BYTE 23.1.2 On-chip debug option byte (000C3H) Control of on-chip debug operation * On-chip debug operation is disabled or enabled. Handling of data of flash memory in case of failure in on-chip debug security ID authentication * Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 717 RL78/G12 CHAPTER 23 OPTION BYTE 23.2 Format of User Option Byte The format of user option byte is shown below. Figure 23-1. Format of User Option Byte (000C0H) Address: 000C0H 7 6 5 4 3 2 1 0 WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON WDTINIT Use of interval interrupt of watchdog timer 0 Interval interrupt is not used. 1 Interval interrupt is generated when 75% + 1/2 fIL of the overflow time is reached. WINDOW1 WINDOW0 Watchdog timer window open period 0 0 Setting prohibited 0 1 50% 1 0 75% 1 1 100% WDTON Operation control of watchdog timer counter 0 Counter operation disabled (counting stopped after reset) 1 Counter operation enabled (counting started after reset) WDCS2 Note WDCS1 WDCS0 Watchdog timer overflow time (fIL = 17.25 kHz (MAX.)) 6 0 0 0 2 /fIL (3.71 ms) 0 0 1 2 /fIL (7.42 ms) 0 1 0 2 /fIL (14.84 ms) 0 1 1 2 /fIL (29.68 ms) 1 0 0 2 /fIL (118.72 ms) 1 0 1 2 /fIL (474.90 ms) 1 1 0 2 /fIL (949.80 ms) 1 1 1 2 /fIL (3799.19m s) WDSTBYON 7 8 9 11 13 14 16 Operation control of watchdog timer counter (HALT/STOP mode) 0 Counter operation stopped in HALT/STOP mode 1 Counter operation enabled in HALT/STOP mode Note Note The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and WINDOW0 bits. <R> Caution The watchdog timer continues its operation even during self-programming or data flash rewrite. During processing, the interrupt acknowledge time is delayed. Set the overflow time and window size taking this delay into consideration. Remark fIL: Low-speed on-chip oscillator clock frequency R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 718 RL78/G12 CHAPTER 23 OPTION BYTE Figure 23-2. Format of User Option Byte (000C1H) (1/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt mode & reset mode) Detection voltage Option byte Setting Value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 0 2.04 V 0 1 3.13 V 3.06 V 0 0 2.61 V 2.55 V 1 0 2.71 V 2.65 V 0 1 3.75 V 3.67 V 0 0 2.92 V 2.86 V 1 0 3.02 V 2.96 V 0 1 4.06 V 3.98 V 0 0 VLVDH VLVDL Rising Falling Falling edge edge edge 1.98 V 1.94 V 1.84 V 2.09 V Mode setting LVIMDS1 LVIMDS0 1 0 2.45 V 1 2.75 V Other than above 0 1 1 Setting prohibited * LVD setting (reset mode) Detection voltage Option byte Setting Value VLVD Mode setting VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 1 Rising edge Falling edge LVIMDS1 LVIMDS0 1.88 V 1.84 V 1 1 1.98 V 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.45 V 1 0 1 1 2.61 V 2.55 V 1 0 1 0 2.71 V 2.65 V 1 0 0 1 2.81 V 2.75 V 1 1 1 1 2.92 V 2.86 V 1 1 1 0 3.02 V 2.96 V 1 1 0 1 3.13 V 3.06 V 0 1 0 0 3.75 V 3.67 V 1 0 0 0 4.06 V 3.98 V 1 1 0 0 Other than above Setting prohibited R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 719 RL78/G12 CHAPTER 23 OPTION BYTE Figure 23-2. Format of User Option Byte (000C1H) (2/2) Address: 000C1H 7 6 5 4 3 2 1 0 VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0 * LVD setting (interrupt mode) Detection voltage Option byte Setting Value VPOC2 VPOC1 VPOC0 LVIS1 LVIS0 0 0 1 1 1 1.94 V 0 1 1 0 2.09 V 2.04 V 0 1 0 1 2.50 V 2.45 V 1 0 1 1 2.61 V 2.55 V 1 0 1 0 2.71 V 2.65 V 1 0 0 1 2.81 V 2.75 V 1 1 1 1 2.92 V 2.86 V 1 1 1 0 3.02 V 2.96 V 1 1 0 1 3.13 V 3.06 V 0 1 0 0 3.75 V 3.67 V 1 0 0 0 4.06 V 3.98 V 1 1 0 0 VPOC1 VPOC0 LVIS1 LVIS0 x x x x VLVD Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 1.88 V 1.84 V 0 1 1.98 V Other than above Remark Setting prohibited Refer to LVD setting, see 20.1 Functions of Voltage Detector. * Setting of LVDOFF Detection voltage Option byte Setting Value VLVD Mode setting Rising edge Falling edge LVIMDS1 LVIMDS0 VPOC2 - - x 1 1 Caution To set the LVD off, execute the external reset when the power supply is turned on, and then release the reset in the operation voltage range. HS (high-speed main) mode: VDD = 2.7 to 5.5 V@1 to 24 MHz VDD = 2.4 to 5.5 V@1 to 16 MHz LS (low-speed main) mode: VDD = 1.8 to 5.5 V@1 to 8 MHz Remark <R> x: don't care * Setting of the P125 (20-, 24-pin products) PORTSELB <R> P125/RESET pin control 0 Port function (P125/KR1/SI01) 1 RESET input (PU125 is set to 1 and internal pull-up resistor can be connected.) Caution In the 30-pin products, be sure to set bit 4 (PORTSELB) to 1. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 720 RL78/G12 CHAPTER 23 OPTION BYTE Figure 23-3. Format of Option Byte (000C2H) Address: 000C2H 7 6 5 4 3 2 1 0 CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 CMODE1 CMODE0 Setting of flash operation mode Operating Frequency Range Range 1 0 LS (low speed main) mode 1 to 8 MHz 1.8 to 5.5 V 1 1 HS (high speed main) mode 1 to 16 MHz 2.4 to 5.5 V 1 to 24 MHz 2.7 to 5.5 V Other than above Setting prohibited FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 0 0 0 0 24 MHz 1 0 0 1 16 MHz 0 0 0 1 12 MHz 1 0 1 0 8 MHz 1 0 1 1 4 MHz 1 1 0 1 1 MHz Other than above <R> Operating Voltage Frequency of the high-speed on-chip oscillator Setting prohibited Caution Be sure to set bit 5 to "1" and bit 4 to "0". R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 721 RL78/G12 CHAPTER 23 OPTION BYTE 23.3 Format of On-chip Debug Option Byte The format of on-chip debug option byte is shown below. Figure 23-4. Format of On-chip Debug Option Byte (000C3H) Address: 000C3H 7 6 5 4 3 2 1 0 OCDENSET 0 0 0 0 1 0 OCDERSD OCDENSET OCDERSD Control of on-chip debug operation 0 0 Disables on-chip debug operation. 0 1 Setting prohibited 1 0 Enables on-chip debugging. Erases data of flash memory in case of failures in authenticating on-chip debug security ID. 1 1 Enables on-chip debugging. Does not erases data of flash memory in case of failures in authenticating on-chip debug security ID. Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value. Be sure to set 000010B to bits 6 to 1. Remark The value on bits 3 to 1 will be written over when the on-chip debug function is in use and thus it will become unstable after the setting. However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 722 RL78/G12 CHAPTER 23 OPTION BYTE 23.4 Setting of Option Byte The user option byte and on-chip debug option byte can be set using the assembler or linker option of CubeSuite+, in addition to describing to the source. A software description example of the option byte setting is shown below. OPT CSEG OPT_BYTE DB 36H ; Does not use interval interrupt of watchdog timer, ; Enables watchdog timer operation, ; Window open period of watchdog timer is 50%, 9 ; Overflow time of watchdog timer is 2 /fIL, ; Stops watchdog timer operation during HALT/STOP mode DB 2AH ; Select 1.84 V for VLVDL ; Select 1.94 V for VLVDH ; Select the interrupt & reset mode as the LVD operation mode ; Do not use reset input DB EDH ; Select the HS (high-speed main) mode as the flash operation mode DB 85H and 1 MHz as the frequency of the high-speed on-chip oscillator clock ; Enables on-chip debug operation, does not erase flash memory data when security ID authorization fails Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute name of the CSEG pseudo instruction. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 723 RL78/G12 CHAPTER 24 FLASH MEMORY CHAPTER 24 FLASH MEMORY The RL78/G12 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory includes the "code flash memory", in which programs can be executed, and the <R> "data flash memory", an area for storing data (provided oly in the R5F102 products). FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAM 2 KB to 256 bytes Mirror F2000H F1FFFH F1800H F17FFH Reserved F1000H F0FFFH Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H FFFFFH Reserved 00000H The following three methods for programming the flash memory are available: * Writing to flash memory by using flash memory programmer (see 24.1) * Writing to flash memory by using external device (that Incorporates UART) (see 24.2) * Self-programming (see 24.7) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 724 RL78/G12 CHAPTER 24 FLASH MEMORY 24.1 Writing to Flash Memory by Using Flash Memory Programmer The following dedicated flash memory programmer can be used to write data to the internal flash memory of the RL78/G12. * PG-FP5, FL-PR5 * E1 on-chip debugging emulator Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the RL78/G12 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system. (2) Off-board programming Data can be written to the flash memory with a dedicated program adapter (FA series) before the RL78/G12 is mounted on the target system. Remark FL-PR5 and FA series are products of Naito Densei Machida Mfg. Co., Ltd. Table 24-1. Wiring Between RL78/G12 and Dedicated Flash Memory Programmer Pin No. Pin Configuration of Dedicated Flash Memory Programmer Pin Signal Name Name E1 on-chip PG-FP5, FL-PR5 20-pin I/O Pin Function SSOP debugging emulator - TOOL0 I/O Transmit/receive signal TOOL0/ Transmit/receive signal P40 24-pin WQFN (4 x 4) 30-pin SSOP 4 24 5 SI/RxD - I/O SCK - Output - - - - - CLK - Output - - - - - 5 1 6 - - - 10 6 12 9 5 11 - - 10 10 6 12 - RESET Output Reset signal /RESET - Output FLMD0 - Output Mode signal I/O VDD voltage generation/ VDD RESET - VDD power monitoring GND - Ground VSS REGC - EMVDD Note Driving power for TOOL pin VDD Note Connect REGC pin to VDD via a capacitor (0.47 to 1 F). Remark Pins that are not indicated in the above table can be left open when using the flash memory programmer for flash programming. About a connection RL78/G12 and a connector, refer to the user's manual of each programmer. About a connection with E1, refer to 25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 725 RL78/G12 CHAPTER 24 FLASH MEMORY 24.1.1 Programming environment The environment required for writing a program to the flash memory of the RL78/G12 is illustrated below. Figure 24-1. Environment for Writing Program to Flash Memory PG-FP5, FL-PR5 E1 VDD RS-232C VSS USB RESET Dedicated flash TOOL0 (dedicated single-line UART) memory programmer RL78/G12 Host machine A host machine that controls the dedicated flash memory programmer is necessary. To interface between the dedicated flash memory programmer and the RL78/G12, the TOOL0 pin is used for manipulation such as writing and erasing via a dedicated single-line UART. 24.1.2 Communication mode Communication between the dedicated flash memory programmer and the RL78/G12 is established by serial communication using the TOOL0 pin via a dedicated single-line UART of the RL78/G12. Transfer rate: 1 M, 500k, 250 k, 115.2 kbps Figure 24-2. Communication with Dedicated Flash Memory Programmer PG-FP5, FL-PR5 E1 VDD VDD EMVDD VDD GND Dedicated flash memory programmer RESETNote 1, /RESETNote 2 TOOL0Note 1 SI/RxDNote 2 VSS/REGCNote 3 RESET TOOL0 RL78/G12 Notes 1. When using E1 on-chip debugging emulator. 2. When using PG-FP5 or FL-PR5. 3. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F) (30-pin products). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 726 RL78/G12 CHAPTER 24 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the RL78/G12. See the manual of PG-FP5, FL-PR5, or E1 on-chip debugging emulator for details. Table 24-2. Pin Connection Dedicated Flash Memory Programmer Signal Name PG-FP5, FL-PR5 I/O RL78/G12 Pin Function Connection Pin Name E1 on-chip debugging emulator - FLMD0 VDD - Output Mode signal I/O VDD voltage generation/power monitoring VDD - Ground VSS, REGC - Driving power for TOOL0 pin VDD GND EMVDD CLK - Output Clock output /RESET - Output Reset signal RESET - RESET Output - TOOL0 I/O Transmit/receive signal TOOL0 SI/RxD - I/O Transmit/receive signal SCK - Output Transfer clock x Note - x - x Note Connect the REGC pin to VSS via a capacitor (0.47 to 1 F) (30-pin products). Remark : Be sure to connect the pin. x: The pin does not have to be connected. 24.2 Writing to Flash Memory by Using External Device (that Incorporates UART) On-board data writing to the internal flash memory is possible by using the RL78/G12 and an external device (a microcontroller or ASIC) connected to a UART. On the development of flash memory programmer by user, refer to the RL78 Microcontrollers (RL78 Protocol A) Programmer Edition Application Note (R01AN0815). 24.2.1 Programming environment The environment required for writing a program to the flash memory of the RL78/G12 is illustrated below. Figure 24-3. Environment for Writing Program to Flash Memory VDD VSS RESET External device (such as microcontroller and ASIC) UART (TOOLTxD, TOOLRxD) RL78/G12 TOOL0 Processing to write data to or delete data from the RL78/G12 by using an external device is performed on-board. Offboard writing is not possible. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 727 RL78/G12 CHAPTER 24 FLASH MEMORY 24.2.2 Communication mode Communication between the external device and the RL78/G12 is established by serial communication using the TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78/G12. Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps Figure 24-4. Communication with External Device VDD GND /RESET External device (such as micro controller and ASIC) VDD VSS/REGCNote RESET RxD TOOLTxD TxD TOOLRxD PORT RL78/G12 TOOL0 Note Connect the REGC pin to VSS via a capacitor (0.47 to 1 F) (30-pin products). The external device generates the following signals for the RL78/G12. Table 24-3. Pin Connection External Device Signal Name VDD I/O I/O - GND RL78/G12 Pin Function Connection Pin Name VDD voltage generation/power monitoring VDD, Ground VSS, REGC Note CLK Output Clock output RESETOUT Output Reset signal output RESET RxD Input Receive signal TOOL0TxD TxD Output Transmit signal TOOL0RxD PORT Output Mode signal TOOL0 SCK Output Transfer clock - x - x Note Connect the REGC pin to GND via a capacitor (0.47 to 1 F) (30-pin products). Remark : Be sure to connect the pin. x: The pin does not have to be connected. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 728 RL78/G12 CHAPTER 24 FLASH MEMORY 24.3 Connection of Pins on Board To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after reset, the pins must be handled as described below. Refer to flash programming mode, see 24.5.2 Flash memory programming mode. 24.3.1 P40/TOOL0 pin In the flash memory programming mode, pull up externally with a 1 k resister, and connect it to the dedicated flash memory programmer. When using it as a port pin, use it as described below. <R> Input: Do not input a low level of 1 ms interval period after the external reset release. Use a resister of 500 k or more when using for pull-down. Output: Use a resister of 500 k or more when using for pull-down. Remark The SAU and IICA pins are not used for communication between the RL78/G12 and dedicated flash memory programmer, because single-line UART (TOOL0 pin) is used. 24.3.2 RESET pin Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are connected to the RESET pin that is connected to the reset signal generator on the board. To prevent this conflict, isolate the connection with the reset signal generator. The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory programmer and external device. Figure 24-5. Signal Conflict (RESET Pin) RL78/G12 Signal conflict Input pin Dedicated flash memory programmer connection pin Another device Output pin In the flash memory programming mode, a signal output by another device will conflict with the signal output by the dedicated flash memory programmer. Therefore, isolate the signal of another device. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 729 RL78/G12 CHAPTER 24 FLASH MEMORY 24.3.3 Port pins In the flash memory programming mode, all the pins not used for flash memory programming enter the same status as that immediately after reset. If an external device connected to the ports does not recognize the port status immediately after reset, the port pin must be connected to either to VDD or VSS via a resistor. 24.3.4 REGC pins Connect the REGC pin to VSS via a capacitor (0.47 to 1 F) as in normal operation (30-pin products). Use a capacitor with good characteristics because it is used for stabilization of internal voltage. 24.3.5 X1 and X2 pins Connect X1 and X2 in the same status as in the normal operation mode. Remark In the flash memory programming mode, the high-speed on-chip oscillation clock (fIH) is used. 24.3.6 Power supply To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory programmer, and the VSS pin to GND of the flash memory programmer. To use the on-board supply voltage, connect in compliance with the normal operation mode. However, when writing to the flash memory by using the flash memory programmer and using the on-board supply voltage, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power monitor function with the flash memory programmer. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 730 RL78/G12 CHAPTER 24 FLASH MEMORY 24.4 Data Flash 24.4.1 Data flash overview <R> In addition to 2K to 16KB of code flash memory, the R5F102 products of the RL78/G12 includes 2 KB of data flash memory for storing data. FFFFFH Special function register (SFR) 256 bytes FFF00H FFEFFH FFEE0H FFEDFH General-purpose register 32 bytes RAM 2 KB to 256 bytes Mirror F2000H F1FFFH Reserved F1800H F17FFH F1000H F0FFFH Data flash memory 2 KB Reserved F0800H F07FFH Special function register (2nd SFR) 2 KB F0000H EFFFFH Reserved 00000H R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 731 RL78/G12 CHAPTER 24 FLASH MEMORY <R> An overview of the data flash memory is provided below. For details of a method for rewriting the data flash memory, refer to RL78 Family Data Flash Library Type04 User's Manual. * The data flash memory can be written to by using the flash memory programmer or an external device * Programming is performed in 8-bit units * Blocks can be deleted in 1 KB units * The only access by CPU instructions is byte reading (1 clock + wait 3 clock cycles) <R> * Because the data flash memory is an area exclusively used for data, it cannot be used to execute instructions (code fetching) * Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, Back Ground Operation (BGO) is supported) * Accessing the data flash memory is not possible while rewriting the code flash memory (during self programming) * Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set up in order to use the data flash memory * Manipulating the DFLCTL register is not possible while rewriting the data flash memory * Transition the HALT, STOP mode is not possible while rewriting the data flash memory <R> Cautions 1. Interrupts are disabled during data flash rewrite for only the R5F10266. Execute the data flash library with the IE flag cleared (0) by the DI instruction. <R> 2. The high-speed on-chip oscillator should be kept operating during data flash rewrite. When it is stopped, start the oscillator (HIOSTOP = 0) and execute the data flash library after 30 s. Refer to flash programming mode, see 24.7 Flash Memory Programming by Self-Programming. 24.4.2 Register controlling data flash memory (1) Data flash control register (DFLCTL) This register is used to enable or disable accessing to the data flash. The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction. Reset input sets this register to 00H. Figure 24-6. Format of Data Flash Control Register (DFLCTL) Address: F0090H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> DFLCTL 0 0 0 0 0 0 0 DFLEN DFLEN Data flash access control 0 Disables data flash access 1 Enables data flash access Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 732 RL78/G12 CHAPTER 24 FLASH MEMORY 24.4.3 Procedure for accessing data flash memory The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To access the memory, perform the following procedure: <1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL). <2> Wait for the setup to finish for software timer ,etc. The time setup takes differs for each main clock mode. <Setup time for each main clock mode> * HS (High-speed main) mode: 5 s * LS (Low-speed main) mode: 720 ns <3> After the wait, the data flash memory can be accessed. Cautions 1. Accessing the data flash memory is not possible during the setup time. 2. Before executing a STOP instruction during the setup time, temporarily clear DFLEN to 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 733 RL78/G12 CHAPTER 24 FLASH MEMORY 24.5 Programming Method 24.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 24-7. Flash Memory Manipulation Procedure Start Controlling TOOL0 pin and RESET pin Flash memory programming mode is set Manipulate flash memory End? No Yes End Refer to flash programming mode, see 24.5.2 Flash memory programming mode. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 734 RL78/G12 CHAPTER 24 FLASH MEMORY 24.5.2 Flash memory programming mode To rewrite the contents of the flash memory, set the RL78/G12 in the flash memory programming mode. To enter the mode, set as follows. <When programming by using the dedicated flash memory programmer> Communication from the dedicated flash memory programmer is performed to automatically switch to the flash memory programming mode. <When programming by using an external device> Set the TOOL0 pin to the low level, and then cancel the reset. Keep the TOOL0 pin at the low level from the reset ends to 1 ms + software processing end, and then use UART communication to send the data "00H" from the external device. Finish UART communication within 100 ms after the reset ends. Figure 24-8. Setting of Flash Memory Programming Mode <1> <2> <4> <3> RESET tHD+ software processing time 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> Low level is input to the TOOL0 pin. <R> <2> External reset is released (POR and LVD reset must be released in advance). <3> Low level of the TOOL0 pin is released. <4> Mode drawing and baud rate setting are complete via UART reception. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. <R> tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends (Min. 10 s) tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end. (Min. 1 s : except software processing time) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 735 RL78/G12 CHAPTER 24 FLASH MEMORY Table 24-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release TOOL0 Operation Mode V DD Normal operation mode 0V Flash memory programming mode There are two flash memory programming modes for which the voltage range in which to write, erase, or verify data differs. Table 24-5. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Mode Voltages at which data can be written, erased, or verified Writing Clock Frequency Wide voltage mode 1.8 V to 5.5 V 8 MHz (MAX.) Full speed mode Note 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 24 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 24 MHz (MAX.) Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1. Specify the mode that corresponds to the voltage range in which to write data. When programming by using the dedicated flash memory programmer, the mode is automatically selected by the voltage setting on GUI. Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, deletion, or verification. 2. For details about communication commands, see 24.5.4 Communication commands. 24.5.3 Selecting communication mode Communication mode of the RL78/G12 as follows. Table 24-6. Communication Modes Communication Mode 1-line mode Standard Setting Port UART (when flash memory programmer is used) UART0 (when external device is used) Speed Note 2 115200 bps, Note 1 Pins Used Frequency Multiply Rate - - TOOL0 - - TOOLTxD, 250000 bps, 500000 bps, 1 Mbps UART 115200 bps, 250000 bps, TOOLRxD 500000 bps, 1 Mbps Notes 1. Selection items for standard settings on GUI of the flash memory programmer. 2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART communication, thoroughly evaluate the slew as well as the baud rate error. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 736 RL78/G12 CHAPTER 24 FLASH MEMORY 24.5.4 Communication commands The RL78/G12 communicates with the dedicated flash memory programmer or external device by using commands. The signals sent from the flash memory programmer or external device to the RL78/G12 are called commands, and the signals sent from the RL78/G12 to the dedicated flash memory programmer or external device are called response. Figure 24-9. Communication Commands Dedicated flash memory programmer E1 PG-FP5, FL-PR5 Command Response RL78/G12 External device (such as microcontroller and ASIC) The flash memory control commands of the RL78/G12 are listed in the table below. All these commands are issued from the programmer or external device, and the RL78/G12 perform processing corresponding to the respective commands. Table 24-7. Flash Memory Control Commands Classification Verify Command Name Function Compares the contents of a specified area of the flash memory with Verify data transmitted from the programmer. Erase Block Erase Erases a specified area in the flash memory. Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly erased. Write Programming Writes data to a specified area in the flash memory. Getting information Silicon Signature Gets the RL78/G12 information (such as the part number and flash memory configuration, firmware version). Security Others Checksum Gets the checksum data for a specified area. Security Set Sets security information. Security Get Gets security information. Security Release Releases the write prohibition setting. Reset Used to detect synchronization status of communication. Baud Rate Set Sets baud rate when UART communication mode is selected. The RL78/G12 returns a response for the command issued by the dedicated flash memory programmer or external device. The response names sent from the RL78/G12 are listed below. Table 24-8. Response Names Response Name Function ACK Acknowledges command/data. NAK Acknowledges illegal command/data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 737 RL78/G12 CHAPTER 24 FLASH MEMORY 24.5.5 Description of signature data When the "silicon signature" command is performed, the RL78/G12 information (such as the part number, flash memory configuration, and programming firmware version) can be obtained. Table 24-9 and 24-10 show signature data list and example of signature data list. Table 24-9. Signature Data List Field name Number of transmit Description data Device code The serial number assigned to the device 3 bytes Device name Device name (ASCII code) 10 bytes Code flash memory area last address Last address of code flash memory area 3 bytes (Sent from lower address. Example. 00000H to 03FFFH (16 KB) FFH, 3FH, 00H) Data flash memory area last address Last address of data flash memory area 3 bytes (Sent from lower address. Example. F1000H to F17FFH (2 KB) FFH, 17H, 0FH) Firmware version Version information of firmware for programming 3 bytes (Sent from upper address. Example. From Ver. 1.23 01H, 02H, 03H) Table 24-10. Example of Signature Data Field name Description Number of transmit Data (hexadecimal) data Device code RL78 protocol A 3 bytes 10 00 06 Device name R5F102AA 10 bytes 52 = "R" 35 = "5" 46 = "F" 31 = "1" 30 = "0" 32 = "2" 41 = "A" 41 = "A" 20 = " " 20 = " " Code flash memory area last address Code flash memory area 3 bytes FF FF 00 3 bytes FF 17 0F 3 bytes 01 02 03 00000H to 03FFFH (16 KB) Data flash memory area last address Data flash memory area F1000H to F17FFH (2 KB) Firmware version R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Ver.1.23 01H, 02H, 03H) 738 RL78/G12 CHAPTER 24 FLASH MEMORY 24.6 Security Settings The RL78/G12 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed by using the Security Set command. * Disabling block erase Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/offboard programming. However, blocks can be erased by means of self programming. * Disabling write Execution of the write command for all the blocks in the flash memory is prohibited during on-board/off-board programming. However, data can be written by means of self programming. * Disabling rewriting boot cluster 0 Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the flash memory is prohibited by this setting. After the security settings are specified, releasing the security settings by the Security Release command is enabled by a reset. <R> The block erase, write, and rewriting boot cluster0 commands are enabled by default when the flash memory is shipped. Security can be set by on-board/off-board programming only. The security settings can be used in combination. Table 24-11 shows the relationship between the erase and write commands when the RL78/G12 security function is enabled. Caution The security function of the flash programmer does not support self-programming. Remark To prohibit writing and erasing during self-programming, use the flash shield window function. (see 24.7.1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 739 RL78/G12 CHAPTER 24 FLASH MEMORY Table 24-11. Relationship Between Enabled Security Function and Commands (1) During on-board/off-board programming Enabled Security Function Executed Command Block Erase Write Note Prohibition of block erasure Blocks cannot be erased. Can be performed . Prohibition of writing Blocks can be erased. Cannot be performed. Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Caution Confirm that no data has been written to the write area. Because data cannot be erased when block erasure is prohibited, do not write data if the data has not been erased. (2) During self programming Enabled Security Function Executed Command Block Erase Prohibition of block erasure Write Blocks can be erased. Can be performed. Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written. Prohibition of writing Prohibition of rewriting boot cluster 0 Remark To prohibit writing and erasing during self-programming, use the flash shield window function. (see 24.7.1) Table 24-12. Security Setting in Each Programming Mode <R> On-board/off-board programming Security Security Setting How to Disable Security Setting Prohibition of block erasure Use the GUI of dedicated flash memory Cannot be disabled after setting. Prohibition of writing programmer. Execute security release command Prohibition of rewriting boot cluster 0 Cannot be disabled after setting. Caution The security release command can be applied only when the security is not set as the block erase prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash memory area being blanks. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 740 RL78/G12 CHAPTER 24 FLASH MEMORY 24.7 Flash Memory Programming by Self-Programming The RL78/G12 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the RL78/G12 self-programming library, it can be used to upgrade the program in the field. <R> Cautions 1. An interrupt is prohibited during self-programming. Execute the self-programming library in the state where the IE flag is cleared (0) by the DI instruction. 2. When RAM parity error reset is enabled (RPERDIS = 0), be sure to initialize "RAM area to be used + 10byte" before rewriting. <R> 3. The high-speed on-chip oscillator clock needs to be operating during self-programming. If the high-speed on-chip oscillator clock is stopped, execute the self-programming library 30 s after operation of the high-speed on-chip oscillator clock is started (HIOSTOP = 0). <R> 4. Remarks 1. The self-programming function cannot be used in the R5F10266 and R5F10366. For details of the self-programming function and the RL78/G12 self-programming library, refer to RL78 Microcontroller Self Programming Library Type01 User's Manual (R01AN0350E). 2. For details of the time required to execute self programming, see the notes on use that accompany the flash self programming library tool. Similar to when writing data by using the flash memory programmer, there are two flash memory programming modes for which the voltage range in which to write, erase, or verify data differs. Table 24-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Mode Voltages at which data can be written, erased, or verified Wide voltage mode Full speed mode Note Writing Clock Frequency 1.8 V to 5.5 V 8 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 24 MHz (MAX.) 2.4 V to 5.5 V 16 MHz (MAX.) 2.7 V to 5.5 V 24 MHz (MAX.) Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1. Specify the mode that corresponds to the voltage range in which to write data. If the argument fsl_flash_voltage_u08 is other than 00H when the FSL_Init function of the self programming library provided by Renesas Electronics is executed, wide-voltage mode is specified. If the argument is 00H, full-speed mode is specified. Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing, deletion, or verification. 2. For details of the self-programming function and the RL78/G12 self-programming library, refer to RL78 Microcontroller Self Programming Library Type01 User's Manual (R01AN0350E). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 741 RL78/G12 CHAPTER 24 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming library. Figure 24-10. Flow of Self Programming (Rewriting Flash Memory) Flash memory control start Initialize flash environment Flash shield window setting Erase * Inhibit access to flash memory Write * Inhibit shifting STOP mode * Inhibit clock stop Verify Flash information getting Flash information setting Close flash environment End R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 742 RL78/G12 CHAPTER 24 FLASH MEMORY 24. 7.1 Flash shield window function The flash shield window function is one of the security functions in self-programming. The flash shield window function is a security function that prohibits writing and erasing outside the specified window range only during self-programming. <R> The window range can be set by specifying the start and end blocks. The window range can be set or changed by only on-board/off-board programming. Writing and erasing are prohibited in areas other than the window range during self-programming. However, writing and erasing can be done in ranges not specified as the window during on-board/off-board programming. Figure 24-11. An example of setting a flash shield window (Target device: R5F1026A, start block: 04H, and end block: 06H) Available writing method 03FFFH Block 0FH Flash shield area 01C00H 01BFFH 01000H 00FFFH Block 04H (Start block) Block 03H OK: On-board/Off-board programming NG: Self-programming Block 01H 00000H <R> OK: On-board/Off-board programming OK: Self-programming Block 02H Flash shield area Caution Block 06H (End block) Block 05H Window area Flash memory area OK: On-board/Off-board programming NG: Self-programming Block 0EH Block 00H A flash shield window can be set only for code flash (data flash is not supported). table 24-14. Setting and changing of the flash shield window function and relations with commands Programming Setting/Changing window condition range During on-board/off- Specify the start block and Block erasure can be Writing can be done board programming end block of the window on done also outside the also outside the window the GUI of the dedicated window range. range. Execution command Block erasure Writing flash memory programmer. Note To prohibit writing and erasing during on-board/off-board programming, refer to "24.6 Security Settings." R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 743 RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12 The RL78/G12 uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip debugging emulator. Serial communication is performed by using a single-line UART that uses the TOOL0 pin. Caution The RL78/G12 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. Figure 25-1. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (20, 24-pin products) Target connector VDD RL78/G12 VDD VDD 8 VDD VDD EMVDD GND GND GND 9 2 GND 12 VDD 14 1 k TOOL0 RESET RESET RSTPU 5 TOOL0 10 RESET 13 4 Note 6 Note 470 to 510 1 k TRESET Reset circuit Reset signal Note Connecting the dotted line is not necessary during flash programming. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 744 RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION For the target system which uses the multi-use feature of RESET pin in 20, 24-pin products, its connection to an external circuit should be isolated. Figure 25-2. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (When using to the alternative function of RESET pin) Target connector RL78/G12 VDD VDD EMVDD GND GND GND TOOL0 RESET RESET RSTPU TRESET VDD 8 VDD VDD 9 2 GND 12 VDD 14 5 TOOL0 10 Alternate Function of RESET pin 13 4 External circuit 6 Output pin Figure 25-3. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (30-pin products) Target connector VDD RL78/G12 VDD VDD 8 VDD VDD EMVDD 9 GND GND GND 2 12 GND 14 VDD 1 k TOOL0 RESET RESET TRESET 5 TOOL0 10 10 k 6 RESET VDD 13 1 k Note 2 Note 1 Reset circuit Reset signal Notes 1. Connecting the dotted line is not necessary during flash programming. 2. If the reset circuit on the target system does not have a buffer and generates a reset signal only with resistors and capacitors, this pull-up resistor is not necessary. Caution This circuit diagram is assumed that the reset signal outputs from an N-ch O.D. buffer (output resistor: 100 or less) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 745 RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.2 On-Chip Debug Security ID The RL78/G12 has an on-chip debug operation control bit in the flash memory at 000C3H (see CHAPTER 23 OPTION BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading memory content. Table 25-1. On-Chip Debug Security ID Address 000C4H to 000CDH On-Chip Debug Security ID Any ID code of 10 bytes 25.3 Securing of User Resources To perform communication between the RL78/G12 and E1 on-chip debugging emulator, as well as each debug function, the securing of memory space must be done beforehand. If Renesas Electronics assembler or compiler is used, the items can be set by using linker options. (1) Securement of memory space The shaded portions in Figure 25-4 are the areas reserved for placing the debug monitor program, so user programs or data cannot be allocated in these spaces. When using the on-chip debug function, these spaces must be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user program. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 746 RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION Figure 25-4. Memory Spaces Where Debug Monitor Programs Are Allocated Note 1 Code flash memory Internal RAM Use prohibited SFR area (512/256 KB Note 2) Stack area for debugging (4 bytes) Note 4 00FFFH 000D8H 000CEH Boot cluster 0 000C4H Internal RAM area Mirror area Debug monitor area (10 bytes) Security ID area (10 bytes) Code flash area On-chip debug option byte area (1 byte) : Area used for on-chip debugging 000C3H 00002H 00000H Debug monitor area (2 bytes) Note 3 Notes 1. Address differs depending on products as follows. Products (code flash memory capacity) Address of Note 1 R5F10266, R5F10366 00600H/00700H to 007FFH R5F10x67, R5F10x77, R5F10xA7 00E00H/00F00H to 00FFFH R5F10x68, R5F10x78, R5F10xA8 01E00H/01F00H to 01FFFH R5F10x69, R5F10x79, R5F10xA9 02E00H/02F00H to 02FFFH R5F10x6A, R5F10x7A, R5F10xAA 03E00H/03F00H to 03FFFH (x = 2, 3) 2. When real-time RAM monitor (RRM) function and dynamic memory modification (DMM) function are not used, it is 256 bytes. 3. In debugging, reset vector is rewritten to address allocated to a monitor program. 4. Since this area is allocated immediately before the stack area, the address of this area varies depending on the stack increase and decrease. That is, 4 extra bytes are consumed for the stack area used. When using self-programming, 12 extra bytes are consumed for the stack area used. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 747 RL78/G12 CHAPTER 26 BCD CORRECTION CIRCUIT CHAPTER 26 BCD CORRECTION CIRCUIT 26.1 BCD Correction Circuit Function The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD code with this circuit. The decimal correction operation result is obtained by performing addition/subtraction having the A register as the operand and then adding/ subtracting the BCD correction result register (BCDADJ). 26.2 Registers Used by BCD Correction Circuit The BCD correction circuit uses the following registers. * BCD correction result register (BCDADJ) (1) BCD correction result register (BCDADJ) The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through add/subtract instructions using the A register as the operand. The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. The BCDADJ register is read by an 8-bit memory manipulation instruction. Reset input sets this register to undefined. Figure 26-1. Format of BCD Correction Result Register (BCDADJ) Address: F00FEH Symbol After reset: undefined 7 6 R 5 4 3 2 1 0 BCDADJ R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 748 RL78/G12 CHAPTER 26 BCD CORRECTION CIRCUIT 26.3 BCD Correction Circuit Operation The basic operation of the BCD correction circuit is as follows. (1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a BCD code value <1> The BCD code value to which addition is performed is stored in the A register. <2> By adding the value of the A register and the second operand (value of one more BCD code to be added) as are in binary, the binary operation result is stored in the A register and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by adding in binary the value of the A register (addition result in binary) and the BCDADJ register (correction value), and the correction result is stored in the A register and CY flag. Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction. An example is shown below. Examples 1: 99 + 89 = 188 Instruction A Register CY Flag AC Flag BCDADJ Register MOV A, #99H ; <1> 99H - - - ADD A, #89H ; <2> 22H 1 1 66H ADD A, !BCDADJ ; <3> 88H 1 0 - A Register CY Flag AC Flag BCDADJ Register ; <1> 85H - - - ADD A, #15H ; <2> 9AH 0 0 66H ADD A, !BCDADJ ; <3> 00H 1 1 - A Register CY Flag AC Flag BCDADJ Register Examples 2: 85 + 15 = 100 Instruction MOV A, #85H Examples 3: 80 + 80 = 160 Instruction MOV A, #80H ; <1> 80H - - - ADD A, #80H ; <2> 00H 1 0 60H ADD A, !BCDADJ ; <3> 60H 1 0 - R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 749 RL78/G12 CHAPTER 26 BCD CORRECTION CIRCUIT (2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by using a BCD code value <1> The BCD code value from which subtraction is performed is stored in the A register. <2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the BCD correction result register (BCDADJ). <3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A register (subtraction result in binary) in binary, and the correction result is stored in the A register and CY flag. Caution The value read from the BCDADJ register varies depending on the value of the A register when it is read and those of the CY and AC flags. Therefore, execute the instruction <3> after the instruction <2> instead of executing any other instructions. To perform BCD correction in the interrupt enabled state, saving and restoring the A register is required within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction. An example is shown below. Example: 91 - 52 = 39 Instruction A Register CY Flag AC Flag BCDADJ Register MOV A, #91H ; <1> 91H - - - SUB A, #52H ; <2> 3FH 0 1 06H SUB A, !BCDADJ ; <3> 39H 0 0 - R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 750 RL78/G12 CHAPTER 27 INSTRUCTION SET CHAPTER 27 INSTRUCTION SET This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and operation code, refer to the separate document RL78 Microcontrollers User's Manual: software (R01US0015E). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 751 RL78/G12 CHAPTER 27 INSTRUCTION SET 27.1 Conventions Used in Operation List 27.1.1 Operand identifiers and specification methods Operands are described in the "Operand" column of each instruction in accordance with the description method of the instruction operand identifier (refer to the assembler specifications for details). When there are two or more description methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and are described as they are. Each symbol has the following meaning. * #: Immediate data specification * !: 16-bit absolute address specification * !!: 20-bit absolute address specification * $: 8-bit relative address specification * $!: 16-bit relative address specification * [ ]: Indirect address specification * ES:: Extension address specification In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to describe the #, !, !!, $, $!, [ ], and ES: symbols. For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in parentheses in Table 27-1 below, R0, R1, R2, etc.) can be used for description. Table 27-1. Operand Identifiers and Specification Methods Identifier Description Method r X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) rp AX (RP0), BC (RP1), DE (RP2), HL (RP3) sfr Special-function register symbol (SFR symbol) FFF00H to FFFFFH sfrp Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses only Note ) FFF00H to FFFFFH saddr FFE20H to FFF1FH Immediate data or labels saddrp FFE20H to FF1FH Immediate data or labels (even addresses only addr20 00000H to FFFFFH Immediate data or labels addr16 0000H to FFFFH Immediate data or labels (Automatically adds F to the top. only even addresses for 16-bit addr5 data transfer instructions Note ) Note ) 0080H to 00BFH Immediate data or labels (specification to bits 5 to 1, even addresses only) word 16-bit immediate data or label byte 8-bit immediate data or label bit 3-bit immediate data or label RBn RB0 to RB3 Note Bit 0 = 0 when an odd address is specified. Remark The special function registers can be described to operand sfr as symbols. See Table 3-6 SFR List for the symbols of the special function registers. The extended special function registers can be described to operand !addr16 as symbols. See Table 3-7 Extended SFR (2nd SFR) List for the symbols of the extended special function registers. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 752 RL78/G12 CHAPTER 27 INSTRUCTION SET 27.1.2 Description of operation column The operation when the instruction is executed is shown in the "Operation" column using the following symbols. Table 27-2. Symbols in "Operation" Column Symbol Function A A register; 8-bit accumulator X X register B B register C C register D D register E E register H H register L L register ES ES register CS CS register AX AX register pair; 16-bit accumulator BC BC register pair DE DE register pair HL HL register pair PC Program counter SP Stack pointer PSW Program status word CY Carry flag AC Auxiliary carry flag Z Zero flag RBS Register bank select flag IE Interrupt request enable flag () Memory contents indicated by address or register contents in parentheses X H, X L 16-bit registers: XH = higher 8 bits, XL = lower 8 bits XS, XH, XL 20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0) Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) - Inverted data addr5 16-bit immediate data (even addresses only in 0080H to 00BFH) addr16 16-bit immediate data addr20 20-bit immediate data jdisp8 Signed 8-bit data (displacement value) jdisp16 Signed 16-bit data (displacement value) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 753 RL78/G12 CHAPTER 27 INSTRUCTION SET 27.1.3 Description of flag operation column The change of the flag value when the instruction is executed is shown in the "Flag" column using the following symbols. Table 27-3. Symbols in "Flag" Column Symbol Change of Flag Value (Blank) Unchanged 0 Cleared to 0 1 Set to 1 x R Set/cleared according to the result Previously saved value is restored 27.1.4 PREFIX instruction Instructions with "ES:" have a PREFIX operation code as a prefix to extend the accessible data area to the 1 MB space (00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX operation code is attached as a prefix to the target instruction, only one instruction immediately after the PREFIX operation code is executed as the addresses with the ES register value added. A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction immediately after. Table 27-4. Use Example of PREFIX Operation Code Instruction Opcode 1 2 3 !addr16 4 5 #byte - MOV !addr16, #byte CFH MOV ES:!addr16, #byte 11H CFH MOV A, [HL] 8BH - - - - MOV A, ES:[HL] 11H 8BH - - - !addr16 #byte Caution Set the ES register value with MOV ES, A, etc., before executing the PREFIX instruction. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 754 RL78/G12 CHAPTER 27 INSTRUCTION SET 27.2 Operation List Table 27-5. Operation List (1/17) Instruction Mnemonic Group 8-bit data transfer Notes 1. MOV Operands Clocks Bytes Flag Clocks Note 1 Note 2 Z r, #byte 2 1 - r byte PSW, #byte 3 3 - PSW byte CS, #byte 3 1 - CS byte ES, #byte 2 1 - ES byte !addr16, #byte 4 1 - (addr16) byte ES:!addr16, #byte 5 2 - (ES, addr16) byte saddr, #byte 3 1 - (saddr) byte sfr, #byte 3 1 - sfr byte [DE+byte], #byte 3 1 - (DE+byte) byte ES:[DE+byte],#byte 4 2 - ((ES, DE)+byte) byte [HL+byte], #byte 3 1 - (HL+byte) byte ES:[HL+byte],#byte 4 2 - ((ES, HL)+byte) byte [SP+byte], #byte 3 1 - (SP+byte) byte word[B], #byte 4 1 - (B+word) byte ES:word[B], #byte 5 2 - ((ES, B)+word) byte word[C], #byte 4 1 - (C+word) byte ES:word[C], #byte 5 2 - ((ES, C)+word) byte word[BC], #byte 4 1 - (BC+word) byte ES:word[BC], #byte 5 2 - ((ES, BC)+word) byte A, r Note 3 1 1 - Ar r, A Note 3 1 1 - rA A, PSW 2 1 - A PSW PSW, A 2 3 - PSW A A, CS 2 1 - A CS CS, A 2 1 - CS A A, ES 2 1 - A ES ES, A 2 1 - ES A A, !addr16 3 1 4 A (addr16) A, ES:!addr16 4 2 5 A (ES, addr16) !addr16, A 3 1 - (addr16) A ES:!addr16, A 4 2 - (ES, addr16) A A, saddr 2 1 - A (saddr) saddr, A 2 1 - (saddr) A AC CY x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 755 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (2/17) Instruction Mnemonic Operands Bytes Group 8-bit data transfer Notes 1. MOV Clocks Clocks Note 1 Note 2 Flag Z A, sfr 2 1 - A sfr sfr, A 2 1 - sfr A A, [DE] 1 1 4 A (DE) [DE], A 1 1 - (DE) A A, ES:[DE] 2 2 5 A (ES, DE) ES:[DE], A 2 2 - (ES, DE) A A, [HL] 1 1 4 A (HL) [HL], A 1 1 - (HL) A A, ES:[HL] 2 2 5 A (ES, HL) ES:[HL], A 2 2 - (ES, HL) A A, [DE+byte] 2 1 4 A (DE + byte) [DE+byte], A 2 1 - (DE + byte) A A, ES:[DE+byte] 3 2 5 A ((ES, DE) + byte) ES:[DE+byte], A 3 2 - ((ES, DE) + byte) A A, [HL+byte] 2 1 4 A (HL + byte) [HL+byte], A 2 1 - (HL + byte) A A, ES:[HL+byte] 3 2 5 A ((ES, HL) + byte) ES:[HL+byte], A 3 2 - ((ES, HL) + byte) A A, [SP+byte] 2 1 - A (SP + byte) [SP+byte], A 2 1 - (SP + byte) A A, word[B] 3 1 4 A (B + word) word[B], A 3 1 - (B + word) A A, ES:word[B] 4 2 5 A ((ES, B) + word) ES:word[B], A 4 2 - ((ES, B) + word) A A, word[C] 3 1 4 A (C + word) word[C], A 3 1 - (C + word) A A, ES:word[C] 4 2 5 A ((ES, C) + word) ES:word[C], A 4 2 - ((ES, C) + word) A A, word[BC] 3 1 4 A (BC + word) word[BC], A 3 1 - (BC + word) A A, ES:word[BC] 4 2 5 A ((ES, BC) + word) ES:word[BC], A 4 2 - ((ES, BC) + word) A AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 756 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (3/17) Instruction Mnemonic Operands Bytes Group 8-bit data MOV transfer Note 1 Note 2 2 1 4 A (HL + B) [HL+B], A 2 1 - (HL + B) A A, ES:[HL+B] 3 2 5 A ((ES, HL) + B) ES:[HL+B], A 3 2 - ((ES, HL) + B) A A, [HL+C] 2 1 4 A (HL + C) [HL+C], A 2 1 - (HL + C) A A, ES:[HL+C] 3 2 5 A ((ES, HL) + C) ES:[HL+C], A 3 2 - ((ES, HL) + C) A X, !addr16 3 1 4 X (addr16) X, ES:!addr16 4 2 5 X (ES, addr16) X, saddr 2 1 - X (saddr) B, !addr16 3 1 4 B (addr16) B, ES:!addr16 4 2 5 B (ES, addr16) B, saddr 2 1 - B (saddr) C, !addr16 3 1 4 C (addr16) C, ES:!addr16 4 2 5 C (ES, addr16) C, saddr 2 1 - C (saddr) 3 1 - ES (saddr) 1 (r = X) 1 - A r A, r Note 3 Flag Z A, [HL+B] ES, saddr XCH Clocks Clocks AC CY 2 (other than r = X) Notes 1. A, !addr16 4 2 - A (addr16) A, ES:!addr16 5 3 - A (ES, addr16) A, saddr 3 2 - A (saddr) A, sfr 3 2 - A sfr A, [DE] 2 2 - A (DE) A, ES:[DE] 3 3 - A (ES, DE) A, [HL] 2 2 - A (HL) A, ES:[HL] 3 3 - A (ES, HL) A, [DE+byte] 3 2 - A (DE + byte) A, ES:[DE+byte] 4 3 - A ((ES, DE) + byte) A, [HL+byte] 3 2 - A (HL + byte) A, ES:[HL+byte] 4 3 - A ((ES, HL) + byte) Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 757 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (4/17) Instruction Mnemonic Operands Bytes Group 8-bit data XCH transfer ONEB CLRB MOVS 16-bit MOVW data Note 1 Note 2 Flag Z AC CY A, [HL+B] 2 2 - A (HL+B) A, ES:[HL+B] 3 3 - A ((ES, HL)+B) A, [HL+C] 2 2 - A (HL+C) A, ES:[HL+C] 3 3 - A ((ES, HL)+C) A 1 1 - A 01H X 1 1 - X 01H B 1 1 - B 01H C 1 1 - C 01H !addr16 3 1 - (addr16) 01H ES:!addr16 4 2 - (ES, addr16) 01H saddr 2 1 - (saddr) 01H A 1 1 - A 00H X 1 1 - X 00H B 1 1 - B 00H C 1 1 - C 00H !addr16 3 1 - (addr16) 00H ES:!addr16 4 2 - (ES,addr16) 00H saddr 2 1 - (saddr) 00H [HL+byte], X 3 1 - (HL+byte) X x x ES:[HL+byte], X 4 2 - (ES, HL+byte) X x x rp, #word 3 1 - rp word saddrp, #word 4 1 - (saddrp) word sfrp, #word transfer Notes 1. Clocks Clocks 4 1 - sfrp word AX, rp Note 3 1 1 - AX rp rp, AX Note 3 1 1 - rp AX AX, !addr16 3 1 4 AX (addr16) !addr16, AX 3 1 - (addr16) AX AX, ES:!addr16 4 2 5 AX (ES, addr16) ES:!addr16, AX 4 2 - (ES, addr16) AX AX, saddrp 2 1 - AX (saddrp) saddrp, AX 2 1 - (saddrp) AX AX, sfrp 2 1 - AX sfrp sfrp, AX 2 1 - sfrp AX Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except rp = AX Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 758 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (5/17) Instruction Mnemonic Operands Bytes Group 16-bit MOVW data Note 1 Note 2 Flag Z AX, [DE] 1 1 4 AX (DE) [DE], AX 1 1 - (DE) AX AX, ES:[DE] 2 2 5 AX (ES, DE) ES:[DE], AX 2 2 - (ES, DE) AX AX, [HL] 1 1 4 AX (HL) [HL], AX 1 1 - (HL) AX AX, ES:[HL] 2 2 5 AX (ES, HL) ES:[HL], AX 2 2 - (ES, HL) AX AX, [DE+byte] 2 1 4 AX (DE+byte) [DE+byte], AX 2 1 - (DE+byte) AX AX, ES:[DE+byte] 3 2 5 AX ((ES, DE) + byte) ES:[DE+byte], AX 3 2 - ((ES, DE) + byte) AX AX, [HL+byte] 2 1 4 AX (HL + byte) [HL+byte], AX 2 1 - (HL + byte) AX AX, ES:[HL+byte] 3 2 5 AX ((ES, HL) + byte) ES:[HL+byte], AX 3 2 - ((ES, HL) + byte) AX AX, [SP+byte] 2 1 - AX (SP + byte) [SP+byte], AX 2 1 - (SP + byte) AX AX, word[B] 3 1 4 AX (B + word) word[B], AX 3 1 - (B+ word) AX AX, ES:word[B] 4 2 5 AX ((ES, B) + word) ES:word[B], AX 4 2 - ((ES, B) + word) AX AX, word[C] 3 1 4 AX (C + word) word[C], AX 3 1 - (C + word) AX AX, ES:word[C] 4 2 5 AX ((ES, C) + word) ES:word[C], AX 4 2 - ((ES, C) + word) AX AX, word[BC] 3 1 4 AX (BC + word) word[BC], AX 3 1 - (BC + word) AX AX, ES:word[BC] 4 2 5 AX ((ES, BC) + word) ES:word[BC], AX 4 2 - ((ES, BC) + word) AX transfer Notes 1. Clocks Clocks AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 759 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (6/17) Instruction Mnemonic Operands Bytes Group 16-bit MOVW data Clocks Clocks Note 1 Note 2 3 1 4 BC (addr16) BC, ES:!addr16 4 2 5 BC (ES, addr16) DE, !addr16 3 1 4 DE (addr16) DE, ES:!addr16 4 2 5 DE (ES, addr16) HL, !addr16 3 1 4 HL (addr16) HL, ES:!addr16 4 2 5 HL (ES, addr16) BC, saddrp 2 1 - BC (saddrp) DE, saddrp 2 1 - DE (saddrp) HL, saddrp 2 1 - HL (saddrp) 1 1 - AX rp AX, rp ONEW AX 1 1 - AX 0001H BC 1 1 - BC 0001H AX 1 1 - AX 0000H BC 1 1 - BC 0000H A, #byte 2 1 - A, CY A + byte x x x 3 2 - (saddr), CY (saddr)+byte x x x 2 1 - A, CY A + r x x x r, A 2 1 - r, CY r + A x x x A, !addr16 3 1 4 A, CY A + (addr16) x x x A, ES:!addr16 4 2 5 A, CY A + (ES, addr16) x x x A, saddr 2 1 - A, CY A + (saddr) x x x A, [HL] 1 1 4 A, CY A+ (HL) x x x A, ES:[HL] 2 2 5 A,CY A + (ES, HL) x x x A, [HL+byte] 2 1 4 A, CY A + (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A,CY A + ((ES, HL)+byte) x x x A, [HL+B] 2 1 4 A, CY A + (HL+B) x x x A, ES:[HL+B] 3 2 5 A,CY A+((ES, HL)+B) x x x A, [HL+C] 2 1 4 A, CY A + (HL+C) x x x A, ES:[HL+C] 3 2 5 A,CY A + ((ES, HL) + C) x x x ADD operation saddr, #byte A, r Notes 1. Note 3 AC CY XCHW CLRW 8-bit Z BC, !addr16 transfer Flag Note 4 Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except rp = AX 4. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 760 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (7/17) Instruction Mnemonic Operands Bytes Group 8-bit ADDC operation Note 2 2 1 - A, CY A+byte+CY x x x 3 2 - (saddr), CY (saddr) +byte+CY x x x 2 1 - A, CY A + r + CY x x x r, A 2 1 - r, CY r + A + CY x x x A, !addr16 3 1 4 A, CY A + (addr16)+CY x x x A, ES:!addr16 4 2 5 A, CY A + (ES, addr16)+CY x x x A, saddr 2 1 - A, CY A + (saddr)+CY x x x A, [HL] 1 1 4 A, CY A+ (HL) + CY x x x A, ES:[HL] 2 2 5 A,CY A+ (ES, HL) + CY x x x A, [HL+byte] 2 1 4 A, CY A+ (HL+byte) + CY x x x A, ES:[HL+byte] 3 2 5 A,CY A+ ((ES, HL)+byte) + CY x x x A, [HL+B] 2 1 4 A, CY A+ (HL+B) +CY x x x A, ES:[HL+B] 3 2 5 A,CY A+((ES, HL)+B)+CY x x x A, [HL+C] 2 1 4 A, CY A+ (HL+C)+CY x x x A, ES:[HL+C] 3 2 5 A,CY A+ ((ES, HL)+C)+CY x x x A, #byte 2 1 - A, CY A - byte x x x 3 2 - (saddr), CY (saddr) - byte x x x 2 1 - A, CY A - r x x x r, A 2 1 - r, CY r - A x x x A, !addr16 3 1 4 A, CY A - (addr16) x x x A, ES:!addr16 4 2 5 A, CY A - (ES, addr16) x x x A, saddr 2 1 - A, CY A - (saddr) x x x A, [HL] 1 1 4 A, CY A - (HL) x x x A, ES:[HL] 2 2 5 A,CY A - (ES, HL) x x x A, [HL+byte] 2 1 4 A, CY A - (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A,CY A - ((ES, HL)+byte) x x x A, [HL+B] 2 1 4 A, CY A - (HL+B) x x x A, ES:[HL+B] 3 2 5 A,CY A - ((ES, HL)+B) x x x A, [HL+C] 2 1 4 A, CY A - (HL+C) x x x A, ES:[HL+C] 3 2 5 A,CY A - ((ES, HL)+C) x x x A, #byte A, rv Note 3 saddr, #byte A, r Notes 1. Flag Note 1 saddr, #byte SUB Clocks Clocks Note 3 Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 761 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (8/17) Instruction Mnemonic Operands Bytes Group 8-bit SUBC operation Note 2 2 1 - A, CY A - byte - CY x x x 3 2 - (saddr), CY (saddr) - byte - CY x x x 2 1 - A, CY A - r - CY x x x r, A 2 1 - r, CY r - A - CY x x x A, !addr16 3 1 4 A, CY A - (addr16) - CY x x x A, ES:!addr16 4 2 5 A, CY A - (ES, addr16) - CY x x x A, saddr 2 1 - A, CY A - (saddr) - CY x x x A, [HL] 1 1 4 A, CY A - (HL) - CY x x x A, ES:[HL] 2 2 5 A,CY A - (ES, HL) - CY x x x A, [HL+byte] 2 1 4 A, CY A - (HL+byte) - CY x x x A, ES:[HL+byte] 3 2 5 A,CY A - ((ES, HL)+byte) - CY x x x A, [HL+B] 2 1 4 A, CY A - (HL+B) - CY x x x A, ES:[HL+B] 3 2 5 A,CY A - ((ES, HL)+B) - CY x x x A, [HL+C] 2 1 4 A, CY A - (HL+C) - CY x x x A, ES:[HL+C] 3 2 5 A, CY A - ((ES:HL)+C) - CY x x x A, #byte 2 1 - A A byte x 3 2 - (saddr) (saddr) byte x 2 1 - AAr x r, A 2 1 - RrA x A, !addr16 3 1 4 A A (addr16) x A, ES:!addr16 4 2 5 A A (ES:addr16) x A, saddr 2 1 - A A (saddr) x A, [HL] 1 1 4 A A (HL) x A, ES:[HL] 2 2 5 A A (ES:HL) x A, [HL+byte] 2 1 4 A A (HL+byte) x A, ES:[HL+byte] 3 2 5 A A ((ES:HL)+byte) x A, [HL+B] 2 1 4 A A (HL+B) x A, ES:[HL+B] 3 2 5 A A ((ES:HL)+B) x A, [HL+C] 2 1 4 A A (HL+C) x A, ES:[HL+C] 3 2 5 A A ((ES:HL)+C) x A, #byte A, r Note 3 saddr, #byte A, r Notes 1. Flag Note 1 saddr, #byte AND Clocks Clocks Note 3 Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 762 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (9/17) Instruction Mnemonic Operands Bytes Group 8-bit OR operation Note 2 2 1 - A Abyte x 3 2 - (saddr) (saddr)byte x 2 1 - A Ar x r, A 2 1 - r rA x A, !addr16 3 1 4 A A(addr16) x A, ES:!addr16 4 2 5 A A(ES:addr16) x A, saddr 2 1 - A A(saddr) x A, [HL] 1 1 4 A A(H) x A, ES:[HL] 2 2 5 A A(ES:HL) x A, [HL+byte] 2 1 4 A A(HL+byte) x A, ES:[HL+byte] 3 2 5 A A((ES:HL)+byte) x A, [HL+B] 2 1 4 A A(HL+B) x A, ES:[HL+B] 3 2 5 A A((ES:HL)+B) x A, [HL+C] 2 1 4 A A(HL+C) x A, ES:[HL+C] 3 2 5 A A((ES:HL)+C) x A, #byte 2 1 - A Abyte x 3 2 - (saddr) (saddr)byte x 2 1 - A Ar x r, A 2 1 - r rA x A, !addr16 3 1 4 A A(addr16) x A, ES:!addr16 4 2 5 A A(ES:addr16) x A, saddr 2 1 - A A(saddr) x A, [HL] 1 1 4 A A(HL) x A, ES:[HL] 2 2 5 A A(ES:HL) x A, [HL+byte] 2 1 4 A A(HL+byte) x A, ES:[HL+byte] 3 2 5 A A((ES:HL)+byte) x A, [HL+B] 2 1 4 A A(HL+B) x A, ES:[HL+B] 3 2 5 A A((ES:HL)+B) x A, [HL+C] 2 1 4 A A(HL+C) x A, ES:[HL+C] 3 2 5 A A((ES:HL)+C) x A, #byte A, r Note 3 saddr, #byte A, r Notes 1. Flag Note 1 saddr, #byte XOR Clocks Clocks Note 3 Z AC CY Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 763 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (10/17) Instruction Mnemonic Operands Bytes Group 8-bit CMP operation CMPS Notes 1. Note 1 Note 2 Flag Z AC CY A, #byte 2 1 - A - byte x x x !addr16, #byte 4 1 4 (addr16) - byte x x x ES:!addr16, #byte 5 2 5 (ES:addr16) - byte x x x saddr, #byte 3 1 - (saddr) - byte x x x 2 1 - A-r x x x r, A 2 1 - r-A x x x A, !addr16 3 1 4 A - (addr16) x x x A, ES:!addr16 4 2 5 A - (ES:addr16) x x x A, saddr 2 1 - A - (saddr) x x x A, [HL] 1 1 4 A - (HL) x x x A, ES:[HL] 2 2 5 A - (ES:HL) x x x A, [HL+byte] 2 1 4 A - (HL+byte) x x x A, ES:[HL+byte] 3 2 5 A - ((ES:HL)+byte) x x x A, [HL+B] 2 1 4 A - (HL+B) x x x A, ES:[HL+B] 3 2 5 A - ((ES:HL)+B) x x x A, [HL+C] 2 1 4 A - (HL+C) x x x A, ES:[HL+C] 3 2 5 A - ((ES:HL)+C) x x x A 1 1 - A - 00H x 0 0 X 1 1 - X - 00H x 0 0 B 1 1 - B - 00H x 0 0 C 1 1 - C - 00H x 0 0 !addr16 3 1 4 (addr16) - 00H x 0 0 ES:!addr16 4 2 5 (ES:addr16) - 00H x 0 0 saddr 2 1 - (saddr) - 00H x 0 0 X, [HL+byte] 3 1 4 X - (HL+byte) x x x X, ES:[HL+byte] 4 2 5 X - ((ES:HL)+byte) x x x A, r CMP0 Clocks Clocks Note3 Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. Except r = A Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 764 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (11/17) Instruction Mnemonic Operands Bytes Group 16-bit ADDW operation SUBW CMPW Multiply Notes 1. MULU Clocks Clocks Note 1 Note 2 Flag Z AC CY AX, #word 3 1 - AX, CY AX+word x x x AX, AX 1 1 - AX, CY AX+AX x x x AX, BC 1 1 - AX, CY AX+BC x x x AX, DE 1 1 - AX, CY AX+DE x x x AX, HL 1 1 - AX, CY AX+HL x x x AX, !addr16 3 1 4 AX, CY AX+(addr16) x x x AX, ES:!addr16 4 2 5 AX, CY AX+(ES:addr16) x x x AX, saddrp 2 1 - AX, CY AX+(saddrp) x x x AX, [HL+byte] 3 1 4 AX, CY AX+(HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX, CY AX+((ES:HL)+byte) x x x AX, #word 3 1 - AX, CY AX - word x x x AX, BC 1 1 - AX, CY AX - BC x x x AX, DE 1 1 - AX, CY AX - DE x x x AX, HL 1 1 - AX, CY AX - HL x x x AX, !addr16 3 1 4 AX, CY AX - (addr16) x x x AX, ES:!addr16 4 2 5 AX, CY AX - (ES:addr16) x x x AX, saddrp 2 1 - AX, CY AX - (saddrp) x x x AX, [HL+byte] 3 1 4 AX, CY AX - (HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX, CY AX - ((ES:HL)+byte) x x x AX, #word 3 1 - AX - word x x x AX, BC 1 1 - AX - BC x x x AX, DE 1 1 - AX - DE x x x AX, HL 1 1 - AX - HL x x x AX, !addr16 3 1 4 AX - (addr16) x x x AX, ES:!addr16 4 2 5 AX - (ES:addr16) x x x AX, saddrp 2 1 - AX - (saddrp) x x x AX, [HL+byte] 3 1 4 AX - (HL+byte) x x x AX, ES: [HL+byte] 4 2 5 AX - ((ES:HL)+byte) x x x X 1 1 - AX AxX Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 765 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (12/17) Instruction Mnemonic Operands Bytes Group Increment/ Note 2 Z AC CY 1 1 - r r+1 x x !addr16 3 2 - (addr16) (addr16)+1 x x ES:!addr16 4 3 - (ES, addr16) (ES, addr16)+1 x x saddr 2 2 - (saddr) (saddr)+1 x x [HL+byte] 3 2 - (HL+byte) (HL+byte)+1 x x ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte)+1 x x r 1 1 - rr-1 x x !addr16 3 2 - (addr16) (addr16) - 1 x x ES:!addr16 4 3 - (ES, addr16) (ES, addr16) - 1 x x saddr 2 2 - (saddr) (saddr) - 1 x x [HL+byte] 3 2 - (HL+byte) (HL+byte) - 1 x x ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte) - 1 x x rp 1 1 - rp rp+1 !addr16 3 2 - (addr16) (addr16)+1 ES:!addr16 4 3 - (ES, addr16) (ES, addr16)+1 saddrp 2 2 - (saddrp) (saddrp)+1 [HL+byte] 3 2 - (HL+byte) (HL+byte)+1 ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte)+1 rp 1 1 - rp rp - 1 !addr16 3 2 - (addr16) (addr16) - 1 ES:!addr16 4 3 - (ES, addr16) (ES, addr16) - 1 saddrp 2 2 - (saddrp) (saddrp) - 1 [HL+byte] 3 2 - (HL+byte) (HL+byte) - 1 ES: [HL+byte] 4 3 - ((ES:HL)+byte) ((ES:HL)+byte) - 1 SHR A, cnt 2 1 - (CY A0, Am-1 Am, A7 0) xcnt x SHRW AX, cnt 2 1 - (CY AX0, AXm-1 AXm, AX15 0) xcnt x SHL A, cnt 2 1 - (CY A7, Am Am-1, A0 0) xcnt x B, cnt 2 1 - (CY B7, Bm Bm-1, B0 0) xcnt x C, cnt 2 1 - (CY C7, Cm Cm-1, C0 0) xcnt x AX, cnt 2 1 - (CY AX15, AXm AXm-1, AX0 0) xcnt x BC, cnt 2 1 - (CY BC15, BCm BCm-1, BC0 0) xcnt x SAR A, cnt 2 1 - (CY A0, Am-1 Am, A7 A7) xcnt x SARW AX, cnt 2 1 - (CY AX0, AXm-1 AXm, AX15 AX15) xcnt x DEC INCW DECW SHLW Notes 1. Note 1 Flag r INC decrement Shift Clocks Clocks Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. Remarks 1. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. 2. cnt indicates the bit shift count. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 766 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (13/17) Instruction Mnemonic Operands Bytes Group Rotate Bit Note 1 Note 2 Flag Z AC CY ROR A, 1 2 1 - (CY, A7 A0, Am-1 Am)x1 x ROL A, 1 2 1 - (CY, A0 A7, Am+1 Am)x1 x RORC A, 1 2 1 - (CY A0, A7 CY, Am-1 Am)x1 x ROLC A, 1 2 1 - (CY A7, A0 CY, Am+1 Am)x1 x ROLWC AX,1 2 1 - (CY AX15, AX0 CY, AXm+1 AXm) x1 x BC,1 2 1 - (CY BC15, BC0 CY, BCm+1 BCm) x1 x CY, A.bit 2 1 - CY A.bit x A.bit, CY 2 1 - A.bit CY CY, PSW.bit 3 1 - CY PSW.bit PSW.bit, CY 3 4 - PSW.bit CY CY, saddr.bit 3 1 - CY (saddr).bit saddr.bit, CY 3 2 - (saddr).bit CY CY, sfr.bit 3 1 - CY sfr.bit sfr.bit, CY 3 2 - sfr.bit CY CY,[HL].bit 2 1 4 CY (HL).bit [HL].bit, CY 2 2 - (HL).bit CY CY, ES:[HL].bit 3 2 5 CY (ES, HL).bit ES:[HL].bit, CY 3 3 - (ES, HL).bit CY CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CY CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY,[HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CYX CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY, [HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x MOV1 manipulate AND1 OR1 Notes 1. Clocks Clocks x x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 767 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (14/17) Instruction Mnemonic Operands Bytes Group Bit Note 1 Note 2 Flag Z AC CY CY, A.bit 2 1 - CY CY A.bit x CY, PSW.bit 3 1 - CY CY PSW.bit x CY, saddr.bit 3 1 - CY CY (saddr).bit x CY, sfr.bit 3 1 - CY CY sfr.bit x CY, [HL].bit 2 1 4 CY CY (HL).bit x CY, ES:[HL].bit 3 2 5 CY CY (ES, HL).bit x A.bit 2 1 - A.bit 1 PSW.bit 3 4 - PSW.bit 1 !addr16.bit 4 2 - (addr16).bit 1 ES:!addr16.bit 5 3 - (ES, addr16).bit 1 saddr.bit 3 2 - (saddr).bit 1 sfr.bit 3 2 - sfr.bit 1 [HL].bit 2 2 - (HL).bit 1 ES:[HL].bit 3 3 - (ES, HL).bit 1 A.bit 2 1 - A.bit 0 PSW.bit 3 4 - PSW.bit 0 !addr16.bit 4 2 - (addr16).bit 0 ES:!addr16.bit 5 3 - (ES, addr16).bit 0 saddr.bit 3 2 - (saddr.bit) 0 sfr.bit 3 2 - sfr.bit 0 [HL].bit 2 2 - (HL).bit 0 ES:[HL].bit 3 3 - (ES, HL).bit 0 SET1 CY 2 1 - CY 1 1 CLR1 CY 2 1 - CY 0 0 NOT1 CY 2 1 - CY CY x XOR1 manipulate SET1 CLR1 Notes 1. Clocks Clocks x x x x x x Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 768 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (15/17) Instruction Mnemonic Operands Bytes Group CALL Call/ rp 2 Clocks Clocks Note 1 Note 2 3 - Flag Z AC CY (SP - 2) (PC+2)S, (SP - 3) (PC+2)H, (SP - 4) (PC+2)L, PC CS, rp, return SP SP - 4 $!addr20 3 3 - (SP - 2) (PC+3)S, (SP - 3) (PC+3)H, (SP - 4) (PC+3)L, PC PC+3+jdisp16, SP SP - 4 !addr16 3 3 - (SP - 2) (PC+3)S, (SP - 3) (PC+3)H, (SP - 4) (PC+3)L, PC 0000, addr16, SP SP - 4 !!addr20 4 3 - (SP - 2) (PC+4)S, (SP - 3) (PC+4)H, (SP - 4) (PC+4)L, PC addr20, SP SP - 4 CALLT [addr5] 2 5 - (SP - 2) (PC+2)S , (SP - 3) (PC+2)H, (SP - 4) (PC+2)L , PCS 0000, PCH (0000, addr5+1), PCL (0000, addr5), SP SP - 4 BRK - 2 5 - (SP - 1) PSW, (SP - 2) (PC+2)S, (SP - 3) (PC+2)H, (SP - 4) (PC+2)L, PCS 0000, PCH (0007FH), PCL (0007EH), SP SP - 4, IE 0 RET - 1 6 - PCL (SP), PCH (SP+1), PCS (SP+2), SP SP+4 RETI - 2 6 - PCL (SP), PCH (SP+1), R R R R R R PCS (SP+2), PSW (SP+3), SP SP+4 RETB - 2 6 - PCL (SP), PCH (SP+1), PCS (SP+2), PSW (SP+3), SP SP+4 Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Remark Number of CPU clocks (fCLK) when the program memory area is accessed. Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 769 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (16/17) Instruction Group Stack Mnemon Operands Bytes ic PUSH PSW Clocks Clocks Note 1 Note 2 1 - 2 manipulate Flag Z AC CY (SP - 1) PSW, (SP - 2) 00H, SP SP-2 rp 1 1 - (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW 2 3 - PSW (SP+1), SP SP + 2 rp 1 1 - rpL (SP), rpH (SP+1), SP SP + 2 SP, #word 4 1 - SP word SP, AX 2 1 - SP AX AX, SP 2 1 - AX SP HL, SP 3 1 - HL SP BC, SP 3 1 - BC SP DE, SP 3 1 - DE SP ADDW SP, #byte 2 1 - SP SP + byte SUBW SP, #byte 2 1 - SP SP - byte BR AX 2 3 - PC CS, AX $addr20 2 3 - PC PC + 2 + jdisp8 $!addr20 3 3 - PC PC + 3 + jdisp16 !addr16 3 3 - PC 0000, addr16 !!addr20 4 3 POP MOVW Unconditio nal branch Conditional BC branch BNC BZ BNZ BH BNH BT - PC addr20 - PC PC + 2 + jdisp8 if CY = 1 $addr20 2 2/4 Note3 $addr20 2 2/4 Note3 - PC PC + 2 + jdisp8 if CY = 0 2/4 Note3 - PC PC + 2 + jdisp8 if Z = 1 2/4 Note3 - PC PC + 2 + jdisp8 if Z = 0 2/4 Note3 - PC PC + 3 + jdisp8 if (ZCY)=0 2/4 Note3 - PC PC + 3 + jdisp8 if (ZCY)=1 3/5 Note3 - PC PC + 4 + jdisp8 if (saddr).bit = 1 3/5 Note3 - PC PC + 4 + jdisp8 if sfr.bit = 1 - PC PC + 3 + jdisp8 if A.bit = 1 $addr20 $addr20 $addr20 $addr20 saddr.bit, $addr20 sfr.bit, $addr20 2 2 3 3 4 4 A.bit, $addr20 3 3/5 Note3 PSW.bit, $addr20 4 3/5 Note3 - PC PC + 4 + jdisp8 if PSW.bit = 1 3/5 Note3 6/7 PC PC + 3 + jdisp8 if (HL).bit = 1 4/6 Note3 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 1 [HL].bit, $addr20 ES:[HL].bit, 3 4 R R R $addr20 Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. This indicates the number of clocks "when condition is not met/when condition is met". Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 770 RL78/G12 CHAPTER 27 INSTRUCTION SET Table 27-5. Operation List (17/17) Instruction Mnemonic Operands Bytes Group Condition Note 1 BF saddr.bit, $addr20 al branch sfr.bit, $addr20 A.bit, $addr20 PSW.bit, $addr20 [HL].bit, $addr20 ES:[HL].bit, Clocks Clocks Note 2 Z 3/5 Note3 - PC PC + 4 + jdisp8 if (saddr).bit = 0 3/5 Note3 - PC PC + 4 + jdisp8 if sfr.bit = 0 3/5 Note3 - PC PC + 3 + jdisp8 if A.bit = 0 3/5 Note3 - PC PC + 4 + jdisp8 if PSW.bit = 0 3/5 Note3 6/7 PC PC + 3 + jdisp8 if (HL).bit = 0 4 4/6 Note3 7/8 PC PC + 4 + jdisp8 if (ES, HL).bit = 0 4 3/5 Note3 - 3/5 Note3 3/5 Note3 3/5 Note3 3/5 Note3 4/6 Note3 4 4 3 4 3 Flag AC CY $addr20 BTCLR saddr.bit, $addr20 PC PC + 4 + jdisp8 if (saddr).bit = 1 then reset (saddr).bit sfr.bit, $addr20 4 - PC PC + 4 + jdisp8 if sfr.bit = 1 then reset sfr.bit A.bit, $addr20 3 - PC PC + 3 + jdisp8 if A.bit = 1 then reset A.bit PSW.bit, $addr20 4 - PC PC + 4 + jdisp8 if PSW.bit = 1 x x x then reset PSW.bit [HL].bit, $addr20 3 - PC PC + 3 + jdisp8 if (HL).bit = 1 then reset (HL).bit ES:[HL].bit, 4 - $addr20 Conditional skip CPU Notes 1. then reset (ES, HL).bit SKC - 2 1 - Next instruction skip if CY = 1 SKNC - 2 1 - Next instruction skip if CY = 0 SKZ - 2 1 - Next instruction skip if Z = 1 SKNZ - 2 1 - Next instruction skip if Z = 0 SKH - 2 1 - Next instruction skip if (ZCY)=0 SKNH - 2 1 - Next instruction skip if (ZCY)=1 2 1 - RBS[1:0] n SEL control PC PC + 4 + jdisp8 if (ES, HL).bit = 1 Note4 RBn NOP - 1 1 - No Operation EI - 3 4 - IE 1 (Enable Interrupt) DI - 3 4 - IE 0 (Disable Interrupt) HALT - 2 3 - Set HALT Mode STOP - 2 3 - Set STOP Mode Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or when no data is accessed. 2. Number of CPU clocks (fCLK) when the program memory area is accessed. 3. This indicates the number of clocks "when condition is not met/when condition is met". Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction from the internal RAM area, the number becomes double number plus 3 clocks at a maximum. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 771 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS CHAPTER 28 ELECTRICAL SPECIFICATIONS Cautions 1. The RL78/G12 has an on-chip debug function, which is provided for development and evaluation. Do not use the on-chip debug function in products designated for mass production, because the guaranteed number of rewritable times of the flash memory may be exceeded when this function is used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for problems occurring when the on-chip debug function is used. 2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions Mounted According to Product. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 772 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.1 Absolute Maximum Ratings Absolute Maximum Ratings (TA = 25C) Parameter Supply Voltage REGC terminal input Note 1 voltage Input Voltage Output Voltage Analog input voltage Symbols Conditions VDD VSS VIREGC REGC Ratings Unit -0.5 to + 6.5 V -0.5 to + 0.3 V V -0.3 to +2.8 Note 2 and -0.3 to VDD + 0.3 VI1 Other than P60, P61 VI2 P60, P61 (N-ch open drain) -0.3 to VDD + 0.3 -0.3 to 6.5 VO VAI Note 3 ANI0 to ANI22 V V -0.3 to VDD + 0.3 Note 3 V -0.3 to VDD + 0.3 Note 3 V and -0.3 to Note 3 AVREF(+)+0.3 Output current, high IOH1 Per pin Other than P20 to P23 -40 mA Total of all pins All the terminals other than P20 to P23 -170 mA 20-, 24-pin products: P40 to P42 -70 mA -100 mA -0.5 mA -2 mA mA 30-pin products: P00, P01, P40, P120 <R> 20-, 24-pin products: P00 to P03 P10 to P14 Note 4 , 30-pin products: P10 to P17, P30, P31, P50, P51, P147 IOH2 Per pin P20 to P23 Total of all pins Output current, low IOL1 Per pin Other than P20 to P23 40 Total of all pins All the terminals other than P20 to P23 170 mA 20-, 24-pin products: P40 to P42 70 mA 100 mA 1 mA 5 mA 30-pin products: P00, P01, P40, P120 20-, 24-pin products: P00 to P03, P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 IOL2 Per pin Total of all pins <R> P20 to P23 Operating ambient temperature TA -40 to +85 C Storage temperature Tstg -65 to +150 C Notes 1. 30-pin product only. 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 F). This value determines the absolute maximum rating of the REGC pin. Do not use it with voltage applied. 3. Must be 6.5 V or lower. 4. 24-pin product only. Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. 2. AVREF (+) : + side reference voltage of the A/D converter. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 773 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.2 Oscillator Characteristics 28.2.1 X1 clock oscillator characteristics (TA = -40 to +85C, 1.8 V VDD VDD 5.5 V, VSS = 0 V) Parameter Resonator X1 clock oscillation Ceramic resonator Note frequency (fX) Recommended Circuit VSS X1 / crystal oscillator C1 Conditions X2 Rd MIN. TYP. MAX. Unit MHz 2.7 V VDD 5.5 V 1.0 20.0 1.8 V VDD < 2.7 V 1.0 8.0 C2 Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1 clock oscillation stabilization time using the oscillation stabilization time counter status register (OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation stabilization time with the resonator to be used. 28.2.2 On-chip oscillator characteristics (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Oscillators Parameters High-speed on-chip oscillator oscillation frequency <R> Conditions High-speed on-chip oscillator accuracy TYP. Unit 1 24 MHz TA = -20 to +85 C -1 +1 % TA = -40 to -20 C -1.5 +1.5 % -5 +5 % Note 1 R5F102 oscillation frequency <R> MAX. fIH MIN. Note 2 R5F103 Low-speed on-chip oscillator 15 fIL kHz oscillation frequency Low-speed on-chip oscillator -15 +15 % oscillation frequency accuracy Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits 0 to 2 of HOCODIV register. 2. This only indicates the oscillator characteristics. Refer to AC Characteristics for instruction execution time. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 774 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.3 DC Characteristics 28.3.1 Pin characteristics (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Output current, high Note 1 IOH1 (1/4) Conditions Per pin <R> MIN. TYP. 20-, 24-pin products: P00 to P03 MAX. Unit -10.0 mA Note 3 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 Total of all pins Note 2 20-, 24-pin products: 4.0 V VDD 5.5 V -30.0 mA P40 to P42 2.7 V VDD < 4.0 V -6.0 mA 30-pin products: P00, 1.8 V VDD < 2.7 V -4.5 mA 4.0 V VDD 5.5 V -80.0 mA 2.7 V VDD < 4.0 V -18.0 mA 1.8 V VDD < 2.7 V -10.0 mA All the terminals -100 mA P20 to P23 -0.1 mA -0.4 mA P01, P40, P120 20-, 24-pin products: P00 to P03 <R> Note 3 , P10 to P14 30-pin products: P10 to P17, P30, P31, P50, P51, P147 IOH2 Per pin Total of all pins Notes 1. Note 2 value of current at which the device operation is guaranteed even if the current flows from the VDD pin to an output pin. 2. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOH x 0.7)/(n x 0.01) <Example> Where n = 50% and IOH = -10.0 mA Total output current of pins = (-10.0 x 0.7)/(50 x 0.01) = -14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. <R> <R> 3. 24-pin products only. Caution P10 to P12, P41 for 20-pin products, P01, P10 to P12, P41 for 24-pin products, and P00, P10 to P15, P17, P50 for 30-pin products, do not output high level in N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 775 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Note 1 Output current, low IOL1 (2/4) Conditions Per pin 20-, 24-pin products: TYP. MAX. Unit 20.0 mA 15.0 mA Note 3 , P00 to P03 <R> MIN. P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 P60, P61 Total of all pins Note 2 20-, 24-pin products: 4.0 V VDD 5.5 V 60.0 mA P40 to P42 2.7 V VDD < 4.0 V 9.0 mA 30-pin products: 1.8 V VDD < 2.7 V 1.8 mA 4.0 V VDD 5.5 V 80.0 mA 2.7 V VDD < 4.0 V 27.0 mA 1.8 V VDD < 2.7 V 5.4 mA All the terminals 140 mA P20 to P23 0.4 mA 1.6 mA P00, P01, P40, P120 20-, 24-pin products: P00 to P03 <R> Note 3 , P10 to P14, P60, P61 30-pin products: P10 to P17, P30, P31, P50, P51, P60, P61, P147 IOL2 Per pin Total of all pins Notes 1. Note 2 Value of current at which the device operation is guaranteed even if the current flows from an output pin to the VSS pin. 2. Specification under conditions where the duty factor is 70%. The output current value that has changed the duty ratio can be calculated with the following expression (when changing the duty factor from 70% to n%). * Total output current of pins = (IOL x 0.7)/(n x 0.01) <Example> Where n = 50% and IOL = 10.0 mA Total output current of pins = (10.0 x 0.7)/(50 x 0.01) = 14.0 mA However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A current higher than the absolute maximum rating must not flow into one pin. <R> 3. Remark 24-pin products only. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 776 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Input voltage, high Symbol VIH1 <R> (3/4) Conditions MIN. Normal input buffer 20-, 24-pin products: P00 to P03 TYP. MAX. Unit 0.8VDD VDD V Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIH2 4.0 V VDD 5.5 V TTL input buffer 2.2 VDD V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 2.0 VDD V 1.8 V VDD < 3.3 V 1.50 VDD V 30-pin products: P01, P10, P11, P13 to P17 Input voltage, low VIH3 P20 to P23 0.7VDD VDD V VIH4 P60, P61 0.7VDD 6.0 V VIH5 P121, P122, P125, P137, EXCLK, RESET 0.8VDD VDD V VIL1 Normal input buffer 0 0.2VDD V 4.0 V VDD 5.5 V 0 0.8 V 20-, 24-pin products: P10, P11 3.3 V VDD < 4.0 V 0 0.5 V 1.8 V VDD < 3.3 V 0 0.32 V 0 0.3VDD V 0 0.3VDD V 0 0.2VDD V 20-, 24-pin products: P00 to P03 <R> Note 2 , P10 to P14, P40 to P42 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147 VIL2 TTL input buffer 30-pin products: P01, P10, P11, P13 to P17 Output voltage, high VIL3 P20 to P23 VIL4 P60, P61 Note 1 VIL5 P121, P122, P125 VOH1 20-, 24-pin products: <R> P00 to P03 Note 2 , P137, EXCLK, RESET , P10 to P14, 4.0 V VDD 5.5 V, P40 to P42 4.0 V VDD 5.5 V, 30-pin products: IOH1 = -3.0 mA P00, P01, P10 to P17, P30, 2.7 V VDD 5.5 V, P31, P40, P50, P51, P120, P147 VDD-1.5 V VDD-0.7 V VDD-0.6 V VDD-0.5 V VDD-0.5 V IOH1 = -10.0 mA IOH1 = -2.0 mA 1.8 V VDD 5.5 V, IOH1 = -1.5 mA VOH2 P20 to P23 IOH2 = -100 A Notes 1. 20, 24-pin products only. <R> 2. 24-pin products only. Caution The maximum value of VIH of pins P01, P10 to P12, P41, for 20-, 24-pin products and P00, P10 to P15, P17, P50 for 30-pin products is VDD even in N-ch open-drain mode. High level is not output in the N-ch open-drain mode. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 777 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Output voltage, low Symbol VOL1 <R> (4/4) Conditions 20-, 24-pin products: P00 to P03 Note , P10 to P14, TYP. 4.0 V VDD 5.5 V, MAX. Unit 1.3 V 0.7 V 0.6 V 0.4 V 0.4 V IOL1 = 20.0 mA P40 to P42 4.0 V VDD 5.5 V, 30-pin products: P00, P01, IOL1 = 8.5 mA P10 to P17, P30, P31, P40, 2.7 V VDD 5.5 V, P50, P51, P120, P147 MIN. IOL1 = 3.0 mA 2.7 V VDD 5.5 V, IOL1 = 1.5 mA 1.8 V VDD 5.5 V, IOL1 = 0.6 mA VOL2 P20 to P23 IOL2 = 400 A 0.4 V VOL3 P60, P61 4.0 V VDD 5.5 V, 2.0 V 0.4 V 0.4 V 0.4 V VI = VDD 1 A VI = VDD Input port or external clock input 1 A 10 A -1 A -1 A -10 A 100 k IOL3 = 15.0 mA 4.0 V VDD 5.5 V, IOL3 = 5.0 mA 2.7 V VDD 5.5 V, IOL3 = 3.0 mA 1.8 V VDD 5.5 V, IOL3 = 2.0 mA Input leakage current, ILIH1 Other than P121, P122 high ILIH2 P121, P122 (X1, X2/EXCLK) When resonator connected Input leakage current, ILIL1 Other than P121, VI = VSS P122 low ILIL2 P121, P122 VI = VSS Input port or external (X1, X2/EXCLK) clock input When resonator connected On-chip pull-up <R> RU 20-, 24-pin products: P00 to P03 resistance VI = VSS, input port 10 20 Note , P10 to P14, P40 to P42, P125, RESET <R> 30-pin products: P00, P01, P10 to P17, P30, P31, P40, P50, P51, P120, P147, <R> <R> RESET Note 24-pin products only. Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port pins. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 778 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.3.2 Supply current characteristics (1) 20-, 24-pin products (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD1 Note 1 (1/2) Conditions Note 3 Operating HS(High-speed fIH = 24 MHz Note 2 mode main) mode MIN. Basic VDD = 5.0 V operation VDD = 3.0 V 1.5 Noramal 5.0 3.3 5.0 VDD = 5.0 V 2.5 3.7 VDD = 3.0 V 2.5 3.7 VDD = 3.0 V 1.2 1.8 VDD = 2.0 V 1.2 1.8 Square wave input 2.8 4.4 Resonator connection 3.0 4.6 Square wave input 2.8 4.4 Resonator connection 3.0 4.6 Square wave input 1.8 2.6 Resonator connection 1.8 2.6 Square wave input 1.8 2.6 Resonator connection 1.8 2.6 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 fIH = 8 MHz HS(High-speed fMX = 20 MHz Note 2 , VDD = 5.0 V Note 4 fMX = 20 MHz , VDD = 3.0 V Note 4 fMX = 10 MHz , VDD = 5.0 V Note 4 fMX = 10 MHz , VDD = 3.0 V Note 4 LS(Low-speed main) mode fMX = 8 MHz Note 2 , VDD = 3.0 V Note 4 fMX = 8 MHz , VDD = 2.0 V Notes 1. mA mA mA Note 2 Note 4 main) mode 1.5 3.3 Note 3 Unit mA VDD = 5.0 V Note 3 main) mode MAX. operation VDD = 3.0 V fIH = 16 MHz LS(Low-speed TYP. mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz 3. When high-speed system clock is stopped 4. When high-speed on-chip osicllator clock is stopped. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 779 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol (2/2) Conditions HALT IDD2 Note 1 mode HS(High-speed Note 2 main) mode fIH = 16 MHz Note 4 MAX. Unit VDD = 5.0 V 440 1210 A VDD = 3.0 V 440 1210 VDD = 5.0 V 400 950 fIH = 8 MHz Note 4 VDD = 3.0 V 400 950 VDD = 3.0 V 270 542 VDD = 2.0 V 270 542 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 190 590 Resonator connection 260 660 Square wave input 190 590 Resonator connection 260 660 Note 3 fMX = 20 MHz Note 5 , Square wave input 110 360 Resonator connection 150 416 Square wave input 110 360 Resonator connection 150 416 VDD = 5.0 V fMX = 20 MHz Note 5 , VDD = 3.0 V fMX = 10 MHz Note 5 , VDD = 5.0 V fMX = 10 MHz Note 5 , VDD = 3.0 V LS(Low-speed main) mode Note 3 fMX = 8 MHz Note 5 , VDD = 3.0 V fMX = 8 MHz Note 5 , VDD = 2.0 V STOP IDD3 mode Notes 1. A A Note 3 HS(High-speed main) mode fIH = 24 MHz TYP. Note 3 LS(Low-speed main) mode MIN. Note 4 A A A A A A A TA = -40C 0.19 TA = +25C 0.24 0.50 TA = +50C 0.25 0.80 TA = +70C 0.28 1.20 TA = +85C 0.88 2.20 Note 6 Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: 4. VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz When high-speed system clock is stopped. 5. When high-speed on-chip oscillator clock is stopped. 6. When high-speed on-chip oscillator clock, high-speed system clock, and watchdog timer are stopped. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except temperature condition of the TYP. value is TA = 25C, other than STOP mode R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 780 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) 30-pin products (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply <R> current Symbol IDD1 Note 1 (1/2) Conditions Note 3 Operating HS(High-speed fIH = 24 MHz mode main) mode MIN. Basic Note 2 VDD = 5.0 V 1.5 operation VDD = 3.0 V 1.5 Noramal 3.7 5.5 3.7 5.5 VDD = 5.0 V 2.7 4.0 VDD = 3.0 V 2.7 4.0 VDD = 3.0 V 1.2 1.8 VDD = 2.0 V 1.2 1.8 Square wave input 3.0 4.6 Resonator connection 3.2 4.8 Square wave input 3.0 4.6 Resonator connection 3.2 4.8 Square wave input 1.9 2.7 Resonator connection 1.9 2.7 Square wave input 1.9 2.7 Resonator connection 1.9 2.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 Square wave input 1.1 1.7 Resonator connection 1.1 1.7 Note 3 main) mode fIH = 8 MHz <R> HS(High-speed fMX = 20 MHz <R> main) mode Note 2 <R> , VDD = 5.0 V Note 4 fMX = 20 MHz , VDD = 3.0 V <R> Note 4 fMX = 10 MHz , VDD = 5.0 V <R> Note 4 fMX = 10 MHz , VDD = 3.0 V Note 4 LS(Low-speed main) mode fMX = 8 MHz Note2 <R> , VDD = 3.0 V Note 4 fMX = 8 MHz , VDD = 2.0 V Notes 1. mA mA mA Note2 Note 4 <R> Unit mA VDD = 5.0 V Note 3 LS(Low-speed MAX. operation VDD = 3.0 V fIH = 16 MHz <R> TYP. mA mA mA mA mA mA Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current (except for background operation (BGO)). However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz 3. When high-speed system clock is stopped 4. When high-speed on-chip osicllator clock is stopped. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Temperature condition of the TYP. value is TA = 25C. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 781 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Supply current Symbol IDD2 Note 1 (2/2) Conditions HALT mode HS(High-speed Note 2 main) mode fIH = 16 MHz Note 4 fIH = 8 MHz Note 4 Note 3 fMX = 20 MHz Note 5 , VDD = 5.0 V fMX = 20 MHz Note 5 , VDD = 3.0 V fMX = 10 MHz Note 5 , VDD = 5.0 V fMX = 10 MHz Note 5 , VDD = 3.0 V LS(Low-speed main) mode Note 3 fMX = 8 MHz Note 5 , VDD = 3.0 V fMX = 8 MHz Note 5 , VDD = 2.0 V IDD3 STOP mode Notes 1. MAX. Unit VDD = 5.0 V 440 1280 A VDD = 3.0 V 440 1280 VDD = 5.0 V 400 1000 VDD = 3.0 V 400 1000 VDD = 3.0 V 260 530 VDD = 2.0 V 260 530 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 280 1000 Resonator connection 450 1170 Square wave input 190 600 Resonator connection 260 670 Square wave input 190 600 Resonator connection 260 670 Square wave input 95 330 Resonator connection 145 380 Square wave input 95 330 Resonator connection 145 380 A A Note 3 HS(High-speed main) mode fIH = 24 MHz TYP. Note 3 LS(Low-speed main) mode MIN. Note 4 A A A A A A A TA = -40C 0.18 TA = +25C 0.23 0.50 TA = +50C 0.26 1.10 TA = +70C 0.29 1.90 TA = +85C 0.90 3.30 Note 6 Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is fixed to VDD or VSS. The values below the MAX. column include the peripheral operation current. However, not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down resistors. 2. During HALT instruction execution by flash memory. 3. Relationship between operation voltage width, operation frequency of CPU and operation mode is as follows. HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz VDD = 2.4 V to 5.5 V @1 MHz to 16 MHz LS(Low speed main) mode: 4. VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz When high-speed system clock is stopped. 5. When high-speed on-chip oscillator clock is stopped. 6. When high-speed on-chip oscillator clock, high-speed system clock, and watchdog timer are stopped. The values below the MAX. column include the leakage current. Remarks 1. fMX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock frequency) 2. fIH: high-speed on-chip oscillator clock frequency 3. Except STOP mode, temperature condition of the TYP. value is TA = 25C. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 782 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) Common to RL78/G12 all products (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Notes 1, 2 fIL = 15 kHz 0.22 A IWDT Notes 1, 3 fIL = 15 kHz 0.22 A A/D converter operating current IADC Note 4 When conversion at maximum speed A/D converter reference voltage current IADREF Temperature sensor operating current ITMPS LVD operating ILVD 12-bit interval ITMKA timer operating current Watchdog timer operating current Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA 75.0 A 75.0 A Note 6 0.08 A Note 7 2.50 12.20 mA 0.50 0.60 mA 1.20 1.44 mA 0.70 0.84 mA Note 5 Note 5 current BGO operating IBGO current SNOOZE ISNOZ Note 5 ADC operation The mode is performed Note 8 operating The A/D conversion operations are current performed, Low voltage mode, AVREFP = VDD = 3.0 V CSI/UART operation Notes 1. When high speed on-chip oscillator and high-speed system clock are stopped. 2. Current flowing only to the 12-bit interval timer (including the operating current of the low-speed on-chip oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB when the watchdog timer operates in STOP mode. 3. Current flowing only to the watchdog timer (including the operating current of the 15 KHz low-speed on-chip oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when fCLK = fSUB when the watchdog timer operates in STOP mode. 4. Current flowing only to the A/D converter. The current value of the RL78/G12 microcontrollers is the sum of IDD1 or IDD2 and IADC when the A/D converter operates in an operation mode or the HALT mode. 5. Current flowing to the VDD. 6. Current flowing only to the LVD circuit. The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IVLD when the LVD circuit operates in the Operating, HALT or STOP mode. 7. Current flowing only to the BGO. The current value of the RL78/G12 microcontrollers is the sum of IDD1 or IDD2 and IBGO when the BGO operates in an operation mode. 8. Refer to shift time to the SNOOZE mode, see 17.2.3 SNOOZE mode.. Remarks 1. fIL: Low-speed on-chip oscillator clock frequency 2. fCLK: CPU/peripheral hardware clock frequency 3. Temperature condition of the TYP. value is TA = 25C R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 783 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.4 AC Characteristics (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Items Instruction cycle (minimum Symbol TCY Conditions fEX External main system clock tEXH, tEXL input high-level width, lowlevel width TI00 to TI07 input high-level MAX. Unit 0.04167 1 s 2.4 V VDD < 2.7 V 0.0625 1 s 1.8 V VDD 5.5 V 0.125 1 s 2.7 V VDD 5.5 V 1.0 20.0 MHz 1.8 V VDD < 2.7 V 1.0 8.0 MHz 2.7 V VDD 5.5 V 24 ns 1.8 V VDD < 2.7 V 60 ns 1/fMCK + 10 ns LS(Low-speed main) mode frequency TYP. 2.7 V VDD 5.5 V HS(High-speed main) mode instruction execution time) External main system clock MIN. tTIH, tTIL width, low-level width TO00 to TO07 output fTO frequency PCLBUZ0, or PCLBUZ1 fPCL output frequency INTP0 to INTP5 input high- 4.0 V VDD 5.5 V 12 MHz 2.7 V VDD < 4.0 V 8 MHz 1.8 V VDD < 2.7 V 4 MHz 4.0 V VDD 5.5 V 16 MHz 2.7 V VDD < 4.0 V 8 MHz 1.8 V VDD < 2.7 V 4 MHz 1 s tKR 250 ns tRSL 10 s tINTH, tINTL level width, low-level width KR0 to KR9 input available width RESET low-level width Remark fMCK: Timer array unit operation clock frequency (Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0 to 7)) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 784 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS AC Timing Test Point VIH VIL VIH Test points VIL External main system clock timing 1/fEX tEXL tEXH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.) TI timing tTIH tTIL TI00 to TI07 Interrupt Request Input Timing tINTH tINTL INTP0 to INTP5 Key Interrupt Input Timing tKR KR0 to KR9 RESET input timing tRSL RESET R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 785 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.5 Serial Communication Characteristics 28.5.1 Serial array unit (1) During communication at same potential (UART mode) (dedicated baud rate generator output) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Transfer rate Conditions MIN. Normal operation TYP. MAX. Unit fMCK/6 bps 4.0 Mbps 9600 bps Theoretical value of the maximum transfer rate fCLK = fMCK = 24 MHz SNOOZE mode 4800 UART mode connection diagram (during communication at same potential) Rx TxDq User's device RL78/G12 Tx RxDq UART mode bit width (during communication at same potential) (reference) 1/Transfer rate High-/Low-bit width Baud rate error tolerance TxDq RxDq Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg) Remarks 1. 2. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 786 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) During communication at same potential (CSI00 master mode (fMCK/2), SCK00... internal clock output) (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCK00 cycle time SCK00 high - /low-level width SI00 setup time (to SCK00) SI00 hold time (to SCK00) Note 2 Note2 Delay time from SCK00 to SO00 output Notes 1. 2. MIN. tKCY1 2.7 V VDD 5.5 V 83.3 TYP. MAX. Unit Note 1 ns tKH1, 4.0 V VDD 5.5 V tKCY1/2 - 7 ns tKL1 2.7 V VDD 5.5 V tKCY1/2 - 10 ns tSIK1 4.0 V VDD 5.5 V 23 ns 2.7 V VDD 5.5 V 33 ns 2.7 V VDD 5.5 V 10 ns tKSI1 Note 4 Conditions tKSO1 Note 5 C = 20 pF 10 ns The value must also be 2/fCLK or more. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes "to SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 3. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes "from SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 4. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes "from SCK00" when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. 5. C is the load capacitance of the SCK00 and SO0 output lines. Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00 pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1). Remarks 1. This specification is valid only when CSI00's peripheral I/O redirect function is not used. 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKS00 bit of serial mode register (SMR00). R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 787 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY1 Conditions MIN. 2.7 V VDD 5.5 V 2.4 V VDD 5.5 V 1.8 V VDD 5.5 V SCKp high-/low-level width Note 2 SIp setup time (to SCKp) Note 3 SIp hold time (from SCKp) Delay time from SCKp to SOp output TYP. MAX. Unit 167 Note 1 ns 250 Note 1 ns 500 Note 1 ns tKH1, 4.0 V VDD 5.5 V tKCY1/2 - 12 ns tKL1 2.7 V VDD 5.5 V tKCY1/2 - 18 ns 2.4 V VDD 5.5 V tKCY1/2 - 38 ns 1.8 V VDD 5.5 V tKCY1/2 - 50 ns tSIK1 4.0 V VDD 5.5 V 44 ns 2.7 V VDD 5.5 V 44 ns 2.4 V VDD 5.5 V 75 ns 1.8 V VDD 5.5 V 110 ns 19 ns tKSI1 tKSO1 Note 5 C = 30 pF 25 ns Note 4 Notes 1. 2. The value must also be 4/fCLK or more. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 5. C is the load capacitance of the SCKp and SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0, POM1). Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unito number (m = 0, 1), n: Channel number (n = 0, 1, 3: "1, 3" is for the R5F102 products.) <R> 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: <R> Channel number (n = 0, 1, 3; "1, 3" is for the R5F102 products.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 788 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY2 Conditions MIN. 2.7 V VDD < 4.0 V 1.8 V VDD < 2.7 V Unit 20 MHz < fMCK 8/fMCK ns fMCK 20 MHz 6/fMCK ns 16 MHz < fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK ns 16 MHz < fMCK 8/fMCK ns fMCK 16 MHz 6/fMCK ns SNOOZE mode tKH2, MAX. Normal operation 4.0 V VDD 5.5 V SCKp high-/low-level width TYP. 1 Mbps 1.8 V VDD 5.5 V tKCY2/2 ns 2.7 V VDD 5.5 V 1/fMCK+20 ns 1.8 V VDD < 2.7 V 1/fMCK+30 ns 1/fMCK+31 ns tKL2 SIp setup time (to SCKp) Note 1 SIp hold time (from SCKp) Note 2 Delay time from SCKp to SOp output tSIK2 tKSI2 tKSO2 C = 30 pF Note 3 Notes 1. Note 4 2.7 V VDD 5.5 V 2/fMCK+44 ns 2.4 V VDD < 2.7 V 2/fMCK+75 ns 1.8 V VDD < 2.4 V 2/fMCK+110 ns When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 4. C is the load capacitance of the SOp output lines. Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0, POM1). Remarks 1. <R> p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3; "1, 3" is for the R5F102 products.) 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: <R> Channel number (n = 0, 1, 3; "1, 3" is for the R5F102 products.) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 789 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI mode connection diagram (during communication at same potential) SCK SCKp RL78/G12 SIp SO SOp SI User's device CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1, 2 tKL1, 2 tKH1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Output data CSI mode serial transfer timing (during communication at same potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1, 2 tKH1, 2 tKL1, 2 SCKp tSIK1, 2 SIp tKSI1, 2 Input data tKSO1, 2 SOp Remarks 1. 2. Output data p: CSI number (p = 00, 01, 11, 20) n: Channel number (0, 1, 3) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 790 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 2 (5) During communication at same potential (simplified I C mode) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol SCLr clock frequency fSCL Conditions MIN. Typ. 1.8 V VDD 5.5 V, MAX. Unit 400 kHz 300 kHz Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "L" tLOW 1.8 V VDD 5.5 V, 1150 ns 1550 ns 1150 ns 1550 ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Hold time when SCLr = "H" tHIGH 1.8 V VDD 5.5 V, Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data setup time (reception) tSU:DAT 1.8 V VDD 5.5 V, 1/fMCK + 145 Note ns 1/fMCK + 230 Note ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Data hold time (transmission) tHD:DAT 1.8 V VDD 5.5 V, 0 355 ns 0 405 ns Cb = 100 pF, Rb = 3 k 1.8 V VDD < 2.7 V, Cb = 100 pF, Rb = 5 k Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register h (POMh). Remarks 1. Rb []:Communication line (SDAr) pull-up resistance Cb [F]: Communication line (SCLr, SDAr) load capacitance 2. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0, 1), n: Channel number (0, 1, 3) <R> 4. 2 Simplified I C mode is supported by the R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 791 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 2 Simplified I C mode connection diagram (during communication at same potential) VDD Rb SDA SDAr RL78/G12 User's device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at same potential) tLOW tHIGH SCLr SDAr tHD : DAT R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 tSU : DAT 792 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UART mode) (dedicated baud rate generator output) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate Symbol Conditions MIN. TYP. MAX. Unit fMCK/6 bps 4.0 Mbps 4.0 Mbps 1.3 Mbps Note 1 bps Normal operation Note 1 Reception 4.0 V VDD 5.5 V, Theoretical maximum 2.7 V Vb 4.0 V transfer rate fCLK = fMCK = 24 MHz 2.7 V VDD < 4.0 V, Theoretical maximum 2.3 V Vb 2.7 V transfer rate fCLK = fMCK = 24 MHz 1.8 V VDD < 3.3 V, Theoretical maximum 1.6 V Vb 2.0 V transfer rate fCLK = fMCK = 8 MHz Transmissio 4.0 V VDD 5.5 V, n 2.7 V Vb 4.0 V Theoretical maximum 2.8 Note 2 Mbps transfer rate Cb = 50 pF, Rb = 1.4 k, Vb = 2.7 V 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V Note 3 Theoretical maximum 1.2 Note 4 bps Mbps transfer rate Cb = 50 pF, Rb = 2.7 k, Vb = 2.3 V 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V Note 5 Note 6 Theoretical maximum 0.43 bps Mbps transfer rate Cb = 50 pF, Rb = 5.5 k, Vb = 1.6 V SNOOZE mode Notes 1. 4800 9600 bps The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 4.0 V VDD 5.5 V and 2.7 V Vb 4.0 V 1 Maximum transfer rate = 2.2 {-Cb x Rb x ln (1 - Vb )} x 3 Baud rate error (theoretical value) = [bps] 1 2.2 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 2. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 1 above to calculate the maximum transfer rate under conditions of the customer. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 793 RL78/G12 3. CHAPTER 28 ELECTRICAL SPECIFICATIONS The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 2.7 V VDD < 4.0 V and 2.3 V Vb 2.7 V 1 Maximum transfer rate = 2.0 {-Cb x Rb x ln (1 - Vb )} x 3 Baud rate error (theoretical value) = [bps] 1 2.0 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 4. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 3 above to calculate the maximum transfer rate under conditions of the customer. 5. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid maximum transfer rate. Expression for calculating the transfer rate when 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V 1 Maximum transfer rate = 1.5 {-Cb x Rb x ln (1 - Vb )} x 3 Baud rate error (theoretical value) = [bps] 1 1.5 - {-Cb x Rb x ln (1 - Vb )} Transfer rate x 2 1 ( Transfer rate ) x Number of transferred bits x 100 [%] * This value is the theoretical value of the relative difference between the transmission and reception sides. 6. This value as an example is calculated when the conditions described in the "Conditions" column are met. Refer to Note 5 above to calculate the maximum transfer rate under conditions of the customer. Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). (In 20- or 24-pin products, redirect to P6 is not supported.) Remarks 1. Rb []:Communication line (TxDq) pull-up resistance, Cb [F]: Communication line (TxDq) load capacitance, Vb [V]: Communication line voltage 2. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n: Channel number (mn = 00 to 03, 10, 11) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 794 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS UART mode connection diagram (during communication at different potential) Vb Rb Rx TxDq RL78/G12 User's device Tx RxDq UART mode bit width (during communication at different potential) (reference) 1/Transfer rate Low-bit width High-bit width Baud rate error tolerance TxDq 1/Transfer rate High-/Low-bit width Baud rate error tolerance RxDq Remarks 1. 2. Rb []: Communication line (TxD0) pull-up resistance, Vb [V]: Communication line voltage q = UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 795 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (7) Communication at different potential (2.5 V, 3 V) (CSI00 mode) (CSI00 master mode (fMCK/2), SCK00... internal clock output) (TA = -40 to +85C, 2.7 V VDD 5.5 V, VSS = 0 V) Parameter SCK00 cycle time Symbol tKCY1 Conditions 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 200 Note 1 ns 300 Note 1 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCK00 high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 - 50 ns tKCY1/2 - 120 ns tKCY1/2 - 7 ns tKCY1/2 - 10 ns 58 ns 121 ns 10 ns 10 ns Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SCK00 low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 setup time (to SCK00) tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 hold time (from SCK00) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCK00 to SO00 output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 60 ns 130 ns Note 2 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 setup time (to SCK00) tSIK1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 23 ns 33 ns 10 ns 10 ns Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k SI00 hold time (from SCK00) tKSI1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Delay time from SCK00 to SO00 output tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 10 ns 10 ns Note 3 Cb = 20 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 20 pF, Rb = 2.7 k Notes 1. The value must also be 2/fCLK or more. 2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1 3. When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 796 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode register 1 (POM1) (Redirect to P0 is not supported in 24-pin products). Remarks 1. Rb []:Communication line (SCK00, SOp) pull-up resistance, Cb [F]: Communication line (SCK00, SO00) load capacitance, Vb [V]: Communication line voltage 2. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKS00 bit of serial mode register (SMR00). CSI mode connection diagram (during communication at different potential) Vb <Master> Rb SCK00 RL78/G12 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Vb Rb SCK SI00 SO SO00 SI User's device 797 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI00 mode) (master mode, SCKp... internal clock output) (1/2) (TA = -40 to +85C, 1.8 V VDD VDD 5.5 V, VSS = 0 V) Parameter Symbol SCKp cycle time tKCY1 Conditions 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 300 Note ns 500 Note ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, 1150 Note ns Cb = 30 pF, Rb = 5.5 k SCKp high-level width tKH1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, tKCY1/2 -75 ns tKCY1/2 -170 ns tKCY1/2 -458 ns tKCY1/2 -12 ns tKCY1/2 -18 ns tKCY1/2 -50 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SCKp low-level width tKL1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Note The value must also be 4/fCLK or more. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at different potential is not allowed in CSI01, CSI11. Remarks 1. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 798 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal clock output) (2/2) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter SIp setup time (to SCKp) Symbol tSIK1 Note 1 Conditions 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MIN. TYP. MAX. Unit 81 ns 177 ns 479 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) tKSI1 Note 1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 100 ns 195 ns 483 ns Cb = 30 pF, Rb = 1.4 k SCKp to Note 1 SOp output 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp setup time (to SCKp) tSIK1 Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 44 ns 44 ns 110 ns 19 ns 19 ns 19 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k SIp hold time (from SCKp) tKSI1 Note 2 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Delay time from tKSO1 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 25 ns 25 ns 25 ns Cb = 30 pF, Rb = 1.4 k SCKp to SOp output Note 2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. 2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at different potential is not allowed in CSI01, CSI11. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 799 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS Remarks 1. Rb []: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) CSI mode connection diagram (during communication at different potential) Vb <Master> Vb Rb Rb SCK SCKp RL78/G12 SIp SO SOp SI User's device CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Output data 800 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (master mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Output data 801 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter SCKp cycle time Symbol tKCY2 Conditions MIN. TYP. MAX. Unit Noromal operation 4.0 V VDD 5.5 V, 20 MHz < fMCK 24 MHz 12/fMCK ns 2.7 V Vb 4.0 V 8 MHz < fMCK 20 MHz 10/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 2.7 V VDD < 4.0 V, 20 MHz < fMCK 24 MHz 16/fMCK ns 2.3 V Vb 2.7 V 16 MHz < fMCK 20 MHz 14/fMCK ns 8 MHz < fMCK 16 MHz 12/fMCK ns 4 MHz < fMCK 8 MHz 8/fMCK ns fMCK 4 MHz 6/fMCK ns 1.8 V VDD < 3.3 V, 20 MHz < fMCK 24 MHz 36/fMCK ns 1.6 V Vb 2.0 V 16 MHz < fMCK 20 MHz 32/fMCK ns 8 MHz < fMCK 16 MHz 26/fMCK ns 4 MHz < fMCK 8 MHz 16/fMCK ns fMCK 4 MHz 10/fMCK ns SNOOZE mode 1 Mbps SCKp high-/low-level tKH2, 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V tKCY2/2 - 12 ns width tKL2 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V tKCY2/2 - 18 ns 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V tKCY2/2 - 50 ns 2.7 V VDD < 5.5 V 1/fMCK + 20 ns 1.8 V VDD < 3.3 V 1/fMCK + 30 ns 1/fMCK + 31 ns SIp setup time (to SCKp) tSIK2 Note 1 SIp hold time (from SCKp) tKSI2 Note 2 Delay time from tKSO2 SCKp to SOp output Note 3 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 2/fMCK + 120 ns 2/fMCK + 214 ns 2/fMCK + 573 ns Cb = 30 pF, Rb = 1.4 k 2.7 V VDD < 4.0 V, 2.3 V Vb 2.7 V, Cb = 30 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 30 pF, Rb = 5.5 k Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes "to SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. 3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output becomes "from SCKp" when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0. Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for the SOp and SCKp pins by using port input mode register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at different potential is not allowed in CSI01, CSI11. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 802 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS Remarks 1. Rb []: Communication line (SOp) pull-up resistance, Cb [F]: Communication line (SOp) load capacitance, Vb [V]: Communication line voltage 2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn) CSI mode connection diagram (during communication at different potential) Vb <Slave> Rb SCK SCKp RL78/G12 SIp SO User's device SI SOp CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.) tKCY1 tKL1 tKH1 SCKp tSIK1 SIp tKSI1 Input data tKSO1 SOp R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Output data 803 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS CSI mode serial transfer timing (slave mode) (during communication at different potential) (When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.) tKCY2 tKL2 tKH2 SCKp tSIK2 tKSI2 Input data SIp tKSO2 SOp R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Output data 804 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 2 (10) Communication at different potential (1.8 V, 2.5 V, 3 V) (simplified I C mode) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter SCLr clock frequency Symbol fSCL Conditions MIN. 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, MAX. Unit 400 kHz 400 kHz 300 kHz Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "L" tLOW 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 1150 ns 1150 ns 1550 ns 675 ns 600 ns 610 ns 1/fMCK Note ns 1/fMCK Note ns 1/fMCK Note ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Hold time when SCLr = "H" tHIGH 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Data setup time (reception) tSU:DAT 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, +190 Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, +190 Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, +190 Cb = 100 pF, Rb = 5.5 k Data hold time (transmission) tHD:DAT 4.0 V VDD 5.5 V, 2.7 V Vb 4.0 V, 0 355 ns 0 355 ns 0 405 ns Cb = 100 pF, Rb = 2.8 k 2.7 V VDD < 4.0 V, 2.3 V Vb < 2.7 V, Cb = 100 pF, Rb = 2.7 k 1.8 V VDD < 3.3 V, 1.6 V Vb 2.0 V, Cb = 100 pF, Rb = 5.5 k Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H". Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1). Communication at different potential is not allowed in IIC01, IIC11. Remarks 1. Rb []: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr) load capacitance, Vb [V]: Communication line voltage 2. r: IIC Number (r = 00, 20) 3. fMCK: Serial array unit operation clock frequency (Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number (m = 0,1), n: Channel number (n = 0)) <R> 4. 2 Simplified I C mode is supported by the R5F102 products. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 805 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 2 Simplified I C mode connection diagram (during communication at different potential) Vb Rb Vb Rb SDA SDAr RL78/G12 User's device SCL SCLr 2 Simplified I C mode serial transfer timing (during communication at different potential) 1/f SCL t LOW t HIGH SCLr SDAr t HD : DAT R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 t SU : DAT 806 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.5.2 Serial interface IICA (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Symbol Conditions Standard Mode MIN. SCLA0 clock frequency fSCL Fast mode: fCLK 3.5 MHz Normal mode: fCLK 1 MHz Setup time of restart condition Note 1 MAX. 0 tSU:STA Fast Mode Unit MIN. MAX. 0 400 kHz 100 4.7 kHz 0.6 s Hold time tHD:STA 4.0 0.6 s Hold time when SCLA0 = "L" tLOW 4.7 1.3 s Hold time when SCLA0 = "H" tHIGH 4.0 0.6 s tSU:DAT 250 100 ns tHD:DAT 0 Setup time of stop condition tSU:STO 4.0 0.6 s Bus-free time tBUF 4.7 1.3 s Data setup time (reception) Data hold time (transmission) Notes 1. 2. Note 2 3.45 0 s 0.9 The first clock pulse is generated after this period when the start/restart condition is detected. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK (acknowledge) timing. The maximum value of Cb (communication line capacitance) and the value of Rb (communication line pull-up Remark resistor) at that time in each mode are as follows. Normal mode: Fast mode: Cb = 400 pF, Rb = 2.7 k Cb = 320 pF, Rb = 1.1 k IICA serial transfer timing t LOW tR SCLA0 tHD:DAT t HIGH tF tSU:STA tHD:STA tSU:STO tSU:DAT tHD:STA SDAA0 t BUF Stop condition Start condition Restart condition Stop condition 28.5.3 On-chip debug (UART) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter Transfer rate R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Symbol Conditions MIN. 115.2 k TYP. MAX. Unit 1M bps 807 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.6 Analog Characteristics 28.6.1 A/D converter characteristics (1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), (target ANI pin : ANI2, ANI3) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM = 0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error Conversion time Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Differential linearity error Note 1 MIN. TYP. 8 AINL 10-bit resolution tCONV AVREFP = VDD 1.2 MAX. Unit 10 bit 3.5 LSB 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s EZS 0.25 %FSR EFS 0.25 %FSR ILE 2.5 LSB DLE 1.5 LSB 1.8 VDD V 0 AVREFP V 1.50 V Reference voltage (+) AVREFP Analog input voltage VAIN VBGR Internal reference voltage is selected 1.38 1.45 2.4 V VDD 5.5 V HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 808 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) When AVREF (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (-) = AVREFM/ANI1 (ADREFM = 1), (target ANI pin : ANI16 to ANI22) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference voltage (-) = AVREFM =0 V) Parameter Symbol Resolution Conditions RES Note 1 Overall error Conversion time Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Differential linearity error Note 1 MIN. TYP. 8 AINL 10-bit resolution tCONV AVREFP = VDD 1.2 MAX. Unit 10 bit 5.0 LSB 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s EZS 0.35 %FSR EFS 0.35 %FSR ILE 3.5 LSB DLE 2.0 LSB VDD V AVREFP V Reference voltage (+) AVREFP Analog input voltage VAIN 1.8 0 and VDD VBGR Internal reference voltage is selected 1.38 1.45 1.5 V 2.4 V VDD 5.5 V HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 809 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS (3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (-) = VSS (ADREFM = 0), (target ANI pin : ANI0 to ANI3, ANI16 to ANI22) (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (-) = VSS) Parameter Symbol Resolution Conditions RES Note 1 Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error Notes 1, 2 Full-scale error Integral linearity error Note 1 Differential linearity error Note 1 Analog input voltage MIN. TYP. 8 10-bit resolution 1.2 MAX. Unit 10 bit 7.0 LSB 3.6 V VDD 5.5 V 2.125 39 s 2.7 V VDD 5.5 V 3.1875 39 s 1.8 V VDD 5.5 V 17 39 s EZS 0.60 %FSR EFS 0.60 %FSR ILE 4.0 LSB DLE 2.0 LSB VDD V 1.50 V VAIN VBGR 0 Internal reference voltage is selected 1.38 1.45 2.4 V VDD 5.5 V HS (high-speed main) mode Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. (4) When AVREF (+) = Internal reference voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (-) = AVREFM (ADREFM = 1), (target ANI pin : ANI0, ANI2, ANI3, ANI16 to ANI22) (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR, Reference voltage (-) = AVREFM = 0 V, HS (high-speed main) mode) Parameter Symbol Resolution Conditions MIN. RES Conversion time Notes 1, 2 Zero-scale error Integral linearity error Note 1 Differential linearity error Note 1 TYP. MAX. 8 Unit bit 39 s 0.60 %FSR ILE 2.0 LSB DLE 1.0 LSB 1.5 V VBGR V tCONV 8-bit resolution EZS AVREFM = 0 V, 2.4 V VDD 5.5 V 17 Reference voltage (+) VBGR 1.38 Analog input voltage VAIN 0 1.45 Notes 1. Excludes quantization error (1/2 LSB). 2. This value is indicated as a ratio (%FSR) to the full-scale value. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 810 RL78/G12 <R> CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.6.2 Temperature sensor/internal reference voltage characteristics (TA = -40 to +85C, 2.4 V VDD 5.5 V, VSS = 0 V, HS (high-speed main) mode Parameter Temperature sensor output voltage Symbol VTMPS25 Conditions MIN. Setting ADS register = 80H, TYP. MAX. 1.05 Unit V TA = +25C <R> Internal reference voltage VCONST Setting ADS register = 81H Temperature coefficient FVTMPS Temperature sensor that 1.38 1.45 1.5 -3.6 V mV/C depends on the temperature Operation stabilization wait time tAMP 5 s 28.6.3 POR circuit characteristics (TA = -40 to +85C, VSS = 0 V) Parameter Detection voltage Minimum pulse width Detection delay time R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Symbol Conditions MIN. TYP. MAX. Unit VPOR Power supply rise time 1.48 1.51 1.54 V VPDR Power supply fall time 1.47 1.50 1.53 V TPW s 300 350 s 811 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.6.4 LVD circuit characteristics LVD Detection Voltage of Reset Mode and Interrupt Mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Detection supply voltage Symbol VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VLVD8 VLVD9 VLVD10 VLVD11 Minimum pulse width Detection delay time R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 tLW Conditions MIN. TYP. MAX. Unit Power supply rise time 3.98 4.06 4.14 V Power supply fall time 3.90 3.98 4.06 V Power supply rise time 3.68 3.75 3.82 V Power supply fall time 3.60 3.67 3.74 V Power supply rise time 3.07 3.13 3.19 V Power supply fall time 3.00 3.06 3.12 V Power supply rise time 2.96 3.02 3.08 V Power supply fall time 2.90 2.96 3.02 V Power supply rise time 2.86 2.92 2.97 V Power supply fall time 2.80 2.86 2.91 V Power supply rise time 2.76 2.81 2.87 V Power supply fall time 2.70 2.75 2.81 V Power supply rise time 2.66 2.71 2.76 V Power supply fall time 2.60 2.65 2.70 V Power supply rise time 2.56 2.61 2.66 V Power supply fall time 2.50 2.55 2.60 V Power supply rise time 2.45 2.50 2.55 V Power supply fall time 2.40 2.45 2.50 V Power supply rise time 2.05 2.09 2.13 V Power supply fall time 2.00 2.04 2.08 V Power supply rise time 1.94 1.98 2.02 V Power supply fall time 1.90 1.94 1.98 V Power supply rise time 1.84 1.88 1.91 V Power supply fall time 1.80 1.84 1.87 V s 300 300 s 812 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS LVD detection voltage of interrupt & reset mode (TA = -40 to +85C, VPDR VDD 5.5 V, VSS = 0 V) Parameter Symbol LVD detection VLVD11 voltage VLVD10 VLVD9 VLVD2 VLVD8 VLVD7 VLVD6 VLVD1 VLVD5 VLVD4 VLVD3 VLVD0 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 Conditions VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V MIN. TYP. MAX. Unit 1.80 1.84 1.87 V LVIS1, LVIS0 = 1, 0 Rising reset release voltage 1.94 1.98 2.02 V (+0.1 V) Falling interrupt voltage 1.90 1.94 1.98 V LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.05 2.09 2.13 V (+0.2 V) Falling interrupt voltage 2.00 2.04 2.08 V LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.07 3.13 3.19 V (+1.2 V) Falling interrupt voltage 3.00 3.06 3.12 V VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V 2.40 2.45 2.50 V LVIS1, LVIS0 = 1, 0 Rising reset release voltage 2.56 2.61 2.66 V (+0.1 V) Falling interrupt voltage 2.50 2.55 2.60 V LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.66 2.71 2.76 V (+0.2 V) Falling interrupt voltage 2.60 2.65 2.70 V LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.68 3.75 3.82 V (+1.2 V) Falling interrupt voltage 3.60 3.67 3.74 V VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage: 2.7 V 2.70 2.75 2.81 V LVIS1, LVIS0 = 1, 0 Rising reset release voltage 2.86 2.92 2.97 V (+0.1 V) Falling interrupt voltage 2.80 2.86 2.91 V LVIS1, LVIS0 = 0, 1 Rising reset release voltage 2.96 3.02 3.08 V (+0.2 V) Falling interrupt voltage 2.90 2.96 3.02 V LVIS1, LVIS0 = 0, 0 Rising reset release voltage 3.98 4.06 4.14 V (+1.2 V) Falling interrupt voltage 3.90 3.98 4.06 V 813 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR 1.47 TYP. Note MAX. Unit 5.5 V Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR reset is affected, but data is not retained when a POR reset is affected. Operation mode STOP mode Data retention mode VDD VDDDR STOP instruction execution Standby release signal (interrupt request) 28.8 Flash Memory Programming Characteristics <R> (TA = -40 to +85C, 1.8 V VDD 5.5 V, VSS = 0 V) Parameter System clock frequency Code flash memory rewritable times Symbol fCLK Cerwr Conditions MIN. 1.8 V VDD 5.5 V TYP. 1 Retained for 20 years TA = 85C Note 3 Retained for 1 year TA = 25C Note 3 Retained for 5 years TA = 85C Note 3 100,000 Retained for 20 years TA = 85C Note 3 10,000 MAX. Unit 24 MHz Times 1,000 Notes 1.2.3 Data flash memory rewritable times Notes 1.2.3 <R> 1,000,000 Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite. The retaining years are until next rewrite after the rewrite. 2. When using flash memory programmer and Renesas Electronics self program library. <R> 3. These are the characteristics of the flash memory and the results obtained from reliability testing by Renesas Electronics Corporation. Caution This specifications show target values, which may change after device evaluation. Remark When updating data multiple times, use the flash memory as one for updating data. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 814 RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS 28.9 Timing Specs for Flash Memory Programming Switching Modes Parameter <R> Symbol Conditions MIN. TYP. POR and LVD reset are How long from when an external reset ends until tSUINIT the initial communication settings are specified MAX. Unit 100 ms released before external reset release How long from when the TOOL0 pin is placed at tsu <R> 10 s 1 ms the low level until an external reset ends How long the TOOL0 pin must be kept at the low tHD level after a reset ends (except soft processing time) <1> <2> <4> <3> RESET tHD+ software processing time 00H reception (TOOLRxD, TOOLTxD mode) TOOL0 tSU tSUINIT <1> The low level is input to the TOOL0 pin. <R> <2> The external reset ends (POR and LVD reset must end before the pin reset ends.). <3> The TOOL0 pin is set to the high level. <4> Setting of the flash memory programming mode by UART reception and complete the baud rate setting. Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within 100 ms from when the resets end. <R> tSU: How long from when the TOOL0 pin is placed at the low level until an external reset ends. tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end. (except soft processing time) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 815 RL78/G12 CHAPTER 29 PACKAGE DRAWINGS CHAPTER 29 PACKAGE DRAWINGS 29.1 20-pin products R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1 2 D detail of lead end 11 20 E 1 c 10 1 L 3 bp A A2 A1 HE e y (UNIT:mm) NOTE 1.Dimensions " 2.Dimension " 1" and " 2" " does not include tr ITEM DIMENSIONS D E 6.50 0.10 4.40 0.10 HE 6.40 0.20 A 1.45 MAX. A1 0.10 0.10 A2 1.15 e bp c L y 0.65 0.12 0.22 0.10 0.05 0.15 0.05 0.02 0.50 0.20 0.10 0 to 10 2012 Renesas Electronics Corporation. All rights reserved. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 816 RL78/G12 CHAPTER 29 PACKAGE DRAWINGS 29.2 24-pin products R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.04 D DETAIL OF A PART E S A A S y S (UNIT:mm) ITEM D2 A EXPOSED DIE PAD 1 6 D 4.00 0.05 E 4.00 0.05 A 0.75 0.05 b 0.25 0.05 0.07 e 7 24 Lp B DIMENSIONS 0.50 0.40 0.10 x 0.05 y 0.05 E2 ITEM 19 12 18 EXPOSED DIE PAD VARIATIONS 13 D2 E2 MIN NOM MAX MIN NOM MAX A 2.45 2.50 2.55 2.45 2.50 2.55 e Lp b x M S AB 2012 Renesas Electronics Corporation. All rights reserved. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 817 RL78/G12 CHAPTER 29 PACKAGE DRAWINGS 29.3 30-pin products R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g] P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18 30 16 detail of lead end F G T P 1 L 15 U E A H I J S C D N M S B M K ITEM A MILLIMETERS 9.85 0.15 B 0.45 MAX. C 0.65 (T.P.) NOTE D 0.24 0.08 0.07 Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. E 0.1 0.05 F 1.3 0.1 G 1.2 H 8.1 0.2 I 6.1 0.2 J 1.0 0.2 K 0.17 0.03 L 0.5 M 0.13 N 0.10 P 3 T 0.25 U 0.6 0.15 5 3 2012 Renesas Electronics Corporation. All rights reserved. R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 818 RL78/G12 APPENDIX A REVISION HISTORY APPENDIX A REVISION HISTORY A.1 Major Revisions in This Edition (1/4) Page Description Though out Classification Deletion of overbars for SCK(serial clock signal) (c) Titles of register description headlined (c) Change from products with data flash memory to R5F102 products (c) CHAPTER 1 OUTLINE 1 Addition of 1.1 Differences between R5F102 and R5F103 (b) 3 Partial modification of description in 1.2 Features (c) 5 Change from 1.3 Ordering Information to 1.3 List of Part Numbers (c) 5 Modification of Figure 1-1. Part Number, Memory size, and Package of RL78/G12 (c) 5 Addition of Fields of Application to 1.3 List of Part Numbers (c) 9 Partial modification of 1.5 Pin Identification (c) 13 Modification of description and Notes 1 to 3 and addition of Caution in 1.7 Outline of Functions (c) CHAPTER 2 PIN FUNCTIONS 20 Modification of error in 2.2.2 Description of Functions (a) CHAPTER 3 CPU ARCHITECTURE 25, 26 Modification of Note1 and Caution1 and addition of Cautions 2 and 3 in Figure 3-1. Memory Map (c) 27 to 31 Modification of Caution in Figure 3-2 to 3-6. Memory Maps (c) 33 Partial modification of description in 3.1.1 Internal program memory space (c) 38 Addition and modification of Cautions 1 and 2 in Processor mode control register (PMC) (c) 38, 39 Modification of description and Cautions 1 and 2 and addition of Caution 3 in 3.1.3 Internal data (c) memory space 41 Modification of Note 1 and Caution 1 and addition of Cautions 2 and 3 in Figure 3-8. (c) Correspondence Between Data Memory and Addressing 42 to 46 Modification of Caution in Figure 3-9 to Figure 3-13. Correspondence Between Data Memory and (c) Addressing 47, 48 Modification of description and Cautions 2 and 3 and addition of Caution 4 in 3.2.1 Control (c) registers 50 Modification of Cautions 1 and 2 and addition of Caution 3 in 3.2.2 General-purpose registers (c) 51 Modification of description in 3.2.3 ES and CS registers (c) 52 Modification of description in 3.2.4 Special function registers (SFRs) (c) 57 Modification of description in 3.2.5 Extended special function registers (2nd SFRs: 2nd (c) Special Function Registers) 57 Modification of Caution in 3.2.5 Extended special function registers (2nd SFRs: 2nd Special (c) Function Registers) 59 Modification of error in Table 3-7. Extended SFR (2nd SFR) List (2/5) (a) 59 Addition of Note in Table 3-7. Extended SFR (2nd SFR) List (c) 63 to 76 Modification of description in Figure 3-21 to Figure 3-48 (c) 66 Modification of description of [Operand format] in 3.4.3 Direct addressing (c) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 819 RL78/G12 APPENDIX A REVISION HISTORY (2/4) Page Description Classification 68 Modification of description of [Operand format] in 3.4.5 SFR addressing (c) 70 Modification of description of [Function] in 3.4.7 Based addressing (c) 74 Modification of description of [Function] and [Format] in 3.4.9 Stack addressing (c) CHAPTER 4 PORT FUNCTION 95 Modification of error in Table 4-7. Settings of Registers When Using Port 6 (20-, 24-pin Products) (a) 128 Modification of error in Figure 4-34. Format of Port Registers (a) CHAPTER 5 CLOCK GENERATOR 151 Modification of Caution 5 and deletion of Cautions 6 and 7 in Figure 5-2. Format of Clock (c) Operation Mode Control register (CMC) 160 Modification of Cautions 1 to 3 in 5.3.8 High-speed on-chip oscillator frequency selection (c) register (HOCODIV) 166 Modification of Note 3 in Figure 5-13. Clock Generator Operation When Power Supply Voltage Is (b) Turned On (When voltage detector (LVD) is used) 167 Modification of [Option byte setting] in 5.6.1 Example of setting high-speed on-chip oscillator (c) 174 Addition of 5.7 Resonator and Oscillator Constants (b) CHAPTER 6 TIMER ARRAY UNIT 188 Modification of description in (2) Timer data register 0n (TDR0n) (a) 192 Modification of error in Figure 6-8. Format of Timer Clock Select Register 0 (TPS0) (a) 197 Modification of description in Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (4/4) (c) CHAPTER 10 A/D CONVERTER 303 304 Modification of Caution 1 in Figure 10-2. Format of Peripheral Enable Register 0 (PER0) (c) Modification of Caution 1 and addition of Caution 2 in 10.3.2 A/D converter mode register 0 (c) (ADM0) 305 Modification of description in Table 10-1. Settings of ADCS and ADCE Bits (c) 308 Addition of Note 3 and modification of Caution 1 in Tables 10-3 A/D Conversion Time Selection (c) (1/4) 309 Addition of Note 6 and modification of Caution 1 and LV1 in Tables 10-3 A/D Conversion Time (c) Selection (2/4) 310 Addition of Note 4 and modification of Caution 1 in Tables 10-3 A/D Conversion Time Selection (c) (3/4) 311 Addition of Note 7 and modification of Caution 1 and LV1 in Tables 10-3 A/D Conversion Time (c) Selection (4/4) 312 Modification of Caution 1 in 10.3.3 A/D converter mode register 1 (ADM1) (c) 313 Modification of Caution 1 in 10.3.4 A/D converter mode register 2 (ADM2) (c) Modification of Caution 5 in Figure 10-11. Format of Analog Input Channel Specification Register (c) 318 (ADS) 330 Modification of error in Figure 10-22. Example of Software Trigger Mode (Scan Mode, Sequential (a) Conversion Mode) Operation Timing 331 Modification of error in Figure 10-23. Example of Software Trigger Mode (Scan Mode, One-Shot (a) Conversion Mode) Operation Timing Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 820 RL78/G12 APPENDIX A REVISION HISTORY (3/4) Page 334 Description Modification of error in Figure 10-26. Example of Hardware Trigger No-Wait Mode (Scan Mode, Classification (a) Sequential Conversion Mode) Operation Timing 335 Modification of error in Figure 10-27. Example of Hardware Trigger No-Wait Mode (Scan Mode, (a) One-Shot Conversion Mode) Operation Timing 338 Modification of error in Figure 10-30. Example of Hardware Trigger Wait Mode (Scan Mode, (a) Sequential Conversion Mode) Operation Timing 339 Modification of error in Figure 10-31. Example of Hardware Trigger Wait Mode (Scan Mode, One- (a) Shot Conversion Mode) Operation Timing 344 Change title of chapter 10.7.4 to Setup when temperature sensor output/internal reference (c) voltage output is selected (example for software trigger mode and one-shot conversion mode) 344 Change title of Figure 10-35 to Setup when temperature sensor output/internal reference (c) voltage output is selected. CHAPTER 11 SERIAL ARRAY UNIT 367 Modification of error in Figure 11-7. Format of Serial Clock Select Register m (SPSm) (a) CHAPTER 17 STANDBY FUNCTION 660 Modification of Figure 17-4. HALT Mode Release by Reset (c) 660 Modification of Note in Figure 17-4. HALT Mode Release by Reset (b) 661 Modification of caution1 in (1) STOP mode setting and operating statuses (c) 662 Modification of error in Table 17-2. Operating Statuses in STOP Mode (c) 663 Deletion of Caution 1 in Table 17-2. Operating Statuses in STOP Mode (c) 665 Modification of Figure 17-6. STOP Mode Release by Reset (c) 665 Modification of Note in Figure 17-6. STOP Mode Release by Reset (b) 666 Modification of description in (1) SNOOZE mode setting and operating statuses (c) CHAPTER 18 RESET FUNCTION 668 Modification of Caution 3 in CHAPTER 18 RESET FUNCTION (c) 670 Modification of description in Figure 18-2. Timing of Reset by RESET Input (b) Modification of description in Figure 18-3. Timing of Reset Due to Execution of Illegal Instruction (b) 670 or Watchdog Timer Overflow 671 Modification of description and deletion of Note in Table 18-1. Operation Statuses During Reset (c) Period 672 Modification of Note 2 in Table 18-2. Hardware Statuses After Reset Acknowledgment (1/3) (b) 675 Modification of Caution 2 in 18.1.1 Reset Control Flag Register (RESF) (c) Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 821 RL78/G12 APPENDIX A REVISION HISTORY (4/4) Page Description Classification CHAPTER 19 POWER-ON-RESET CIRCUIT 679 Modification of Note 3 in Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on- (c) reset Circuit and Voltage Detector (1/3) 680 Modification of Note 4 in Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on- (c) reset Circuit and Voltage Detector (2/3) 681 Addition of Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit (c) and Voltage Detector (3/3) CHAPTER 21 SAFETY FUNCTIONS 701 Modification of 21.1 (2) RAM parity error detection function (a) 705 Modification of Caution in 21.3.2 RAM parity error detection function (c) CHAPTER 23 OPTION BYTE 716 Modification of description in 23.1 Functions of Option Bytes (c) 718 Modification of Caution in Figure 23-1. Format of User Option Byte (000C0H) (c) 720 Addition of Caution in Figure 23-2. Format of User Option Byte (000C1H)(2/2) (c) 721 Addition of Caution in Figure 23-3. Format of User Option Byte (000C2H) (c) CHAPTER 24 FLASH MEMORY 729 Modification of description in 24.3.1 P40/TOOL0 pin (c) 732 Modification of description and addition of Cautions 1 and 2 in 24.4.1 Data flash overview (c) Modification of description and Remark in Figure 24-8. Setting of Flash Memory Programming (c) 735 Mode 739 Modification of explanation of 24.6 Security Settings 740 Deletion of (2) Self programming in Table 24-12. Security Setting in Each Programming Mode (c) 741 Modification of Cautions 1 to 4 in 24.7 Flash Memory Programming by Self-Programming (c) 743 Modification of description in 24.7.1 Flash shield window function (c) 743 Modification of description in Table 24-14. Setting and changing of the flash shield window function (c) (c) and relations with commands CHAPTER 28 ELECTRICAL SPECIFICATIONS 773 Addition of Note 4 in 28.1 Absolute Maximum Ratings (c) 775 Addition of Note 3 in 28.3.1 Pin characteristics (1/4) (c) 776 Addition of Note 3 in 28.3.1 Pin characteristics (2/4) (c) 777 Addition of Notes 1 and 2 in 28.3.1 Pin characteristics (3/4) (c) 778 Modification of Note in 28.3.1 Pin characteristics (4/4) (c) 781 Modification of Notes 2 and 4 in (2) 30-pin products (c) 811 Change title of chapter 28.6.2 to Temperature sensor/internal reference voltage (c) 811 Change from reference output voltage to internal reference voltage (c) 814 Modification of description in 28.8 Flash Memory Programming Characteristics (b) 815 Modification of description in 28.9 Timing Specs for Flash Memory Programming Switching (c) Modes Remark "Classification" in the above table classifies revisions as follows. (a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note, (d): Addition/change of package, part number, or management division, (e): Addition/change of related documents R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 822 RL78/G12 APPENDIX A REVISION HISTORY A.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/11) Edition Rev.1.00 Description Addition of products of industrial application Chapter Though out Renamed interval timer (unit) to 12-bit interval timer Addition of pin name of the peripheral I/O redirection function Modification of reset processing time Deletion of LIN communication function Renamed VLVI, VLVIH, VLVIL to VLVD, VLVDH, VLVDL (LVD detection voltage) Renamed RAMTOP to RPE, renamed ITIF, ITMK, ITKAPR0, ITKAPR1 to TMKAIF, TMKAMK, TMKAPR0, TMKAPR1 (interrupt source, flag) Addition of description to 1.1 Features CHAPTER 1 OUTLINE Modification of description in 1.2 Ordering Information Addition of Figure 1-1. Part Number, Memory Size, and Package of RL78/G12 Addition and Modification of description in 1.6 Outline of Functions Modification of description in 2.1 Port Function CHAPTER 2 PIN Modification of description in 2.2 Functions other than port pins (Deletion of FUNCTIONS description of port function) Modification of description in 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Addition of remark to Table 3-1. Correspondence Between Address Values and CHAPTER 3 CPU Block ARCHITECTURE Numbers in Flash Memory Addition of product in Table 3-2. Internal ROM Capacity Addition of INTFL to Table 3-3. Vector Table (20-, 24-pin products) Modification of description in 3.1.2 Mirror area Addition of description to Caution in Table 3-5. Internal RAM Capacity Modification of Figure 3-23. Outline of Table Indirect Addressing Addition of setting of registers when using port xx to Table 4-2 to 4-4, 4-6 to 4-12, 4-14 CHAPTER 4 PORT to 4-20 FUNCTIONS Modification of block diagrams for Pxxx Addition of description to (3) Port 2 Addition of description to (4) Port 4 Addition of Note to (6) Port 12 Addition of description to (3) Port 2 Addition of description to (2) Port register (Pxx) Addition of description to (3) Pull-up resistor option registers (PUxx) Modification of description in Figure 4-37. Format of Port Output Mode Register Addition of Caution to Figure 4-38. Format of Port Mode Control Register Addition of description to (8) Peripheral I/O redirection register (PIOR) Addition of description to 4.4.1 Writing to I/O port, and 4.4.3 Operations on I/O port R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 823 RL78/G12 APPENDIX A REVISION HISTORY (2/11) Edition Rev.1.00 Description Chapter Addition of description to 4.4.4 Connecting to external device with different CHAPTER 4 PORT potential (1.8 V, 2.5 V, 3 V) FUNCTIONS Addition of description to 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function Addition of 4.6.2 Notes on specifying the pin settings Addition of description to 5.1 (1) <2> High-speed on-chip oscillator CHAPTER 5 Addition of Caution to Figure 5-2. Format of Clock Operation Mode Control GENERATOR CLOCK Register (CMC) Modification of Figure 5-1. Block Diagram of Clock Generator Modification of description in Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting Deletion of Note to Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2) Addition of description to (7) Operation speed mode control register (OSMC) Modification of Caution 3 to Figure 5-9 Format of High-Speed On-Chip Oscillator Frequency Selection Register (HOCODIV) Modification of description in Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When voltage detector (LVD) is used) Addition of description to 5.6.2 Example of setting X1 oscillation clock Addition of description to Figure 5-14. CPU Clock Status Transition Diagram Addition of description to (2) CPU operating with high-speed system clock (C) after reset release (A) Modification and deletion of description in Table 5-4. Changing CPU Clock Modification of description in Table 5-5. Maximum Number of Clocks Required for fIH fMX, and Table 5-6. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Addition of Figure to (7) Delay counter CHAPTER 6 TIMER Addition of description to Figure 6-2. Entire Configuration of Timer Array Unit (30- ARRAY UNIT pin products) Addition of Figure 6-3. Internal Block Diagram of Channel of Timer Array Unit Addition of description to (1) Timer/counter register 0n (TCR0n) Addition of description to (2) Timer data register 0n (TDR0n) Modification of description and addition of caution to Figure 6-8. Format of Timer Clock Select register 0 (TPS0) Modification of description in Table 6-4. Interval Times Available for Operation Clock CKS02 or CKS03, and addition of Caution in (3) Timer mode register 0n (TMR0n) Modification of Figure 6-9. Format of Timer Mode Register 0n (TMR0n) Addition of description to (5) Timer channel enable status register 0 (TE0) Modification of Figure 6-12. Format of Timer Channel Start register 0 (TS0) Addition of description to Figure 6-13. Format of Timer Channel Stop register 0 (TT0) Addition of description to (8) Timer input select register 0 (TIS0) Modification of description to Figure 6-15. Format of Timer Output Enable register 0 (TOE0) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 824 RL78/G12 APPENDIX A REVISION HISTORY (3/11) Edition Description Chapter Rev.1.00 Addition of description to (14) Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or CHAPTER 6 TIMER PM4) ARRAY UNIT Addition of description to 6.4.1 Basic Rules of Simultaneous Channel Operation Function Addition of description to 6.5.1 Count clock (fTCLK) Modification of description to Table 6-6. Operations from Count Operation Enabled State to Timer count Register 0n (TCR0n) Count Start Addition of title to 6.5.3 Operation of counter Modification of Figure 6-27. Operation Timing (In Capture & One-count Mode: High-level Width Measurement) Addition of description to 6.6.2 TO0n Pin Output Setting Modification of description to Figure 6-39, 43, 51, 55, 59, 64, 69, 74 Example of Set Contents of Registers Modification of Figure 6-41, 45, 49, 53, 61 Addition of 6.9 Cautions When Using Timer Array Unit Addition of description to (2) Operation speed mode control register (OSMC) CHAPTER 7 12-BIT Addition of Caution to Figure 7-4. Format of Interval Timer Control Register INTERVAL TIMER (ITMC) Modification of Figure 7-5. 12-Bit Interval Timer Operation Timing Modification of Figure 8-1. Block Diagram of Clock Output/Buzzer Output CHAPTER 8 CLOCK Controller OUTPUT/BUZZER Modification of Figure 8-2. Format of Clock Output Select Register n (CKSn) OUTPUT CONTROLLER Addition of description to (2) Port mode register 1, 3 (PM1, PM3) Addition of Caution to 8.4.1 Operation as output pin Modification of description to 9.1 Functions of Watchdog Timer, 9.4.4 Setting CHAPTER 9 watchdog timer interval interrupt WATCHDOG TIMER Modification of Figure 10-1. Block Diagram of A/D Converter CHAPTER 10 Modification of description to (3) A/D voltage comparator A/D CONVERTER Addition of Caution to Figure 10-3. Format of A/D Converter Mode Register 0 (ADM0) Modification of description to Figure 10-4. Timing Chart When A/D Voltage Comparator Is Used Addition of description to Table 10-3. A/D Conversion Time Selection Modification of Caution to Figure 10-6. Format of A/D Converter Mode Register 1 (ADM1) Addition of description to Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) Addition of description to Figure 10-11. Format of Analog Input Channel Specification Register (ADS) Addition of description and Caution to (10) A/D test register (ADTES), (11) A/D port configuration register (ADPC), (12) Port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14), and (13) Port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 825 RL78/G12 APPENDIX A REVISION HISTORY (4/11) Edition Rev.1.00 Description Chapter Addition of Note to 10.4 A/D Converter Conversion Operations CHAPTER 10 Modification of Figure 10-32. Setting up Software Trigger Mode to Figure 10- A/D CONVERTER 36. Setting up Test Trigger Mode Addition of description to 10.8 SNOOZE mode function Addition and modification of description to 10.10 Cautions for A/D Converter Change the value to Table 10-6. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) Addition of description to CHAPTER 11 SERIAL ARRAY UNIT CHAPTER 11 Addition of description to 11.1.2 UART (UART0 to UART2) SERIAL ARRAY UNIT Modification of Figure 11-1. to 11-3 Block Diagram of Serial Array Unit 0 (20- or 24-pin products) Modification of Caution to Figure 11-6. Format of Peripheral Enable Register 0 (PER0) Modification of frequency to Figure 11-7. Format of Serial Clock Select Register m (SPSm) Addition of description for Note to Figure 11-9. Format of Serial Communication Operation Setting Register mn (SCRmn) Addition of description to Figure 11-10. Format of Serial Data Register mn (SDRmn) Addition of description to Figure 11-12. Format of Serial Status Register mn (SSRmn) (2/2) Addition and modification of Note and Caution to Figure 11-13. Format of Serial Channel Start Register m (SSm) Addition and modification of Note to Figure 11-14. Format of Serial Channel Stop Register m (STm), Figure 11-15. Format of Serial Channel Enable Status Register m (SEm) Addition of description to Figure 11-16. Format of Serial Output Enable Register m (SOEm) and Figure 11-17. Format of Serial Output Register m (SOm) Addition of description to (13) Serial output level register m (SOLm) Modification of description to Figure 11-19. Format of Serial Standby Control Register 0 (SSC0) Addition of description to (18) Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6) Addition of description to Figure 11-25. Each Register Setting When Stopping Operation by Channels Modification of description to 11.5.1 Master transmission, 11.5.2 Master reception, 11.5.3 Master transmission/reception Modification of description to Figure 11-26, 34, 42, 50, 58, 64, 77, 85, 99, 103, 106 (Example of Contents of Registers) Modification of description to Figure 11-28, 29, 31, 33, 36, 37, 39, 41, 44, 45, 47, 49, 52, 53, 55, 57, 60, 61, 63, 66, 69, 71, 73, 75, 79, 80, 82, 84, 86, 87, 88, 90, 93, 95, 100, 102, 105, 108 (flow chart) Addition of description to 11.5.4 Slave transmission, 11.5.5 Slave reception, 11.5.6 Slave transmission/reception Addition of Caution to 11.5.7 SNOOZE mode function (only CSI00), 11.6.3 SNOOZE mode function (only UART0 reception) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 826 RL78/G12 APPENDIX A REVISION HISTORY (5/11) Edition Rev.1.00 Description Chapter Addition of Caution to 11.6 Operation of UART (UART0 to UART2) CHAPTER 11 SERIAL Communication ARRAY UNIT Modification of description to 11.7.1 Address field transmission, 11.7.2 Data transmission, 11.7.3 Data reception Addition of Caution to 11.7.5 Calculating transfer rate Modification of description for example of setting IIC transfer rate Modification of description to Figure 12-6. Format of IICA Control Register 00 CHAPTER 12 SERIAL (IICCTL00) INTERFACE IICA Addition of description to Figure 12-7. Format of IICA Status Register 0 (IICS0) Modification of Figure 12-28, 29, 30 Modification of Figure 13-1. Block Diagram of Multiplier and Divider/Multiply- CHAPTER 13 Accumulator Modification of value to Figure 13-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) Addition of description to 13.4.5 Division operation Addition of description CHAPTER 15 Addition of description to Table 15-1 and 15-2 Interrupt Source List INTERRUPT FUNCTION Addition of INTFL to Table 15-3 and 15-4 Flags Corresponding to Interrupt Request Sources Modification of description to Table 15-5. Time from Generation of Maskable Interrupt Until Servicing Modification of Figure 15-12. Interrupt Request Acknowledgment Timing (Maximum Time) Modification of Table 15-6. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing During Interrupt Servicing Addition and modification of description to Though out CHAPTER 16 KEY INTERRUPT FUNCTION Modification of Caution to (3) SNOOZE mode CHAPTER 17 Modification of description to Table 17-1. Operating Statuses in HALT Mode STANDBY FUNCTION Addition and modification of rerease to standby function, wait time for SNOOZE status Addition of description to Table 18-1. Operation Statuses During Reset Period CHAPTER 18 RESET Addition of description to Table 18-2. Hardware Statuses After Reset FUNCTION Acknowledgment Addition of Note to Table 18-2. Hardware Statuses After Reset Acknowledgment Addition and modification of 19.1 Functions of Power-on-reset Circuit, 19.3 CHAPTER 19 POWER- Operation of Power-on-reset Circuit ON-RESET CIRCUIT Modification of Figure 20-1. Block Diagram of Voltage Detector CHAPTER 20 Modification of description to Figure 20-2. Format of Voltage Detection Register VOLTAGE DETECTOR (LVIM) Addition of description to Figure 20-3. Format of Voltage Detection Level Select Register (LVIS) Addition of Caution to Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) Modification of Figure 20-4, 20-5, 20-6 Addition of description to Figure 20-7, 20-8 R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 827 RL78/G12 APPENDIX A REVISION HISTORY (6/11) Edition Rev.1.00 Description Chapter Addition of description to 21.3.1 CRC operation function (general-purpose CRC) CHAPTER 21 SAFETY Addition of description to Figure 21-3. CRC Operation Function (General-Purpose FUNCTIONS CRC) Addition of description to Figure 21-5. Format of Invalid Memory Access Detection Control Register (IAWCTL) Modification of Figure 21-7. Invalid access detection area Addition of description to 21.3.7 A/D test function Addition of Figure CHAPTER 22 REGULATOR Addition of description to (2) 000C1H CHAPTER 23 OPTION Addition of description to Figure 23-1. Format of User Option Byte (000C0H) BYTE Modification and addition of Caution to Figure 23-2. Format of User Option Byte (000C1H) Deletion of description to 24.1.1 Programming environment CHAPTER 24 FLASH Addition of description to 24.2 Writing to Flash Memory by Using External Device (that MEMORY Incorporates UART) Addition of description to Figure 24-8. Setting of Flash Memory Programming Mode Addition of description to Table 24-5, Table 24-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Modification of description to Table 24-10. Example of Signature Data Addition of description to 24.6 Security Settings Addition of Figure 25-3. Connection Example of E1 On-chip Debugging Emulator and CHAPTER 25 ON-CHIP RL78/G12 (30-pin products) DEBUG FUNCTION Modification of description to Figure 25-4. Memory Spaces Where Debug Monitor Programs Are Allocated Modification of flag status CHAPTER 27 INSTRUCTION SET Deletion of target, and public release CHAPTER 28 ELECTRICAL SPECIFICATIONS Rev.0.03 Deletion of temperature trimming registers 0 to 3 (TEMPCAL0 to TEMPCAL3) Throughout Change of value in power supply voltage: Addition of description to 1.1 Features CHAPTER 1 OUTLINE Addition of description to 1.6 Outline of Functions Change of description for 2.1.4 Pins for each product (pins other than port pins) CHAPTER 2 PIN Addition of 2.2 Description of Pin Functions FUNCTIONS Addition of note in Figures 3-3 to 3-5 Memory Map, Figures 3-10 to 3-12 Correspondence Between Data Memory and Addressing CHAPTER 3 CPU ARCHITECTURE Addition of description to 3.1.2 Mirror area Addition of caution 2 to 3.1.3 Internal data memory space Addition of caution 3 to 3.2.1 (3) Stack pointer (SP) Addition of caution 2 to 3.2.2 General-purpose registers Change of description in Table 3-7. Extended SFR (2nd SFR) List (2/5) Addition of description to 3.4.3 Direct addressing Addition of 4.4 Port Function Operations Change of setting value in Table 4-6. Settings of Port Mode Register and Output Latch When Using Alternate Function and Table 4-9. Settings of Port Mode Register and Output Latch When Using Alternate Function (30-pin products) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 CHAPTER 4 PORT FUNCTIONS 828 RL78/G12 APPENDIX A REVISION HISTORY (7/11) Edition Rev.0.03 Description Chapter Addition of value to 5.1 (1) <2> High-speed on-chip oscillator (HOCO) CHAPTER 5 CLOCK Change of Figure 5-1. Block Diagram of Clock Generator GENERATOR Addition of description to 5.3 (2) System clock control register (CKC) Change of value in Figure 5-4. Format of Clock Operation Status Control Register (CSC) Change of description in 5.3 (4) Oscillation stabilization time counter status register (OSTC) Addition of value to Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS) Addition of description to 5.3 (6) Peripheral enable register 0 (PER0) Addition of description to 5.3 (9) High-speed on-chip oscillator trimming register (HIOTRM) Addition of note 3 to Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On Addition of 5.6.1 Example of setting high-speed on-chip oscillator Addition of description to 5.6.2 Example of setting X1 oscillation clock Addition of description to 5.6.3 CPU clock status transition diagram Addition of X1 clock to Table 5-4. Changing CPU Clock Addition of description to 5.6.5 Time required for switchover of CPU clock and main system clock Change of description in Table 5-6. Conditions Before the Clock Oscillation Is Stopped and Flag Settings Addition of 6.1.3 8-bit timer operation function (channels 1 and 3 only) Addition of description of caution 1 to Figure 6-7. Format of Peripheral Enable Register 0 (PER0) CHAPTER 6 TIMER ARRAY UNIT Addition of remark to Figure 6-8. Format of Timer Clock Select register 0 (TPS0) Addition of address and change of description of note 2 in Figure 6-9. Format of Timer Mode Register 0n (TMR0n) Addition of address to Figure 6-10. Format of Timer Status Register 0n (TSR0n) Addition of 30-pin products to Figure 6-11. Format of Timer Channel Enable Status register 0 (TE0) to Figure 6-13. Format of Timer Channel Stop register 0 (TT0), and Figure 6-15. Format of Timer Output Enable register 0 (TOE0) Change of description in Figure 6-17. Format of Timer Output Level register 0 (TOL0) Addition of description to 6.4.1 Basic Rules of Simultaneous Channel Operation Function Addition of 6.5 Operation Timing of Counter Change of description in 6.6.1 TO0n pin output circuit configuration and 6.6.2 TO0n Pin Output Setting Addition of 6.6.3 Cautions on Channel Output Operation Addition of 6.6.4 Collective manipulation of TO0n bit Addition of 6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start Addition of 6.7 Independent Channel Operation Function of Timer Array Unit Addition of 6.8 Simultaneous Channel Operation Function of Timer Array Unit Change of description in 7.1 Functions of Interval Timer CHAPTER 7 INTERVAL Change of description and addition of caution to Figure 7-2. Format of Peripheral Enable Register 0 (PER0) TIMER Addition of caution to Figure 7-4. Format of Interval Timer Control Register (ITMC) Change of Figure 8-1. Block Diagram of Clock Output/Buzzer Output Controller CHAPTER 8 CLOCK Addition of frequency to Figure 8-2. Format of Clock Output Select Register n (CKSn) OUTPUT/BUZZER OUTPUT CONTROLLER Change of remark in Table 9-4. Setting Window Open Period of Watchdog Timer CHAPTER 9 WATCHDOG TIMER R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 829 RL78/G12 APPENDIX A REVISION HISTORY (8/11) Edition Rev.0.03 Description Chapter Change of internal reference voltage CHAPTER 10 A/D Change of Figure 10-1. Block Diagram of A/D Converter CONVERTER Addition of caution to Table 10-1. Settings of ADCS and ADCE Bits Change of description in Table 10-2. Setting and Clearing Conditions for ADCS Bit Addition of frequency to f Table 10-3. A/D Conversion Time Selection Change of Figure 10-6. Format of A/D Converter Mode Register 1 (ADM1) Change of bit name in Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) Change of caution 5 in Figure 10-11. Format of Analog Input Channel Specification Register (ADS) Addition of 10.7 A/D Converter Setup Flowchart Change of description of note 2 in 10.8 SNOOZE mode function Addition of 10.10 Cautions for A/D Converter Addition of description to CHAPTER 11 SERIAL ARRAY UNIT CHAPTER 11 SERIAL Addition of description to 11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) ARRAY UNIT Addition of description to 11.1.2 UART (UART0 to UART2) Addition of description to 11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20) Addition of SSC1 to Figure 11-3. Block Diagram of Serial Array Unit 1 (30-pin products) Addition of value to Figure 11-7. Format of Serial Clock Select Register m (SPSm) Change of address in Figure 11-10. Format of Serial Data Register mn (SDRmn) Addition of description to 11.3 (14) Serial standby control register m (SSCm) Addition of description to 11.3 (16) Noise filter enable register 0 (NFEN0) Addition of description to 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication Change of value in (c) Serial communication operation setting register mn (SCRmn) of Figure 11-86 Change of value of remark 1 in 11.6.4 (1) Baud rate calculation expression Change of description and addition of caution to Figure 12-9. Format of IICA Control Register 01 (IICCTL01) CHAPTER 12 SERIAL INTERFACE IICA Addition of description to 12.3 (6) IICA low-level width setting register 0 (IICWL0) Change of description in Figure 12-32. Example of Master to Slave Communication and Figure 12-33. Example of Slave to Master Communication Change of value in Figure 13-6. Timing Diagram of Multiplication (Unsigned) Operation (2 x 3 = 6) CHAPTER 13 Addition of description to 13.4.3 Multiply-accumulation (unsigned) operation DIVIDER/MULTIPLYACCUMULATOR Addition of description to 13.4.4 Multiply-accumulation (signed) operation MULTIPLIER AND Change of Figure 13-9. Timing Diagram of Multiply-Accumulation (signed) Operation Change of description in 14.2 (2) DMA RAM address register n (DRAn) CHAPTER 14 DMA Addition of description to Figure 14-4. Format of DMA Mode Control Register n (DMCn) CONTROLLER Addition of 14.5 Example of Setting of DMA Controller Addition of 14.6 Cautions on Using DMA Controller Addition of 30-pin products to Figure 15-8. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge Enable Register (EGN0) CHAPTER 15 Addition of value to Figure 17-2. Format of Oscillation Stabilization Time Select Register (OSTS) CHAPTER 17 STANDBY R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 INTERRUPT FUNCTION FUNCTION 830 RL78/G12 APPENDIX A REVISION HISTORY (9/11) Edition Rev.0.03 Description Addition of description to Table 17-1. Operating Statuses in HALT Mode to Table 17-3. Operating Statuses in SNOOZE Mode Chapter CHAPTER 17 STANDBY FUNCTION Addition of note in Figure 17-3. HALT Mode Release by Interrupt Request Generation to Figure 17-6. STOP Mode Release by Reset Change of value and hardware name in Table 18-2. Hardware Statuses After Reset Acknowledgment CHAPTER 18 RESET FUNCTION Addition of name and value of note 2 to Table 18-2. Hardware Statuses After Reset Acknowledgment Addition of note to Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detector CHAPTER 19 POWERON-RESET CIRCUIT Change of value in Figure 19-3. Example of Software Processing After Reset Release Change of description in 20.1 Functions of Voltage Detector CHAPTER 20 VOLTAGE Addition of note to Figure 20-2. Format of Voltage Detection Register (LVIM) DETECTOR Change of notes to Figure 20-3. Format of Voltage Detection Level Select Register (LVIS) Change of Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) Change of description in 20.4.1 When used as reset mode to 20.4.3 When used as interrupt and reset mode Change of Figure 20-4. Timing of Voltage Detector Internal Reset Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) to Figure 20-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 0) Change of Figure 20-8. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released Change of all CHAPTER 21 SAFETY FUNCTIONS Change of Table 22-1. Regulator Output Voltage Conditions CHAPTER 22 REGULATOR Deletion of description of 23.1.1 (2) 000C1H CHAPTER 23 OPTION Change of description in Figure 23-2. Format of User Option Byte (000C1H) and Figure 23-3. Format of Option Byte (000C2H) BYTE Change of setting value in 23.4 Setting of Option Byte Addition of description to 24.1.2 Communication mode Change of description in Table 24-2. Pin Connection CHAPTER 24 FLASH MEMORY Change of description in 24.2.2 Communication mode Addition of description to 24.4.1 Data flash overview Change of description in 24.5.2 Flash memory programming mode Addition of 24.5.5 Description of signature data Change of description in (2) Self programming of Table 24-12. Addition of description to 24.7.1 Flash shield window function Change of description in Figure 24-14. Setting and changing of the flash shield window function and relations with commands Change of value in Table 24-13. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified Change of Figure 25-1. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION Addition of Figure 25-2. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (When using to the alternative function of RESET pin) R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 831 RL78/G12 APPENDIX A REVISION HISTORY (10/11) Edition Rev.0.03 Description Chapter Change of description in Figure 25-3. Memory Spaces Where Debug Monitor CHAPTER 25 ON-CHIP Programs Are Allocated DEBUG FUNCTION Addition of description to Table 27-1. Operand Identifiers and Specification Methods CHAPTER 27 Addition of value to 28.3.2 On-chip oscillator characteristics CHAPTER 28 Change of 28.4.1 Pin characteristics ELECTRICAL Addition of value to 28.4.2 Supply current characteristics SPECIFICATIONS (target) Change of value in 28.5.1 Basic operation INSTRUCTION SET Change of value in 28.6.1 Serial array unit Addition of value to 28.7.1 A/D converter characteristics Addition of value to 28.7.2 Temperature sensor characteristics and 28.7.3 POR circuit characteristics Deletion of value of LVD detection voltage of interrupt & reset mode Change of value in 28.8 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics Change of 28.10 Timing Specs for Switching Modes Addition of all CHAPTER 29 PACKAGE DRAWINGS Rev.0.02 Addition of the 30-pin product Throughout Modification of the names "internal high-speed oscillator circuit" and "internal lowspeed oscillator circuit" to "high-speed on-chip oscillator (HOCO)" and "low-speed onchip oscillator (LOCO)" Addition of cautions in Figures 3-1 through 3-6 Memory maps and Figure 3-8 through 3-13 Correspondences between data memory and addressing CHAPTER 3 CPU ARCHITECTURE Modification of reset values of P13 in Table 3-6 SFR list Addition of high-speed on-chip oscillator frequency selecting register (HOCODIV) to nd Table 3-7 Extended SFR (2 SFR) list Modification of description method of operand Addition of Cautions 1 through 3 in 4.2.1 20-, 24-pin product (2) Port 1 CHAPTER 4 PORT Addition of Caution 2 in 4.2.1 20-, 24-pin product (4) Port 4 FUNCTIONS Addition of Caution in 4.2.1 20-, 24-pin product (5) Port 6 Addition of the high-speed on-chip oscillator frequency selection register (HOCODIV) in control registers CHAPTER 5 CLOCK GENERATOR Deletion of LV (low-voltage main) mode in 5.6.1 Example of setting high-speed onchip oscillator Modification of voltages in Figure 5-14 CPU clock status transition diagram Addition of description of alternate ports in 6.2 Timer array unit configuration CHAPTER 6 TIMER ARRAY UNIT Modification in Figure 11-10 Format of Serial Data Register mn (SDRmn) CHAPTER 11 SERIAL Deletion of values in Caution 2 in Figure 11-10 Format of Serial Data Register mn (SDRmn) and Caution in 11.6.4 Calculating baud rate ARRAY UNIT Addition of description in cautions in 12.4.2 Setting transfer clock by using the IICWL0 and IICWH0 registers CHAPTER 12 SERIAL Addition of setting values in Figure 15-6 Format of Priority Specification Flag CHAPTER 15 Registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) (20-, 24-pin product) INTERRUPT FUNCTIONS Addition of Cautions 2 and 3 in Figure 18-5 Format of Reset Control Flag Register CHAPTER 18 RESET (RESF) FUNCTION Modification of voltage in Figure 19-2 Timing of Generation of Internal Reset Signal by Power-on-reset Circuit and Voltage Detectior CHAPTER 19 POWER- R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 INTERFACE IICA ON-RESET CIRCUIT 832 RL78/G12 APPENDIX A REVISION HISTORY (11/11) Edition Rev.0.02 Description Chapter Deletion of description in 20.1 Function of Voltage Detector CHAPTER 20 VOLTAGE Modification in Figure 20-5 Timing of Interrupt Signal Generation DETECTIOR Addition of Caution 2 in Figure 21-4 Format of RAM Parity Error Control Register (RPECTL) CHAPTER 21 SAFETY FUNCTIONS Deletion of the description of boot swap CHAPTER 23 OPTION BYTE Modification of description in Table 24-1 Wiring Between RL78/G12 and Dedicated Flash Memory Programmer and Table 24-2 Pin Connection CHAPTER 24 FLASH MEMORY Modification of description in Notes of 24.1.2 Communication Mode Addition of description in 24.3.1 TOOL0 pin Modification of description in 24.4.1 Data flash overview Modification in Figure 24-8 Setting of Flash Memory Programming Mode Modification in Table 24-7 Flash Memory Control Commands Addition of Caution 2 in 24.7 Flash Memory Programming by Self-Programming Addition of 24.7.1 Flash shield window function Modification of values of Absolute Maximum Ratings CHAPTER 28 Modification of values of On-chip Oscillator Characteristics ELECTRICAL Modification of values in 28.4 DC Characteristics SPECIFICATIONS (TARGET) Modification of values in 28.6.1 Serial array unit Addition of Caution in 28.6.1 Serial array unit Addition of description in Caution of 28.6.1 Serial array unit Addition and deletion of values in 28.7 Analog Characteristics, and modification of the value in the same section Modification in 28.9 Flash Memory Programming Characteristics Modification in 28.10 Timing Specs for Switching Modes and of tHD unit R01UH0200EJ0110 Rev.1.10 Sep. 28, 2012 833 RL78/G12 User's Manual: Hardware Publication Date: Rev.1.10 Sep. 28, 2012 Published by: Renesas Electronics Corporation http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. 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