User’s Manual
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
RL78/G12
User’s Manual: Hardware
Rev.1.10 Sep 2012
16
16-Bit Single-Chip Microcontrollers
www.renesas.com
Notice
1. Descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of
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and information in the design of your equipment. Renesas Electronics assumes no responsibility for any losses incurred by you
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incurred by you resulting from errors in or omissions from the information included herein.
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(2012.4)
NOTES FOR CMOS DEVICES
(1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a
reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL
(MAX) and VIH (MIN) due to noise, etc., the device m ay malfunction. Take care to prevent chatteri ng noise
from entering the device when the input level is fixed, and also in the transition period when the input level
passes through the area between VIL (MAX) and VIH (MIN).
(2) HANDLING OF UNUSED INPUT PINS: Unconnected CMOS device inputs can be cause of malfunction. If
an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc.,
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or lo w by using pull-up or pull-do wn circuitry. Eac h unused pin should be
connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling
related to unused pins must be judged separately for each device and according to related specifications
governing the device.
(3) PRECAUTION AGAINST ESD: A strong electric field, when exposed to a MOS device, can cause
destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it when it has occurred.
Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended
to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shiel ding bag or conductive material. All test and measurement
tools including work benches and flo ors should b e gr ound e d. The operator should be gr ounded usin g a wrist
strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken
for PW boards with mounted semiconductor devices.
(4) STATUS BEFORE INITIALIZATION: Power-on does not necessarily define the initial status of a MOS
device. Immediately after the power source is turned ON, devices with reset functions have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A
device is not initialized until the reset signal is received. A reset operation must be executed immediately
after power-on for devices with reset functions.
(5) POWER ON/OFF SEQUENCE: In the case of a device that uses different power supplies for the internal
operation and exter nal interface, as a rule, s witch on the external power supply after s witching on the in ternal
power supply. When s witching the power supply off, as a rule, s witch off the external power supply and then
the internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements
due to the passage of an abnormal current. The correct power on/off sequence must be judged separately
for each device and according to related specifications governing the device.
(6) INPUT OF SIGNAL DURING POWER OFF STATE : Do not input signals or an I/O pull-up power supply
while the device is not powered. The current injection that results from input of such a signal or I/O pull-up
power supply may cause malfunction and the abnormal current that passes in the device at this time may
cause degradation of internal elements. Input of signals during the power off state must be judged
separately for each device an d accord ing to related specifications governing the device.
How to Use This Manual
Readers This manual is intended for user engineers who wish to understand the functions of the
RL78/G12 and design and develop application systems and programs for these devices.
Purpose This manual is intended to give users an understanding of the functions described in the
Organization below.
Organization The RL78/G12 manual is separated into two parts: this manual and the software edition
(common to the RL78/G12 family).
RL78/G12
User’s Manual
Hardware
RL78 family
User’s Manual
Software
• Pin functions
• Internal block functions
• Interrupts
• Other on-chip peripheral functions
• Electrical specifications
• CPU functions
• Instruction set
• Explanation of each instruct ion
How to Read This Manual It is assumed that the readers of this manual have general knowledge of electrical
engineering, logic circuits, and microcontrollers.
• To gain a gen eral understanding of functions:
→ Read this manual in the order of the CONTENTS. The mark “<R>” shows major
revised points. The revised points can be easily searched by copying an “<R> ” in the
PDF file and specifying it in the “F ind what:” field.
• How to interpret the register format:
→ For a bit number enclosed in angle brackets, the bit name is defined as a reserved
word in the assembler, and is defined as an sfr variable using the #pragma sfr
directive in the compiler.
• To know details of the RL78/ G12 Microcontroller instructions:
→ Refer to the separate document RL78 Family Software User’s Manual
(R01US0015E).
Conventions Data significance: Higher digits on the left and lower digits on the right
Active low representations: ××× (overscore over pin and signal name)
Note: Footnote for item marked with Note in the text
Caution: Information requiring particular attention
Remark: Supplementary information
Numerical representations: Binary
...×××× or ××××B
Decimal
...××××
Hexadecimal
...××××H
Related Documents The related documents indicated in this publication may include preliminary versions.
However, preliminary versions are not marked as such.
Documents Related to Devices
Document Name Document No.
RL78/G12 User’s Manual Hardware R01UH0200E
RL78 Microcontroller Software User’s Manual R01US0015E
Documents Related to Flash Memory Programming
Document Name Document No.
PG-FP5 Flash Memory Programmer User’s Manual R20UT0008E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
Other Documents
Document Name Document No.
RENESAS MICROCOMPUTER GENERAL CATALOG R01CS0001E
Semiconductor Device Mount Manual Note
Quality Grades on NEC Semiconductor Devices C11531E
NEC Semiconductor Device Reliability/Quality Control System C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
Note See the “Semiconductor Dev ice Mount Manual” website (http://www.renesas.com/prod/package/manual/index.html).
Caution The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document when designing.
All trademarks and registered trademarks are the property of their respective owners.
EEPROM is a trademark of Renesas Electronics Corporation.
Windows, Window s NT and Windows XP are registered trademarks or trademarks of Microsoft Corporation in the
United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
SuperFlash is a registered trademark of Silicon Storage Technolog y, Inc. in several cou ntries including the United States
and Japan.
Caution: This product uses SuperFlash® technology l icensed from Silicon Storage Technology, Inc.
Index-1
CONTENTS
CHAPTER 1 OUTLINE...............................................................................................................................1
1.1 Differences between R5F102 and R5F103................................................................................ 1
1.1.1 Data Flash.......................................................................................................................................... 1
1.1.3 Peripheral Functions .......................................................................................................................... 2
1.2 Features...........................................................................................................................................3
1.3 List of Part Numbers......................................................................................................................5
1.4 Pin Configuration (Top View)........................................................................................................6
1.4.1 20-pin products................................................................................................................................... 6
1.4.2 24-pin products................................................................................................................................... 7
1.4.3 30-pin products................................................................................................................................... 8
1.5 Pin Identification.............................................................................................................................9
1.6 Block Diagram ..............................................................................................................................10
1.6.1 20-pin products................................................................................................................................. 10
1.6.2 24-pin products................................................................................................................................. 11
1.6.3 30-pin products................................................................................................................................. 12
1.7 Outline of Functions.....................................................................................................................13
CHAPTER 2 PIN FUNCTIONS...............................................................................................................15
2.1 Port Functions..............................................................................................................................15
2.1.1 20-pin products................................................................................................................................. 15
2.1.2 24-pin products................................................................................................................................. 16
2.1.3 30-pin products.............................................................................................................................. 17
2.2 Functions other than port pins...................................................................................................19
2.2.1 Functions for each product............................................................................................................... 19
2.2.2 Description of Functions................................................................................................................... 20
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins...........................................21
CHAPTER 3 CPU ARCHITECTURE......................................................................................................25
3.1 Memory Space..............................................................................................................................25
3.1.1 Internal program memory space....................................................................................................... 33
3.1.2 Mirror area........................................................................................................................................ 37
3.1.3 Internal data memory space............................................................................................................. 38
3.1.4 Special function register (SFR) area ................................................................................................ 40
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area ....................... 40
3.1.6 Data memory addressing................................................................................................................. 40
3.2 Processor Registers.....................................................................................................................47
3.2.1 Control registers............................................................................................................................... 47
Index-2
3.2.2 General-purpose registers................................................................................................................ 49
3.2.3 ES and CS registers......................................................................................................................... 51
3.2.4 Special function registers (SFRs)..................................................................................................... 52
3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers)........................... 57
3.3 Instruction Address Addressing.................................................................................................63
3.3.1 Relative addressing.......................................................................................................................... 63
3.3.2 Immediate addressing...................................................................................................................... 63
3.3.3 Table indirect addressing ................................................................................................................. 64
3.3.4 Register direct addressing................................................................................................................ 64
3.4 Addressing for Processing Data Addresses.............................................................................65
3.4.1 Implied addressing ........................................................................................................................... 65
3.4.2 Register addressing ......................................................................................................................... 65
3.4.3 Direct addressing ............................................................................................................................. 66
3.4.4 Short direct addressing .................................................................................................................... 67
3.4.5 SFR addressing................................................................................................................................ 68
3.4.6 Register indirect addressing............................................................................................................. 69
3.4.7 Based addressing............................................................................................................................. 70
3.4.8 Based indexed addressing............................................................................................................... 73
3.4.9 Stack addressing.............................................................................................................................. 74
CHAPTER 4 PORT FUNCTIONS...........................................................................................................77
4.1 Port Functions..............................................................................................................................77
4.2 Port Configuration........................................................................................................................77
4.2.1 20, 24-pin products........................................................................................................................... 78
4.2.2 30-pin products............................................................................................................................... 100
4.3 Registers Controlling Port Function ........................................................................................124
4.4 Port Function Operations..........................................................................................................135
4.4.1 Writing to I/O port........................................................................................................................... 135
4.4.2 Reading from I/O port..................................................................................................................... 135
4.4.3 Operations on I/O port.................................................................................................................... 135
4.4.4 Connecting to external device with different potential (1.8 V, 2.5 V, 3 V)....................................... 136
4.5 Settings of Port Related Register When Using Alternate Function ......................................138
4.6 Cautions When Using Port Function........................................................................................145
4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) ............................................... 145
4.6.2 Notes on specifying the pin settings.............................................................................................. 146
CHAPTER 5 CLOCK GENERATOR ....................................................................................................147
5.1 Functions of Clock Generator...................................................................................................147
5.2 Configuration of Clock Generator ............................................................................................148
5.3 Registers Controlling Clock Generator....................................................................................150
5.3.1 Clock operation mode control register (CMC) ................................................................................ 151
Index-3
5.3.2 System clock control register (CKC)............................................................................................... 152
5.3.3 Clock operation status control register (CSC) ................................................................................ 153
5.3.4 Oscillation stabilization time counter status register (OSTC).......................................................... 154
5.3.5 Oscillation stabilization time select register (OSTS)....................................................................... 156
5.3.6 Peripheral enable register 0 (PER0)............................................................................................... 158
5.3.7 Operation speed mode control register (OSMC) ............................................................................ 159
5.3.8 High-speed on-chip oscillator frequency selection register (HOCODIV) ........................................ 160
5.3.9 High-speed on-chip oscillator trimming register (HIOTRM)............................................................ 160
5.4 System Clock Oscillator ............................................................................................................162
5.4.1 X1 oscillator.................................................................................................................................... 162
5.4.2 High-speed on-chip oscillator......................................................................................................... 165
5.4.3 Low-speed on-chip oscillator.......................................................................................................... 165
5.5 Clock Generator Operation .......................................................................................................165
5.6 Controlling Clock........................................................................................................................167
5.6.1 Example of setting high-speed on-chip oscillator ........................................................................... 167
5.6.2 Example of setting X1 oscillation clock........................................................................................... 168
5.6.3 CPU clock status transition diagram............................................................................................... 169
5.6.4 Condition before changing CPU clock and processing after changing CPU clock ......................... 172
5.6.5 Time required for switchover of CPU clock and main system clock ............................................... 173
5.6.6 Conditions before clock oscillation is stopped................................................................................ 173
5.7 Resonator and Oscillator Constants.........................................................................................174
CHAPTER 6 TIMER ARRAY UNIT......................................................................................................176
6.1 Functions of Timer Array Unit...................................................................................................177
6.1.1 Independent channel operation function ........................................................................................ 177
6.1.2 Simultaneous channel operation function....................................................................................... 178
6.1.3 8-bit timer operation function (channels 1 and 3 only).................................................................... 179
6.2 Configuration of Timer Array Unit............................................................................................180
6.3 Registers Controlling Timer Array Unit....................................................................................189
6.3.1 Peripheral enable register 0 (PER0)............................................................................................... 190
6.3.2 Timer clock select register 0 (TPS0) .............................................................................................. 191
6.3.3 Timer mode register 0n (TMR0n)................................................................................................... 193
6.3.4 Timer status register 0n (TSR0n)................................................................................................... 198
6.3.5 Timer channel enable status register 0 (TE0)................................................................................. 199
6.3.6 Timer channel start register 0 (TS0)............................................................................................... 200
6.3.7 Timer channel stop register 0 (TT0)............................................................................................... 201
6.3.8 Timer input select register 0 (TIS0)................................................................................................ 202
6.3.9 Timer output enable register 0 (TOE0)........................................................................................... 203
6.3.10 Timer output register 0 (TO0)....................................................................................................... 204
6.3.11 Timer output level register 0 (TOL0)............................................................................................. 205
6.3.12 Timer output mode register 0 (TOM0).......................................................................................... 206
Index-4
6.3.13 Noise filter enable register 1 (NFEN1).......................................................................................... 207
6.3.14 Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4)........................................................ 208
6.4 Basic Rules of Timer Array Unit ...............................................................................................209
6.4.1 Basic Rules of Simultaneous Channel Operation Function............................................................ 209
6.4.2 Basic rules of 8-bit timer operation function (Only Channels 1 and 3)............................................ 211
6.5 Operation of Counter .................................................................................................................212
6.5.1 Count clock (fTCLK)....................................................................................................................... 212
6.5.2 Start timing of counter .................................................................................................................... 214
6.5.3 Counter Operation.......................................................................................................................... 215
6.6 Channel Output (TO0n pin) Control..........................................................................................220
6.6.1 TO0n pin output circuit configuration.............................................................................................. 220
6.6.2 TO0n Pin Output Setting ................................................................................................................ 221
6.6.3 Cautions on Channel Output Operation ......................................................................................... 222
6.6.4 Collective manipulation of TO0n bit................................................................................................ 226
6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start................................................................ 227
6.7 Independent Channel Operation Function of Timer Array Unit.............................................228
6.7.1 Operation as interval timer/square wave output............................................................................. 228
6.7.2 Operation as external event counter .............................................................................................. 234
6.7.3 Operation as frequency divider (channel 0 of unit 0 only) .............................................................. 239
6.7.4 Operation as input pulse interval measurement............................................................................. 243
6.7.5 Operation as input signal high-/low-level width measurement........................................................ 248
6.7.6 Operation as delay counter ............................................................................................................ 252
6.8 Simultaneous Channel Operation Function of Timer Array Unit ..........................................257
6.8.1 Operation as one-shot pulse output function.................................................................................. 257
6.8.2 Operation as PWM function............................................................................................................ 264
6.8.3 Operation as multiple PWM output function ................................................................................... 271
6.9 Cautions When Using Timer Array Unit...................................................................................279
6.9.1 Cautions When Using Timer output................................................................................................ 279
CHAPTER 7 12-BIT INTERVAL TIMER................................................................................................281
7.1 Functions of 12-bit Interval Timer.............................................................................................281
7.2 Configuration of 12-bit Interval Timer.................................................................................... ..281
7.3 Registers Controlling 12-bit Interval Timer..............................................................................282
7.3.1 Peripheral enable register 0 (PER0)............................................................................................... 282
7.3.2 Operation speed mode control register (OSMC) ............................................................................ 283
7.3.3. Interval timer control register (ITMC)............................................................................................. 284
7.4 12-bit Interval Timer Operation.................................................................................................285
CHAPTER 8 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER.................................................286
8.1 Functions of Clock Output/Buzzer Output Controller ............................................................286
8.2 Configuration of Clock Output/Buzzer Output Controller......................................................287
Index-5
8.3 Registers Controlling Clock Output/Buzzer Output Controller.............................................287
8.3.1 Clock output select registers 0, 1 (CKS0, CKS1) ........................................................................... 287
8.3.2 Port mode register 1, 3 (PM1, PM3)............................................................................................... 289
8.4 Operations of Clock Output/Buzzer Output Controller ..........................................................290
8.4.1 Operation as output pin.................................................................................................................. 290
CHAPTER 9 WATCHDOG TIMER .......................................................................................................291
9.1 Functions of Watchdog Timer...................................................................................................291
9.2 Configuration of Watchdog Timer............................................................................................292
9.3 Register Controlling Watchdog Timer...................................................................................... 293
9.3.1 Watchdog timer enable register (WDTE)........................................................................................ 293
9.4 Operation of Watchdog Timer...................................................................................................294
9.4.1 Controlling operation of watchdog timer......................................................................................... 294
9.4.2 Setting overflow time of watchdog timer......................................................................................... 295
9.4.3 Setting window open period of watchdog timer.............................................................................. 296
9.4.4 Setting watchdog timer interval interrupt........................................................................................ 297
CHAPTER 10 A/D CONVERTER .........................................................................................................298
10.1 Function of A/D Converter.......................................................................................................298
10.2 Configuration of A/D Converter..............................................................................................300
10.3 Registers Used in A/D Converter............................................................................................302
10.3.1 Peripheral enable register 0 (PER0)............................................................................................. 303
10.3.2 A/D converter mode register 0 (ADM0) ........................................................................................ 304
10.3.3 A/D converter mode register 1 (ADM1) ........................................................................................ 312
10.3.4 A/D converter mode register 2 (ADM2) ........................................................................................ 313
10.3.5 10-bit A/D conversion result register (ADCR)............................................................................... 315
10.3.6 8-bit A/D conversion result register (ADCRH) .............................................................................. 316
10.3.7 Analog input channel specification register (ADS)........................................................................ 317
10.3.8 Conversion result comparison upper limit setting register (ADUL)............................................... 319
10.3.9 Conversion result comparison lower limit setting register (ADLL) ................................................ 319
10.3.10 A/D test register (ADTES) .......................................................................................................... 320
10.3.11 A/D port configuration register (ADPC)....................................................................................... 321
10.3.12 Port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14)... 322
10.3.13 Port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14)............... 323
10.4 A/D Converter Conversion Operations ..................................................................................325
10.5 Input Voltage and Conversion Results ..................................................................................327
10.6 A/D Converter Operation Modes.............................................................................................328
10.6.1 Software trigger mode (select mode, sequential conversion mode)............................................. 328
10.6.2 Software trigger mode (select mode, one-shot conversion mode) ............................................... 329
10.6.3 Software trigger mode (scan mode, sequential conversion mode)............................................... 330
10.6.4 Software trigger mode (scan mode, one-shot conversion mode) ................................................. 331
Index-6
10.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)............................... 332
10.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode).................................. 333
10.6.7 Hardware trigger no-wait mode (scan mode, sequential conversion mode)................................. 334
10.6.8 Hardware trigger no-wait mode (scan mode, one-shot conversion mode) ................................... 335
10.6.9 Hardware trigger wait mode (select mode, sequential conversion mode) .................................... 336
10.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)..................................... 337
10.6.11 Hardware trigger wait mode (scan mode, sequential conversion mode).................................... 338
10.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode) ...................................... 339
10.7 A/D Converter Setup Flowchart ..............................................................................................340
10.7.1 Setting up software trigger mode.................................................................................................. 341
10.7.2 Setting up hard ware trigger no-wait mode.................................................................................... 342
10.7.3 Setting up hard ware trigger wait mode......................................................................................... 343
10.7.4 Setup when temperature sensor output/internal reference voltage output is selected
(example for software trigger mode and one-shot conversion mode)......................................... 344
10.7.5 Setting up test mode .................................................................................................................... 345
10.8 SNOOZE mode function...........................................................................................................346
10.9 How to Read A/D Converter Characteristics Table...............................................................349
10.10 Cautions for A/D Converter...................................................................................................351
CHAPTER 11 SERIAL ARRAY UNIT..................................................................................................355
11.1 Functions of Serial Array Unit................................................................................................356
11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20)........................................................................... 356
11.1.2 UART (UART0 to UART2)............................................................................................................ 357
11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20) .................................................................................... 358
11.2 Configuration of Serial Array Unit..........................................................................................359
11.3 Registers Controlling Serial Array Unit..................................................................................365
11.3.1 Peripheral enable register 0 (PER0)............................................................................................. 366
11.3.2 Serial clock select register m (SPSm).......................................................................................... 367
11.3.3 Serial mode register mn (SMRmn)............................................................................................... 368
11.3.4 Serial communication operation setting register mn (SCRmn)..................................................... 369
11.3.5 Higher 7 bits of the serial data register mn (SDRmn)................................................................... 372
11.3.6 Serial flag clear trigger register mn (SIRmn) ................................................................................ 373
11.3.7 Serial status register mn (SSRmn)............................................................................................... 374
11.3.8 Serial channel start register m (SSm)........................................................................................... 376
11.3.9 Serial channel stop register m (STm)........................................................................................... 377
11.3.10 Serial channel enable status register m (SEm) .......................................................................... 378
11.3.11 Serial output enable register m (SOEm)..................................................................................... 379
11.3.12 Serial output register m (SOm)................................................................................................... 380
11.3.13 Serial output level register m (SOLm) ........................................................................................ 381
11.3.14 Serial standby control register 0 (SSC0) .................................................................................... 382
11.3.15 Noise filter enable register 0 (NFEN0)........................................................................................ 383
Index-7
11.3.16 Port input mode register 0, 1 (PIM0, PIM1)................................................................................ 384
11.3.17 Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5) ........................................ 385
11.3.18 Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)......................................................... 386
11.4 Operation Stop Mode...............................................................................................................388
11.4.1 Stopping the operation by units.................................................................................................... 388
11.4.2 Stopping the operation by channels............................................................................................. 389
11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication ...................390
11.5.1 Master transmission ..................................................................................................................... 391
11.5.2 Master reception........................................................................................................................... 400
11.5.3 Master transmission/reception...................................................................................................... 408
11.5.4 Slave transmission....................................................................................................................... 417
11.5.5 Slave reception............................................................................................................................. 426
11.5.6 Slave transmission/reception........................................................................................................ 432
11.5.7 SNOOZE mode function (only CSI00).......................................................................................... 441
11.5.8 Calculating transfer clock frequency............................................................................................. 445
11.5.9 Procedure for processing errors that occurred during 3-wire serial I/O
(CSI00, CSI01, CSI11, CSI20) communication............................................................................. 447
11.6 Operation of UART (UART0 to UART2) Communication......................................................448
11.6.1 UART transmission ...................................................................................................................... 449
11.6.2 UART reception............................................................................................................................ 459
11.6.3 SNOOZE mode function (only UART0 reception) ........................................................................ 467
11.6.4 Calculating baud rate ................................................................................................................... 473
11.6.5 Procedure for processing errors that occurred duri ng UART (UART0 to UART2)
communication............................................................................................................................. 477
11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20) Communication..............................478
11.7.1 Address field transmission............................................................................................................ 480
11.7.2 Data transmission......................................................................................................................... 485
11.7.3 Data reception.............................................................................................................................. 488
11.7.4 Stop condition generation............................................................................................................. 492
11.7.5 Calculating transfer rate ............................................................................................................... 493
11.7.6 Procedure for processing errors that occurred durin g simplified I2C
(IIC00, IIC01, IIC11, IIC20) communication ................................................................................ 495
CHAPTER 12 SERIAL INTERFACE IICA...........................................................................................496
12.1 Functions of Serial Interface IICA...........................................................................................496
12.2 Configuration of Serial Interface IICA ....................................................................................499
12.3 Registers Controlling Serial Interface IICA............................................................................502
12.3.1 Peripheral enable register 0 (PER0)............................................................................................. 502
12.3.2 IICA control register 00 (IICCTL00)............................................................................................. 502
12.3.3 IICA status register 0 (IICS0)........................................................................................................ 507
12.3.4 IICA flag register 0 (IICF0)............................................................................................................ 509
Index-8
12.3.5 IICA control register 01 (IICCTL01).............................................................................................. 511
12.3.6 IICA low-level width setting register 0 (IICWL0) ........................................................................... 513
12.3.7 IICA high-level width setting register 0 (IICWH0) ......................................................................... 513
12.3.8 Port mode register 6 (PM6).......................................................................................................... 514
12.4 I2C Bus Mode Functions..........................................................................................................515
12.4.1 Pin configuration........................................................................................................................... 515
12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers...................................................... 516
12.5 I2C Bus Definitions and Control Methods..............................................................................517
12.5.1 Start conditions............................................................................................................................. 517
12.5.2 Addresses .................................................................................................................................... 518
12.5.3 Transfer direction specification..................................................................................................... 518
12.5.4 Acknowledge (ACK) ..................................................................................................................... 519
12.5.5 Stop condition............................................................................................................................... 520
12.5.6 Wait.............................................................................................................................................. 521
12.5.7 Canceling wait.............................................................................................................................. 523
12.5.8 Interrupt request (INTIICA0) generation timing and wait control................................................... 524
12.5.9 Address match detection method................................................................................................. 525
12.5.10 Error detection............................................................................................................................ 525
12.5.11 Extension code........................................................................................................................... 526
12.5.12 Arbitration................................................................................................................................... 527
12.5.13 Wakeup function......................................................................................................................... 529
12.5.14 Communication reservation........................................................................................................ 532
12.5.15 Cautions..................................................................................................................................... 536
12.5.16 Communication operations......................................................................................................... 537
12.5.17 Timing of I2C interrupt request (INTIICA0) occurrence............................................................... 545
12.6 Timing Charts ...........................................................................................................................566
CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR......................................... 581
13.1 Functions of Multiplier and Divider/Multiply-Accumulator.................................................581
13.2 Configuration of Multiplier and Divider/Multiply-Accumulator ..........................................581
13.3 Register Controlling Multiplier and Divider/Multiply-Accumulator....................................587
13.3.1 Multiplication/division control register (MDUC)............................................................................. 587
13.4 Operations of Multiplier and Divider/Multiply-Accumulator...............................................589
13.4.1 Multiplication (unsigned) operation .............................................................................................. 589
13.4.2 Multiplication (signed) operation .................................................................................................. 590
13.4.3 Multiply-accumulation (unsigned) operation................................................................................. 591
13.4.4 Multiply-accumulation (signed) operation..................................................................................... 593
13.4.5 Division operation ........................................................................................................................ 595
CHAPTER 14 DMA CONTROLLER.....................................................................................................597
14.1 Functions of DMA Controller ..................................................................................................597
Index-9
14.2 Configuration of DMA Controller............................................................................................598
14.3 Registers Controlling DMA Controller ...................................................................................601
14.3.1 DMA mode control register n (DMCn) .......................................................................................... 602
14.3.2 DMA operation control register n (DRCn)..................................................................................... 604
14.4 Operation of DMA Controller...................................................................................................605
14.4.1 Operation procedure .................................................................................................................... 605
14.4.2 Transfer mode.............................................................................................................................. 606
14.4.3 Termination of DMA transfer ........................................................................................................ 606
14.5 Example of Setting of DMA Controller...................................................................................607
14.5.1 CSI consecutive transmission ...................................................................................................... 607
14.5.2 Consecutive capturing of A/D conversion results ......................................................................... 609
14.5.3 UART consecutive reception + ACK transmission........................................................................ 611
14.5.4 Holding DMA transfer pending by DWAITn bit............................................................................. 613
14.5.5 Forced termination by software.................................................................................................... 614
14.6 Cautions on Using DMA Controller ........................................................................................616
CHAPTER 15 INTERRUPT FUNCTIONS.............................................................................................618
15.1 Interrupt Function Types.........................................................................................................618
15.2 Interrupt Sources and Configuration .....................................................................................618
15.3 Registers Controlling Interrupt Functions............................................................................. 625
15.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)............................................ 629
15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H)................................. 631
15.3.3 Priority specification flag registers (PR00L, PR 00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) ...................................................................... 633
15.3.4 External interrupt rising edg e enable register (EGP0), external interrupt falling edge
enable register (EGN0)................................................................................................................ 637
15.3.5 Program status word (PSW)......................................................................................................... 638
15.4 Interrupt Servicing Operations ...............................................................................................639
15.4.1 Maskable interrupt request acknowledgment............................................................................... 639
15.4.2 Software interrupt request acknowledgment ................................................................................ 642
15.4.3 Multiple interrupt servicing............................................................................................................ 643
15.4.4 Interrupt request hold ................................................................................................................... 647
CHAPTER 16 KEY INTERRUPT FUNCTION .....................................................................................648
16.1 Functions of Key Interrupt ......................................................................................................648
16.2 Configuration of Key Interrupt................................................................................................649
16.3 Register Controlling Key Interrupt .........................................................................................649
16.3.1 Key return control register (KRCTL)............................................................................................. 650
16.3.2 Key return mode control registers (KRM0, KRM1)....................................................................... 650
16.3.3 Key return flag register (KRF)....................................................................................................... 652
16.3.4 Port mode registers 0, 4, 6, 12 (PM0, PM4, PM6, PM12) ............................................................ 652
Index-10
CHAPTER 17 STANDBY FUNCTION..................................................................................................653
17.1 Standby Function and Configuration.....................................................................................653
17.1.1 Standby function........................................................................................................................... 653
17.1.2 Registers controlling standby function.......................................................................................... 654
17.2 Standby Function Operation............................................................................................... ....657
17.2.1 HALT mode.................................................................................................................................. 657
17.2.2 STOP mode.................................................................................................................................. 661
17.2.3 SNOOZE mode............................................................................................................................ 666
CHAPTER 18 RESET FUNCTION........................................................................................................668
18.1 Register for Confirming Reset Source...................................................................................675
18.1.1 Reset Control Flag Register (RESF)............................................................................................. 675
CHAPTER 19 POWER-ON-RESET CIRCUIT......................................................................................677
19.1 Functions of Power-on-reset Circuit......................................................................................677
19.2 Configuration of Power-on-reset Circuit................................................................................678
19.3 Operation of Power-on-reset Circuit ......................................................................................678
19.4 Cautions for Power-on-reset Circuit.......................................................................................682
CHAPTER 20 VOLTAGE DETECTOR...................................................................................................684
20.1 Functions of Voltage Detector................................................................................................684
20.2 Configuration of Voltage Detector..........................................................................................685
20.3 Registers Controlling Voltage Detector.................................................................................685
20.3.1 Voltage detection register (LVIM)................................................................................................. 686
20.3.2 Voltage detection level register (LVIS) ......................................................................................... 687
20.4 Operation of Voltage Detector ................................................................................................690
20.4.1 When used as reset mode............................................................................................................ 690
20.4.2 When used as interrupt mode ...................................................................................................... 692
20.4.3 When used as interrupt and reset mode ...................................................................................... 694
20.5 Cautions for Voltage Detector.................................................................................................699
CHAPTER 21 SAFETY FUNCTIONS.....................................................................................................701
21.1 Overview of Safety Functions.................................................................................................701
21.2 Registers Used by Safety Functions...................................................................................... 702
21.3 Operation of Safety Functions................................................................................................702
21.3.1 CRC operation function (general-purpose CRC).......................................................................... 702
21.3.2 RAM parity error detection function.............................................................................................. 705
21.3.3 RAM guard function...................................................................................................................... 706
21.3.4 SFR guard function ...................................................................................................................... 707
21.3.5 Invalid memory access detection function.................................................................................... 708
Index-11
21.3.6 Frequency detection function ....................................................................................................... 709
21.3.7 A/D test function........................................................................................................................... 711
CHAPTER 22 REGULATOR ...................................................................................................................715
22.1 Overview of Regulators ...........................................................................................................715
CHAPTER 23 OPTION BYTE...............................................................................................................716
23.1 Functions of Option Bytes ......................................................................................................716
23.1.1 User option byte (000C0H to 000C2H)......................................................................................... 716
23.1.2 On-chip debug option byte (000C3H)........................................................................................... 717
23.2 Format of User Option Byte ....................................................................................................718
23.3 Format of On-chip Debug Option Byte...................................................................................722
23.4 Setting of Option Byte..............................................................................................................723
CHAPTER 24 FLASH MEMORY..........................................................................................................724
24.1 Writing to Flash Memory by Using Flash Memory Programmer .........................................725
24.1.1 Programming environment........................................................................................................... 726
24.1.2 Communication mode .................................................................................................................. 726
24.2 Writing to Flash Memory by Using External Device (that Incorporates UART).................727
24.2.1 Programming environment........................................................................................................... 727
24.2.2 Communication mode .................................................................................................................. 728
24.3 Connection of Pins on Board..................................................................................................729
24.3.1 P40/TOOL0 pin ............................................................................................................................ 729
24.3.2 RESET pin.................................................................................................................................... 729
24.3.3 Port pins....................................................................................................................................... 730
24.3.4 REGC pins ................................................................................................................................... 730
24.3.5 X1 and X2 pins............................................................................................................................. 730
24.3.6 Power supply................................................................................................................................ 730
24.4 Data Flash .................................................................................................................................731
24.4.1 Data flash overview...................................................................................................................... 731
24.4.2 Register controlling data flash memory ........................................................................................ 732
24.4.3 Procedure for accessing data flash memory ................................................................................ 733
24.5 Programming Method ..............................................................................................................734
24.5.1 Controlling flash memory.............................................................................................................. 734
24.5.2 Flash memory programming mode............................................................................................... 735
24.5.3 Selecting communication mode.................................................................................................... 736
24.5.4 Communication commands.......................................................................................................... 737
24.5.5 Description of signature data........................................................................................................ 738
24.6 Security Settings......................................................................................................................739
24.7 Flash Memory Programming by Self-Programming.............................................................741
Index-12
24. 7.1 Flash shield window function....................................................................................................... 743
CHAPTER 25 ON-CHIP DEBUG FUNCTION .....................................................................................744
25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12.................................................744
25.2 On-Chip Debug Security ID .....................................................................................................746
25.3 Securing of User Resources...................................................................................................746
CHAPTER 26 BCD CORRECTION CIRCUIT .....................................................................................748
26.1 BCD Correction Circuit Function............................................................................................748
26.2 Registers Used by BCD Correction Circuit ...........................................................................748
26.3 BCD Correction Circuit Operation..........................................................................................749
CHAPTER 27 INSTRUCTION SET........................................................................................................751
27.1 Conventions Used in Operation List......................................................................................752
27.1.1 Operand identifiers and specification methods............................................................................. 752
27.1.2 Description of operation column................................................................................................... 753
27.1.3 Description of flag operation column ............................................................................................ 754
27.1.4 PREFIX instruction....................................................................................................................... 754
27.2 Operation List...........................................................................................................................755
CHAPTER 28 ELECTRICAL SPECIFICATIONS.................................................................................772
28.1 Absolute Maximum Ratings ....................................................................................................773
28.2 Oscillator Characteristics........................................................................................................774
28.2.1 X1 clock oscillator characteristics................................................................................................. 774
28.2.2 On-chip oscillator characteristics.................................................................................................. 774
28.3 DC Characteristics ...................................................................................................................775
28.3.1 Pin characteristics........................................................................................................................ 775
28.3.2 Supply current characteristics ...................................................................................................... 779
28.4 AC Characteristics ...................................................................................................................784
28.5 Serial Communication Characteristics ..................................................................................786
28.5.1 Serial array unit............................................................................................................................ 786
28.5.2 Serial interface IICA ..................................................................................................................... 807
28.5.3 On-chip debug (UART)................................................................................................................. 807
28.6 Analog Characteristics ............................................................................................................808
28.6.1 A/D converter characteristics........................................................................................................ 808
28.6.2 Temperature sensor/internal reference voltage characteristics.................................................... 811
28.6.3 POR circuit characteristics ........................................................................................................... 811
28.6.4 LVD circuit characteristics............................................................................................................ 812
28.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics...............814
28.8 Flash Memory Programming Characteristics........................................................................814
Index-13
28.9 Timing Specs for Flash Memory Programming Sw itching Modes......................................815
CHAPTER 29 PACKAGE DRAWINGS................................................................................................816
29.1 20-pin products.........................................................................................................................816
29.2 24-pin products.........................................................................................................................817
29.3 30-pin products.........................................................................................................................818
APPENDIX A REVISION HISTORY .........................................................................................................819
A.1 Major Revisions in This Edition ...............................................................................................819
A.2 Revision History of Preceding Editions ..................................................................................823
R01UH0200EJ0110 Rev.1.10 1
Sep. 28, 2012
R01UH0200EJ0110
Rev.1.10
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RL78/G12
RENESAS MCU
CHAPTER 1 OUTLINE
1.1 Differences between R5F102 and R5F103
The following are differences between the R5F102 and R5F103.
Whether the data flash memory is mounted or not
High-speed on-chip oscillator oscillation frequency accuracy
Number of channels in serial interface
Whether the DMA function is mounted or not
Whether the safety function is mounted or not
1.1.1 Data Flash
The data flash memory of 2 KB is mounted on the R5F102 but not on the R5F103.
Product Data Flash
R5F102
R5F1026A, R5F1027A, R5F102AA,
R5F10269, R5F10279, R5F102A9,
R5F10268, R5F10278, R5F102A8,
R5F10267, R5F10277, R5F102A7,
R5F10266 Note
2KB
R5F103
R5F1036A, R5F1037A, R5F103AA,
R5F10369, R5F10379, R5F103A9,
R5F10368, R5F10378 R5F10 3A8,
R5F10367, R5F10377, R5F103A7,
R5F10366
Not mounted
Note The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer’s program
specification, the stack area to execute the data flash libra ry may not be kept and data may not be written to or
erased from the data flash memory.
Caution When the flash memor y is rewritten via a user program, the flash ROM area and RAM area are used
because each library is used. When using the library, refer to RL78 Family Flash Self Programming Library
Type01 User’s Manual and RL78 Family Data Flash L ibrar y Type04 User’s Manual.
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1.1.2 On-chip oscillator characteristics
(1) High-speed on-chip oscill ator oscillation frequency of the R5F102
Oscillator Condition MIN MAX Unit
TA = -20 to +85 °C -1 +1 High-speed on-chip
oscillator oscillation
frequency accuracy TA = -40 to -20 °C -1.5 +1.5
%
(2) High-speed on-chip oscill ator oscillation frequency of the R5F103
Oscillator Condition MIN MAX Unit
High-speed on-chip
oscillator oscillation
frequency accuracy
TA = -40 to + 85 °C -5 +5 %
1.1.3 Peripheral Functions
R5F102 R5F103
RL78/G12 20, 24 pin
product
30 pin product 20, 24 pin
product
30 pin product
UART 1 channel 3 channels 1 channel
CSI 2 channels 3 channels 1 channel
Serial interface
Simplified I2C 2 channels 3 channels None
DMA function 2 channels None
CRC operation Yes None
RAM guard Yes None
Safety function
SFR guard Yes None
RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 3
Sep. 28, 2012
1.2 Features
Minimum instruction execution time can be changed from high speed (0.04167
μ
s @ 24 MHz operation with high
speed on-chip oscillator clock) to ultra low-speed (1
μ
s @ 1 MHz operation)
General-purpose registers: (8-bit register × 8) × 4 banks
ROM: 2 KB to 16 KB, RAM: 256 bytes to 2 KB, data flash memory: −/2 KB
High speed on-chip oscillator : 24/16/12/ 8/4/1 MHz(TYP) can be selected
Flash memory
Prohibition of block erase and writing(security function)
Dual operation: Execution of instructions in the code flash memory is possible while writing the data flash memory.
Self-programming
On-chip debug function
On-chip power-on-reset (POR) circuit and voltage detector (LVD)
On-chip watchdog timer (operable with the dedicated low speed on-chip oscillator clock)
On-chip multiplier and divider/multiply-accumulator
• 16 bits × 16 bits = 32 bits (Unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned or signed)
On-chip key interrupt function
On-chip clock output/buzzer output controller
On-chip BCD adjustment
I/O ports: 18/22/26 (N-ch open drain: 2)
Timer
• 16-bit timer: 4/8 channels
• Watchdog timer: 1 channel
• 12-bit Interval timer: 1 channel
Serial interface
CSI: 1/2/3 channel
• UART: 1/3 channel
• Simplified I2C: 0/2/3 channel
• I2C: 1 channel
Different potential interface: Can connect to a 1.8/2.5/3 V device
8/10-bit resolution A/D converter: 8/11 channels
Standby function: HALT, STOP, SNOOZE mode
Power supply voltage: VDD = 1.8 to 5.5 V
Operating ambient temperature: TA = −40 to +85°C
Remark The functions mounted depend on the product. See 1.6 Outline of Functions.
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ROM, RAM capacities
Flash ROM Data flash RAM 20 pins 24 pins 30 pins
2 KB − − R5F102AA
−
2 KB
− − R5F103AA
2 KB R5F1026ANote R5F1027ANote −
16 KB
−
1.5 KB
R5F1036ANote R5F1037ANote −
2KB R5F10269Note R5F10279Note R5F102A9 12 KB
−
1 KB R5F10369Note R5F10379Note R5F103A9
2 KB R5F10268Note R5F10278Note R5F102A8 8 KB
−
768B R5F10368Note R5F10378Note R5F103A8
2KB R5F10267 R5F10277 R5F102A7 4 KB
−
512B R5F10367 R5F10377 R5F103A7
2 KB R5F10266 − −
2 KB
−
256B
R5F10366 − −
Note This is about 639 byte when the self-programing function and data flash function are used (For detail, see
CHAPTER 3 CPU ARCHITECTURE
RL78/G12 CHAPTER 1 OUTLINE
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Sep. 28, 2012
1.3 List of Part Numbers
Figure 1-1. Part Number, Memory Size, and Package of RL78/G12
Part No. R 5 F 1 0 2 A A A x x x S P
Package type:
ROM number (Omitted with blank products)
ROM capacity:
RL78/G12 group
Renesas MCU
Renesas semiconductor product
SP
: SSOP, 0.65 mm pitch
NA : WQFN, 0.50 mm pitch
6
: 2 KB
7
: 4 KB
8
: 8 KB
9
: 12 KB
A
: 16 KB
Pin count:
6
: 20-pin
7
: 24-pin
A
: 30-pin
Classification:
A : Consumer applications, operating ambient temperature : -40˚C to 85˚C
D : Industrial applications, operating ambient temperature : -40˚C to 85˚C
Memory type:
F : Flash memory
102 : Data flash is povided
103 : Data flash is not provided
Pin
count Package Data flash
Fields
of
Applica
tion
Part Number
Mounted A
R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP
R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP
20 pins 20-pin plastic
SSOP
(4.4 × 6.5) Not mounted D R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP
R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP
Mounted A
R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA
R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F1027 7DNA
24 pins 24-pin plastic
WQFN
(4 × 4) Not mounted D R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F1037 7ANA
R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F1037 7DNA
Mounted A
R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP
R5F102AADSP, R5F102A9DSP, R5F102A8DSP, R5F102A7DSP
30 pins 30-pin plastic
SSOP
(7.62 mm
(300) ) Not mounted D R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP
R5F103AADSP, R5F103A9DSP, R5F103A8DSP, R5F103A7DSP
Note For fields of application, see Figure 1-1. Part Number , Memory Size, and Package of RL78/G12.
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RL78/G12 CHAPTER 1 OUTLINE
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1.4 Pin Configuration (Top View)
1.4.1 20-pin products
• 20-pin plastic SSOP (4.4 × 6.5)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00
P11/ANI17/SI00/RxD0/SDA00 /TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
P61/KR5/SDAA0/(RxD0)
P60/KR4/SCLA0/(TxD0)
P20/ANI0/AVREFP
P40/KR0/TOOL0
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
P42/ANI21/SCK01 /SCL01NoteNote /TI03/TO03
P41/ANI22/SO01 /SDA01NoteNote /TI02/TO02/INTP1
P125/KR1/SI01 /RESET
Note
Note
Note
Note Provided in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parenthes es in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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1.4.2 24-pin products
• 24-pin plastic WQFN (4 × 4)
P40/KR0/TOOL0
P41/ANI22/SO01Note/SDA01Note/TI02/TO02/INTP1
P42/ANI21/SCK01Note/SCL01Note/TI03/TO03
P20/ANI0/AVREFP
P21/ANI1/AVREFM
P22/ANI2
P23/ANI3
P10/ANI16/PCLBUZ0/SCK00/SCL00Note
P11/ANI17/SI00/RxD0/SDA00Note/TOOLRxD
P12/ANI18/SO00/TxD0/TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
P125/KR1/SI01Note/RESET
P137/INTP0
P122/KR2/X2/EXCLK/(TI02)/(INTP2)
P121/KR3/X1/(TI03)/(INTP3)
VSS
VDD
P00/KR6/(SI01)Note
P01/KR7/(SO01/SDA01)Note
P02/KR8/(SCK01/SCL01)Note
P03/KR9
P60/KR4/SCLA0/(TxD0)
P61/KR5/SDAA00/(RxD0)
exposed die pad
1 2 3 4 5 6
12
11
10
9
8
7
18 17 16 15 14 13
19
20
21
22
23
24
Note Provided in the R5F102 products.
Remarks 1. For pin identification, see 1.5 Pin Identification.
2. Functions in parenthes es in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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1.4.3 30-pin products
• 30-pin plastic SSOP (7.62 mm (300))
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
P21/ ANI1/AVREFM
P22/ ANI2
P23/ ANI3
P147/ ANI18
P10/ SCK00/ SCL00Note/ (TI07/TO07)
P11/ SI00/ RxD0/TOOLRxD/SDA00Not e/(TI06/ TO06)
P12/ SO00/TxD0/TOOLTxD/(TI05/TO05)
P13/ TxD2Not e/SO20Not e/(SDAA0)/(TI04/ TO04)
P14/RxD2Note/SI20Note/SDA20Note/(SCLA0) /(TI03/TO03)
P15/PCLBUZ1/SCK20/SCL20/(TI02/TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/ TI02/TO02/(TxD0)
P51/INTP2/SO11
P50/INTP1/SI11/SDA11
P30/INTP3/SCK11/SCL11
P20/ ANI0/AV
REFP
P01/ANI16/TO00/RxD1
P00/ANI17/TI00/TxD1
P120/ANI19
P40/ TOOL0
RESET
P137/ INTP0
P122/ X2/ EXCLK
P121/ X1
REGC
VSS
VDD
P60/ SCLA0
P61/ SDAA0
P31/ TI03/TO03/ INTP4/PCLBUZ0
Note Provided in the R5F102 products.
Caution Connect the REGC pin to VSS via capacitor (0.47 to 1
μ
F).
Remarks 1. F or pin id entification, see 1.5 Pin Identification .
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 9
Sep. 28, 2012
1.5 Pin Identification
ANI0 to ANI3,
ANI16 to ANI22:
Analog input
REGC:
RESET:
Regulator Capacitance
Reset
AVREFM: Analog Reference Voltage Minus
AVREFP: Analog reference voltage plus
RxD0 to RxD2:
SCK00, SCK01, SCK11,
Receive Data
EXCLK: External Clock Input
(Main System Clock)
SCK20:
SCL00, SCL01, SCL11,
Serial Clock Input/Output
INTP0 to INTP5 Interrupt Request From Peripheral
KR0 to KR9 Key Return
SCL20, SCLA0:
SDA00, SDA01, SDA11,
Serial Clock Input/Output
P00 to P03: Port 0 SDA20, SDAA0: Serial Data Input/Output
P10 to P17: Port 1 SI00, SI01, SI11, SI20: Serial Data Input
P20 to P23: Port 2 SO00, SO01, SO11,
P30 to P31: Port 3 SO20: Serial Data Output
P40 to P42: Port 4 TI00 to TI07: Timer Input
P50, P51: Port 5 TO00 to TO07: Timer Output
P60, P61: Port 6 TOOL0: Data Input/Output for Tool
P120 to P122, P125: Port 12
P137: Port 13
TOOLRxD, TOOLTxD: Data Input/Output for External
Device
P147: Port 14 TxD0 to TxD2: Transmit Data
V
DD: Power supply
V
SS: Ground
PCLBUZ0, PCLBUZ1: Programmable Clock Output/
Buzzer Output
X1, X2: Crystal Oscillator (Main System
Clock)
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 10
Sep. 28, 2012
1.6 Block Diagram
1.6.1 20-pin products
4
2
5
PCLBUZ0
RESET
TAU0 (4 ch)
SAU0 (2 ch)
ch03
UART0
CSI00
ch01
ch00
ch02
CSI01
Note
IIC00
Note
IIC01
Note
RxD0
TxD0
SCK00
SI00
SO00
SCK01
SI01
SO01
SCL00
SDA00
SCL01
SDA01
SCLA0
SDAA0
TOOL0
On-chip debugger
Clock Generator
+
Reset Generator
Power-on
reset/low
voltage
detector
Low-speed
on-chip
oscillator
15 kHz
High-Speed
on-chip
oscillator
1 to 24 MHz
Main OSC
1 to 20 MHz
RAM
1.5 KB
Interrupt control
Port 1
Port 2
Port 4
Port 6
Port 12
Port 13
Buzzer/clock
output control
Key return
6 ch
Interrupt control
4 ch
Window watchdog
timer
12-bit Interval timer
10-bit A/D converter
11 ch
CRC
Note
RL78 CPU core DMA
2 ch
Note
Code ash: 16 KB
Data ash: 2 KB
Note
X1 X2/EXCLK
IICA0
BCD
adjustment
Multiplier &
divider/
multiply
accumulator
TOOL
TxD
TOOL
RxD
9
6
4
KR0 to KR5
INTP0 to INTP3
ANI2, ANI3, ANI16 to ANI22
ANI0/AV
REFP
ANI1/AV
REFM
P137
P10 to P14
P20 to P23
P40 to P42
P60, P61
P121, P122, P125
T
I00/TO00
T
I01/TO01
T
I02/TO02
T
I03/TO03
3
3
V
DD
V
SS
Note Provided for the R5F102 products.
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 11
Sep. 28, 2012
1.6.2 24-pin products
4
2
5
PCLBUZ0
RESET
TAU0 (4 ch)
SAU0 (2 ch)
ch03
UART0
CSI00
ch01
ch00
ch02
CSI01
Note
IIC00
Note
IIC01
Note
RxD0
TxD0
SCK00
SI00
SO00
SCK01
SI01
SO01
SCL00
SDA00
SCL01
SDA01
SCLA0
SDAA0
TOOL0
On-chip debugger
Clock Generator
+
Reset Generator
Power-on
reset/low
voltage
detector
Low-speed
on-chip
oscillator
15 kHz
High-Speed
on-chip
oscillator
1 to 24 MHz
Main OSC
1 to 20 MHz
RAM
1.5KB
Interrupt control
Port 1
Port 2
Port 4
Port 6
Port 12
Port 13
Buzzer/clock
output control
Key return
10 ch
Interrupt control
4 ch
Window watchdog
timer
12-bit Interval timer
10-bit A/D converter
11 ch
CRCNote
RL78 CPU core DMANote
2 ch
Code flash: 16 KB
Data flash: 2 KBNote
X1 X2/EXCLK
IICA0
BCD
adjustment
Multiplier &
divider/
multiply
accumulator
TOOL
TxD
TOOL
RxD
9
6
4
KR0 to KR9
INTP0 to INTP3
ANI2, ANI3, ANI16 to ANI22
ANI0/AVREFP
ANI1/AVREFM
P137
P10 to P14
4
Port 0 P00 to P03
P20 to P23
P40 to P42
P60, P61
P121, P122, P125
T
I00/TO00
T
I01/TO01
T
I02/TO02
T
I03/TO03
3
3
VDD VSS
Note Provided for the R5F102 products.
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 12
Sep. 28, 2012
1.6.3 30-pin products
PORT 1 P10 to P17
PORT 2 P20 t o P23
4
PORT 4 P40
P120
2
PORT 6
PORT 1 2
8
PCLBUZ0, PCLBUZ1
P60, P61
P121, P122
X1
X2/ EXCLK
RESET
TOOL0
TOOL
TxD
TOOL
Rx D
IICA0
Main OSC
1 to 20 MHz
SCL A 0
SDAA0
6
2
6INTP0 to INTP5
PORT 0 P00, P01
2
ANI2, ANI3,
ANI16 to ANI19
ANI0/ AV
REFP
ANI1/ AV
REFM
PORT 1 3 P137
RL7 8
CPU
CORE
DMA
Note
2ch
RA M
2KB
CODE FLA SH :16KB
DATA FLASH:2KB
Note
2
V
DD
V
SS
ON-CHIP DEBUG
BCD
ADJUSTMENT
MULTIPLIER&
DIVIDER
MULITIPLY-
ACCUM ULATOR
INTERRUPT
CONTROL
INTERRUPT
CONTROL
6ch
WINDOW
WATCHDOG
TIMER
CRC
Note
12-bit INTERVAL
TIMER
Low Speed
ON-CHIP
OSCILLATOR
15 kHz
High Speed
ON-CHIP
OSCILLATOR
1 to 24 MHz
POWER ON
RESET/
VOLTAGE
DETECTOR
Cl o ck Gen erat or
+
Reset Generator
10-bit
A/ D CONVERTER
8ch
BUZZER/ CLOCK
OUTPUT CONTROL
VOLTAGE
REGU LATOR REGC
PORT 1 4 P147
PORT 5 P50, P51
2
PORT 3 P30, P31
2
SAU0(4ch)
UART0
UART1
Note
IIC00
Note
CSI1 1
Note
IIC11
Note
CSI0 0
SAU1(2ch)
Note
UART2
IIC20
Rx D 0
TxD0
Rx D 1
TxD1
SCL 0 0
SDA 0 0
SCK1 1
SO1 1
SI 1 1
SCL 1 1
SDA 1 1
SCK0 0
SO0 0
SI 0 0
Rx D 2
TxD2
SCL 2 0
SDA 2 0
SCK2 0
SO2 0
SI 2 0
CSI2 0
ch2
TI02/ TO02
ch3
TI03/ TO03
ch0
ch1
ch4
ch5
ch6
ch7
TI00
TO0 0
TI01/ TO01
(TI04/ TO04)
(TI05/ TO05)
(TI06/ TO06)
(TI07/ TO07)
TAU(8ch)
Note Provided for the R5F102 products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 13
Sep. 28, 2012
1.7 Outline of Functions
This outline describes the function at the time when Peripheral I/O redirection register (PIOR) is set to 00H (except
timer output of R5F102Ax) (1/2)
20-pin 24-pin 30-pin Item
R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax
Code flash memory 2 to 16 KB Note 1 4 to 16 KB
Data flash memory 2 KB − 2 KB − 2 KB −
RAM 256 B to 1.5 KB 512 B to 1.5 KB 512 B to 2KB
Address space 1 MB
High-speed system clock X1, X2 (crystal/ceramic) oscillation, external main system clock input (EXCLK)
1 to 20 MHz: VDD = 2.7 to 5.5 V, 1 to 8 MHz: VDD = 1.8 to 5.5 V
Main
system
clock High-speed on-chip
oscillator clock HS (High-speed main) mode : 1 to 24 MHz (VDD = 2.7 to 5.5 V), 1 to 16 MHz (VDD = 2.4 to 5.5 V),
LS (Low-speed main) mode : 1 to 8 MHz (VDD = 1.8 to 5.5 V)
Low-speed on-chip oscillator clock 15 kHz (TYP)
General-purpose register (8-bit register × 8) × 4 banks
0.04167 μs (High-speed on-chip oscillator clock: fIH = 24 MHz operation) Minimum instruction execution time
0.05 μs (High-speed system clock: fMX = 20 MHz operation)
Instruction set • Data transfer (8/16 bits)
• Adder and subtractor/logical operation (8/16 bits)
• Multiplication (8 bits × 8 bits)
• Rotate, barrel shift, and bit manipulation (set, reset, test, and Boolean operation), etc.
Total 18 22 26
CMOS I/O 12 16 21
CMOS input 4 4 3
I/O port
N-ch open-drain I/O
(6 V tolerance) 2
16-bit timer 4 channels 8 channels
Watchdog timer 1 channel
12-bit Interval timer 1 channel
Timer
Timer output 4/8Note 2 (PWM Output Note 3: 3/7 Note 2)
Notes 1. The self-programming function cannot be used in the R5F10266 and R5F10366.
2. When PIOR0 is set to 1 in R5F102Az.
3. The number of PWM outputs varies depen ding on the setting of channels in use (the number of masters and
slaves). (see 6.8.3 Operation as multiple PWM o utpu t function).
Caution When the flash memory is re written via a user p rogram, the flash ROM area and RAM area are us ed because
each library is used. When using the library, refer to RL78 Family Flash Self Programming Library Type01
User’s Manual and RL78 Family Data Flash Library T ype04 User’s Manual.
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RL78/G12 CHAPTER 1 OUTLINE
R01UH0200EJ0110 Rev.1.10 14
Sep. 28, 2012
(2/2)
20-pin 24-pin 30-pin Item
R5F1026x R5F1036x R5F1027x R5F1037x R5F102Ax R5F103Ax
1 Clock output/buzzer output
2.44 kHz to 10 MHz: (Peripheral hardware clock: fMAIN = 20 MHz ope ration)
8/10-bit resolution A/D converter 11 channels 8 channels
Serial interface CSI/UART/Simplified I2C + CSI/Simplified I2C
[Product with data flash memory (30-pin)]
CSI/UART/Simplified I2C x 3
CSI + UART
I
2C bus 1 channel
Multiplier and divider/multiply-
accumulator
• 16 bits × 16 bits = 32 bits (unsigned or signed)
• 32 bits ÷ 32 bits = 32 bits (unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (unsigned or signed)
DMA controller 2 channels − 2 channels − 2 channels −
Internal 18 16 18 16 26 19
Vectored interrupt
sources External 5 6
Key interrupt 6 10 −
Reset • Reset by RESET pin
• Internal reset by watchdog timer
• Internal reset by power-on-reset
• Internal reset by voltage detector
• Internal reset by illegal instruction execution Note
• Internal reset by RAM parity error
• Internal reset by illegal-memory access
Power-on-reset circuit • Power-on-reset: 1.51 ± 0.03 V
• Power-down-reset: 1.50 ± 0.03 V
Voltage detector • Rising edge : 1.88 to 4.06 V (12 stages)
• Falling edge : 1.84 to 3.98 V (12 stages)
On-chip debug function Provided
Power supply voltage VDD = 1.8 to 5.5 V
Operating ambient temperature TA = −40 to +85°C
Note The illegal instruction is g enerated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emu lator or on-chip debug
emulator.
RL78/G12 CHAPTER 2 PIN FUNCTIONS
R01UH0200EJ0110 Rev.1.10 15
Sep. 28, 2012
CHAPTER 2 PIN FUNCTIONS
2.1 Port Functions
Set in each port I/O, buffer, pull-up resistor is also valid for alternate functions.
2.1.1 20-pin products
Function
Name I/O Function After Reset Alternate Function
P10 ANI16/PCLBUZ0/
SCK00/SCL00
P11 ANI17/SI00/RxD0/
SDA00/TOOLRxD
P12 ANI18/SO00/TxD0/
TOOLTxD
P13 ANI19/TI00/TO00/
INTP2
P14
I/O Port 1.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in port mode control register 0 (PMC0). This register
can be specified in 1-bit unit.
Input of P10, P11 can be set to TTL input buffer.
Output of P10 to P12 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Analog
input port
ANI20/TI01/TO01/
INTP3
P20 ANI0/AVREFP
P21 ANI1/AVREFM
P22 ANI2
P23
I/O Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in A/D port configuration register (ADPC).
Analog
input port
ANI3
P40 Input port KR0/TOOL0
P41
ANI22/SO01/SDA01/
TI02/TO02/INTP1
P42
I/O Port 4.
3-bit I/O port.
Input/output can be specified in 1-bit units.
P41 and P42 pins can be set to analog input. Specify then as
either digital or analog in port mode control register 4 (PMC4).
This register can be specified in 1-bit unit.
Output of P41 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Analog
input port
ANI21/SCK01/SCL01/
TI03/TO03
P60 KR4/SCLA0/(TxD0)
P61
I/O Port 6
2-bit I/O port.
Input/output can be specified in 1-bit units.
Output can be set to N-ch open-drain output (6-V tolerance).
Input port
KR5/SDAA0/(RxD0)
P121 KR3/X1/
(TI03)/(INTP3)
P122 KR2/X2/EXCLK/
(TI02)/(INTP2)
P125
Input Port 12
3-bit I/O port.
For P125, use of an on-chip pull-up resistor can be specified by
a software setting.
Input port
KR1/SI01/RESET
P137 Input
Port 13
1-bit input port
Input port INTP0
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 2 PIN FUNCTIONS
R01UH0200EJ0110 Rev.1.10 16
Sep. 28, 2012
2.1.2 24-pin products
Function
Name I/O Function After Reset Alternate Function
P00 KR6/(SI01)
P01 KR7/(SO01/SDA01)
P02 KR8/(SCK01/SCL01)
P03
I/O Port 0.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Output of P01 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Input port
KR9
P10 ANI16/PCLBUZ0/
SCK00/SCL00
P11 ANI17/SI00/RxD0/
SDA00/TOOLRxD
P12 ANI18/SO00/TxD0/
TOOLTxD
P13 ANI19/TI00/TO00/
INTP2
P14
I/O Port 1.
5-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in port mode control register 0 (PMC0). This register
can be specified in 1-bit unit.
Input of P10, P11 can be set to TTL input buffer.
Output of P10 to P12 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Analog
input port
ANI20/TI01/TO01/
INTP3
P20 ANI0/AVREFP
P21 ANI1/AVREFM
P22 ANI2
P23
I/O Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in A/D port configuration register (ADPC). This register
can be specified in 1-bit unit.
Analog
input port
ANI3
P40 Input port KR0/TOOL0
P41
ANI22/SO01/SDA01/
TI02/TO02/INTP1
P42
I/O Port 4.
3-bit I/O port.
Input/output can be specified in 1-bit units.
P41 and P42 pins can be set to analog input. Specify then as
either digital or analog in port mode control register 4 (PMC4).
This register can be specified in 1-bit unit.
Output of P41 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Analog
input port
ANI21/SCK01/SCL01/
TI03/TO03
P60 KR4/SCLA0/(TxD0)
P61
I/O Port 6.
2-bit I/O port. Input/output can be specified in 1-bit units.
Output can be set to N-ch open-drain output (6-V tolerance).
Input port
KR5/SDAA0/(RxD0)
P121 KR3/X1/
(TI03)/(INTP3)
P122 KR2/X2/EXCLK/
(TI02)/(INTP2)
P125
Input Port 12.
3-bit I/O port.
For P125, use of an on-chip pull-up resistor can be specified by
a software setting.
Input port
KR1/SI01/RESET
P137 Input Port 13.
1-bit input port.
Input port INTP0
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 2 PIN FUNCTIONS
R01UH0200EJ0110 Rev.1.10 17
Sep. 28, 2012
2.1.3 30-pin products (1/2)
Function
Name I/O Function After Reset Alternate Function
P00 ANI17/TI00/TxD1
P01
I/O Port 0.
2-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in port mode control register 0 (PMC0). This register
can be specified in 1-bit unit.
Input of P01 can be set to TTL input buffer.
Output of P00 can be set to N-ch open-drain output (VDD
tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Analog
input port ANI16/TO00/RxD1
P10 SCK00/SCL00/
(TI07/TO07)
P11 SI00/RxD0/
TOOLRxD/SDA00/
(TI06/TO06)
P12 SO00/TxD0/
TOOLTXD/
(TI05/TO05)
P13 TxD2/SO20/
(SDAA0)/
(TI04/TO04)
P14 RxD2/SI20/SDA20/
(SCLA0)/
(TI03/TO03)
P15 PCLBUZ1/SCK20/
SCL20/(TI02/TO02)
P16 TI01/TO01/INTP5/
(RxD0)
P17
I/O Port 1.
8-bit I/O port.
Input/output can be specified in 1-bit units.
Input of P10, P11, P13 to P17 can be set to TTL input buffer.
Output of P10 to P15, P17 can be set to N-ch open-drain output
(VDD tolerance).
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Input port
TI02/TO02/(TxD0)
P20 ANI0/AVREFP
P21 ANI1/AVREFM
P22 ANI2
P23
I/O Port 2.
4-bit I/O port.
Input/output can be specified in 1-bit units.
Can be set to analog input. Specify then as either digital or
analog in A/D port configuration register (ADPC). This register
can be specified in 1-bit unit.
Analog
input port
ANI3
P30 INTP3/SCK11/
SCL11
P31
I/O Port 3.
2-bit I/O port.
Input/output can be specified in 1-bit units.
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Input port
TI03/TO03/INTP4/
PCLBUZ0
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 2 PIN FUNCTIONS
R01UH0200EJ0110 Rev.1.10 18
Sep. 28, 2012
(2/2)
Function
Name I/O Function After Reset Alternate Function
P40 I/O Port 4.
1-bit I/O port.
Input/output can be specified in 1-bit units.
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Input port TOOL0
P50 INTP1/SI11/SDA11
P51
I/O Port 5.
2-bit I/O port.
Output of P50 can be set to N-ch open-drain output (VDD
tolerance).
Input/output can be specified in 1-bit units.
When input port use of an on-chip pull-up resistor can be
specified by a software setting (1-bit units).
Input port
INTP2/SO11
P60 SCLA0
P61
I/O Port 6.
2-bit I/O port.
N-ch open-drain output (6V tolerance).
Input/output can be specified in 1-bit units.
Input port
SDAA0
P120 I/O Analog
input port ANI19
P121 X1
P122
Input
Port 12.
1-bit I/O port and 2-bit input port.
P120 can be set to analog input. Specify then as either digital or
analog in port mode control register 12 (PMC12).
Only for P120, input/output can be specified.
Only for P120, use of an on-chip pull-up resistor can be
specified by a software setting.
Input port
X2/EXCLK
P137 Input Port 13.
Dedicated 1-bit input port.
Input port INTP0
P147 I/O Port 14.
1-bit I/O port.
Can be set to analog input. Specify then as either digital or
analog in port mode control register 14 (PMC14).
Input/output can be specified in 1-bit units.
When input port use of an on-chip pull-up resistor can be
specified by a software setting.
Analog
input port ANI18
RL78/G12 CHAPTER 2 PIN FUNCTIONS
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Sep. 28, 2012
2.2 Functions other than port pins
2.2.1 Functions for each product
Function
Name 20-pin
products 24-pin
products 30-pin
products Function
Name 20-pin
products 24-pin
products 30-pin
products
ANI0 √ √ √ SCL00 √Note √Note √Note
ANI1 √ √ √ SCL01 √Note √Note −
ANI2 √ √ √ SCL11 − − √Note
ANI3 √ √ √ SCL20 − − √Note
ANI16 √ √ √ SDA00 √Note √Note √Note
ANI17 √ √ √ SDA01 √Note √Note −
ANI18 √ √ √ SDA11 − − √Note
ANI19 √ √ √ SDA20 − − √Note
ANI20 √ √ − SI00 √ √ √
ANI21 √ √ − SI01 √Note √Note −
ANI22 √ √ − SI11 − − √Note
INTP0 √ √ √ SI20 − − √Note
INTP1 √ √ √ SO00 √ √ √
INTP2 √ √ √ SO01 √Note √Note −
INTP3 √ √ √ SO11 − − √Note
INTP4 − − √ SO20 − − √Note
INTP5 − − √ TI00 √ √ √
KR0 √ √ − TI01 √ √ √
KR1 √ √ − TI02 √ √ √
KR2 √ √ − TI03 √ √ √
KR3 √ √ − TI04 − − (√)
KR4 √ √ − TI05 − − (√)
KR5 √ √ − TI06 − − (√)
KR6 − √ − TI07 − − (√)
KR7 − √ − TO00 √ √ √
KR8 − √ − TO01 √ √ √
KR9 − √ − TO02 √ √ √
PCLBUZ0 √ √ √ TO03 √ √ √
PCLBUZ1 − − √ TO04 − − (√)
REGC − − √ TO05 − − (√)
RESET √ √ √ TO06 − − (√)
RxD0 √ √ √ TO07 − − (√)
RxD1 − − √Note X1 √ √ √
RxD2 − − √Note X2 √ √ √
TxD0 √ √ √ EXCLK √ √ √
TxD1 − − √Note VDD √ √ √
TxD2 − − √Note AVREFP √ √ √
SCK00 √ √ √ AVREFM √ √ √
SCK01 √Note √Note − VSS √ √ √
SCK11 − − √Note TOOLRxD √ √ √
SCK20 − − √Note TOOLTxD √ √ √
SCLA0 √ √ √ TOOL0 √ √ √
SDAA0 √ √ √
Note R5F102 products.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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2.2.2 Description of Functions
Function Name I/O Functions
ANI0 to ANI3, ANI16 to ANI22 input Analog input pins (ANI16 to ANI20) of A/D converter
See, Figure 10-47. Analog Input Pin Connection)
AVREFP input Inputs the A/D converter reference potential (+ side)
AVREFM input Inputs the A/D converter reference potential (− side)
INTP0 to INTP5 input External interrupt request input
Specified available edge : rising edge, falling edge, or both rising and falling
edges
KR0 to KR9 input Key interrupt input
PCLBUZ0 to PCLBUZ1 output Clock/buzzer output
REGC − Connecting regulator output stabilization capacitance for internal operation.
Connect this pin to VSS via a capacitor (0.47 to 1
μ
F)
RESET input External reset input
When the external reset pin is used, design the circuit based on VDD
RxD0 to RxD2 input UART0 to UART2 serial data input
TxD0 to TxD2 output UART0 to UART2 serial data output
SCK00, SCK01, SCK11, SCK20 I/O CSI00, CSI01, CSI11, CSI20 serial clock I/O
SI00, SI01, SI11, SI20 input CSI00, CSI01, CSI11, CSI20 serial data input
SO00, SO01, SO11, SO20 output CSI00, CSI01, CSI11, CSI20 serial data output
SCLA0 I/O I2C clock I/O
SDAA0 I/O I2C serial data I/O
SCL00, SCL01, SCL11, SCL20 output Simple I2C (IIC00, IIC01, IIC11, IIC20) clock I/O
SDA00, SDA01, SDA11, SDA20 I/O Simple I2C (IIC00, IIC01, IIC11, IIC2) serial data I/O
TI00 to TI07 input Inputting an exte rnal count clock/capture trigger to 16-bit timers 00 to 07
TO00 to TO07 output Timer output pins of 16-bit timers 00 to 07
X1, X2 − Connecting a resonator for main system clock
EXCLK input External clock input pin for main system clock
VDD − Positive power supply
VSS − Ground potential
Use bypass capacitors (about 0.1
μ
F) as noise and latch up countermeasures
with relatively thick wires at the shortest distance to VDD to VSS lines.
TOOLRxD input
This UART serial data input pin for an external device connection is used during
flash memory programming
TOOLTxD output
This UART serial data output pin for an external device connection is used
during flash memory programming
TOOL0 I/O Data I/O pin fo r a flas h memory prog ram mer/de bugge r
The operation mode after start-up is determined by the status of the TOOL0 pin
at the time of releasing a reset. Connect via an external resistor to VDD when
normal operation or on-chip debugging (pulling it down is prohibited)
TOOL0 Operation mode
VDD Normal operation mode
0 V F la sh me mo ry pro gramming mode
For details, see 24.5.2 Flash Memory Programming Mode.
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2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-1 and 2-2 sho w the types of pin I/O circuits and the recommended connections of unused pins.
Table 2-1. Connection of Unused Pins (20-, 24-pin products)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/KR6/(SI01) Note
P01/KR7/(SO01/SDA01) Note
P02/KR8/(SCK01/SCL01) Note
P03/KR9 Note
8-R
P10/ANI16/PCLBUZ0/SCK00/
SCL00
P11/ANI17/SI00/RxD0/SDA00/
TOOLRxD
11-V
P12/ANI18/SO00/TxD0/
TOOLTxD
P13/ANI19/TI00/TO00/INTP2
P14/ANI20/TI01/TO01/INTP3
11-U
P20/ANI0/AVREFP
P21/ANI1/AVREFM
11-T
P22/ANI2
P23/ANI3
11-G
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P40/KR0/TOOL0 8-R Input: Independently connect to VDD via a resistor or leave open.
Output: Leave open.
P41/ANI22/SO01/SDA01/TI02/
TO02/INTP1
P42/ANI21/SCK01/SCL01/TI03/
TO03
11-U Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P60/KR4/SCLA0/(TxD0)
P61/KR5/SDAA0/(RxD0)
13-R
I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Set the port’s output latch to 0 and leave the pins open, or
set the port’s output latch to 1 and independently connect the
pins to VDD or VSS via a resistor.
P121/KR3/X1/(TI03)/(INTP3) 37-C
P122/KR2/X2/EXCLK/(TI02)/
(INTP2)
Independently connect to VDD or VSS via a resistor.
P125/KR1/SI01/RESET 42-B PORTSELB = 0: Independently connect to VDD or VSS via a resistor.
PORTSELB = 1: Independently connect to VDD via a resistor.
P137/INTP0 2
input
Independently connect to VDD or VSS via a resistor.
Note 24-pin products only
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 2 PIN FUNCTIONS
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Sep. 28, 2012
Table 2-2. Connection of Unused Pins (30-pin products)
Pin Name I/O Circuit Type I/O Recommended Connection of Unused Pins
P00/ANI17/TI00/TxD1 11-U
P01/ANI16/TO00/RxD1 11-V
P10/SCK00/SCL00/
(TI07/TO07)
P11/SI00/RxD0/TOOLRxD/
SDA00/(TI06/TO06)
5-AN
P12/SO00/TxD0/TOOLTxD/
(TI05/TO05) 8-R
P13/TxD2/SO20/
(SDAA0)/(TI04/TO04)
P14/RxD2/SI20/SDA20/
(SCLA0)/(TI03/TO03)
P15/PCLBUZ1/SCK20/
SCL20/(TI02/TO02)
P16/TI01/TO01/INTP5/(RxD0)
P17/TI02/TO02/(TxD0)
5-AN
P20/ANI0/AVREFP
P21/ANI1/AVREFM
11-T
P22/ANI2
P23/ANI3
11-G
P30/INTP3/SCK11/SCL11
P31/TI03/TO03/INTP4/
PCLBUZ0
P40/TOOL0
P50/INTP1/SI11/SDA11
P51/INTP2/SO11
8-R
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P60/SCLA0
P61/SDAA0
13-R Input: Independently connect to VDD or VSS via a resistor.
Output: Set the port’s output latch to 0 and leave the pins open,
or set the port’s output latch to 1 and independently
connect the pins to VDD or VSS via a resistor.
P120/ANI19 11-U
I/O
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P121/X1
P122/X2/EXCLK
37-C
P137/INTP0 2
input Independently connect to VDD or VSS via a resistor.
P147/ANI18 11-U I/O Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
RESET 2 input Directly or independently connect to VDD via a resistor.
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 2 PIN FUNCTIONS
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Figure 2-1. Pin I/O Circuit List (1/2)
Type 2 Type 5-AN
Schmitt-triggered input with hysteresis characteristics
IN
pull-up
enable
data
output
disable
P-ch
VDD
VDD
VSS
P-ch
IN/OUT
N
-ch
CMOS
TTL
input
characteristic
Type 8-R Type 13-R
data
output
disable
VDD
P-ch
IN/OUT
N-ch
VSS
pullup
enable
VDD
P-ch
IN/OUT
N
-ch
data
output disable
VSS
Type 37-C Type 42-B
X1
input
enable
input
enable
P-ch
N-ch
X2
amp
enable
IN
pullup
enable
V
DD
P-ch
reset mask
reset
input enable SCHMIT
RL78/G12 CHAPTER 2 PIN FUNCTIONS
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Sep. 28, 2012
Figure 2-1. Pin I/O Circuit List (2/2)
Type 11-G Type 11-T
data
output
disable
V
DD
P-ch
IN/OUT
N-ch
input enable
V
SS
P-ch
N-ch
+
_
VSS
Series resistor string voltage
Comparator
data
output
disable
V
DD
P-ch
IN/OUT
N-ch
P-ch
N-ch
input enable
AV
REFP
, AV
REFM
V
SS
P-ch
N-ch
+
_
V
SS
Series resistor string voltage
Comparator
Type 11-U Type 11-V
pull-up
enable
data
output
disable
P-ch
V
DD
V
DD
V
SS
V
SS
P-ch
IN/OUT
N
-ch
P-ch
N-ch
+
_
input enable
Series resistor string voltage
Comparator
pull-up
enable
data
output
disable
P-ch
V
DD
V
DD
V
SS
P-ch
IN/OUT
N
-ch
CMOS
TTL
input
characteristic
P-ch
N-ch
+
_
V
SS
Series resistor string voltage
Comparator
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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CHAPTER 3 CPU ARCHITECT U RE
3.1 Memory Space
Products in the RL78/G12 can access a 1 MB memory space. Figures 3-1 to 3-6 show the memory maps.
Figure 3-1. Memory Map for th e R5F10266 and R5F10366
FFFFFH
FFF00H
FFEFFH
00800H
007FFH
00000H
FFE00H
FFDFFH
F1800H
F17FFH
F1000H
F0FFFH
FFEE0H
FFEDFH
F0000H
EFFFFH
F0800H
F07FFH
007FFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAM
Notes 1, 2
256 bytes
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Data flash memory
Note 4
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 3
On-chip debug
security ID setting area
10 bytes
Note 3
Code flash memory
2KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1 When the data flash memory is rewritten, the stack used for the data flash library should be set to
FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer should be set to
FFE00H to FFE19H. For details, refer to RL78 Family Data Flash Library Type04 User’s Manual..
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the optio n bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. Provided in R5F10266 only.
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Caution 1. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where
data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM
areas, respecti vely. Reset signal generation sets RAM parity error resets to en abled (RPERDIS =
0). For details, see 21.3.3 RAM parity error detection function.
2. The RAM in the R5F10266 has capacity as small as 256 bytes. Depending on the customer’s
program specification, the stack area to execute the data flash library may not be kept and data
may not be written to or erased from the data flash memory. For details, refer to RL78 Family
Data Flash Library Type04 User’s Manual.
3. The self-programming function cannot be used in the R5F10266 and R5F10366
<R>
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RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Figure 3-2. Memory Map for the R5F10x67, and R5F10x77, and R5F10xA7 (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
01000H
00FFFH
00000H
FFD00H
FFCFFH
F1800H
F17FFH
F1000H
F0FFFH
FFEE0H
FFEDFH
F0000H
EFFFFH
F0800H
F07FFH
00FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAM
Notes 1, 2
512 bytes
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Data flash memory
Note 4
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 3
On-chip debug
security ID setting area
10 bytes
Note 3
Code flash memory
4KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1. Use of the area FFE20H to FFEFFH is prohibited when using the self-programming function an d data flash
function, because this area is used for self-pr ogramming library.
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chi p debug security IDs to 000C4H to 000CDH.
4. Provided in R5F10267, R5F10277, and R5F102A7 onl y.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection function.
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Figure 3-3. Memory Map for the R5F10x68, R5F10x78, and R5F10xA8 (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
02000H
01FFFH
00000H
FFC00H
FFBFFH
F1800H
F17FFH
F1000H
F0FFFH
FFEE0H
FFEDFH
F0000H
EFFFFH
F0800H
F07FFH
01FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAM
Notes 1, 2
768 bytes
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Data flash memory
Note 4
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 3
On-chip debug
security ID setting area
10 bytes
Note 3
Code flash memory
8KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-
programming function and data flash function are used. In R5F 10x68, R5F10x78, FFC00H to F FC80H area
cannot be used.
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. Provided in R 5F10268, R5F10278, and R5102A8 only.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection function.
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Figure 3-4. Memory Map for the R5F10x69, R5F10x79, and R5F10xA9 (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
03000H
02FFFH
00000H
FFB00H
FFAFFH
F3000H
F2FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
FFEE0H
FFEDFH
02FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAMNotes 1, 2
1KB
Prohibited area
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Mirror
4KB
Data flash memoryNote 4
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 3
On-chip debug
security ID setting area
10 bytes
Note 3
Code flash memory
12KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1. FFE20H to FFC80H area used by the self-programming libraries ca nnot be used when the self-
programming function and data flash function are used. In R5F10x69, R5F10x79, FFB00H to FFC80H area
cannot be used.
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. Provided in R5F10269, R5F10279, and R5F102A9 only.
Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize R AM areas w here data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
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Figure 3-5. Memory Map for th e R5F10x6A, R5F10x7A (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
04000H
03FFFH
00000H
FF900H
FF8FFH
F4000H
F3FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
FFEE0H
FFEDFH
03FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAM
Notes 1, 2
1.5 KB
Prohibited area
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Mirror
8KB
Data flash memory
Note 4
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 3
On-chip debug
security ID setting area
10 bytes
Note 3
Code flash memory
16KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1. FFE20H to FFEFFH and FF900H to FFC80H area used by the self-programming libraries cannot be used
when the self-programming function and d ata flash functio n are used.
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chip debug security IDs to 000C4H to 000CDH.
4. Provided in R5F1026A and R5F1027A only.
Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection function.
<R>
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Figure 3-6. Memory Map for the R5F10xAA (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
F0000H
EFFFFH
F0800H
F07FFH
04000H
03FFFH
00000H
FFEE0H
FFEDFH
FF700H
FF6FFH
F4000H
F3FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
03FFFH
000CEH
000CDH
000C4H
000C3H
000C0H
000BFH
00080H
0007FH
00000H
User RAM
Note 1
2 KB
Prohibited area
Prohibited area
Prohibited area
Program area
CALLT table area
64 bytes
Vector table area
128 bytes
Prohibited area
Mirror
8KB
Data flash memory
Note 3
2KB
Data memory
space
Program
memory
space
Option byte area
4 bytes
Note 2
On-chip debug
security ID setting area
10 bytes
Note 2
Code flash memory
16KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-
programming function and data flash function are used.
2. Instructions can be executed from the RAM area e xc luding the general-pur pose register area.
3. Set the option bytes to 000C0H to 000C3H, and the on-chi p debug security IDs to 000C4H to 000CDH.
4. Provided in R 5F102AA only.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers, see
Table 3-1 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 0FH
03FFFH
03C00H
03BFFH
00400H
003FFH
007FFH
00000H
Block 01H
Block 00H 1 KB
(For the R5F1026A and R5F1027A)
Correspondence between the address values and block numbers in the flash memory are shown below.
Table 3-1. Correspondence Between Address Values and Block Numbers in Flash Memory
Address Value Block Number product
00000H to 003FFH 00H
00400H to 007FFH 01H
R5F10x66
00800H to 00BFFH 02H
00C00H to 00FFFH 03H
R5F10x67
R5F10x77
01000H to 013FFH 04H
01400H to 017FFH 05H
01800H to 01BFFH 06H
01C00H to 01FFFH 07H
R5F10x68
R5F10x78
02000H to 023FFH 08H
02400H to 027FFH 09H
02800H to 02BFFH 0AH
02C00H to 02FFFH 0BH
R5F10x69
R5F10x79
03000H to 033FFH 0CH
03400H to 037FFH 0DH
03800H to 03BFFH 0EH
03C00H to 03FFFH 0FH
R5F10x6A
R5F10x7A
R5F10xAA
(x = 2, 3)
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3.1.1 Internal program memory space
The internal program memory space stores the program an d table data.
The RL78/G12 products incorporate internal ROM (flash memory), as shown below.
Table 3-2. Internal ROM Capacity
Internal ROM Part Number
Structure Capacity
R5F10x66 2048 × 8 bits (00000H to 07FFFH)
R5F10x67, R5F10x77, R5F10xA7 4096 × 8 bits (00000H to 00FFFH)
R5F10x68, R5F10x78, R5F10xA8 8192 × 8 bits (00000H to 01FFFH)
R5F10x69, R5F10x79, R5F10xA9 12288 × 8 bits (00000H to 02FFFH)
R5F10x6A, R5F10x7A, R5F10xAA
Flash memory
16384 × 8 bits (00000H to 03FFFH)
(x = 2 or 3)
The internal program memory space is divided into the following areas.
(1) Vector table area
The 128-byte area of 000 00H to 0007FH is reserved as a vector table ar ea. The program start addresses for branch
upon reset or generation of ea ch interrupt request are store d in the vector t able area. Furthermore, the interrupt jump
addresses are assigned to a 64 KB address area of 00000H to 0FFFFH, because the vector code is 2 bytes.
Of 16-bit addresses, the lower 8 bits are stored at even addresses and the high er 8 bits are stored at odd addresses.
<R>
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Table 3-3. Vector Table (20-, 24-pin products)
Vector Table Address Interrupt Source
0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE
0004H INTWDTI
0006H INTLVI
0008H INTP0
000AH INTP1
000CH INTP2
000EH INTP3
0010H INTDMA0Note
0012H INTDMA1Note
0014H INTST0/INTCSI00/INTIIC00Note
0016H INTSR0/INTCSI01Note/INTIIC01Note
0018H INTSRE0
001AH INTTM01H
001CH INTTM03H
001EH INTIICA0
0020H INTTM00
0022H INTTM01
0024H INTTM02
0026H INTTM03
0028H INTAD
002AH INTIT
002CH INTKR
002EH INTMD
0030H INTFL
007EH BRK
Note R5F102 products.
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Table 3-4. Vector Table (30-pin products)
Vector Table Address Interrupt Source
0000H RESET, POR, LVD, WDT, TRAP, IAW, RPE
0004H INTWDTI
0006H INTLVI
0008H INTP0
000AH INTP1
000CH INTP2
000EH INTP3
0010H INTP4
0012H INTP5
0014H INTST2/INTCSI20Note/INTIIC20Note
0016H INTSR2Note
0018H INTSRE2Note
001AH INTDMA0Note
001CH INTDMA1Note
001EH INTST0/INTCSI00/INTIIC00Note
0020H INTSR0
0022H INTSRE0/INTTM01H
0024H INTST1Note
0026H INTSR1Note/INTCSI11Note/INTIIC11Note
INTFL 0028H
INTTM03H
002AH INTIICA0
002CH INTTM00
002EH INTTM01
0030H INTTM02
0032H INTTM03
0034H INTAD
0038H INTIT
0042H INTTM04
0044H INTTM05
0046H INTTM06
0048H INTTM07
005EH INTMD
0062H INTFL
007EH BRK
Note R5F102 products.
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(2) CALLT instruction table area
The 64-byte area of 00080H to 000BFH can store the subroutine entry address of a 2-byte call instruction (CALLT).
Set the subroutine entry address to a value in a range of 00000H to 0FFFFH (because an address code is 2 bytes).
(3) Option byte area
The 4-byte area of 000C0H to 000C3H can b e used as an option byte area . For details, see CHAPTER 23 OPTION
BYTE.
(4) On-chip debug security ID setting area
The 10-byte areas of 000C4H to 000CDH and 010C4H to 010CDH can be used as an on-chip debug security ID
setting area. For details, see CHAPTER 25 ON-CHIP DEBUG FUNCTION.
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3.1.2 Mirror area
The products with 12/16 KB flash memory mirror the code flash area of 02000H to 02FFF/03FFFHH to the area of
F2000H to F2FFFH/03FFFH (the code flash area to be mirrored is set by the processor mode control register (PMC)).
By reading data from F2000H to F2FFFH/03FFFH, an instruction that does not have the ES register as an operand can
be used, and thus the contents of the code flash can be read with the shorter code. However, the code flash area is not
mirrored to the SFR, extended SFR, RAM, and use prohibited areas.
See 3.1 Memory Space for the mirror area of each product.
The mirror area can only be read and no instruction can be fetched from this area.
The following shows examples.
Example R5F1026A and RF5F1027A (Flash memory: 16 KB, RAM: 1.5 KB)
F
FFFFH
F
FF00H
F
FEFFH
F
FEE0H
F
FEDFH
F
F900H
F
F8FFH
F
4000H
F
3FFFH
F
2000H
F
1FFFH
F
1800H
F
17FFH
F
1000H
F
0FFFH
F
0800H
F
07FFH
E
0000H
E
FFFFH
0
4000H
0
3FFFH
0
2000H
0
1FFFH
0
0000H
Code flash memory
Code flash memory
Data flash memory
Mirror (same data as that
in 02000H to 03FFFH)
Use prohibited
Use prohibited
Use prohibited
Use prohibited
Special function register (2nd SFR)
2 KB
Mirror
Special function register (SFR)
256 bytes
General-purpose register
32 bytes
RAM
1.5 KB
For example, 03789H is mirrored
to F3789H.
Data can therefore be read by
MOV A, !3789H
instead of
MOV ES, #00H
MOV A, ES:!3789H.
The PMC register is described below.
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• Processor mode control register (PMC)
This register sets the flash memory space for mirroring to the area from F0000H to FFFFFH.
The PMC register can be set by a 1-bit or 8-bit memory manipu lation instruction.
Reset signal generation sets this register to 00H.
Figure 3-7. Format of Conf ig uration of Processor Mode Control Register (PMC)
Address: FFFFEH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
PMC 0 0 0 0 0 0 0 MAA
MAA Selection of flash memory space for mirroring to the area from F0000H to FFFFFH
0 00000H to 0FFFFH is mirrored to F0000H to FFFFFH
1 Setting prohibited
Caution 1. Be sure to clear bit 0 (MAA) of this register to 0 (default value).
2. After setting the PMC register, wait for at least one instruction and access the mirr or area.
3.1.3 Internal data memory space
The RL78/G12 products incorporate the follo wing RAMs.
Table 3-5. Internal RAM Capacity
Part Number Internal RAM
R5F10x66 256 × 8 bits (FFE00H to FFEFFH)
R5F10x67, R5F10x77, R5F10xA7 512 × 8 bits (FFD00H to FFEFFH)
R5F10x68, R5F10x78, R5F10xA8 768 × 8 bits (FFC00H to FFEFFH)
R5F10x69, R5F10x79, R5F10xA9 1024 × 8 bits (FFB00H to FFEFFH)
R5F10x6A, R5F10x7A 1536 × 8 bits (FF900H to FFEFFH)
R5F10xAA 2048 × 8 bits (FF700H to FFEFFH)
(x = 2 or 3)
The internal RAM can be us ed as a data area and a program area where instructions are fetched (it is prohib ited
to usethe general-purpose register area for fetching instruct ions). Four general-purpose register, banks consisting of
eight 8-bit registers registers per bank are assigned to the 32-byte area of FFEE0H to FFEFFH of the internal RAM
area.
The internal RAM is used as a stack memory.
Cautions 1. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching
instructions or as a stack ar ea.
2. When self-programming is performed or the data flash memory is rewritten, the stack used for
each library and the RAM address used for the data buffer and DMA transfer should not be set to
the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User’s
Manual.
R5F10266 : FFE20H-FFEA1H，FFEE0H-FFEFFH
(The stack used for the data flash library should be set
to FFEA2H to FFEDFH and the RAM address used for
the data buffer and DMA transfer should be set to
FFE00H to FFE19H.)
R5F102mn, R5F103mn :FFE20H-FFEA1H
<R>
<R>
<R>
<R>
<R>
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Remark m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A)
3. Use ofthe RAM areas of the following products is prohibited, because these areas are used for
self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map)
R5F102m8, R5F103m8: FFC00H to FFC80H
R5F102m9, R5F103m9: FFB00H-FFC80H
R5F102mA, R5F103mA: FF900H-FFC80H
Remarks m: Pin count (m = 6, 7)
<R>
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3.1.4 Special function register (SFR) area
On-chip peripheral hardware special function registers (SFRs) are allocated in the area of FFF00H to FFFFFH (see
Table 3-6 in 3.2.4 Special function registers (SFRs)).
Caution Do not access addresses to which SFRs are not assigned.
3.1.5 Extended special function register (2nd SFR: 2nd Special Function Register) area
On-chip peripheral hardware special function registers (2nd SFRs) are all ocated in the a rea of F0000 H to F07F FH (see
Table 3-7 in 3.2.5 Extended Special function registers (2nd SFRs: 2nd Special Function Registers)).
SFRs other than those in the SFR area (FFF00H to FFFFFH) are allocated to this area. An instruction that accesses
the extended SFR area, however, is 1 byte longer than an instruction that accesses the SFR area.
Caution Do not access addresses to which extended SFRs are not assign ed.
3.1.6 Data memory addressing
Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the
register or memory relevant to the execution of instructions.
Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the
RL78/G12, based on operability and other considerations. In particular, special addressing methods designed for the
functions of the special function registers (S FR) and general-purpose registers are av ailable for use. Figures 3-8 to 3-13
show correspondence between data memory and addressing.
For details of each addressing, see 3.4 Addressing for Processing Data Addresses.
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Figure 3-8. Correspondence Between Data Memory and A ddressing for the R5F10266 and R5F10366
User RAM
256 bytes
Prohibited area
Prohibited area
Prohibited area
Data flash memory
Note
2KB
Code flash memory
2KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. When the data flash memory is rewritten, the stack used for the data flash library should be set to FFEA2H
to FFEDFH and the RAM address used for the data buffer and DMA trans fer should be set to FFE00H to
FFE19H. For details, refer to RL78 Family Data Flash Libra ry Type04 User’s Manual.
2. Provided in R5F10266 onl y.
Caution 1. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where
data access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM
areas, respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS =
0). For details, see 21.3.2 RAM parity error detection.
2. The RAM in the R5F10266 has capacity as small as 256 bytes. Dependi ng on the customer’s
program specification, the stack area to e xecu te the data flash library may not be kept and data
may not be written to or erased from the data flash memory. For details, refer to RL78 Family Data
Flash Library Type04 User’s Manual.
3. The self-programming function cannot be used for R5F10266 and R5F10366.
<R>
<R>
<R>
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Figure 3-9. Correspondence Between Data Memory and Addressing for the R5F10x67, R5F10x77,
R5F10xA7
(x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
01000H
00FFFH
00000H
FFF20H
FFF1FH
FFEE0H
FFEDFH
FFE20H
FFE1FH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
FFD00H
FFCFFH
User RAM
512 bytes
Prohibited area
Prohibited area
Prohibited area
Data flash memory
Note
2KB
Code flash memory
4KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-
programming function and data flash function are used.
2. Provided in R5F10267, R5F10277, and R5F102A7 onl y.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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Figure 3-10. Correspondence Between Data Memory and Addressing for the R5F10x68, R5F10x78, and R5F10xA8
(x = 2 or 3)
User RAM Note 1
768 bytes
Prohibited area
Prohibited area
Prohibited area
Data flash memory Note 2
2KB
Code flash memory
8KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-programming
function and data flash function are used. In R5F10x68, R5F10x78, FFC00H to FFC80H area cannot b e
used.
2. Provided in R5F10268, R5F10278, and R5F 102A8 only.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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Figure 3-11. Correspondence Between Data Memory and Addressing for the (R5F10x69, R5F10x79, and
R5F10xA9 (x = 2 or 3)
FFFFFH
FFF00H
FFEFFH
FFF20H
FFF1FH
FFEE0H
FFEDFH
FFE20H
FFE1FH
03000H
02FFFH
00000H
FFB00H
FFAFFH
F3000H
F2FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
User RAM Note 1
1KB
Prohibited area
Prohibited area
Mirror
4KB
Prohibited area
Prohibited area
Data flash memory Note 2
2KB
Code flash memory
12KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-programming
function and data flash function are used. In R5F10x69, R5F10x79, FFC00H to FFC80H area cannot b e
used.
2. Provided in R5F10269, R5F10279, and R5F 102A9 only.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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Figure 3-12. Correspondence Between Data Memory and Addressing for the R5F10x6A, and R5F10x7A (x = 2 or 3)
FFFFFH
FFE20H
FFE1FH
FFEE0H
FFEDFH
FFF00H
FFEFFH
00000H
FFF20H
FFF1FH
FF900H
FF8FFH
F4000H
F3FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
FF9C0H
FF9BFH
04000H
03FFFH
User RAM
Note 1
1.5KB
Prohibited area
Prohibited area
Mirror
8KB
Prohibited area
Prohibited area
Data flash memory
Note 2
2KB
Code flash memory
16KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. FFE20H to FFEFFH and FF900H to F FC80H area used by the self-programming libraries cannot be used
when the self-programming function and d ata flash functio n are used.
2. Provided in R5F1026A and R5F1027A only.
Caution. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize R AM areas w here data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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Figure 3-13. Correspondence Between Data Memory and Addressing for the R5F10xAA (x = 2 or 3)
FFFFFH
FFE20H
FFE1FH
FFEE0H
FFEDFH
FFF00H
FFEFFH
04000H
03FFFH
00000H
FFF20H
FFF1FH
FF700H
FF6FFH
F4000H
F3FFFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0000H
EFFFFH
F0800H
F07FFH
RAM
2KB
Prohibited area
Prohibited area
Mirror
8KB
Prohibited area
Prohibited area
Data flash memoryNote
2KB
Code flash memory
16KB
SFR 256 bytes
2nd SFR 2KB
General-purpose
register 32 bytes
SFR addressing
Register addressing Short direct
addressing
Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Notes 1. FFE20H to FFEFFH area used by the self-programming libraries cannot be used when the self-
programming function and data flash function are used.
2. Provided in R5F102AA onl y.
Caution While RAM parity error res ets are enabled (RPERDIS = 0), be sure to in itialize RAM areas where data
access is to proceed and the RAM area +10 bytes when instructions are fetched from RAM areas,
respectively. Reset signal generation sets RAM parity error resets to enabled (RPERDIS = 0). For
details, see 21.3.2 RAM parity error detection.
<R>
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3.2 Processor Registers
The RL78/G12 products incor porate the following processor registers.
3.2.1 Control registers
The control registers control the program sequence, statuses and stack memory. The control registers consist of a
program counter (PC), a program status word (PSW) and a stack pointer ( SP).
(1) Program counter (PC)
The program counter is a 20-bit register that holds the a ddress information of the next program to be executed.
In normal operation, PC is automatically incr emented according to the nu mber of bytes of the instruction to be fetched .
When a branch instruction is executed, immediate data and register contents are set.
Reset signal generation sets the reset vector table values at addresses 0000H and 0001H to the 16 lower-order bits
of the program counter. The four higher-order bits of the program counter are cleared to 0000.
Figure 3-14. Format of Program Counter
19
P
C
0
(2) Program status wo rd (PSW)
The program status word is an 8-bit register consistin g of various flags set/reset by instruct ion execution.
Program status word contents are stored in the stack area upon acknowledgment of a vectored interrupt request or
PUSH PSW instruction execution, and are restored upon execution of the RETB, RETI and POP PSW instructions.
Reset signal generation sets the PSW register to 06H.
Figure 3-15. Format of Program Status Word
IE Z RBS1 AC RBS0 ISP0 CY
70
ISP1PSW
(a) Interrupt enable flag (IE)
This flag controls the interrupt request acknowledge operations of the CPU.
When 0, the IE flag is set to the interrupt disabled (DI) state, and all maskable int errupt requests are disabled.
When 1, the IE flag is set to the int errupt enabled (EI) state, and interrupt request ackno wledgment is controll ed
with an in-service priority flag (ISP1, ISP0), an interrupt mask flag for various interrupt sources, and a priority
specification flag.
The IE flag is reset (0) upon DI instruction execution or interrupt acknowledgment and is set (1) upon EI
instruction execution.
(b) Zero flag (Z)
When the operation or compa rison result is zero or equal, this flag is set (1). It is reset (0) in all other cases.
(c) Register bank select flags (RBS0, RBS1)
These are 2-bit flags to select one of the four register banks.
In these flags, the 2-bit information that indicates the re gister bank selected by SEL RBn instruction e xecution is
stored.
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(d) Auxiliary carry flag (AC)
If the operation result has a carr y from bit 3 or a borro w at bit 3, this flag is s et (1). It is reset (0) in all oth er cases.
(e) In-service priority flags (ISP1, ISP0)
These flags manage the priority of acknowledgeable maskable vectored interrupts. Vectored interrupt requests
specified lower than the value of ISP0 and ISP1 flags by the priorit y specification flag registers (PR00 L, PR00H,
PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (see 15.3 (3)) can not be
acknowledged. Actual vectored interrupt request acknowledgment is controlled by the interrupt enable flag (IE).
Remark n = 0, 1
(f) Carry flag (CY)
This flag stores overflow and underflo w upon add/subtract instruction execution. It stores the shift-out value up on
rotate instruction execution and functions as a bit accumulator during bit operation instru ction execution.
(3) Stack pointer (SP)
This is a 16-bit register to hol d the start addr ess of the memor y stack area. Only the internal RAM area can be set a s
the stack area.
Figure 3-16. Format of Stack Pointer
15
SP
SP15 SP14 SP13 SP12 SP11 SP10
SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
0
In stack addressing through a stack pointer, the SP is decremented ahead of write (save) to the stack memory and is
incremented after read (restore) from the stack memor y. Each stack operation saves data as shown in Figure 3- 17.
Cautions 1. Since reset signal g en eratio n makes the SP contents undefined, be sure to initialize the SP
before using the stack.
2. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching
instructions or as a stack ar ea.
3. When self-programming is performed or the data flash memory is rewritten, the stack used for
each library and the RAM address used for the data buffer and DMA transfer should not be set to
the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User’s
Manual.
R5F10266 : FFE20H-FFEA1H，FFEE0H-FFEFFH
(The stack used for the data flash library should be set
to FFEA2H to FFEDFH and the RAM address used for
the data buffer and DMA transfer should be set to
FFE00H to FFE19H.)
R5F102mn, R5F103mn :FFE20H-FFEA1H
Remarks m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A)
4. Use of the RAM areas of the following products is prohibited, because these areas are used for
self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map)
R5F102m8, R5F103m8: FFC00H to FFC80H
R5F102m9, R5F103m9: FFB00H-FFC80H
R5F102mA, R5F103mA: FF900H-FFC80H
Remarks m: Pin count (m = 6, 7)
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Figure 3-17. Data to Be Saved to Stack Memory
PC7 to PC0
PC15 to PC8
PC19 to PC16
PSW
Interrupt, BRK instruction
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
CALL, CALLT instructions
Register pair lower
Register pair higher
PUSH rp instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
(4-byte stack) (4-byte stack)
PC7 to PC0
PC15 to PC8
PC19 to PC16
00H
SP←SP−4
↑
SP−4
↑
SP−3
↑
SP−2
↑
SP−1
↑
SP →
00H
PSW
PUSH PSW instruction
SP←SP−2
↑
SP−2
↑
SP−1
↑
SP →
3.2.2 General-purpose registers
General-purpose registers ar e mapped at particular a ddresses (FF EE0H to FFEFFH) of the data memory. The general-
purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-b it register , and t wo 8-bit registers can also b e used in a pair as a 16- bit register (A X,
BC, DE, and HL).
These registers can be described in terms of function nam es (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and absolute
names (R0 to R7 and RP0 to RP3).
Register banks to be us ed for instructio n exec ution are set b y the CPU c ontrol instructi on (SEL RBn). B ecaus e of the 4-
register bank configuration, an efficient prog ram can be created by switching bet ween a register for normal processing and
a register for interrupts for each bank.
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Cautions 1. It is prohibited to use the general-purpose register space (FFEE0H to FFEFFH) for fetching
instructions or as a stack ar ea.
2. When self-programming is performed or the data flash memory is rewritten, the stack used for
each library and the RAM address used for the data buffer and DMA transfer should not be set to
the RAM area of the following products. For details, refer to RL78 Family sh Library Type04 User’s
Manual.
R5F10266 : FFE20H-FFEA1H，FFEE0H-FFEFFH
(The stack used for the data flash library should be set
to FFEA2H to FFEDFH and the RAM address used for
the data buffer and DMA transfer should be set to
FFE00H to FFE19H.)
R5F102mn, R5F103mn :FFE20H-FFEA1H
Remark m: Pin count (m = 6, 7, A), n: ROM capacitance (n = 7, 8, 9, A)
3. Use of the RAM areas of the following products is prohibited, because these areas are used for
self-programming library and data flash library. (Refer to figure 3-3 to figure 3-5, Memory Map)
R5F102m8, R5F103m8: FFC00H to FFC80H
R5F102m9, R5F103m9: FFB00H-FFC80H
R5F102mA, R5F103mA: FF900H-FFC80H
Remark m: Pin count (m = 6, 7)
Figure 3-18. Configuration of General-Purpose Registers
(a) Function name
Register bank 0
Register bank 1
Register bank 2
Register bank 3
FFEFFH
FFEF8H
FFEE0H
HL
DE
BC
AX
H
15 0 7 0
L
D
E
B
C
A
X
16-bit processing 8-bit processing
FFEF0H
FFEE8H
<R>
<R>
<R>
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Sep. 28, 2012
3.2.3 ES and CS registers
The ES register is used for data access and the CS register is used to specify the higher address when a branch
instruction is executed.
The default value of the ES register after reset is 0FH, and that of the CS register is 00H.
Figure 3-19. Configuration of ES and CS Registers
0 0 0 0 ES3 ES2 ES1 ES0
70
ES
654321
0 0 0 0 CS3 CP2 CP1 CP0
70
CS
654321
Though the data area which can be accessed with 16-bit addresses is the 64 Kbytes from F0000H to FFFFFH, using the
ES register as well extends this to the 1 Mbyte from 00000H to FFFFFH.
Figure 3-20 Extension of Data Area Which Can Be Accessed
<R>
<R>
<R>
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
3.2.4 Special function registers (SFRs)
Unlike a general-purpose register, each SFR has a special function.
SFRs are allocated to the FFF00H to FFFFFH area.
SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
The manipulable bit units, 1, 8, and 16, depe nd on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe as follows for the 1-bit manipul ation instruction operand (sfr.bit).
When the bit name is defined: <B it name>
When the bit name is not defined: <Register name>, <Bit number> or <Address> , < Bit number>
• 8-bit manipulation
Describe the symbol defined by the assembl er for the 8-bit manip ulation instruction operand (sfr). This manipulation
can also be specified with an address
.• 16-bit manipulation
Describe the symbol defined by the assembl er for the 16-bit manipulation instruction operand (sfrp). When
specifying an address, describe an even address.
Table 3-6 gives a list of the SFRs. The meanings of items in the table are as follows.
• Symbol
Symbol indicating the address of a special function register. It is a reserved word in the assembler, and is defined
as an sfr variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and
simulator, symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipu lation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assign ed.
Remark For extended SFRs (2nd SFRs), see 3.2.5 Extended special function registers (2nd SFRs: 2nd Special
Function Registers).
<R>
<R>
<R>
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-6. SFR List (1/4)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF00H Port register 0 P0 R/W √ √ − 00H
FFF01H Port register 1 P1 R/W √ √ − 00H
FFF02H Port register 2 P2 R/W √ √ − 00H
FFF03H Port register 3 P3 R/W √ √ − 00H
FFF04H Port register 4 P4 R/W √ √ − 00H
FFF05H Port register 5 P5 R/W √ √ − 00H
FFF06H Port register 6 P6 R/W √ √ − 00H
FFF0CH Port register 12 P12 R/W
Note √ √ − Undefined
FFF0DH Port register 13 P13 R √ √ − Undefined
FFF0EH Port register 14 P14 R/W √ √ − 00H
FFF10H TXD0/
SIO00 − √
FFF11H
Serial data register 00
−
SDR00 R/W
− −
√ 0000H
FFF12H RXD0/
SIO01 − √
FFF13H
Serial data register 01
−
SDR01 R/W
− −
√ 0000H
FFF18H
FFF19H
Timer data register 00 TDR00 R/W − − √ 0000H
FFF1AH
TDR01L
− √ 00H
FFF1BH
Timer data register 01
TDR01H
TDR01 R/W
− √
√
00H
FFF1EH 10-bit A/D conversion result
register ADCR R − − √ 0000H
FFF1FH 8-bit A/D conversion
result register ADCRH R − √ − 00H
FFF20H Port mode register 0 PM0 R/W √ √ − FFH
FFF21H Port mode register 1 PM1 R/W √ √ − FFH
FFF22H Port mode register 2 PM2 R/W √ √ − FFH
FFF23H Port mode register 3 PM3 R/W √ √ − FFH
FFF24H Port mode register 4 PM4 R/W √ √ − FFH
FFF25H Port mode register 5 PM5 R/W √ √ − FFH
FFF26H Port mode register 6 PM6 R/W √ √ − FFH
FFF2CH Port mode register 12 PM12 R/W √ √ − FFH
FFF2EH Port mode register 14 PM14 R/W √ √ − FFH
FFF30H A/D converter mode register 0 ADM0 R/W √ √ − 00H
FFF31H Analog input channel
specification register ADS R/W √ √ − 00H
FFF32H A/D converter mode register 1 ADM1 R/W √ √ − 00H
FFF34H Key return control register KRCTL R/W √ √ − 00H
FFF35H Key return flag register KRF R/W √ √ − 00H
FFF36H Key return mode register 1 KRM1 R/W √ √ − 00H
FFF37H Key return mode register 0 KRM0 R/W √ √ − 00H
FFF38H External interrupt request rising
edge enable register 0 EGP0 R/W √ √ − 00H
FFF39H External interrupt request falling
edge enable register 0 EGN0 R/W √ √ − 00H
Note Read only for 30-pin product.
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-6. SFR List (2/4)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFF44H TXD1/
SIO10
− √
FFF45H
Serial data register 02
−
SDR02 R/W
− −
√ 0000H
FFF46H RXD1/
SIO11
− √
FFF47H
Serial data register 03
−
SDR03 R/W
− −
√ 0000H
FFF48H TXD2/
SIO20
− √
FFF49H
Serial data register 10
−
SDR10 R/W
− −
√ 0000H
FFF4AH RXD2/
SIO21
− √
FFF4BH
Serial data register 11
−
SDR11 R/W
− −
√ 0000H
FFF50H IICA shift register 0 IICA0 R/W − √ − 00H
FFF51H IICA status register 0 IICS0 R √ √ − 00H
FFF52H IICA flag register 0 IICF0 R/W √ √ − 00H
FFF64H
FFF65H
Timer data register 02 TDR02 R/W − − √ 0000H
FFF66H
TDR03L
− √ 00H
FFF67H
Timer data register 03
TDR03H
TDR03 R/W
− √
√
00H
FFF68H
FFF69H
Timer data register 04 TDR04 R/W − − √ 0000H
FFF6AH
FFF6BH
Timer data register 05 TDR05 R/W − − √ 0000H
FFF6CH
FFF6DH
Timer data register 06 TDR06 R/W − − √ 0000H
FFF6EH
FFF6FH
Timer data register 07 TDR07 R/W − − √ 0000H
FFF90H
FFF91H
Interval timer control register ITMC R/W − − √ 0FFFH
FFFA0H Clock operation mode control
register CMC R/W − √ − 00H
FFFA1H Clock operation status control
register CSC R/W √ √ − C0H
FFFA2H Oscillation stabilization time
counter status register OSTC R √ √ − 00H
FFFA3H Oscillation stabilization time
select register OSTS R/W − √ − 07H
FFFA4H System clock control register CKC R/W √ √ − 00H
FFFA5H Clock output selec t register 0 CKS0 R/W √ √ − 00H
FFFA6H Clock output selec t register 1 CKS1 R/W √ √ − 00H
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Table 3-6. SFR List (3/4)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFA8H Reset control flag register RESF R − √ − Undefined Note 1
FFFA9H Voltage detection register LVIM R/W √ √ − 00HNote 2
FFFAAH Voltage detection level register LVIS R/W √ √ − 00H/01H/81HNote 3
FFFABH Watchdog timer enable register WDTE R/W − √ − 1A/9ANote 4
FFFACH CRC input register CRCIN R/W − √ − 00H
FFFB0H DMA SFR address register 0 DSA0 R/W − √ − 00H
FFFB1H DMA SFR address register 1 DSA1 R/W − √ − 00H
FFFB2H DMA RAM address register 0L DRA0L R/W − √ 00H
FFFB3H DMA RAM address register 0H DRA0H
DRA0
R/W − √
√
00H
FFFB4H DMA RAM address register 1L DRA1L R/W − √ 00H
FFFB5H DMA RAM address register 1H DRA1H
DRA1
R/W − √
√
00H
FFFB6H DMA byte count register 0L DBC0L R/W − √ 00H
FFFB7H DMA byte count register 0H DBC0H
DBC0
R/W − √
√
00H
FFFB8H DMA byte count register 1L DBC1L R/W − √ 00H
FFFB9H DMA byte count register 1H DBC1H
DBC1
R/W − √
√
00H
FFFBAH DMA mode control register 0 DMC0 R/W √ √ − 00H
FFFBBH DMA mode control register 1 DMC1 R/W √ √ − 00H
FFFBCH DMA operation control register 0 DRC0 R/W √ √ − 00H
FFFBDH DMA operation control register 1 DRC1 R/W √ √ − 00H
FFFC0H − PFCMDNote 5 − − − − Undefined
FFFC2H − PFSNote 5 − − − − Undefined
FFFC4H − FLPMCNote 5 − − − − Undefined
FFFD0H Interrupt request flag register 2L IF2L R/W √ √ 00H
FFFD1H Interrupt request flag register 2H IF2H
IF2
R/W √ √
√
00H
FFFD4H Interrupt mask flag register 2L MK2L R/W √ √ FFH
FFFD5H Interrupt mask flag register 2H MK2H
MK2
R/W √ √
√
FFH
FFFD8H Priority specification flag register
02L PR02L R/W √ √ FFH
FFFD9H Priority specification flag register
02H PR02H
PR02
R/W √ √
√
FFH
FFFDCH Priority specification flag register
12L PR12L R/W √ √ FFH
FFFDDH Priority specification flag register
12H PR12H
PR12
R/W √ √
√
FFH
Notes 1. The reset value of the RESF register varies depending on the reset source.
2. The reset value of the LVIM register varies depending on the reset source.
3. The reset value of the LVIS register varies depending on the reset source and the setting of the
option byte.
4. The reset value of the WDTE register is determined by the setting of the option b yte.
5. Do not directly operate this SFR, because it is to be used in the self programming library.
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-6. SFR List (4/4)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W
1-bit 8-bit 16-bit
After Reset
FFFE0H Interrupt request flag register 0L IF0L R/W √ √ 00H
FFFE1H Interrupt request flag register 0H IF0H
IF0
R/W √ √
√
00H
FFFE2H Interrupt request flag register 1L IF1L R/W √ √ 00H
FFFE3H Interrupt request flag register 1H IF1H
IF1
R/W √ √
√
00H
FFFE4H Interrupt mask flag register 0L MK0L R/W √ √ FFH
FFFE5H Interrupt mask flag register 0H MK0H
MK0
R/W √ √
√
FFH
FFFE6H Interrupt mask flag register 1L MK1L R/W √ √ FFH
FFFE7H Interrupt mask flag register 1H MK1H
MK1
R/W √ √
√
FFH
FFFE8H Priority specification flag register
00L PR00L R/W √ √ FFH
FFFE9H Priority specification flag register
00H PR00H
PR00
R/W √ √
√
FFH
FFFEAH Priority specification flag register
01L PR01L R/W √ √ FFH
FFFEBH Priority specification flag register
01H PR01H
PR01
R/W √ √
√
FFH
FFFECH Priority specification flag register
10L PR10L R/W √ √ FFH
FFFEDH Priority specification flag register
10H PR10H
PR10
R/W √ √
√
FFH
FFFEEH Priority specification flag register
11L PR11L R/W √ √ FFH
FFFEFH Priority specification flag register
11H PR11H
PR11
R/W √ √
√
FFH
FFFF0H
FFFF1H
Multiplication/division data register
A (L) MDAL R/W − − √ 0000H
FFFF2H
FFFF3H
Multiplication/division data register
A (H) MDAH R/W − − √ 0000H
FFFF4H
FFFF5H
Multiplication/division data register
B (H) MDBH R/W − − √ 0000H
FFFF6H
FFFF7H
Multiplication/division data register
B (L) MDBL R/W − − √ 0000H
FFFFEH Processor mode control register PMC R/W √ √ − 00H
Remark For extended SFRs (2nd SFRs), see Table 3-7 Extended SFR (2nd SFR) List.
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
3.2.5 Extended special function regi sters (2nd SFRs: 2nd Special Function Registers)
Unlike a general-purpose register, each extended SF R (2nd SFR) has a special function.
Extended SFRs are allocated to the F0000H to F07FFH area. SFRs other than those in the SFR area (FFF00H to
FFFFFH) are allocated to this area. An instruction that accesses the extended SFR area, however, is 1 byte longer than
an instruction that accesses the SFR area.
Extended SFRs can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation
instructions. The manipulable bit units, 1, 8, and 16, depend on the SFR type.
Each manipulation bit unit can be specified as follows.
• 1-bit manipulation
Describe the symbol reserved by the assembler for the 1-bit manipulation instruction operand (!addr16.bit). This
manipulation can also be sp ecified with an address.
• 8-bit manipulation
Describe the symbol reserved by the assembler for the 8-bit manipulation instruction operand (!addr16). This
manipulation can also be sp ecified with an address.
• 16-bit manipulation
Describe the symbol reserved by the assembler for the 16-bit manipulation instruction operand (!addr16). When
specifying an address, describe an even address.
Table 3-7 gives a list of the extended SFRs. The meanin gs of items in the table are as follows.
• Symbol
S ymbol indicating the address of an extended SFR. It is a reserved word in the assembler, and is defined as an sfr
variable using the #pragma sfr directive in the compiler. When using the assembler, debugger, and simulator,
symbols can be written as an instruction operand.
• R/W
Indicates whether the corresponding extended SFR can be read or written.
R/W: Read/write enable
R: Read only
W: Write only
• Manipulable bit units
“√” indicates the manipulable bit unit (1, 8, or 16). “−” indicates a bit unit for which manipu lation is not possible.
• After reset
Indicates each register status upon reset signal generation.
Caution Do not access addresses to which extended SFRs are not assign ed.
Remark For SFRs in the SFR area, see 3.2.4 Special function registers (SFRs) .
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-7. Extended SFR (2nd SFR) List (1/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W 1-bit 8-bit 16-bit After Reset
F0010H A/D converter mode register 2 ADM2 R/W √ √ − 00H
F0011H Conversion result comparison
upper limit setting register ADUL R/W − √ − FFH
F0012H Conversion result comparison
lower limit setting register ADLL R/W − √ − 00H
F0013H A/D test register ADTES R/W − √ − 00H
F0030H Pull-up resistor option register 0 PU0 R/W √ √ − 00H
F0031H Pull-up resistor option register 1 PU1 R/W √ √ − 00H
F0033H Pull-up resistor option register 3 PU3 R/W √ √ − 00H
F0034H Pull-up resistor option register 4 PU4 R/W √ √ − 01H
F0035H Pull-up resistor option register 5 PU5 R/W √ √ − 00H
F0037H Pull-up resistor option register 7 PU7 R/W √ √ − 00H
F003CH Pull-up resistor op tion register 12 PU12 R/W √ √ − 00H
F003EH Pul l - u p r e sist o r op t ion regis t e r 14 PU14 R/W √ √ − 00H
F0040H Port input mode register 0 PIM0 R/W √ √ − 00H
F0041H Port input mode register 1 PIM1 R/W √ √ − 00H
F0050H Port output mode register 0 POM0 R/W √ √ − 00H
F0051H Port output mode register 1 POM1 R/W √ √ − 00H
F0054H Port output mode register 4 POM4 R/W √ √ − 00H
F0055H Port output mode register 5 POM5 R/W √ √ − 00H
F0060H Port mode control register 0 PMC0 R/W √ √ − FFH
F0061H Port mode control register 1 PMC1 R/W √ √ − FFH
F0064H Port mode control register 4 PMC4 R/W √ √ − FFH
F006CH Port mode control register 12 PMC12 R/W √ √ − FFH
F006EH Port mode control register 14 PMC14 R/W √ √ − FFH
F0070H Noise filter enable register 0 NFEN0 R/W √ √ − 00H
F0071H Noise filter enable register 1 NFEN1 R/W √ √ − 00H
F0074H Timer input select register 0 TIS0 R/W − √ − 00H
F0076H A/D port configuration register ADPC R/W − √ − 00H
F0077H Peripheral I/O redirection
register PIOR R/W − √ − 00H
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-7. Extended SFR (2nd SFR) List (2/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W 1-bit 8-bit 16-bit After Reset
F0078H Invalid memory access
detection control register IAWCTL R/W − √ − 00H
F0090H Data flash control register DFLCTL R/W √ √ − 00H
F00A0H High-speed on-chip oscillator
trimming register HOTRM R/W − √ − Undefined Note
F00A8H High-speed on-chip oscillator
frequency selecting register HOCODIV R/W − √ − Undefined
F00E0H Multiplication/division data
register C (L) MDCL R/W − − √ 0000H
F00E2H Multiplication/division data
register C (H) MDCH R/W − − √ 0000H
F00E8H Multiplication/division control
register MDUC R/W √ √ − 00H
F00F0H Peripheral enable register 0 PER0 R/W √ √ − 00H
F00F3H Operation speed mode control
register OSMC R/W − √ − 00H
F00F5H RAM parity error control register RPECTL R/W √ √ − 00H
F00FEH BCD adjust result register BCDADJ R − √ − Undefined
F0100H
SSR00L
− √
F0101H Serial status register 00
− SSR00 R
− −
√ 0000H
F0102H SSR01L − √
F0103H Serial status register 01
− SSR01 R
− −
√ 0000H
F0104H SSR02L − √ 0000H
F0105H Serial status register 02
− SSR02 R
− −
√ 0000H
F0106H SSR03L − √ 0000H
F0107H Serial status register 03
− SSR03 R
− −
√ 0000H
F0108H SIR00L − √
F0109H Serial flag clear trigger register
00 − SIR00 R/W
− −
√ 0000H
F010AH SIR01L − √
F010BH Serial flag clear trigger register
01 − SIR01 R/W
− −
√ 0000H
F010CH SIR02L − √
F010DH Serial flag clear trigger register
02 − SIR02 R/W
− −
√ 0000H
F010EH SIR03L − √
F010FH Serial flag clear trigger register
03 − SIR03 R/W
− −
√ 0000H
F0110H
F0111H Serial mode register 00 SMR00 R/W − − √ 0020H
F0112H
F0113H Serial mode register 01 SMR01 R/W − − √ 0020H
F0114H
F0115H Serial mode register 02 SMR02 R/W − − √ 0020H
F0116H
F0117H Serial mode register 03 SMR03 R/W − − √ 0020H
F0118H
F0119H Serial communication operation
setting register 00 SCR00 R/W − − √ 0087H
F011AH
F011BH Serial communication operation
setting register 01 SCR01 R/W − − √ 0087H
F011CH
F011DH Serial communication operation
setting register 02 SCR02 R/W − − √ 0087H
F011EH
F011FH Serial communication operation
setting register 03 SCR03 R/W − − √ 0087H
Note The value after a reset is adjusted at the time of shipment.
<R>
<R>
RL78/G12 CHAPTER 3 CPU ARCHITECTURE
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Sep. 28, 2012
Table 3-7. Extended SFR (2nd SFR) List (3/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W 1-bit 8-bit 16-bit After Reset
F0120H SE0L √ √
F0121H Serial channel enable status
register 0 − SE0 R
− −
√ 0000H
F0122H SS0L √ √
F0123H Serial channel start register 0
− SS0 R/W
− −
√ 0000H
F0124H ST0L √ √
F0125H Serial channel stop register 0
− ST0 R/W
− −
√ 0000H
F0126H SPS0L − √
F0127H Serial clock select register 0
− SPS0 R/W
− −
√ 0000H
F0128H
F0129H Serial output register 0 SO0 R/W − − √ 0F0FH
F012AH SOE0L √ √
F012BH Serial output enable register 0
− SOE0 R/W
− −
√ 0000H
F0134H SOL0L − √
F0135H Serial output level register 0
− SOL0 R/W
− −
√ 0000H
SSC0L − √ F0138H Serial standby control register 0
− SSC0 R/W
− −
√ 0000H
F0140H SSR10L − √
F0141H Serial status register 10
− SSR10 R
− −
√ 0000H
F0142H SSR11L − √
F0143H Serial status register 11
− SSR11 R
− −
√ 0000H
F0148H SIR10L − √
F0149H Serial flag clear trigger register
10 − SIR10 R/W
− −
√ 0000H
F014AH SIR11L − √
F014BH Serial flag clear trigger register
11 − SIR11
R/W
− −
√
0000H
F0150H − −
F0151H Serial mode register 10 SMR10 R/W
√ 0020H
F0152H − −
F0153H Serial mode register 11 SMR11 R/W
√ 0020H
F0158H − −
F0159H Serial communication operation
setting register 10 SCR10 R/W
√ 0087H
F015AH − −
F015BH Serial communication operation
setting register 11 SCR11 R/W
√ 0087H
F0160H SE1L √ √
F0161H Serial channel enable status
register 1 − SE1 R
− −
√ 0000H
F0162H SS1L √ √
F0163H Serial channel start register 1
− SS1 R/W
− −
√ 0000H
F0164H ST1L √ √
F0165H Serial channel stop register 1
− ST1 R/W
− −
√ 0000H
F0166H SPS1L − √
F0167H Serial clock select register 1
− SPS1 R/W
− −
√ 0000H
F0168H − −
F0169H Serial output register 1 SO1 R/W
√ 0F0FH
F016AH SOE1L √ √
F016BH Serial output enable register 1
− SOE1 R/W
− −
√ 0000H
F0174H SOL1L − √
F0175H Serial output level register 1
− SOL1 R/W
− −
√ 0000H
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Table 3-7. Extended SFR (2nd SFR) List (4/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W 1-bit 8-bit 16-bit After Reset
F0180H
F0181H Timer counter register 00 TCR00 R − − √ FFFFH
F0182H
F0183H Timer counter register 01 TCR01 R − − √ FFFFH
F0184H
F0185H Timer counter register 02 TCR02 R − − √ FFFFH
F0186H
F0187H Timer counter register 03 TCR03 R − − √ FFFFH
F0188H
F0189H Timer counter register 04 TCR04 R − − √ FFFFH
F018AH
F018BH Timer counter register 05 TCR05 R − − √ FFFFH
F018CH
F018DH Timer counter register 06 TCR06 R − − √ FFFFH
F018EH
F018FH Timer counter register 07 TCR07 R − − √ FFFFH
F0190H
F0191H Timer mode register 00 TMR00 R/W − − √ 0000H
F0192H
F0193H Timer mode register 01 TMR01 R/W − − √ 0000H
F0194H
F0195H Timer mode register 02 TMR02 R/W − − √ 0000H
F0196H
F0197H Timer mode register 03 TMR03 R/W − − √ 0000H
F0198H
F0199H Timer mode register 04 TMR04 R/W − − √ 0000H
F019AH
F019BH Timer mode register 05 TMR05 R/W − − √ 0000H
F019CH
F019DH
Timer mode register 06 TMR06 R/W − − √ 0000H
F019EH
F019FH
Timer mode register 07 TMR07 R/W − − √ 0000H
F01A0H TSR00L − √
F01A1H
Timer status register 00
−
TSR00 R
− −
√ 0000H
F01A2H TSR01L − √
F01A3H
Timer status register 01
−
TSR01 R
− −
√ 0000H
F01A4H TSR02L − √
F01A5H
Timer status register 02
−
TSR02 R
− −
√ 0000H
F01A6H TSR03L − √
F01A7H
Timer status register 03
−
TSR03 R
− −
√ 0000H
F01A8H TSR04L − √
F01A9H
Timer status register 04
−
TSR04 R
− −
√ 0000H
F01AAH TSR05L − √
F01ABH
Timer status register 05
−
TSR06 R
− −
√ 0000H
F01ACH TSR06L − √
F01ADH
Timer status register 06
−
TSR07 R
− −
√ 0000H
F01AEH TSR07L − √
F01AFH
Timer status register 07
−
TSR03 R
− −
√ 0000H
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Table 3-7. Extended SFR (2nd SFR) List (5/5)
Manipulable Bit Range Address
Special Function Register (SFR) Name
Symbol R/W 1-bit 8-bit 16-bit After Reset
F01B0H TE0L √ √
F01B1H
Timer channel enable status
register 0 −
TE0 R
− −
√ 0000H
F01B2H TS0L √ √
F01B3H
Timer channel start register 0
−
TS0 R/W
− −
√ 0000H
F01B4H TT0L √ √
F01B5H
Timer channel stop register 0
−
TT0 R/W
− −
√ 0000H
F01B6H
F01B7H
Timer clock select register 0 TPS0 R/W − − √ 0000H
F01B8H TO0L − √
F01B9H
Timer output register 0
−
TO0 R/W
− −
√ 0000H
F01BAH TOE0L √ √
F01BBH
Timer output enable register 0
−
TOE0 R/W
− −
√ 0000H
F01BCH TOL0L − √
F01BDH
Timer output level register 0
−
TOL0 R/W
− −
√ 0000H
F01BEH TOM0L − √
F01BFH
Timer output mode register 0
−
TOM0 R/W
− −
√ 0000H
F0230H IICA control register 00 IICCTL00 R/W √ √ − 00H
F0231H IICA control register 01 IICCTL01 R/W √ √ − 00H
F0232H IICA low-level width setting
register 0 IICWL0 R/W − √ − FFH
F0233H IICA high-level width setting
register 0 IICWH0 R/W − √ − FFH
F0234H Slave address register 0 SVA0 R/W − √ − 00H
F02FAH CRC data register CRCD R/W − − √ 0000H
Remark For SFRs in the SFR area, see Table 3-6 SFR List.
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3.3 Instruction Address Addressing
3.3.1 Relative addressing
[Function]
Relative addressing stores in the program counter (PC) the result of adding a displacement value included in the
instruction word (signed complement data: −12 8 to +127 or −32768 to +32767) to the program counter (PC)’s value
(the start address of the next instruction), and specifies the program address to be used as the branch destination.
Relative addressing is appl ied only to branch instructions.
Figure 3-21. Outline of Relative Addressing
3.3.2 Immediate addressing
[Function]
Immediate addressing stores immediate data of the instruction word in the program counter, and specifies the
program address to be used as the branch destination.
For immediate addressing, CALL !!addr20 or BR !!addr20 is used to specify 20-bit addresses and CALL !addr16 or
BR !addr16 is used to specify 16-bit ad dresses. 0000 is set to the higher 4 bits when specifying 16-bit addresses.
Figure 3-22. Example o f CALL !!addr20/ BR !!addr20
Figure 3-23. Example of CALL !addr16/BR !addr16
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3.3.3 Table indirect addres sin g
[Function]
Table indirect addressing specifies a table address in the CALLT table area (0080H to 00BFH) with the 5-bit
immediate data in the instruction word, stores the contents at that table a ddress an d the next address in the program
counter (PC) as 16-bit data, and specifies the program address. Table indirect addr essing is applied onl y for CALLT
instructions.
In the RL78 microcontrollers, branching is enabled only to the 64 KB space from 00000H to 0FFFFH.
Figure 3-24. Outline of Table Indirect Addressing
3.3.4 Register direct addressing
[Function]
Register direct addressing stores in the program counter (PC) the contents of a general-purpose register pair
(AX/BC/DE/HL) and CS register of the current register bank specified with the instruction word as 20-bit data, and
specifies the program address. Register direct addressi ng c an be a pplie d only to the CA LL A X, BC, DE, HL, and BR
AX instructions.
Figure 3-25. Outline of Register Direct Addressing
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3.4 Addressing for Processing Data Address es
3.4.1 Implied addressing
[Function]
Instructions for accessing registers (such as accumulators) that have special func tions are directly specified with the
instruction word, without using any register specification field in the instruction word.
[Operand format]
Implied addressing ca n be applied only to MULU X.
Figure 3-26. Outline of Implied Addressing
3.4.2 Register addressing
[Function]
Register addressing accesses a general- purpose register as an operand. The instruction word of 3-bit long is used
to select an 8-bit register and the instruction word of 2-bit long is used to select a 16- bit register.
[Operand format]
Identifier Description
r X, A, C, B, E, D, L, H
rp AX, BC, DE, HL
Figure 3-27. Outline of Register Addressing
Re g i st e r
OP code
Memory (register bank area
)
Instruction code
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3.4.3 Direct addressing
[Function]
Direct addressing uses immediate data in the instruction word as an operand address to directly specify the target
address.
[Operand format]
Identifier Description
ADDR16 Label or 16-bit immediate data (only the space from F0000H to FFFFFH is specifiable: automatically
added F of higher 4-bit addresses)
ES: ADDR16 Label or 16-bit immediate data (higher 4-bit addresses are specified by the ES register)
Figure 3-28. Example of ADDR16
Figure 3-29. Example of ES:ADDR16
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3.4.4 Short direct addressing
[Function]
Short direct addressing directly specifies the target addresses using 8-bit data in the instruction word. This type of
addressing is applied onl y to the spac e from F FE20H to FFF1FH.
[Operand format]
Identifier Description
SADDR Label or FFE20H to FFF1FH immediate data
SADDRP Label or FFE20H to FFF1FH immediate data (only even address is specifiable.)
Figure 3-30. Outline of Short Direct Addressing
Remark SADDR and SADDRP are used to describe the values of addresses FE20H to FF1FH with 16-bit immediate
data (higher 4 bits of actual address are omitted) , and the values of addresses FFE20H to FFF1FH with 20-
bit immediate data.
Regardless of whether SADDR or SADDRP is used, addresses within the space from FFE20H to FFF1FH
are specified for the memory.
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3.4.5 SFR addressing
[Function]
SFR addressing directly specifies the target SFR addresses using 8-bit data in the instruction word. This type of
addressing is applied only to the space from FFF00H to FFFFFH.
[Operand format]
Identifier Description
SFR SFR name
SFRP 16-bit-manipulatable SFR name (even address)
Figure 3-31. Outline of SFR Addressing
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3.4.6 Register indirect addressing
[Function]
Register indirect addressing directly specifies the target addresses using the contents of the register pair specified
with the instruction word as an operand a ddress.
[Operand format]
Identifier Description
− [DE], [HL] (only the space from F0000H to FFFFFH is specifiable)
− ES:[DE], ES:[HL] (higher 4-bit addresses are specified by the ES register)
Figure 3-32. Example of [DE], [HL]
Figure 3-33. Example of ES:[DE], ES:[HL]
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3.4.7 Based addressing
[Function]
Based addressing uses the contents of a register pair spe cified with the instruction word as a base address, and 8-
bit immediate data or 16-bit immediate data as offset data. The sum of these values is used to specify the target
address.
[Operand format]
Identifier Description
− [HL + byte], [DE + byte], [SP + byte] (only the space from F0000H to FFFFFH is specifiable)
− word[B], word[C] (only the space from F0000H to FFFFFH is specifiable)
− word[BC] (only the space from F0000H to FFFFFH is specifiable)
− ES:[HL + byte], ES:[DE + byte] (higher 4-bit addresses are specified by the ES register)
− ES:word[B], ES:word[C] (higher 4-bit addresses are specified by the ES register)
− ES:word[BC] (higher 4-bit addresses are specified by the ES register)
Figure 3-34. Example of [SP+byte]
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Figure 3-35. Example of [HL + byte], [DE + byte]
Figure 3-36. Example of word[B], word[C]
Figure 3-37. Example of word[BC]
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Figure 3-38. Example of ES:[HL + byte], ES:[DE + byte]
Figure 3-39. Example of ES:word[B], ES:word[C]
Figure 3-40. Example of ES:word[BC]
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3.4.8 Based indexed addressing
[Function]
Based indexed addressing uses the contents of a register pair specified with the instruction word as the base
address, and the content of the B register or C register sim ilarly sp ecified wit h the instruction word as offset address.
The sum of these values is used to specify the target address.
[Operand format]
Identifier Description
− [HL+B], [HL+C] (only the space from F0000H to FFFFFH is specifiable)
− ES:[HL+B], ES:[HL+C] (higher 4-bit addresses are specified by the ES register)
Figure 3-41 Example of [HL+B], [HL+C]
Figure 3-42. Example of ES:[HL+B], ES:[HL+C]
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3.4.9 Stack addressing
[Function]
The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing is automatically
employed when the PUSH, POP, subroutine call, and return instructions are executed or the register is
saved/restored upon generation of an interrupt request.
Stack addressing is applied o nly to the internal RAM area.
[Operand format]
Identifier Description
− PUSH AX/BC/DE/HL
POP AX/BC/DE/HL
CALL/CALLT
RET
BRK
RETB
(Interrupt request generated)
RETI
Figure 3-43. Example of PUSH rp
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Figure 3-44 Example of POP
Figure 3-45. Example of CALL, CALLT
Figure 3-46. Example of RET
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Figure 3-47. Example of Interrupt, BRK
Figure 3-48. Example of RETI, RETB
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CHAPTER 4 PORT FUNCTIONS
4.1 Port Functions
The RL78/G12 microcontrollers are provided with digital I/O ports, which enable variety of control operations.
In addition to the function as digital I/O port s, these ports have several alternate functions. For details of the alternate
functions, see CHAPTER 2 PIN FUNCTIONS.
4.2 Port Configuration
Ports include the following hardware.
Table 4-1. Port Configuration
Item Configuration
Control registers Port mode registers (PM0 to PM6, PM12, PM14)
Port registers (P0 to P06, P12 to P14)
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU12, PU14)
Port input mode register (PIM0, PIM1)
Port output mode registers (POM0, POM1, POM4, POM5)
Port mode control registers (PMC0, PMC1, PMC4, PMC12, PMC14)
A/D port configuration register (ADPC)
Peripheral I/O redirection register (PIOR)
Port • 20-pin products
Total: 18 (CMOS I/O: 12, CMOS input: 4, N-ch open drain I/O: 2)
• 24-pin products
Total: 22 (CMOS I/O: 16, CMOS input: 4, N-ch open drain I/O: 2)
• 30-pin products
Total: 26 (CMOS I/O: 21, CMOS input: 3, N-ch open drain I/O: 2)
Pull-up resistor • 20-pin products Total: 9
• 24-pin products Total: 13
• 30-pin products Total: 17
Caution Most of the following descriptions in this chapter use the R5F102 products.
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4.2.1 20, 24-pin products
(1) Port 0
Port 0 is an I/O port with an output latch (with 24-pin products). Port 0 can be set to the input mode or output mode in
1-bit units using port mode register 0 (PM0). When the P00 to P03 pins are used as a n input port, use of an on-chip
pull-up resistor can be specified in 1-bit units by pull-up resistor option register 0 (PU0).
Output from the P01 pin can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output
mode register 0 (POM0).
This port can also be used for ke y return input.
Reset signal generation sets port 0 to input mode.
Table 4-2. Settings of Registers When Using Port 0 (24-pin Products)
Pin
name I/O PM0× PIM0× POM0× PMC0× Alternate FunctionNote2 Buffer type
Input 1 − × CMOS input P00
Output 0
−
− × CMOS output
Input 1 × − × CMOS input
0 − CMOS output
P01
Output 0
1 −
(SO01/SDA01output = 1Note 1)
N-ch open-drain output
Input 1 − × CMOS input P02
Output 0 − (SCK01/SCL01output = 1Note 1)CMOS output
Input 1 − × CMOS input P03
Output 0
−
−
− × CMOS output
Notes 1. If P01, P02 are used as general-purpose port and PIOR3 is set to 1 in the R5F102 products, use bits 1 (SE01,
SO01, SOE01) of serial channel enable status register 0 (SE0), serial output register 0 (S O0), and serial
output enableregister 0 (SOE0) with the same setting as the initial status.
2. The descriptions in parentheses indicate the case where PIOR3 = 1.
Remark × : don' t care
PM0 : Port mode register 0
PIM0 : Port input mode register 0
POM0 : Port output mode register 0
PMC0 : Port mode control register 0
PIOR : Peripheral I/O redirection register
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Figures 4-1 to 4-3 show block diagrams of port 0.
Figure 4-1. Block Diagram of P00, and P03 (24-pin Products)
Internal bus
PM0
RD
WR
PM
P0
WR
PORT
P-ch
Selector
PU0
WR
PU
Alternate
function
V
DD
PU00, PU03
PM00, PM03
Output latch
(
P00, P03
)
P00/KR6/(SI01),
P03/KR9
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode regi ster 0
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Figure 4-2. Block Diagram of P01 (24-pin Products)
Internal bus
POM0
RD
WR
POM
P0
WR
PORT
P-ch
Selector
PU0
WR
PU
P01/KR7/(SO01/SDA01)
PM0
WR
PM
VDD
Alternate
function
PU01
PM01
Output latch
(P01)
POM01
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode regi ster 0
POM0: Port output mode register 0
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Figure 4-3. Block Diagram of P02 (24-pin Products)
Internal bus
PM0
RD
WRPM
P0
WRPORT
P-ch
Selector
PU0
WRPU
P01/KR8/(SCK01/SCL01)
VDD
Alternate
function
PU02
Output latch
(P02)
PM02
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode regi ster 0
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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(2) Port 1
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P14 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor opti on register 1 (PU1). At this time, in case of P10 to P12, set 0 in a bit of
port output mode register 1 (POM1) corresponding to the bit using an on-chip p ull-up register.
Input to the P10 and P11 pins can be specifi ed through a normal input buffer or a TTL input buffer in 1-bit units using
port input mode register 1 (PIM1).
Output from the P10 to P12 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port
output mode register 1 (POM1).
When P10 to P14 pins are used as input, specify them as either digital or analog in port mode co troll register 1
(PMC1). This register can be specified in 1-bit unit.
This port can also be used for analog input, clock/buzzer output, serial interface data I/O, clock I/O, timer I/O, and
external interrupt request input.
Reset signal generation sets port 1 to analog input.
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Table 4-3. Settings of Registers Wh en Using Port 1 (20-, 24-pin Products)
Pin
name I/O PM1× PIM1× POM1× PMC1× Alternate Function Buffer type
1 0 × 0 × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P10
Output
0 × 1
PCLBUZ0 output = 0Note 1
SCK00/SCL00 output = 1Note 1 N-ch open-drain output
1 0 × 0 × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P11
Output
0 × 1
SDA00 output = 1Note 2
N-ch open-drain output
Input 1 × 0 × CMOS input
0 0 CMOS output
P12
Output
0
−
1
SO00/TxD0 output = 1 Note 2
N-ch open-drain output
Input 1 0 × CMOS input P13
Output 0
− −
TO 0 0 output = 0 Note 3 CMOS output
Input 1 0 × CMOS input P14
Output 0
− −
TO 0 1 output = 0 Note 3 CMOS output
Cautions 1. When using P10/ANI16/PCLBUZ0/SCK00/SCL00 as a general-purpose port, use the bit 7
(PCLOE0) of clock output select register 0 (CKS0), serial chan nel enable status register 0 (SE0),
serial output register 0 (SO0), and use the each bit 0 (SE00, SO00, SOE00), serial channel
enable status register 0 (SOE 0) with the settings “0” same as the initial status.
2. When using P11/SI00/RxD0/SDA00/TOOLRxD/ANI17, P12/SO00/TxD0/TOOLTxD/ANI18 as a
general-purpose port, use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), use the each bi t 0 (SE00, SO00, SOE00), serial channel enable status regi ster 0
(SOE0) with the settings “0” same as the initial status.
3. When using P13/ ANI19/TI00/TO00/INTP2, P14/ ANI20/TI01/TO01/INTP3 as a general-p urpose port,
use the bit 0, 1 (TO00, TO01) of timer output register 0 (TO0), and bit 0, 1 (TOE00, TOE01) of
timer output enable register 0 (TOE0) with the settings “0” same as the initial status.
Remaek ×: don't care
PM1: Port mode register 1
PIM1: Port input mode register 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
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Figures 4-4 to 4-8 show block diagrams of port 1.
Figure 4-4. Block Diagram of P10 (20-, 24-pin Products)
Internal bus
POM1
RD
P1
P-ch
Selector
PU1
WR
PU
Alternate
function
P10/ANI16/
PCLBUZ0/
SCK00/SCL00
WR
PMC
WR
PIM
PIM1
PMC1
WR
PORT
WR
POM
PM1
WR
PM
A
/D converter
CMOS
TTL
V
DD
Output latch
(P10)
PMC10
PM10
POM10
Alternate
function 2
(clock/buzzer)
Alternate
function 1
(serial)
PU10
PIM10
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PIM1: Port input mod e register 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-5. Block Diagram of P11 (20-, 24-pin Products)
Internal bus
POM1
RD
P1
P-ch
Selector
PU1
WR
PU
Alternate
function
P11/ANI17/
SI00/RxD0/
SDA00/TOOLRxD
WR
PMC
WR
PIM
PIM1
PMC1
WR
PORT
WR
POM
PM1
WR
PM
A
/D converter
CMOS
TTL
V
DD
Output latch
(P11)
PMC11
PM11
POM11
PU11
PIM11
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PIM1: Port input mod e register 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-6. Block Diagram of P12 (20-, 24-pin Products)
Internal bus
POM12
POM1
RD
Output latch
(
P12
)
P1
P-ch
Selector
PU12
PU1
WR
PU
P12/ANI18/SO00/
TxD0
WR
PMC
PMC12
PMC1
WR
PORT
WR
POM
PM12
PM1
WR
PM
A
/D converter
V
DD
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
POM1: Port output mode register 1
PMC1: Port mode control register 1
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-7. Block Diagram of P13 (20-, 24-pin Products)
Internal bus
RD
Output latch
(
P13
)
P1
P-ch
Selector
PU13
PU1
WRPU
WRPMC
PMC13
PMC1
WRPORT
PM13
PM1
WRPM
A
/D converter
VDD
Alternate
function
Alternate
function
P13/ANI19/
TI00/TO00
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PMC1: Port mode control register 1
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-8. Block Diagram of P14 (20-, 24-pin Products)
Internal bus
RD
Output latch
(
P14
)
P1
P-ch
Selector
PU14
PU1
WR
PU
P14/AN20/
TI01/TO01
WR
PMC
PMC14
PMC1
WR
PORT
PM14
PM1
WR
PM
A
/D converter
V
DD
Alternate
function
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PMC1: Port mode control register 1
RD: Read signal
WR××: Write signal
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(3) Port 2
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input and reference voltage inpu ts (positive and negative).
To use P20/ANI0 to P23/ANI3 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using the PM2 register. Use these pins startin g from the upper bit.
To use P20/ANI0 to P23/ANI3 as digital output pins, set them in the digital I/O mode by using the ADPC register and
in the output mode by using the PM2 register. Use these pins starting from the upper bit.
To use P20/ANI0 to P23/ANI3 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the
lower bit.
Table 4-4. Settings of Registers Wh en Using Port 2 (20-, 24-pin Products)
Pin
name I/O PM2× ADPC Alternate
Function Buffer type Remark
input 1 CMOS input P2n
output 0
01 to
n+1H
−
CMOS output
To use P2n as a port, use
these pins from a higher bit.
Remark PM2 : Port mode register 2
ADPC : A/D port configuration register
Table 4-5. Setting Functions of P20/ANI0 to P23/ANI3 Pins
ADPC Register PM2 Register ADS Register P20/ANI0 to P23/ANI3 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
Reset signal generation sets port 2 to analog input.
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Figure 4-9 shows a block diagram of port 2.
Figure 4-9. Block Diagram of P20 to P23 (20-, 24-pin Products)
Internal bus
RD
Output latch
(
P20 to P23
)
P2
Selector
P20/ANI0/AVREFP,
P21/ANI1/AVREFM,
P22/ANI2,
P23/ANI3
WRPORT
PM20 to PM23
PM2
WRPM
A
/D converter
P2: Port register 2
PM2: Port mode regi ster 2
RD: Read signal
WR××: Write signal
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(4) Port 4
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port
mode register 4 (PM4). When the P40 to P42 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 4 (PU4).
Output from the P41 pin can be specifie d as N-ch o pen-drain o utput (VDD t olerance) usin g port output m ode register 4
(POM4).
When P41 and P42 pins are used as input, specify them as either digital or analog in port mode control register 4
(PMC4). This register can be specified in 1-bit unit.
This port can also be used for key return input, data I/O for a flash memory programmer/debugger, analog input,
serial interface data I/O, clock I/O, timer I/O, and external interrupt request input.
Reset signal generation sets port 4 to input mode (the P41 and P42 pins are analog input).
Table 4-6. Settings of Registers Wh en Using Port 4 (20-, 24-pin Products)
Pin
name I/O PM4× PIM4× POM4× PMC4× Alternate Function Buffer type
Input 1 × CMOS input P40
Output 0
− − −
× CMOS output
Input 1 × × CMOS input
0 CMOS output
P41
Output 0
−
1
0
SO01, SDA01 output = 1Note
TO02 output = 0 Note N-ch open-drain output
Input 1 × CMOS input P42
Output 0
− − 0
SCK01/SCL01 output = 1 Note
TO03 output = 0 Note
CMOS output
Note When using P41/SO01/SDA01/TI02/TO02/INTP1/ANI22, P42/SCK01/SCL01/TI03/TO03/ANI21 as a general-
purpose port, use the serial channel e nable status register 0 (SE0), serial output register 0 (SO0), use the each
bit 0 (SE00, SO00, SOE00), serial channel enable status register 0 (SOE0), use the each bit 1 (SE01, SO01,
SOE01), bits 2, 3 (TO02, TO03) of timer output register 0 (TO0), bits 2,3 (TOE02, TOE03) of timer output
enable register 0 (TOE0) with the same settings as the initial status. In addition, Set the port output mode
register 4 (POM4) to 00H.
Caution When a tool is connected, the P40 pin cannot be used as a port pin.
Remark ×: don't care
PM4 : Port mode register 4
PIM4 : Port input mod e register 4
POM4 : Port output mode register 4
PMC4 : Port mode control register 4
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Figures 4-10 to 4-12 show block diagrams of port 4.
Figure 4-10. Block Diagram of P40 (20-, 24-pin Products)
P40/KR0/TOOL0
Internal bus
PM40
PM4
RD
WR
PM
Output latch
(
P40
)
P4
WR
PORT
P-ch
Selector
PU40
PU4
WR
PU
V
DD
Selector
Alternate
function
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode regi ster 4
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Sep. 28, 2012
Figure 4-11. Block Diagram of P41 (20-, 24-pin Products)
Internal bus
POM41
POM4
RD
Output latch
(
P41
)
P4
P-ch
Selector
PU41
PU4
WR
PU
P41/ANI22/
SO01/SDA01/
TI02/TO02/INTP1
WR
PMC
PMC41
PMC4
WR
PORT
WR
POM
PM41
PM4
WR
PM
A
/D converter
V
DD
Alternate
function
Alternate
function 1
(serial)
Alternate
function 2
(Timer)
P4: Port register 4
PM4: Port mode regi ster 4
POM4: Port output mode register 4
PMC4: Port mode control register 4
PU4: Pull-up resistor option register 4
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-12. Block Diagram of P42 (20-, 24-pin Products)
Internal bus
RD
Output latch
(
P42
)
P4
P-ch
Selector
PU42
PU4
WR
PU
WR
PMC
PMC42
PMC4
WR
PORT
PM42
PM4
WR
PM
A
/D converter
V
DD
P42/ANI21/SCK01/
SCL01/TI03/TO03
Alternate
function 1
(serial)
Alternate
function 2
(Timer)
Alternate
function
P4: Port register 4
PM4: Port mode regi ster 4
PMC4: Port mode control register 4
PU4: Pull-up resistor option register 4
RD: Read signal
WR××: Write signal
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(5) Port 6
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6).
This port can also be used for key return input, serial interface data I/O, and clock I/O.
Reset signal generation sets port 6 to input mode.
Table 4-7. Settings of Registers Wh en Using Port 6 (20-, 24-pin Products)
Pin name I/O PM6× Alternate FunctionNote3 Buffer type
input 1 CMOS input P60
output 0
SCLA0 output = 0Note1
(TxD0 output = 1 Note 2) N-ch open-drain output (6 V tolerance)
input 1 CMOS input P61
output 0
SDAA0 output = 0 Note 1
N-ch open-drain output (6 V tolerance)
Notes 1. When using P60/KR4/SCLA0, P61/KR5/SDAA0 as a general-purpose port, set the serial interface IICA to
operation stop mode.
2. When using P60 as a general-purpose port and PIOR1 is set to 1, use the serial channel enable status
register 0 (SE0), serial output register 0 (SO0), serial channel enable status register 0 (SOE0), use the
each bit 0 (SE00, SO00, SOE00) with the settings “0” same as the initial status.
3. The descriptio ns in parentheses indicate the case where PIOR1 = 1.
Remark PM6 : Port mode reg ister 6
PIOR : Peripheral I/O redirection register
<R>
<R>
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-13 sho ws a block diagram of port 6 .
Figure 4-13. Block Diagram of P60 and P61 (20-, 24-pin Products)
P60/KR4/SCLA0/(TxD0),
P61/KR5/SDAA0/(RxD0)
Internal bus
PM60,PM61
PM6
RD
WR
PM
Output latch
(P60, P61)
P6
WR
PORT
Selector
Alternate
function 1
(se rial arra y
unit)
Alternate
function 2
(IICA)
Alternate
function
P6: Port register 6
PM6: Port mode regi ster 6
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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(6) Port 12
Port 12 is an input port. Use of an on-chip pull-up resistor can be specified for P125 using pull-up resistor option
register 12 (PU12) (valid after RESET input) Note.
This port can also be used for key return input, connecting resonator for main system clock, external clock input for
main system clock, and reset input.
Note Once the power is turned on, P125 functions as RESET input until the power-on-reset (POR) is released.
After the POR is released, the PORTSELB bit of the option byte (000C1H) defines whether this port is
P125/KR1/SI01 or RESET. Therefore, when the port is set as P125/KR1/SI01, to avoid continuing the external
reset status, do not input the low level to this pin until the POR is released.
T his pull-up re sistor is enabled by releasing the reset.
Table 4-8. Settings of Registers When Usin g Po rt 12 (20-, 24-pin Products)
Pin name I/O PM12× PMC12× Alternate Function Buffer type
P121 Input
− − OSCSEL bit = 0 of CMC register or EXCLK
bit = 1
CMOS input
P122 Input
− − OSCSEL bit = 0 of CMC register CMOS input
P125 Input
− − − CMOS input
Caution The function setting on P121 and P122 is available only once after the reset release. The port once
set for connection to an X1, XT1 oscillator, external clock input cannot be used as an input port
unless the reset is performed.
Remark PM12: Port mode register 12
PMC12: Port mode control register 12
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figures 4-14 and 4-15 show block diagrams of port 12.
Figure 4-14 Block Diagram of P121 and P122 (20-, 24-pin Products)
Internal bus
RD
P121/KR3/X1/
(TI03)/(INTP3)
RD
EXCLK,OSCSEL
CMC
OSCSEL
CMC
Clock generato
r
P122/KR2/X2/EXCLK/
(TI02)/(INTP2)
Alternate
function
Alternate
function
CMC: Clock operation mode control register
RD: Read signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-15 Block Diagram of P125 (20-, 24-pin Products)
RD
P-ch
PU125
PU12
WR
PU
V
DD
P125/KR1/
SI01/RESET
Internal bus
PORTSELB
Alternate
functiom
PU12: Pull-u p resistor option register 12
RD: Read signal
WR××: Write signal
(7) Port 13
Port 13 is an input port.
This port can also be used for external interrupt request input.
Table 4-9. Settings of Registers When Usin g Po rt 13 (20-, 24-pin Products)
Pin name I/O Alternate Function Buffer type
P137 Input × CMOS input
Remark ×: don't care
Figures 4-16 shows a block diagram of port 13.
Figure 4-16. Block Diagram of P137 (20-, 24-pin Products)
Internal bus
P137/INTP0
Alternate
function
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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4.2.2 30-pin products
(1) Port 0
Port 0 is an I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port
mode register 0 (PM0). When the P00 a nd P01 pins are us ed as an input port, use of an on-c hip pull-up resist or can
be specified in 1-bit units by pull-u p resistor option reg ister 0 (PU0). At this time, in case of PU00, set 0 in bit 0 of port
output mode register 0 (POM0).
Input to the P01 pins can be specified through a normal input buffer or a TTL input buffer using port input mode
register 0 (PIM0).
Input to the P00 and P01 pins can be specified as analog input or digital input in 1-bit units, using port mode control
register 0 (PMC0).
Output from the P00 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using port output
mode register 1 (POM1).
This port can also be used for timer I/O, analog input of A/D converter, and transmission/reception of programming
UART.
Reset signal generation sets port 0 to input mode.
Table 4-10. Settings of Registers When Using Port 0 (30-pin Products)
Pin name I/O PM0× PIM0× POM0× PMC0× Alternate Function Buffer type
Input 1 − × 0 × CMOS input
0 0 0 CMOS output
P00
Output
0 1 0
TxD1 output = 1Note1
N-ch open-drain output
1 0 − 0 × CMOS input Input
1 1 0 × TTL input
P01
Output 0 × 0 TO00 output = 0 Note 2 CMOS output
Notes 1. When usi ng P00/ANI17/TI00/TxD1 as a general-p urpose port, use the each bit 0 (SE00, SO00, SOE00) of
serial channel enable status register 0 (SE0), serial output register 0 (SO0), and serial output enable
register 0 (SOE0) with the same settings as the initial status. In addition, set the port output mode register
0 (POM0) to 00H.
2. W hen using P01/ANI16TO00/ RxD1 as a general-pur pose port, use the bit 0 (TO00) of timer output register
0 (TO0), and bit 0 (TOE00) of timer output enable register 0 (TOE0) with the settings “0” same as the initial
status.
Remark ×: don't care
PM0: Port mode regi ster 0
PIM0: Port input mode register 0
POM0: Port output mode register 0
PMC0: Port mode control register 0
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figures 4-17 and 4-18 show block diagr ams of port 0.
Figure 4-17. Block Diagram of P00 (30-pin Products)
Internal b us
RD
Output latch
(P00)
P0
P-ch
Selector
PU00
PU0
WR
PU
P00/ANI17/
TI00/TxD1
WR
PMC
PMC00
PMC0
WR
PORT
PM00
PM0
WR
PM
A/D converter
V
DD
POM00
POM0
WR
POM
Alternate
function
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode regi ster 0
POM0: Port mode output register 0
PMC0: Port mode control register 0
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-18. Block Diagram of P01 (30-pin Products)
Internal bus
RD
Output latch
(P01)
P0
P-ch
Selector
PU01
PU0
WRPU
WRPMC
WRPIM
PIM01
PIM0
PMC01
PMC0
WRPORT
PM01
PM0
WRPM
A/D converter
CMOS
TTL
VDD
P01/ANI16/
TO00/RxD1
Alternate
function
Alternate
function
P0: Port register 0
PU0: Pull-up resistor option register 0
PM0: Port mode regi ster 0
PIM0: Port input mod e register 0
PMC0: Port mode control register 0
RD: Read signal
WR××: Write signal
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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(2) Port 1
Port 1 is an I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port
mode register 1 (PM1). When the P10 to P17 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor o ption regist er 1 (PU1). At this time, in case of P10 to P15, and P17, set 0 in
a bit of port output mode register 1 (POM1) corresponding to the bit using an on-chip pull-up register.
Input to the P10, P11, P13 to P17 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit
units using port input mode register 1 (PIM1).
Output from the P10 to P15, P17 pins can be specified as N-ch open-drain output (VDD tolerance) in 1-bit units using
port output mode register 1 (POM1).
This port can also be used for serial interface data I/O, clock I/O, transmission/reception of programming UART, timer
I/O, clock/buzzer output, and external interrupt request input.
Reset signal generation sets port 1 to input mode.
Table 4-11. Settings of Registers When Using Port 1 (30-pin Products) (1/2)
Pin
name I/O PM1× PIM1× POM1× PMC×× Alternate Function Note 8 Buffer type
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P10
Output
0 × 1
SCK00/SCL00 output = 1Note 1
(TO07 output = 0 Note 5) N-ch open-drain output
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P11
Output
0 × 1
SDA00 output = 1 Note 1
(TO06 output = 0 Note 5) N-ch open-drain output
Input 1 − × − × CMOS input
0 0 CMOS output
P12
Output
0 1
SO00/TxD0 output = 1 Note 1
(TO05 output = 0 Note 5) N-ch open-drain output
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P13
Output
0 × 1
Tx D 2/SO 2 0 output = 1 Note 2
(S D A A 0 / TO04 output = 0 Note 6)N-ch open-drain output
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P14
Output
0 × 1
SDA20 output = 1 Note 2
(S C L A 0 / T O03 output = 0 Note 6)N-ch open-drain output
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P15
Output
0 × 1
PCLBUZ1 output = 0 Note 3
SCK20/SCL20 output = 1 Note 1
(TO02 output = 0 Note 3)
N-ch open-drain output
1 0 − − × CMOS input Input
1 1 × TTL input
P16
Output 0 ×
TO01 output = 0 Note 4 CMOS output
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Table 4-11. Settings of Registers When Using Port 1 (30-pin Products) (2/2)
Pin
name I/O PM1× PIM1× POM1× PMC×× Alternate Function Note 8 Buffer type
1 0 × − × CMOS input Input
1 1 × × TTL input
0 × 0 CMOS output
P17
Output
0 × 1
TO02 output = 0 Note 4
(TxD0 output = 1 Note 7) N-ch open-drain output
Notes 1. When using P10/SCK00/SCL00, P11/SI00/RxD0/TOOLRxD/SDA00, P12/S O 00/TxD0/TOOLTxD as a
general-purpose port, use the each bit 0 (SE00, SO00, SOE00) of serial channel enable status register 0
(SE0), serial output register 0 (SO0), serial channel enable status register 0 (SOE0) with the same setting
as the initial status.
2. When using P13/TxD2/SO20, P14/RxD2/SI20/SDA20 as a general-purpose port, use the each b it 0 (SE10,
SO10, SOE10) of serial channel enable status register 1 (SE1), serial output register 1 (S O1), serial
channel enable status register 1 (SOE1) with the same setting as the initial status.
3. When using P15/PCLBUZ1/SCK20/SCL20 as a general-purpose p ort, use the each b it 0 (SE10, SO10,
SOE10) of serial channel enable status reg ister 1 (SE1), serial output register 1 (SO1), serial channel
enable status register 1 (SOE1), and bit 7 (PCLOE1) of clock output select register 1 (CKS1) with the same
setting as the initial status.
4. When using P16/TI01/TO01/INTP5, P17/TI0 2/TO02 as a general-purpose port, use the bit 1, 2 (TO01,
TO02) of timer output register 0 (TO0), and bit 1, 2 of (TOE01, TOE02) of timer output enable register 0
(TOE0) with the settings “0” same as the initial status.
5. If P10 to P12 is used as general-purpos e port and PIOR0 is set to 1, set bits 5 to 7 (TO05 to TO07) of timer
output register 0 (TO0) and bits 5 to 7 (T OE05 to TOE07) of timer output enable register 0 (TOE0) to “0”,
which is the same as their default status setting.
6. If P13 and P14 is used as general-purpose port and PIOR2 is set to 1, stop operate the serial interfac e IICA.
If P13 and P14 are used as general-p urpose ports and PIOR0 is set to 1, use the corresponding bits in bits
3, 4 (TO03, TO04) of timer output register 0 (T O0) and bits 3, 4 (TOE03, TOE04) of timer output enable
register (TOE0) with the same setting as the initial status.
7. If P17 is used as general-purpose port and PIOR1 is set to 1, use the each bit 0 (SE00, SO00, SOE00) of
serial channel enable status register 0 (SE0), serial output register 0 (SO0) and Serial output enable
register 0 (SOE0) with the same setting as the initial status.
8. The descriptions in parenthe ses indicate the case where PIORx = 1.
Remark ×: don't care
PM1: port mode regi ster 1
PIM1: port input mode register 1
POM1: port output mode register 1
PMC1: port mode control register 1
PIOR: Peripheral I/O redirection register
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Figures 4-19 to 4-21 show block diagrams of port 1.
Figure 4-19. Block Diagram of P10, P11, P13 to P15, P17 (30-pin Products)
Internal bus
POM1n
POM1
RD
Output latch
(P1n)
P1
P-ch
Selector
PU1n
PU1
WR
PU
WR
PIM
PIM1n
PIM1
WR
PORT
WR
POM
PM1n
PM1
WR
PM
CMOS
TTL
V
DD
P10/SCK00/SCL00/
(TI07/TO07),
P11/SI00/TOOLRxD/
SDA00/(TI06/TO06),
P15/PCLBUZ1/SCK20/
SCL20/(TI02/TO02),
P17/TI02/TO02 /(TxD0)
Alternate
function 1
(serial)
P14/RxD2/SI20/SDA20/
(
SCLA0
)
/
(
TI03/TO03
)
,
P13/TxD2/SO20/
(SDAA0)/(TI04/TO04),
Alternate
function 2
(Timer, IICA, clock/
buzzer)
Alternate
function
(n = 0, 1, 3 to 5, 7)
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PIM1: Port input mod e register 1
POM1: Port output mode register 1
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Figure 4-20. Block Diagram of P12 (30-pin Products)
Internal bus
POM12
POM1
RD
Output latch
(P12)
P1
P-ch
Selector
PU12
PU1
WR
PU
P12/SO00/TxD0/
TOOL TxD/
(TI05/TO05)
WR
PORT
WR
POM
PM12
PM1
WR
PM
V
DD
Alternate
function 1
(serial)
Alternate
function 2
(timer)
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
POM1: Port output mode register 1
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Figure 4-21. Block Diagram of P16 (30-pin Products)
Internal bus
RD
Output latch
(P16)
P1
P-ch
Selector
PU16
PU1
WR
PU
WR
PIM
PIM16
PIM1
WR
PORT
PM16
PM1
WR
PM
CMOS
TTL
V
DD
P16/TI01/TO01/
INTP5/(RxD0)
Alternate
function
Alternate
function
P1: Port register 1
PU1: Pull-up resistor option register 1
PM1: Port mode regi ster 1
PIM1: Port input mod e register 1
RD: Read signal
WR××: Write signal
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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(3) Port 2
Port 2 is an I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port
mode register 2 (PM2).
This port can also be used for A/D converter analog input and reference voltage inpu ts (positive and negative).
To use P20/ANI0 to P23/ANI3 as digital input pins, set them in the digital I/O mode by using the A/D port configuration
register (ADPC) and in the input mode by using the PM2 register. Use these pins startin g from the upper bit.
To use P20/ANI0 to P23/ANI3 as digital output pins, set them in the digital I/O mode by using the ADPC register and
in the output mode by using the PM2 register. Use these pins starting from the upper bit.
To use P20/ANI0 to P23/ANI3 as analog input pins, set them in the analog input mode by using the A/D port
configuration register (ADPC) and in the input mode by using the PM2 register. Use these pins starting from the
lower bit.
Table 4-12. Settings of Registers When Using Port 2 (30-pin Products)
Pin
name I/O PM2× ADPC Alternate
Function Buffer type Remark
Input 1 CMOS input P2n
Output 0
01 to
n+1H
−
CMOS output
To use P2n as a port, use
these pins from a higher bit.
Remark PM2: Port mode register 2
ADPC: A/D port configuration register
Table 4-13. Setting Functions of P20/ANI0 to P23/ANI3 Pins
ADPC Register PM2 Register ADS Register P20/ANI0 to P23/ANI3 Pins
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
Reset signal generation sets port 2 to analog input.
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Figure 4-22 sho ws a block diagram of port 2 .
Figure 4-22. Block Diagram of P20 to P23 (30-pin Products)
WR
PM
Internal b us
RD
Output latch
(P20 to P23)
P2
Selector
P20/ANI0/AV
REFP
,
P21/ANI1/AV
REFM
,
P22/ANI2,
P23/ANI3
Alternate
PM20 to PM23
PM2
A/D converter
P2: Port register 2
PM2: Port mode regi ster 2
RD: Read signal
WR××: Write signal
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(4) Port 3
Port 3 is an I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port
mode register 3 (PM3). When this port is used as an input port, use of an on-chip pull- up resistor can be specified in
1-bit units by pull-up resistor option register 3 (PU3).
This port can also be used for external interrupt request input, serial interface data I/O, clock I/O, clock/buzzer output,
and timer I/O.
Reset signal generation sets port 3 to input mode.
Table 4-14. Settings of Registers When Using Port 3 (30-pin Products)
Pin name I/O PM3× PMC3× Alternate Function Buffer type
Input 1 × CMOS input P30
Output 0
−
SCK11/SCL11 output = 1 Note 1 CMOS output
Input 1 × CMOS input P31
Output 0
−
TO03 output = 0 Note 2
PCLBUZ0 output = 0 Note 2
CMOS output
Notes 1. When using P30/SCK11/SCL11/INTP3 as a general-purpose port, use the each bit 3 (SE03, SO03,
SOE00) of serial channel enable status register 1 (SE1), serial output register 1 (SO1), and serial
output enable register 1 (SOE1) with the same settings as the initial status.
2. When using P31/TI03/TO03/INTP4/PCLBUZ0 as a general-purpose port, use the bit 3 (TO03) of timer
output register 0 (TO0), bit 3 (TOE03) of timer output enable register 0 (TOE0), and bit 7 of clock
output select register 0 (CKS0) w ith th e same settings as the initial status.
Remark ×: don't care
PM3: Port mode register 3
PMC3: Port mode control register 3
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Figure 4-23 and 4-24 shows a block diagram of port 3.
Figure 4-23. Block Diagram of P30 (30-pin Products)
Internal bus
RD
Output latch
(P30)
P3
P-ch
Selector
PU30
PU3
WR
PU
P30/SCK11/SCL11/INTP3
WR
PORT
PM30
PM3
WR
PM
V
DD
Alternate
function
Alternate
function
P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode regi ster 3
RD: Read signal
WR××: Write signal
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Figure 4-24. Block Diagram of P31 (30-pin Products)
Internal bus
RD
Output latch
(P31)
P3
P-ch
Selector
PU31
PU3
WRPORT
PM31
PM3
WRPM
VDD
P31/TI03/TO03/
PCLBUZ0/INTP4
Alternate
function
Alternate
function
WRPU
P3: Port register 3
PU3: Pull-up resistor option register 3
PM3: Port mode regi ster 3
RD: Read signal
WR××: Write signal
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(5) Port 4
Port 4 is an I/O port with an output latch. Port 4 can be set to the input mode or output mode using port mode register
4 (PM4). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by pull-up
resistor option register 4 (PU4) Note.
Reset signal generation sets port 4 to input mode.
Table 4-15. Settings of Registers When Using Port 4 (30-pin Products)
Pin name I/O PM4× PIM4× POM4× PMC4× Alternate Function Buffer type
Input 1 × CMOS input P40
Output 0
− − −
× CMOS output
Note When a tool is connected, the P40 pin cannot be used as a port pin.
Remark ×: don't care
PM4: Port mode register 4
PIM4: Port input mode register 4
POM4: Port output mode register 4
PMC4: Port mode control register 4
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Figure 4-25 sho ws a block diagram of port 4 .
Figure 4-25. Block Diagram of P40 (30-pin Products)
Internal b us
RD
Output latch
(P40)
P4
P-ch
Selector
PU40
PU4
WRPU
P40/TOOL0
WRPORT
PM40
PM4
WRPM
VDD
Alternate
function
Alternate
function
P4: Port register 4
PU4: Pull-up resistor option register 4
PM4: Port mode regi ster 4
RD: Read signal
WR××: Write signal
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(6) Port 5
Port 5 is an I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port
mode register 5 (PM5). When the P50 to P57 pins are used as an input port, use of an on-chip pull-up resistor can be
specified in 1-bit units by pull-up resistor option register 5 (PU5). At this time, in case of PU50, set 0 in bit 0 of port
output mode register 5 (POM5).
Output from the P50 pin can be specifie d as N-ch o pen-drain o utput (VDD t olerance) usin g port output m ode register 5
(POM5).
This port can also be used for external interrupt request input, serial interface data I/O, and clock I/O.
Reset signal generation sets port 5 to input mode.
Table 4-16. Settings of Registers When Using Port 5 (30-pin Products)
Pin name I/O PM5× PIM5× POM5× Alternate Function Remark
Input 1 × × CMOS input
0 0 CMOS output
P50
Output
0
−
1
SDA11 output = 1Note
N-ch open-drain output
Input 1 × CMOS input P51
Output 0
− −
SO11 output = 1Note CMOS output
Note When using P50/INTP1/SI11/SDA11, P51/INTP2/SO11 as a general-purpose port, use the serial channel
enable status register 0 (SE0) , serial output r egister 0 (SO 0), and seri al out put en abl e regi ster 0 (SOE0) with the
same settings as the initial status.
Remark ×: don't care
PM5: Port mode register 5
PIM5: Port input mode register 5
POM5: Port output mode register 5
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Figures 4-26 and 4-27 show block diagr ams of port 5.
Figure 4-26. Block Diagram of P50 (30-pin Products)
Internal bus
POM50
POM5
RD
Output latch
(P50)
P5
P-ch
Selector
PU50
PU5
WR
PU
P50/SI11/SDA11/
INTP1
WR
PORT
WR
POM
PM50
PM5
WR
PM
V
DD
Alternate
function
Alternate
function
P5: Port register 5
PU5: Pull-up resistor option register 5
PM5: Port mode regi ster 5
POM5: Port output mode register 5
RD: Read signal
WR××: Write signal
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Figure 4-27. Block Diagram of P51 (30-pin Products)
Internal bus
RD
Output latch
(P51)
P5
P-ch
Selector
PU51
PU5
WR
PU
P51/SO11/INTP2
WR
PORT
PM51
PM5
WR
PM
V
DD
Alternate
function
Alternate
function
P5: Port register 5
PU5: Pull-up resistor option register 5
PM5: Port mode regi ster 5
RD: Read signal
WR××: Write signal
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(7) Port 6
Port 6 is an I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port
mode register 6 (PM6).
N-ch open-drain output (6 V tolerance).
This port can also be used for serial interface data I/O and clock I/O.
Reset signal generation sets port 6 to input mode.
Table 4-17. Settings of Registers When Using Port 6 (30-pin Products)
Pin name I/O PM6× Alternate Function Remark
Input 1 CMOS input P60
Output 0
SCLA0 output = 0Note
N-ch open-drain output (6 V tolerance)
Input 1 CMOS input P61
Output 0
SDAA0 output = 0 Note
N-ch open-drain output (6 V tolerance)
Note When using P60/SCLA0, P61/SDAA0 as a general-purpose port, set the serial interface IICA to operation stop
mode.
Remark PM6: Port mode register 6
Figure 4-28 sho ws a block diagram of port 6 .
Figure 4-28. Block Diagram of P60 and P61 (30-pin Products)
P60/SCLA0,
P61/SDAA0
Internal bus
PM60, PM61
PM6
RD
WR
PM
P6
WR
PORT
Selector
Output latch
(P60, P61)
Alternate
function
Alternate
function
P6: Port register 6
PM6: Port mode regi ster 6
RD: Read signal
WR××: Write signal
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(8) Port 12
P120 is a 1-bit I/O port with an output latch. Port 12 can be set to the input mode or output mode using port mode
register 12 (PM12). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 12 (PU12).
P121 to P122 is a 2-bit input port.
When the P120 pin is used as input, specify them as either digital or analog in Port mode control register 12 (PMC12).
This port can also be used for A/D converter analog input, conn ecting resonator for main system clock, external clock
input for main system clock, and external clock input for sub-system clock.
Reset signal generation sets P120 analog input. P121, P122 to input mode.
Table 4-18. Settings of Registers When Using Port 12 (30-pin Products)
Pin name I/O PM12× PMC12× Alternate Function Buffer type
Input 1 0 × CMOS input P120
Output 0 0 × CMOS output
P121 Input − − OSCSEL bit of CMC register = 0 or EXCLK
bit = 1 CMOS input
P122 Input − − OSCSEL bit of CMC register = 0 CMOS input
Note The function setting on P121 or P122 is available only once after the reset release. The port once set for
connection to an X1 oscillator/exter nal clock input cannot be used as an input port unless the reset is performed.
Remark ×: don't care
PM12: Port mode register 12
PM12: Port mode control register 12
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Figures 4-29 and 4-30 show block diagrams of port 12.
Figure 4-29. Block Diagram of P120 (30-pin Products)
Internal bus
RD
Output latch
(P120)
P12
P-ch
Selector
PU120
PU12
WR
PU
P120/ANI19
WR
PMC
PMC120
PMC12
WR
PORT
PM120
PM12
WR
PM
A
/D converter
V
DD
P12: Port register 12
PU12: Pull-u p resistor option register 12
PM12: Port mode register 12
PMC12: Port mode control register 12
RD: Read signal
WR××: Write signal
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Figure 4-30. Block Diagram of P121 and P122 (30-pin Products)
Internal bus
RD
P121/X1
RD
EXCLK, OSCSEL
CMC
OSCSEL
CMC
Clock generator
P122/X2/EXCLK
CMC: Clock operation mode control register
RD: Read signal
(9) Port 13
Port 13 is dedicated 1-bit input port.
This port can also be used for external interrupt request input.
Table 4-19. Settings of Registers When Using Port 13 (30-pin Products)
Pin name I/O Alternate Function Buffer type
P137 Input × CMOS input
Remark ×: don't care
Figure 4-31 sho ws a block diagram of port 1 3.
Figure 4-31. Block Diagram of P137 (30-pin Products)
Internal bus
P137/INTP0
Alternate
function
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(10) Port 14
Port 14 is an I/O port with an output latch. Port 14 can be set to the input mode or output mode using port mode
register 14 (PM14). When this port is used as an input port, use of an on-chip pull-up resistor can be specified by
pull-up resistor option register 14 (PU14).
When the P147 pin is used as input, specify them as either digital or analog in Port mode control register 14 (PMC14).
This port can also be used for A/D converter anal og input.
Reset signal generation sets port to analog input.
Table 4-20. Settings of Registers When Using Port 14 (30-pin Products)
Pin name I/O PM14× PIM14× POM14× PMC14× Alternate Function Buffer type
Input 1 0 × CMOS input P147
Output 0
− −
0 × CMOS output
Remark ×: don't care
PM14: Port mode register 14
PIM14: Port input mode register 14
POM14: Port output mode register 14
PMC14: Port mode control register 1 4
RL78/G12 CHAPTER 4 PORT FUNCTIONS
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Figure 4-32 sho ws a block diagram of port 1 4.
Figure 4-32. Block Diagram of P147 (30-pin Products)
WR
PM
Internal bus
RD
Output latch
(P147)
P14
P-ch
Selector
PU147
PU14
WR
PU
P147/ANI18
WR
PMC
PMC147
PMC1
WR
PORT
PM147
PM14
A
/D converter
V
DD
P14: Port register 14
PU14: Pull-u p resistor option register 14
PM14: Port mode register 14
PMC14: Port mode control register 14
RD: Read signal
WR××: Write signal
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4.3 Registers Controlling Port Function
Port functions are controlled by the following registers.
• Port mode registers (PMxx)
• Port registers (Pxx)
• Pull-up resistor option registers (PUxx)
• Port input mode registers (PIMxx)
• Port output mode registers (POMxx)
• Port mode control registers (PMCxx)
• A/D port configuration register (ADPC)
• Peripheral I/O redirection register (PIOR)
Caution The undefined bits in each register vary by product and must be used with their initial value.
Table 4-21. PMxx, Pxx, PUxx, PIMxx, POMxx, PMCxx Registers and the Bits (20-, 24-pin Products)
Bit name
Port PMxx register Pxx register PUxx register PIMxx register POMxx register PMCxx register
Port 0 Note 0 PM00 P00 PU00 − − −
1 PM01 P01 PU01 − POM01 −
2 PM02 P02 PU02 − − −
3 PM03 P03 PU03 − − −
Port 1 0 PM10 P10 PU10 PIM10 POM10 PMC10
1 PM11 P11 PU11 PIM11 POM11 PMC11
2 PM12 P12 PU12 − POM12 PMC12
3 PM13 P13 PU13 − − PMC13
4 PM14 P14 PU14 − − PMC14
Port 2 0 PM20 P20 − − − −
1 PM21 P21 − − − −
2 PM22 P22 − − − −
3 PM23 P23 − − − −
Port 4 0 PM40 P40 PU40 − − −
1 PM41 P41 PU41 − POM41 PMC41
2 PM42 P42 PU42 − − PMC42
Port 6 0 PM60 P60 − − − −
1 PM61 P61 − − − −
Port 12 1 − P121 − − − −
2
− P122 − − − −
5
− P125 PU125 − − −
Port 13 7 − P137 − − − −
Note Provided in 24-pin products only.
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Table 4-22. PMxx, Pxx, PUxx, PIMx, POMx, PMCxx Registers and the Bits (30-pin Products)
Bit name
Port PMxx register Pxx register PUxx register PIMx register POMx register PMCxx register
Port 0 0 PM00 P00 PU00 − POM00 PMC00
1 PM01 P01 PU01 PIM01 − PMC01
Port 1 0 PM10 P10 PU10 PIM10 POM10 −
1 PM11 P11 PU11 PIM11 POM11
−
2 PM12 P12 PU12 − POM12 −
3 PM13 P13 PU13 PIM13 POM13
−
4 PM14 P14 PU14 PIM14 POM14
−
5 PM15 P15 PU15 PIM15 POM15
−
6 PM16 P16 PU16 PIM16 − −
7 PM17 P17 PU17 PIM17 POM17
−
Port 2 0 PM20 P20 − − − −
1 PM21 P21 − − − −
2 PM22 P22 − − − −
3 PM23 P23 − − − −
Port 3 0 PM30 P30 PU30 − − −
1 PM31 P31 PU31 − − −
Port 4 0 PM40 P40 PU40 − − −
Port 5 0 PM50 P50 PU50 − POM50 −
1 PM51 P51 PU51 − − −
Port 6 0 PM60 P60 − − − −
1 PM61 P61 − − − −
Port 12 0 PM120 P120 PU120 − − PMC120
1
− P121 − − − −
2
− P122 − − − −
Port 13 7 − P137 − − − −
Port 14 7 PM147 P147 PU147 − − PMC147
The format of each register is described below.
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(1) Port mode registers (PMxx)
These registers specif y input or output mode for the port in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these reg isters to FFH.
When port pins are used as alternate-function pins, set the port mode register by referencing 4.5 Settings of Port
Mode Register, and Output Latch When Using Alternate Function.
Figure 4-33. Format of Port Mode Register
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 Note 1 1 1 1 PM03 PM02 PM01 PM00 FFF20H FFH R/W
PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W
PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W
Note Provided in 24-pin products only.
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W
PM4 1 1 1 1 1 1 1 PM40 FFF24H FFH R/W
PM5 1 1 1 1 1 1 PM51 PM50 FFF25H FFH R/W
PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W
PM12 1 1 1 1 1 1 1 PM120 FFF2CH FFH R/W
PM14 PM147 1 1 1 1 1 1 1 FFF2EH FFH R/W
PMmn Pmn pin I/O mode selection (m = 0 to 6, 12, 14; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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(2) Port registers (Pxx)
These registers set the output latch value of a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
readNote.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the P4 register to 01H and clears the other registers to 00H.
Note In the ports that are set up as analog inputs of the A/D converter, when a port is read while in the input mode, 0
is always returned, not the pin level.
In addition, in the output latch that are set up as RESET pin for P125, 1 is always read.
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Figure 4-34. Format of Po rt Regi ster
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
P0 0 0 0 0 P03 P02 P01 P00 FFF00H 00H (output latch) R/W
P1 0 0 0 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W
P2 0 0 0 0 P23 P22 P21 P20 FFF02H 00H (output latch) R/W
P4 0 0 0 0 0 P42 P41 P40 FFF04H 00H (output latch) R/W
P6 0 0 0 0 0 0 P61 P60 FFF06H 00H (output latch) R/W
P12 0 0 P125 0 0 P122 P121 0 FFF0CH Undefined R
P13 P137 0 0 0 0 0 0 0 FFF0DH Undefined R
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
P0 0 0 0 0 0 0 P01 P00 FFF00H 00H (output latch) R/W
P1 P17 P16 P15 P14 P13 P12 P11 P10 FFF01H 00H (output latch) R/W
P2 0 0 0 0 P23 P22 P21 P20 FFF02H 00H (output latch) R/W
P3 0 0 0 0 0 0 P31 P30 FFF03H 00H (output latch) R/W
P4 0 0 0 0 0 0 0 P40 FFF04H 00H (output latch) R/W
P5 0 0 0 0 0 0 P51 P50 FFF05H 00H (output latch) R/W
P6 0 0 0 0 0 0 P61 P60 FFF06H 00H (output latch) R/W
P12 0 0 0 0 0 P122 P121 P120 FFF0CH Undefined R/WNote
P13 P137 0 0 0 0 0 0 0 FFF0DH Undefined R
P14 P147 0 0 0 0 0 0 0 FFF0EH 00H (output latch) R/W
Pmn Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
m = 0 to 6, 12, 13, 14; n = 0 to 7
Note P121 and P12 2 are read-only.
<R>
<R>
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(3) Pull-up resistor option registers (PUxx)
These registers specif y whether the on-chip pull-up res istors are to be used or not. On-chip pull-up resistors can be
used in 1-bit units only for the bits set satisfied follo wing three conditio ns which the use of an on-chip pull-up resistor
has been specified in these registers.
• PMmn = 1(Input mode)
• PMCmn, sets the digital input of ADPC register
• POMmn = 0: (POM10 to POM12 of 20-, 24-pin products and 30-pin products: Sa me sta te as the rese t de faul t valu e)
Caution When a port with the PIMn register is input from different potential device to TTL buffer, pull up to
the power supply of th e differen t po tential d e vice via a extern al pu ll-up resistor by settin g PUmn = 0.
On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output
pins, regardless of the settings of these registers.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PU4 to 01H, PU12 to 20H (20-, 24-pin products), and others to 00H.
Figure 4-35. Format of Pull-up Resistor Option Register
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PU0 0 0 0 0 PU03 PU02 PU01 PU00 F0030H 00H R/W
PU1 0 0 0 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W
PU4 0 0 0 0 0 PU42 PU41 PU40 F0034H 01H R/W
PU12 0 0 PU125 0 0 0 0 0 F003CH 20H R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PU0 0 0 0 0 0 0 PU01 PU00 F0030H 00H R/W
PU1 PU17 PU16 PU15 PU14 PU13 PU12 PU11 PU10 F0031H 00H R/W
PU3 0 0 0 0 0 0 PU31 PU30 F0033H 00H R/W
PU4 0 0 0 0 0 0 0 PU40 F0034H 01H R/W
PU5 0 0 0 0 0 0 PU51 PU50 F0035H 00H R/W
PU12 0 0 0 0 0 0 0 PU120 F003CH 00H R/W
PU14 PU147 0 0 0 0 0 0 0 F003EH 00H R/W
PUmn Pmn pin on-chip pull-up resistor selection (m = 0, 1, 3 to 5, 12, 14; n = 0 to 7)
0 On-chip pull-up resistor not connected (When PORTSELB = 0, P125 of 20-, 24-pin products) .
1 On-chip pull-up resistor connected
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(4) Port input mode register (PIMx)
These registers set CMOS input or TTL input in 1-bit units.
TTL input buffer can be selected during serial communication with an external device of a different potent ial.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 4-36. Format of Port Input Mode Register
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIM1 0 0 0 0 0 0 PIM11 PIM10 F0041H 00H R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIM0 0 0 0 0 0 0 PIM11 0 F0040H 00H R/W
PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 F0041H 00H R/W
PIMmn Pmn pin input buffer selection (m = 0, 1; n = 0, 1, 3 to 7)
0 Normal input buffer
1 TTL input buffer
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(5) Port output mode registers (POMx)
These registers set CMOS output or N-ch open drain output in 1-bit units.
N-ch open drain output (VDD tolera nce) mode can be selected for the SDAxx p in during serial communication with an
external device of a different potential or during simplified I2C communication with an external device of the same
potential.
When port 1 of 20-, 24-pin products or port 0, 1, 5 of 30-pin products is in input mode, POMx and PUx specifies
whether to connect an on-chip pull-up resistor to port 1 along with PU1.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-37. Format of Port Output Mode Register
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 0 0 0 POM01 0 F0050H 00H R/W
POM1 0 0 0 0 0 POM12 POM11 POM10 F0051H 00H R/W
POM4 0 0 0 0 0 0 POM41 0 F0054H 00H R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 0 0 0 0 POM01 F0050H 00H R/W
POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W
POM5 0 0 0 0 0 0 0 POM50 F0055H 00H R/W
POMmn Pmn pin output mode selection (m = 0, 1, 4, 5; n = 0 to 7)
0 Normal output mode
When input mode, enable to the PUmn bit (POM1 of 20-, 24-pin products, and POM0, POM1, POM5 of 30-
pin products).
1 N-ch open-drain output (VDD tolerance) mode
When input mode, disable to the PUmn bit (POM1 of 20-, 24-pin products, and POM0, POM1, POM5 of
30-pin products).
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(6) Port mode control registers (PMCxx)
These registers set the digital I/O or analo g i nput in 1-bit units.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these reg isters to FFH.
Figure 4-38. Format of Port Mode Control Register
20-, 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PMC1 1 1 1 PMC14 PMC13 PMC12 PMC11 PMC10 F0061H FFH R/W
PMC4 1 1 1 1 1 PMC42 PMC41 1 F0064H FFH R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PMC0 1 1 1 1 1 1 PMC01 PMC00 F0060H FFH R/W
PMC12 1 1 1 1 1 1 1 PMC120 F006CH FFH R/W
PMC14 PMC147 1 1 1 1 1 1 1 F006EH FFH R/W
PMCmn Pmn pin digital I/O/analog input selection (m = 1, 4, 12, 14; n = 0 to 4, 7)
0 Digital I/O (alternate function other than analog input)
1 Analog input
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register m
(PMm).
2. Do not set the pin set by the PMC register as digital I/O by the analog input channel
specification register (ADS).
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(7) A/D port configuration register (ADPC)
This register switches the P20/ANI0 to P23/ANI3 pins to digital I/O of port or analog input of A/D converter.
This register can be set by an 8-bit memory manipulation i nstruction.
Reset signal generation clears this register to 00H.
Figure 4-39. Format of A/D Port Configuration Register (ADPC)
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPC0 F0076H 00H R/W
Analog input (A)/digital I/O (D) switching ADPC2 ADPC1 ADPC0
ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20
0 0 0 A A A A
0 0 1 D D D D
0 1 0 D D D A
0 1 1 D D A A
1 0 0 D A A A
Other than the above Setting prohibited
Cautions 1. Set the channel used for A/D conversion to the input mode by using port mode register 2.
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
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(8) Peripheral I/O redirection register (PIOR)
This register is used to specify whether to enable or disable the peripheral I/O redirect function.
This function is used to switch ports to which alternate functions are assigned.
Use the PIOR register to assign a port to the function to redirect and enable the function.
In addition, can be changed the settings for redirection u ntil its function enable operation.
The PIOR register can be set by an 8-bit memor y manipula tion instruction.
Reset signal generation clears this register to 00H.
Figure 4-40. Format of Peripheral I/O Redirection Register (PIOR)
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIOR 0 0 0 0 PIOR3 PIOR2 PIOR1 PIOR0 F0077H 00H R/W
20-, 24-pin products Setting value
Bit Function 0 1
SCK01 P42 P02 Note 2
SI01 P125 P00 Note 2
SO01 P41 P01 Note 2
SCL01 P42 P02 Note 2
PIOR3 Note 1
SDA01 P41 P01 Note 2
TI02 P41 P122 PIOR2 TI03 P42 P121
RxD0 P11 P61 PIOR1 TxD0 P12 P60
INTP2 P13 P122 PIOR0 INTP3 P14 P121
30-pin products Setting value
Bit Function 0 1
PIOR3 − (fixed) −
SCLA0 P60 P14 PIOR2 SDAA0 P61 P13
TxD2 Note 1 P13 −
RxD2 Note 1 P14 −
SCL20 Note 1 P15 −
SDA20 Note 1 P14 −
SI20 Note 1 P14 −
SO20 Note 1 P13 −
SCK20 Note 1 P15 −
TxD0 P12 P17
RxD0 P11 P16
SCL00 P10 −
SDA00 P11 −
SI00 P11 −
SO00 P12 −
PIOR1
SCK00 P10 −
TI02/TO02 P17 P15
TI03/TO03 P31 P14
TI04/TO04 Note 1 − P13
TI05/TO05 Note 1 − P12
TI06/TO06 Note 1 − P11
PIOR0
TI07/TO07 Note 1 − P10
Notes 1. R5F102 products.
2. Provided only in 24-pin products.
<R>
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4.4 Port Function Operations
Port operations differ depending on whether the input or output mode is set, as shown below.
4.4.1 Writing to I/O port
(1) Output mode
A value is written to the output latch by a transfer instruction, and the o utp ut latch contents are output from the pin.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
A value is written to the output latch by a transfer instruction, but since the output buffer is off, the pin status does not
change. Therefore, byte data can be written to the ports used for both input and output.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
4.4.2 Reading from I/O port
(1) Output mode
The output latch contents are read by a transfer instruction. The output latch contents do not change.
(2) Input mode
The pin status is read by a transfer instruction. The output latch contents do not chan ge.
4.4.3 Operations on I/O port
(1) Output mode
An operation is performed on the output latch contents, and the result is written to the output latch. The output latch
contents are output from the pins.
Once data is written to the output latch, it is retained until data is written to the output latch again.
The data of the output latch is cleared when a reset signal is generated.
(2) Input mode
The pin level is read a nd an operati on is performed o n its contents. The result of the o peration is written to the output
latch, but since the output buffer is off, the pin status does not change. Therefore, byte data can be written to the
ports used for both input and output.
The data of the output latch is cleared when a reset signal is generated.
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4.4.4 Connecting to extern al d evice with different potential (1.8 V, 2.5 V, 3 V)
When parts of ports 0 and 1 I/O connections with an external device by serial interface or general-purpose port that
operates on 1.8 V, 2.5 V, 3 V power supply voltage are possible (20-, 24-pin products is port 1 only).
External device RL78/G12
3 V 4.0 V ≤ VDD ≤ 5.5 V
2.5 V 3.3 V ≤ VDD ≤ 4.0 V
1.8 V 1.8 V ≤ VDD ≤ 3.3 V
Regarding inputs, normal (CMOS)/TTL input buffer switching is possible on a bit-by-bit basis by the port input mode
registers (PIM0, PIM1) (PIM0 is 30-pin products only).
Moreover, regarding outputs, different potentials can be sup ported by switching the output buffer to the N-ch open drain
(VDD withstand voltage) by the port output mode registers (POM0, POM1).
Following, describes the conn ection of a serial interface.
(1) Setting procedure when using I/O pins of UART0 to UART2, CSI00 and CSI20 functions
(a) Use as 1.8 V, 2.5 V, 3 V input port
<1> If pull-up is needed, exte rnally pull up the pin to be used to the power supply of the target device (o n-chip
pull-up resistor cannot be used).
Interface Pin name 20, 24-pin product 30-pin productNote
UART0 RxD0 P11 P11 (P16)
UART1 RxD1 − P01
UART2 RxD2 − P14
SCK00 P10 P10 CSI00
SI00 P11 P11
SCK20 P14 CSI20
SI20
−
P15
Note The descriptions in parentheses indicate the case where PIOR1 = 1.
<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the corresponding bit of the PIM0 and PIM1 registers to 1 to switch to the TTL input buffer.
<4> VIH/VIL operates on 1.8 V, 2.5 V, 3 V operating voltage .
(b) Use as 1.8 V, 2.5 V, 3 V output port
<1> Pull up externally the pin to be used to the power supply of the target device (on-chip pull-up resistor
cannot be used).
Interface Pin name 20, 24-pin product 30-pin productNote
UART0 TxD0 P12 P12 (P17)
UART1 TxD1 − P00
UART2 TxD2 − P13
SCK00 P10 P10 CSI00
SO00 P12 P12
SCK20 P15 CSI20
SO20
−
P13
Note The descriptions in parentheses indicate the case where PIOR1 = 1.
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<2> After reset release, the port mode changes to the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM0 and POM1 registers to 1 to set the N-ch open drain output (VDD
withstand voltage) mode.
<5> Set the output mode by manipulating the PM0 and PM1 registers.
At this time, the output data is high level, so the pin is in the Hi-Z state.
<6> Can be communication by setting the serial array unit.
(2) Setting procedure when using I/O pins of IIC00 and IIC20 functions
<1> Externally pull up the pin to be used (on-chip pull-up resistor cannot be used).
In case of IIC00: P10, P11 (SCL00, SDA00)
In case of IIC20: P14, P15 (SDA20, SCL20) (30-pin products only)
<2> After reset release, the port mode is the input mode (Hi-Z).
<3> Set the output latch of the corresponding port to 1.
<4> Set the corresponding bit of the POM1 register to 1 to set the N-ch open drain output (VDD withstand
voltage) mode.
<5> Set the corresponding bit of the PIM1 registers to 1 to switch the TTL input buffer.
<6> Set the corresponding bit of the PM1 register to the output mode (data I/O is possible in the output mode).
At this time, the output data is high level, so the pin is in the Hi-Z state.
<7> Enable the operation of t he serial array unit and set the mode to the simplified I2C mode.
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4.5 Settings of Port Related Register When Using Alternate Function
To use the alternate function of a port pin, set the port associated register and output latch as sho wn in Tab le 4-23 and
4-26.
Caution If the output function of an alternate function is assigned to a pin that is also used as an output pin,
the output of the unused alternate function must be set to its initial state. See 4.6.2 for details ab out
the applicable units and how to handle such pins.
Table 4-23. Settings of Port Related Re gister When Us ing Alternate Function (20-, 24-pin products) (1/3)
Alternate Function Pin Name
Function Name I/O
PIOR× POM× PMC×× PM×× P××
KR6 Note 1 Input 0
− − 1 ×
P00Note1
(SI01)Note 1 Input 1
− − 1 ×
KR7 Note 1 Input 0
− − 1 ×
(SO01)Note 1 Output 1 0/1
− 0 1
P01 Note 1
(SDA01)Note 1 I/O 1 1
− 0 1
KR8 Note 1 Input 0
− − 1 ×
Input 1
− − 1 ×
(SCK01)Note 1
Output 1
− − 0 1
P02 Note 1
(SCL01)Note 1 Output 1
− − 0 1
P03 Note 1 KR9 Note 1 Input − − − 1 ×
ANI16 Note 2 Input − × 1 1 ×
PCLBZ0 Note 2 Output − × 0 0 0
Input − × 0 1 ×
SCK00 Note 2
Output − 0/1 0 0 1
P10 Note 2
SCL00 Note 2 Output − 0/1 0 0 1
ANI17 Note 2 Input − × 1 1 ×
SI00 Note 2 Input − × 0 1 ×
RxD0 Note 2 Input − × 0 1 ×
SDA00 Note 2 I/O − 1 0 0 1
P11 Note 2
TOOLRxD Note 2 Input − × 0 1 ×
ANI18 Note 2 Input − × 1 1 ×
SO00 Note 2 Output − 0/1 0 0 1
TxD0 Note 2 Output − 0/1 0 0 1
P12 Note 2
TOOLTxD Note 2 Output − 0/1 0 0 1
Remarks 1. ×: don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PM××: Port mode register
P××: Port output latch
PMC××: Port mode control register
2. Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Table 4-23. Settings of Port Related Re gister When Us ing Alternate Function (20-, 24-pin products) (2/3)
Alternate Function Pin Name
Function Name I/O
PIOR× POM× PMC×× PM×× P××
ANI19 Note 2 Input − − 1 1 ×
TI00 Note 2 Input − − 0 1 ×
TO00 Note 2 Output − − 0 0 0
P13 Note 2
INTP2 Note 2 Input − − 0 1 ×
ANI20 Note 2 Input − − 1 1 ×
TI01 Note 2 Input − − 0 1 ×
TO01 Note 2 Output − − 0 0 0
P14 Note 2
INTP3 Note 2 Input − − 0 1 ×
ANI0 Note 3 Input − − − 1 ×
P20 Note 3
AVREFP Note 3 Input − − − 1 ×
ANI1 Note 3 Input − − − 1 ×
P21 Note 3
AVREFM Note 3 Input − − − 1 ×
P22, P23 Note
3 ANI2, AN3 Note 3 Input − − − 1 ×
KR0 Input
− − − 1 ×
P40
TOOL0 I/O
− − − × ×
ANI22 Note 2 Input − × 1 1 ×
SO01 Note 2 Output − 0/1 0 0 1
SDA01 Note 2 I/O − 1 0 0 1
TI02 Note 2 Input − × 0 1 ×
TO02 Note 2 Output − 0 0 0 0
P41 Note 2
INTP1 Note 2 Input − × 0 1 ×
ANI21 Note 2 Input − − 1 1 ×
Input − − 0 1 ×
SCK01 Note 2
Output − − 0 0 1
SCL01 Note 2 Output − − 0 0 1
TI03 Note 2 Input − − 0 1 ×
P42 Note 2
TO03 Note 2 Output − − 0 0 0
KR4 Input 0
− − 1 ×
SCLA0 I/O 0
− − 0 0
P60
(TxD0) Output 1
− − 0 1
Remarks 1. ×: don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PM××: Port mode register
P××: Port output latch
PMC××: Port mode control register
2. Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Table 4-23. Settings of Port Related Re gister When Us ing Alternate Function (20-, 24-pin products) (3/3)
Alternate Function Pin Name
Function Name I/O
PIOR× POM× PMC×× PM×× P××
KR5 Input 0
− − 1 ×
SDAA0 I/O 0
− − 0 0
P61
(RxD0) Input 1
− − 1 ×
KR3 Input 0
− − 1 ×
(TI03) Input 1
− − 1 ×
P121
(INTP3) Input 1
− − 1 ×
KR2 Input 0
− − 1 ×
(TI02) Input 1
− − 1 ×
P122
(INTP2) Input 1
− − 1 ×
KR1 Input
− − − 1 ×
P125 Note 4
SI01 Input
− − − 1 ×
P137 INTP0 Input − − − 1 ×
Remarks 1. ×: don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PM××: Port mode register
P××: Port output latch
PMC××: Port mode control register
2. Functions in parentheses in the ab ove table can be assigned via settings in the peripheral I/O redirection
register (PIOR).
Notes 1. 24-pin products only
2. T he functions of the ANI16/P 10 to ANI20/P14, ANI21/P42, and ANI22/P41 pins can be selected by usin g the
port mode control registers 1, 4 (PMC1, PMC4), analog input channel specification register (ADS), and port
mode registers 1, 4 (PM1, PM4).
Table 4-24. Setting the Functions of ANI16/P10 to ANI20/P14, A N I21/P42, and ANI22/P41 Pins (20-, 24-pin Products)
PMC1, PMC4
Registers PM1, PM4 Registers ADS Register ANI16/P10 to ANI20/P14, ANI21/P42, and
ANI22/P41 Pins
Input mode × Digital input Digital I/O selection
Output mode × Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input
selection
Output mode
Does not select ANI.
Setting prohibited
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Notes 3. The functions of the ANI0/P20 to ANI3/P23 pins can be selected by using the A/D port configuration register
(ADPC), analog input channel specificati on register (ADS), and port mode register 2.
Table 4-25. Setting the functions of ANI0/P20 to ANI3/P23 Pins (20-, 24-pin products)
ADPC Register PM2 Register ADS Register ANI0/P20 to ANI3/P23 Pins
Input mode × Digital input Digital I/O selection
Output mode × Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input
selection
Output mode
Does not select ANI.
Setting prohibited
4. Setting to PORTSELB = 0 by user option byte (0001CH)
Remark ×: don’t care
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Table 4-26. Settings of Port Related Re gister When Using A lternate Function (30-pin products) (1/2)
Alternate Function Pin name
Neme I/O
PIOR× POM× PMC×× PM×× P××
ANI17 Note 1 Input − × 1 1 ×
TI00 Note 1 Input − × 0 1 ×
P00 Note 1
TxD1 Note 1 Output − 0/1 0 0 1
ANI16 Note 1 Input − − 1 1 ×
TO00 Note 1 Output − − 0 0 0
P01 Note 1
RxD1 Note 1 Input − − 0 1 ×
Input 0
× − 1 ×
SCK00
Output 0 0/1
− 0 1
SCL00 Output 0 0/1
− 0 1
(TI07) Input 1
× − 1 ×
P10
(TO07) Output 1 0
− 0 0
SI00 Input 0
× − 1 ×
RxD0 Input 0
× − 1 ×
TOOLRxD Input 0
× − 1 ×
SDA00 Output 0 1
− 0 1
(TI06) Input 1
× − 1 ×
P11
(TO06) Output 1 0
− 0 0
SO00 Output 0 0/1
− 0 1
TxD0 Output 0 0/1
− 0 1
TOOLTxD Output 0 0/1
− 0 1
(TI05) Input 1
× − 1 ×
P12
(TO05) Output 1 0
− 0 0
TxD2 Output 0 0/1
− 0 1
SO20 Output 0 0/1
− 0 1
(SDAA0) I/O 1 1
− 0 0
(TI04) Input 1
× − 1 ×
P13
(TO04) Output 1 0
− 0 0
RxD2 Input 0
× − 1 ×
SI20 Input 0
× − 1 ×
SDA20 I/O 0 1
− 0 1
(SCLA0) Output 1 1
− 0 0
(TI03) Input 1
× − 1 ×
P14
(TO03) Output 1 0
− 0 0
Remarks 1. ×: don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PM××: Port mode register
P××: Port output latch
PMC××: Port mode cont rol register
2. Functions in parentheses in the above table can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Table 4-26. Settings of Port Related Re gister When Using A lternate Function (30-pin products) (2/2)
Alternate Function Pin name
Name I/O
PIOR× POM× PMC×× PM×× P××
PCLBUZ1 Output 0 0
− 0 0
Input 0 × − 1 ×
SCK20
Output 0 0/1 − 0 1
SCL20 Output 0 0/1
− 0 1
(TI02) Input 1
× − 1 ×
P15
(TO02) Output 1 0
− 0 0
TI01 Input 0
− − 1 ×
TO01 Output 0
− − 0 0
INTP5 Input 0
− − 1 ×
P16
(RxD0) Input 1
− − 1 ×
TI02 Input 0 ×
− 1 ×
TO02 Output 0 0
− 0 0
P17
(TxD0) Output 1 0/1
− 0 1
ANI0 Note 2 Input − − − 1 ×
P20Note2
AVREFP Note 2 Input − − − 1 ×
ANI1 Note 2 Input − − − 1 ×
P21 Note 2
AVREFM Note 2 Input − − − 1 ×
P22, P23 Note 2 ANI2, ANI3 Note 2 Input − − − 1 ×
INTP3 Input
− − − 1 ×
Input − − − 1 ×
SCK11
Output − − − 0 1
P30
SCL11 Output
− − − 0 1
TI03 Input
− − − 1 ×
TO03 Output
− − − 0 0
INTP4 Input
− − − 1 ×
P31
PCLBUZ0 Output
− − − 0 0
P40 TOOL0 I/O
− − − × ×
SI11 Input
− × − 1 ×
SDA11 I/O
− 1 − 0 1
P50
INTP1 Input
− × − 1 ×
SO11 Output
− − − 0 1 P51
INTP2 Input
− − − 1 ×
P60 SCLA0 I/O
− − − 0 0
P61 SDAA0 I/O
− − − 0 0
P120 Note 1 ANI19 Note 1 Input − − 1 1 ×
P137 INTP0 Input
− − − 1 ×
P147 Note 1 ANI18 Note 1 Input − − 1 1 ×
Remarks 1. ×: don’t care
PIOR×: Peripheral I/O redirection register
POM××: Port output mode register
PM××: Port mode register
P××: Port output latch
PMC××: Port mode control register
2. Functions in parentheses in th e abov e table c an be a ssigne d via settings in the periph eral I /O redirection
register (PIOR).
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Notes 1. The functions of the ANI16/P01, ANI17/P00, ANI18/P147, and ANI19/P120 pins can be selected by using
the port mode control registers 0, 12, 14 (PMC0, PMC12, PMC14), analog input channel specification
register (ADS), and port mode registers 0, 12, 14 (PM0, PM12, PM14).
Tab l e 4-27 . S e t t ing the func t ions o f ANI16/P03, ANI17/P02, ANI18/P147, and ANI19/P120 Pin s (30-p i n p rodu cts)
PMC0, PMC12, and
PMC14 Registers PM0, PM12, and
PM14 Registers ADS Register ANI16/P01, ANI17/P00, ANI18/P147, and
ANI19/P120 Pins
Input mode × Digital input Digital I/O selection
Output mode × Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input
selection
Output mode
Does not select ANI.
Setting prohibited
2. The functions of the ANI0/P20-ANI3/P23, ANI8/P150-ANI14/P156 pins can be selected by using the A/D
port configuration register (ADPC), analog input channel specification register (ADS), and port mode
register 2 and 15 (PM2, PM15).
Table 4-11. Setting t he funct ions of ANI0/P20 to ANI3/P2 3 Pins (30- pin prod ucts)
ADPC Register PM2, PM15 Registers ADS Register ANI0/P20 to ANI7/P27, ANI3/P23 Pins
Input mode × Digital input Digital I/O selection
Output mode × Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input
selection
Output mode
Does not select ANI.
Setting prohibited
Remark ×: don’t care
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4.6 Cautions When Using Port Function
4.6.1 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn)
When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output
latch value of an input port that is not subject to manipulation may be written in addition to t he targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
Example When P00 is an output port, P01 to P03 are input ports (all pin statuses are high level), and the port
latch value of port 0 is 00H, if the output of output port P00 is changed from lo w level to high level via a
1-bit manipulation instruction, the output latch value of port 0 is FFH.
Explanation: The targets of writing to and reading from the Pn register of a port whose PMmn bit is 1 are the output
latch and pin status, respectively.
A 1-bit manipulation instruction is executed in the following order in the RL78/G12.
<1> The Pn register is rea d in 8-bit units.
<2> T he targeted one bit is manipulated.
<3> The Pn register is written in 8-bit units.
In step <1>, the output latch value (0) of P00, which is an output port, is read, while the pin statuses of
P01 to P03, which are input ports, are read. If the pin statuses of P01 to P03 are high level at this time,
the read value is EH.
T he value is changed to FH by the manipulation in <2> .
FH is written to the output latch by the manipulatio n in < 3>.
Figure 4-41. Bit Manipulation In struction (P00)
1-bit manipulation
instruction ( set1
P1.0) is executed for
P00 bit.
Low-level output
× × × × 00 0 0
Port 0 output latch
P00 to P03
P00
×××× 1 1 1 1
P00 to P03
P00
1-bit manipulation instruction for P00 bit
<1> Port register 0 (P0) is read in 8-bit units.
• For P00, an output port, the value of the port output latch (0) is read.
• For P01 to P03, input ports, the pin status (1) is read.
<2> Set the P00 bit to 1.
<3> Write the results of <2> to the output latch of port register 0 (P0) in 8-bit units.
Pin status: High
High-level output
Pin status: High
Port 0 output latch
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4.6.2 Notes on specifying the pin settings
If the output function of an alternate function is assigned to a pin that is also used as an output pin, the output of the
unused alternate function must be set to its initial state so as to prevent conflicting outputs. This also applies to the
functions assigned by using the peripheral I/O redirection register (PIOR). For details about the alternate output function,
see 4.5 Settings of Port Mode Register, and Output Latch When Using Alternate Function.
No specific setting is required for input pins because the output function of their alternate functions is disabled (the
buffer output is Hi-Z).
Table 4-29. Handling of Unused Alternate Functions
Affected Unit Output or I/O Pins of
Unused Alternate
Functions
Handling of Unused Alternate Functions
Timer array units TO0n Make sure that bit m (TOmn) of timer output register m (TOm) and bit n (TOEmn) of
timer output enable register m (TOEm) are set to their initial value (0).
Clock/buzzer
output circuit PCLBUZn Make sure that bit 7 (PCLOEn) of clock output select register n (CKSn) is set to its
initial value (0).
Serial array units SCKmn, SOmn,
SCLmn, SDAmn,
TxDn
Make sure that bit n (SEmn) of serial channel enable status register m (SEm), bit n
(SOmn) of serial output register m (SOm), and bit n (SOEmn) of serial output enable
register m (SOEm) are set to their initial value (1 for SOmn and 0 for others) Note.
IICA SCAA0, SDAA0 Disable the IICA operation by setting bit 7 (IICE0) of the IICCTL00 register to 0.
Note m = 0 for TxD0 and TxD1, and m = 1 for TxD2
Example: P41/ANI22/SO01/SDA01/TI02/TO02/INTP1 pin of 20-pin products
(1) When the pin is used as SO01 output
P41: Specify the output mode by setting PM41 of port mode register 4 to 0.
ANI22: T hese are input pins, so this note does not apply for A/D converter. (Setting PM41 of port
mode register 4 to 0 to digital I/O)
SDA01: This note does not apply Note
TI02, INTP1: These are input pins, so this note does not apply.
TO02: This is an output pin, so set TO02 and TOE02 of timer array unit 0 to 0.
Note Changing the operation mode does not ena ble alternate functions assign ed to pins on the same
serial channel 01 with SO01, and this note does not apply to such pins. (If the CSI function is
specified (MD012 = MD011 = 0), the pin doe s not function as a simplified I2C pin, and therefore
SDA01 I/O is invalid.)
(2) When the pin is used as TO01 output
P41: Specify the output mode by setting PM41 of port mode register 4 to 0.
ANI22: T hese are input pins, so this note does not apply for A/D converter. (Setting PM41 of port
mode register 4 to 0 to digital I/O)
SO01/SDA01: T his is an output and I/O pin, so set SE01, SO01, and SOE01 of serial array unit 0 to 0, 1,
and 0, respectively.
TI02: T hese are input pins, so this note does not apply.
Disabling the unused functions, including blocks that are only used for input or do not have I/O, is recommended to
lower power consumption.
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CHAPTER 5 CLOCK GENERATO R
5.1 Functions of Clock Generator
The clock generator generates the clock to be supplied to the CPU and peripheral hardware.
The following three kinds of system clocks and clock oscillators are selectable.
(1) Main system clock
<1> X1 oscillator
This circuit oscillates a clock of fX = 1 to 20 MHz by connecting a reso nator to X1 and X2.
Oscillation can be stopped by executing the STOP instruction or setting of the MSTOP bit (bit 7 of the clock
operation status control register (CSC)).
<2> High-speed on-chip oscillator
The frequency at which to osc illate can be se lected from am ong fIH = 24/16/12/8/4/1 MHz (TYP.) b y using the
option byte (000C2H). After a reset release, the CPU always starts operating with this high-speed on-chip
oscillator clock. Oscillation can be sto pped b y execut i ng the STOP instruction or s etting the HIOST OP bit (bit
0 of the CSC register).
The frequency specified by using an option byte can be changed b y using the high-speed on-chip oscillator
frequency select register (HOCODIV). For details about the frequency, see Figure 5-9. Format of High-
speed On-chip Oscillator Frequency Select Register (HOCODIV).
The frequencies that can be specifie d for the high-speed on-chip oscillator by using the option byte and the
high-speed on-chip oscillator frequency select register (HOCODIV) are shown below.
Oscillation Frequency (MHz) Power Supply Voltage
1 23468121624
2.7 V ≤ VDD ≤ 5.5 V √ √√√√√√√√
2.4 V ≤ VDD < 2.7 V √ √√√√√√√−
1.8 V ≤ VDD < 2.4 V √ √√√√√−−−
An external main system clock (fEX = 1 to 20 MHz) can also be supplied from the EXCLK pin. An external main
system clock input can be disabled by executing the STOP instruction or setting of the MSTOP bit.
As the main system clock, a high-speed system clock (X1 clock or external main system clock) or high-speed on-
chip oscillator clock can be selected by setting of the MCM0 bit (bit 4 of the system clock control register (CKC)).
(2) Low Speed On-chip Oscillator clock
This circuit oscillates a clock of fIL = 15 kHz (T YP.).
The low speed on-chip oscillator clock cannot be used as the CPU clock.
Only the following peripheral hardware runs on the low speed on-chip oscillator clock.
• Watchdog timer
• 12-bit Interval timer
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation
speed mode control register (OSMC), or both are set to 1.
However, when WDTON = 1, WUTMMCK0 = 0, and bit 0 (WDSTBYON) of the option byte (000C0H) is 0,
oscillation of the LOCO stops if the HALT or STOP instruction is executed.
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Remark fX: X1 clock oscil lation frequency
fIH: High-speed on-chip oscillator clock frequency
f
EX: External main system clock frequenc y
f
IL: Low speed on-chip oscillator clock frequency
5.2 Configuration of Clock Generator
The clock generator includes the following hardware.
Table 5-1. Configuration of Clock Generator
Item Configuration
Control registers Clock operation mode control register (CMC)
System clock control register (CKC)
Clock operation status control register (CSC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Peripheral enable register 0 (PER0)
Operation speed mode control register (OSMC)
High-speed on-chip oscillator frequency selection register (HOCODIV)
High-speed on-chip oscillator trimming register (HIOTRM)
Oscillators X1 oscillator
High-speed on-chip oscillator
Low-speed on-chip oscillator
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Figure 5-1. Block Diagram of Clock Generator
SAU0
EN
3
6
Clock operation mode
control register
(CMC)
Clock operation status
control register
(CSC)
MSTOP
EXCLK
OSCSEL
AMPH
STOP mode
signal
f
MX
X1/P121/KR3
Note1
(TI03/INTP03)
Note1
X2/EXCLK/
P122/KR2
Note1
/
(TI02/INTP02)
Note1
f
X
f
EX
Crystal/ceramic
oscillation
External input
clock
High-speed system
clock oscillator
High-speed on-chip oscillator
Option byte (000C2H)
FRQSEL0 to FRQSEL3
f
IH
Low-speed on-chip
oscillator
Option byte (000C0H)
WDTON
WDSTBYON
HALT/STOP mode signal
HIOSTOP
high-speed on-chip oscillator
trimming register(HIOTRM)
HIOTRM0HIOTRM1
HIOTRM2
HIOTRM3
HIOTRM4HIOTRM5
Internal bus
Clock operation status
control register
(CSC)
High-speed on-chip oscillator
frequency selection register
(HOCODIV)
TAU 0
EN
SAU1
EN
Note2
IICA0
EN
ADC
EN
Peripheral enable
register 0 (PER0)
f
CLK
f
MAIN
CPU
Watchdog timer
CPU clock
and peripheral
hardware
clock source
selection
Timer array unit
Serial arrayry unit 0
A/D converter
Serial interface IICA
Controller
Clock output/buzzer output
Main system clock
source selector
System clock control
register (CKC)
MCM0
MCS
Normal
operation mode
HALT mode
STOP mode
Standby controller
Oscillation stabilization
time select register (OSTS)
Oscillation stabilization
time counter status
register (OSTC)
Internal bus
OSTS1 OSTS0OSTS2
MOST
9
MOST
8
MOST
11
MOST
10
MOST
15
MOST
13
MOST
18
MOST
17
X1 oscillation
stabilization time counter
24/16/12/8/6/4/3/2/1 MHz (TYP.)
HOCODIV2 HOCODIV1 HOCODIV0
15 kHz (TYP.)
f
IL
WUTMMCK0
Operation speed
mode control register
(OSMC)
Controller
12 bits Interval timer
TMKA
EN
Serial arrayry unit 1
Notes 1. 20-, 24-pin products only.
2. 30-pin products only.
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Remark fX: X1 clock oscillation frequency
f
IH: High-speed on-chip oscillator clock frequency
f
EX: External main system clock frequency
f
MX: High-speed system clock frequency
fMAIN: Main system clock frequency
f
CLK: CPU/peripheral hardware clock frequency
f
IL: Low-speed on-chip oscillator clock frequency
5.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operatio n mode control register (CMC)
• System clock control register (CKC)
• Clock operatio n status control register (CSC)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Peripheral ena ble register 0 (PER0)
• Operation speed mod e control register (OSMC)
• High-speed on-chip oscillator frequency selection register (HOCODIV)
• High-speed on-chip oscillator trimming register (HIOTRM)
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5.3.1 Clock operation mode control register (CMC)
This register is used to set the operation m ode of the X1/P121 and X2/EXCLK/P122 pins , and to select a gain of the
oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-2. Format of Clock Operation Mode Control Register (CMC)
Address: FFFA0H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CMC EXCLK OSCSEL 0 0 0 0 0 AMPH
EXCLK OSCSEL High-speed system clock
pin operation mode X1/P121/KR3 pin X2/EXCLK/P122/KR2
pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input mode Input port External clock input
AMPH Control of X1 clock oscillation frequency
0 1 MHz ≤ fX ≤ 10 MHz
1 10 MHz < fX ≤ 20 MHz
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
manipulation instruction. When using the CMC register with its initial value (00H), be
sure to set the registe r to 00H after a reset ends in order to prevent malfunction due
to a program loop. Such a malfunction becomes unrecoverable when a value other
than 00H is mistakenly written.
2. After reset rel ease, set the CMC register before X1 oscillation is started as set by the
clock operation status control register (CSC).
3. Specify the settings for the AMPH bits while fIH is selected as fCLK after a reset ends
(before fCLK is switched to fMX).
4. Switch the operation mode of the X1/X2 pins only when MSTOP = 1.
5. Although the maximum system clock frequency is 24 MHz, the maximum frequency
of the X1 oscillator is 20 MHz.
Remark f
X: X1 clock frequency
<R>
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5.3.2 System clock control register (CKC)
This register is used to select a CPU/peripheral hardware clock and a ma in system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipu lation instruction.
Reset signal generation sets this register to 00H.
Figure 5-3. Format of System Clock Control Register (CKC)
Address: FFFA4H After reset: 00H R/W Note
Symbol 7 6 <5> <4> 3 2 1 0
CKC 0 0 MCS MCM0 0 0 0 0
MCS Status of Main system clock (fMAIN)
0 High-speed on-chip oscillator clock (fIH)
1 High-speed system clock (fMX)
MCM0 Main system clock (fMAIN) operation control
0 Selects the high-speed on-chip oscillator clock (fIH) as the main system clock (fMAIN)
1 Selects the high-speed system clock (fMX) as the main system clock (fMAIN)
Note Bit 5 is read-only.
Caution Be sure to set undefined bits to 0.
Remark fIH: High-speed on-chip oscillator clock frequency
fMX: High-speed system clock frequency
f
MAIN: Main system clock frequency
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5.3.3 Clock operation status control register (CSC)
This register is used to control the operation s of the high-speed system clock and high-s peed on-chip oscillator clock,
(except the low-speed on-chip oscillator clock).
The CSC register can be set by a 1-bit or 8-bit memory manipu lation instruction.
Reset signal generation sets this register to C0H.
Figure 5-4. Format of Clock Operation Statu s Co n t ro l Register (CSC)
Address: FFFA1H After reset: C0H R/W
Symbol <7> 6 5 4 3 2 1 <0>
CSC MSTOP 1 0 0 0 0 0 HIOSTOP
High-speed system clock operation control
MSTOP
X1 oscillation mode External clock input mode Input port mode
0 X1 oscillator operating External clock from EXCLK
pin is valid
1 X1 oscillator stopped External clock from EXCLK
pin is invalid
Input port
HIOSTOP High-speed on-chip oscillator clock operation control
0 High-speed on-chip oscillator clock operating
1 High-speed on-chip oscillator clock stopped
Cautions 1. After reset release, set the clock operation mode control register (CMC) before
setting the CSC register.
2. Set the oscillation stabilization time select register (OSTS) before setting the MSTOP
bit to 0 after releasing reset. Note that if the OSTS register is being used with its
default settings, the OSTS register is not required to be set here.
3. To start X1 oscillation as set by the MSTOP bit, check the oscillation stabilization
time of the X1 clock by using the oscillation stabilization time counter status register
(OSTC).
4. Do not stop the clock selected for the CPU peripheral hardware clock (fCLK) with the
CSC register.
5. The setting of the flags of the register to stop clock oscillation (invalidate the
external clock input) and the condition before clock oscillation is to be stopped are
as Table 5-2.
Table 5-2. Condition Before Stopping Clock Oscillation and Flag Setting
Clock Condition Before Stopping Clock
(Invalidating External Clock Input) Setting of CSC
Register Flags
X1 clock
External main system
clock
CPU and peripheral hardware clocks operate with a high-
speed on-chip oscillator clock. (MCS = 0) MSTOP = 1
High-speed on-chip
oscillator clock CPU and peripheral hardware clocks operate with a high-
speed system clock.(MCS = 1) HIOSTOP = 1
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5.3.4 Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the follo wing case:
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock.
• If the STOP mode is entered and then r ele as ed while the high- spee d on-c hip oscillator cl ock is bein g us ed as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read b y a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the foll owing cases.
• W hen oscillation of the X1 clock starts (EXCLK, OSCSEL = 0, 1 → MSTOP = 0)
• When the STOP mode is released
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Figure 5-5. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST
8 MOST
9 MOST
10 MOST
11 MOST
13 MOST
15 MOST
17 MOST
18
Oscillation stabilization time status MOST
8 MOST
9 MOST
10 MOST
11 MOST
13 MOST
15 MOST
17 MOST
18 f
X = 10 MHz fX = 20 MHz
0 0 0 0 0 0 0 0 28/fX max. 25.6
μ
s max. 12.8
μ
s max.
1 0 0 0 0 0 0 0 28/fX min. 25.6
μ
s min. 12.8
μ
s min.
1 1 0 0 0 0 0 0 29/fX min. 51.2
μ
s min. 25.6
μ
s min.
1 1 1 0 0 0 0 0 210/fX min. 102.4
μ
s min. 51.2
μ
s min.
1 1 1 1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 1 1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 1 1 1 0 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 1 1 0 217/fX min. 13.11 ms min. 6.55 ms min.
1 1 1 1 1 1 1 1 218/fX min. 26.21 ms min. 13.11 ms min.
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from the MOST8 bit
and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the oscillation stabilization time select register (OSTS).
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is
being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating.
(Note, therefore, that only the status up to the oscillation stabilization time set by
the OSTS register is set to the OSTC register after the STOP mode is released.)
3. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
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5.3.5 Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU clock, the operation automatically waits for the time set using the OSTS
register after the STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OST C) that the desired oscill ation stabilization ti me has elapsed after the STOP mode is
released. The oscillation stabi lization time can be checked up to the time set using the OSTC register.
The OSTS register can be set b y an 8-bit memory manipulation instruction.
Reset signal generation sets the OSTS register to 07H.
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Figure 5-6. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
OSTS2 OSTS1 OSTS0
fX = 10 MHz fX = 20 MHz
0 0 0 28/fX 25.6
μ
s 12.8
μ
s
0 0 1 29/fX 51.2
μ
s 25.6
μ
s
0 1 0 210/fX 102.4
μ
s 51.2
μ
s
0 1 1 211/fX 204.8
μ
s 102.4
μ
s
1 0 0 213/fX 819.2
μ
s 409.6
μ
s
1 0 1 215/fX 3.27 ms 1.64 ms
1 1 0 217/fX 13.11 ms 6.55 ms
1 1 1 218/fX 26.21 ms 13.11 ms
Cautions 1. To set the STOP mode when the X1 clock is used as the CPU clock, set the OSTS
register before executing the STOP instruction.
2. Change the setting of the OSTS register before setting the MSTOP bit of the clock
operation status control register (CSC) to 0.
3. Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization
time set by the OSTS register.
In the following cases, set the oscillation stabilization time of the OSTS register to
the value greater than the count value which is to be checked by the OSTC register
after the oscillation starts.
• If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is
being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock with the X1 clock oscillating. (Note,
therefore, that only the status up to the oscillation stabilization time set by the
OSTS register is set to the OSTC register after the STOP mode is released.)
5. The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
a
STOP mode release
X1 pin voltage
waveform
Remark f
X: X1 clock oscillation frequency
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5.3.6 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
To use the peripheral functions below, which are controlled by this register, set (1) the bit corresponding to each
function before specifying the initial settings of the peripheral functions.
• 12-bit Interval timer
• A/D converter
• Serial interface IICA
• Serial array unit 1
• Serial array unit 0
• Timer array unit 0
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (1/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
TMKAE Control of 12-bit interval timer input clock supply
0 Stops input clock supply.
• SFR used by the 12-bit interval timer cannot be written.
• The 12-bit interval timer is in the reset status.
1
Enables input clock supply.
• SFR used by the 12-bit interval timer can be read and written.
ADCEN Control of A/D converter input clock supply
0 Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1
Enables input clock supply.
• SFR used by the A/D converter can be read and written.
IICA0EN Control of serial interface IICA input clock supply
0 Stops input clock supply.
• SFR used by the serial interface IICA cannot be written.
• The serial interface IICA is in the reset status.
1
Enables input clock supply.
• SFR used by the serial interface IICA can be read and written.
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Figure 5-7. Format of Peripheral Enable Register 0 (PER0) (2/2)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
SAU1EN Control of serial array unit 1 input clock supply
0 Stops input clock supply. (Fixed as 0 in 20-, and 24-pin products)
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial array unit 1 can be read and written.
SAU0EN Control of serial array unit 0 input clock supply
0 Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
1
Enables input clock supply.
• SFR used by the serial array unit 0 can be read and written.
TAU0EN Control of timer array unit input clock supply
0 Stops input clock supply.
• SFR used by timer array unit cannot be written.
• Timer array unit is in the reset status.
1
Enables input clock supply.
• SFR used by timer array unit can be read and written.
Caution Be sure to clear undefined bits to 0.
5.3.7 Operation speed mode contro l reg ister (OSMC)
The OSMC register can be used to control supply of the op eration clock for the 12-bit interval timer.
When operating the 12-bit interval timer, set WUTMMCK0 = 1 beforehand and do not set WUTMMCK0 = 0 until the
timer is stopped.
The OSMC register can be set by an 8-bit memor y manipula tion instruction.
Reset signal generation clears this register to 00H.
Figure 5-8. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC 0 0 0
WUTMMCK0
0 0 0 0
WUTMMCK0
Supply of operation clock for 12-bit interval timer
0 Stops Clock supply
1 Low-speed on-chip oscillator clock (fIL) supply
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5.3.8 High-speed on-chip oscillator frequency selection register (HOCODIV)
This register is used to change the frequency of the high-speed on-chip oscillator clock set with the option byte
(000C2H). The available frequency varies depending on the value of the FRQSEL3 bit of the option byte (000C2H).
HOCODIV can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to default value (undefined).
Figure 5-9 Format of High-Speed On-Chip Oscillator Frequency Selection Register (HOCODIV)
Address: F00A8H After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
HOCODIV 0 0 0 0 0
HOCODIV 2 HOCODIV 1 HOCODIV 0
High-speed on-chip oscillator clock frequency selection
HOCODIV 2 HOCODIV 1 HOCODIV 0
FRQSEL3 bit is 0 FRQSEL 3 bit is 1
0 0 0 24 MHz Setting prohibited
0 0 1 12 MHz 16 MHz
0 1 0 6 MHz 8 MHz
0 1 1 3 MHz 4 MHz
1 0 0 Setting prohibited 2 MHz
1 0 1 Setting prohibited 1 MHz
Other than above Setting prohibited
Cautions 1. Set the HOCODIV register within the operable voltage range of the flash operation
mode set in the option byte (000C2H) before and after the frequency change.
Option byte (000C2H) value
CMODE1 CMODE2
Flash operation mode Operating frequency
range Operating voltage
range
1 0
LS (low-speed main)
mode 1 MHz to 8 MHz 1.8 V to 5.5 V
1 MHz to 16 MHz 2.4 V to 5.5 V 1 1
HS (high-speed main)
mode 1 MHz to 24 MHz 2.7 V to 5.5 V
2. Set the HOCODIV register with the high-speed on-chip oscillator clock (fIH) selected as
the CPU/peripheral hardware clock (fCLK).
3. After settings are changed with the HOCODIV regi ster, the frequency is switched after
the following tran sition time has elapsed.
•Operation for three clocks at the pre-change frequency
•CPU/peripheral hardware clock wait at the post-change frequency for up to three
clocks
5.3.9 High-speed on-chip oscillator trimming register (HIOTRM)
This register is used to adjust the accuracy of the high-speed on-chip oscilla t or.
With self-measurement of the high-speed on-chip oscillator frequency via a timer using high-accuracy external clock
input (timer array unit), and so on, the accuracy can be adjusted.
The HIOTRM register can be set by an 8-bit memory manipulation instruction.
<R>
<R>
<R>
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Caution The frequency will vary if the temperature and VDD pin voltage change after accuracy adjustment.
When the temperature an d VDD voltage ch ange, accuracy adjustment mu st be executed regul arly or
before the frequency accuracy is required.
Figure 5-10. Format of High-Speed On-chip Oscillator Trimming Register (HIOTRM)
Address: F00A0H After reset: Note R/W
Symbol 7 6 5 4 3 2 1 0
HIOTRM 0 0 HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0
HIOTRM5 HIOTRM4 HIOTRM3 HIOTRM2 HIOTRM1 HIOTRM0 High-speed on-chip
oscillator
0 0 0 0 0 0
Minimum speed
0 0 0 0 0 1
0 0 0 0
1 0
0 0 0 0
1 1
0 0 0
1 0 0
•
•
•
1 1 1 1 1 0
1 1 1 1 1 1 Maximum speed
Note The reset value differs for each chip.
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5.4 System Clock Oscillator
5.4.1 X1 oscillator
The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 20 MHz) connected to the X1 and X2
pins.
An external clock can also be input. In this case, input the clock signal to the EXCLK pin.
To use the X1 oscillator, set bits 7 and 6 (EXCLK, OSCSEL) of the clock operation mode control register (CMC) as
follows.
• Crystal or ceramic oscillation: EXCLK, OSCSEL = 0, 1
• External clock input: EXCLK, OSCSEL = 1, 1
When the X1 oscillator is not used, set the input port mode (EXCLK, OSCSEL = 0, 0).
When the pins are not used as input port pins, either, see 2.3 Pin I/O Circuits and Recommended Connection of
Unused Pins.
Figure 5-11 shows an example of the external circuit of the X1 oscill ator.
Figure 5-11. Example of External Circuit of X1 Oscillator
(a) Crystal or ceramic oscillation (b) External clock
V
SS
X1
X2
Crystal resonator
or
ceramic resonator
EXCLK
External clock
Caution When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the Figure 5-
11 to avoid an adverse effect fro m wiring capacitance.
• Keep the wiring leng th as short as possible.
• Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS. Do not
ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
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Figure 5-12 sho ws examples of incorrect resonator connection.
Figure 5-12. Examples of Inco rrect Resonator Connection (1/2)
(a) Too long wiring (b ) Cro ssed signal line
X2VSS X1 X1
NG
NG
NG
VSS X2
PORT
(c) The X1 and X2 signal line wires cross. (d) A power supply/GND pattern exists
under the X1 and X2 wires.
X2VSS X1
X1
Power supply/GND pattern
VSS X2
Note
Note Do not place a power supply/GND pattern under the wiring section (section indicated by a broken line in the
figure) of the X1 and X2 pins and the resonators in a multi-layer board or double-sided board.
Do not configure a layout that will cause ca pacitance elements and affect the oscill ation characteristics.
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Figure 5-12. Examples of Inco rrect Resonator Connection (2/2)
(e) Wiring near high alternating current (f) Current flowing through ground line of oscillator
(potential at points A, B, and C fluctuates)
V
SS
X1 X2
V
SS
X1 X2
AB C
Pmn
V
DD
High current
High current
(g) Signals are fetched
VSS X1 X2
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5.4.2 High-speed on-chip oscillator
The high-speed on-chip oscillator is in corporated i n the RL 78/G12. The frequ enc y can be select ed from among 24, 16,
12, 8, 4, or 1 MHz by using the option byte (000C2H). Oscillation can be controlled by bit 0 (HIOSTOP) of the clock
operation status control register (CSC). The high-speed on-chip oscillator automatically starts oscillating after reset
release.
5.4.3 Low-speed on-chip oscillator
The low-speed on-chip oscill ator is incorporated in the RL78/G12.
The low-speed on-chip oscillator clock is used only as the watchdog timer, and 12-bit interval timer clock. The low-
speed on-chip oscillator clock cannot be used as the CPU clock.
This clock operates when bit 4 (WDTON) of the option byte (000C0H), bit 4 (WUTMMCK0) of the operation speed
mode control register (OSMC), or both are set to 1.
Unless the watchdog timer is stoppe d and WUTMMCK0 is a valu e other than zero, oscill ation of the low-speed on-chip
oscillator continues. While the watchdog timer operates, the low-speed on-chip oscillator clock does not stop even if the
program freezes.
5.5 Clock Generator Operation
The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby
mode (see Figure 5-1).
• Main system clock fMAIN
• High-speed system clock fMX
X1 clock fX
External main system clock fEX
• High-speed on-chip oscillator clock fIH
• Low-speed on-chip oscillat or clock fIL
• CPU/peripheral hardware clock fCLK
The CPU starts operation when the high-sp eed on-chi p os cillator starts outputti ng after a reset releas e in the RL78/G12.
When the power supply voltage is turned on, the clock generator operation is shown in Figure 5-13.
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Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On
(When voltage detector (LVD) is used)
Note 1
Power supply
voltage (V
DD
)
Internal reset signal
CPU clock
High-speed on-chip
oscillator clock (f
IH
)
High-speed
system clock (f
MX
)
(
when X1 oscillation
selected)
Reset processing
Note 3
Switched by software
High-speed system clockHigh-speed on-chip oscillator
clock
X1 clock
oscillation stabilization time
Note 2
Starting X1 oscillation
is specified by software.
<4>
<5>
<1>
<2>
<3>
0 V
LVD release
reset voltage
<1> When the power is turned on, an internal reset signal is generated by the power-on-reset (POR) circuit.
<2> When the power supply voltage exceeds detection voltage of voltage detector (LVD), the reset is released and
the high-speed on-chip oscilla t or automatica lly starts oscillation.
<3> The CPU starts operation on the high-speed on-chip oscillator clock after a reset processing such as waiting for
the voltage of the power supply or regulator to stabilize has bee n performed after reset release.
<4> Set the start of oscillation of the X1 clock via software (see 5.6.2 Example of setting X1 oscillation clock).
<5> When switching the CPU cl ock to the X1 clock, wait for the clock oscill ation to stabiliz e, and then s witch the clock
via software.
Notes 1. T he internal reset processing time includes the oscillation accuracy stabilization time of the hi gh-speed on-
chip oscillator clock.
2. When releasing a reset, confirm the oscillation stabilization time for the X1 clock using the oscillation
stabilization time counter status register (OSTC).
3. .For the reset processing time, see CHAPTER 19 POWER-ON-RESET CIRCUIT.
Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the
EXCLK pin is used.
<R>
<R>
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5.6 Controlling Clock
5.6.1 Example of setting high-speed on-chip oscillator
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. The frequency of the high-speed on-chip oscillator can be selected by using FRQSEL0 to FRQSEL3 of
the option byte (000C2H). This frequency can be chang ed with the high-speed on-chip oscillator freq uency select register
(HOCODIV).
[Option byte setting]
Address: 000C2H 7 6 5 4 3 2 1 0
Option
byte
(000C2H) CMODE1
0/1
CMODE0
0/1
1
0
FRQSEL3
0/1
FRQSEL2
0/1
FRQSEL1
0/1
FRQSEL0
0/1
CMODE1 CMODE0 Setting of flash operation mode
1 0
LS (low speed main) mode VDD = 1.8 V to 5.5 V @ 1 MHz to 8 MHz
1 1
HS (high speed main) mode VDD = 2.4 V to 5.5 V @ 1 MHz to 16 MHz
VDD = 2.7 V to 5.5 V @ 1 MHz to 24 MHz
Other than above Setting prohibited
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator
0 0 0 0
24 MHz
1 0 0 1
16 MHz
0 0 0 1
12 MHz
1 0 1 0
8 MHz
1 0 1 1
4 MHz
1 1 0 1
1 MHz
Other than above Setting prohibited
[High-speed on-chip oscillator frequency selection register (HOCODIV) setting]
Address: F00A8H
7 6 5 4 3 2 1 0
HOCODIV 0 0 0 0 0
HOCODIV 2 HOCODIV 1 HOCODIV 0
High-speed on-chip oscillator clock frequency selection
HOCODIV 2 HOCODIV 1 HOCODIV 0
FRQSEL3 bit is 0 FRQSEL 3 bit is 1
0 0 0 24 MHz Setting prohibited
0 0 1 12 MHz 16 MHz
0 1 0 6 MHz 8 MHz
0 1 1 3 MHz 4 MHz
1 0 0 Setting prohibited 2 MHz
1 0 1 Setting prohibited 1 MHz
Other than above Setting prohibited
<R>
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5.6.2 Example of setting X1 oscillation clock
After a reset release, the CPU/peripheral hardware clock (fCLK) always starts operating with the high-speed on-chip
oscillator clock. To subsequently change the clock to the X1 oscillation clock, set the oscillator and start oscillation by
using the oscillation stabilization time select register (OSTS) and clock operation mode control register (CMC) and clock
operation status control register (CSC) and wait for oscillation to stabilize by using the oscillation stabilization time select
register (OSTC). After the oscillation stabilizes, set the X1 oscillation clock to fCLK by using the system clock control
register (CKC).
[Register settings] Set the register in the order of <1> to <5> below.
<1> Set (1) the OSCSEL bit of the CMC register, except for the cases fX > 10 MHz, in such cases set (1) the AMPH bit,
to operate the X1 oscillator.
7 6 5 4 3 2 1 0
CMC EXCLK
0
OSCSEL
1
0
0
0
0
0
AMPH
1
AMPH bit: Set this bit to 0 if the X1 oscillation clock is 10 MHz or less.
<2> Using the OSTS register, select the oscillation stabilization time of the X1 oscillator at releasing of the STOP mode.
Example: Setting values when a wait of at least 102.4
μ
s is set based on a 10 MHz resonator.
7 6 5 4 3 2 1 0
OSTS
0
0
0
0
0
OSTS2
0
OSTS1
1
OSTS0
0
<3> Clear (0) the MSTOP bit of the CSC register to start oscillating the X1 oscillator.
7 6 5 4 3 2 1 0
CSC MSTOP
0
0
0
0
0
0
0
HIOSTOP
0
<4> Use the OSTC register to wait for oscillation of the X1 oscillator to stabilize.
Example: Wait until the bits re ach the following values when a wait of at l east 102.4
μ
s is set based on a 10 MHz
resonator.
7 6 5 4 3 2 1 0
OSTC MOST8
1
MOST9
1
MOST10
1
MOST11
0
MOST13
0
MOST15
0
MOST17
0
MOST18
0
<5> Use the MCM0 bit of the CKC register to specify the X1 oscillation clock as the CPU/peripheral hardware clock.
7 6 5 4 3 2 1 0
CKC
0
0
MCS
0
MCM0
1
0
0
0
0
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5.6.3 CPU clock status transition diagram
Figure 5-14 sho ws the CPU clock status transition di agram of this product.
Figure 5-14. CPU Clock Status Transition Diagram
CPU: High-speed
on-chip oscillator
=> SNOOZE
High-speed on-chip oscillator: Woken up
X1 oscillation/EXCLK input: Stops (input port mode)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops (input port mode)
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Selectable by CPU
High-speed on-chip oscillator: Selectable by CPU
X1 oscillation/EXCLK input: Operating
Power ON
Reset release
(A)
(B)
(C)
V
DD
1.51 V to 0.03 V
>
V
DD
1.51 V to 0.03 V
V
DD
1.8 V
(operation guaranteed range:Transition voltage is defined by the LVD)
CPU: Operating
high-speed on-chip
oscillator
(D)
(F)
(H)
CPU: High-speed
on-chip oscillator
=> STOP
CPU: High-speed
on-chip oscillator
=> HALT
CPU: Internal high-
speed oscillation
=> HALT
CPU: Operating
with X1 oscillation or
EXCLK input
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
High-speed on-chip oscillator: Stops
X1 oscillation/EXCLK input: Stops
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Stops
High-speed on-chip oscillator: Operating
X1 oscillation/EXCLK input: Oscillatable
High-speed on-chip oscillator: Oscillatable
X1 oscillation/EXCLK input: Operating
CPU: X1
oscillation/EXCLK
input => STOP
(G)
(E)
=
=
>
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Table 5-3 shows transition of the CPU clock and examples of setting the SFR registers.
Table 5-3. CPU Clock Transition and SFR Register Setting Examples (1/3)
(1) CPU operating with high-speed on-chip oscillator clock (B) after reset release (A)
Status Transition SFR Register Setting
(A) → (B) SFR registers do not have to be set (default status after reset release).
(2) CPU operating with high-speed system clock (C) after reset release (A)
(The CPU operates with the high-speed on-chip oscillator clock immedi ately after a reset release (B).)
(Setting sequence of SFR registers)
CMC Register Note1 CSC
Register CKC
Register
Setting Flag of SFR Register
Status Transition EXCLK OSCSEL AMPH
OSTS
Register
MSTOP
OSTC
Register
MCM0
(A) → (B) → (C)
(X1 clock: 1 MHz ≤ fX ≤ 10 MHz) 0 1 0 Note 2 0 Must be
checked 1
(A) → (B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz) 0 1 1 Note 2 0 Must be
checked 1
(A) → (B) → (C)
(external main clock) 1 1 × Note 2 0 Must not
be
checked
1
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory manipulation
instruction after reset release.
2. Set the oscillati on stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. ×: don’t care
2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14
.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (2/3)
(3) CPU clock changing from high-speed on-chip oscillator clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
CMC RegisterNote 1 CSC
Register CKC
Register
Setting Flag of SFR Register
Status Transition EXCLK OSCSEL AMPH
OSTS
Register
MSTOP
OSTC Register
MCM0
(B) → (C)
(X1 clock: 1 MHz ≤ fX ≤ 10 MHz)
0 1 0 Note 2 0 Must be checked 1
(B) → (C)
(X1 clock: 10 MHz < fX ≤ 20 MHz)
0 1 1 Note 2 0 Must be checked 1
(B) → (C)
(external main clock)
1 1 × Note 2 0 Must not be checked 1
Unnecessary if these registers
are already set
Unnecessary if the CPU is operating with
the high-speed system clock
Notes 1. The clock operation mode control register (CMC) can be written only once by an 8-bit memory
manipulation instruction after reset release. T his setting is not necessary if it has already been set.
2. Set the oscillation stabilization time as follows.
• Desired the oscillation stabilization time counter status register (OSTC) oscillation stabilization time ≤
Oscillation stabilization time set by the oscillation stabilization time select register (OSTS)
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 28 ELECTRICAL SPECIFICATIONS).
(4) CPU clock ch anging from high-speed system clock (C) to high-speed on-chip oscillator clock (B)
(Setting sequence of SFR registers)
CSC Register CKC Register
Setting Flag of SFR Register
Status Transition HIOSTOP
Oscillation accuracy
stabilization time MCM0
(C) → (B) 0 30
μ
s 0
Unnecessary if the CPU is operating with the
high-speed on-chip oscillator clock
(5) • HALT mode (D) set while CPU is operating with high-speed on-chip oscillator clock (B)
• HALT mode (E) set w hile CPU is operating with high-speed system clock (C)
Status Transition Setting
(B) → (D)
(C) → (E) Executing HALT instruction
Remarks 1. ×: don’t care
2. (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14.
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Table 5-3. CPU Clock Transition and SFR Register Setting Examples (3/3)
(6) • STOP mode (F) set while CPU is operating with high-speed on-chip oscillator clock (B)
• STOP mode (G) set while CPU is operating with high-speed system cl o ck (C)
(Setting sequence)
Status Transition Setting
(B) → (F)
−
In X1 oscillation Sets the OSTS
register
(C) → (G)
External main
system clock
Stopping peripheral
functions that cannot
operate in STOP mode
−
Executing STOP
instruction
(7) CPU changing from STOP mode (F) to SNOOZE mode (H)
For details about the setting for switching from the STOP mode to the SNOOZE mode, see 10.8 SNOOZE Mode
Function, 11.5.7 SNOOZE mode function and 11.6.3 SNOOZE mode function.
Remark (A) to (H) in Table 5-3 correspond to (A) to (H) in Figure 5-14.
5.6.4 Condition before changing CPU clock and processing after changing CPU clock
Condition before changin g the CPU clock and processing after changing the CPU clock are shown below.
Table 5-4. Changing CPU Clock
CPU Clock
Before Change After Change Condition Before Change Processing After Change
X1 clock Stabilization of X1 oscillation
• OSCSEL = 1, EXCLK = 0, MSTOP = 0
• After elapse of oscillation stabilization time
High-speed on-
chip oscillator
clock
External main
system clock Enabling external clock input from the
EXCLK pin
• OSCSEL = 1, EXCLK = 1, MSTOP = 0
Operating current can be reduced by
stopping high-speed on-chip oscillator
(HIOSTOP = 1).
High-speed on-
chip oscillator
clock
Oscillation of high-speed on-chip oscillator
• HIOSTOP = 0
• After elapse of oscillation stabilization time
X1 oscillation can be stopped
(MSTOP = 1).
X1 clock
External main
system clock Transition not possible
−
High-speed on-
chip oscillator
clock
Oscillation of high-speed on-chip oscillator
• HIOSTOP = 0
• After elapse of oscillation stabilization time
External main system clock input can
be disabled (MSTOP = 1).
External main
system clock
X1 clock Transition not possible −
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5.6.5 Time required fo r sw itchover of CPU clock and main system clock
The main system clock can be switched between the high-speed on-chip oscillator clock and the high-speed system
clock by specifying bit 4 (MCM0) of the system clock contr ol register (CKC).
The actual switchover operation is not performed immediately after rewriting to the CKC register; operation continues
on the pre-switchover clock for several clocks (see Table 5-5).
Whether the main system clock is op erating on the high-speed s ystem clock or high-speed on-chi p oscillator clock can
be ascertained using bit 5 (MCS) of the CKC register.
When the CPU clock is switched, the peripheral hardware is also switched.
Table 5-5. Maximum Number of Clocks Required for fIH ↔ fMX
Set Value Before Switchover Set Value After Switchover
MCM0 MCM0
0
(fMAIN = fIH) 1
(fMAIN = fMX)
fMX≥fIH 2 clock
0
(fMAIN = fIH) fMX<fIH 2fIH/fMX clock
fMX≥fIH 2fMX/fIH clock
1
(fMAIN = fMX) fMX<fIH 2 clock
Remarks 1. Number of CPU clocks before switchover.
2. Calculate the number of clocks by rounding to the nearest whole number.
Example When switching the main system clock from t he h igh-s peed s ystem clock to the hig h-speed o n-
chip oscillator clock (@ oscillation with fIH = 8 MHz selected, fMX = 10 MHz)
2 fIH/fMX = 2(10/8) = 2.5 → 3 clocks
5.6.6 Conditions before clock oscillation is stopped
The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and
conditions before the clock oscillation is stopped.
Table 5-6. Conditions Before the Clock Oscillation Is Stopped and Flag Settings
Clock Conditions Before Clock Oscillation Is Stopped
(External Clock Input Disabled) Flag Settings of SFR
Register
High-speed on-chip
oscillator clock MCS = 1
(The CPU is operating on the high-speed system clock.) HIOSTOP = 1
X1 clock
External main system clock
MCS = 0
(The CPU is operating on the high-speed on-chip oscillator clock.) MSTOP = 1
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5.7 Resonator and Oscillator Constants
The resonators for which the operation is verified and their oscillator constants are shown below.
Cautions 1. The constants for these oscillator circuits are reference values based on specific environments
set up for evaluation by the manufacturers. For actual applications, request evaluation by the
manufacturer of the oscillator circuit mounted on a board. Furthermore, if you are switching
from a different product to this microcontroller, and whenever you change the board, again
request evaluation by the manufacturer of the oscillator circuit mounted on the new board.
2. The oscillation voltage and oscillation frequency only indicate the oscillator characteristic. Use
the RL78/G12 so that the internal operation conditions are within the specifications of the DC and
AC characteristics. Figure 5-15. External Circuit Example
C1
X2X1
C2
V
SS
Rd
<R>
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As of September, 2012
Recommended Circuit
Constants Note 2 (reference) Oscillation Voltage
Range (V)
Manufacturer Resonator Part Number SMD/
Lead Frequency
(MHz) Frash
operation
modeNote 1 C1 (pF) C2 (pF) Rd (kΩ) MIN. MAX.
CSTCC2M00G56-R0 SMD 2.000 (47) (47) 0
CSTCR4M00G55-R0 SMD (39) (39) 0
CSTLS4M00G53-B0 READ
4.000
LS，HS
(15) (15) 0
CSTCR4M19G55-R0 SMD (39) (39) 0
CSTLS4M19G53-B0 READ
4.194
(15) (15) 0
CSTCR4M91G53-R0 SMD (15) (15) 0
CSTLS4M91G53-B0 READ
4.915
(15) (15) 0
CSTCR5M00G53-R0 SMD (15) (15) 0
CSTLS5M00G53-B0 READ
5.000
(15) (15) 0
CSTCR6M00G53-R0 SMD (15) (15) 0
CSTLS6M00G53-B0 READ
6.000
(15) (15) 0
CSTCE8M00G52-R0 SMD (10) (10) 0
CSTLS8M00G53-B0 READ
8.000
(15) (15) 0
1.8(LS)
2.4(HS)
5.5
CSTCE8M38G52-R0 SMD (10) (10) 0
CSTLS8M38G53-B0 read
8.388
(15) (15) 0
CSTCE10M0G52-R0 SMD (10) (10) 0
CSTLS10M0G53-B0 READ
10.000
HS
(15) (15) 0
CSTCE12M0G52-R0 SMD 12.000 (10) (10) 0
CSTCE16M0V53-R0 SMD (15) (15) 0
CSTLS16M0X51-B0 READ
16.000
(5) (5) 0
2.4 5.5
CSTCE20M0V51-R0 SMD (5) (5) 0
Murata
Manufacturing
Co., Ltd.
Ceramic
resonator
CSTLS20M0X51-B0 READ
20.000
(5) (5) 0
2.7 5.5
Notes 1. Set the flash o peration mode by using CMODE1 and CMODE0 bits of the option byte (000C2H/010C2 H).
2. Values in parentheses in the C1, C2 columns indicate an in ternal capacitance.
Remark Relationship between operation voltage width, operation frequency of CPU and operation mode is as below.
HS (High speed main) mode: 2.7 V ≤ VDD ≤ 5.5 V@1 MHz to 24 MHz
2.4 V ≤ VDD ≤ 5.5 V@1 MHz to 16 MHz
LS (Low speed main) mode: 1.8 V ≤ VDD ≤ 5.5 V@1 MHz to 8 MHz
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CHAPTER 6 TIMER ARRAY UNIT
The timer array unit has four/eight 16-bit timers.
Each 16-bit timer is called a channel and can be used as an independent timer. In addition, two or more “channels” can
be used to create a high-accuracy timer.
TIMER ARRAY UNIT
16-bit timers
channel 1
channel 0
channel 2
channel 3
channel 4
Note
channel 7
Note Provided only in 30-pin products
For details about each function, see the table below.
Independent channel operation function Simultaneous channel operation function
• Interval timer (→ refer to 6.7.1)
• Square wave output (→ refer to 6.7.1)
• External event counter (→ refer to 6.7.2)
• Divider Note (→ refer to 6.7.3)
• Input pulse interval measurement (→ refer to 6.7.4)
• Measurement of high-/low-level width of input signal
(→ refer to 6.7.5)
• Delay counter (→ refer to 6.7.6)
• One-shot pulse output(→ refer to 6.8.1)
• PWM output(→ refer to 6.8.2)
• Multiple PWM output(→ refer to 6.8.3)
Note Only channel 0
It is possible to use the 16-bit timer of channels 1 and 3 as two 8-bit timers (higher and lower). The functions that can
use channels 1 and 3 as 8-bit timers are as follows:
• Interval timer/square wave output
• External event counter (lower 8-bit timer only)
• Delay counter (lower 8-bit timer only)
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6.1 Functions of Ti mer Array Unit
Timer array unit has the following functions.
6.1.1 Independent channel operation function
By operating a channel independently, it can be used for the following purposes without being affected by the operation
mode of other channels.
(1) Interval timer
Each timer of a unit can be used as a reference timer that generates an interrupt (INTTM0n) at fixed intervals.
Interrupt signal
(INTTM0n)
Operation clock Compare operation
Channel n
(2) Square wave output
A toggle operation is performed each time INTTM0n interrupt is generated and a square wave with a duty factor of
50% is output from a timer output pin (TO0n).
Timer output
(TO0n)
Operation clock Compare operation
Channel n
(3) External event counter
Each timer of a unit can be used as an event counter that generates an interrupt when the number of the valid
edges of a signal input to the timer input pin (TI0n) has reached a specific value.
Interrupt signal
(INTTM0n)
Edge detection
Timer input
(TI0n)
Compare operation
Channel n
(4) Divider function (channel 0 only)
A clock input from a timer input pin (TI00) is divided and output from an output pin (TO00).
Timer output
(TO00)
Timer input
(TI00) Channel n
Compare operation
(5) Input pulse interval measurement
Counting is started by the valid edge of a pulse signal input to a timer input pin (TI0n). The count value of the timer
is captured at the valid edge of the next pulse. In this way, the interval of the input pulse can be measured.
Edge detection
Timer input
(TI0n)
Capture
xxH
00H
Start
Channel n
Capture operation
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(6) Measurement of high-/low-level width of input signal
Counting is started by a single edge of the signal input to the timer input pin (TI0n), and the count value is captured
at the other edge. In this way, the high-level or low-level width of the input signal can be measured.
Edge detection
Timer input
(TI0n)
Capture
xxH
00H
Start
Channel n
Capture operation
(7) Delay counter
Counting is started at the valid edge of the signal input to the timer input pin (TI0n), and an interrupt is generated
after any delay period.
Edge detection
Timer input
(TI0n) Channel n
Compare operation Interrupt signal
(INTTM0n)
Start
Remark n: Channel number (n = 0 to 7)
6.1.2 Simultaneous channel operation function
By using the combination of a master channel (a reference timer mainly controlling the cycle) and slave channels
(timers operating according to the master channel), channels can be used for the following purposes.
(1) One-shot pulse output
Two channels are used as a set to generate a one-shot pulse with a specified output timing and a specified pulse
width.
Timer output
(TO0p)
Interrupt signal (INTTM0n)
Edge detection
Timer input
(TI0n)
Toggle
(Master)
Output
timing
Pulse width
Start
(Master)
Toggle
(Slave)
Channel n (master)
Channel p (slave)
Compare operation
Compare operation
(2) PWM (Pulse Width Modulation) output
Two channels are used as a set to generate a pulse with a specified period and a specified duty factor.
Operation clock
Duty
Cycle
Compare operation
Compare operation
Channel n (master)
Channel p (slave)
Timer output
(TO0p)
Interrupt signal (INTTM0n)
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(3) Multiple PWM (Pulse Width Modulation) output
By extending the PWM function and using one master channel and two or more slave channels, up to three types
of PWM signals that have a specific period and a specified duty factor can be generated.
Duty
Cycle
Cycle
Interrupt signal (INTTM0n)
Duty
Channel n (master)
Channel p (slave)
Channel q (slave)
Operation clock Compare operation
Compare operation
Compare operation
Timer output
(TO0p)
Timer output
(TO0q)
Caution The rules apply when using multiple channels simultaneously.
For details about the rules of simultaneous channel operation function, see 6.4.1 Basic Rules of
Simultaneous Channel Operation Function.
Remark n: Channel number (n = 0 to 7)
p, q: Slave channel number (n < p < q ≤ 7)
6.1.3 8-bit timer operation function (channels 1 and 3 only)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-
bit timer channels. This function can only be used for channels 1 and 3.
Caution There are several rules for using 8-bit timer operation function.
For details, see 6.4.2 Basic rules of 8-bit timer operation function (channels 1 and 3 only).
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6.2 Configuration of Ti mer Array Unit
Timer array unit includes the following hardware.
Table 6-1. Configuration of Timer Array Unit
Item Configuration
Timer/counter Timer/counter register 0n (TCR0n)
Register Timer data register 0n (TDR0n)
Timer input TI00 to TI07
Timer output TO00 to TO07 pins, output controller
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Timer clock select register 0 (TPS0)
• Timer channel enable status register 0 (TE0)
• Timer channel start register 0 (TS0)
• Timer channel stop register 0 (TT0)
• Timer input select register 0 (TIS0)
• Timer output enable register 0 (TOE0)
• Timer output register 0 (TO0)
• Timer output level register 0 (TOL0)
• Timer output mode register 0 (TOM0)
Control registers
<Registers of each channel>
• Timer mode register 0n (TMR0n)
• Timer status register 0n (TSR0n)
• Noise filter enable register 1 (NFEN1)
• Port mode control register 0, 1, 4 (PMC0, PMC1, PMC4)
• Port mode register 0, 1, 3, 4 (PM0, PM1, PM3, PM4)
• Port register (P0, P1, P3, P4)
Remark n: Channel number (n = 0 to 7)
Alternate port for timer I/O of the timer array unit channels varies depending on products.
Table 6-2. Timer I/O Pins in the Products
Timer array unit channel 30-pin products 20, 24-pin products
Channel 0 P00/TI00, P01/TO00 P13/TI00/TO00
Channel 1 P16/TI01/TO01 P14/TI01/TO01
Channel 2 P17/TI02/TO02 (P15/TI02/TO02) P41/TI02/TO02 (P122/TI02)
Channel 3 P31/TI03/TO03 (P14/TI03/TO03) P42/TI03/TO03 (P121/TI03)
Channel 4 (P13/TI04/TO04) ×
Channel 5 (P12/TI05/TO05) ×
Channel 6 (P11/TI06/TO06) ×
Channel 7 (P10/TI07/TO07) ×
Remarks 1. If a pin is to be used for both timer input and timer output, it can be used only for timer input or timer output.
2. ×: The channel is not available
3. The pin names in parentheses are for PIOR0 = 1 in 30-pin products or PIOR2 = 1 in 24-, 20-pin products.
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Figures 6-1 to 6-3 show the block diagrams of the timer array unit.
Figure 6-1. Entire Configuration of Timer Array Unit (20-, and 24-pin products)
2 2 4 4
Timer clock select register 0 (TPS0)
PRS013 PRS003PRS012 PRS011 PRS010 PRS002 PRS001 PRS000PRS031 PRS030 PRS021 PRS020
Prescaler
fCLK/20 - fCLK/215
fCLK/21, fCLK/22,
fCLK/24,fCLK/26
fCLK/28, fCLK/210,
fCLK/212,fCLK/214
Selector Selector
SelectorSelector
Peripheral enable
register 0
(PER0)
fCLK
TAU0EN
TI00
TI02
TI03
Channel 0
Channel 1
Channel 2
Channel 3
Slave/master controller
Slave/master controller
Timer input select
register 0 (TIS0)
TIS0TIS1
Selector
fIL
TI01
INTTM00
(Timer interrupt)
TO00
TO01
TO02
TO03
INTTM02
INTTM03
INTTM01
INTTM03H
INTTM01H
CK03
CK02
CK01
CK00
Remark fIL: Low-speed on-chip oscillator clock frequency
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Figure 6-2. Entire Configuration of Timer Array Unit (30-pin products)
(TO04)
(TO05)
(TO06)
(TO07)
TO03
TO01
TI00
TI01
TI02
TO00
TO02
INTTM02
INTTM03
INTTM04
INTTM05
INTTM06
INTTM07
INTTM01
INTTM03H
INTTM01H
2 2 4 4
f
CLK
f
CLK
/2
0
- f
CLK
/2
15
TAU0EN
f
CLK
/2
1
, f
CLK
/2
2
,
f
CLK
/2
4
,f
CLK
/2
6
,
f
CLK
/2
8
, f
CLK
/2
10
,
f
CLK
/2
12
,f
CLK
/2
14
,
PRS013 PRS003PRS012 PRS011 PRS010 PRS002 PRS001 PRS000PRS031 PRS030 PRS021 PRS020
CK03
CK02
CK01
CK00
TI03
(TI04)
(TI06)
(TI07)
TIS2 TIS1 TIS0
f
IL
(TI05)
Timer clock select register 0 (TPS0)
Prescaler
Selector Selector
Slave/master controller
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
Channel 6
Channel 7
Slave/master controller
SelectorSelector
Peripheral enable
register 0
(PER0)
INTTM00
(Timer interrupt)
Selector
Timer input select
register 0 (TIS0)
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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Figure 6-3. Internal Block D i agram of Channel of Timer Array Un it
(a) Channel 0, 2, 4, 6
PMxx
CKS0n CCS0n MAS
TER0n STS0n2STS0n1 STS0n0 MD0n2CIS0n1CIS0n0 MD0n3 MD0n1 MD0n0
OVF
0n
CK00
CK01
fMCK
f
TCLK
Interrupt
controller
Output
controller
Output latch
(Pxx)
INTTM0n
(Timer interrupt)
TO00,
TO02,
(TO04),
(TO06)
Timer status
register 0n (TSR0n)
Overflow
Timer data register 0n (TDR0n)
Timer counter register 0n (TCR0n)
Timer mode register 0n (TMR0n)
Channel n
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
TI0n
Master channel
Note
Note n = 0, 2, 4, 6 only.
Remarks 1. n = 0, 2, 4, or 6
2. Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
(b) Channel 1 for 20-pin and 24-pin product
TO01
PM14
CKS01 CCS01 SPLIT
01 STS012STS011STS010 MD012CIS011CIS010 MD013 MD011MD010
OVF
01
INTTM01
(Timer interrupt)
CK00
CK01
fMCK
f
TCLK
CK02
CK03
INTTM01H
(Timer interrupt)
Interrupt
controller
Output
controller
Output latch
(P14)
Timer status
register 01 (TSR01)
Overflow
Timer data register 01 (TDR01)
Timer counter register 01 (TCR01)
Timer mode register 01 (TMR01)
Channel 1
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Slave channel
8-bit timer
controller
Mode
selection
Interrupt
controller
TIS1 TIS0
fIL
TI01
Timer input select
register 0 (TIS0)
Selector
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(c) Channel 1 for 30-pin product
TO01
CKS01 CCS01 SPLIT
01 STS012STS011 STS010 MD012CIS011CIS010 MD013 MD011 MD010
OVF
01
INTTM01
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
CK02
CK03
INTTM01H
(Timer interrupt)
TI01
PM16
Slave/master
controller
Trigger signal to master channel
Clock signal to master channel
Interrupt signal to master channel
Slave channel
Operating
clock selection
Interrupt
controller
Output
controller
Output latch
(P16)
Timer status
register 01 (TSR01)
Overflow
Timer data register 01 (TDR01)
Timer counter register 01 (TCR01)
Timer mode register 01 (TMR01)
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Edge
detection
Mode
selection
8-bit timer
controller Interrupt
controller
Channel 1
(d) Channel 3
TO03
CKS03 CCS03 SPLIT
03 STS032STS031 STS030 MD032CIS031CIS030 MD033 MD031 MD030
OVF
03
INTTM03
(Timer interrupt)
CK00
CK01 f
MCK f
TCLK
CK02
CK03
INTTM03H
(Timer interrupt)
TI03
PMxx
Slave/master
controller
Trigger signal to master channel
Clock signal to master channel
Interrupt signal to master channel
Slave channel
Operating
clock selection
Interrupt
controller
Output
controller
Output latch
(Pxx)
Timer status
register 03 (TSR03)
Overflow
Timer data register 03 (TDR03)
Timer counter register 03 (TCR03)
Timer mode register 03 (TMR03)
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Edge
detection
Mode
selection
8-bit timer
controller Interrupt
controller
Channel 3
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
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(e) Channel 5 for 30-Pin product
TO05
PM12
CKS05 CCS05STS052STS051 STS050 MD052CIS051CIS050 MD053 MD051 MD050
OVF
05
INTTM05
(Timer interrupt)
CK00
CK01
f
MCK
f
TCLK
Interrupt
controller
Output
controller
Output latch
(P12)
Timer status
register 05 (TSR05)
Overflow
Timer data register 05 (TDR05)
Timer counter register 05 (TCR05)
Timer mode register 05 (TMR05)
Channel 5
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
Slave channel
TIS1 TIS0
f
IL
(TI05)
Timer input select
register 0 (TIS0)
TIS2
Selector
(f) Channel 7 for 30-Pin product
PM10
CKS07 CCS07 STS072STS071 STS070 MD072CIS071CIS070 MD073 MD071 MD070
OVF
07
CK00
CK01
f
MCK
f
TCLK
Interrupt
controller
Output
controller
Output latch
(P10)
INTTM07
(Timer interrupt)
(TO07)
Timer status
register 07 (TSR07)
Overflow
Timer data register 07 (TDR07)
Timer counter register 07 (TCR07)
Timer mode register 07 (TMR07)
Channel 7
Timer controller
Trigger
selection Count clock
selection
Mode
selection
Slave/master
controller
Slave/master
controller
Edge
detection
Operating
clock selection
Trigger signal to slave channel
Clock signal to slave channel
Interrupt signal to slave channel
(TI07)
Master channel
STS072
Remark Functions in parentheses in the above figure can be assigned via settings in the peripheral I/O redirection
register (PIOR).
(1) Timer/counter register 0n (TCR0n)
The TCR0n register is a 16-bit read-only register and is used to count clocks.
The value of this counter is incremented or decremented in synchronization with the rising edge of a count clock.
Whether the counter is incremented or decremented depends on the operation mode that is selected by the MD0n3
to MD0n0 bits of timer mode register 0n (TMR0n) (refer to 6.3 (3) Timer mode register 0n (TMR0n)).
Figure 6-4. Format of Timer/Counter Register 0n (TCR0n)
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Address: F0180H, F0181H (TCR00) to F0186H, F0187H (TCR03) After reset: FFFFH R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCR0n
Remark n: Channel number (n = 0 to 7)
The count value can be read by reading timer counter register 0n (TCR0n).
The count value is set to FFFFH in the following cases.
• When the reset signal is generated
• When the TAU0EN bit of peripheral enable register 0 (PER0) is cleared
• When counting of the slave channel has been completed in the PWM output mode
• When counting of the slave channel has been completed in the delay count mode
• When counting of the master/slave channel has been completed in the one-shot pulse output mode
• When counting of the slave channel has been completed in the multiple PWM output mode
The count value is cleared to 0000H in the following cases.
• When the start trigger is input in the capture mode
• When capturing has been completed in the capture mode
Caution The count value is not captured to timer data register 0n (TDR0n) even when the TCR0n register
is read.
The TCR0n register read value differs as follows according to operation mode changes and the operating status.
F0181H (TCR00) F0180H (TCR00)
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Table 6-3. Timer/counter Register 0n (TCR0n) Read Value in Various Operation Modes
Timer/counter register 0n (TCR0n) Read ValueNote Operation Mode Count Mode
Value if the
operation mode
was changed after
releasing reset
Value if the count
operation paused
(TT0n = 1)
Value if the
operation mode was
changed after count
operation paused
(TT0n = 1)
Value when waiting
for a start trigger
after one count
Interval timer
mode
Count down FFFFH Value if stop Undefined −
Capture mode Count up 0000H Value if stop Undefined −
Event counter
mode
Count down FFFFH Value if stop Undefined −
One-count mode Count down FFFFH Value if stop Undefined FFFFH
Capture & one-
count mode
Count up 0000H Value if stop Undefined Capture value of
TDR0n register + 1
Note This indicates the value read from the TCR0n register when channel n has stopped operating as a timer (TE0n = 0)
and has been enabled to operate as a counter (TS0n = 1). The read value is held in the TCR0n register until the count
operation starts.
Remark n: Channel number (n = 0 to 7)
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(2) Timer data register 0n (TDR0n)
This is a 16-bit register from which a capture function and a compare function can be selected.
The capture or compare function can be switched by selecting an operation mode by using the MD0n3 to MD0n0
bits of timer mode register 0n (TMR0n).
The value of the TDR0n register can be changed at any time.
This register can be read or written in 16-bit units.
In addition, for the TDR01, TDR03 registers, while in the 8-bit timer mode (when the SPLIT bit of timer mode
register m1, m3 (TMR01, TMR03) is 1), it is possible to read and write the data in 8-bit units, with TDR01H,
TDR03H used as the higher 8 bits, and TDR01L, TDR03L used as the lower 8 bits.
Reset signal generation clears this register to 0000H.
Figure 6-5. Format of Timer Data Register 0n (TDR0n) (n = 0, 2, 4 to 7)
Address: FFF18H, FFF19H (TDR00), FFF64H, FFF65H (TDR02), After reset: 0000H R/W
FFF68H, FFF69H (TDR04) to FFF6EH, FFF6FH (TDR07)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR0n
Figure 6-6. Format of Timer Data Register 01, 03 (TDR01, TDR03)
Address: FFF1AH, FFF1BH (TDR01), FFF66H, FFF67H (TDR03) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TDR0n
(i) When timer data register 0n (TDR0n) is used as compare register
Counting down is started from the value set to the TDR0n register. When the count value reaches 0000H, an
interrupt signal (INTTM0n) is generated. The TDR0n register holds its value until it is rewritten.
Caution The TDR0n register does not perform a capture operation even if a capture trigger is input,
when it is set to the compare function.
(ii) When timer data register 0n (TDR0n) is used as capture register
The count value of timer/counter register 0n (TCR0n) is captured to the TDR0n register when the capture
trigger is input.
A valid edge of the TI0n pin can be selected as the capture trigger. This selection is made by timer mode
register 0n (TMR0n).
Remark n: Channel number (n = 0 to 7)
FFF19H (TDR00) FFF18H (TDR00)
FFF1BH (TDR01) FFF1AH (TDR01)
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6.3 Registers Controlling Timer Array Unit
Timer array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Timer clock select register 0 (TPS0)
• Timer mode register 0n (TMR0n)
• Timer status register 0n (TSR0n)
• Timer channel enable status register 0 (TE0)
• Timer channel start register 0 (TS0)
• Timer channel stop register 0 (TT0)
• Timer input select register 0 (TIS0)
• Timer output enable register 0 (TOE0)
• Timer output register 0 (TO0)
• Timer output level register 0 (TOL0)
• Timer output mode register 0 (TOM0)
• Noise filter enable register 1 (NFEN1)
• Port mode control register 0, 1, 4 (PMC0, PMC1, PMC4)
• Port mode register 0, 1, 3, 4 (PM0, PM1, PM3, PM4)
• Port register 0, 1, 3, 4 (P0, P1, P3, P4)
Remark n: Channel number (n = 0 to 7)
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6.3.1 Peripheral enable register 0 (PER0)
This registers is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When the timer array unit is used, be sure to set bit 0 (TAU0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-7. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
TAU0EN Control of timer array unit input clock
0 Stops supply of input clock.
• SFR used by the timer array unit cannot be written.
• The timer array unit is in the reset status.
1 Supplies input clock.
• SFR used by the timer array unit can be read/written.
Cautions 1. When setting the timer array unit, be sure to set the TAU0EN bit to 1 first. If TAU0EN = 0,
writing to a control register of timer array unit is ignored, and all read values are default
values (except for the timer input select register 0 (TIS0), input switch control register
(ISC), noise filter enable register 1 (NFEN1), port mode registers 0, 1, 3, 4 (PM0, PM1,
PM3, PM4), port registers 0, 1, 3, 4 (P0, P1, P3, P4), and Port mod e control register 0, 1, 4
(PMC0, PMC1, PMC4)).
2. Be sure to clear undefined bits to 0.
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6.3.2 Timer clock select register 0 (TPS0)
The TPS0 register is a 16-bit register that is used to select four types of operation clocks (CK00 to CK03) that are
commonly supplied to each channel from external prescaler.
Bit 7 to 4 : CK01
Bit 3 to 0 : CK00
Bit 9, 8 : CK02 (Channel 1, 3)
Bit 13 to 12 : CK03 (Channel 1, 3)
Rewriting of the TPS0 register during timer operation is possible only in the following cases.
If the PRS000 to PRS003 bits can be rewritten (n = 0 to 7):
All channels for which CK00 is selected as the operation clock (CKS0n1, CKS0n0 = 0, 0) are stopped (TE0n = 0).
If the PRS010 to PRS013 bits can be rewritten (n = 0 to 7):
All channels for which CK01 is selected as the operation clock (CKS0n1, CKS0n0 = 0, 1) are stopped (TE0n = 0).
If the PRS020 and PRS021 bits can be rewritten (n = 1, 3):
All channels for which CK02 is selected as the operation clock (CKS0n1, CKS0n0 = 1, 0) are stopped (TE0n = 0).
If the PRS030 and PRS031 bits can be rewritten (n = 1, 3):
All channels for which CK03 is selected as the operation clock (CKS0n1, CKS0n0 = 1, 1) are stopped (TE0n = 0).
The TPS0 register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
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Figure 6-8. Format of Timer Clock Select register 0 (TPS0)
Address: F01B6H, F01B7H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TPS0 0 0
PRS
031
PRS
030
0 0
PRS
021
PRS
020
PRS
013
PRS
012
PRS
011
PRS
010
PRS
003
PRS
002
PRS
001
PRS
000
Selection of operation clock (CK0k) Note(k = 0, 1) PRS
0k3
PRS
0k2
PRS
0k1
PRS
0k0 fCLK =
2 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
20 MHz
fCLK =
24 MHz
0 0 0 0 fCLK 2 MHz 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz
0 0 0 1 fCLK/2 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz
0 0 1 0 fCLK/22 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz
0 0 1 1 fCLK/23 250 kHz 500 kHz 1 MHz 2 MHz 2.5 MHz 3 MHz
0 1 0 0 fCLK/24 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz
0 1 0 1 fCLK/25 62.5 kHz 125 kHz 250 kHz 500 kHz 625 kHz 750 kHz
0 1 1 0 fCLK/26 31.25 kHz 62.5 kHz 125 kHz 250 kHz 312.5 kHz 375 kHz
0 1 1 1 fCLK/27 15.62 kHz 31.2 kHz 62.5 kHz 125 kHz 156.2 kHz 187.5 kHz
1 0 0 0 fCLK/28 7.81 kHz 15.6 kHz 31.2 kHz 62.5 kHz 78.1 kHz 93.75 kHz
1 0 0 1 fCLK/29 3.91 kHz 7.8 kHz 15.6 kHz 31.2 kHz 39.1 kHz 46.88 kHz
1 0 1 0 fCLK/210 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz
1 0 1 1 fCLK/211 976 Hz 1.95 kHz 3.9 kHz 7.8 kHz 9.76 kHz 11.72 kHz
1 1 0 0 fCLK/212 488 Hz 0.97 kHz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz
1 1 0 1 fCLK/213 244 Hz 485 Hz 0.97 kHz 1.95 kHz 2.44 kHz 2.93 kHz
1 1 1 0 fCLK/214 122 Hz 242 Hz 485 Hz 0.97 kHz 1.22 kHz 1.47 kHz
1 1 1 1 fCLK/215 61 Hz 121 Hz 242 Hz 485 Hz 610 Hz 732 Hz
Selection of operation clock (CK02) Note PRS
021
PRS
020 f
CLK = 2 MHz fCLK = 4 MHz fCLK = 8 MHz fCLK = 16 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/2 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz
0 1 fCLK/22 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz
1 0 fCLK/24 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz
1 1 fCLK/26 31.25 kHz 62.5 kHz 125 kHz 250 kHz 312.5 kHz 375 kHz
Selection of operation clock (CK03) Note PRS
031
PRS
030 f
CLK = 2 MHz fCLK = 4 MHz fCLK = 8 MHz fCLK = 16 MHz fCLK = 20 MHz fCLK = 24 MHz
0 0 fCLK/28 7.81 kHz 15.6 kHz 31.2 kHz 62.4 kHz 78.1 kHz 93.75 kHz
0 1 fCLK/210 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz
1 0 fCLK/212 488 Hz 976 Hz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz
1 1 fCLK/214 122 Hz 244 Hz 488 Hz 976 Hz 1.22 kHz 1.47 kHz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value),
stop timer array unit (TT0 = 00FFH).
Cautions 1. Be sure to clear bits 15, 14, 11, 10 to “0”.
2. If fCLK (undi vided) is selected as the operation clo ck (CKmk) and TDRnm is set to 0000H (n =
0 or 1, m = 0 to 7), interrupt requests output from timer arra y units are not detected.
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Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. The above selected clock , but a signal which becomes high level for one period of fCLK from its rising
edge (m = 2 to 15). For details, see 6.5.1 Count clock (fTCLK).
By using channels 1 and 3 in the 8-bit timer mode and specifying CK02 or CK03 as the operation clock, the interval
times shown in Table 6-4 can be achieved by using the interval timer function.
Table 6-4. Interval Times Available for Operatio n Clock CKS02 or CKS03
Interval time (fCLK = 20 MHz)Note
Clock
10
μ
s 100
μ
s 1 ms 10 ms
fCLK/2 √ − − −
fCLK/22 √ − − −
fCLK/24 √ √ − −
CK02
fCLK/26 − √ √ −
fCLK/28 − √ √ −
fCLK/210 − − √ −
fCLK/212 − − − √
CK03
fCLK/214 − − − −
Note The margin is within 4 %.
Remarks 1. fCLK: CPU/peripheral hardware clock frequency
2. For details of asignal of fCLK/2n selected with the TPSm register, see 6.5.1 Count clock (fTCLK).
6.3.3 Timer mode register 0n (TMR0n)
The TMR0n register sets an operation mode of channel n. This register is used to select the operation clock (fMCK),
select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the
start trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval,
capture, event counter, one-count, or capture and one-count).
Rewriting the TMR0n register is prohibited when the register is in operation (when TE0n = 1). However, bits 7 and
6 (CIS0n1, CIS0n0) can be rewritten even while the register is operating with some functions (when TE0n = 1) (for
details, see 6.7 Independent Channel Operation Function of Timer Array Unit and 6.8 Simultaneous
Channel Operation Function of Timer Array Unit).
The TMR0n register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution The bits mounted depend on the channels in the bit 11 of TMR0n register.
TMR02, TMR04, TMR06: MASTER0n bit (n = 2, 4, 6)
TMR01, TMR03: SPLIT0n bit (n = 1, 3)
TMR00, TMR05, TMR07: F i xed to 0
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Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (1/4)
Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 2, 4, 6)
CKS
0n1
CKS
0n0
0 CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 1, 3)
CKS
0n1
CKS
0n0
0 CCS
0n
SPLIT
0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 0, 5, 7)
CKS
0n1
CKS
0n0
0 CCS
0n
0Note
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
CKS
0n1
CKS
0n0
Selection of operation clock (fMCK) of channel n
0 0 Operation clock CK00 set by timer clock select register 0 (TPS0)
0 1 Operation clock CK02 set by timer clock select register 0 (TPS0)
1 0 Operation clock CK01 set by timer clock select register 0 (TPS0)
1 1 Operation clock CK03 set by timer clock select register 0 (TPS0)
Operation clock (fMCK ) is used by the edge detector. A count clock (fTCLK) and a sampling clock are generated
depending on the setting of the CCS0n bit.
The operation clocks CK02 and CK03 can only be selected for channels 1 and 3.
CCS
0n
Selection of count clock (fTCLK) of channel n
0 Operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits
1 Valid edge of input signal input from the TI0n pin
In channel 1 for 20-, 24-pin product and channel 5 for 30-pin product, Valid edge of input signal selected by
TIS0
Count clock (fTCLK) is used for the timer/counter, output controller, and interrupt controller.
Note Bit 11 is fixed at 0 of read only, write is ignored.
Cautions 1. Be sure to clear bits 13, 5, and 4 to “0”.
2. The timer array unit must be stopped (TT0 = 00FFH) if the clock selected for fCLK is changed
(by changing the value of the system clock control register (CKC)), even if the op erating clock
specified by using the CKS0n0 and CKS0n1 bits (fMCK) or the valid edge of the signal input
from the TI0n pin is selected as the count clock (fTCLK).
Remark n: Channel number (n = 0 to 7)
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Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (2/4)
Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n =2, 4, 6)
CKS
0n1
CKS
0n0
0 CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 1, 3)
CKS
0n1
CKS
0n0
0 CCS
0n
SPLIT
0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 0, 5, 7)
CKS
0n1
CKS
0n0
0 CCS
0n
0Note
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
(Bit 11 of TMR0n (n = 2, 4, 6))
MAS
TER
0n
Selection between using channel n independently or
simultaneously with another channel (as a slave or master)
0 Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.
1 Operates as master channel in simultaneous channel operation function.
Only the 2, 4, 6 channel can be set as a master channel (MASTER0n = 1).
Be sure to use channel 0, 5, 7 are fixed to 0 (Regardless of the bit setting, channel 0 operates as master, because it
is the highest channel).
Clear the MASTER0n bit to 0 for a channel that is used with the independent channel operation function.
(Bit 11 of TMR0n (n = 1, 3))
SPLI
T0n
Selection of 8 or 16-bit timer operation for channels 1 and 3
0 Operates as 16-bit timer.
(Operates in independent channel operation function or as slave channel in simultaneous channel operation
function.)
1 Operates as 8-bit timer.
STS
0n2
STS
0n1
STS
0n0
Setting of start trigger or capture trigger of channel n
0 0 0 Only software trigger start is valid (other trigger sources are unselected).
0 0 1 Valid edge of the TI0n pin input is used as both the start trigger and capture trigger.
0 1 0 Both the edges of the TI0n pin input are used as a start trigger and a capture trigger.
1 0 0
Interrupt signal of the master channel is used (when the channel is used as a slave channel
with the simultaneous channel operation function).
Other than above Setting prohibited
Note Bit 11 is fixed at 0 of read only, write is ignored.
Remark n: Channel number (n = 0 to 7)
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Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (3/4)
Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 2, 4, 6)
CKS
0n1
CKS
0n0
0 CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 1, 3)
CKS
0n1
CKS
0n0
0 CCS
0n
SPLIT
0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 0, 5, 7)
CKS
0n1
CKS
0n0
0 CCS
0n
0Note
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
CIS
0n1
CIS
0n0
Selection of TI0n pin input valid edge
0 0 Falling edge
0 1 Rising edge
1 0
Both edges (when low-level width is measured)
Start trigger: Falling edge, Capture trigger: Rising edge
1 1
Both edges (when high-level width is measured)
Start trigger: Rising edge, Capture trigger: Falling edge
If both the edges are specified when the value of the STS0n2 to STS0n0 bits is other than 010B, set the CIS0n1 to
CIS0n0 bits to 10B.
Note Bit 11 is fixed at 0 of read only, write is ignored.
Remark n: Channel number (n = 0 to 7)
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Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (4/4)
Address: : F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 2, 4, 6)
CKS
0n1
CKS
0n0
0 CCS
0n
MAST
ER0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 1, 3)
CKS
0n1
CKS
0n0
0 CCS
0n
SPLIT
0n
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n
(n = 0, 5, 7)
CKS
0n1
CKS
0n0
0 CCS
0n
0 Note
STS
0n2
STS
0n1
STS
0n0
CIS
0n1
CIS
0n0
0 0
MD
0n3
MD
0n2
MD
0n1
MD
0n0
MD
0n3
MD
0n2
MD
0n1
Setting of operation mode
of channel n
Corresponding function
Count operation of TCR
0 0 0 Interval timer mode Interval timer / Square wave output /
Divider function / PWM output
(master)
Down count
0 1 0 Capture mode Input pulse interval measurement Up count
0 1 1 Event counter mode External event counter Down count
1 0 0 One-count mode Delay counter / One-shot pulse
output / PWM output (slave)
Down count
1 1 0
Capture & one-count
mode
Measurement of high-/low-level
width of input signal
Up count
Other than above Setting prohibited
The operation of MD0n0 bit changes depending on the operation of each mode (refer to the table bellow)
Operation mode
(Value set by the MD0n3 to MD0n1 bits
(see table above))
MD
0n0
Setting of starting counting and interrupt
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
• Interval timer mode
(0, 0, 0)
• Capture mode
(0, 1, 0)
1 Timer interrupt is generated when counting is started
(timer output also changes).
• Event counter mode
(0, 1, 1)
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
0 Start trigger is invalid during counting operation.
At that time, interrupt is not generated, either.
• One-count mode
Note 2
(1, 0, 0)
1 Start trigger is valid during counting operationNote 3.
At that time, interrupt is also generated.
• Capture & one-count mode
(1, 1, 0)
0 Timer interrupt is not generated when counting is started
(timer output does not change, either).
Start trigger is invalid during counting operation.
At that time interrupt is not generated, either.
Other than above Setting prohibited
<R>
<R>
<R>
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Notes 1. Bit 11 is fixed at 0 of read only, write is ignored.
2. In one-count mode, interrupt output (INTTM0n) when starting a count operation and TO0n output are not
controlled.
3. If the start trigger (TS0n = 1) is issued during operation, the counter is initialaized, and recounting is
started (interrupt request is not generated).
Remark n: Channel number (n = 0 to 7)
6.3.4 Timer status register 0n (TSR0n)
The TSR0n register indicates the overflow status of the counter of channel n.
The TSR0n register is valid only in the capture mode (MD0n3 to MD0n1 = 010B) and capture & one-count mode
(MD0n3 to MD0n1 = 110B). It will not be set in any other mode. See Table 6-4 for the operation of the OVF bit in
each operation mode and set/clear conditions.
The TSR0n register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TSR0n register can be set with an 8-bit memory manipulation instruction with TSR0nL.
Reset signal generation clears this register to 0000H.
Figure 6-10. Format of Timer Status Register 0n (T SR0n)
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TSR0n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OVF
OVF Counter overflow status of channel n
0 Overflow does not occur.
1 Overflow occurs.
When OVF = 1, this flag is cleared (OVF = 0) when the next value is captured without overflow.
Remark n: Channel number (n = 0 to 7)
Table 6-5. OVF Bit Operation and Set/Clear Conditions in Each Operation Mode
Timer operation mode OVF bit Set/clear conditions
clear When no overflow has occurred upon capturing • Capture mode
• Capture & one-count mode set When an overflow has occurred upon capturing
clear • Interval timer mode
• Event counter mode
• One-count mode set
− (Use prohibited)
Remark The OVF bit does not change immediately after the counter has overflowed, but changes upon the
subsequent capture.
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6.3.5 Timer channel enable status register 0 (TE0)
The TE0 register is used to enable or stop the timer operation of each channel.
Each bit of the TE0 register corresponds to each bit of the timer channel start register 0 (TS0) and the timer
channel stop register 0 (TT0). When a bit of the TSm register is set to 1, the corresponding bit of this register is set
to 1. When a bit of the TT0 register is set to 1, the corresponding bit of this register is cleared to 0.
The TE0 register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TE0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TE0L.
Reset signal generation clears this register to 0000H.
Figure 6-11. Format o f Timer Channel Enable Status register 0 (TE0)
Address: F01B0H, F01B1H After reset: 0000H R
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE0 0 0 0 0 TEH03 0 TEH01 0 0 0 0 0 TE03 TE02 TE01 TE00
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TE0 0 0 0 0 TEH03 0 TEH01 0 TE07 TE06 TE05 TE04 TE03 TE02 TE01 TE00
TEH
03
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit
timer mode
0 Operation is stopped.
1 Operation is enabled.
TEH
01
Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit
timer mode
0 Operation is stopped.
1 Operation is enabled.
TE0n Indication of operation enable/stop status of channel n
0 Operation is stopped.
1 Operation is enabled.
This bit displays whether operation of the lower 8-bit timer for TE01, TE03 is enabled or stopped when channel 1, 3
is in the 8-bit timer mode.
Remark n: Channel number (n = 0 to 7)
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6.3.6 Timer channel start register 0 (TS0)
The TS0 register is a trigger register that is used to initialize timer/counter register 0n (TCR0n) and start the
counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is set to
1. The TS0n, TSH01, TSH03 bits are immediately cleared when operation is enabled (TE0n, TEH01, TEH03 = 1),
because they are trigger bits.
The TS0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TS0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TS0L.
Reset signal generation clears this register to 0000H.
Figure 6-12. Format of Timer Channel Start register 0 (TS0)
Address: F01B2H, F01B3H After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS0 0 0 0 0 TSH03 0 TSH01 0 0 0 0 0 TS03 TS02 TS01 TS00
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TS0 0 0 0 0 TSH03 0 TSH01 0 TS07 TS06 TS05 TS04 TS03 TS02 TS01 TS00
TSH
03
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
0 No trigger operation
1 The TEH03 bit is set to 1 and the count operation becomes enabled.
The TCR03 register count operation start in the interval timer mode in the count operation enabled state
(see Table 6-6).
TSH
01
Trigger to enable operation (start operation) of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
0 No trigger operation
1 The TEH01 bit is set to 1 and the count operation becomes enabled.
The TCR01 register count operation start in the interval timer mode in the count operation enabled state
(see Table 6-6).
TS0n Operation enable (start) trigger of channel n
0 No trigger operation
1 The TE0n bit is set to 1 and the count operation becomes enabled.
The TCR0n register count operation start in the count operation enabled state varies depending on each
operation mode (see Table 6-6).
This bit is the trigger to enable operation (start operation) of the lower 8-bit timer for TS01 and TS03 when
channel 1 or 3 is in the 8-bit timer mode.
Cautions 1. Be sure to clear undifined bits to “0”.
2. When switching from a function that does not use TI0n pin input to one that does, the
following wait period is required from when timer mode register 0n (TMR0n) is set until the
TS0n (TSH01, TSH03) bit is set to 1.
When the TI0n pin noise filter is enab led (TNFEN = 1): Four cycles of the operation clock (fMCK)
When the TI0n pin noise filter is di sab led (TNFEN = 0): Two cycles of the operation clock (fMCK)
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Remarks 1. When the TS0 register is read, 0 is always read.
2. n: Channel number (n = 0 to 7)
6.3.7 Timer channel stop register 0 (TT0)
The TT0 register is a trigger register that is used to stop the counting operation of each channel.
When a bit of this register is set to 1, the corresponding bit of timer channel enable status register 0 (TE0) is
cleared to 0. The TT0n, TTH01, TTH03 bits are immediately cleared when operation is stopped (TE0n, TTH01,
TTH03 = 0), because they are trigger bits.
The TT0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TT0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TT0L.
Reset signal generation clears this register to 0000H.
Figure 6-13. Format of Timer Channel Stop register 0 (TT0)
Address: F01B4H, F01B5H After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TT0 0 0 0 0 TTH03 0 TTH01 0 0 0 0 0 TT03 TT02 TT01 TT00
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TT0 0 0 0 0 TTH03 0 TTH01 0 TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
TTH
03
Trigger to stop operation of the higher 8-bit timer when channel 3 is in the 8-bit timer mode
0 No trigger operation
1 TEH03 is cleared to 0. Operation is stopped (stop trigger is generated).
TTH
01
Trigger to stop operation of the higher 8-bit timer when channel 1 is in the 8-bit timer mode
0 No trigger operation
1 TEH01 is cleared to 0. Operation is stopped (stop trigger is generated).
TT0n Operation stop trigger of channel n
0 No trigger operation
1 TE0n is cleared to 0. Operation is stopped (stop trigger is generated).
This bit is the trigger to stop operation of the lower 8-bit timer for TT01 and TT03 when channel 1 or 3 is in
the 8-bit timer mode.
Caution Be sure to clear undifined bits to “0”.
Remarks 1. When the TT0 register is read, 0 is always read.
2. n: Channel number (n = 0 to 7)
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6.3.8 Timer input select register 0 (TIS0)
The TIS0 register is used to select the channel 1 for 20- or 24-pin product, channel 5 for 30-pin product timer input.
The TIS0 register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-14. Format of Timer Input Select register 0 (TIS0)
Address: F0074H After reset: 00H R/W
20- and 24-pin products
Symbol 7 6 5 4 3 2 1 0
TIS0 0 0 0 0 0 0 TIS01 TIS00
TIS01 TIS00 Selection of timer input used with channel 1
× 0 Input signal of timer input pin (TI01)
0 1 Low-speed on-chip oscillator clock (fIL)
1 1 Setting prohibited
30-pin products
Symbol 7 6 5 4 3 2 1 0
TIS0 0 0 0 0 0 TIS2 TIS01 TIS00
TIS2 TIS01 TIS00 Selection of timer input used with channel 5
0
× × Input signal of timer input pin (TI05)
1 0 0 Low-speed on-chip oscillator clock (fIL)
Other than above Setting prohibited
×: don’t care
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6.3.9 Timer output enable register 0 (TOE0)
The TOE0 register is used to enable or disable timer output of each channel.
Channel n for which timer output has been enabled becomes unable to rewrite the value of the TO0n bit of timer
output register 0 (TO0) described later by software, and the value reflecting the setting of the timer output function
through the count operation is output from the timer output pin (TO0n).
The TOE0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOE0 register can be set with a 1-bit or 8-bit memory manipulation instruction with TOE0L.
Reset signal generation clears this register to 0000H.
Figure 6-15. Format of Timer Output Enable register 0 (TOE0)
Address: F01BAH, F01BBH After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOE0 0 0 0 0 0 0 0 0 0 0 0 0
TOE
03
TOE
02
TOE
01
TOE
00
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOE0 0 0 0 0 0 0 0 0
TOE
07
TOE
06
TOE
05
TOE
04
TOE
03
TOE
02
TOE
01
TOE
00
TOE
0n
Timer output enable/disable of channel n
0 Diseble output of timer.
Without reflecting on TOmn bit timer operation, to fixed the output.
Writing to the TOmn bit is enabled.
1 Enable output of timer.
Reflected in the TOmn bit timer operation, to generate the output waveform.
Writing to the TOmn bit is disabled (writing is ignored).
Caution Be sure to clear undifined bits to “0”.
Remark n: Channel number (n = 0 to 7)
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6.3.10 Timer output register 0 (TO0)
The TO0 register is a buffer register of timer output of each channel.
The value of each bit in this register is output from the timer output pin (TO0n) of each channel.
The TO0n bit oh this register can be rewritten by software only when timer output is disabled (TOE0n = 0). When
timer output is enabled (TOE0n = 1), rewriting this register by software is ignored, and the value is changed only
by the timer operation.
To use the TO0n alternate pin as a port function pin, set the corresponding TO0n bit to 0.
The TO0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TO0 register can be set with an 8-bit memory manipulation instruction with TO0L.
Reset signal generation clears this register to 0000H.
Figure 6-16. Format of Timer Output register 0 (TO0)
Address: F01B8H, F01B9H After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO0 0 0 0 0 0 0 0 0 0 0 0 0 TO03 TO02 TO01 TO00
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TO0 0 0 0 0 0 0 0 0 TO07 TO06 TO05 TO04 TO03 TO02 TO01 TO00
TO0n Timer output of channel n
0 Timer output value is “0”.
1 Timer output value is “1”.
Caution Be sure to clear undefined bits to 0.
Remark n: Channel number (n = 0 to 7)
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6.3.11 Timer output level register 0 (TOL0)
The TOL0 register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer
output signal while the timer output is enabled (TOE0n = 1) in the Slave channel output mode (TOM0n = 1). In the
master channel output mode (TOM0n = 0), this register setting is invalid.
The TOL0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOL0 register can be set with an 8-bit memory manipulation instruction with TOL0L.
Reset signal generation clears this register to 0000H.
Figure 6-17. Format of Timer Output Level register 0 (TOL0)
Address: F01BCH, F01BDH After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOL0 0 0 0 0 0 0 0 0 0 0 0 0
TOL
03
TOL
02
TOL
01
0
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOL0 0 0 0 0 0 0 0 0
TOL
07
TOL
06
TOL
05
TOL
04
TOL
03
TOL
02
TOL
01
0
TOL
0n
Control of timer output level of channel n
0 Positive logic output (active-high)
1 Negative logic output (active-low)
Caution Be sure to clear undefined bits to 0.
Remarks 1. If the value of this register is rewritten during timer operation, the timer output logic is inverted when
the timer output signal changes next, instead of immediately after the register value is rewritten.
2. n: Channel number (n = 1 to 7)
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6.3.12 Timer output mode register 0 (TOM0)
The TOM0 register is used to control the timer output mode of each channel.
When a channel is used for the independent channel operation function, set the corresponding bit of the channel
to be used to 0.
When a channel is used for the simultaneous channel operation function (PWM output, one-shot pulse output, or
multiple PWM output), set the corresponding bit of the master channel to 0 and the corresponding bit of the slave
channel to 1.
The setting of each channel n by this register is reflected at the timing when the timer output signal is set or reset
while the timer output is enabled (TOE0n = 1).
The TOM0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOM0 register can be set with an 8-bit memory manipulation instruction with TOM0L.
Reset signal generation clears this register to 0000H.
Figure 6-18. Format of Timer Output Mode register 0 (TOM0)
Address: F01BEH, F01BFH After reset: 0000H R/W
20- and 24-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOM0 0 0 0 0 0 0 0 0 0 0 0 0
TOM
03
TOM
02
TOM
01
0
30-pin products
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOM0 0 0 0 0 0 0 0 0
TOM
07
TOM
06
TOM
05
TOM
04
TOM
03
TOM
02
TOM
01
0
TOM
0n
Control of timer output mode of channel n
0 Master channel output mode (to produce toggle output by timer interrupt request signal (INTTM0n))
1 Slave channel output mode (output is set by the timer interrupt request signal (INTTM0n) of the master
channel, and reset by the timer interrupt request signal (INTTM0p) of the slave channel)
Caution Be sure to clear undefined bits to 0.
Remark n: Channel number
n = 1 to 7 (n = 0, 2, 4, or 6 for master channel)
p: Slave channel number
n<p≤7
(For details of the relation between the master channel and slave channel, refer to 6.4.1 Basic Rules of
Simultaneous Channel Operation Function.)
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6.3.13 Noise filter enable register 1 (NFEN1)
The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (fMCK). When the noise filter is OFF, only synchronization is performed with the
CPU/peripheral hardware clock (fMCK). For details, see 6.5.1 (2) When valid edge of inpu t signal input from the
TI0n pin is selected (CCS0n = 1) and 6.5.2 Start timing of counter.
The NFEN1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 6-20. Format of No ise F ilter Enable Register 1 (NFEN1)
Address: F0071H After reset: 00H R/W
20- and 24-pin products
Symbol 7 6 5 4 3 2 1 0
NFEN1 0 0 0 0 TNFEN03 TNFEN02 TNFEN01 TNFEN00
30-pin products
Symbol 7 6 5 4 3 2 1 0
NFEN1 TNFEN07 TNFEN06 TNFEN05 TNFEN04 TNFEN03 TNFEN02 TNFEN01 TNFEN00
TNFEN0n Enable/disable using noise filter of TI0n pin input signal
0 Noise filter OFF
1 Noise filter ON
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6.3.14 Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or PM4)
These registers set input/output of ports 0, 1, 3, or 4 in 1-bit units.
When using the ports that shares the pin with the timer output (such as TI00/TO00/P13) for timer output, set the
port mode register (PMxx) bit, port register (Pxx) bit and port mode control register (PMCxx) bit corresponding to
each port to 0.
Example: When using P13/TI00/TO00 for timer output fot 20-, 24-pin product
Set the PMC13 bit of port mode control register 1 to 0.
Set the PM00 bit of port mode register 1 to 0.
Set the P00 bit of port register 1 to 0.
When using the ports (such as TI00/TO00/P13) to be shared with the timer output pin for timer input, set the port
mode register (PMxx) bit corresponding to each port to 1. Also set the port mode control register (PMCxx) bit
corresponding to each port to 0. At this time, the port register (Pxx) bit may be 0 or 1.
Example: When using P13/TO00/TI00 for timer input fot 20-, 24-pin product
Set the PMC13 bit of port mode control register 1 to 0.
Set the PM00 bit of port mode register 1 to 1.
Set the P00 bit of port register 1 to 0 or 1.
The PM0, PM1, PM3, and PM4 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark In the 20- and 24-pin products, TI00, TO00 (P13, P14, P41, P42) and the 30-pin products TI00 (P00)
and TO00 (P01) pins alternate analog input pins. When using the timer I/O function, the corresponding
bit of the PMCx register for switching digital I/O or analog input is sure to set to “0”.
Figure 6-20. Format of Port Mode Registers 0, 1, 3, 4 (PM0, PM1, PM3, or PM4)
20- and 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W
PM0n P0n pin I/O mode selection (m = 0, 1, 3, 4 ; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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6.4 Basic Rules of Time r Array Unit
6.4.1 Basic Rules of Simultaneous Channel Operation Function
When simultaneously using multiple channels, namely, a combination of a master channel (a reference timer mainly
counting the cycle) and slave channels (timers operating according to the master channel), the following rules apply.
(1) Only an even channel (channel 0, 2, 4, 6, 8) can be set as a master channel.
(2) Any channel, except channel 0, can be set as a slave channel.
(3) The slave channel must be lower than the master channel.
Example: If channel 2 is set as a master channel, channel 3 or those that follow (Channel 3 to 7) can be set as a
slave channel.
(4) Two or more slave channels can be set for one master channel.
(5) When two or more master channels are to be used, slave channels with a master channel between them may not
be set.
Example: If channels 0 and 4 are set as master channels, channels 1 to 3 can be set as the slave channels of
master channel 0. Channels 5 to 7 cannot be set as the slave channels of master channel 0.
(6) The operating clock for a slave channel in combination with a master channel must be the same as that of the
master channel. The CKS0n0 and CKS0n1 bits (bits 15 and 14 of timer mode register 0n (TMR0n)) of the slave
channel that operate in combination with the master channel must be the same value as that of the master channel.
(7) A master channel can transmit INTTM0n (interrupt), start software trigger, and count clock to the lower channels.
(8) A slave channel can use INTTM0n (interrupt), a start software trigger, or the count clock of the master channel as a
source clock, but cannot transmit its own INTTM0n (interrupt), start software trigger, or count clock to channels
with lower channel numbers.
(9) A master channel cannot use INTTM0n (interrupt), a start software trigger, or the count clock from the other higher
master channel as a source clock.
(10) To simultaneously start channels that operate in combination, the channel start trigger bit (TS0n) of the channels in
combination must be set at the same time.
(11) During the counting operation, a TS0n bit of a master channel or TS0n bits of all channels which are operating
simultaneously can be set. It cannot be applied to TS0n bits of slave channels alone.
(12) To stop the channels in combination simultaneously, the channel stop trigger bit (TT0n) of the channels in
combination must be set at the same time.
(13) CK02/CK03 cannot be selected while channels are operating simultaneously, because the operating clocks of
master channels and slave channels have to be synchronized.
(14) Timer mode register 0n (TMR0n) has no master bit (it is fixed as “0”). However, as channel 0 is the highest
channel, it can be used as a master channel during simultaneous operation.
Remark n: Channel number (n = 0 to 7)
The rules of the simultaneous channel operation function are applied in a channel group (a master channel and slave
channels forming one simultaneous channel operation function).
If two or more channel groups that do not operate in combination are specified, the basic rules of the simultaneous
channel operation function in 6.4.1 Basic rules of simultaneous channel operation function do not apply to the
channel groups.
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Channel 1: Slave
Channel 0: Master
Channel group 1
(Simultaneous channel operation function)
* Operation clocks can be different between
channel groups 1 and 2.
Channel 2: Slave
Channel 3: Independent channel operation function
Channel 4: Master
Channel 6: Slave
Channel 5: Independent channel
operation function
Channel 7: Independent channel
operation function
CK00
CK01
Channel group 2
(Simultaneous channel operation function)
TAU0
* The channel that operates with the
independent channel operation function
can exist between channel groups 1 and 2.
CK00
* Between the master and slave channel
group 2, the channel that operates with the
independent channel operation function
can exist. In addition, the settings of
operation clocks can be performed
individually.
Example
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6.4.2 Basic rules of 8-bit timer o peration function (Only Channels 1 and 3)
The 8-bit timer operation function makes it possible to use a 16-bit timer channel in a configuration consisting of two 8-
bit timer channels.
This function can only be used for channels 1 and 3, and there are several rules for using it.
The basic rules for this function are as follows:
(1) The 8-bit timer operation function applies only to channels 1 and 3.
(2) When using 8-bit timers, set the SPLIT bit of timer mode register 0n (TMR0n) to 1.
(3) The higher 8 bits can be operated as the interval timer function.
(4) At the start of operation, the higher 8 bits output INTTM01H/INTTM03H (an interrupt) (which is the same operation
performed when MD0n0 is set to 1).
(5) The operation clock of the higher 8 bits is selected according to the CKS0n1 and CKS0n0 bits of the lower-bit
TMR0n register.
(6) For the higher 8 bits, the TSH01/TSH03 bit is manipulated to start channel operation and the TTH01/TTH03 bit is
manipulated to stop channel operation. The channel status can be checked using the TEH01/TEH03 bit.
(7) The lower 8 bits operate according to the TMR0n register settings. The following three functions support operation
of the lower 8 bits:
• Interval timer function
• External event counter function
• Delay count function
(8) For the lower 8 bits, the TS01/TS03 bit is manipulated to start channel operation and the TT01/TT03 bit is
manipulated to stop channel operation. The channel status can be checked using the TE01/TE03 bit.
(9) During 16-bit operation, manipulating the TSH01/TSH03/TTH01/TTH03 bits is invalid. The TS01/TS03/TT01/TT03
bits are manipulated to operate channels 1 and 3. The TEH03 and TEH01 bits are not changed.
(10) For the 8-bit timer function, the simultaneous operation functions (one-shot pulse, PWM, and multiple PWM)
cannot be used.
Remark n: Channel number (n = 1, 3)
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6.5 Operation of Counter
6.5.1 Count clock (fTCLK)
The count clock (fTCLK) of the timer array unit can be selected between following by CCS0n bit of timer mode register 0n
(TMR0n). .
• Operation clock (fMCK) specified by the CKS0n0 and CKS0n1 bits
• Valid edge of input signal input from the TI0n pin
Because the timer array unit is designed to operate in synchronization with fCLK, the timings of the count clock (fTCLK)
are shown below.
(1) When operation clo ck (fMCK) specified by the CKS0n0 an d CKS0n1 bits is selected (CCS0n = 0)
The count clock (fTCLK) is between fCLK to fCLK /215 by setting of timer clock select register 0 (TPS0). When a divided
fCLK is selected, however, the clock selected in TPSmn register, but a signal which becomes high level for one
period of fCLK from its rising edge. When a fCLK is selected, fixed to high level
Counting of timer count register 0n (TCR0n) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at rising edge of the count clock”, as a
matter of convenience.
Figure 6-21. Ti ming of fCLK and count clo ck (fTCLK) (When CCS0n = 0)
Remarks 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. f
CLK: CPU/peripheral hardware clock
fCLK
fTCLK
( = fMCK
= CK0n)
fCLK/2
fCLK/4
fCLK/8
fCLK/16
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(2) When valid edge of input signal via the TI0n pin is selected (CCS0n = 1)
The count clock (fTCLK) becomes the signal that detects valid edge of input signal via the TI0n pin and synchronizes
next rising fMCK. The count clock (fTCLK) is delayed for 1 to 2 period of fMCK from the input signal via the TI0n pin
(when a noise filter is used, the delay becomes 3 to 4 clock).
Counting of timer count register 0n (TCR0n) delayed by one period of fCLK from rising edge of the count clock,
because of synchronization with fCLK. But, this is described as “counting at valid edge of input signal via the TI0n
pin”, as a matter of convenience.
Figure 6-22. Ti ming of fCLK and count clo ck (fTCLK) (When CCS0n = 1, noise filter unused)
<1> Setting TS0n bit to 1 enables the timer to be started and to become wait state for valid edge of input signal
via the TI0n pin.
<2> The rise of input signal via the TI0n pin is sampled by fMCK.
<3> The edge is detected by the rising of the sampled signal and the detection signal (count clock) is output.
Remarks 1. : Rising edge of the count clock
: Synchronization, increment/decrement of counter
2. f
CLK: CPU/peripheral hardware clock
f
MCK: Operation clock of channel n
3. The waveform of the input signal via TI0n pin of the input pulse interval measurement, the
measurement of high/low width of input signal, and the delay counter, the one-shot pulse
output are the same as that shown in Figure 6-22.
fMC
K
TS0n (Write)
TE0n
TI0n input
<1>
<2>
Rising edge
detection signal (fTCLK)
Sampling wave
Edge detection Edge detection
<3>
fCL
K
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6.5.2 Start tim ing of counter
Timer count register 0n (TCR0n) becomes enabled to operation by setting of TS0n bit of timer channel start register 0
(TS0).
Operations from count operation enabled state to timer count Register 0n (TCR0n) count start is shown in Table 6-6 .
Table 6 -6. Ope rati ons from Cou nt Opera tio n Ena bled State to Timer count Register 0n (TCR0n) Count Start
Timer operation mode Operation when TS0n = 1 is set
• Interval timer mode
No operation is carried out from start trigger detection (TS0n = 1) until count
clock generation.
The first count clock loads the value of the TDR0n register to the TCR0n register
and the subsequent count clock performs count down operation (see 6.5.3 (1)
Interval timer mode operation).
• Event counter mode
Writing 1 to the TS0n bit loads the value of the TDR0n register to the TCR0n
register.
Detection TI0n input edge, the subsequent count clock performs count down
operation. (see 6.5.3 (2) Event counter mode operation).
• Capture mode
No operation is carried out from start trigger (TS0n = 1) detection until count
clock generation.
The first count clock loads 0000H to the TCR0n register and the subsequent
count clock performs count up operation (see 6.5.3 (3) Capture mode operation
(input pulse interval measurement) ).
• One-count mode The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the
timer is stopped (TE0n = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads the value of the TDR0n register to the TCR0n register
and the subsequent count clock performs count down operation (see 6.5.3 (4)
One-count mode operation).
• Capture & one-count mode The waiting-for-start-trigger state is entered by writing 1 to the TS0n bit while the
timer is stopped (TE0n = 0).
No operation is carried out from start trigger detection until count clock
generation.
The first count clock loads 0000H to the TCR0n register and the subsequent
count clock performs count up operation (see 6.5.3 (5) Capture & one-count
mode operation (high-level width is measured)).
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6.5.3 Counter Operation
Here, the counter operation in each mode is explained.
(1) Interval timer mode operation
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit. Timer count register 0n (TCR0n) holds the
initial value until count clock generation.
<2> A start trigger is generated at the first count clock after operation is enabled.
<3> When the MD0n0 bit is set to 1, INTTM0n is generated by the start trigger.
<4> By the first count clock after the operation enable, the value of timer data register 0n (TDR0n) is loaded to
the TCR0n register and counting starts in the interval timer mode.
<5> When the TCR0n register counts down and its count value is 0000H, INTTM0n is generatedIn the next
count clock (fMCK) and the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and
counting keeps on.
Figure 6-23. Operation Timing (In Interval Timer Mode)
Caution In the first cycle operatio n of count clock after writing the TS0n bit, an error at a maximum o f one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MD0n0 = 1.
Remark fMCK, the start trigger detection signal, and INTTM0n become active between one clock in
synchronization with fCLK.
fMC
K
(fTCLK)
m
TS0n (Write)
TE0n
Start trigge
r
detection signal
TCR0n Initial
value m
TDR0n
INTTM0n
When MD0n0 = 1 setting
<1>
<3> <4>
m−10000 m
0001
<2>
<5>
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(2) Event counter mode operation
<1> Timer count register 0n (TCR0n) holds its initial value while operation is stopped (TE0n = 0).
<2> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
<3> As soon as 1 has been written to the TS0n bit and 1 has been set to the TE0n bit, the value of timer data
register 0n (TDR0n) is loaded to the TCR0n register to start counting.
<4> After that, the TCR0n register value is counted down according to the count clock of the valid edge of the
TI0n input.
Figure 6-24. Operation Timing (In Event Counter Mode)
Remark The timing is shown in Figure 6-24 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TI0n input.
The error per one period occurs be the asynchronous between the period of the TI0n input and that of
the count clock (fMCK).
fMCK
TS0n (Write)
TE0n
TI0n input
<1>
<2>
Count clock
Edge detection Edge detection
<4>
m
TCR0n Initial
value mm−1m−2
TDR0n
<3>
Start trigge
r
detection signal
<1> <3>
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(3) Capture mode operation (input pulse interval measurement)
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
<2> Timer count register 0n (TCR0n) holds the initial value until count clock generation.
<3> A start trigger is generated at the first count clock after operation is enabled. And the value of 0000H is
loaded to the TCR0n register and counting starts in the capture mode. (When the MD0n0 bit is set to 1,
INTTM0n is generated by the start trigger.)
<4> On detection of the valid edge of the TI0n input, the value of the TCR0n register is captured to timer data
register 0n (TDR0n) and INTTM0n is generated. However, this capture value is nomeaning. The TCR0n
register keeps on counting from 0000H.
<5> On next detection of the valid edge of the TI0n input, the value of the TCR0n register is captured to timer
data register 0n (TDR0n) and INTTM0n is generated.
Figure 6-25. Operation Timing (In Capture Mode: Input Pulse Interval Measurement)
Note If a clock has been input to TImn (the trigger exists) when capturing starts, counting starts when a
trigger is detected, even if no edge is detected. Therefore, the first captured value (<4>) does not
determine a pulse interval (in the above figure, 0001 just indicates two clock cycles but does not
determine the pulse interval) and so the user can ignore it.
Caution In the first cycle operatio n of count clock after writing the TS0n bit, an error at a maximum o f one
clock is generated since count start delays until count clock has been generated. When the
information on count start timing is necessary, an interrupt can be generated at count start by
setting MD0n0 = 1.
Remark The timing is shown in Figu re 6-25 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TI0n input.
The error per one period occurs be the asynchronous between the period of the TI0n input and that of
the count clock (fMCK).
fMC
K
(fTCLK)
TS0n(Write)
TE0n
TI0n input
<1>
<2>
Rising edge
<4>
TCR0n Initial value m−1
m
TDR0n
Start trigger
detection signal
<3>
0000 m
Edge detection
0001 Note
0000
INTTM0n
<5>
0000 0001
<3>
Note
Edge detection
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(4) One-count mode operation
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit.
<2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.
<3> Rising edge of the TI0n input is detected.
<4> On start trigger detection, the value of timer data register 0n (TDR0n) is loaded to the TCR0n register and
count starts.
<5> When the TCR0n register counts down and its count value is 0000H, INTTM0n is generated and the value
of the TCR0n register becomes FFFFH and counting stops
.
Figure 6-26. Operation Timing (In One-count Mode)
Remark The timing is shown in Figure 6-26 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n
input and that of the count clock (fMCK).
fMC
K
(fTCLK)
TS0n (Write)
TE0n
TI0n input
<1>
<2>
Rising edge
Edge detection
<4>
TCR0n Initial value 1
Start trigger
detection signal
<3>
m 0 FFFF
INTTM0n
Start trigger input wait status
<5>
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(5) Capture & one-count mode operation (high-level width is measured)
<1> Operation is enabled (TE0n = 1) by writing 1 to the TS0n bit of timer channel start register 0 (TS0).
<2> Timer count register 0n (TCR0n) holds the initial value until start trigger generation.
<3> Rising edge of the TI0n input is detected.
<4> On start trigger detection, the value of 0000H is loaded to the TCR0n register and count starts.
<5> On detection of the falling edge of the TI0n input, the value of the TCR0n register is captured to timer data
register 0n (TDR0n) and INTTM0n is generated.
Figure 6-27. Operation Timing (In Capture & One-count Mode: High-level Width Measurement)
Remark The timing is shown in Figure 6-28 indicates while the noise filter is not used. By making the noise filter
on-state, the edge detection becomes 2 fMCK cycles (it sums up to 3 to 4 cycles) later than the normal
cycle of TI0n input. The error per one period occurs be the asynchronous between the period of the TI0n
input and that of the count clock (fMCK).
fMC
K
(fTCLK)
TS0n(Write)
TE0n
TI0n input
<1>
<2>
Rising edge
Edge detection
<4>
TCR0n Initial value m−1
m
TDR0n
Start trigger
detection signal
<3>
Falling edge
0000 m
Edge detection
0000
m+1
INTTM0n
<5>
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6.6 Channel Output (TO0n pin) Control
6.6.1 TO0n pin output circuit configuration
Figure 6-28. Output Circuit Configuration
Interrupt signal of the master channel
(INTTM0n)
TOL0n
TOM0n
TOE0n
<1>
<2> <3><4>
<5>
TO0n write signal
TO0n pin
TO0n register
Set
Reset/toggle
Internal bus
Interrupt signal of the slave channel
(INTTM0p)
Controller
The following describes the TO0n pin output circuit.
<1> When TOM0n = 0 (master channel output mode), the set value of timer output level register 0 (TOL0) is
ignored and only INTTM0p (slave channel timer interrupt) is transmitted to timer output register 0 (TO0).
<2> When TOM0n = 1 (slave channel output mode), both INTTM0n (master channel timer interrupt) and INTTM0p
(slave channel timer interrupt) are transmitted to the TO0 register.
At this time, the TOL0 register becomes valid and the signals are controlled as follows:
When TOL0n = 0: Positive logic output (INTTM0n → set, INTTM0p → reset)
When TOL0n = 1: Negative logic output (INTTM0n → reset, INTTM0p → set)
When INTTM0n and INTTM0p are simultaneously generated, (0% output of PWM), INTTM0p (reset signal)
takes priority, and INTTM0n (set signal) is masked.
<3> While timer output is enabled (TOE0n = 1), INTTM0n (master channel timer interrupt) and INTTM0p (slave
channel timer interrupt) are transmitted to the TO0 register. Writing to the TO0 register (TO0n write signal)
becomes invalid.
When TOE0n = 1, the TO0n pin output never changes with signals other than interrupt signals.
To initialize the TO0n pin output level, it is necessary to set timer operation is stopped (TOE0n = 0) and to
write a value to the TO0 register.
<4> While timer output is disabled (TOE0n = 0), writing to the TO0n bit to the target channel (TO0n write signal)
becomes valid. When timer output is disabled (TOE0n = 0), neither INTTM0n (master channel timer interrupt)
nor INTTM0p (slave channel timer interrupt) is transmitted to the TO0 register.
<5> The TO0 register can always be read, and the TO0n pin output level can be checked.
Remark n: Channel number
n = 0 to 7 (n = 0, 2, 4, or 6 for master channel)
p: Slave channel number
n<p≤7
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6.6.2 TO0n Pin Output Setting
The following figure shows the procedure and status transition of the TO0n output pin from initial setting to timer
operation start.
Figure 6-29. Status Transition from Timer Output Setting to Operation Start
TCR0n
Timer alternate-function pin
Timer output signal
TOE0n
TO0n
(Counter)
Undefined value (FFFFH after reset)
Write operation enabled period to TO0n
<1> Set TOM0n
Set TOL0n
<4> Set the port to
output mode
<2> Set TO0n <3> Set TOE0n <5> Timer operation start
Write operation disabled period to TO0n
Hi-Z
<1> The operation mode of timer output is set.
• TOM0n bit (0: Master channel output mode, 1: Slave channel output mode)
• TOL0n bit (0: Positive logic output, 1: Negative logic output)
<2> The timer output signal is set to the initial status by setting timer output register 0 (TO0).
<3> The timer output operation is enabled by writing 1 to the TOE0n bit (writing to the TO0 register is disabled).
<4> The port is set to digital I/O by port mode control register (PMCxx) (see 6.3 (14) Port mode registers 0, 1, 3,
or 4 (PM0, PM1, PM3, or PM4)).
<5> The port I/O setting is set to output (see 6.3 (14) Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or
PM4)).
<6> The timer operation is enabled (TS0n = 1).
Remark n: Channel number (n = 0 to 7)
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6.6.3 Cautions on Channel Output Operation
(1) Changing values set in the registers TO0, TOE0, and TOL0 during timer operation
Since the timer operations (operations of timer count register 0n (TCR0n) and timer data register 0n (TDR0n)) are
independent of the TO0n output circuit and changing the values set in timer output register 0 (TO0), timer output enable
register 0 (TOE0), timer output level register 0 (TOL0) does not affect the timer operation, the values can be changed
during timer operation. To output an expected waveform from the TO0n pin by timer operation, however, set the TO0,
TOE0, TOL0, and TOM0 registers to the values stated in the register setting example of each operation.
When the values set to the TOE0 and TOL0 registers (but not the TO0 register) are changed close to the occurrence of
the timer interrupt (INTTM0n) of each channel, the waveform output to the TO0n pin might differ, depending on whether
the values are changed immediately before or immediately after the timer interrupt (INTTM0n) occurs.
Remark n: Channel number (n = 0 to 7)
(2) Default level of TO0n pin and output level after timer operation start
The change in the output level of the TO0n pin when timer output register 0 (TO0) is written while timer output is
disabled (TOE0n = 0), the initial level is changed, and then timer output is enabled (TOE0n = 1) before port output
is enabled, is shown below.
(a) When operation starts with master chann el ou tput mode (TOM0n = 0) setting
The setting of timer output level register 0 (TOL0) is invalid when master channel output mode (TOM0n = 0).
When the timer operation starts after setting the default level, the toggle signal is generated and the output
level of the TO0n pin is reversed.
Figure 6-30. TO0n Pin Output Status at Toggle Output (TOM0n = 0)
Hi
-
Z
TOE
mn
TOm
n
T Omn bit = 0
(Default status : Low)
T Omn bit = 1
(Default status : High)
T Omn bit = 0
(Default status : Low)
T Omn bit = 1
(Default status : High)
Bold : Active level
Toggle Toggle Toggle Toggle Toggle
Default
status
(output)
Port output is enabled
T OLmn bit = 0
(Active high)
T OLmn bit = 1
(Active lo w)
Remarks 1. Toggle: Reverse TO0n pin output status
2. n: Channel number (n = 0 to 7)
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(b) When operation starts with slave channel output mode (TOM0p = 1) setting (PWM output))
When slave channel output mode (TOM0p = 1), the active level is determined by timer output level register 0
(TOL0p) setting.
Figure 6-31. TOM0p Pin Output Status at PWM Output (TO0p = 1)
Hi-Z Active
TOEmp
Default
status
Set
Reset
Set
Reset Set
Port output is enabled
TOmp
(output)
ActiveActive
T Omp bit = 0
(Default status : Low)
T Omp bit = 1
(Default status : High)
T Omp bit = 0
(Default status : Low)
T Omp bit = 1
(Default status : High)
T OLmp bit = 0
(Active high)
T OLmp bit = 1
(Active lo w)
Remarks 1. Set: The output signal of the TO0p pin changes from inactive level to active level.
Reset: The output signal of the TO0p pin changes from active level to inactive level.
2. p: Channel number (n < p ≤ 7)
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(3) Operation of TO0n pin in slave channel output mode (TOM0n = 1)
(a) When timer output level register 0 (TOL0) setting has been changed during timer operation
When the TOL0 register setting has been changed during timer operation, the setting becomes valid at the
generation timing of the TO0n pin change condition. Rewriting the TOL0 register does not change the output
level of the TO0n pin.
The operation when TOM0n is set to 1 and the value of the TOL0 register is changed while the timer is
operating (TE0n = 1) is shown below.
Figure 6-32. Operation when TOL0 Register Has Been Ch anged during Timer Operation
TO0n(
Output
)
TOL0
Set Reset Set Reset Set Reset Set Reset
Active Active Active Active
Remarks 1. Set: The output signal of the TO0p pin changes from inactive level to active level.
Reset: The output signal of the TO0p pin changes from active level to inactive level.
2. n: Channel number (n = 0 to 7)
(b) Set/reset timing
To realize 0%/100% output at PWM output, the TO0n pin/TO0n bit set timing at master channel timer interrupt
(INTTM0n) generation is delayed by 1 count clock by the slave channel.
If the set condition and reset condition are generated at the same time, a higher priority is given to the latter.
Figure 6-34 shows the set/reset operating statuses where the master/slave channels are set as follows.
Master channel: TOE0n = 1, TOM0n = 0, TOL0n = 0
Slave channel: TOE0p = 1, TOM0p = 1, TOL0p = 0
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Figure 6-33. Set/Reset Timing Operating Statuses
(a) Basic operation timing
(b) Operation timing when 0 % duty
Remarks 1. Internal reset signal: TO0n pin reset/toggle signal
Internal set signal: TO0n pin set signal
2. n: Channel number (n = 0 to 7)
n = 0 to 7 (n = 0, 2, 4, 6 for master channel)
p: Slave channel number
n < p ≤ 7
TO0n pin/
TO0n
INTTM0p
fTCLK
INTTMmn
Internal reset
signal
Internal set
signal
Internal reset
signal
TO0p pin/
TO0p
Master
channel
Slave
channel
1 clock delay
Toggle Toggle
Set
Set
Reset
Reset has priority.
Reset
Reset has priority.
TCR0p 0000 0001 0000 0001
TO0n pin/
TO0n
INTTM0p
fTCLK
INTTM0n
Internal reset
signal
Internal reset
signal
TO0p pin/
TO0p
Master
channel
Slave
channel
1 clock delay
Toggle Toggle
Set Set
Reset
Internal set
signal
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6.6.4 Collective manipulation of TO0n bit
In timer output register 0 (TO0), the setting bits for all the channels are located in one register in the same way as timer
channel start register 0 (TS0). Therefore, the TO0n bit of all the channels can be manipulated collectively.
Only the desired bits can also be manipulated by enabling writing only to the TO0n bits (TOE0n = 0) that correspond to
the relevant bits of the channel used to perfor0 output (TO0n).
Figure 6-34 Example of TO0n Bit Collective Manip u lation
Before writing
TO0 0 0 0 0 0 0 0 0 TO07
0
TO06
0
TO05
1
TO04
0
TO03
0
TO02
0
TO01
1
TO00
0
TOE0 0 0 0 0 0 0 0 0
TOE07
0
TOE06
0
TOE05
1
TOE04
0
TOE03
1
TOE02
1
TOE01
1
TOE00
1
Data to be written
0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1
After writing
TO0 0 0 0 0 0 0 0 0 TO07
1
TO06
1
TO05
1
TO04
0
TO03
0
TO02
0
TO01
1
TO00
0
Writing is done only to the TO0n bit with TOE0n = 0, and writing to the TO0n bit with TOE0n = 1 is ignored.
TO0n (channel output) to which TOE0n = 1 is set is not affected by the write operation. Even if the write operation is
done to the TO0n bit, it is ignored and the output change by timer operation is normally done.
Figure 6-35. TO0n Pin Statuses by Collective Manipulation of TO0n Bit
TO07
TO06
TO05
TO04
TO03
TO02
TO01
TO00
Two or more TO0n output can
be changed simultaneously
Output does not change
when value does not
change
Before writing
Writing to the TO0n bit is
ignored when TOE0n
= 1
Writing to the TO0n bit
Remark n: Channel number (n = 0 to 7)
O
OO××
×
××
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6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start
In the interval timer mode or capture mode, the MD0n0 bit in timer mode register 0n (TMR0n) sets whether or not to
generate a timer interrupt at count start.
When MD0n0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTM0n) generation.
In the other modes, neither timer interrupt at count operation start nor TO0n output is controlled.
Figure 6-37 shows operation examples when the interval timer mode (TOE0n = 1, TOM0n = 0) is set.
Figure 6-36. Operation examples of timer interrupt at count operation start and TOmn output
(a) When MD0n0 is set to 1
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
(b) When MD0n0 is set to 0
TCR0n
TE0n
TO0n
INTTM0n
Count operation start
When MD0n0 is set to 1, a timer interrupt (INTTM0n) is output at count operation start, and TO0n performs a toggle
operation.
When MD0n0 is set to 0, a timer interrupt (INTTM0n) is not output at count operation start, and TO0n does not change
either. After counting one cycle, INTTM0n is output and TO0n performs a toggle operation.
Remark n: Channel number (n = 0 to 7)
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6.7 Independent Channel Operation Function of Timer Array Unit
6.7.1 Operation as interval timer/square wave output
(1) Interval
timer
The timer array unit can be used as a reference timer that generates INTTM0n (timer interrupt) at fixed intervals.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTM0n (timer interrupt) = Period of count clock × (Set value of TDR0n + 1)
(2) Operation as square wave output
TO0n performs a toggle operation as soon as INTTM0n has been generated, and outputs a square wave with a
duty factor of 50%.
The period and frequency for outputting a square wave from TO0n can be calculated by the following expressions.
• Period of square wave output from TO0n = Period of count clock × (Set value of TDR0n + 1) × 2
• Frequency of square wave output from TO0n = Frequency of count clock/{(Set value of TDR0n + 1) × 2}
Timer count register 0n (TCR0n) operates as a down counter in the interval timer mode.
The TCR0n register loads the value of timer data register 0n (TDR0n) at the first count clock after the channel start
trigger bit (TS0n, TSH01, TSH03) of timer channel start register 0 (TS0) is set to 1. If the MD0n0 bit of timer mode
register 0n (TMR0n) is 0 at this time, INTTM0n is not output and TO0n is not toggled. If the MD0n0 bit of the
TMR0n register is 1, INTTM0n is output and TO0n is toggled.
After that, the TCR0n register count down in synchronization with the count clock.
When TCR0n = 0000H, INTTM0n is output and TO0n is toggled at the next count clock. At the same time, the
TCR0n register loads the value of the TDR0n register again. After that, the same operation is repeated.
The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid from the
next period.
Remark n: Channel number (n = 0 to 7)
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Figure 6-37. Block Diagram of Operation as Interval Timer/Square Wave Output
CK00
CK01
TS0n
Timer counter
register 0n (TCR0n) TO0n pin
Interrupt signal
(INTTM0n)
Timer data
register 0n (TDR0n) Interrupt
controller
Output
controller
Clock selection
Trigger selection
Operation clock
Note
Note When channels 1 and 3, the clock can be selected from CK00 to CK03.
Figure 6-38. Example of Basic Timing of Operation as Interval Timer/Square Wave Output (MD0n0 = 1)
TS0n
TE0n
TDR0n
TCR0n
TO0n
I
NTTM0n
a
a+1
b
0000H
a+1 a+1 b+1 b+1 b+1
Remarks 1. n: Channel number (n = 0 to 7)
2. TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
TO0n: TO0n pin output signal
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Figure 6-39. Example of Set Content s of Re gisters During Opera tion as Interval T imer /Sq uare Wave Output (1/2)
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
1/0
0
CCS0n
0
M/S Note
0/1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1/0
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
1: Generates INTTM0n and inverts timer
output when counting is started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
1: 8-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
1/0
0: Outputs 0 from TO0n.
1: Outputs 1 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
1/0
0: Stops the TO0n output operation by counting operation.
1: Enables the TO0n output operation by counting operation.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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Figure 6-39. Example of Set Content s of Re gisters During Opera tion as Interval T imer /Sq uare Wave Output (2/2)
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when master channel output mode (TOM0n = 0)
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0 to 7)
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01 (or
CK02 and CK03 when using the 8-bit timer mode).
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel).
Sets interval (period) value to timer data register 0n
(TDR0n).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
To use the TO0n output
Clears the TOM0n bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the TOL0n bit to 0.
Sets the TO0n bit and determines default level of the
TO0n output.
Sets the TOE0n bit to 1 and enables operation of TO0n.
Clears the port register and port mode register to 0.
The TO0n pin goes into Hi-Z output state.
The TO0n default setting level is output when the port mode
register is in the output mode and the port register is 0.
TO0n does not change because channel stops operating.
The TO0n pin outputs the TO0n set level.
Operation
start
(Sets the TOE0n bit to 1 only if using TO0n output and
resuming operation.).
Sets the TS0n (TSH01, TSH03) bit to 1.
The TS0n (TSH01, TSH03) bit automatically returns to
0 because it is a trigger bit.
TE0n (TEH01, TEH03) = 1, and count operation starts.
Value of the TDR0n register is loaded to timer count
register 0n (TCR0n) at the count clock input. INTTM0n is
generated and TO0n performs toggle operation if the
MD0n0 bit of the TMR0n register is 1.
During
operation
Set values of the TMR0n register, TOM0n, and TOL0n
bits cannot be changed.
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Counter (TCR0n) counts down. When count value reaches
0000H, the value of the TDR0n register is loaded to the
TCR0n register again and the count operation is continued.
By detecting TCR0n = 0000H, INTTM0n is generated and
TO0n performs toggle operation.
After that, the above operation is repeated.
The TT0n (TTH01, TTH03) bit is set to 1.
The TT0n (TTH01, TTH03) bit automatically returns to
0 because it is a trigger bit.
TE0n (TEH01, TEH03), and count operation stops.
The TCR0n register holds count value and stops.
The TO0n output is not initialized but holds current status.
Operation
stop
The TOE0n bit is cleared to 0 and value is set to the TO0n bit.
The TO0n pin outputs the TO0n bit set level.
(Remark is listed on the next page.)
Operation is resumed.
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Figure 6-40. Operation Procedure of Interval Timer/Square Wave Output Function (2/2)
Software Operation Hardware Status
TAU
stop
To hold the TO0n pin output level
Clears the TO0n bit to 0 after the value to
be held is set to the port register.
When holding the TO0n pin output level is not necessary
Setting not required.
The TO0n pin output level is held by port function.
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO0n bit is cleared to 0 and the TO0n pin is set to
port mode.)
Remark n: Channel number (n = 0 to 7)
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6.7.2 Operation as external event counter
The timer array unit can be used as an external event counter that counts the number of times the valid input edge
(external event) is detected in the TI0n pin. When a specified count value is reached, the event counter generates an
interrupt. The specified number of counts can be calculated by the following expression.
Specified number of counts = Set value of TDR0n + 1
Timer count register 0n (TCR0n) operates as a down counter in the event counter mode.
The TCR0n register loads the value of timer data register 0n (TDR0n) by setting any channel start trigger bit (TS0n,
TSH01, TSH03) of timer channel start register 0 (TS0) to 1.
The TCR0n register counts down each time the valid input edge of the TI0n pin has been detected. When TCR0n =
0000H, the TCR0n register loads the value of the TDR0n register again, and outputs INTTM0n.
After that, the above operation is repeated.
An irregular waveform that depends on external events is output from the TO0n pin. Stop the output by setting the
TOE0n bit of timer output enable register 0 (TOE0) to 0.
The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid during the next
count period.
Figure 6-41. Block Diagram of Operation as External Event Counter
Edge
detection
TI0n pin
Clock selection
Trigger selection
TS0n Interrupt signal
(INTTM0n)
Interrupt
controller
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Noise
filter
TNFEN0n
Remark n: Channel number (n = 0 to 7)
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Figure 6-42. Example of Basic Timing of Operation as External Event Counter
TS0n
TE0n
TI0n
TDR0n
TCR0n
0003H 0002H
0
0000H
1
3
0
120
121
2
3
2
INTTM0n
4 events 4 events 3 events
Remarks 1. n: Channel number (n = 0 to 7)
2. TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TI0n: TI0n pin input signal
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
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Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (1/2)
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
1/0
0
CCS0n
1
M/S Note
0/1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
1
MD0n1
1
MD0n0
0
Operation mode of channel n
011B: Event count mode
Setting of operation when counting is started
0: Neither generates INTTM0n nor inverts
timer output when counting is started.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
1: 8-bit timer
Count clock selection
1: Selects the TI0n pin input valid edge.
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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Figure 6-43. Example of Set Contents of Registers in External Event Counter Mode (2/2)
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when master channel output mode (TOM0n = 0).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0 to 7)
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Figure 6-44. Operation Procedure When External Event Counter Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01 (or
CK02 and CK03 when using the 8-bit timer mode).
Channel
default
setting
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel).
Sets number of counts to timer data register 0n (TDR0n).
Sets noise filter enable register 1 (NFEN1)
Clears the TOE0n bit of timer output enable register 0
(TOE0) to 0.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation
start
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and count operation starts.
Value of the TDR0n register is loaded to timer count
register 0n (TCR0n) and detection of the TI0n pin input
edge is awaited.
During
operation
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TMR0n register, TOM0n, TOL0n, TO0n,
and TOE0n bits cannot be changed.
Counter (TCR0n) counts down each time input edge of the
TI0n pin has been detected. When count value reaches
0000H, the value of the TDR0n register is loaded to the
TCR0n register again, and the count operation is
continued. By detecting TCR0n = 0000H, the INTTM0n
output is generated.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
The TCR0n register holds count value and stops.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n: Channel number (n = 0 to 7)
Operation is resumed.
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6.7.3 Operation as frequency divider (channel 0 of unit 0 only)
The timer array unit can be used as a frequency divider that divides a clock input to the TI00 pin and outputs the result
from the TO00 pin.
The divided clock frequency output from TO00 can be calculated by the following expression.
• When rising edge/falling edge is selected:
Divided clock frequency = Input clock frequency/{(Set value of TDR00 + 1) × 2}
• When both edges are selected:
Divided clock frequency ≅ Input clock frequency/(Set value of TDR00 + 1)
Timer count register 00 (TCR00) operates as a down counter in the interval timer mode.
After the channel start trigger bit (TS00) of timer channel start register 0 (TS0) is set to 1, the TCR00 register loads the
value of timer data register 00 (TDR00) when the TI00 valid edge is detected.
If the MD000 bit of timer mode register 00 (TMR00) is 0 at this time, INTTM00 is not output and TO00 is not toggled. If
the MD000 bit of timer mode register 00 (TMR00) is 1, INTTM00 is output and TO00 is toggled.
After that, the TCR00 register counts down at the valid edge of the TI00 pin. When TCR00 = 0000H, it toggles TO00.
At the same time, the TCR00 register loads the value of the TDR00 register again, and continues counting.
If detection of both the edges of the TI00 pin is selected, the duty factor error of the input clock affects the divided clock
period of the TO00 output.
The period of the TO00 output clock includes a sampling error of one period of the operation clock.
Clock period of TO00 output = Ideal TO00 output clock period ± Operation clock period (error)
The TDR00 register can be rewritten at any time. The new value of the TDR00 register becomes valid during the next
count period.
Figure 6-45. Block Diagram of Operation as Frequency Divider
Edge
detection
TI00 pin
Clock selection
Trigger selection
TS00
TO00 pin
Output
controller
Timer counter
register 00 (TCR00)
Timer data
register 00 (TDR00)
Noise
filter
TNFEN00
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Figure 6-46. Example of Basic Timing of Operation as Frequ en cy Divider (MD000 = 1)
TS00
TE00
TI00
TDR00
TCR00
TO00
INTTM00
0002H
Divided
by 6
0001H
0
0000H
1
2
0
1
2
0
10
10
10
10
1
2
Divided
by 4
Remark TS00: Bit n of timer channel start register 0 (TS0)
TE00: Bit n of timer channel enable status register 0 (TE0)
TI00: TI00 pin input signal
TCR00: Timer count register 00 (TCR00)
TDR00: Timer data register 00 (TDR00)
TO00: TO00 pin output signal
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Figure 6-47. Example of Set Contents of Registers During Operation as Frequency Divider
(a) Timer mode register 00 (TMR00)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR00 CKS0n1
1/0
CKS0n0
0
0
CCS00
1
MAS
TER00
0
STS002
0
STS001
0
STS000
0
CIS001
1/0
CIS000
1/0
0
0
MD003
0
MD002
0
MD001
0
MD000
1/0
Operation mode of channel 0
000B: Interval timer
Setting of operation when counting is started
0: Neither generates INTTM00 nor inverts
timer output when counting is started.
1: Generates INTTM00 and inverts timer
output when counting is started.
Selection of TI00 pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
000B: Selects only software start.
Slave/master selection
0: Independent channel operation.
Count clock selection
1: Selects the TI00 pin input valid edge.
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel 0.
10B: Selects CK01 as operation clock of channel 0.
(b) Timer output register 0 (TO0)
Bit 0
TO0 TO00
1/0
0: Outputs 0 from TO00.
1: Outputs 1 from TO00.
(c) Timer output enable register 0 (TOE0)
Bit 0
TOE0 TOE00
1/0
0: Stops the TO00 output operation by counting operation.
1: Enables the TO00 output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit 0
TOL0 TOL00
0
0: Cleared to 0 when master channel output mode (TOM00 = 0)
(e) Timer output mode register 0 (TOM0)
Bit 0
TOM0 TOM00
0
0: Sets master channel output mode.
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Figure 6-48. Operation Procedure When Frequency Divider Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel and selects the detection
edge).
Sets interval (period) value to timer data register 00
(TDR00).
Sets noise filter enable register 1 (NFEN1)
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Clears the TOM00 bit of timer output mode register 0
(TOM0) to 0 (master channel output mode).
Clears the TOL00 bit to 0.
Sets the TO00 bit and determines default level of the
TO00 output.
Sets the TOE00 bit to 1 and enables operation of TO00.
Clears the port register and port mode register to 0.
The TO00 pin goes into Hi-Z output state.
The TO00 default setting level is output when the port mode
register is in output mode and the port register is 0.
TO00 does not change because channel stops operating.
The TO00 pin outputs the TO00 set level.
Operation
start
Sets the TOE00 bit to 1 (only when operation is
resumed).
Sets the TS00 bit to 1.
The TS00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 1, and count operation starts.
Value of the TDR00 register is loaded to timer count
register 00 (TCR00) at the count clock input. INTTM00 is
generated and TO00 performs toggle operation if the
MD000 bit of the TMR00 register is 1.
During
operation
Set value of the TDR00 register can be changed.
The TCR00 register can always be read.
The TSR00 register is not used.
Set values of the TO0 and TOE0 registers can be
changed.
Set values of the TMR00 register, TOM00, and TOL00
bits cannot be changed.
Counter (TCR00) counts down. When count value reaches
0000H, the value of the TDR00 register is loaded to the
TCR00 register again, and the count operation is continued.
By detecting TCR00 = 0000H, INTTM00 is generated and
TO00 performs toggle operation.
After that, the above operation is repeated.
The TT00 bit is set to 1.
The TT00 bit automatically returns to 0 because it is a
trigger bit.
TE00 = 0, and count operation stops.
The TCR00 register holds count value and stops.
The TO00 output is not initialized but holds current status.
Operation
stop
The TOE00 bit is cleared to 0 and value is set to the TO00 bit.
The TO00 pin outputs the TO00 set level.
To hold the TO00 pin output level
Clears the TO00 bit to 0 after the value to be held is
set to the port register.
When holding the TO00 pin output level is not
necessary
Setting not required.
The TO00 pin output level is held by port function.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is also
initialized.
(The TO00 bit is cleared to 0 and the TO00 pin is set to
port mode).
Operation is resumed.
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6.7.4 Operation as input pulse interval measurement
The count value can be captured at the TI0n valid edge and the interval of the pulse input to TI0n can be measured.
The pulse interval can be calculated by the following expression.
TI0n input pulse interval = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of timer
mode register 0n (TMR0n), so an error of up to one operating clock cycle occurs.
Timer count register 0n (TCR0n) operates as an up counter in the capture mode.
When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TCR0n register counts
up from 0000H in synchronization with the count clock.
When the TI0n pin input valid edge is detected, the count value of the TCR0n register is transferred (captured) to timer
data register 0n (TDR0n) and, at the same time, the TCR0n register is cleared to 0000H, and the INTTM0n is output. If
the counter overflows at this time, the OVF bit of timer status register 0n (TSR0n) is set to 1. If the counter does not
overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Set the STS0n2 to STS0n0 bits of the TMR0n register to 001B to use the valid edges of TI0n as a start trigger and a
capture trigger.
When TE0n = 1, a software operation (TS0n = 1) can be used as a capture trigger, instead of using the TI0n pin input.
Figure 6-49. Block Diagram of Operation as Input Pulse Interval Measurement
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
Note
CK00
CK01
Edge
detection
TI0n pin
TS0n
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Noise
filter
TNFEN0n
Note When channels 1 and 3, the clock can be selected from CK00 to CK03.
Remark n: Channel number (n = 0 to 7)
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Figure 6-50. Example of Basic Timing of Operation as Input Pulse Interval Measurement (MD0n0 = 0)
TS0n
TE0n
TI0n
TDR0n
TCR0n
0000H c
b
0000H
acd
INTTM0n
FFFFH
ba d
OVF
Remarks 1. n: Channel number (n = 0 to 7)
2. TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TI0n: TI0n pin input signal
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
OVF: Bit 0 of timer status register 0n (TSR0n)
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Figure 6-51. Example of Set Contents of Registers to Measure Input Pulse Interval
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
0
0
CCS0n
0
M/S Note
0
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
0
MD0n2
1
MD0n1
0
MD0n0
1/0
Operation mode of channel n
010B: Ca
p
ture mode
Setting of operation when counting is started
0: Does not generate INTTM0n when
counting is started.
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Capture trigger selection
001B: Selects the TI0n pin input valid edge.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
0: 16-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops TO0n output operation by counting operation.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when master channel output mode (TOM0n = 0).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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Figure 6-52. Operation Procedure When Input Pulse Interval Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel).
Sets Noise filter enable register 1 (NFEN1).
Channel stops operating.
(Clock is supplied and some power is consumed.)
Operation
start
Sets TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and count operation starts.
Timer count register 0n (TCR0n) is cleared to 0000H at
the count clock input.
When the MD0n0 bit of the TMR0n register is 1,
INTTM0n is generated.
During
operation
Set values of only the CIS0n1 and CIS0n0 bits of the
TMR0n register can be changed.
The TDR0n register can always be read.
The TCR0n register can always be read.
The TSR0n register can always be read.
Set values of the TOM0n, TOL0n, TO0n, and TOE0n bits
cannot be changed.
Counter (TCR0n) counts up from 0000H. When the TI0n
pin input valid edge is detected, the count value is
transferred (captured) to timer data register 0n (TDR0n).
At the same time, the TCR0n register is cleared to 0000H,
and the INTTM0n signal is generated.
If an overflow occurs at this time, the OVF bit of timer
status register 0n (TSR0n) is set; if an overflow does not
occur, the OVF bit is cleared.
After that, the above operation is repeated.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
The TCR0n register holds count value and stops.
The OVF bit of the TSR0n register is also held.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n: Channel number (n = 0 to 7)
Operation is resumed.
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6.7.5 Operation as input signal high-/low-level width measurement
By starting counting at one edge of the TI0n pin input and capturing the number of counts at another edge, the signal
width (high-level width/low-level width) of TI0n can be measured. The signal width of TI0n can be calculated by the
following expression.
Signal width of TI0n input = Period of count clock × ((10000H × TSR0n: OVF) + (Capture value of TDR0n + 1))
Caution The TI0n pin input is sampled using the operating clock selected with the CKS0n bit of timer
mode register 0n (TMR0n), so an error equivalent to one operation clo ck occurs.
Timer count register 0n (TCR0n) operates as an up counter in the capture & one-count mode.
When the channel start trigger bit (TS0n) of timer channel start register 0 (TS0) is set to 1, the TE0n bit is set to 1 and
the TI0n pin start edge detection wait status is set.
When the TI0n pin input start edge (rising edge of the TI0n pin input when the high-level width is to be measured) is
detected, the counter counts up from 0000H in synchronization with the count clock. When the valid capture edge (falling
edge of the TI0n pin input when the high-level width is to be measured) is detected later, the count value is transferred to
timer data register 0n (TDR0n) and, at the same time, INTTM0n is output. If the counter overflows at this time, the OVF bit
of timer status register 0n (TSR0n) is set to 1. If the counter does not overflow, the OVF bit is cleared. The TCR0n
register stops at the value “value transferred to the TDR0n register + 1”, and the TI0n pin start edge detection wait status
is set. After that, the above operation is repeated.
As soon as the count value has been captured to the TDR0n register, the OVF bit of the TSR0n register is updated
depending on whether the counter overflows during the measurement period. Therefore, the overflow status of the
captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF bit of
the TSR0n register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two or more
overflows occur.
Whether the high-level width or low-level width of the TI0n pin is to be measured can be selected by using the CIS0n1
and CIS0n0 bits of the TMR0n register.
Because this function is used to measure the signal width of the TI0n pin input, the TS0n bit cannot be set to 1 while
the TE0n bit is 1.
CIS0n1, CIS0n0 of TMR0n register = 10B: Low-level width is measured.
CIS0n1, CIS0n0 of TMR0n register = 11B: High-level width is measured.
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Figure 6-53. Block Diagram of Operation as Input Signal High-/Low-Level Width Measurement
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
Note
CK00
CK01
Edge
detection
TI0n pin
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Noise
filter
TNFEN0n
Note For channels 1 and 3, the clock can be selected from CK00 to CK03.
Figure 6-54. Example of Basic Timing of Operation as Input Signal High-/Low-Level Width Measurement
TS0n
TE0n
TI0n
TDR0n
TCR0n
b
0000H
ac
INTTM0n
FFFFH
b
ac
OVF
0000H
Remarks 1. n: Channel number (n = 0 to 7)
2. TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TI0n: TI0n pin input signal
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
OVF: Bit 0 of timer status register 0n (TSR0n)
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Figure 6-55. Example of Set Contents of Registers to Measure Input Signal High-/Low-Level Width
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
0
0
CCS0n
0
M/S Note
0
STS0n2
0
STS0n1
1
STS0n0
0
CIS0n1
1
CIS0n0
1/0
0
0
MD0n3
1
MD0n2
1
MD0n1
0
MD0n0
0
Operation mode of channel n
110B: Capture & one-count
Setting of operation when counting is started
0: Does not generate INTTM0n when
counting is started.
Selection of TI0n pin input edge
10B: Both edges (to measure low-level width)
11B: Both edges (to measure high-level width)
Start trigger selection
010B: Selects the TI0n pin input valid edge.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
0: 16-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
01B: Selects CK02 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when master channel output mode (TOM0n = 0).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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Figure 6-56. Operation Procedure When Input Signal High-/Low-Level Width Measurement Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Channel
default
setting
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel).
Sets noise filter enable register 1 (NFEN1)
Clears the TOE0n bit to 0 and stops operation of TO0n.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and the TI0n pin start edge detection wait
status is set.
Operation
start
Detects the TI0n pin input count start valid edge. Clears timer count register 0n (TCR0n) to 0000H and
starts counting up.
During
operation
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
Set values of the TMR0n register, TOM0n, TOL0n, TO0n,
and TOE0n bits cannot be changed.
When the TI0n pin start edge is detected, the counter
(TCR0n) counts up from 0000H. If a capture edge of the
TI0n pin is detected, the count value is transferred to timer
data register 0n (TDR0n) and INTTM0n is generated.
If an overflow occurs at this time, the OVF bit of timer
status register 0n (TSR0n) is set; if an overflow does not
occur, the OVF bit is cleared. The TCR0n register stops
the count operation until the next TI0n pin start edge is
detected.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
The TCR0n register holds count value and stops.
The OVF bit of the TSR0n register is also held.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n: Channel number (n = 0 to 7)
Operation is resumed.
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6.7.6 Operation as delay counter
It is possible to start counting down when the valid edge of the TI0n pin input is detected (an external event), and then
generate INTTM0n (a timer interrupt) after any specified interval.
It can also generate INTTM0n (timer interrupt) at any interval by making a software set TS0n = 1 and the count down
start during the period of TE0n = 1.
The interrupt generation period can be calculated by the following expression.
Generation period of INTTM0n (timer interrupt) = Period of count clock × (Set value of TDR0n + 1)
Timer count register 0n (TCR0n) operates as a down counter in the one-count mode.
When the channel start trigger bit (TS0n, TSHm1, TSHm3) of timer channel start register 0 (TS0) is set to 1, the TE0n,
TEHm1, TEHm3 bits are set to 1 and the TI0n pin input valid edge detection wait status is set.
Timer count register 0n (TCR0n) starts operating upon TI0n pin input valid edge detection and loads the value of timer
data register 0n (TDR0n). The TCR0n register counts down from the value of the TDR0n register it has loaded, in
synchronization with the count clock. When TCR0n = 0000H, it outputs INTTM0n and stops counting until the next TI0n
pin input valid edge is detected.
The TDR0n register can be rewritten at any time. The new value of the TDR0n register becomes valid from the next
period.
Figure 6-57. Block Diagram of Operation as Delay Counter
Interrupt signal
(INTTM0n)
Interrupt
controller
Operation clockNote
TI0n pin
CK00
CK01
TS0n
Clock selection
Trigger selection
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Edge
detection
Noise
filter
TNFEN0n
Note For using channels 1 and 3 in 8-bit timer mode, the clock can be selected from CK00 to CK03.
Remark n: Channel number (n = 0 to 7)
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Figure 6-58. Example of Basic Timing of Operation as Delay Counter
TE0n
TDR0n
TCR0n
INTTM0n
ab
0000H
a+1 b+1
FFFFH
TI0n
TS0n
Remarks 1. n: Channel number (n = 0 to 7)
2. TS0n: Bit n of timer channel start register 0 (TS0)
TE0n: Bit n of timer channel enable status register 0 (TE0)
TI0n: TI0n pin input signal
TCR0n: Timer count register 0n (TCR0n)
TDR0n: Timer data register 0n (TDR0n)
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Figure 6-59. Example of Set Contents of Registers to Delay Counter (1/2)
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
1/0
0
CCS0n
0
M/S Note
0/1
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
1
MD0n2
0
MD0n1
0
MD0n0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
1: Trigger input is valid.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TI0n pin input valid edge.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
1: 8-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK02 as operation clock of channel n.
01B: Selects CK01 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
11B: Selects CK03 as operation clock of channels 1, 3 (This can only be selected channels 1 and 3).
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0 to 7)
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Figure 6-59. Example of Set Contents of Registers to Delay Counter (2/2)
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when master channel output mode (TOM0n = 0).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0 to 7)
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Figure 6-60. Operation Procedure When Delay Counter Function Is Used
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01 (or
CK02 and CK03 when using the 8-bit timer mode).
Channel
default
setting
Sets timer mode register 0n (TMR0n) (determines
operation mode of channel).
INTTM0n output delay is set to timer data register 0n
(TDR0n).
Sets noise filter enable register 1 (NFEN1).
Clears the TOE0n bit to 0 and stops operation of TO0n.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Sets the TS0n bit to 1.
The TS0n bit automatically returns to 0 because it is a
trigger bit.
TE0n = 1, and the TI0n pin input valid edge detection wait
status is set.
Operation
start
Detects the TI0n pin input valid edge. Value of the TDR0n register is loaded to the timer count
register 0n (TCR0n).
During
operation
Set value of the TDR0n register can be changed.
The TCR0n register can always be read.
The TSR0n register is not used.
The counter (TCR0n) counts down. When TCR0n counts
down to 0000H, INTTM0n is output, and counting stops
(which leaves TCR0n at 0000H) until the next TI0n pin
input.
Operation
stop
The TTmn bit is set to 1.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
TE0n = 0, and count operation stops.
The TCR0n register holds count value and stops.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
Remark n: Channel number (n = 0 to 7)
Operation is resumed.
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6.8 Simult aneous Channel Operation Function of Timer Array Unit
6.8.1 Operation as one-shot pulse output function
By using two channels as a set, a one-shot pulse having any delay pulse width can be generated from the signal input
to the TI0n pin.
The delay time and pulse width can be calculated by the following expressions.
Delay time = {Set value of TDR0n (master) + 2} × Count clock period
Pulse width = {Set value of TDR0p (slave)} × Count clock period
The master channel operates in the one-count mode and counts the delays. Timer count register 0n (TCR0n) of the
master channel starts operating upon start trigger detection and loads the value of timer data register 0n (TDR0n).
The TCR0n register counts down from the value of the TDR0n register it has loaded, in synchronization with the count
clock. When TCR0n = 0000H, it outputs INTTM0n and stops counting until the next start trigger is detected.
The slave channel operates in the one-count mode and counts the pulse width. The TCR0p register of the slave
channel starts operation using INTTM0n of the master channel as a start trigger, and loads the value of the TDR0p
register. The TCR0p register counts down from the value of The TDR0p register it has loaded, in synchronization with the
count value. When count value = 0000H, it outputs INTTM0p and stops counting until the next start trigger (INTTM0n of
the master channel) is detected. The output level of TO0p becomes active one count clock after generation of INTTM0n
from the master channel, and inactive when TCR0p = 0000H.
Instead of using the TI0n pin input, a one-shot pulse can also be output using the software operation (TS0n = 1) as a
start trigger.
Caution The timing of loading of timer data register 0n (TDR0n) of the master channel is different from that of
the TDR0p register of the slave channel. If the TDR0n and TDR0p registers are rewritten during
operation, therefore, an illegal waveform is output. Rewrite the TDR0n register after INTTM0n is
generated and the TDR0p register after INTTM0p is generated.
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-61. Block Diagram of Operation as One-Shot Pulse Output Function
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TS0n
Interrupt signal
(INTTM0p)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TO0p pin
Output
controller
Master channel
(one-count mode)
Slave channel
(one-count mode)
Edge
detection
TI0n pin
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Timer counter
register 0p (TCR0p)
Timer data
register 0p (TDR0p)
Noise
filter
TNFEN0n
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-62. Example of Basic Timing of Operation as One-Shot Pulse Output Function
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a
b
0000H
TS0p
TE0p
TDR0p
TCR0p
TO0p
INTTM0p
0000H
b
Master
channel
Slave
channel
a+2 b
a+2
FFFFH
FFFFH
TI0n
TS0n
Remarks 1. n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
2. TS0n, TS0p: Bit n, p of timer channel start register 0 (TS0)
TE0n, TE0p: Bit n, p of timer channel enable status register 0 (TE0)
TI0n, TI0p: TI0n and TI0p pins input signal
TCR0n, TCR0p: Timer count registers mn, mp (TCR0n, TCR0p)
TDR0n, TDR0p: Timer data registers mn, mp (TDR0n, TDR0p)
TO0n, TO0p: TO0n and TO0p pins output signal
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Figure 6-63. Ex ample of Set Content s of Regis ters When One- Shot Pulse Output Fu nction Is Used (Ma ster Channel)
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
0
0
CCS0n
0
MAS
TERmn
1
STS0n2
0
STS0n1
0
STS0n0
1
CIS0n1
1/0
CIS0n0
1/0
0
0
MD0n3
1
MD0n2
0
MD0n1
0
MD0n0
0
Operation mode of channel n
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TI0n pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Start trigger selection
001B: Selects the TI0n pin input valid edge.
Slave/master selectionNote
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channels n.
10B: Selects CK01 as operation clock of channels n.
Note If n = 0, Bit 11 is fixed at 0 of read only. Even if 1 is written to bit 11, become master channel.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (master channel output mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0, 2, 4, 6)
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Figure 6-64. Example of Set Contents of Registers When One-S hot Pu lse Out put F unctio n Is Used (Slav e Channe l)
(a) Timer mode register 0p (TMR0p)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0p CKS0p1
1/0
CKS0p0
0
0
CCS0p
0
M/S Note
0
STS0p2
1
STS0p1
0
STS0p0
0
CIS0p1
0
CIS0p0
0
0
0
MD0p3
1
MD0p2
0
MD0p1
0
MD0p0
0
Operation mode of channel p
100B: One-count mode
Start trigger during operation
0: Trigger input is invalid.
Selection of TI0p pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
0: 16-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel p.
10B: Selects CK01 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit p
TO0 TO0p
1/0
0: Outputs 0 from TO0p.
1: Outputs 1 from TO0p.
(c) Timer output enable register 0 (TOE0)
Bit p
TOE0 TOE0p
1/0
0: Stops the TO0p output operation by counting operation.
1: Enables the TO0p output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit p
TOL0 TOL0p
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit p
TOM0 TOM0p
1
1: Sets the slave channel output mode.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR00, TMR05, TMR07: 0 fixed
Remark n: Master channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable registers 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Sets timer mode register 0n, mp (TMR0n, TMR0p) of two
channels to be used (determines operation mode of
channels).
An output delay is set to timer data register 0n (TDR0n)
of the master channel, and a pulse width is set to the
TDR0p register of the slave channel.
Sets Noise filter enable register 1 (NFEN1) of the master
channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOM0p bit of timer output mode register 0 (TOM0)
is set to 1 (slave channel output mode).
Sets the TOL0p bit.
Sets the TO0p bit and determines default level of the
TO0p output.
Sets the TOE0p bit to 1 and enables operation of TO0p.
Clears the port register and port mode register to 0.
The TO0p pin goes into Hi-Z output state.
The TO0p default setting level is output when the port
mode register is in output mode and the port register is 0.
TO0p does not change because channel stops operating.
The TO0p pin outputs the TO0p set level.
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-65. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation Hardware Status
Sets the TOE0p bit (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0p (slave) bits of timer
channel start register 0 (TS0) are set to 1 at the same
time.
The TS0n and TS0p bits automatically return to 0
because they are trigger bits.
The TE0n and TE0p bits are set to 1 and the master
channel enters the TI0n input edge detection wait status.
Counter stops operating.
Operation
start
Detects the TI0n pin input valid edge of master channel. Master channel starts counting.
During
operation
Set values of only the CIS0n1 and CIS0n0 bits of the
TMR0n register can be changed.
Set values of the TMR0p, TDR0n, TDR0p registers,
TOM0n, TOM0p, TOL0n, and TOL0p bits cannot be
changed.
The TCR0n and TCR0p registers can always be read.
The TSR0n and TSR0p registers are not used.
Set values of the TO0 and TOE0 registers of slave
channel can be changed.
Master channel loads the value of the TDR0n register to
timer count register 0n (TCR0n) when the TI0n pin valid
input edge is detected, and the counter starts counting
down. When the count value reaches TCR0n = 0000H,
the INTTM0n output is generated, and the counter stops
until the next valid edge is input to the TI0n pin.
The slave channel, triggered by INTTM0n of the master
channel, loads the value of the TDR0p register to the
TCR0p register, and the counter starts counting down.
The output level of TO0p becomes active one count clock
after generation of INTTM0n from the master channel. It
becomes inactive when TCR0p = 0000H, and the counting
operation is stopped.
After that, the above operation is repeated.
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
TE0n, TE0p = 0, and count operation stops.
The TCR0n and TCR0p registers hold count value and
stop.
The TO0p output is not initialized but holds current
status.
Operation
stop
The TOE0p bit of slave channel is cleared to 0 and value
is set to the TO0p bit.
The TO0p pin outputs the TO0p set level.
To hold the TO0p pin output level
Clears the TO0p bit to 0 after the value to
be held is set to the port register.
When holding the TO0p pin output level is not
necessary
Setting not required.
The TO0p pin output level is held by port function.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0. Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p bit is cleared to 0 and the TO0p pin is set to
port mode.)
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
Operation is resumed.
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6.8.2 Operation as PWM function
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDR0p (slave)}/{Set value of TDR0n (master) + 1} × 100
0% output: Set value of TDR0p (slave) = 0000H
100% output: Set value of TDR0p (slave) ≥ {Set value of TDR0n (master) + 1}
Remark The duty factor exceeds 100% if the set value of TDR0p (slave) > (set value of TDR0n (master) + 1), it
summarizes to 100% output.
The master channel operates in the interval timer mode. If the channel start trigger bit (TS0n) of timer channel start
register 0 (TS0) is set to 1, an interrupt (INTTM0n) is output, the value set to timer data register 0n (TDR0n) is loaded to
timer count register 0n (TCR0n), and the counter counts down in synchronization with the count clock. When the counter
reaches 0000H, INTTM0n is output, the value of the TDR0n register is loaded again to the TCR0n register, and the
counter counts down. This operation is repeated until the channel stop trigger bit (TTmn) of timer channel stop register 0
(TTm) is set to 1.
If two channels are used to output a PWM waveform, the period until the master channel counts down to 0000H is the
PWM output (TO0p) cycle.
The slave channel operates in one-count mode. By using INTTM0n from the master channel as a start trigger, the
TCR0p register loads the value of the TDR0p register and the counter counts down to 0000H. When the counter reaches
0000H, it outputs INTTM0p and waits until the next start trigger (INTTM0n from the master channel) is generated.
If two channels are used to output a PWM waveform, the period until the slave channel counts down to 0000H is the
PWM output (TO0p) duty.
PWM output (TO0p) goes to the active level one clock after the master channel generates INTTM0n and goes to the
inactive level when the TCR0p register of the slave channel becomes 0000H.
Caution To rewrite both timer data register 0n (TDR0n) of the master channel and the TDR0p register of the
slave channel, a write access is necessary two times. The timing at which the values of the TDR0n
and TDR0p registers are loaded to the TCR0n and TCR0p registers is upon occurrence of INTTM0n of
the master channel. Thus, when rewriting is performed split before and after occurrence of INTTM0n
of the master channel, the TO0p pin cannot output the expected waveform. To rewrite both the
TDR0n register of the master and the TDR0p register of the slave, therefore, be sure to rewrite both
the registers immediately after INTTM0n is generated from the master channel.
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-66. Block Diagram of Operation as PWM Function
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TS0n
Interrupt signal
(INTTM0p)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TO0p pin
Output
controller
Master channel
(interval timer mode)
Slave channel
(one-count mode)
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Timer counter
register 0p (TCR0p)
Timer data
register 0p (TDR0p)
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-1. Example of Basic Timing of Operation as PWM Function
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a b
0000H
TS0p
TE0p
TDR0p
TCR0p
TO0p
INTTM0p
c
c
d
0000H
cd
Master
channel
Slave
channel
a+1 a+1 b+1
FFFFH
FFFFH
Remark 1. n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
2. TS0n, TS0p: Bit n, p of timer channel start register 0 (TS0)
TE0n, TE0p: Bit n, p of timer channel enable status register 0 (TE0)
TCR0n, TCR0p: Timer count registers mn, mp (TCR0n, TCR0p)
TDR0n, TDR0p: Timer data registers mn, mp (TDR0n, TDR0p)
TO0n, TO0p: TO0n and TO0p pins output signal
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Figure 6-68. Example of Set Cont en ts of Registers When PWM Function (Master Channel) Is Used
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
0
0
CCS0n
0
MAS
TERmn
1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
Note If n = 0, Bit 11 is fixed at 0 of read only. Even if 1 is written to bit 11, become master channel.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (master channel output mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0, 2, 4, 6)
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Figure 6-69. Example of Set Contents of Registers When PWM Function (Slave Channel) Is Used
(a) Timer mode register 0p (TMR0p)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0p CKS0p1
1/0
CKS0p0
0
0
CCS0p
0
M/S Note
0
STS0p2
1
STS0p1
0
STS0p0
0
CIS0p1
0
CIS0p0
0
0
0
MD0p3
1
MD0p2
0
MD0p1
0
MD0p0
1
Operation mode of channel p
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TI0p pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Setting of MASTER0p/SPLIT0p bit
0: Slave channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel p.
10B: Selects CK01 as operation clock of channel p.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit p
TO0 TO0p
1/0
0: Outputs 0 from TO0p.
1: Outputs 1 from TO0p.
(c) Timer output enable register 0 (TOE0)
Bit p
TOE0 TOE0p
1/0
0: Stops the TO0p output operation by counting operation.
1: Enables the TO0p output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit p
TOL0 TOL0p
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit p
TOM0 TOM0p
1
1: Sets the slave channel output mode.
Note TMR01, TMR03: SPLIT0p bit
TMR05, TMR07: 0 fixed
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-70. Operation Procedure When PWM Function Is Used (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Sets timer mode registers mn, mp (TMR0n, TMR0p) of
two channels to be used (determines operation mode of
channels).
An interval (period) value is set to timer data register 0n
(TDR0n) of the master channel, and a duty factor is set
to the TDR0p register of the slave channel.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channel.
The TOM0p bit of timer output mode register 0 (TOM0)
is set to 1 (slave channel output mode).
Sets the TOL0p bit.
Sets the TO0p bit and determines default level of the
TO0p output.
Sets the TOE0p bit to 1 and enables operation of TO0p.
Clears the port register and port mode register to 0.
The TO0p pin goes into Hi-Z output state.
The TO0p default setting level is output when the port
mode register is in output mode and the port register is 0.
TO0p does not change because channel stops operating.
The TO0p pin outputs the TO0p set level.
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
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Figure 6-70. Operation Procedure When PWM Function Is Used (2/2)
Software Operation Hardware Status
Operation
start
Sets the TOE0p bit (slave) to 1 (only when operation is
resumed).
The TS0n (master) and TS0p (slave) bits of timer
channel start register 0 (TS0) are set to 1 at the same
time.
The TS0n and TS0p bits automatically return to 0
because they are trigger bits.
TE0n = 1, TE0p = 1
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMR0n and TMR0p registers, TOM0n,
TOM0p, TOL0n, and TOL0p bits cannot be changed.
Set values of the TDR0n and TDR0p registers can be
changed after INTTM0n of the master channel is
generated.
The TCR0n and TCR0p registers can always be read.
The TSR0n and TSR0p registers are not used.
The counter of the master channel loads the TDR0n
register value to timer count register 0n (TCR0n), and
counts down. When the count value reaches TCR0n =
0000H, INTTM0n output is generated. At the same time,
the value of the TDR0n register is loaded to the TCR0n
register, and the counter starts counting down again.
At the slave channel, the value of the TDR0p register is
loaded to the TCR0p register, triggered by INTTM0n of
the master channel, and the counter starts counting down.
The output level of TO0p becomes active one count clock
after generation of the INTTM0n output from the master
channel. It becomes inactive when TCR0p = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
TE0n, TE0p = 0, and count operation stops.
The TCR0n and TCR0p registers hold count value and
stop.
The TO0p output is not initialized but holds current
status.
Operation
stop
The TOE0p bit of slave channel is cleared to 0 and value
is set to the TO0p bit.
The TO0p pin outputs the TO0p set level.
To hold the TO0p pin output level
Clears the TO0p bit to 0 after the value to
be held is set to the port register.
When holding the TO0p pin output level is not
necessary
Setting not required.
The TO0p pin output level is held by port function.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p bit is cleared to 0 and the TO0p pin is set to
port mode.)
Remark n: Channel number (n = 0, 2, 4, 6)
p: Slave channel number (n < p ≤ 7)
Operation is resumed.
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6.8.3 Operation as multiple PWM output fu n ctio n
By extending the PWM function and using multiple slave channels, many PWM waveforms with different duty values
can be output.
For example, when using two slave channels, the period and duty factor of an output pulse can be calculated by the
following expressions.
Pulse period = {Set value of TDR0n (master) + 1} × Count clock period
Duty factor 1 [%] = {Set value of TDR0p (slave 1)}/{Set value of TDR0n (master) + 1} × 100
Duty factor 2 [%] = {Set value of TDR0q (slave 2)}/{Set value of TDR0n (master) + 1} × 100
Remark Although the duty factor exceeds 100% if the set value of TDR0p (slave 1) > {set value of TDR0n
(master) + 1} or if the {set value of TDR0q (slave 2)} > {set value of TDR0n (master) + 1}, it is
summarized into 100% output.
Timer count register 0n (TCR0n) of the master channel operates in the interval timer mode and counts the periods.
The TCR0p register of the slave channel 1 operates in one-count mode, counts the duty factor, and outputs a PWM
waveform from the TO0p pin. The TCR0p register loads the value of timer data register 0p (TDR0p), using INTTM0n of
the master channel as a start trigger, and starts counting down. When TCR0p = 0000H, TCR0p outputs INTTM0p and
stops counting until the next start trigger (INTTM0n of the master channel) has been input. The output level of TO0p
becomes active one count clock after generation of INTTM0n from the master channel, and inactive when TCR0p = 0000H.
In the same way as the TCR0p register of the slave channel 1, the TCR0q register of the slave channel 2 operates in
one-count mode, counts the duty factor, and outputs a PWM waveform from the TO0q pin. The TCR0q register loads the
value of the TDR0q register, using INTTM0n of the master channel as a start trigger, and starts counting down. When
TCR0q = 0000H, the TCR0q register outputs INTTM0q and stops counting until the next start trigger (INTTM0n of the
master channel) has been input. The output level of TO0q becomes active one count clock after generation of INTTM0n
from the master channel, and inactive when TCR0q = 0000H.
When channel 0 is used as the master channel as above, up to seven types of PWM signals can be output at the same
time.
Caution To rewrite both timer data register 0n (TDR0n) of the master channel and the TDR0p register of the
slave channel 1, w rite access is necessary at least tw ice. Since the values of the TDR0n and TDR0p
registers are loaded to the TCR0n and TCR0p registers after INTTM0n is generated from the master
channel, if rewriting is performed separately before and after generation of INTTM0n from the master
channel, the TO0p pin cannot output the expected waveform. To rewrite both the TDR0n register of
the master and the TDR0p register of the slave, be sure to rewrite both the registers immediately
after INTTM0n is generated from the master channel (This applies also to the TDR0q register of the
slave channel 2).
Remark n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are consecutive integers greater than n)
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Figure 6-71. Block Diagram of Operation as Multiple PWM Output Function (output two types of PWMs)
Interrupt signal
(INTTM0n)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TS0n
Interrupt signal
(INTTM0p)
Interrupt
controller
Clock selection
Trigger selection
Operation clock
CK00
CK01
TO0p pin
Output
controller
Master channel
(interval timer mode)
Slave channel 1
(one-count mode)
Interrupt signal
(INTTM0q)
Interrupt
controller
Clock selection
Trigger selection
Operation clock CK00
CK01
TO0q pin
Output
controller
Slave channel 2
(one-count mode)
Timer counter
register 0n (TCR0n)
Timer data
register 0n (TDR0n)
Timer counter
register 0p (TCR0p)
Timer data
register 0p (TDR0p)
Timer counter
register 0q (TCR0q)
Timer data
register 0q (TDR0q)
Remark n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are consecutive integers greater than n)
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Figure 6-72. Example of Basic T iming of Operation as Multiple PWM Output Function
(Output two types of PWMs) (1/2)
TS0n
TE0n
TDR0n
TCR0n
TO0n
INTTM0n
a b
0000H
TS0p
TE0p
TDR0p
TCR0p
TO0p
INTTM0p
c
c
d
0000H
cd
Master
channel
Slave
channel 1
a+1 a+1 b+1
FFFFH
FFFFH
TS0q
TE0q
TDR0q
TCR0q
TO0q
INTTM0q
ef
0000H
ef
Slave
channel 2
a+1 a+1 b+1
FFFFH
ef
d
(Remark is listed on the next page.)
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Figure 6-72. Example of Basic T iming of Operation as Multiple PWM Output Function
(Output two types of PWMs) (2/2)
Remarks 1. n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are consecutive integers greater than n)
2. TS0n, TS0p, TS0q: Bit n, p, q of timer channel start register 0 (TS0)
TE0n, TE0p, TE0q: Bit n, p, q of timer channel enable status register 0 (TE0)
TCR0n, TCR0p, TCR0q: Timer count registers mn, mp, mq (TCR0n, TCR0p, TCR0q)
TDR0n, TDR0p, TDR0q: Timer data registers mn, mp, mq (TDR0n, TDR0p, TDR0q)
TO0n, TO0p, TO0q: TO0n, TO0p, and TO0q pins output signal
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Figure 6-73. Example of Set Contents of Registers
When Multiple PWM Output Function (Master Channel) Is Used
(a) Timer mode register 0n (TMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0n CKS0n1
1/0
CKS0n0
0
0
CCS0n
0
MAS
TERmn
1
STS0n2
0
STS0n1
0
STS0n0
0
CIS0n1
0
CIS0n0
0
0
0
MD0n3
0
MD0n2
0
MD0n1
0
MD0n0
1
Operation mode of channel n
000B: Interval timer
Setting of operation when counting is started
1: Generates INTTM0n when counting is
started.
Selection of TI0n pin input edge
00B: Sets 00B because these are not used.
Start trigger selection
000B: Selects only software start.
Slave/master selection
1: Master channel.
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel n.
10B: Selects CK01 as operation clock of channel n.
(b) Timer output register 0 (TO0)
Bit n
TO0 TO0n
0
0: Outputs 0 from TO0n.
(c) Timer output enable register 0 (TOE0)
Bit n
TOE0 TOE0n
0
0: Stops the TO0n output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit n
TOL0 TOL0n
0
0: Cleared to 0 when TOM0n = 0 (master channel output mode).
(e) Timer output mode register 0 (TOM0)
Bit n
TOM0 TOM0n
0
0: Sets master channel output mode.
Remark n: Channel number (n = 0, 2, 4)
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Figure 6-74. Example of Set Contents of Registers
When Multiple PWM Output Function (Slave Channel) Is Used (output two types of PWMs)
(a) Timer mode register 0p, mq (TMR0p, TMR0q)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0p CKS0p1
1/0
CKS0p0
0
0
CCS0p
0
M/S Note
0
STS0p2
1
STS0p1
0
STS0p0
0
CIS0p1
0
CIS0p0
0
0
0
MD0p3
1
MD0p2
0
MD0p1
0
MD0p0
1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMR0q CKS0q1
1/0
CKS0q0
0
0
CCS0q
0
M/S Note
0
STS0q2
1
STS0q1
0
STS0q0
0
CIS0q1
0
CIS0q0
0
0
0
MD0q3
1
MD0q2
0
MD0q1
0
MD0q0
1
Operation mode of channel p, q
100B: One-count mode
Start trigger during operation
1: Trigger input is valid.
Selection of TI0p and TI0q pins input edge
00B: Sets 00B because these are not used.
Start trigger selection
100B: Selects INTTM0n of master channel.
Setting of MASTERmn bit (Channel 2, 4, 6)
0: Independent channel operation.
Setting of SPLITmn bit (Channel 1, 3)
0: 16-bit timer
Count clock selection
0: Selects operation clock (fMCK).
Operation clock (fMCK) selection
00B: Selects CK00 as operation clock of channel p, q.
10B: Selects CK01 as operation clock of channel p, q.
* Make the same setting as master channel.
(b) Timer output register 0 (TO0)
Bit q Bit p
TO0 TO0q
1/0
TO0p
1/0
0: Outputs 0 from TO0p or TO0q.
1: Outputs 1 from TO0p or TO0q.
(c) Timer output enable register 0 (TOE0)
Bit q Bit p
TOE0 TOE0q
1/0
TOE0p
1/0
0: Stops the TO0p or TO0q output operation by counting operation.
1: Enables the TO0p or TO0q output operation by counting operation.
(d) Timer output level register 0 (TOL0)
Bit q Bit p
TOL0 TOL0q
1/0
TOL0p
1/0
0: Positive logic output (active-high)
1: Negative logic output (active-low)
(e) Timer output mode register 0 (TOM0)
Bit q Bit p
TOM0 TOM0q
1
TOM0p
1
1: Sets the slave channel output mode.
Note TMR02, TMR04, TMR06: MASTER0n bit
TMR01, TMR03: SPLIT0n bit
TMR05, TMR07: 0 fixed
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are consecutive integers greater than n)
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Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (1/2)
Software Operation Hardware Status
Power-off status
(Clock supply is stopped and writing to each register is
disabled.)
Sets the TAU0EN bit of peripheral enable register 0
(PER0) to 1.
Power-on status. Each channel stops operating.
(Clock supply is started and writing to each register is
enabled.)
TAU
default
setting
Sets timer clock select register 0 (TPS0).
Determines clock frequencies of CK00 and CK01.
Sets timer mode registers mn, mp, 0q (TMR0n, TMR0p,
TMR0q) of each channel to be used (determines
operation mode of channels).
An interval (period) value is set to timer data register 0n
(TDR0n) of the master channel, and a duty factor is set
to the TDR0p and TDR0q registers of the slave
channels.
Channel stops operating.
(Clock is supplied and some power is consumed.)
Channel
default
setting
Sets slave channels.
The TOM0p and TOM0q bits of timer output mode
register 0 (TOM0) are set to 1 (slave channel output
mode).
Sets the TOL0p and TOL0q bits.
Sets the TO0p and TO0q bits and determines default
level of the TO0p and TO0q outputs.
Sets the TOE0p and TOE0q bits to 1 and enables
operation of TO0p and TO0q.
Clears the port register and port mode register to 0.
The TO0p and TO0q pins go into Hi-Z output state.
The TO0p and TO0q default setting levels are output when
the port mode register is in output mode and the port
register is 0.
TO0p and TO0q do not change because channels stop
operating.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
Remark n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
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Figure 6-75. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Software Operation Hardware Status
Operation
start
(Sets the TOE0p and TOE0q (slave) bits to 1 only when
resuming operation.)
The TS0n bit (master), and TS0p and TS0q (slave) bits of
timer channel start register 0 (TS0) are set to 1 at the
same time.
The TS0n, TS0p, and TS0q bits automatically return to
0 because they are trigger bits.
TE0n = 1, TE0p, TE0q = 1
When the master channel starts counting, INTTM0n is
generated. Triggered by this interrupt, the slave
channel also starts counting.
During
operation
Set values of the TMR0n, TMR0p, TMR0q registers,
TOM0n, TOM0p, TOM0q, TOL0n, TOL0p, and TOL0q
bits cannot be changed.
Set values of the TDR0n, TDR0p, and TDR0q registers
can be changed after INTTM0n of the master channel is
generated.
The TCR0n, TCR0p, and TCR0q registers can always be
read.
The TSR0n, TSR0p, and TSR0q registers are not used.
The counter of the master channel loads the TDR0n
register value to timer count register 0n (TCR0n) and
counts down. When the count value reaches TCR0n =
0000H, INTTM0n output is generated. At the same time,
the value of the TDR0n register is loaded to the TCR0n
register, and the counter starts counting down again.
At the slave channel 1, the values of the TDR0p register
are transferred to the TCR0p register, triggered by
INTTM0n of the master channel, and the counter starts
counting down. The output levels of TO0p become active
one count clock after generation of the INTTM0n output
from the master channel. It becomes inactive when TCR0p
= 0000H, and the counting operation is stopped.
At the slave channel 2, the values of the TDR0q register
are transferred to TCR0q regster, triggered by INTTM0n of
the master channel, and the counter starts counting down.
The output levels of TO0q become active one count clock
after generation of the INTTM0n output from the master
channel. It becomes inactive when TCR0q = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
TE0n, TE0p, TE0q = 0, and count operation stops.
The TCR0n, TCR0p, and TCR0q registers hold count
value and stop.
The TO0p and TO0q output are not initialized but hold
current status.
Operation
stop
The TOE0p and TOE0q bits of slave channels are
cleared to 0 and value is set to the TO0p and TO0q bits.
The TO0p and TO0q pins output the TO0p and TO0q set
levels.
To hold the TO0p and TO0q pin output levels
Clears the TO0p and TO0q bits to 0 after
the value to be held is set to the port register.
When holding the TO0p and TO0q pin output levels are
not necessary
Setting not required
The TO0p and TO0q pin output levels are held by port
function.
TAU
stop
The TAU0EN bit of the PER0 register is cleared to 0.
Power-off status
All circuits are initialized and SFR of each channel is
also initialized.
(The TO0p and TO0q bits are cleared to 0 and the
TO0p and TO0q pins are set to port mode.)
Remark n: Channel number (n = 0, 2, 4)
p: Slave channel number 1, q: Slave channel number 2
n < p < q ≤ 7 (Where p and q are a consecutive integer greater than n)
Operation is resumed.
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6.9 Cautions When Using Ti mer Array Unit
6.9.1 Cautions When Using Timer outpu t
Depends on products, a pin is assigned atimer output and other alternate functions. In this case, outputs of the other
alternate functions must be set in initial status.
(1) 20-, 24-pin products
(a) Using TO02 output assigned to the P41
So that the alternated SO01/SDA01 output becomes 1, not only set the port mode register (the PM41 bit) and
the port register (the P41 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE01 =.
0, SO01 = 1, SOE01 = 0).
(b) Using TO03 output assigned to the P42
So that the alternated SCK01/SCL01 output becomes 1, not only set the port mode register (the PM42 bit) and
the port register (the P17 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE01 =
0, SO01=1, SOE01=0).
(2) 30-pin products
(a) Using TO03 output assigned to the P31
So that the alternated PCLBUZ0 output becomes 0, not only set the port mode register (the PM31 bit) and the
port register (the P31 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting 0 as the initial status.
(b) Using TO07 output assigned to the P10 (When PIOR0 = 1)
So that the alternated SCK00/SCL00 output becomes 1, not only set the port mode register (the PM10 bit) and
the port register (the P10 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE00 =
0, SO00=1, SOE00=0).
(c) Using TO06 output assigned to the P11 (When PIOR0 = 1)
So that the alternated SDA00 output becomes 1, not only set the port mode register (the PM11 bit) and the port
register (the P11 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output register 0
(SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE11 = 0, SO11=1,
SOE11=0).
(d) Using TO05 output assigned to the P12 (When PIOR0 = 1)
So that the alternated SO00/TxD0 output becomes 1, not only set the port mode register (the PM12 bit) and
the port register (the P12 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE12 =
0, SO12=1, SOE12=0).
(e) Using TO04 output assigned to the P13 (When PIOR0 = 1)
So that the alternated TxD2/SO20 output becomes 1, not only set the port mode register (the PM13 bit) and
the port register (the P13 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE13 =
0, SO13=1, SOE13=0).
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(f) Using TO03 output assigned to the P14 (When PIOR0 = 1)
So that the alternated SDA20 output becomes 1, not only set the port mode register (the PM14 bit) and the
port register (the P14 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE14 =
0, SO14=1, SOE14=0).
(g) Using TO02 output assigned to the P15 (When PIOR0 = 1)
So that the alternated SCK20/SCL20 output becomes 1, not only set the port mode register (the PM15 bit) and
the port register (the P15 bit) to 0, but also use the serial channel enable status register 0 (SE0), serial output
register 0 (SO0), and serial output enable register 0 (SOE0) with the same setting as the initial status (SE15 =
0, SO15=1, SOE15=0).
And that the alternated PCLBUZ1 output becomes 1, but also use the bit 7 (PCLOE1) of clock output select
register 1 (CKS1) with the same setting 0 as the initial status
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CHAPTER 7 12-BIT INTERVAL TIMER
7.1 Functions of 12-bit Interval Timer
An interrupt (INTIT) is generated at any previously specified time interval. It can be utilized for wakeup from STOP
mode and triggering an A/D converter’s SNOOZE mode.
7.2 Configuration of 12-bit Interv al Timer
The 12-bit interval timer includes the following hardware.
Table 7-1. Configuration of 12-bit Interval Timer
Item Configuration
Counter 12-bit counter
Peripheral enable register 0 (PER0)
Operation speed mode control register (OSMC)
Control registers
Interval timer control register (ITMC)
Figure 7-1. Block Diagram of 12-bit Interval Timer
WUTMM
CK0
Operation speed mode
control register (OSMC)
Interrupt signal (INTIT)
f
IL
RINTE ITMCMP11 to ITMCMP0
Interval timer control
register (ITMC)
Count clock
Match singnal
Clear
12-bit counter
Internal bus
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7.3 Registers Controlling 12-bit Interv al Timer
The 12-bit interval timer is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Operation speed mode control register (OSMC)
• Interval timer control register (ITMC)
7.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to the
hardware that is not used is also stopped so as to decrease the power consumption and noise.
When using the 12-bit interval timer, be sure to set bit 7 (TMKAEN) to 1 at first.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 7-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN
IICA0EN
SAU1EN SAU0EN 0 TAU0EN
TMKAEN Control of clock (fIL) for register access of 12-bit interval timer
0 Stops input clock supply.
• SFR used by the 12-bit interval timer cannot be written.
• The 12-bit interval timer is in the reset status.
1 Enables input clock supply.
• SFR used by the 12-bit interval timer can be read and written.
Cautions 1. When using the 12-bit interval timer, first set the TMKAEN bit to 1. If TMKAEN = 0, writing to a
control register of the 12-bit interval timer is ignored, and, even if the register is read, only the
default value is read.
2 Be sure to clear undefined bits to 0.
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7.3.2 Operation speed mode contro l reg ister (OSMC)
The WUTMMCK0 bit can be used to control supply of the 12-bit interval timer operation clock.
The OSMC register can be set by an 8-bit memor y manipula tion instruction.
Reset signal generation clears this register to 00H.
Figure 7-3. Format of Operation Speed Mode Control Register (OSMC)
Address: F00F3H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
OSMC 0 0 0
WUTMMCK0
0 0 0 0
WUTMMCK0
Supply of operation clock for 12-bit interval timer
0 Clock supply stop.
1 Low-speed on-chip oscillator clock (fIL) supply
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7.3.3. Interval timer control register (ITMC)
This register is used to set up the starting and stopping of the 12-bit interval timer operation and to specify the timer
compare value.
The ITMC register can be set b y a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0FFFH.
Figure 7-4. Format of Interval Timer Control Register (ITMC)
Address: FFF90H After reset: 0FFFH R/W
Symbol 15 14 13 12 11 to 0
ITMC RINTE 0 0 0 ITCMP11 to ITCMP0
RINTE 12-bit interval timer operation control
0 Count operation stopped (count clear)
1 Count operation started
ITCMP11 to ITCMP0 Specification of the 12-bit interval timer compare value
001H
•
•
•
FFFH1
These bits generate an interrupt at the fixed cycle (count clock cycles x (ITCMP
setting + 1)).
Example interrupt cycles when 001H or FFFH is specified for ITCMP11 to ITCMP0
• ITCMP11 to ITCMP0 = 001H, count clock: when fIL = 15 kHz
1/15 [kHz] × (1 + 1) ÷ 0.1333 [ms] = 133.3 [
μ
s]
• ITCMP11 to ITCMP0 = FFFH, count clock: when fIL = 15 kHz
1/15 [kHz] × (4095 + 1) ÷ 273 [ms]
Cautions 1. When RINTE bit is changed from 0 to 1, set WUTMMCK0 bit of OSMC register to 1 before the
change so that the operation clock is estab lish ed .
2. Before changing the RINTE bit from 1 to 0, use the interrupt mask flag register to disable the
INTIT interrupt servicing. When operation starts (0 to 1) again, clear the TMKAIF flag, and
then enable the interrup t servicing.
3. The value read from the RINTE bit is applied one count clock cycle after setting the RINTE bit.
4. When setting the RINTE bit after returned from standby mode and entering standby mode
again, confirm that the written value of the RINTE bit is reflected, or wait that more than one
clock of the count clock has elapsed after returned from standby mode. Then enter standby
mode.
5. Only change the setting of the ITCMP11 to ITCMP0 bits w hen RINT E = 0.
How ever, it is possible to change th e settings of the IT CMP11 to ITCMP0 bits at the same time
as when changin g RINTE from 0 to 1 or 1 to 0.
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7.4 12-bit Interval Timer Operation
The count value specified for the ITCMP11 to IT CMP0 bits is used as an interval to operate an 1 2-bit interval timer that
repeatedly generates interrupt requests (INTIT).
When the RINTE bit is set to 1, the 12-bit counter starts counting.
When the 12-bit counter value matches the value specified for the IT CMP11 to ITCMP0 bits, the 12-bit counter value is
cleared to 0, counting continues, and an interrupt request signal (INTIT) is generated at the same time.
The basic operation of the 12- bit interval time r is shown in Figure 7-5.
Figure 7-5. 12-bit Interval Timer Operation Timing
(ITCMP11 to ITCMP0 = 0FFH, count clock: fIL = 15 kHz)
INTIT
RINTE
0FFH
000H
0FFH
ITCMP11 to
ITCMP0
Count clock
12-bit counter
After RINTE is changed from 0 to 1, counting starts
at the two fall of the count clock signal.
When RINTE is changed from 1 to 0,
the 12-bit counter is cleared without
synchronization with the count clock.
Period (17.06 ms)
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CHAPTER 8 CLOCK OUTPUT/B UZZER OUTPUT CONTROLLER.
8.1 Functions of Clock Output/Buzzer Outp ut Controller
The clock output controller is intended for carrier output during remote controlled transmission and clock output for
supply to peripheral ICs.
Buzzer output is a function to output a square wave of buzzer frequency.
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 or PCLBUZ1 pin outputs a clock selected by clock output select register 0, 1 (CKS0, CKS1).
Figure 8-1 shows the block di agram of clock output/buzzer output controller.
Figure 8-1. Block Diagram of Clock Output/Buzzer Output Controller
Note The PCLBUZ0 or PCLBUZ1 pin can output a freque ncy, refer to 28.4 AC Characteristics.
PCLBUZ1 output function is available only in 30-pin products.
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8.2 Configuration of Clock Output/Bu zzer Output Controller
The clock output/buzzer output controller includes the following hardware.
Table 8-1. Configuration of Clock Output/Buzzer Output Controller
Item Configuration
Control registers Clock output select registers 0, 1 (CKS0, CKS1)
Port mode register 1, 3 (PM1, PM3)
Port register 1, 3 (P1, P3)
8.3 Registers Controlling Clock Output/Buz zer Output Controller
The following two registers are used to control the clock output/buzzer o utput control ler.
• Clock output select registers 0, 1 (CKS0, CKS1)
• Port mode register 1, 3 (PM1, PM3)
8.3.1 Clock output select registers 0, 1 (CKS0, CKS1)
These registers set output enable/disable for clock output or for the buzzer frequency output pin (PCLBUZ0 or
PCLBUZ1), and set the output clock.
Select the clock to be output from the PCLBUZ0 pin by using the CKS0 register.
The CKS0 or CKS1 register are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
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Figure 8-2. Format of Clock Output Select Register n (CKSn)
Address: FFFA5H (CKS0), FFFA6 (CKS1) After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CKSn PCLOEn 0 0 0 0 CCSn2 CCSn1 CCSn0
PCLOEn PCLBUZn pin output enable/disable specification
0 Output disable (default)
1 Output enable
PCLBUZn pin output clock selection
fMAIN (MHz)
CCSn2 CCSn1 CCSn0
5 10 16 20 24
0 0 0 fMAIN 5 MHz 10 MHzNote 16 MHz
Note
Setting
prohibited
Not
e
Setting
prohibited
Not
e
0 0 1 fMAIN/2 2.5 MHz 5 MHz 8 MHz Note 10 MHz
Note 12 MHz
Note
0 1 0 fMAIN/221.25 MHz 2.5 MHz 4 MHz 5 MHz 6 MHz
0 1 1 fMAIN/23625 kHz 1.25 MHz 2 MHz 2.5 MHz 3 MHz
1 0 0 fMAIN/24312.5 kHz 625 kHz 1 MHz 1.25 MHz 1.5 MHz
1 0 1 fMAIN/211 2.44 kHz 4.88 kHz 7.81 kHz 9.77 kHz 11.72 kHz
1 1 0 fMAIN/212 1.22 kHz 2.44 kHz 3.91 kHz 4.88 kHz 5.86 kHz
1 1 1 fMAIN/213 610 Hz 1.22 kHz 1.95 kHz 2.44 kHz 2.93 kHz
Note Use the output clock within a range of 10 MHz. Furthermore, when using the output clock at 2.7 V ≤ VDD < 4.0
V, use it within 8 MHz. For detail, refer to 28.4 AC characteristics.
Cautions 1. Change the output clock after disabling clock output (PCLOEn = 0).
2. To shift to STOP mode, set PCLOEn = 0 before executing the STOP instruction.
Remarks 1. n = 0, 1
2. fMAIN: Main s ystem clock frequenc y
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8.3.2 Port mode register 1, 3 (PM1, PM3)
This register sets input/output of port 1, 3 in 1-bit units.
When using the P10/PCLBU Z0 pin (20- and 24-pin products) or P15/PCLBUZ1, P31/PCLBUZ0 (30-pin products) for
clock output and buzzer outpu t, clear PM10, PM15, or PM31 bits and the output latches of P10, P15, or P31 to 0.
And the 20- and 24-pin products, set 0 to PMC10 bit for port mode control register 1.
The PM1. PM3 register can be set by a 1-bit or 8-bit memory manipulation instructio n.
Reset signal generation sets these registers to FFH.
Figure 8-3. Format of Port Mode Register 1, 3 (PM1, PM3)
20-, 24-pin product
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
30-pin product
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W
PMmn Pmn pin I/O mode selection (mn = 10 to 17, 30 or 31)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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8.4 Operations of Clock Output/Buzzer Output Controller
One pin can be used to output a clock or buzzer sound.
The PCLBUZ0 pin outputs a clock/buzzer se lected by the clock output select register 0 (CKS0).
The PCLBUZ1 pin outputs a clock/buzzer se lected by the clock output select register 1 (CKS1).
8.4.1 Operation as output pin
The PCLBUZn pin is output as the following proced ure.
<1> Select the output frequency with bits 0 to 3 (CCSn0 to CCS n2, CSELn) of the clock outpu t select register (CKSn)
of the PCLBUZn pin (output in disabled).
<2> Set bit 7 (PCLOEn) of the CKSn register to 1 to enable clock/buzzer output.
Remarks 1. The controller used for output ting the clock starts or stops outputting the clock one clock after enabl ing or
disabling clock output (PCLOEn bit) is s witc hed. At this time, pulses with a narrow width are not output.
Figure 8-5 shows enabling or stopping output using the PCLOEn bit and the timing of outputting the clock.
2. n = 0 or 1
Figure 8-5. Remote Control Output Application Example
PCLOEn
1 clock elapsed
Narrow pulses are not recognized
Clock output
Caution After specifying the setting for stopping PCLBUZn output (PCLOEn = 0), if the STOP or HALT
instruction is executed at high-le vel output, the clock w idth may be shorter than th e selected value.
Execute the STOP or HALT instruction only when 1.5 clocks of the selected clock or more elapse
after specifying the setting for stopping PCLBUZn output.
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CHAPTER 9 WATCHDOG TIMER
9.1 Functions of Watchdog Timer
The watchdog timer operates on the low-speed on-chip oscillator clock.
The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset
signal is generated.
Program loop is detected in the following cas es.
• If the watchdog timer counter overflows
• If a 1-bit manipulation instruction is executed on the watchdog timer enable register (W DT E)
• If data other than “ACH” is written to the WDTE register
• If data is written to the WDTE register during a window close period
When a reset occurs due to the watchdog timer, bit 4 (WDT RF) of the reset control flag re gister (RESF) is set to 1. For
details of the RESF register, see CHAPTER 18 RESET FUNCTION.
When 75%+1/2fIL of the overflow time is reached, an interval interrupt can be generated.
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9.2 Configuration of Watchdog Timer
The watchdog timer includes the following hardware.
Table 9-1. Configuration of Watchdog Timer
Item Configuration
Control register Watchdog timer enable register (WDTE)
How the counter operation is controlled, overflow time, window open period, and i nterval interrupt are set by the option
byte.
Table 9-2. Setting of Option Bytes and Watchdog Timer
Setting of Watchdog Timer Option Byte (000C0H)
Watchdog timer interval interrupt Bit 7 (WDTINT)
Window open period Bits 6 and 5 (WINDOW1, WINDOW0)
Controlling counter operation of watchdog timer Bit 4 (WDTON)
Overflow time of watchdog timer Bits 3 to 1 (WDCS2 to WDCS0)
Controlling counter operation of watchdog timer
(in HALT/STOP mode) Bit 0 (WDSTBYON)
Remark For the option byte, see CHAPTER 23 OPTION BYTE.
Figure 9-1. Block Diagram of Watchdog Timer
fIL
WDTON of option
byte (000C0H)
WDTINT of option
byte (000C0H)
Interval time controller
(Count value overflow time x 3/4) Interval interrupt request
WDCS2 to WDCS0 of
option byte (000C0H)
Clock
input
controller
17-bit
counter Selector Overflow signal
Reset
output
controller
Internal reset signal
Count clear
signal Window size
decision signal
Window size check
Watchdog timer enable
register (WDTE)
Write detector to
WDTE except ACH
Internal bus
WINDOW1 and
WINDOW0 of option
byte (000C0H)
f
IL
/2
6
to f
IL
/2
16
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9.3 Register Controlling Watchdog Timer
The watchdog timer is controlled by the watchdog timer enable register (WDTE).
9.3.1 Watchdog timer enable register (WDTE)
Writing “ACH” to the WDTE register clears the watchdog timer counter and starts counting again.
This register can be set by an 8-bit memory manipulation i nstruction.
Reset signal generation sets this register to 1AH or 9AHNote.
Figure 9-2. Format of Watchdog Timer Enable Register (WDTE)
01234567
Symbol
WDTE
Address: FFFABH After reset: 1AH/9AH
Note
R/W
Note The WDTE register reset value differs depending on the WDTON bit setting value of the option byte
(000C0H). To operate watchdog timer, set the WDT O N bit to 1.
WDTON Bit Setting Value WDTE Register Reset Value
0 (watchdog timer count operation disabled) 1AH
1 (watchdog timer count operation enabled) 9AH
Cautions 1. If a value other than “ACH” is written to the WDTE register, an internal reset signal is
generated.
2. If a 1-bit memory mani pu latio n instru ction is execu ted for the WDTE register, an internal reset
signal is generated.
3. The value read from the WDTE register is 1AH/9AH (this differs from the written value (ACH)).
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9.4 Operation of Watchdog Timer
9.4.1 Controlling operation of watchdog timer
<1> When the watchdog timer is used, its operation is specified by the option byte (000C0H).
• Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option b yte (000C0H) to 1 (the
counter starts operating after a reset release) (for details, see CHAPTER 23).
WDTON Watchdog Timer Counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
• Set an overflow time by using bits 3 to 1 ( WDCS2 to WDCS0) of the opt ion byte (000C0H) (for d etails, see 9.4.2
and CHAPTER 23).
• Set a window open period by using bits 6 and 5 (WINDOW1 and WINDOW0) of the option byte (000C0H) (for
details, see 9.4.3 and CHAPTER 23).
<2> After a reset release, the watchdog timer starts counting.
<3> B y writing “ACH” to the watchdog timer ena ble regist er (WDTE) after the watchdog timer starts counting and before
the overflow time set by the option byte, the watchdog timer is cleared and starts counting again.
<4> After that, write the WDTE register the second time or later after a reset release during th e window open period. If
the WDTE register is written during a window close period, an internal reset signal is generated.
<5> If the overflow time expires without “ACH” written to the WDTE register, an internal reset signal is generated.
An internal reset signal is generated in the following cases.
• If a 1-bit manipulation instruction is executed on the WDTE register
• If data other than “ACH” is written to the WDTE register
Cautions 1. When data is written to the watchdog timer enable register (WDTE) for the first time after reset
release, the watchdog timer is cleared in any timing regardless of the window open time, as long
as the register is written before the overflow time, and the watchdog timer sta rts counting again.
2. If the watchdog timer is cleared by writing “ACH” to the WDTE register, the actual overflow time
may be different from the overflow time set by the option byte by up to 2/fIL seconds.
3. The watchdog timer can be cleared immediately before the count value overflows.
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Cautions 4. The operation of the watchdog timer in the HALT and STOP modes, and SNOOZE mode differs as
follows depending on the set value of bit 0 (WDSTBYON) of the option byte (000C0H).
WDSTBYON = 0 : Watchdog timer operation stops.
WDSTBYON = 1 : Watchdog timer operation continues.
If WDSTBYON = 0, the watchdog timer resumes counting after the HALT or STOP mode is
released. At this time, the counter is cleared to 0 and counting starts.
When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short,
an overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the
STOP mode release by an interval interrupt.
9.4.2 Setting overflow time of watchdog timer
Set the overflow time of the watchdog timer by using bits 3 to 1 (WDCS2 to WDCS0) of the option byte (000C0H).
If an overflow occurs, an internal reset sign al is generated. The present count is cl eared and the watchdog timer starts
counting again by writing “ACH” to the watchdog timer enable register (WDTE) during the window open period before the
overflow time.
The following overflow times can be set.
Table 9-3. Setting of Overflow Time of Watchdog Timer
WDCS2 WDCS1 WDCS0 Overflow Time of Watchdog Timer
(fIL = 17.25 kHz (MAX.))
0 0 0 26/fIL (3.71 ms)
0 0 1 27/fIL (7.42 ms)
0 1 0 28/fIL (14.84 ms)
0 1 1 29/fIL (29.68 ms)
1 0 0 211/fIL (118.72 ms)
1 0 1 213/fIL (474.90 ms)
1 1 0 214/fIL (949.80 ms)
1 1 1 216/fIL (3799.19 ms)
Remark f
IL: Low-speed on- chip oscillator clock frequency
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9.4.3 Setting window open period of watchdog timer
Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte
(000C0H). The outline of the window is as follows.
• If “ACH” is written to the watchdog timer enable register (WDT E) during the window open period, the watchdog timer
is cleared and starts counting again.
• Even if “ACH” is written to the WDTE register during the window close period, an abnormality is detected and an
internal reset signal is generated.
Example: If the window open period is 50%
Window close period (50%) Window close period (50%)
Counting
starts
Overflow
time
Counting starts again when
"ACH" is written to WDTE.
Internal reset signal is generated
if "ACH" is written to WDTE.
Caution When data is written to the WDTE register for the first time after reset release, the w atchdog timer is
cleared in any timing regardless of the window open time, as long as the register is written before the
overflow time, and the watchdog timer starts counting again.
The window open period can be set is as follows.
Table 9-4. Setting Window Open Period of Watchdog Timer
WINDOW1 WINDOW0 Window Open Period of Watchdog Timer
0 0 Setting prohibited
0 1 50%
1 0 75%
1 1 100%
Caution When bit 0 (WDSTBYON) of the option byte (000C0H) = 0, the window open period is 100%
regardless of the values of the WINDOW1 and WINDOW0 bits.
Remark If the overflow time is set to 29/fIL, the window close time and open time are as follo ws.
Setting of Window Open Period
50% 75% 100%
Window close time 0 to 20.08 ms 0 to 10.04 ms None
Window open time 20.08 to 29.68 ms 10.04 to 29.68 ms 0 to 29.68 ms
Example: When window open period is 50%
• Overflow time:
29/fIL (MAX.) = 29/17.25 kHz (MAX.) = 29.68 ms
• Window close time:
0 to 29/fIL (MIN.) × (1 − 0.5) = 0 to 29/12.75 kHz × 0.5 = 0 to 20.08 ms
• Window open time:
29/fIL (MIN.) × (1 − 0.5) to 29/fIL (MAX.) = 29/12.75 kHz × 0.5 to 29/17.25 kHz = 20.08 to 29.68 ms
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9.4.4 Setting watchdog timer interval interrupt
Depending on the setting of bit 7 (WDTINT) of an option byte (000C0H), an interval interrupt (INTWDTI) can be
generated when 75% + 1/2 fIL of the overflow time is reached.
Table 9-5. Setting of Watchdog Timer Interval Interrupt
WDTINT Use of Watchdog Timer Interval Interrupt
0 Interval interrupt is used.
1 Interval interrupt is generated when 75% + 1/2 fIL of overflow time is reached.
Caution When operating with the X1 oscillation clock after releasing the STOP mode, the CPU starts
operating after the oscillation stabilization time has elapsed.
Therefore, if the period between the STOP mode release and the watchdog timer overflow is short, an
overflow occurs during the oscillation stabilization time, causing a reset.
Consequently, set the overflow time in consideration of the oscillation stabilization time when
operating with the X1 oscillation clock and when the watchdog timer is to be cleared after the STOP
mode release by an interval interrupt.
Remark The watchdog timer continues counting even after INTWDTI is generated (until ACH is written to the
watchdog timer enable registe r (W DTE)). If ACH is not written to the WDTE register before the overflow time,
an internal reset signal is generated.
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CHAPTER 10 A/D CONVERTER
10.1 Function of A/D Converter
The A/D converter is a 10-bit resolutionNote converter that converts analog input signals into digital values, and is
configured to control analog inputs, including up to 11 channels of A/D converter analog inputs (ANI0 to ANI3 and ANI16
to ANI22).
The A/D converter has the following function.
• 10-bit resolution A/D conversionNote
10-bit resolution A/D conversion is carried out repeatedly for one analog input channel selected from ANI0 to ANI3
and ANI16 to ANI22 (ANI0 to ANI3, ANI16 to ANI19 for 30-pin products). Each time an A/D conversion operation
ends, an interrupt request (INTAD) is generated (when in the select mode).
Note 8-bit resolution can also be selected by using the ADTYP bit of A/D converter mode register 2 (ADM2).
Various A/D conversion modes can be specified by using the mode combinations below.
Trigger Mode Channel Selection Mode Conversion Operation Mode
• Software trigger
Conversion is started by specifying a
software trigger.
• Hardware trigger no-wait mode
Conversion is started by detecting a
hardware trigger.
• Hardware trigger wait mode
The power is turned on by detecting a
hardware trigger while the system is off and
in the conversion standby state, and
conversion is then started automatically
after the stabilization wait time passes.
• Select mode
A/D conversion is performed on
the analog input of one channel.
• Scan mode
A/D conversion is performed on
the analog input of four channels
in order.
• One-shot conversion mode
A/D conversion is performed on
the selected channel once.
• Sequential conversion mode
A/D conversion is sequentially
performed on the selected
channels until it is stopped by
software.
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Figure 10-1. Block Diagram of A/D Converter
Timer trigger signal (INTTM01)
3
INTAD
ADCS ADMD FR2 FR1 ADCEFR0
Sample & hold circuit
Temperature sensor
VSS
A/D voltage comparator
A/D converter mode
register 0 (ADM0)
Internal bus
Internal bus
6
Analog input channel
specification register (ADS)
ANI16
ANI17
ANI18
ANI19
ANI20Note
ANI21Note
ANI22Note
Controller
A/D conversion result
register (ADCR)
Conversion result
comparison upper limit
setting register (ADUL)
Conversion result
comparison lower limit
setting register (ADLL)
A/D conversion
result upper
limit/lower limit
comparator
Timer trigger signal (INTIT)
Comparison
voltage
generator
LV1 LV0
6
A/D port configuration
register (ADPC)
ADPC2 ADPC1 ADPC0
A/D test register
(ADTES)
ADTES1 ADTES0
2
ADS3ADS4 ADS2 ADS1 ADS0
ADISS
ADREFPMADREFP0
ADRCK AWC ADTYP
ADREFP1
Internal reference voltage (1.45 V)
VDD
AV
REFP
/ANI0/P20
AV
REFM
/ANI1/P21
VSS
ADCS bit
ADREFP1 and ADREFP0 bits
ADTMD1 ADTMD0 ADTRS1 ADTRS0
A/D converter mode
register 1 (ADM1)
A/D converter mode
register 2 (ADM2)
Successive
approximation register
(SAR)
Internal reference voltage (1.45 V)
ADREFM bit
Selector
Selector
Selector
ADSCM
Digital port
control
ANI0/AV
REFP
/P20
ANI1/AV
REFM
/P21
ANI2/P22
ANI3/P23
3
3
5
Note Provided in only 20- or 24-pin products.
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10.2 Configuration of A/D Converter
The A/D converter includes the following hardware.
(1) ANI0 to ANI3 and ANI16 to ANI22 pins
These are the analog input pins of the 11 channels of the A/D converter. For 30-pin pro ducts, these are analog input
pins of the 8 channels of ANI0 to ANI3 or ANI16 to ANI19 pins. They input analog signals to be converted into d igital
signals. Pins other than the one selected as the analog input pin can be used as I/O port pins.
(2) Sample & hold circuit
The sample & hold circuit samples each of the analog input voltages sequentially sent from the input circuit, and
sends them to the A/D voltage comparator. This circuit also holds the sampled analog input voltage during A/D
conversion.
(3) A/D voltage comparator
This A/D voltage comparator compares the voltage generated from the voltage tap of the comparison voltage
generator with the analog input voltage. If the ana log input voltage is found to be greater than the referenc e voltage
(1/2 AVREF) as a result of the comparison, the most significant bit (MSB) of the successive approximation register
(SAR) is set. If the analog input voltage is less than the reference voltage (1/2 AVREF), the MSB bit of the SAR is
reset.
After that, bit 8 of the SAR register is automatically set, and the next comparison is made. The voltage tap of the
comparison voltage ge nerator is selected by the value of bit 9, to which the result has been already set.
Bit 9 = 0: (1/4 AVREF)
Bit 9 = 1: (3/4 AVREF)
The voltage tap of the comparison voltage g enerator and the analog inpu t voltage are compared and bit 8 of the SAR
register is manipulated accor ding to the result of the comparison.
Analog input voltage ≥ Voltage tap of compa r ison voltage generator: Bit 8 = 1
Analog input voltage ≤ Voltage tap of compa r ison voltage generator: Bit 8 = 0
Comparison is continued like this to bit 0 of the SAR register.
When performing A/D conversion at a resolu tion of 8 bits, the comparison continues until bit 2 of the SAR register.
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
(4) Comparison voltage generator
The comparison voltage generator generates the comparison voltage inp ut from an ana log input pin.
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(5) Successive approximation register (SAR)
The SAR register is a register that sets voltage tap data whose values from the comparison voltage ge nerator match
the voltage values of the analog input pins, 1 bit at a time starting from the most significant bit (MSB).
If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of
the SAR register (conversion results) are held in the A/D conversion result register (ADCR). When all the specified
A/D conversion operations have ended, an A / D conversion end interrupt request signal (INTAD) is generated.
(6) 10-bit A/D conversion result register (ADCR)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCR register holds the A/D conversion result in its higher 10 bits (the lo wer 6 bits
are fixed to 0).
(7) 8-bit A/D conversion result register (ADCRH)
The A/D conversion result is loaded from the successive approximation register to this register each time A/D
conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result.
(8) Controller
This circuit controls the conversion time of an input analog signal that is to be converted into a digital signal, as well
as starting and stopping of the conversion operation. When A/D conversion has been completed, this controller
generates INTAD.
(9) AVREFP pin
This pin inputs an external reference voltage (AVREFP).
If using AVREFP as the + side reference voltage of the A/D converter, set the ADREFP1 and ADREFP0 bits of A/D
converter mode register 2 (ADM2) to 1.
The analog signals input to ANI3 to ANI10 and ANI16 to ANI22 are conv erted to digital signals based on the voltage
applied bet ween AVREFP and the − side reference voltage (AVREFM/VSS).
In addition to AVREFP, it is possible to select VDD or the internal reference voltage (1.45 V) as the + side reference
voltage of the A/D converter.
(10) AVREFM pin
This pin inputs an external reference voltage (AVREFM). If using AVREFM as the − side reference voltage of the A/D
converter, set the ADREFM bit of the ADM2 register to 1.
In addition to AVREFM, it is possible to select VSS as the − side reference voltage of the A/D converter.
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10.3 Registers Used in A/D Converter
The A/D converter uses the following registers.
• Peripheral ena ble register 0 (PER0)
• A/D converter mode register 0 (ADM0)
• A/D converter mode register 1 (ADM1)
• A/D converter mode register 2 (ADM2)
• 10-bit A/D conversion res ult register (ADC R)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• Conversion result comparison upper limit setting register (ADUL)
• Conversion result comparison lower limit setting register (ADLL)
• A/D test register (ADTES)
• A/D port configuration register (ADPC)
• Port mode control registers 0, 1, 4, 12, 14 (PMC0, PMC1, PMC4, PMC12, PMC14)
• Port mode registers 0, 1, 2, 4, 12, 14 (PM0, PM1, PM2, PM4, PM12, PM14)
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10.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disa ble supplying the clock to the perip heral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-2. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
ADCEN Control of A/D converter input clock supply
0 Stops input clock supply.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
1 Enables input clock supply.
• SFR used by the A/D converter can be read/written.
Cautions 1. When setting the A/D converter, be sure to set the following registers first while the ADCEN
bit is set to 1. If ADCEN = 0, writing to a control register of the A/D converter is ignored, and,
even if the register is read, only the default value is read (except for port mode registers 0, 1, 2,
4, 12, and 14 (PM0, PM1, PM2, PM4, PM12, and PM14), port mode control registers 0, 1, 4, 12,
and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14), and A/D port configuration register (ADPC)).
• A/D converter mode register 0 (ADM0)
• A/D converter mode register 1 (ADM1)
• A/D converter mode register 2 (ADM2)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
• Analog input channel specification register (ADS)
• Conversion result comparison upper limit setting register (ADUL)
• Conversion result comparison lower limit setting register (ADLL)
• A/D test register (ADTES).
2. Be sure to clear the undefined bits to 0.
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 304
Sep. 28, 2012
10.3.2 A/D converter mode regi ster 0 (ADM0)
This register sets the conversion time for analog inp ut to be A/D converted, and starts/stops conversion.
The ADM0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-3. Format of A/D Converter Mode Register 0 (ADM0)
ADCELV0
Note 1
LV1
Note 1
FR0
Note 1
FR1
Note 1
FR2
Note 1
ADMDADCS
A/D conversion operation control
Stops conversion operation
[When read]
Conversion stopped/standby status
ADCS
0
<0>123456<7>
ADM0
A
ddress: FFF30H After reset: 00H R/W
S
ymbol
Specification of the A/D conversion channel selection mode
Select mode
Scan mode
ADMD
0
1
A/D voltage comparator operation control
Note 2
Stops A/D voltage comparator operation
Enables A/D voltage comparator operation
ADCE
0
1
Enables conversion operation
[When read]
While in the software trigger mode: Conversion operation status
While in the hardware trigger wait mode: Stabilization wait status + conversion
operation status
1
Notes 1. For details of the FR2 to F R0, LV1, LV0 bits, and A/D conversion, see Table 10-3 A/D Conversion Time
Selection.
2. While in the software trigger mode or hardware trigger no-wait mode, the operation of the A/D voltage
comparator is controlled by the ADCS and ADCE bits, and it takes 1
μ
s from the start of operation for the
operation to stabilize. T herefore, when the ADCS bit is set to 1 after 1
μ
s or more has elapsed from the
time ADCE bit is set to 1, the conversion result at that time has priority over the first conversion result.
Otherwise, ignore data of the first conversion.
Cautions 1. Change the ADMD, FR2 to FR0, LV1 and LV0 bits while conversion is stopped (ADCS = 0, ADCE =
0).
2. The setting combination of the ADCS bit to 1 and the ADCE bit to 0 is prohibited.
3. Do not change the ADCS and ADCE bits from 0 to 1 at the same time by using an 8-bit
manipulation instruction. Be sure to set these bits in the order described in 10.7 A/D Converter
Setup Flowchart.
<R>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 305
Sep. 28, 2012
Table 10-1. Settings of ADCS and ADCE Bits
ADCS ADCE A/D Conversion Operation
0 0 Conversion stopped state
0 1 Conversion standby state
1 0 Setting prohibited
1 1 Conversion-in-progress state
Note In hardware trigger wait mode, there is no DC power consumption path even during conversion
standby mode.
Table 10-2. Setting and Clearing Conditions for ADCS Bit
A/D Conversion Mode Set Conditions Clear Conditions
Sequential conversion
mode When 0 is written to ADCS
Select mode
One-shot conversion
mode
• When 0 is written to ADCS
• The bit is automatically cleared to 0 when
A/D conversion ends.
Sequential conversion
mode When 0 is written to ADCS
Software
trigger
Scan mode
One-shot conversion
mode
• When 0 is written to ADCS
• The bit is automatically cleared to 0 when
conversion ends on the specified four
channels.
Sequential conversion
mode When 0 is written to ADCS
Select mode
One-shot conversion
mode When 0 is written to ADCS
Sequential conversion
mode When 0 is written to ADCS
Hardware
trigger no-wait
mode
Scan mode
One-shot conversion
mode
When 1 is
written to ADCS
When 0 is written to ADCS
Sequential conversion
mode When 0 is written to ADCS
Select mode
One-shot conversion
mode
• When 0 is written to ADCS
• The bit is automatically cleared to 0 when
A/D conversion ends.
Sequential conversion
mode When 0 is written to ADCS
Hardware
trigger wait
mode
Scan mode
One-shot conversion
mode
When a
hardware trigger
is input
• When 0 is written to ADCS
• The bit is automatically cleared to 0 when
conversion ends on the specified four
channels.
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 306
Sep. 28, 2012
Figure 10-4. Timing Chart When A/D Voltage Comparator Is Used
ADCE
ADCS
ADCS
ADCS
Conversion start time Note 2
Conversion start time Note 2
Conversion start time Note 2
A/D voltage comparator
Software
trigger mode
Conversion
stopped
Conversion
standby
1 is written
to ADCS. 0 is written
to ADCS.
Conversion
standby
A/D voltage comparator: enables operation
Note 1
Note 1
Hardware trigger
no-wait mode
Conversion
operation
Conversion
stopped
Conversion
standby Trigger
standby
1 is written
to ADCS.
Hardware
trigger detection 0 is written
to ADCS.
Conversion
standby
Conversion
operation
Hardware trigger
wait mode
Conversion
stopped
Conversion
standby
A/D power supply stabilization wait
Note 2
Hardware trigger
detection 0 is written
to ADCS.
Conversion
standby
Conversion
operation
Notes 1. While in th e software trigger mode or hardware trigger no- wait mode, the time from the rising of the ADCE
bit to the falling of the ADCS bit must be 1
μ
s or longer to stabilize the internal circuit.
2. In starting conversion, the longer will take up to following time
ADM0 Conversion Start Time (Number of fCLK Clock)
FR2 FR1 FR0
Conversion
Clock (fAD) Software Trigger Mode/
Hardware Trigger No-wait Mode Hardware Trigger Wait Mode
0 0 0 fCLK/64 63
0 0 1 fCLK/32 31
0 1 0 fCLK/16 15
0 1 1 fCLK/8 7
1 0 0 fCLK/6 5
1 0 1 fCLK/5 4
1 1 0 fCLK/4 3
1 1 1 fCLK/2 1
1
Remark fCLK: CPU / Peripheral hardware clock frequency
However, for the second and subsequent conversion in sequential conversion mode or scan mode, the
conversion start time and stabilizati on wait time for A/D power supply do not occur after a hard ware trigger
is detected.
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 307
Sep. 28, 2012
Cautions 1. If using the hardware trigger wait mode, setting the ADCS bit to 1 is prohibited (but the bit is
automatically switched to 1 when the hardware trigger signal is detected). However, it is possible
to clear the ADCS bit to 0 to specify the A/D con version standby status.
2. While in the one-shot conversion mode of the hardware trigger no-wait mode, the ADCS flag is
not automatically cleared to 0 when A/D conversion ends. Instead, 1 is retained.
3. Only rewrite the value of the ADCE bit when ADCS = 0 (while in the conversion
stopped/conversion standby status).
4. To complete A/D con version, specify at least the following time as the hardw are trigger interval:
Hardware trigger no wait mode: 2 fCLK clock + A/D conversion time
Hardware trigger w ait mode: 2 fCLK clock + stabilization wait time + A/D conversion time
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 308
Sep. 28, 2012
Table 10-3. A/D Conversion Time Selection (1/4)
(1) Normal Mode 2.7 V ≤ VDD ≤ 5.5 V
When there is no stabilization w ait time (software trigger mode/hardware trigger no-w ait mode)
A/D Converter Mode
Register 0 (ADM0) Conversion Time Selection
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock (fAD) Number of
Conversion
Clock
Conversion
Time
fCLK =
1 MHz fCLK =
2 MHz fCLK =
4 MHz fCLK =
8 MHz fCLK =
16 MHz fCLK =
24 MHz
0 0 1 fCLK/32 608/fCLK
Setting
prohibited
76
μ
s 38
μ
s 25.33
μ
s
0 1 0 fCLK/16 304/fCLK
Setting
prohibited
76
μ
s
38
μ
s 19
μ
s 12.67
μ
s
0 1 1 fCLK/8 152/fCLK 76
μ
s
38
μ
s 19
μ
s 9.5
μ
s 6.33
μ
s
1 0 0 fCLK/6 114/fCLK
Setting
prohibited
57
μ
s
28.5
μ
s 14.25
μ
s 7.125
μ
s 4.75
μ
s
1 0 1 fCLK/5 95/fCLK 95
μ
s
47.5
μ
s 23.75
μ
s 11.875
μ
s 5.938
μ
s 3.96
μ
s
1 1 0 fCLK/4 76/fCLK 76
μ
s 38
μ
s 19
μ
s 9.5
μ
s 4.75
μ
s 3.17
μ
s
Note 1
1 1 1
0 0
Normal
1
fCLK/2
19 fAD
(Number of
sampling
clock : 7
fAD)
38/fCLK 38
μ
s 19
μ
s 9.5
μ
s 4.75
μ
s 2.375
μ
s
Notes 1 , 2
Setting
prohibited
0 0 1 fCLK/32 544/fCLK
Setting
prohibited
68
μ
s 34
μ
s 22.67
μ
s
0 1 0 fCLK/16 272/fCLK
Setting
prohibited
68
μ
s 34
μ
s 17
μ
s 11.33
μ
s
0 1 1 fCLK/8 136/fCLK 68
μ
s 34
μ
s 17
μ
s 8.5
μ
s 5.67
μ
s
1 0 0 fCLK/6 102/fCLK
Setting
prohibited
51
μ
s 25.5
μ
s 12.75
μ
s 6.375
μ
s 4.25
μ
s
1 0 1 fCLK/5 85/fCLK 85
μ
s 42.5
μ
s 21.25
μ
s 10.625
μ
s 5.3125
μ
s 3.54
μ
s
1 1 0 fCLK/4 68/fCLK 68
μ
s 34
μ
s 17
μ
s 8.5
μ
s 4.25
μ
s 2.83
μ
s
Notes 1, 2
1 1 1
0 1
Normal
2
fCLK/2
17fAD
(Number of
sampling
clock : 5
fAD)
34/fCLK 34
μ
s 17
μ
s 8.5
μ
s 4.25
μ
s 2.125
μ
s
Notes 1, 2
Setting
prohibited
Other than the above
−
−
−
Setting prohibited
Notes 1. Setting prohibited in the VDD < 3.6 V
2. This value is prohibited when using the temperature sensor
3. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution
is selected, the values are shorter by two cycles of the conversion clock (fAD)
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D
conversion once (ADCS = 0) beforehand.
2. The above conversion time does not include conversion state time. Conversion state time ad d in
the first conversion. Select con version time, taking clock frequency errors into consideration.
Remark f
CLK: CPU/peripheral hardware clock frequency
<R>
<R>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 309
Sep. 28, 2012
Table 10-3. A/D Conversion Time Selection (2/4)
(2) Low voltage ModeNote 1
When there is no stabilization w ait time (software trigger mode/hardware trigger no-w ait mode)
Conversion Time Selection
A/D Converter Mode
Register 0 (ADM0) 1.8 V ≤ VDD ≤ 5.5 V Note 2 Note 3
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock (fAD) Number of
Conversion
Clock
Conversion
Time
fCLK =
1 MHz fCLK =
2 MHz fCLK =
4 MHz fCLK =
8 MHz fCLK =
16 MHz fCLK =
24 MHz
0 0 1 fCLK/32 608/fCLK
Setting
prohibited
76
μ
s 38
μ
s 25.33
μ
s
0 1 0 fCLK/16 304/fCLK
Setting
prohibited
76
μ
s
38
μ
s 19
μ
s 12.67
μ
s
0 1 1 fCLK/8 152/fCLK 76
μ
s
38
μ
s 19
μ
s 9.5
μ
s
Note 4 6.33
μ
s
1 0 0 fCLK/6 114/fCLK
Setting
prohibited
57
μ
s
28.5
μ
s14.25
μ
s
Note 4 7.125
μ
s
Note 4 4.75
μ
s
1 0 1 fCLK/5 95/fCLK 95
μ
s
47.5
μ
s 23.75
μ
s11.875
μ
s
Note 4 5.938
μ
s
Note 4 3.96
μ
s
1 1 0 fCLK/4 76/fCLK 76
μ
s 38
μ
s 19
μ
s 9.5
μ
s
Note 4 4.75
μ
s
Note 4 3.17
μ
s
Note 5
1 1 1
１ 0 Low
voltage
1
fCLK/2
19 fAD
(Number of
sampling
clock : 7
fAD)
38/fCLK 38
μ
s 19
μ
s 9.5
μ
s
Note 4 4.75
μ
s
Note 4 2.375
μ
s
Note 5
Setting
prohibited
0 0 1 fCLK/32 544/fCLK
Setting
prohibited
68
μ
s 34
μ
s 22.667
μ
s
0 1 0 fCLK/16 272/fCLK
Setting
prohibited
68
μ
s 34
μ
s 17
μ
s 11.333
μ
s
0 1 1 fCLK/8 136/fCLK 68
μ
s 34
μ
s 17
μ
s 8.5
μ
s
Note 4 5.667
μ
s
1 0 0 fCLK/6 102/fCLK
Setting
prohibited
51
μ
s 25.5
μ
s12.75
μ
s
Note 4 6.375
μ
s
Note 4 4.25
μ
s
1 0 1 fCLK/5 85/fCLK 85
μ
s 42.5
μ
s 21.25
μ
s10.625
μ
s
Note 4 5.313
μ
s
Note 4 3.542
μ
s
1 1 0 fCLK/4 68/fCLK 68
μ
s 34
μ
s 17
μ
s 8.5
μ
s
Note 4 4.25
μ
s
Note 4 2.833
μ
s
Note 5
1 1 1
1 1 Low
voltage
2
fCLK/2
17 fAD
(Number of
sampling
clock : 5
fAD)
34/fCLK 34
μ
s 17
μ
s 8.5
μ
s
Note 4 4.25
μ
s
Note 4 2.125
μ
s
Note 5
Setting
prohibited
Other than the above
−
−
−
Setting prohibited
Notes 1. This mode is prohibited when using the temperature se nsor
2. 2.4 V ≤ VDD ≤ 5.5 V
3. 2.7 V ≤ VDD ≤ 5.5 V
4. Setting prohib ited in the V DD < 2.7 V
5. Setting prohib ited in the VDD < 3.6 V
6. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by t wo cycles of the conver sion clock (fAD).
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D
conversion once (ADCS = 0) beforehand.
2. The above con version time does n ot includ e con version state time. Con version state time add in the
first conversion. Select co nver sio n time, taking clock frequency errors into consideration.
Remark fCLK: CPU/peripheral hardware clock frequency
<R>
<R>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 310
Sep. 28, 2012
Table 10-3. A/D Conversion Time Selection (3/4)
(3) Normal Mode 2.7 V ≤ VDD ≤ 5.5 V
When there is stabilization wait time (hardware trigger wait mode)
A/D Converter Mode
Register 0 (ADM0) Stabilization Wait Time + Conversion Time Selection
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock
(fAD)
Number of
Stabilization
Wait Clock
Number of
Conversion
Clock
Stabilization
Wait Time +
Conversion
Time
fCLK =
1 MHz fCLK =
2 MHz fCLK =
4 MHz fCLK =
8 MHz fCLK =
16 MHz fCLK =
24 MHz
0 0 1 fCLK/32 864/fCLK
Setting
prohibited
108
μ
s 54
μ
s 36
μ
s
0 1 0 fCLK/16 432/fCLK
Setting
prohibited
108
μ
s
54
μ
s 27
μ
s 18
μ
s
0 1 1 fCLK/8 216/fCLK 108
μ
s
54
μ
s 27
μ
s 13.5
μ
s 9
μ
s
1 0 0 fCLK/6 162/fCLK
Setting
prohibited
81
μ
s
40.5
μ
s 20.25
μ
s 10.125
μ
s 6.75
μ
s
1 0 1 fCLK/5 135/fCLK 135
μ
s
67.5
μ
s 33.75
μ
s 16.875
μ
s 8.438
μ
s 5.625
μ
s
1 1 0 fCLK/4 108/fCLK 108
μ
s 54
μ
s 27
μ
s 13.5
μ
s 6.75
μ
s 4.5
μ
s
Note 2
1 1 1
0 0
Normal
1
fCLK/2
19 fAD
(Number of
sampling
clock : 7
fAD)
54/fCLK 54
μ
s 27
μ
s 13.5
μ
s 6.75
μ
s 3.375
μ
s
Notes 2, 3
Setting
prohibited
0 0 1 fCLK/32 800/fCLK
Setting
prohibited
100
μ
s 50
μ
s 33.33
μ
s
0 1 0 fCLK/16 400/fCLK
Setting
prohibited
100
μ
s 50
μ
s 25
μ
s 16.67
μ
s
0 1 1 fCLK/8 200/fCLK 100
μ
s 50
μ
s 25
μ
s 12.5
μ
s 8.33
μ
s
1 0 0 fCLK/6 150/fCLK
Setting
prohibited
75
μ
s 37.5
μ
s 18.75
μ
s 9.375
μ
s 6.25
μ
s
1 0 1 fCLK/5 125/fCLK 125
μ
s 62.5
μ
s 31.25
μ
s 15.625
μ
s 7.8125
μ
s 5.21
μ
s
1 1 0 fCLK/4 100/fCLK 100
μ
s 50
μ
s 25
μ
s 12.5
μ
s 6.25
μ
s 4.17
μ
s
Notes 2, 3
1 1 1
0 1
Normal
2
fCLK/2
8 fAD
17 fAD
(Number of
sampling
clock : 5
fAD)
50/fCLK 50
μ
s 25
μ
s 12.5
μ
s 6.25
μ
s 3.125
μ
s
Notes 2, 3
Setting
prohibited
Other than the above
−
−
−
−
Setting prohibited
Notes 1. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabiliz ation wait time for A/D power
supply do not occur after a hardware trigger is detected (see table 10-3 (1/4)).
2. Setting prohibited in the VDD < 3.6 V
3. This value is prohibited when using the temperature sensor
4 These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by t wo cycles of the conver sion clock (fAD).
Cautions 1. When rewriting the FR2 to FR0, LV1, and LV0 bits to other than the current data, stop A/D
conversion once (ADCS = 0) beforehand.
2. The above conversion time does not include conversion state time. Conversion state time add in
the first conversion. Select con version time, taking clock frequency errors into consideration.
3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for
stabilization after the hardware trigger is detected.
Remark f
CLK: CPU/peripheral hardware clock frequency
<R>
<R>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 311
Sep. 28, 2012
Table 10-3. A/D Conversion Time Selection (4/4)
(4) Low voltage ModeNote 1
When there is stabilization wait time Note 2 (hardware trigger wait mode)
Stabilization Wait Time + Conversion Time Selection
A/D Converter Mode
Register 0 (ADM0) 1.8 V ≤ VDD ≤ 5.5 V Note3 Note4
FR2 FR1 FR0 LV1 LV0
Mode
Conversion
Clock
(fAD)
Number of
stabilization
wait clock
Number of
Conversion
Clock
Stabilization
Wait Time +
Conversion
Time
fCLK =
1 MHz fCLK =
2 MHz fCLK =
4 MHz fCLK =
8 MHz fCLK =
16 MHz fCLK =
24 MHz
0 0 1 fCLK/32 672/fCLK
Setting
prohibited
84
μ
s 42
μ
s 28
μ
s
0 1 0 fCLK/16 336/fCLK
Setting
prohibited
84
μ
s
42
μ
s 21
μ
s 14
μ
s
0 1 1 fCLK/8 168/fCLK 84
μ
s
42
μ
s 21
μ
s 10.5
μ
s
Note 5 7
μ
s
1 0 0 fCLK/6 126/fCLK
Setting
prohibited
63
μ
s
31.25
μ
s15.75
μ
s
Note 5 7.875
μ
s
Note 5 5.25
μ
s
1 0 1 fCLK/5 105/fCLK 105
μ
s
52.5
μ
s26.25
μ
s13.125
μ
s
Note 5 6.563
μ
s
Note 5 4.38
μ
s
1 1 0 fCLK/4 84/fCLK 84
μ
s
42
μ
s 21
μ
s 10.5
μ
s
Note 5 5.25
μ
s
Note 5 3.5
μ
s
Note 6
1 1 1
1 0 Low
voltage
1
fCLK/2
19 fAD
(Number of
sampling
clock :7
fAD)
42/fCLK 42
μ
s 21
μ
s 10.5
μ
s
Note 5 5.25
μ
s
Note 5 2.625
μ
s
Note 6
Setting
prohibited
0 0 1 fCLK/32 608/fCLK
Setting
prohibited
76
μ
s
38
μ
s 25.33
μ
s
0 1 0 fCLK/16 304/fCLK
Setting
prohibited
76
μ
s 38
μ
s 19
μ
s 12.67
μ
s
0 1 1 fCLK/8 152/fCLK 76
μ
s 38
μ
s 19
μ
s 9.5
μ
sNote
5 6.33
μ
s
1 0 0 fCLK/6 114/fCLK
Setting
prohibited
57
μ
s 28.5
μ
s 14.25
μ
s
Note 5 7.125
μ
s
Note 5 4.75
μ
s
1 0 1 fCLK/5 95/fCLK 95
μ
s 47.5
μ
s 23.75
μ
s11.875
μ
s
Note 5 5.938
μ
s
Note 5 3.96
μ
s
1 1 0 fCLK/4 76/fCLK 76
μ
s 38
μ
s 19
μ
s 9.5
μ
s
Note 5 4.75
μ
s
Note 5 3.17
μ
s
Note 6
1 1 1
1
1 Low
voltage
2
fCLK/2
2 fAD
17 fAD
(Number of
sampling
clock :5
fAD)
38/fCLK 38
μ
s 19
μ
s 9.5
μ
s
Note 5 4.75
μ
s
Note 5 2.375
μ
s
Note 6
Setting
prohibited
Other than the above
−
−
−
−
Setting prohibited
Notes 1. This mode is prohibited when using the temperature sensor
2. For the second and subsequent conversion in sequential conversion mode and for conversion of the channel
specified by scan 1, 2, and 3 in scan mode, the conversion start time and stabiliz ation wait time for A/D power
supply do not occur after a hardware trigger is detected (see table 10-3 (2/4)).
3. 2.4 V ≤ VDD ≤ 5.5 V
4. 2.7 V ≤ VDD ≤ 5.5 V
5. Setting prohib ited in the V DD < 2.7 V
6. Setting prohib ited in the VDD < 3.6 V
7. These are the numbers of clock cycles when conversion is with 10-bit resolution. When eight-bit resolution is
selected, the values are shorter by t wo cycles of the conversion clock (fAD ).
Cautions 1. Rewrite the FR2 to FR0, LV1 and LV0 bits to other than the current data while conversion is stopped
(ADCS = 0, ADCE = 0).
2. The above con version time does not inclu de conversion state time. Con version state time add in th e
sfirst conversion. Select con version time, taking clock frequency errors into consideration.
3. While in the hardware trigger wait mode, the conversion time includes the time spent waiting for
stabilization after the hardware trigger is detected.
Remark f
CLK: CPU/peripheral hardware clock frequency
<R>
<R>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 312
Sep. 28, 2012
Figure 10-5. A/D Converter Sampling and A/D Conversion Timing (Example for Software Trigger Mode)
ADCS
Conversion time Conversion time
Sampling
Sampling
timing
INTAD
ADCS ← 1 or ADS rewrite
Sampling
SAR
clear SAR
clear
Transfer
to ADCR,
INTAD
generation
Successive conversion
10.3.3 A/D converter mode regi ster 1 (ADM1)
This register is used to specify the A/D conver sion trigger, conversion mode, and hardware trigger signal.
The ADM1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-6. Format of A/D Converter Mode Register 1 (ADM1)
Address: FFF32H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADM1 ADTMD1 ADTMD0 ADCSM 0 0 0 ADTRS1 ADTRS0
ADTMD1 ADTMD0 Selection of the A/D conversion trigger mode
0 × Software trigger mode
1 0 Hardware trigger no- wait mode
1 1 Hardware trigger wait mode
ADSCM Specification of the A/D conversion mode
0 Sequential conversion mode
1 One-shot conversion mode
ADTRS1 ADTRS0 Selection of the hardware trigger signal
0 0 Count completion of timer channel 1 or capture completion interrupt signal (INTTM01)
1 1 12-bit interval timer interrupt signal (INTIT)
Other than above Settig prohibited
Cautions 1. Only rewrite the value of the ADM1 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mo d e register 0 (ADM0) being 0).
2. For the trigger interval in the hardware trigger wait mode, specify at least (2 fCLK clock +
stabilization wait time + A/D con version time) (Refer to Table 10-3).
3. In modes other than SNOOZE mode, input of the next INTRTC or INTIT w ill not be recognized as
a valid hardware trigger for up to four fCLK cycles after the first INTRTC or INTIT is input.
Remark ×: don’t care
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10.3.4 A/D converter mode regi ster 2 (ADM2)
This register is used to select the A/D converter reference voltage, check the upper limit and lower limit A/D
conversion result values, select the resolution, and specify whether to use the wakeup function (SNOOZE mode).
The ADM2 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) (1/2)
Address: F0010H After reset: 00H R/W
Symbol 7 6 5 4 <3> <2> 1 <0>
ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP
ADREFP1 ADREFP0 Selection of the + side reference voltage source of the A/D converter
0 0 Supplied from VDD
0 1 Supplied from P20/AVREFP/ANI0
1 0
Supplied from the internal reference voltage (1.45 V) (Can be used only in HS (high-
speed main) mode)
1 1 Setting prohibited
• When ADREFP1 or ADREFP0 bit is rewritten, this must be configured in accordance with the following procedures.
(1) Set ADCE = 0
(2) Change the values of ADREFP1 and ADREFP0
(3) Stabilization wait time (A)
(4) Set ADCE = 1
(5) Stabilization wait time (B)
When ADREFP1 and ADREFP0 are set to 1 and 0, the setting is changed to A = 5
μ
s, B = 1
μ
s.
When ADREFP1 and ADREFP0 are set to 0 and 0 or 0 and 1, A needs no wait and B = 1
μ
s.
After wait of (5), start A/D conversion
• When ADREFP1 and ADREFP0 are set to 1 and 0, respectively, A/D conversion cannot be performed on the
temperature sensor output and internal reference voltage output.
Be sure to perform A/D conversion while ADISS = 0.
ADREFM Selection of the − side reference voltage source of the A/D converter
0 Supplied from VSS
1 Supplied from P21/AVREFM/ANI1
ADRCK Checking the upper limit and lower limit conversion result values
0 The interrupt signal (INTAD) is output w hen the ADLL register ≤ the ADCR register ≤ the ADUL register (<1 >).
1 The interrupt signal (INTAD) is output when the ADCR register < the ADLL register (<2>) or the ADUL
register < the ADCR register (<3>).
Figure 10-8 shows the generation range of the interrupt signal (INTAD) for <1> to <3>.
Cautions 1. Only rewrite the value of the ADM2 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mo d e register 0 (ADM0) being 0).
2. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and
specify input mode by using the port mode register.
3. Do not set the ADREFP1 bit to 1 when shifting to STOP mode. Also, if the internal reference
voltage (ADREFP1, ADREFP0 = 1, 0) is selected, the operating current indicated in 28.4.2
Supply current characteristics (ITMPS) will be added to the current consumption when
shifting to HALT mode.
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Figure 10-7. Format of A/D Converter Mode Register 2 (ADM2) (2/2)
Address: F0010H After reset: 00H R/W
Symbol 7 6 5 4 <3> <2> 1 <0>
ADM2 ADREFP1 ADREFP0 ADREFM 0 ADRCK AWC 0 ADTYP
AWC Specification of the SNOOZE mode
0 Do not use the SNOOZE mode function.
1 Use the SNOOZE mode function.
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is performed
without operating the CPU (the SNOOZE mode).
• The SNOOZE mode function can be specified only when the high-speed on-chip oscillator clock is selected for the
CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
• Using the SNOOZE mode function in the software trigger mode or hardware trigger no-wait mode is prohibited.
• Using the SNOOZE mode function in the sequential conversion mode is prohibited.
• When using the SNOOZE mode function, specify a hardware trigger interval of at least (shift time to SNOOZE mode
Note + A/D power supply stabilization wait time + A/D conversion time+ 2 fCLK) (Refer to table 10-3).
• If using SNOOZE mode, be sure to set the AWC bit to 0 in normal operation mode and change it to 1 just before
shifting to STOP mode.
Also, be sure to change the AWC bit to 0 after returning from STOP mode to normal operation mode. If the AWC bit
is left set to 1, A/D conversion will not start normally in spite of the subsequent SNOOZE or normal operation mode.
ADTYP Selection of the A/D conversion resolution
0 10-bit resolution
1 8-bit resolution
Note Refer to “From STOP to SNOOZE” in 18.2.3 SNOOZE mode
Caution Only rewrite the value of the ADM2 register while conversion operation is stopped (which is
indicated by the ADCE bit of A/D converter mo d e register 0 (ADM0) being 0).
Figure 10-8. ADRCK Bit Interrupt Signal Generation Range
1111111111
0000000000
ADCR register value
(
A/D conversion result)
<1> Area 1
(ADLL £ ADCR £ ADUL)
<2> Area 2
(ADCR < ADLL)
<3> Area 3
(ADUL < ADCR)
ADUL register settin
g
INTAD is generated
when ADRCK = 0.
INTAD is generated
when ADRCK = 1.
INTAD is generated
when ADRCK = 1.
ADLL register settin
g
Remark If INTAD does not occur, the A/D conversion result is not stored in the ADCR or ADCRH register.
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10.3.5 10-bit A/D conversion result reg i ster (ADCR)
This register is a 16-bit register that stores the A/D conversion result in the select mode. The lower 6 bits are fixed to
0. Each time A/D conversion ends, the conversion result is load ed from the successiv e approximatio n register (SAR).
The higher 8 bits of the conversion resu lt are stored in FFF1FH and the lower 2 bits are stored in the higher 2 bits of
FFF1EH Note.
The ADCR register can be read by a 16-b it memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Note If the A/D conversion result is outside the range s pecified by using the A/ D conversion comparison func tion (the
value specified by the ADRCK bit of the ADUL/ADLL registers; see Figure 10-8), the result is not stored.
Figure 10-9. Format of 10-b it A/D Conversion Result Register (ADCR)
Symbol
Address: FFF1FH, FFF1EH After reset: 0000H R
FFF1FH FFF1EH
000000
ADCR
Cautions 1. When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCR register
may become undefined. Read the conversion result following conversion completion before
writing to the ADM0, ADS, and ADPC registers. Using timing other than th e above may cause an
incorrect conversion result to be read .
2. When 8-bit resolution A/D conversion is selected (when the ADTYP bit of A/D converter mode
register 2 (ADM2) is 1) and the ADCR register is read, 0 is read from the lower two bits (ADCR1
and ADCR0).
3. When the ADCR register is accessed in 16-bit units, the higher 10 bits of the conversion result
are read in order starting at bit 15.
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10.3.6 8-bit A/D conversion result register (ADCRH)
This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored
Note.
The ADCRH register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note If the A/D conversion result is outside the range s pecified by using the A/ D conversion comparison func tion (the
value specified by the ADRCK bit of the ADUL/ADLL registers; see Figure 10-8), the result is not stored.
Figure 10-10. Format of 8-bit A/D Conversion Result Register (ADCRH)
Symbol
ADCRH
Address: FFF1FH After reset: 00H R
76543210
Caution When writing to the A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), and A/D port configuration register (ADPC), the contents of the ADCRH register may
become undefined. Read the conversion result following conversion completion before writing to
the ADM0, ADS, and ADPC registers. Using timing other than the above may cause an incorrect
conversion result to be read.
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10.3.7 Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-11. Format of Analog Input Channel Specification Register (ADS)
Address: FFF31H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0
Select mode (ADMD = 0)
ADISS ADS4 ADS3 ADS2 ADS1 ADS0
Analog input
channel Input sourceNote1
0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin
0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin
0 0 0 0 1 0 ANI2 P22/ANI2 pin
0 0 0 0 1 1 ANI3 P23/ANI3 pin
0 1 0 0 0 0 ANI16 P10/ANI16 pin
P01/ANI16 pin
0 1 0 0 0 1 ANI17 P11/ANI17 pin
P00/ANI17 pin
0 1 0 0 1 0 ANI18 P12/ANI18 pin
P147/ANI18 pin
0 1 0 0 1 1 ANI19 P13/ANI19 pin
P120/ANI19 pin
0 1 0 1 0 0 ANI20 P14/ANI20 pin
−
0 1 0 1 0 1 ANI21 P42/ANI21 pin
−
0 1 0 1 1 0 ANI22 P41/ANI22 pin
−
1 0 0 0 0 0 − Temperature sensor output
Note2
1 0 0 0 0 1 − Internal reference voltage
output (1.45 V) Note2
Other than the above Setting prohibited
Notes 1. Upper: 20- or 24-pin products, lower: 30-pin products.
2. This setting can be used only in HS (high-speed main) mode.
Remark − : Ignore the conversion result because it is underfined.
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Scan mode (ADMD = 1)
Analog input channel ADS4 ADS3 ADS2 ADS1 ADS0
Scan 0 Scan 1 Scan 2 Scan 3
0 0 0 0 0 ANI0 ANI1 ANI2 ANI3
0 0 0 0 1 ANI1 ANI2 ANI3
−
0 0 0 1 0 ANI2 ANI3
− −
0 0 0 1 1 ANI3
− − −
Other than the above Setting prohibited
Cautions 1. Be sure to clear bits 5 and 6 to 0.
2. Set a channel to be set the analog input by ADPC and PMC registers in the input mode by
using port mode registers 0, 1, 2, 4, 12, or 14 (PM0, PM1, PM2, PM4 PM12, PM14).
3. Do not set the pin that is set by the A/D port configuration register (ADPC) as digital I/O
by the ADS register.
4. Do not set the pin that is set by port mode control registers 0, 1, 4, 12, 14 (PMC0, PMC1,
PMC4, PMC12, PMC14) as digital I/O by the ADS register.
5. Only rewrite the value of the ADISS bit while A/D conversion comparator operation is
stopped(ADCS = 0, ADCE = 0)
6. If using AVREFP as the + side reference voltage so urce of the A/D converter, do not select
ANI0 as an A/D conversion ch an nel.
7. If using AVREFM as the − side reference voltage sou rce of the A/D converter, do not select
ANI1 as an A/D conversion ch an nel.
8. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side
reference voltage source.
9. While in the hardware trigger wait mode, the conversion time includes the time spent
waiting for stabilization after the hardware trigger is detected.
10. Ignore the conversion result if the corresponding ANI pin does not exist in the product
used.
Remark − : Ignore the conversion result because it is undefined.
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10.3.8 Conversion result comparison u p per limit setting register (ADUL)
This register is used to specify the setting for checking the u pper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (sho wn in Figure 10-8).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Caution When 10-bit resolution A/D conversion is selected, the higher 8 bits of the 10-bit A/D conversion
result register (ADCR) are compared with the ADUL register.
Figure 10-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: F0011H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
ADUL ADUL7 ADUL6 ADUL5 ADUL4 ADUL3 ADUL2 ADUL1 ADUL0
10.3.9 Conversion result comparison lower limit setting register (ADLL)
This register is used to specify the setting for checkin g the lo wer limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 10-8).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: F0012H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADLL ADLL7 ADLL6 ADLL5 ADLL4 ADLL3 ADLL2 ADLL1 ADLL0
Caution When 10-bit resolution A/D conversion is selected, the higher 8 bits of the 10-bit A/D conversion
result register (ADCR) are compared with the ADLL register.
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10.3.10 A/D test register ( ADTES)
This register is used to select the + side reference voltage (AVREFP) or - side reference voltage (AVREFM) of the A/D
converter, or the analog input channel (ANIxx) as the A/D conversion target for the A/D test function. For detail,
refer to 21.3.7 A/D test function
The ADTES register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-14. Format of A/D Test Register (ADTES)
Address: F0013H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADTES 0 0 0 0 0 0 ADTES1 ADTES0
ADTES1 ADTES0 A/D conversion target
0 0
ANIxx / temperature sensor output / internal reference voltage output (1.45V) (This is
specified using the analog input channel specification register (ADS).)Note
1 0 AVREFM
1 1 AVREFP
Other than the above Setting prohibited
Note Temperature sensor output/internal reference voltage (1.45V) can be used only in HS (high-speed
main) mode.
Caution For details of the A/D test function, see 21.3.7 A/D test function.
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10.3.11 A/D port configuration register (ADPC)
This register switches the ANI0/P20 to ANI3/P23 pins to analog input of A/D converter or digital I/O of port.
The ADPC register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 10-15. Format of A/D Port Configuration Register (ADPC)
Address: F0076H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADPC 0 0 0 0 0 ADPC2 ADPC1 ADPC0
Analog input (A)/digital I/O (D) switching
ADPC2 ADPC1 ADPC0 ANI3/P23 ANI2/P22 ANI1/P21 ANI0/P20
0 0 0 A A A A
0 0 1 D D D D
0 1 0 D D D A
0 1 1 D D A A
1 0 0 D A A A
Other than above Setting prohibited
Cautions 1. Set the port to analog input by ADPC register to the input mode by using port mode registers 2
(PM2).
2. Do not set the pin set by the ADPC register as digital I/O by the analog input channel
specification register (ADS).
3. When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify
input mode by using the port mode register.
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10.3.12 Port mode control registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and PMC14)
These registers are used to set the digital I/O/analog input of ports 0, 1, 4, 12, and 14 in 1-bit units.
When using the P10/ANI16/PCLBUZ0/SCK00/SCL00, P11/ANI17/SI00/RxD0/SDA00/TOOLRxD, P12/ANI18/SO00/
TxD0/TOOLTxD, P13/ANI19/TI00/TO00/INTP2, P14/ANI20/TI01/TO01/INTP3, P42/ANI21/SCK01/SCL01/TI03/TO03,
or P41/ANI22/SO01/SDA01/TI02/TO02/INTP1 pin of 20- or 24-pin products as an analog input pin, set the
corresponding bit (PMC10, PMC11, PMC12, PMC13, PMC14, PMC41, PMC42) to 1.
When using the P01/ANI16/TO00/RxD1, P00/ANI17/TI00/TxD1, P147/ANI18, or P120/ANI19 pin of 30-pin products
as an analog input pin, set the correspondi ng bit (PMC00, PMC01, PMC12 0, PMC147) to 1.
The PMC0, PMC1, PMC4, PMC12, and PMC14 registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Figure 10-16. Formats of Port Mode Control Registers 0, 1, 4, 12, and 14 (PMC0, PMC1, PMC4, PMC12, and
PMC14)
20- and 24-pin products
Symbol 7 6 5 4 3 2 1 0
Address After reset R/W
PMC1 1 1 1 PMC14 PMC13 PMC12 PMC11 PMC10 F0061H FFH R/W
PMC4 1 1 1 1 1 PMC42 PMC41 1 F0064H FFH R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0
Address After reset R/W
PMC0 1 1 1 1 1 1 PMC01 PMC00 F0060H FFH R/W
PMC12 1 1 1 1 1 1 1 PMC120 F006CH FFH R/W
PMC14 PMC147 1 1 1 1 1 1 1 F006EH FFH R/W
PMCm Pmn pin digital I/O/analog input selection (m = 0, 1, 4, 12, and 14; n = 0 to 4, and 7)
0 Digital I/O (dual-use function other than analog input)
1 Analog input
Cautions 1. Set the port to analog input by PMC register to the input mode by using port mode registers x
(PMx).
2. Do not set the pin set by the PMC regi ster as digital I/O by the analog input ch annel specification
register (ADS).
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10.3.13 Port mode registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14)
When using the P10/ANI16/PCLBUZ0/SCK00/SCL00, P11/ANI17/SI00/RxD0/SDA00/TOOLRxD, P12/ANI18/SO00/
TxD0/TOOLTxD, P13/ANI19/TI00/TO00/INTP2, P14/ANI20/TI01/TO01/INTP3, P42/ANI21/SCK01/SCL01/TI03/TO03,
P41/ANI22/SO01/SDA01/TI02/TO02/INTP1P20/ANI0/AVREFP, P21/ANI1/AVREFM, P22/ANI2, or P23/ANI3 pin of 20- or
24-pin products for an analog input port, set the corresponding bit (PM10 to PM14, PM20 to PM23, PM41, PM42) to 1.
At this time, the output latches of P10 to P14, P20 to P23, P41, and P42 may be 0 or 1.
When using the P01/ANI16/TO00/RxD1, P00/ANI17/TI00/TxD1, P20/ANI0/AVREFM, P21/ANI1/AVREFP, P22/ANI2,
P23/ANI3, P147/ANI18, P120/ANI19 pin of 30-pin products for an analog input port, set the correspondi ng bit (PM00,
PM01, PM20 to PM23, PM120, and PM14 7) to 1. At this ti me, the output latches of P00, P01, P2 0 to P23, P120, a nd
P147 may be 0 or 1.
If a port mode register bit corresponding to the pin is set to 0, the pin func tions as an output pin and the refore cannot
be used as an analog input p in.
The PM0, PM1, PM2, PM14, PM12, and PM14 registers can be set by a 1-bit or 8-bit memory manipulation
instruction.
Reset signal generation sets these registers to FFH.
Caution If a pin is set as an analog input port, not the pin level but “0” is always read.
Figure 10-17. Formats of Port Mode Registers 0, 1, 2, 4, 12, and 14 (PM0, PM1, PM2, PM14, PM12, PM14)
20- and 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W
PM2 1 1 1 1 PM23 PM22 PM21 PM20 FFF22H FFH R/W
PM12 1 1 1 1 1 1 1 PM120 FFF2CH FFH R/W
PM14 PM147 1 1 1 1 1 1 1 FFF2EH FFH R/W
PMm Pmn pin I/O mode selection (m = 0 to 2, 12, and 14; n = 0 to 4)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
Caution When using AVREFP and AVREFM, specify ANI0 and ANI1 as the analog input channels and specify
input mode by using the PM20 and PM21 bits for port mode register.
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The function of the ANI0/P20 t o ANI3/P23 pins are set de pending on the settings of the A/ D port configu ration register
(ADPC), analog input channel specification r egister (ADS), and PM2 registers.
Table 10-4. Functions of ANI0/P20 to ANI3/P23 Pins
ADPC PM2 ADS Function
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
The function of the P10/ANI16 to P14/ANI20, P42/ANI21, and P41/ANI22 pins of 20- or 24-pin products are set
depending on the settings of port mode control registers 1, 4 (PMC1, PMC4), analog input channel specification
register (ADS), and port mode registers 1, 4 (PM1, PM4).
The function of the P01/ANI16, P00/ANI17, P147/ANI18, and P120/ANI19 pins of 30-pin products are set depen ding
on the settings of port mode control registers 0, 12, 14 (PMC0, PMC12, PMC14), analog input channel specification
register (ADS), and port mode registers 0, 12, 14 (PM0, PM12, PM14).
Table 10-5. Functions of Pins for Analog Input as Dual-use Excluding ANI0 to ANI3
PMCn PMn ADS FunctionNote
Input mode − Digital input Digital I/O selection
Output mode − Digital output
Selects ANI. Analog input (to be converted) Input mode
Does not select ANI. Analog input (not to be converted)
Selects ANI.
Analog input selection
Output mode
Does not select ANI.
Setting prohibited
Remark n = 0, 1, 4, 12, 14
Note 20- or 24-pin products: P10/ANI16-P14/ANI20, P42/ANI21, P41/ANI22
30-pin pro ducts: P01/ANI16, P00/ANI17, P147/ANI18, P120/ANI19
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10.4 A/D Converter Conversion Operations
The A/D converter conversion operations are described below.
<1> The voltage input to the selected analog input channel is sampled by the sample & hold circuit.
<2> When sampling has been done for a certain time, the sample & hold circuit is placed in the hold state and the
sampled voltage is held until the A/D conversion operation has en ded.
<3> Bit 9 of the successive approximation register (SAR) is set. The series resistor string voltage tap is set to (1/2)
AVREF by the tap selector.
<4> The voltage difference between the series resistor string voltage tap and sampled voltage is compared by the
voltage comparator. If the analog in put is greater than (1/2) AVREF, the MSB bit of the SAR reg ister remains set
to 1. If the analog input is smaller than (1/2) AVREF, the MSB bit is reset to 0.
<5> Next, bit 8 of t he SAR register is automaticall y set to 1, and the operation proceeds to the next comparis on. The
series resistor string voltage tap is selected according to the preset value of bit 9, as described below.
• Bit 9 = 1: (3/4) AVREF
• Bit 9 = 0: (1/4) AVREF
The voltage tap and sampled voltage are compared and bit 8 of the SAR register is manipulated as foll ows.
• Sampled voltage ≥ Voltage tap: Bit 8 = 1
• Sampled voltage < Voltage tap: Bit 8 = 0
<6> Comparison is continued in this way up to bit 0 of the SAR register.
<7> Upon completion of the comparison of 10 bits, an effective digital result value remains in the SAR register, and
the result value is transferred to the A/D conversion result re gister (ADCR, ADCRH) and then latched Note 1.
At the same time, the A/D conversion end interrupt request (INTAD) can also be generated Note 1.
<8> Repeat steps <1> to <7>, until the ADCS bit is cleare d to 0 Note 2.
To stop the A/D converter, clear the ADCS bit to 0.
Notes 1. If the A/D conversion result is outside the A/D conv ersion result range specified by the ADRCK bit and the
ADUL and ADLL registers (see Figure 10-8), the A/D conversion result interrupt request signal is not
generated and no A/D conver sion results are stored in the ADCR and ADC RH registers.
2. While in the sequential conversion mode, the ADCS flag is not automatic ally cleared to 0. This flag is not
automatically cleared to 0 while in the one-shot conversion mode of the hardware trigger no-wait mode,
either. Instead, 1 is retained.
Remarks 1. Two types of the A/D conversion result registers are availabl e.
• ADCR register (16 bits): Store 10-bit A/D conversion value
• ADCRH register (8 bits): Store 8-bit A/D conversion value
2. AVREF: The + side reference v oltage of the A/D co nverter. T his can be select ed from AV REFP, the internal
reference voltage (1.45 V), and VDD.
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Figure 10-18. Conversion Operation of A/D Converter (Software Trigger Mode)
Sampling time
Sampling A/D conversion
Undefined
A/D converter
operation
ADCS ← 1 or ADS rewrite
SAR
ADCR
INTAD
SAR clear
Conversion time
Conversion
result
Conversion
result
A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/ D converter mode register (ADM) is
reset (0) by software.
If a write operation is performed to the analog input channel specification register (ADS) during an A/D conversion
operation, the conversion operation is initialized, and if the ADCS bit is set (1), conversion starts again from the begi nning.
Reset signal generation clears the A/D conversion result register (ADCR, ADCRH) to 0000H or 00H.
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10.5 Input Voltage and Conversion Results
The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI3, ANI16 to ANI22) and
the theoretical A/D conversion re sult (stored in the 10-bit A/ D conversion resu lt register (ADCR)) is sh own by the following
expression.
SAR = INT ( × 1024 + 0.5)
ADCR = SAR × 64
or
( − 0.5) × ≤ VAIN < ( + 0.5) ×
where, INT( ): Function which returns integer part of value in parentheses
V
AIN: Analog input voltage
AVREF: AVREF pin voltage
ADCR: A/D conversion result register (ADCR) value
SAR: Successive approximation register
Figure 10-19 shows the relationshi p between the analog input voltage and the A/D conversion result.
Figure 10-19. Relationship Between Analog Input Voltage and A/D Conversion Result
1023
1022
1021
3
2
1
0
FFC0H
FF80H
FF40H
00C0H
0080H
0040H
0000H
A/D conversion result
SAR ADCR
1
2048 1
1024 3
2048 2
1024 5
2048
Input voltage/AVREF
3
1024 2043
2048 1022
1024 2045
2048 1023
1024 2047
2048
1
Remark AVREF: The + side reference voltage of the A/D converter. This can be selected from AVREFP, the internal
reference voltage (1.45 V), and VDD.
VAIN
AVREF
AVREF
1024 AVREF
1024
ADCR
64 ADCR
64
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10.6 A/D Converter Operation Modes
The operation of each A/D converter mod e is described below. In addition, the procedure for specif ying each mode is
described in 10.7 A/D Converter Setup Flowchart.
10.6.1 Software trigger mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specifi ed by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> Even if a hardware trigger is input dur ing conversion operation, A/D conversion does not start.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversi on does not start.
Figure 10-20. Example of Software Trigger Mode (Select Mode, Sequential Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Data 0
(ANI0) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1)
Data0
(ANI0)
Data 0
(ANI0) Data0
(ANI0) Data0
(ANI0)
Data0
(ANI0) Data0
(ANI0) Data 0
(ANI0) Data0
(ANI0)
The trigger
is not
acknowledged.
The trigger
is not
acknowledged.
Conversion
standby
Conversion
standby
Stop
status Stop
status
A/D conversion
ends and the next
conversion starts.
Conversion is
interrupted.
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
ADCS is set to 1 while in the
conversion standby status. ADCS is overwritten
with 1 during A/D
conversion operation.
ADCE is set to 1.
<3> <3> <3>
Conversion is
interrupted
and restarts.
<3>
<4> A hardware trigger
is generated
(and ignored).
<6>
<5>
<2> ADCS is cleared to
0 during A/D
conversion operation.
<7>
<1> ADCE is cleared to 0. <8>
<3>
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10.6.2 Software trigger mode (select mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
perform the A/D conversion of the analog input specifi ed by the analog input channel specification register (ADS).
<3> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the s ystem enters the A/D conversion
standby status.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 10-21. Example of Software Trigger Mode (Select Mode, One-Shot Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1>
ADCS is set to
1 while in the
conversion
standby status.
ADCS is
automatically
cleared to
0 after
conversion
ends.
<2> <4> <2> <2>
<4> <2><4>
A/D
conversion
ends.
<3>
ADCS is overwritten
with 1 during A/D
conversion operation.
<5>
Conversion is
interrupted
and restarts. Conversion is
interrupted.
<3>
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
<6>
<3>
ADCE is cleared to 0. <8>
ADCS is
cleared to
0 during A/D
conversion
operation.
<7>
The trigger
is not
acknowledged. The trigger
is not
acknowledged.
Conversion
standby
Conversion
standby Conversion
standby
Conversion
standby
Conversion
standby
Data 0
(ANI0) Data 1
(ANI1)
Stop
status Data 0
(ANI0) Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1)
Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1) Data 1
(ANI1) Stop
status
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10.6.3 Software trigger mode (scan mode, sequent ial conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification reg ister (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automaticall y starts (until all fo ur channels are finished).
<4> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<6> Even if a hardware trigger is input dur ing conversion operation, A/D conversion does not start.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversi on does not start.
Figure 10-22. Example of Software Trigger Mode (Scan Mode, Sequential Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1> ADCE is cleared to 0. <8>
The trigger
is not
acknowledged.
The trigger
is not
acknowledged.
ADCS is set to 1 while in the
conversion standby status.
<2>
Conversion
standby
Conversion
standby
Stop
status Stop
status
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 3
(ANI3)
Undened
value
Undened
value
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Conversion is
interrupted and restarts.
Conversion is
interrupted and restarts.
Conversion is
interrupted.
A/D conversion ends and the
next conversion starts.
<3>
ADCS is overwritten
with 1 during A/D
conversion operation.
<4>
<3> <3>
ADS is rewritten during
A/D conversion operation.
<5>
ADCS is cleared
to 0 during A/D
conversion operation.
<7>
A hardware trigger is
generated (and ignored).
<6>
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
Data 0 (ANI0)
ANI1 to ANI3ANI0 to ANI3
<R>
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10.6.4 Software trigger mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
perform A/D conversion on the four analog input channels specified by scan 0 to scan 3, which are specified by
the analog input channel specification reg ister (ADS). A/D conversion is performed on the analog input channels
in order, starting with that specified by scan 0.
<3> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<4> After A/D conversion of the four chan nels en ds, the ADCS bit is aut omatic ally cleare d to 0, and th e s ystem enters
the A/D conversion standby status.
<5> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status.
<8> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversion does not start. In addition, A/D
conversion does not start even if a hardware trigger is input while in the A/D conversion standby status.
Figure 10-23. Example of Software Trigger Mode (Scan Mode, One-Shot Conversion Mode) Operation Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1>
The trigger
is not
acknowledged.
ADCS is set to 1 while
in the conversion
standby status.
<2>
Conversion
standby
Conversion
standby
Conversion
standby
Conversion
standby
Stop
status Stop
status
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 3
(ANI3)
Undened
value
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 3
(ANI3)
Data 1
(ANI1)
Data 2
(ANI2)
Data 1
(ANI1)
Conversion is
interrupted and restarts.
Conversion is
interrupted and restarts.
<3>
ADCS is
automatically
cleared to
0 after
conversion
ends.
<4> ADCS is overwritten
with 1 during A/D
conversion operation.
<5>
<2> <2><4>
Data 1
(ANI1)
Conversion is
interrupted.
ADCS is cleared
to 0 during A/D
conversion operation.
<7>
ADCE is cleared to 0. <8>
The trigger
is not
acknowledged.
A/D conversion
ends.
<3>
The interrupt is generated four times. The interrupt is generated four times.
ADS is rewritten during
A/D conversion operation.
<6>
ANI0 to ANI3 ANI1 to ANI3
Data 0 (ANI0)
<R>
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10.6.5 Hardware trigger no-wait mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hard ware trigger standby status (and conversion d oes not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
<4> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
<9> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-24. Example of Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE is set to 1.
<1>
ADCS is set to 1.
<2>
A hardware trigger
is generated.
<3> A hardware trigger is
generated during A/D
conversion operation.
<5>
A/D conversion
ends and the next
conversion
starts.
<4>
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
<6>
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted and
restarts.
<4> <4> <4> <4>
ADCS is overwritten
with 1 during A/D
conversion operation. <7> ADCS is cleared
to 0 during A/D
conversion operation.
ADCE is cleared to 0.<9>
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
Stop
status
Data 0
(ANI0) Data 1
(ANI1)
The trigger is not
acknowledged.
Trigger
standby
status
The trigger is not
acknowledged.
Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1) Data 1
(ANI1)
Conversion
standby
Conversion
standby
Stop
status
Conversion
is interrupted.
<8>
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10.6.6 Hardware trigger no-wait mode (select mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hard ware trigger standby status (and conversion d oes not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the analog input specified by the
analog input channel specification register (ADS).
<4> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<5> After A/D conversion ends, the ADCS bit remains set to 1, and the system enters the A/D conversion standby
status.
<6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
<10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-25. Example of Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
ADCE is set to 1.
<1>
Stop
status Stop
status
Conversion
standby
Data 0
(ANI0)
Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1) Data 1
(ANI1)
Data 0
(ANI0) Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1)
Data 0
(ANI0)
Data 0
(ANI0)
ADCE is cleared to 0.<10>
The trigger is not
acknowledged.
Trigger
standby
status
ADCS is set to 1.
<2>
ADCS retains
the value 1.<5> <5> <5>
A hardware trigger
is generated.
<3> <3> <3> <3> <3>
Conversion
standby Conversion
standby Conversion
standby Conversion
standby
Conversion
standby
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
<4>
A hardware trigger is
generated during A/D
conversion operation.
<6>
<7>
<4>
<4>
Data 1
(ANI1)
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
<8> <5>
ADCS is overwritten with 1 during
A/D conversion
operation.
<4>
Conversion is
interrupted
and restarts.
Trigger
standby
status
Conversion is
interrupted.
<9>ADCS is cleared
to 0 during A/D
conversion
operation.
A/D conversion
ends.
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10.6.7 Hardware trigger no - wait mode (scan mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hard ware trigger standby status (and conversion d oes not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are s pecified by the analog input channel spec ification register (ADS). A/D
conversion is performed on the analog input chan nels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
<9> When ADCE is cleared to 0 while in the A/D conversion standb y status, the A/D converter enters the stop status.
When ADCE = 0, specifying 1 for ADCS is ignored and A/D conversi on does not start.
Figure 10-26. Example of Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1> ADCE is cleared to 0. <9>
The trigger is not
acknowledged.
Conversion
standby
Stop
status
Conversion
standby
Stop
status
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 4
(ANI4)
Data 2
(ANI2)
Data 2
(ANI2)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 3
(ANI3)
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted.
Conversion is
interrupted
and restarts.
A/D conversion
ends and the next
conversion starts.
<4> <4> <4><4>
ADS is rewritten during
A/D conversion operation.
<6>
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
Trigger
standby
status
Hardware
trigger
ADCS is set to 1.
<2>
A hardware trigger
is generated.
<3> A hardware trigger is
generated during A/D
conversion operation.
<5>
ADCS is overwritten
with 1 during A/D
conversion operation.
<7> ADCS is cleared to 0
during A/D conversion
operation.
Trigger
standby
status
<8>
The trigger
is not
acknowledged.
Data 0 (ANI0)
ANI0 to ANI3 ANI1 to ANI3
<R>
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Sep. 28, 2012
10.6.8 Hardware trigger no - wait mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> After the software counts up to the stabilization wait time (1
μ
s), the ADCS bit of the ADM0 register is set to 1 to
place the system in the hard ware trigger standby status (and conversion d oes not start at this stage). Note that,
while in this status, A/D conversion does not start even if ADCS is set to 1.
<3> If a hardware trigger is input while ADCS = 1, A/D conversion is performed on the four analog input channels
specified by scan 0 to scan 3, which are s pecified by the analog input channel spec ification register (ADS). A/D
conversion is performed on the analog input chan nels in order, starting with that specified by scan 0.
<4> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<5> After A/D conversion of the four channels ends, the ADCS bit remains set to 1, and the system enters the A/D
conversion standby status.
<6> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<7> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<8> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<9> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, and the
system enters the A/D conversion standby status. However, the A/D converter does not power down in this
status.
<10> When ADCE is cleared to 0 while in the A/D conversion standby status, the A/D converter enters the stop status.
When ADCS = 0, inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-27. Example of Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Con version Mode) Operation
Timing
Trigger
standby
status
Conversion
standby
status
Conversion
standby
Stop
status
Stop
status
ADCE is set to 1.
<1>
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
ADCS is set to 1.
<2>
A hardware trigger
is generated.
<3> <3> <3> <3>
The trigger is not
acknowledged.
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
Conversion
standby
Conversion
standby
Conversion
standby
Conversion
standby
ADCS retains
the value 1.
<5> <5> <5>
<4>
A/D
conversion
ends.
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted.
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 3
(ANI3)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 3
(ANI3)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 3
(ANI3)
Undened
value
Undened
value
Data 3
(ANI3)
<4> <4>
<8>
A hardware trigger is
generated during A/D
conversion operation.
<6>
ADS is rewritten
during A/D
conversion operation.
<7>
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
to 0 during A/D
conversion
operation.
ADCE is cleared to 0. <10>
Data 0 (ANI0) Data 1 (ANI1)
ANI0 to ANI3 ANI1 to ANI3
<9>
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 336
Sep. 28, 2012
10.6.9 Hardware trigger wait mode (select mode, sequential conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby stat us.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated. After A/D conversion ends, the next
A/D conversion immediately starts. (At this time, no hardware trigger is necessary.)
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-28. Example of Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode) Operation
Timing
ADCE is set to 1.
<1>
A hardware trigger
is generated.
<2> A hardware trigger is
generated during A/D
conversion operation.
<4>
A/D conversion ends
and the next
conversion
starts.
<3>
ADS is rewritten during
A/D conversion operation
(from ANI0 to ANI1).
<5>
Conversion is
interrupted
and restarts. Conversion is
interrupted
and restarts.
Conversion is
interrupted and
restarts.
<3> <3> <3> <3>
ADCS is overwritten
with 1 during A/D
conversion operation.
<6> ADCS is cleared
to 0 during A/D
conversion operation.
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
Stop status
Data 0
(ANI0) Data 1
(ANI1)
The trigger
is not
acknowledged.
Trigger
standby
status
Trigger
standby
status
The trigger
is not
acknowledged.
Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1) Data 1
(ANI1) Data 1
(ANI1) Stop status
Conversion is
interrupted.
<7>
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Sep. 28, 2012
10.6.10 Hardware trigger wait mode (select mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
hardware trigger standby stat us.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
analog input specified by the analog input channel specification register (ADS). The ADCS bit of the ADM0
register is automatically set to 1 according to the hardware trigger input.
<3> When A/D conversion ends, the conv ersion result is stored in the A/D conv ersion r esult register (ADCR, ADCRH),
and the A/D conversion end interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the analog input respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is initialized.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-29. Example of Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode) Operation
Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
ADCE is set to 1.
<1>
Stop status Stop status
Stop
status Stop
status Stop
status Stop
status
Data 0
(ANI0)
Data 0
(ANI0)
Data 0
(ANI0) Data 0
(ANI0) Data 1
(ANI1) Data 1
(ANI1)
Data 0
(ANI0) Data 1
(ANI1) Data 1
(ANI1) Data 1
(ANI1)
Data 1
(ANI1)
Data 0
(ANI0)
Data 0
(ANI0)
The trigger is not
acknowledged.
Trigger
standby
status
A hardware trigger
is generated.
<2> <2> <2>
<2> <2>
Conversion is
interrupted
and restarts.
<3> A/D conversion
ends.
A hardware trigger is
generated during A/D
conversion operation.
<5>
<6>
<3>
<8>
<3>
Data 1
(ANI1)
ADS is rewritten
during A/D conversion
operation (from ANI0
to ANI1).
Conversion is
interrupted.
ADCS is cleared
to 0 during A/D
conversion
operation.
Trigger
standby
status
ADCS is automatically
cleared to 0 after
conversion ends.
<4> <4> <4> <4>
ADCS is overwritten
with 1 during A/D
conversion operation.
<7>
<3>
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
RL78/G12 CHAPTER 10 A/D CONVERTER
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Sep. 28, 2012
10.6.11 Hardware trigger wait mode (scan mode, sequential conversio n mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
<3> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated. After A/D conversion of the four channels ends, the A/D
conversion of the channel following the specified channel automatically starts.
<4> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<5> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<6> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<7> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-30. Example of Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode) Operation
Timing
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
ADCE is set to 1.
<1>
The trigger is not
acknowledged.
Stop status Stop status
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 3
(ANI3)
Undened
value
Undened
value
Undened
value
Undened
value
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 3
(ANI3)
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 3
(ANI3)
Conversion is
interrupted and restarts.
Conversion is
interrupted and restarts.
Conversion is
interrupted.
Conversion is
interrupted and restarts.
A/D conversion
ends and the next
conversion starts.
<3> <3> <3>
<3>
ADS is rewritten during
A/D conversion operation.
<5>
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
Trigger
standby status
Hardware
trigger
A hardware trigger
is generated.
<2> A hardware trigger is
generated during A/D
conversion operation.
<4>
ADCS is overwritten
with 1 during A/D
conversion operation.
<6> ADCS is cleared
to 0 during A/D
conversion operation.
Trigger
standby
status
<7>
The trigger
is not
acknowledged.
Data 0 (ANI0)
ANI0 to ANI3 ANI1 to ANI3
<R>
RL78/G12 CHAPTER 10 A/D CONVERTER
R01UH0200EJ0110 Rev.1.10 339
Sep. 28, 2012
10.6.12 Hardware trigger wait mode (scan mode, one-shot conversion mode)
<1> In the stop status, the ADCE bit of A/D converter mode register 0 (ADM0) is set to 1, and the system enters the
A/D conversion standby status.
<2> If a hardware trigger is input while in the hardware trigger standby status, A/D conversion is performed on the
four analog input channels specified by scan 0 to scan 3, which are specified by the analog input channel
specification register (ADS). The ADCS bit of the ADM0 register is automatically set to 1 according to the
hardware trigger input. A/D conversion is performed on the analog input channels in order, starting with that
specified by scan 0.
<3> A/D conversion is sequentially performed on the four anal og input channels, the conversion results are stored in
the A/D conversion result register (ADCR, ADCRH) each time conversion ends, and the A/D conversion end
interrupt request signal (INTAD) is generated.
<4> After A/D conversion ends, the ADCS bit is automatically cleared to 0, and the A/D converter enters the stop
status.
<5> If a hardware trigger is input during conversion operation, the current A/D conversion is interrupted, and
conversion restarts at the first channel. The partially converted data is discarded.
<6> When the value of the ADS register is rewritten or overwritten during conversion operation, the current A/D
conversion is interrupted, and A/D conversion is performed on the first channel respecified by the ADS register.
The partially converted data is discarded.
<7> When ADCS is overwritten with 1 during conversion operation, the current A/D conversion is interrupted, and
conversion restarts. The partially conv erted data is discarded.
<8> When ADCS is cleared to 0 during conversion operation, the current A/D conversion is interrupted, the system
enters the hardware trigger standby status, and the A/D converter enters the stop status. When ADCE = 0,
inputting a hardware trigger is ignored and A/D conversion does not start.
Figure 10-31. Example of Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode) Operation
Timing
Trigger
standby
status
Conversion
standby
status
Stop status Stop status
Stop
status
Stop
status
Stop
status
ADCE is set to 1.
<1>
ADCE
ADCS
ADS
INTAD
ADCR,
ADCRH
A/D
conversion
status
Hardware
trigger
A hardware trigger
is generated.
<2> <2> <2> <2>
The trigger is not
acknowledged.
The trigger is not
acknowledged.
The interrupt is generated four times. The interrupt is generated four times. The interrupt is generated four times.
<4> <4>
<3> Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted
and restarts.
Conversion is
interrupted.
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 1
(ANI1)
Data 0
(ANI0)
Data 0
(ANI0)
Data 1
(ANI1)
Data 2
(ANI2)
Data 3
(ANI3)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 0
(ANI0)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 3
(ANI3)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 1
(ANI1)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 2
(ANI2)
Data 3
(ANI3)
Data 3
(ANI3)
Undined
value
Undined
value
Data 3
(ANI3)
<3> <3>
<7>
A hardware trigger is
generated during A/D
conversion operation.
<5>
ADS is rewritten
during A/D
conversion operation.
<6>
ADCS is overwritten
with 1 during A/D
conversion operation.
ADCS is cleared
to 0 during A/D
conversion
operation.
ADCS is automatically
cleared to 0 after
conversion ends.
<4>
Data 0 (ANI0) Data 1 (ANI1)
ANI0 to ANI3 ANI1 to ANI3
<8>
A/D
conversion
ends.
<R>
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Sep. 28, 2012
10.7 A/D Converter Setup Flowchart
The A/D converter setup flowchart in each op eration mode is described below.
RL78/G12 CHAPTER 10 A/D CONVERTER
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Sep. 28, 2012
10.7.1 Setting up software trigger mode
Figure 10-32. Setting up Software Trigger Mode
ADCS bit setting
Start of setup
PE R0 register setting
ADPC and PMC register settings
PM register setting
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
A
NI0 to ANI14 pins: Set using the ADPC register
A
NI16 to ANI26 pins: Set using the PMC registe r
The ports are set to the input mode.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result
comparison value generated by the interrupt signal from AREA1,
AREA3, and AREA2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
ADCE bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D
conversion standby status.
Sta bilizatio n wa it t ime co u nt B
Counting 1
μ
s for the stabilization wait time
Start of A/D conversion
The A/D conversion operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
Note
Storage of conversion results in
the AD CR and AD C RH registers
The conversion results are stored in the ADCR and ADCRH registers
Note
.
A
fter counting up to the stabilization wait time ends, the ADCS bit of the ADM0
register is set (1), and A/D conv er sion start s.
End
End of A/D conversion
Stabilization wait tim e count A
The stabilization wait time count A is required when the value of the ADREFP1 and
A
DREFP0 bits is changed.
If change the ADREFP1 and ADR E FP0 = 1, 0: 5
μ
s
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0
μ
s
Note Depending on the settings of the ADRCK bit and AD UL/ADLL register, the re is a possibilit y of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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10.7.2 Setting up hardware trigger no-wait mode
Figure 10-33. Setting up Hardw are Trigger No-Wait Mode
Start of setup
PER0 register setting
AD PC and PMC register settings
PM register setting
• ADM 0 regi st er s etting
• ADM 1 regi st er s etting
• ADM 2 regi st er s etting
• ADUL/ADLL regis ter s ett ing
• ADS reg ister set ting
(The orde r of the settings is
irrelevant.)
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to analog input.
A
NI0 to ANI14 pins: Set using the ADPC register
A
NI16 to ANI26 pins: Set using the PMC register
The ports are set to the input mode.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/sca n mode
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger no-wait
mode.
ADSCM bit: Se qu ent ia l con ve rsio n mode / on e- sho t con ve r si on mo de
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and
AREA2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison valu es.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby statu s.
Counting 1
μ
s for the stabilization wait time
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
A
fter counting up to the stabilization wait time B ends, the ADCS bit of the ADM0
register is set (1), and the system enters the hardware trigger standby status.
Hardware trigger standby status
The A/D conversion operations are performed.
The stabilization wait time count A is required when the value of the ADREFP1 and
A
DREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 1, 0: 5
μ
s
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0
μ
s t
ADCE bit setting
Stabilization wait time count B
Start of A/D conversion by
generating a hardware trigger
End of A/D conversion
Storage of conversion results in
the AD CR and AD C RH registers
ADCS bit setting
Stabilization wait time count A
End
Note Depending on the settings of the ADRCK bit and AD UL/ADLL register, the re is a possibilit y of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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10.7.3 Setting up hardware trigger wait mode
Figure 10-34. Setting up Hardware Trigger Wait Mode
Start of setup
PER 0 register setting
ADPC and PMC register settings
PM register setting
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
The ports are set to the input mode.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: Select mode/scan mode
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the hardware trigger wait mode.
ADSCM bit: Sequential conversion mode/one-shot conversion mode
ADTRS1 and ADTRS0 bits: These are used to select the hardware trigger signal.
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select the reference
voltage source.
ADRCK bit: This is used to select the range for the A/D conversion result comparison
value generated by the interrupt signal from AREA1, AREA3, and AREA2.
AWC bit: This is used to set up the SNOOZE mode function.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D conversion result
comparison values.
• ADS register
ADS4 to ADS0 bits: These are used to select the analog input channels.
ADCE bit setting The ADCE bit of the ADM0 register is set (1), and the system enters the A/D conversion
standby status.
Hardware trigger generation
The system automatically counts up to the st abilization wait time for A/D pow er supply.
Start of A/D conversion
A
fter counting up to the stabilization wait time ends, A/D conversion starts
End of A/D conversion
The A/D conversion operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
Note
Storage of conversion results in
the ADCR and ADCRH registers
The conversion results are stored in the ADCR and ADCRH registers.
The ports are set to analog input.
A
NI0 to ANI14 pins: Set using the ADPC register
A
NI16 to ANI26 pins: Set using the PMC register
Stabilization wait time count B
Stabilization w ait tim e count A
The stabilization wait time count A is required when the value of the ADREFP1 and
A
DREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 1, 0: 5
μ
s
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0
μ
s
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
End
Note Depending on the settings of the ADRCK bit and AD UL/ADLL register, the re is a possibilit y of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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10.7.4 Setup when temperat ure sensor output/internal reference voltage outpu t is selected
(example for software trigger mode and one-shot conversion mode)
Figure 10-35. Setup when Temperature Sensor Output/internal Reference Voltage Output is Selected
PER0 register setting
The ADCEN bit of the PER0 register is set (1), and supplying the clock
starts.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D
conversion time.
ADMD bit: This is used t o specify the select mode .
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software
trigger mode.
ADSCM bit: Sequential conversion mode/one-shot con ver sion mode
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bit s: These are used to select the
reference voltage sou rce.
ADRCK bit: This is used to select the r ange for the A/D conve rsi on
result comparison value generated by the interrupt si gnal
from AREA1, AREA3, and ARE A2.
ADTYP bit: 8-bit/10-bit resolution
• ADUL/ADLL register
These are used to specify the upper limit and lower limit A/D con version
result comp arison values.
• ADS register
ADISS and ADS4 to ADS0 bits: These are used to select temperature
sensor 0 output or int ernal reference
voltage output.
The ADCE bit of the ADM0 regi st er is set (1), and the syst em enters the
A
/D conversion st andby st at us.
Counting 1
μ
s for the stabilization wait time
The A/D conversio n end interrupt (INTAD) is gener ated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
A
fter counting up to the stabilization wait time B ends, the ADCS bit of the
A
DM0 register is set (1), and A/ D conversion starts
Start of setup
The A/D conversion end int errupt (INTAD) will be generated.
A
fter ADISS is set (1), the initial conversion result cannot be used.
The ADCS bit of the ADM0 regi st er is set (1), and A/D conversi on starts.
First A/D conversion time
The stabilization wait time count A is required when the value of the
A
DREFP1 and ADREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0
μ
s
If change the ADREFP1 and ADREFP0 = 1, 0: Setting prohibited
Second A/D conversion time
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
(The order of the settings is
irrelevant.)
ADCE bit setting
Stabilization wait time count B
Start of A/D conversion
End of A/D conversion
ADCS bit setting
Storage of conversion results in
the AD C R and A DC R H registers
End of A/D conversion
ADCS bit setting
Start of A/D conversion
Stabilization wait time count A
End
Note Depending on the settings of the ADRCK bit and AD UL/ADLL register, the re is a possibilit y of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
Caution HS (high-speed main) mode can be selected
<R>
<R>
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10.7.5 Setting up test mode
Figure 10-36. Setting up Test Trigger Mode
The ADCEN bit of the PER0 register is set (1), and supplying the clock starts.
• ADM0 register
FR2 to FR0, LV1, and LV0 bits: These are used to specify the A/D conversion time.
ADMD bit: This is used to specify the select mode.
• ADM1 register
ADTMD1 and ADTMD0 bits: These are used to specify the software trigger mode.
ADSCM bit: This is used to specify the one-shot conversion mode.
• ADM2 register
ADREFP1, ADREFP0, and ADREFM bits: These are used to select for the reference
voltage source.
ADRCK bit: This is used to set the range for the A/D conversion result comparison
value generated by the interrupt signal to AREA2.
ADTYP bit: This is used to specify 10-bit resolution.
• ADUL/ADLL register
These set ADUL to FFH and ADLL to 00H (initial values).
• ADS register
ADS4 to ADS0 bits: These are used to set to ANI0.
The A/D conversion operations are performed.
The A/D conversion end interrupt (INTAD) is generated.
Note
The conversion results are stored in the ADCR and ADCRH registers.
PER 0 register setting
• ADM0 register setting
• ADM1 register setting
• ADM2 register setting
• ADUL/ADLL register setting
• ADS register setting
• ADTES register setting
(The order of the settings is
irrelevant.)
Counting 1
μ
s for the stabilization wait time
Stabilization wait time count B
Start of A/D conversion
End of A/D conversion
Storage of conversion results in
the ADC R and ADC RH registers
The ADCE bit of the ADM0 register is set (1), and the system enters the A/D
conversion standby status.
ADCE bit setting
ADCS bit setting
A
fter counting up to the stabilization wait time B ends, the ADCS bit of the ADM0
register is set (1), and A/D conversion starts.
• ADTES register
ADTES1, ADTES0 bits: AV
REFM
/AV
REFP
Start of setup
Stabilization wait time count A The stabilization wait time count A is required when the value of the ADREFP1 and
A
DREFP0 bits is changed.
If change the ADREFP1 and ADREFP0 = 1, 0: 5
μ
s
If change the ADREFP1 and ADREFP0 = 0, 0 or 0, 1: 0
μ
s
End
Note Depending on the settings of the ADRCK bit and AD UL/ADLL register, the re is a possibilit y of no interrupt signal
being generated. In this case, the results are not stored in the ADCR, ADCRH registers.
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10.8 SNOOZE mode function
In the SNOOZE mode, A/D conversion is triggered by inputting a hardware trigger in the STOP mode. Normally, A/D
conversion is stopped while in the STOP mode, but, by using the SNOOZE mode, A/D conversion can be performed
without operating the CPU by inputting a h ardware trigger. This is effective for reducing the operation current.
If the A/D conversion result range is specified using the ADUL and ADLL registers, A/D conversion results can be
judged at a certain interval of time in SNOOZE mode. Using this function enables power supply voltage monitoring and
input key judgment based on A/D inputs.
In the SNOOZE mode, only the following two conversion modes can be used:
• Hardware trigger wait mode (select mode, one-shot conversion mode)
• Hardware trigger wait mode (scan mode, one-shot conversion mo de)
Caution SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected for
fCLK.
Figure 10-37. Block Diagram When Using SNOOZE Mode Function
(INTIT)
Hardware trigger
input
Clock request signal
(internal signal)
A/D converter Clock generator
A/D conversion end
interrupt request
signalNote 1 (INTAD)
12-bit interval timer
High-speed on-chip
oscillator clock
When using the SNOOZE mode function, the initial setting of each register is specified before switching to the STOP
mode (for details about these settings, see 10.7.3 Setting up hardware trigger w ait mode Note 2). After the initial settings
are specified, bit 2 (AWC) of A/D converter mode register 2 (ADM2) and bit 0 (ADCE) of A/D converter mode register 0
(ADM0) is set to 1.
If a hardware trigger is input after switching to the STOP mode, the high-speed on-chip oscillator clock is supplied to
the A/D converter. After supplying this clock, the system automatically counts up to the stabilization wait time, and then
A/D conversion starts.
The SNOOZE mode operation after A/D conversion ends differs depending on whether an interrupt request signal is
generated Note 1.
Notes 1. Depending on the setting of the A/D conversion result comparison function (ADRCK bit, ADUL/ADLL
register), there is a possibility of no interrupt request signal being generate d.
2. Be sure to set the ADM1 register to E2H or E3H.
Remark Specify the hardware trigger by using t he A/D Converter Mode Register 1 (ADM1).
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(1) If an interrupt request is generated after A/D conversion ends
If the A/D conversion result value is inside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ADRCK bit and ADUL/ADLL registe r, refer to Figure 10-8), the A/D conversion
end interrupt request signal (INTAD) is generated.
• While in the select mode
After A/D conversion ends and the A/D conversion end interrupt request signal (INTAD) is generated, the clock
request signal remains at the high level, and the A/D converter switches from the SNOOZE mode to the normal
operation mode.
At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of the A/D converter mode register 2 (ADM2).
If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZ E or normal operatio n
mode.
• While in the scan mode
If even one A/D conversion end interrupt request signal (INTAD) is generated during A/D conversion of the four
channels, the clock request signal remains at the high level, and the A/D converter switches from the SNOOZE
mode to the normal operation mode.
At this time, be sure to clear bit 2 (AWC = 0: SNOOZE mode release) of A/D converter mode register 2 (ADM2) to 0.
If the AWC bit is left set to 1, A/D conversion will not start normally in the subsequent SNOOZ E or normal operatio n
mode.
Figure 10-38. Operation Example When Interrupt Request Is Generated After A/D Conversion Ends (While in Scan
Mode)
ADCS
Interrupt request
signal (INTAD)
INTIT
Clock request signal
(internal signal)
Conversion
channels Channel 1Channel 2Channel 3Channel 4
An interrupt request is
generated when conversion on
one of the channels ends.
The clock request signal
remains at the high level.
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(2) If no interrupt request is generated after A/D conversion ends
If the A/D conversion result value is outside the range of values specified by the A/D conversion result comparison
function (which is set up by using the ARDCK bit and ADUL/ADLL registe r, refer to Figure 10-8), the A/D conversion
end interrupt request signal (INTAD) is not generated.
• While in the select mode
If the A/D conversion end interrupt request signal (INTAD) is not generated after A/D conversion ends, the clock
request signal (an internal signal) is automatically set to the low level, and supplying the high-speed on-chip
oscillator clock stops. If a hardware trigger is input later, A /D conversion work is again performed in the SNOOZE
mode.
• While in the scan mode
If the A/D conversion end interrupt request signal (INTAD) is not generated even once during A/D conv ersion of the
four channels, the clock request signal (an i nternal signal) is automatically set to the low level after A/ D conversion
of the four channels ends, and supplying the high-spee d on -chip oscillator clock stops. If a hard ware trigger is input
later, A/D conversion work is again performe d in the SNOOZ E mode.
Figure 10-39. Operation Example When No Interrupt Request Is Generated After A/D Conversion Ends (While in
Scan Mode)
ADCS
Interrupt request
signal (INTAD)
INTIT
Clock request signal
(internal signal)
Conversion
channels Channel 1Channel 2Channel 3Channel 4
No interrupt request is generated when
conversion ends for any channel.
The clock request signal
is set to the low level.
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10.9 How to Read A/D Converter Characteristics Table
Here, special terms unique to the A/D converter are explained.
(1) Resolution
This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage
per bit of digital output is calle d 1LSB (Least Significant Bit). T he percentage of 1LSB with respect to the full scale is
expressed by %FSR (Full Scale Ra nge).
1LSB is as follows when the resolution is 10 bits.
1LSB = 1/210 = 1/1024
= 0.098%FSR
Accuracy has no relation to resolution, but is determined by overall error.
(2) Overall error
This shows the maximum error value between the actual measured value and the theoretical value.
Zero-scale error, full-scale error, integr al linearity error, and differential linearity errors that are c ombinations of these
express the overall error.
Note that the quantization error is not includ ed in the overall error in the characteristics table.
(3) Quantization error
When analog values are conv erted to digital values, a ±1/2L SB error naturall y occurs. In an A/D converter, an analo g
input voltage in a range of ±1/2LSB is conver ted to the same digital code, so a quantization error cannot be avoided.
Note that the quantization error is not included in the overall error, zero-scale error, full-scale error, integral linearity
error, and differential linearity error in the characteristics table.
Figure 10-40. Overall Error Figure 10-41. Quantization Error
Ideal line
0......0
1......1
Digital output
Overall
error
Analog input AV
REF
0
0......0
1......1
Digital output
Quantization error
1/2LSB
1/2LSB
Analog input
0AV
REF
(4) Zero-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (1/2LSB) when the digital output changes from 0......000 to 0......001.
If the actual measurement value is greater than the theoretical value, it shows the difference between the actual
measurement value of the analog input voltage and the theoretical value (3/2LSB) when the digital output changes
from 0……001 to 0……010.
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(5) Full-scale error
This shows the difference between the actual measurement value of the analog input voltage and the theoretical
value (full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111.
(6) Integral linearity error
This shows the degree to which the conversion characteris tics deviate from the ideal linear relationship. It expr esses
the maximum value of the difference between the actual m easurement value and the ideal straight line when the zero-
scale error and full-scale error are 0.
(7) Differential linearity error
While the ideal width of code output is 1LSB, this indicates the differenc e bet ween the actual measurement value a nd
the ideal value.
Figure 10-42. Zero-Scale Error Figure 10-43. F ull-Scale Error
111
011
010
001 Zero-scale error
Ideal line
000012 3 AV
REF
Digital output (Lower 3 bits)
Analog input (LSB)
111
110
101
0000
AV
REF
−3
Full-scale error
Ideal line
Analog input (LSB)
Digital output (Lower 3 bits)
AV
REF
−2AV
REF
−1
AV
REF
Figure 10-44. Integral Linearity Error Figure 10-45. Differential Linearity Error
0
AVREF
Digital output
Analog input
Integral linearity
error
Ideal line
1......1
0......0
0
AV
REF
Digital output
Analog input
Differential
linearity error
1......1
0......0
Ideal 1LSB width
(8) Conversion time
This expresses the time from the start of sampling to when the digital output is obtained.
The sampling time is included in the conversi on time in the characteristics table.
(9) Sampling time
This is the time the analog s witch is turned on for the analog voltage to be sampled by the sample & hold circuit.
Sampling time
Conversion time
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10.10 Cautions for A/D Converter
(1) Operating current in STOP mode
Shift to STOP mode after stopping the A/D converter (by setting bit 7 (ADCS) of A/D converter mode register 0
(ADM0) to 0). The operating current can be reduced by setting bit 0 (ADCE) of the ADM0 register to 0 at the same
time.
To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1H (IF1H) to 0 and start
operation.
(2) Input range of ANI0 to ANI3 and ANI16 to ANI22 pins
Observe the rated range of the ANI0 to A NI3 and ANI16 to ANI22 pins input voltage. If a voltage of VDD and AVREFP
or higher and VSS and AVREFM or lower (even in the range of absolute maximum ratings) is input to an analog input
channel, the converted value of that channel becomes undefined. In addition, the converted values of the other
channels may also be affected.
When internal reference voltage (1.45 V) is selected refere nce voltage source for the + side of the A/D converter, do
not input internal reference voltage or hig her voltage to a pi n selected by the ADS registe r. However, it is no problem
that a pin not selected by the ADS register is inputed voltage greater than the internal refe rence voltage.
Caution Internal reference voltage (1.45 V) can be used onl y in HS (high-speed main) mod e.
(3) Conflicting operations
<1> Conflict between the A/D conversion result register (ADCR, ADCRH) write and the ADCR or ADCRH register
read by instruction upon the end of conversion
The ADCR or ADCRH register read has priority. After the read operation, the new conversion result is written to
the ADCR or ADCRH registers.
<2> Conflict between the ADCR or ADCRH register write and the A/D converter mode register 0 (ADM0) write, the
analog input channel specific ation register (ADS), or A/D port configuration register (ADPC) write upon the end
of conversion
The ADM0, ADS, or ADPC registers write has priority. The ADCR or ADCRH register write is not performed,
nor is the conversion end interrupt sign al (INTAD) generated.
(4) Noise countermeasures
To maintain the 10-bit resolution, attent ion must be pai d to noise inp ut to the AVREFP, VDD, ANI0 to ANI3, and ANI16 to
ANI22 pins.
<1> Connect a capacitor with a low equivalent resistance and a good frequ ency response to the power supply.
<2> The higher the output impedance of the analog input source, the greater the influence. To reduce the noise,
connecting external C as shown in F ig ure 10-47 is recommended.
<3> Do not switch these pins with other pins during conversion.
<4> The accuracy is improved if the HALT mode is set immediately after the start of conversion.
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Figure 10-46. Analog Input Pin Connection
AV
REFP
or V
DD
ANI0 to ANI3, ANI16 to ANI22
Reference
voltage
input
C = 100 to 1,000 pF
If there is a possibility that noise equal to or higher than AV
REFP
and
V
DD
or equal to or lower than AV
REFM
and V
SS
may enter, clamp with
a diode with a small V
F
value (0.3 V or lower).
(5) Analog input (ANIn) pins
<1> The analog input pins (ANI0 to ANI3) are also used as input port pins (P20 to P23).
When A/D conversion is performed with any of the ANI0 to ANI3 pins selected, do not change output value to
alternat port P20 to P23 while conversion is in progress; otherwise the conversion resolution may be d egraded.
<2> If a pin adjacent to a pin that is being A/D converted is used as a digital I/O port pin, the A/D conversion result
might differ from the expected value due t o a coupling noise. Be sur e to prevent such a pulse from being input
or output.
(6) Input impedance of analog input (ANIn) pins
This A/D converter charges a sampling capacitor for sampling during sampling time.
Therefore, only a leakage current flows when sampling is not in progress, and a current that charges the capacitor
flows during sampling. Conseque ntly, the input impedance fluctuates depending on whether sampling is in pr ogress,
and on the other states.
To make sure that sampling is effective, however, it is recommended to keep the output impedance of the analog
input source to within 1 kΩ, and to connect a capac itor of about 100 pF to the ANI0 to ANI3 and ANI16 to ANI22 pins
(see Figure 10-46).
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(7) Interrupt request flag (ADIF)
The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is
changed.
Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF flag for the
pre-change analog input ma y be set just before the ADS register rewrite. Caution is ther efore required since, at this
time, when ADIF flag is read immediately after the ADS register rewrite, ADIF flag is set despite the fact A/D
conversion for the post-change analog input has not ended.
When A/D conversion is stopped and then resumed, clear ADIF flag before the A/D conversion operation is resumed.
Figure 10-47. Timing of A/D Conversion End Interrupt Request Generation
ADS rewrite
(start of ANIn conversion)
A/D conversion
ADCR
ADIF
ANIn ANIn ANIm ANIm
ANIn ANIn ANIm ANIm
ADS rewrite
(start of ANIm conversion) ADIF is set but ANIm conversion
has not ended.
(8) Conversion results just after A/D conversion start
While in the software trigger mode or hard ware trigger no-wait mode, the first A/D conversion value immediately after
A/D conversion starts may not fall within the rating range if the ADCS bit is set to 1 within 1
μ
s after the ADCE bit was
set to 1. Take measures such as polling the A/D conversion end interrupt request (INTAD) and removing the first
conversion result.
(9) A/D conversion result register (ADCR, ADCRH) read operation
When a write operation is performed to A/D converter mode register 0 (ADM0), analog input channel specification
register (ADS), A/D port configuration register (ADPC), and port mode control register (PMC), the contents of the
ADCR and ADCRH registers may become undefined. Read the conversion result following conversion completion
before writing to the ADM0, ADS, ADPC, or PMC register. Using a timing other than the above may cause an
incorrect conversion result to be read.
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(10) Internal equ ivalent circuit
The equivalent circuit of the analog input block is shown below.
Figure 10-48. Internal Equivalent Circuit of ANIn Pin
ANIn
C1 C2
R1
Table 10-6. Resistance and Cap acitan ce Values of Equivalent Circuit (Referen ce Values)
AVREFP, VDD ANIn Pins R1 [kΩ] C1 [pF C2 [pF]
ANI0 to ANI3 14 8 2.5 3.6 V ≤ VDD ≤ 5.5 V
ANI16 to ANI22 18 7.0
ANI0 to ANI3 39 2.5 2.7 V ≤ VDD < 3.6 V
ANI16 to ANI22 53 7.0
ANI0 to ANI3 231 2.5 1.8 V ≤ VDD < 2.7 V
ANI16 to ANI22 321 7.0
Remark The resistance and capacitance values shown in Table 10-6 are not guaranteed values.
(11) Starting the A/D con verter
Start the A/D converter after the AVREFP and VDD voltages stabilize.
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CHAPTER 11 SERIAL ARRAY UNI T
Serial array unit 0 has two serial channels in 20- and 24-pinproducts and four serial channels in 30-pin products, and
serial array unit 1 mounte d 30-pin pr od ucts, has two serial channels. Each cha nnel can achiev e 3-wire serial (CSI), UART,
and simplified I2C communication.
Function assignment of each channel supported by the RL78/G12 is as shown belo w.
20- or 24-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00 Note 0
1 CSI01Note
UART0
IIC01Note
30-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00Note
1 −
UART0
−
2 − −
0
3 CSI11Note
UART1Note
IIC11Note
0 CSI20Note IIC20Note
1
1 −
UART2 Note
−
Note Provided in the R5F102 products only.
A single channel cannot be us ed under multi ple communic a tion metho ds. When a differe nt communic ation metho d is to
be configured, use another channel.
When using CSI00, CSI20, IIC00, IIC20, UART0, UART1, or UART2, communication between devices with different
voltages (1.8, 2.5, or 3 V) is possible, except when using a 20- or 24-pin product with PIOR set to 1 and UART I/O
assigned to P6. For details about the settings, see 4.4.4 Connecting to external device with different potential (1.8 V,
2.5 V, 3 V).
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11.1 Functions of Serial Array Unit
Each serial interface support ed by the RL78/G12 has the following features.
11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20)
Data is transmitted or received in synchronization with the serial clock (SCK) output from the master channel.
3-wire serial communication is clocked communication performed by using three communication lines: one for the serial
clock (SCK), one for transmitting serial data (SO), one for receiving serial data (SI).
For details about the settings, see 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20)
Communication.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
• Maximum transfer rate
During master communication (CSI00): Max. fMCK/2 Notes 1, 2
During master communication (other than CSI00): Max. fMCK/4 Note 2
During slave communication: Max. fMCK/6 Note 2
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
Notes 1. In master communication (CSI00), maximum transfer rate become fMCK/2 when the following three conditions.
• 2.7 V ≤ VDD ≤ 5.5 V
• fMCK ≤ 24 MHz
• PIOR1 = 0
Other cases, maximum transfer rate become fMCK/4.
2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 28
ELECTRICAL SPECIFICATIONS).
In addition, CSI00 (channel 0 of unit 0) supports the SNOOZE mode. When SCK00 pin input is detected while in the
STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible. Only CSI00 can be
specified.
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11.1.2 UART (UART0 to UART2)
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. By using these two communication lines, each data frame, which consist of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(even-numbered channel) and a channel dedicated to reception (odd-numbered channel).
For details about the settings, see 11.6 Operation of UART (UART0 to UART2) Communication.
[Data transmission/reception]
• Data length of 7, 8, or 9 bits (Only UART0 can be specified for the 9-bit data length)
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse
• Parity bit appending and parit y check functions
• Stop bit appending
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
In addition, UART0 reception (channel 1 of unit 0) supports the SNOOZE mode. When RxD0 pin input is detected
while in the STOP mode, the SNOOZE mode makes data reception that does not require the CPU possible.
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11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20)
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This simplified I2C is designed for single communication with a device such as EEPROM,
flash memory, or A/D converter, and therefore, it functions onl y as a master.
Make sure by using soft ware, as well as operating the control reg isters, that the AC specifications of the start and sto p
conditions are observed.
For details about the settings, see 11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20).
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits (When an addr ess is transmitted, t he addr ess is specified b y the hi gher 7 bits, and the least
significant bit is used for R/W control.)
• Manual generation of start condition and stop condition
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• ACK error, or overrun error
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Arbitration loss detection function
• Wait detection functions
Note When receiving the last data, 0 is written to the SOEmn bit of the serial output enable register m (SOEm) and
serial communication data output is stopped, disabling ACK output. See the processing flow in 11.7.3 (2) for
details.
m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3), mn = 00, 01, 03, 10
Remark To use a fully functional I2C bus, see CHAPTER 12 SERIAL INTERFACE IICA.
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11.2 Configuration of Serial Array Unit
The serial array unit includes the following hardware.
Table 11-1. Configuration of Serial Array Unit
Item Configuration
Shift register 8 or 9 bitsNote 1
Buffer register Lower 8 or 9 bits of serial data register mn (SDRmn)Notes 1 , 2
Serial clock I/O SCK00, SCK01, SCK11, and SCK20 pins (for 3-wire serial I/O), SCL00, SCL01, SCL11, and
SCL20 pins (for simplified I2C)
Serial data input SI00, SI01, SI11, and SI20 pins (for 3-wire serial I/O), RxD0, RxD1, and RxD2 pins (for UART)
Serial data output SI00, SI01, SI11, and SI20 pins (for 3-wire serial I/O), TxD0, TxD1, and TxD2 pins (for UART),
output control circuit
Serial data I/O SDA00, SDA01, SDA11 and SDA20 pins (for simplified I2C)
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Serial standby control register m (SSCm)
• Noise filter enable register 0 (NFEN0)
<Registers of each channel>
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
Control registers
• Port input mode register 0, 1 (PIM0, PIM1)
• Port output mode registers 1, 4, 5 (POM1, POM4, POM5)
• Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4)
• Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)
• Port register 0, 1, 3 to 6 (P0, P1, P3 to P6)
Notes 1. T he number of bits used as shift register or buffer register varies depending on the unit or channel.
mn = 00, 01: lower 9 bits, mn = 02, 03, 10, 11: lower 8 bits
2. The lo wer 8 bits of serial data register mn (SDRmn) can be read or written as the following SFR, depending
on the communication mode.
• During CSIp co mmunication: SIOp (CSIp data register)
• During UARTq reception: RXDq (UART0 receive data register)
• During UARTq transmission: TXDq (UART0 transmit data register)
• During IICr communicati on: SIOr (IICr data register)
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q: UART
number (q = 0 to 2), r: IIC number (r = 00, 01, 11, 20)
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Figure 11-1 or 11-2 shows the block diagram of the serial array unit 0.
Figure 11-1. Block Diagram of Serial Array Unit 0 (20- or 24-pin products)
PRS
013
4
PRS
003
PRS
012
PRS
011
PRS
010
PRS
002
PRS
001
PRS
000
4
f
CLK
f
CLK
/2
0
to f
CLK
/2
15
f
CLK
/2
0
to f
CLK
/2
15
CKS00 MD001CCS00 STS00 MD002
SOE02SOE03 SOE01 SOE00
PM10
SAU0EN
SE03 SE02 SE01 SE00
ST03 ST02 ST01 ST00
SS03 SS02 SS01 SS00
TXE
00
RXE
00
DAP
00
CKP
00
EOC
00
PECT
00
OVCT
00
PTC
001
SLC
000
PTC
000
DIR
00
SLC
001
DLS
001
DLS
000
TSF
00
OVF
00
BFF
00
PEF
00
CK01 CK00
f
MCK
f
TCLK
f
SCK
CK01 CK00
SNFEN
10
SNFEN
00
SNFEN00
PMxx
0SOL02 0 SOL00
CKO02CKO03 CKO01 CKO00 SO02SO03 SO01 SO00
0000 0000
Serial output
enable register 0
(SOE0)
Serial channel
enable status
register 0 (SE0)
Serial channel
stop register 0
(ST0)
Serial channel
start register 0
(SS0)
Noise filter enable
register 0 (NFEN0)
SSEC0 SWC0
Serial standby
control register 0
(SSC0)
Serial output level
register 0 (SOL0)
Serial output register 0 (SO0)
Serial clock select register 0 (SPS0)
Selector Selector
Peripheral enable
register 0 (PER0)
Prescaler
Shift register
Serial data register 00 (SDR00)
(Buffer register block)
(Clock division setting block)
Output latch
(Pxx)
Selector
Clock controller
Selector
Interrupt
controller
Output
controller
Communication controller
Serial flag clear trigger
register 00 (SIR00)
Communication
status
Error
information
Clear
Serial status register 00 (SSR00)
Error controller
Channel 0
Channel 1
Edge/level
detection
Serial communication operation setting register 00 (SCR00)
When UART0
Serial mode register 00 (SMR00)
Communication controller
Error controller
Edge/level
detection
Output latch
(P10)
Mode selection
CSI00 or IIC00
or UART0
(for transmission)
Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: T
X
D0)
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)
Edge
detection
Serial clock I/O pin
(when CSI00: SCK00)
(when IIC00: SCL00)
Serial data input pin
(when CSI00: SI00)
(when IIC00: SDA00)
(when UART0: RxD0)
Serial transfer end interrupt
(when CSI01: INTCSI01)
(when IIC01: INTIIC01)
(when UART0: INTSR0)
Mode selection
CSI01 or IIC01
or UART0
(for reception) Serial transfer error interrupt
(INTSRE0)
Serial data output pin
(when CSI01: SO01)
(when IIC01: SDA01)
Serial data input pin
(when CSI01: SI01)
(when IIC01: SDA01)
Serial clock I/O pin
(when CSI01: SCK01)
(when IIC01: SCL01)
Selector
Noise
elimination
enabled/
disabled
Synchro-
nous
circuit
Synchro-
nous
circuit
Synchro-
nous
circuit
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Figure 11-2. Block Diagram of Serial Array Unit 0 (30-pin products)
SNFEN
10 SNFEN
00
SSEC0 SWC0
SOE03 SOE02 SOE01 SOE00
SE03 SE02 SE01 SE00
ST03 ST02 ST01 ST00
SS03 SS02 SS01 SS00
0SOL02 0 SOL00
CKO03 SO03CKO02 CKO01 CKO00 SO02 SO01 SO000000 0000
PRS
013 PRS
003
PRS
012 PRS
011 PRS
010 PRS
002 PRS
001 PRS
000
SAU0EN
PM1x
PECT
00 OVCT
00
TSF
00 OVF
00
BFF
00 PEF
00
f
CLK
CK01 CK00
CKS00 MD001CCS00 STS00 MD002
PM10
f
MCK
f
TCLK
f
SCK
SNFEN00
CK01 CK00
CK01 CK00
CK01 CK00
SNFEN10
44
TXE RXE DAP CKP EOC PTC SLCPTC DIR SLC DLS DLS
00 00 00 00 00 001 000000 00 001 001 000
Serial output register 0 (SO0)
Serial channel
enable status
register 0 (SE0)
Noise filter enable
register 0 (NFEN0)
Serial standby
control register 0
(SSC0)
Serial channel
start register 0
(SS0)
Serial channel
stop register 0
(ST0)
Serial output
enable register 0
(SOE0)
Serial output level
register 0 (SOL0)
Serial data output pin
(when CSI00: SO00)
(when IIC00: SDA00)
(when UART0: T
X
D0)
Serial data input pin
(when CSI00: SI00)
(when IIC00: SDA00)
(when UART0: RxD0)
Serial data input pin
(when CSI11: SI11)
(when IIC11: SDA11)
Serial data input pin
(when UART1: RxD1)
When UART0
When UART1
Serial transfer end interrupt
(when CSI00: INTCSI00)
(when IIC00: INTIIC00)
(when UART0: INTST0)
Serial data output pin
(when CSI11: SO11)
(when IIC11: SDA11)
Serial transfer end interrupt
(when CSI11: INTCSI11)
(when IIC11: INTIIC11)
(when UART1: INTSR1)
Serial transfer end interrupt
(when UART0: INTSR0)
Serial transfer end interrupt
(INTSRE0)
Serial transfer error interrupt
(INTSRE1)
Serial data output pin
(when UART1: T
X
D1)
Serial transfer end interrupt
(when UART1: INTST1)
Output latch
(P1x)
Output
controller
Interrupt
controller
Serial flag clear trigger
register 00 (SIR00)
Clear
Error
information
Error controller
Serial status register 00 (SSR00)Serial communication operation setting register 00 (SCR00)
Serial mode register 00 (SMR00)
Error controller
Error controller
Serial clock select register 0 (SPS0)
Prescaler
Selector
Selector
Selector
Clock controller
Communication
status
Selector
Selector
Selector
f
CLK
/2
0
to f
CLK
/2
15
Serial data register 00 (SDR00)
Shift register
Communication controller
Mode selection
CSI00 or IIC00
or UART0
(for transmission)
Communication controller
Mode selection
CSI01 or IIC01
or UART0
(for reception)
Communication controller
Mode selection
CSI11 or IIC11
or UART1
(for reception)
Communication controller
Mode selection
CSI10 or IIC10
or UART1
(for transmission)
(Clock division setting block) (Buffer register block)
Channel 0
Channel 1
Channel 2
Channel 3
Synchro-
nous
circuit
Synchro-
nous
circuit
Synchro-
nous
circuit
Synchro-
nous
circuit
Edge
detection
Output latch
(P10)
Edge/
level
detection
Edge/level
detection
Edge/level
detection
Edge/level
detection
Noise
elimination
enabled/
disabled
Noise
elimination
enabled/
disabled
fCLK/20 to fCLK/215
Peripheral enable
register 0 (PER0)
Serial clock I/O pin
(when CSI11: SCK11)
(when IIC11: SCL11)
Serial clock I/O pin
(when CSI00: SCK00)
(when IIC00: SCL00)
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Figure 11-3 shows the block diagram of the serial array unit 0.
Figure 11-3. Block Diagram of Serial Array Unit 1 (30-pin products)
PRS
113
4
PRS
103
PRS
112
PRS
111
PRS
110
PRS
102
PRS
101
PRS
100
4
fCLK
SAU1EN
10 10 10 10 10 101 100100 10 101 100
TS F
10
OVF
10
BFF
10
PEF
10
CK11 CK10
f
MCK
f
TCLK
SNFEN20
0SOE11 SOE10
SE11 SE10
ST11 ST10
SS11 SS10
00 SOL10
111 CKO11 CKO10 SO11 SO10
0000 0000
0
1
0
0
0
00
00
PM15
f
SCK
SNFEN
20
CK11 CK10
Serial output register 1 (SO1)
Serial channel
enable status
register 1 (SE1)
Noise filter enable
register 0 (NFEN0)
Serial channel
start register 1
(SS1)
Serial channel
stop register 1
(ST1)
Serial output
enable register 0
(SOE1)
Serial output level
register 0 (SOL1)
Serial clock select register 1 (SPS1)
Prescaler
Selector Selector
fCLK/20 to fCLK/215
f
CLK
/2
0
to f
CLK
/2
15
Peripheral enable
register 0 (PER0)
Serial data register 10 (SDR10)
(Clock division setting block) (Buffer register block)
Selector
Selector
Clock controller
Shift register
Channel 0
Synchro-
nous
circuit
Synchro-
nous
circuit
Edge
detection
Output latch
(P15)
Edge/
level
detection
Noise
elimination
enabled/
disabled
MD101MD102CKS10 CCS10
TXE RXE DAP CKP EOC PTC SLCPTC DIR SLC DLS
Serial communication operation setting register 10 (SCR10)
Serial mode register 10 (SMR10)
When UART2
Serial data input pin
(when CSI20: SI20)
(when IIC20: SDA20)
(when UART2: RxD2)
Serial clock I/O pin
(when CSI20: SCK20)
(when IIC20: SCL20)
Selector
Channel 1
Edge/level
detection
PM14 or PM13
Serial data output pin
(when CSI20: SO20)
(when IIC20: SDA20)
(when UART2: TXD2)
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Output latch
(P14 or P13)
Output
controller
Interrupt
controller
PECT
10
OVCT
10
Serial flag clear trigger
register 10 (SIR10)
Clear
Error
information
Error controller
Communication
status
Communication controller
Mode selection
CSI20 or IIC20
or UART2
(for transmission)
Serial transfer end interrupt
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Communication controller
Mode selection
CSI21 or IIC21
or UART2
(for reception)
Serial status register 10 (SSR10)
Error controller
SSEC1 SWC1
Serial standby
control register 1
(SSC0)
The serial array unit 1 is available only in the 30-pin R5F 102 products.
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(1) Shift register
This is an 8-bit register that converts parallel data into serial data or vice versa.
In case of the UART communication of nine bits of data using UART0, nine bits (bits 0 to 8) are used.
During reception, it converts data input to the serial pin into parallel data.
When data is transmitted, the value set to this register is output as serial data from the serial output pin.
The shift register cannot be directly manipulated b y progr am.
To read or write to the shift register, use the lower 8/9 bits of serial data register mn (SDRmn).
8 7 6 5 4 3 2 1 0
Shift register
(2) Lower 8/9 bits of the serial data regi ster mn (SDRmn)
The SDRmn register is the transmit/receive data register (16 bits) of channel n. Bits 8 to 0 (lower 9 bits) of SDR00
and SDR01 or Bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, and SDR11 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock ( fMCK, fSCK).
When data is received, parallel data convert ed by the shift register is stored in the lower 8/9 bits. When data is to
be transmitted, set transmit data to be transferred to the shift register to the lower 8/9 bits.
The length of data stored in th e lower 8/9 bits of this re gister is as follo ws, depending on the settin g of bits 0 and 1
(DLSmn0, DLS0m1) of serial communication operation setting register mn (SCRmn), regardless of the output
sequence of the data.
• 7-bit data length (stored in bits 0 to 6 of SDRmn register)
• 8-bit data length (stored in bits 0 to 7 of SDRmn register)
• 9-bit data length (stored in bits 0 to 8 of SDRmn register (mn = 00, 01)) (settable in UART 0 mode only)
The SDRmn register can be read or written in 16-bit units.
The lower 8/9 bits of the SDRmn register can be read or written in 8-bit units as the following SFR, depending on
the communication mode. Note, ho wever, writing in 8-bits units is prohibited when the operation is stop ped (SEmn
= 0).
• During CSIp communication: SIOp (CSIp data register)
• During UARTq reception: RXDq (UARTq receive data register)
• During UARTq transmission: TXDq (UARTq transmit data register)
• During IICr communication: SIOr (IICr data register)
Reset signal generation clears the SDRmn register to 0000H.
Remarks 1. After data is received, “0” is applied to some bits of bits 0 to 8 to make up the specified data length.
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q:
UART number (q = 0 to 2), r: IIC number (r = 00, 01, 11, 20)
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Figure 11-4. Format of Serial Data Register mn (SDRmn) (mn = 00, 01)
Address: FFF10H, FFF11H (SDR00), FFF12H, FFF13H (SDR01) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDR0n
8 7 6 5 4 3 2 1 0
Shift register
Remark For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial
Array Unit.
Figure 11-5. Format of Serial Data Register mn (SDRmn) (mn = 02, 03, 10, 11)
Address: FFF44H, FFF45H (SDR02), FFF46H, FFF47H (SDR03) After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDR0n 0
8 7 6 5 4 3 2 1 0
Shift register
Caution Be sure to clear bit 8 to “0”.
Remark For the function of the higher 7 bits of the SDRmn register, see 11.3 Registers Controlling Serial
Array Unit.
FFF11H (SDR00) FFF 11 H (SDR00 )
FFF45H (SDR02) FFF44H (SDR02)
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11.3 Registers Controlling Serial Array Unit
Serial array unit is controlled by the following registers.
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial data register mn (SDRmm)
• Serial flag clear trigger register mn (SIRmn)
• Serial status register mn (SSRmn)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial channel enable status register m (SEm)
• Serial output enable register m (SOEm)
• Serial output level register m (SOLm)
• Serial output register m (SOm)
• Serial standby control register m (SSCm)
• Noise filter enable register 0 (NFEN0)
• Port input mode registers 0, 1 (PIM0, PIM1)
• Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5)
• Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4)
• Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)
• Port registers 0, 1, 3 to 6 (P0, P1, P3 to P6)
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.1 Peripheral enable register 0 (PER0)
PER0 is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a hardware
macro that is not used is stopped in order to reduce the power consumption and noise.
When serial array unit 0 is used, be sure to set bit 2 (SAU0EN) of this register to 1.
When serial array unit 1 is used, be sure to set bit 3 (SAU1EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the PER0 register to 00H.
Figure 11-6. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1ENNote SAU0EN 0 TAU0EN
SAU1EN Control of serial array unit 1 input clock supply
0 Stops supply of input clock (fixed as “0” in 20- or 24-pin products).
• SFR used by serial array unit 1 cannot be written.
• Serial array unit 1 is in the reset status.
1 Enables input clock supply.
• SFR used by serial array unit 1 can be read/written.
SAU0EN Control of serial array unit 0 input clock supply
0 Stops supply of input clock.
• SFR used by serial array unit 0 cannot be written.
• Serial array unit 0 is in the reset status.
1 Enables input clock supply.
• SFR used by serial array unit 0 can be read/written.
Note Be sure to clear SAU1EN bit to “0” in 20- or 24-pin products.
Cautions 1. When setting serial array unit m, b e sure to set the SAUmEN bit to 1 first. If SAUmEN = 0, writing
to a control register of serial array unit m is ignored, and, even if the register is read, only the
default value is read (except for the noise filter enable register 0 (NFEN0), port input mode
register x (PIMx), port output mode register x (POMx), port mode register xx (PMxx), port mode
control register xx (PMCxx), and port register xx (Pxx)).
2. Be sure to clear the undefined bits to 0.
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11.3.2 Serial clock select register m (SPSm)
The SPSm register is a 16-bit register that is used to select two types of operation clocks (CKm0, CKm1) that are
commonly supplied to each channel. CKm1 is selected by bi ts 7 to 4 of the SPSm register, and CKm0 is selected
by bits 3 to 0.
Rewriting the SPSm register is prohibited when the register is in operation (when SEmn = 1).
The SPSm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SPSm register can be set with an 8-bit memory manipulation instruction with SPSmL.
Reset signal generation clears the SPSm register to 0000H.
Figure 11-7. Format o f Serial Clock Select Register m (SPSm)
Address: F0126H, F0127H (SPS0), F0166H, F0167H (SPS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPSm 0 0 0 0 0 0 0 0
PRS
m13 PRS
m12 PRS
m11 PRS
m10 PRS
m03 PRS
m02 PRS
m01 PRS
m00
Section of operation clock (CKmk) Note PRS
mk3 PRS
mk2 PRS
mk1 PRS
mk0 f
CLK =
2 MHz
fCLK =
4 MHz
fCLK =
8 MHz
fCLK =
16 MHz
fCLK =
20 MHz
fCLK =
24 MHz
0 0 0 0 fCLK 2 MHz 4 MHz 8 MHz 16 MHz 20 MHz 24 MHz
0 0 0 1 fCLK/2 1 MHz 2 MHz 4 MHz 8 MHz 10 MHz 12 MHz
0 0 1 0 fCLK/22 500 kHz 1 MHz 2 MHz 4 MHz 5 MHz 6 MHz
0 0 1 1 fCLK/23 250 kHz 500 kHz 1 MHz 2 MHz 2.5 MHz 3 MHz
0 1 0 0 fCLK/24 125 kHz 250 kHz 500 kHz 1 MHz 1.25 MHz 1.5 MHz
0 1 0 1 fCLK/25 62.5 kHz 125 kHz 250 kHz 500 kHz 625 kHz 750 kHz
0 1 1 0 fCLK/26 31.3 kHz 62.5 kHz 125 kHz 250 kHz 313 kHz 375 kHz
0 1 1 1 fCLK/27 15.6 kHz 31.2 kHz 62.5 kHz 125 kHz 156 kHz 187.5 kHz
1 0 0 0 fCLK/28 7.81 kHz 15.6 kHz 31.2 kHz 62.5 kHz 78.1 kHz 93.75 kHz
1 0 0 1 fCLK/29 3.91 kHz 7.8 kHz 15.6 kHz 31.2 kHz 39.1 kHz 46.88 kHz
1 0 1 0 fCLK/210 1.95 kHz 3.9 kHz 7.8 kHz 15.6 kHz 19.5 kHz 23.44 kHz
1 0 1 1 fCLK/211 977 Hz 1.95 kHz 3.9 kHz 7.8 kHz 9.77 kHz 11.72 kHz
1 1 0 0 fCLK/212 488 Hz 0.97 kHz 1.95 kHz 3.9 kHz 4.88 kHz 5.86 kHz
1 1 0 1 fCLK/213 244 Hz 485 Hz 0.97 kHz 1.95 kHz 2.44 kHz 2.93 kHz
1 1 1 0 fCLK/214 122 Hz 242 Hz 485 Hz 0.97 kHz 1.22 kHz 1.47 kHz
1 1 1 1 fCLK/215 61 Hz 121 Hz 242 Hz 485 Hz 610 Hz 732 Hz
Note When changing the clock sel ected for fCLK (by changing the system clock control register (CKC) value), do
so after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array
unit (SAU).
Caution Be sure to clear bits 15 to 8 to “0”.
Remarks 1. f
CLK: CPU/peripheral hardware clock freque ncy
2. m: Unit numbe r (m = 0, 1) k = 0, 1
<R>
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11.3.3 Serial mode register mn (SMRmn)
The SMRmn register is a register that sets an operation mode of chan nel n. It is also used to select an operation
clock (fMCK), specify whether the serial clock (f SCK) may be input or not, set a start trigger, an operati on mode (CSI,
UART, or I2C), and an interrupt source. This register is also used to invert the level of the receive data only in the
UART mode.
Rewriting the SMRmn register is prohibited when the register is in operation (when SEmn = 1). However, the
MDmn0 bit can be rewritten during oper ation.
The SMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SMRmn register to 0020H.
Figure 11-8. Format of Serial Mode Register mn (SMRmn) (1/2)
Address: F0110H, F0111H (SMR00), F0116H, F0117H (SMR03) After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS
mn CCS
mn 0 0 0 0 0
STS
mnNote 0 SIS
mn0Note 1 0 0
MD
mn2 MD
mn1 MD
mn0
CKS
mn Selection of operation clock (fMCK) of channel n
0 Operation clock CK00 set by the SPSm register
1 Operation clock CK01 set by the SPSm register
Operation clock (fMCK) is used by the edge detector. In addition, depending on the setting of the CCSmn bit and the
higher 7 bits of the SDRmn register, a transfer clock (fTCLK) is generated.
CCS
mn Selection of transfer clock (fTCLK) of channel n
0 Divided operation clock fMCK specified by the CKSmn bit
1 Clock input fSCK from the SCKp pin (slave transfer in CSI mode)
Transfer clock fTCLK is used for the shift register, communication controller, output controller, interrupt controller, and
error controller. When CCSmn = 0, the division ratio of operation clock (fMCK) is set by the higher 7 bits of the
SDRmn register.
STS
mn
Note
Selection of start trigger source
0 Only software trigger is valid (selected for CSI, UART transmission, and simplified I2C).
1 Valid edge of the RXDq pin (selected for UART reception)
Transfer is started when the above source is satisfied after 1 is set to the SSm register.
Note Provided in the SMR01, SMR03, and SMR11 registers only.
Caution Do not change the value of the undefined bits (fixed to 0 or 1).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20), q: UART
number (q = 0 to 2)
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Figure 11-8. Format of Serial Mode Register mn (SMRmn) (2/2)
Address: F0110H, F0111H (SMR00) t o F0116H, F0117H (SMR03), After reset: 0020H R/W
F0150H, F0151H (SMR10), F0152H, F0153H (SMR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKS
mn CCS
mn 0 0 0 0 0
STS
mnNote 0 SIS
mn0Note 1 0 0
MD
mn2 MD
mn1 MD
mn0
SIS
mn0
Note
Controls inversion of level of receive data of channel n in UART mode
0 Falling edge is detected as the start bit.
The input communication data is captured as is.
1 Rising edge is detected as the start bit.
The input communication data is inverted and captured.
MD
mn2 MD
mn1 Setting of operation mode of channel n
0 0 CSI mode
0 1 UART mode
1 0 Simplified I2C mode
1 1 Setting prohibited
MD
mn0 Selection of interrupt source of channel n
0 Transfer end interrupt
1 Buffer empty interrupt
(Occurs when data is transferred from the SDRmn register to the shift register.)
For successive transmission, the next transmit data is written by setting the MDmn0 bit to 1 when SDRmn data has
run out.
Note Provided in the SMR01, SMR03, and SMR11 registers only.
Caution Do not change the value of the undefined bits (fixed to 0 or 1).
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
11.3.4 Serial communication operation setting register mn (SCRmn)
The SCRmn register is a communication operation setting register of channel n. It is used to set a data
transmission/reception mode, phase of data and clock, whether an error signal is to be masked or not, parity bit,
start bit, stop bit, and data length.
Rewriting the SCRmn register is prohibite d when the register is in operation ( when SEmn = 1).
The SCRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation sets the SCRmn register to 0087H.
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Figure 11-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (1/2)
Address: F0118H, F0119H (SCR00 ) to F011EH, F011FH (SCR03) After reset: 0087H R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE
mn RXE
mn DAP
mn CKP
mn 0 EOC
mn PTC
mn1 PTC
mn0 DIR
mn 0 SLCm
n1Note 1 SLC
mn0 0 1
DLSm
n1
Note 2
DLS
mn0
TXEmn RXEmn Setting of operation mode of channel n
0 0 Disable communication.
0 1 Reception only
1 0 Transmission only
1 1 Transmission/reception
DAPmn CKPmn Selection of data and clock phase in CSI mode Type
0 0
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
1
0 1
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p input timing
2
1 0
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
3
1 1
D7 D6 D5 D4 D3 D2 D1 D0
SCKp
SOp
SI
p
input timing
4
Be sure to set DAPmn, CKPmn = 0, 0 in the UART mode and simplified I2C mode.
EOCmn Selection of masking of error interrupt signal (INTSREx (x = 0 to 3))
0 Masks error interrupt INTSREx (INTSR0 is not masked).
1 Enables generation of error interrupt INTSREx (INTSRx is masked if an error occurs).
Set EOCmn = 0 in the CSI mode, simplified I2C mode, and during UART transmission Note 3.
Notes 1. Provided in the SCR00, SCR02, and SCR10 registers only.
2. Provided in the SCR00 a nd SCR01 registers only (others are fixed to 1).
3. If EOCmn is not cleared for CSImn, error interrupt INTSREn may be generated.
Caution Be sure to set the bit 2 to “1”, and clear the undefined bits to 0.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), p: CSI number (p = 00, 01, 11, 20)
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Figure 11-9. Format of Serial Communication Operation Setting Register mn (SCRmn) (2/2)
Address: F0118H, F0119H (SCR00 ), F011EH, F011FH (SCR03) After reset: 0087H R/W
F0158H, F0159H (SCR10), F015AH, F015BH (SCR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXE
mn RXE
mn DAP
mn CKP
mn 0 EOC
mn PTC
mn1 PTC
mn0 DIR
mn 0 SLCm
n1Note 1 SLC
mn0 0 1
DLSm
n1Note 2 DLS
mn0
Setting of parity bit in UART mode
PTC
mn1 PTC
mn0 Transmission Reception
0 0 Does not output the parity bit. Receives without parit y
0 1 Outputs 0 parityNote 3. No parity judgment
1 0 Outputs even parity. Judged as even parity.
1 1 Outputs odd parity. Judges as odd parity.
Be sure to set PTCmn1, PTCmn0 = 0, 0 in the CSI mode and simplified I2C mode.
DIRmn Selection of data transfer sequence in CSI and UART modes
0 Inputs/outputs data with MSB first.
1 Inputs/outputs data with LSB first.
Be sure to clear DIRmn = 0 in the simplified I2C mode.
SLCm
n1Note 1 SLCm
n0 Setting of stop bit in UART mode
0 0 No stop bit
0 1 Stop bit length = 1 bit
1 0 Stop bit length = 2 bits (mn = 00, 02, 10 only)
1 1 Setting prohibited
When the transfer end interrupt is selected, the interrupt is generated when all stop bits have been completely
transferred.
Set the stop bit length to 1 bit (SLCmn1, SLCmn0 = 0, 1) during UART reception and in the simplified I2C mode.
Set no stop bit (SLCmn1, SLCmn0 = 0, 0) in the CSI mode.
DLSmn
1
Note 2
DLSmn
0 Setting of data length in CSI and UART modes
0 1 9-bit data length ( stored in bits 0 to 8 of the SDRmn register (mn = 00, 01)) (settable in UART0 mode on ly)
1 0 7-bit data length (stored in bits 0 to 6 of the SDRmn register)
1 1 8-bit data length (stored in bits 0 to 7 of the SDRmn register)
Other than above
Setting prohibited
Be sure to set DLSmn0 = 1 in the simplified I2C mode.
Notes 1. Provided in the SCR00, SCR02, and SCR10 registers only.
2. Provided in the SCR00 a nd SCR01 registers only (others are fixed to 1).
3. 0 is always added regardless of the data contents.
Caution Be sure to set bit 2 to 1 and clear undefined bits to 0.
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
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11.3.5 Higher 7 bits of the serial data register mn (SDRmn)
The SDRmn register is the transmit/receive data register of channel n (16 bits). Bits 8 to 0 (lower 9 bits) of SDR00
and SDR01 or bits 7 to 0 (lower 8 bits) of SDR02, SDR03, SDR10, and SDR11 function as a transmit/receive
buffer register, and bits 15 to 9 are used as a register that sets the division ratio of the operation clock ( fMCK, fSCK).
If the CCSmn bit of serial mode register mn (SMRmn) is cleared to 0, the operating clock divided by the division
ratios specified by the higher 7 bits of the SDRmn register is used as the transfer clock.
The lower 8/9 bits of the SDRmn register function as a transmit/receive buffer register. During reception, the
parallel data converted by the shift register is stored in the lower 8/9 bits, and during transmission, the data to be
transmitted to the shift register is set to the lower 8/9 bits.
The SDRmn register can be read or written in 16-bit units.
However, the h igher 7 bits can be written or read o nly when the operation is stopped (SE mn = 0). During oper atio n
(SEmn = 1), a value is written only to the l ower 8/9 bits of the SDRmn register. When the SDRm n register is read
during operation, 0 is al ways read.
Reset signal generation clears the SDRmn register to 0000H.
Figure 11-10. Format of Serial Data Register mn (SDRmn)
Address: FFF10H, FFF11H (SDR00), FFF12H, F FF13H (SDR01) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
Address: FFF44H, FFF45H (SDR02), FFF46H, F FF47H (SDR03) After reset: 0000H R/W
FFF48H, FFF49H (SDR10), FFF4AH, FFF4BH (SDR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0
SDRmn[15:9] Transfer clock setting by dividing the operating clock (fMCK)
0 0 0 0 0 0 0 fMCK/2, fSCK/2 (in CSI slave)
0 0 0 0 0 0 1 fMCK/4
0 0 0 0 0 1 0 fMCK/6
0 0 0 0 0 1 1 fMCK/8
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1 1 1 0 fMCK/254
1 1 1 1 1 1 1 fMCK/256
Cautions 1. Be sure to clear bit 8 of SDR02, SDR03, SDR10, and SDR11 registers to 0.
2. Setting SDRmn[15:9] = 0000000B to 00000 01B is prohi bited w hen UART is used. Set SDRmn[15: 9]
to 0000010B or greater.
3. Setting SDRmn[15:9] = 0000000B is prohibited when simplified I2C is used. Set SDRmn[15:9] to
0000001B or greater.
4. Do not write 8-bit data to the lower 8 bits if operation is stopped (SEmn = 0). Otherwise, the
higher 7 bits are cleared to 0.
Remarks 1. For the function of the lower 8/9 bits of the SDRmn register, see 11.2 Configuration of Serial Array
Unit.
2. m: Unit numbe r (m = 0, 1) n: Channel number (n = 0 to 3)
FFF11H (SDR00) FFF10H (SDR00)
FFF45H (SDR02) FFF44H (SDR02)
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11.3.6 Serial flag clear trigger register mn (SIRmn)
The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn (SSRmn) is cleared to 0. Because the SIRmn regist er is a trigger register, it is
cleared immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulati on instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 11-11. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00), F010EH, F010FH (SIR03), After reset: 0000H R/W
F0148H, F0149H (SIR10), F014AH, F014BH (SIR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SIRmn 0 0 0 0 0 0 0 0 0 0 0 0 0
FECT
mnNote PECT
mn OVCT
mn
FECT
mn Clear trigger of framing error of channel n
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PECT
mn Clear trigger of parity error flag of channel n
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVCT
mn Clear trigger of overrun error flag of channel n
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
Note Provided in the SIR01, SIR03, SIR11 registers only.
Caution Be sure to set undefined bits to 0
Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
2. W hen the SIRmn register is read, 0000H is always read.
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11.3.7 Serial status register mn (SSRmn)
The SSRmn register indicates the communication status and error occurrence status of channel n. The errors
indicated by this register are framing errors, parity errors, and overrun errors.
The SSRmn register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSRmn register can be read with an 8-bit memory manipulation instruction as SSRmnL.
Reset signal generation clears the SSRmn register to 0000H.
Figure 11-12. Format of Serial Status Register mn (SSRmn) (1/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03) After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn BFF
mn 0 0
FEF
mnNote PEF
mn OVF
mn
TSF
mn Communication status indication flag of channel n
0 Communication is stopped or suspended.
1 Communication is in progress.
<Clear conditions>
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is
set to 1 (communication is suspended).
• Communication ends.
<Set condition>
• Communication starts.
BFF
mn Buffer register status indication flag of channel n
0 Valid data is not stored in the SDRmn register.
1 Valid data is stored in the SDRmn register.
<Clear conditions>
• Transferring transmit data from the SDRmn register to the shift register ends during transmission.
• Reading receive data from the SDRmn register ends during reception.
• The STmn bit of the STm register is set to 1 (communication is stopped) or the SSmn bit of the SSm register is set
to 1 (communication is enabled).
<Set conditions>
• Transmit data is written to the SDRmn register while the TXEmn bit of the SCRmn register is set to 1
(transmission or transmission and reception mode in each communication mode).
• Receive data is stored in the SDRmn register while the RXEmn bit of the SCRmn register is set to 1 (reception or
transmission and reception mode in each communication mode).
• A reception error occurs.
Note Provided in the SSR01, SSR03, SSR11 registers only.
Caution If data is written to the SDRmn register when BFFmn = 1, the transmit/receive data stored in the
register is discarded and an overrun error (OVEmn = 1) is detected .
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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Figure 11-12. Format of Serial Status Register mn (SSRmn) (2/2)
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03) After reset: 0000H R
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11)
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSRmn 0 0 0 0 0 0 0 0 0
TSF
mn BFF
mn 0 0
FEF
mnNote PEF
mn OVF
mn
FEF
mn
Note
Framing error detection flag of channel n
0 No error occurs.
1 An error occurs (during UART reception).
<Clear condition>
• 1 is written to the FECTmn bit of the SIRmn register.
<Set condition>
• A stop bit is not detected when UART reception ends.
PEF
mn Parity / ACK error detection flag of channel n
0 No error occurs.
1 Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission).
<Clear condition>
• 1 is written to the PECTmn bit of the SIRmn register.
<Set condition>
• The parity of the transmit data and the parity bit do not match when UART reception ends (parity error).
• No ACK signal is returned from the slave channel at the ACK reception timing during I2C transmission (ACK is
not detected).
OVF
mn Overrun error detection flag of channel n
0 No error occurs.
1 An error occurs
<Clear condition>
• 1 is written to the OVCTmn bit of the SIRmn register.
<Set condition>
• Even though receive data is stored in the SDRmn register, that data is not read and transmit data or the next
receive data is written while the RXEmn bit of the SCRmn register is set to 1 (reception or transmission and
reception mode in each communication mode).
• Transmit data is not ready for slave transmission or transmission and reception in CSI mode.
Note Provided in the SSR01, SSR03, SSR11 registers only.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.8 Serial channel start register m (SSm)
The SSm register is a trigger register that is used to enable communication/count for each channel.
When 1 is written to a bit of this register (SSmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is set to 1 (operation is enabled). Because the SSmn bit is a trigger bit, it is cleared immediatel y
when SEmn = 1.
The SSm register can be set by a 16-bit memory manipulation instructi on.
The lower 8 bits of the SSm register can be set with a 1-bit or 8-bit memory manipulati on instruction with SSmL.
Reset signal generation clears the SSm register to 0000H.
Figure 11-13. Format of Serial Channel Start Register m (SSm)
Address: F0122H, F0123H (SS0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS0 0 0 0 0 0 0 0 0 0 0 0 0
SS03
Note1 SS02
Note1 SS01 SS00
Address: F0162H, F0163H (SS1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SS1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS11 SS10
SSmn Operation start trigger of channel n
0 No trigger operation
1 Sets the SEmn bit to 1 and enters the communication wait status Note2.
Notes 1. 30-pin product only.
2. If set the SSmn = 1 to during a communication operation, will wait status to stop the
communication. At this time, holding status value of control register and shift register, SCKmn and
SOmn pins, and FEFmn, PEFmn, OVFmn flags.
Cautions 1. Be sure to clear the undefined bits to 0.
2. For the UART reception, set the RXEmn bit of SCRmn register to 1, and then be sure to
set SSmn to 1 after 4 or more fMCK clocks have elapsed.
Remarks 1. m: Unit numbe r (m = 0, 1) n: Channel number (n = 0 to 3)
2. When the SSm register is read, 0000H is al wa ys read.
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11.3.9 Serial channel stop register m (STm)
The STm register is a trigger register that is used to enable stopping communication/count for each channel.
When 1 is written to a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared
immediately when SEmn = 0.
The STm register is set by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction as STmL.
Reset signal generation clears the STm register to 0000H.
Figure 11-14. Format of Serial Channel Stop Register m (STm)
Address: F0124H, F0125H (ST0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST0 0 0 0 0 0 0 0 0 0 0 0 0
ST03
Note1 ST02
Note1 ST01 ST00
Address: F0164H, F0165H (ST1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ST11 ST10
STm
n Operation stop trigger of channel n
0 No trigger operation
1 Clears the SEmn bit to 0 and stops the communication operationNote2
Notes 1. 30-pin product only.
2. While holding the value of the control register and shift register, and the status of the, SCKmn,
SOmn pins, FEFmn, PEFmn, OVFmn flag.
Caution Be sure to clear the undefined bits to 0.
Remarks 1. m: Unit numbe r (m = 0, 1) n: Channel number (n = 0 to 3)
2. When the STm register is read, 0000H is always read.
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11.3.10 Serial chan nel enable status register m (SEm)
The SEm register indicates whether the data transmission/reception operation of each channel is enabled or
disabled.
When 1 is written to a bit of serial channel start register m (SSm), the corresponding bit of this register is set to 1.
When 1 is written to a bit of serial channel stop register m (ST m), the corresponding bit o f this register is cleared t o
0.
If the operation of channel n is enabled, the value of the CKOmn bit (serial clock output of channel n) of serial
output register m (SOm) cannot be rewritten b y software, and a value is o utput from the serial clock pin according
to the communication operation.
If the operation of channel n is disabled, the value of the CKOmn bit of the SOm register can be set by software
and its value is output from the serial clock pin. In this way, any waveform, such as that of a start condition/stop
condition, can be created by software.
The SEm register can be read by a 16-bit memor y manipula tion instruction.
The lower 8 bits of the SEm register can be set with a 1-bit or 8-bit memory manipulation instruction as SEmL.
Reset signal generation clears the SEm register to 0000H.
Figure 11-15. Format of Serial Channel Enable Status Register m (SEm)
Address: F0120H, F0121H (SE0) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE0 0 0 0 0 0 0 0 0 0 0 0 0
SE03
Note SE02
Note SE01 SE00
Address: F0160H, F0161H (SE1) After reset: 0000H R
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SE1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SE11 SE11
SEmn Indication of operation enable/disable status of channel n
0 Operation is disabled (stopped)
1 Operation is enabled.
Note 30-pin product only.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.11 Serial output enable register m (SOEm)
The SOEm register is used to enable or disable output of the serial communication operation of each channel.
If serial output is enabled for channel n, the value of the SOmn bit of serial output register m (SOm) cannot be
rewritten by software, and a value is output from the serial data output pin according to the communication
operation.
If serial output is disabled for channel n, the SOmn bit value of the SOm register can be set by software, and its
value is output from the serial data output pin. In this way, any waveform, such as that of a start condition/stop
condition, can be created by software.
The SOEm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOEm register can be set with a 1-bit or 8-bit memory manipulation instruction as SOEmL.
Reset signal generation clears the SOEm register to 0000H.
Figure 11-16. Format of Serial Output Enable Register m (SOEm)
Address: F012AH, F012BH(SOE0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE0 0 0 0 0 0 0 0 0 0 0 0 0
SOE0
3 Note1 SOE0
2 Note1 SOE0
1 Note2 SOE
00
Address: F016AH, F016BH(SOE1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOE1 Note1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SOE
10
SOEmn Serial output enable/disable of channel n
0 Disables output by serial communication operation.
1 Enables output by serial communication operation.
Notes 1. 30-pin product only.
2. 20-, 24-pin product only.
Caution Be sure to clear the undefined bits to 0.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.12 Serial ou t put register m (SOm)
The SOm register is a buffer register for serial output of each channel.
The value of the SOmn bit of this register is output from the serial data output pin of channel n.
The value of the CKOmn bit of this register is output from the serial clock o utput pin of ch ann el n.
The SOmn bit of this register can be rewritten by software only when serial output is disabled (SOEmn = 0). When
serial output is enabled (SOEmn = 1), rewriting by software is ignored, and the value of the register can be
changed only by a serial communication operation.
The CKOmn bit of this register can be re written by software only when the channel operation is stopped (SEmn =
0). While channel operation is enabled (SEmn = 1), re writing by software is ignored, and the value of the CKOmn
bit can be changed only by a serial communication operation.
To use the pin for serial interface as a port function pin, set the corresponding CKOmn and SOmn bit to 1.
The SOm register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears the SOm register to 0F0FH.
Figure 11-17. Format of Serial Output Register m (SOm)
Address: F0128H, F0129H(SO0) After reset: 0F0FH R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO0 0 0 0 0
CKO
03 1 CKO
01 CKO
00 0 0 0 0
SO
03Note1 SO
02Note1 SO
01Note2 SO
00
Address: F0168H, F0169H(SO1) After reset: 0F0FH R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SO1 Note1 0 0 0 0 1 1 1
CKO
10 0 0 0 0 1 1 1
SO
10
CKOmn Serial clock output of channel n
0 Serial clock output value is “0”.
1 Serial clock output value is “1”.
SOmn Serial data output of channel n
0 Serial data output value is “0”.
1 Serial data output value is “1”.
Notes 1. 30-pin product only.
2. 20-, 24-pin product only.
Caution Be sure to not change the undefined bits.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.13 Serial output level register m (SOLm)
The SOLm register is used to set inversion of the data output level of each chan nel.
This register can be set only in the UART mode. Be sure to set 0 to corresponding bit in the CSI mode and
simplified I2C mode.
Inverting channel n by using this reg ister is reflected on pin output only when serial output is enabled (SOEmn = 1).
When serial output is disabled (SOEmn = 0), the value of the SOmn bit is output as is.
Rewriting the SOLm register is prohibited during operation (SEmn = 1).
The SOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SOLm register can be set with an 8-bit memory manipulation instruction as SOLmL.
Reset signal generation clears the SOLm register to 0000H.
Figure 11-18. Format of Serial Output Level Register m (SOLm)
Address: F0134H, F0135H (SOL0) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOL0 0 0 0 0 0 0 0 0 0 0 0 0 0
SOL
02Note 0 SOL
00
Address: F0174H, F0175H (SOL1) After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOL1 Note 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SOL
10
SOL
mn Selects inversion of the level of the transmit data of channel n in UART mode
0 Communication data is output as is.
1 Communication data is inverted and output.
Note 30-pin product only.
Caution Be sure to clear the undefined bits to 0.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
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11.3.14 Serial standby control register 0 (SSC0)
The SSC0 register is used to control the startup of reception (the SNOOZE mode) while in the STOP mode when
receiving CSI00 or UART0 serial data.
The SSC0 register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SSC0 register can be set with an 8-bit memory manipulati on instruction as SSC0L.
Reset signal generation clears the SSC0 register to 0000H.
Caution The maximum transfer r ate in the SNOOZE mode is as follows.
• When using CSI00: 1 Mb ps
• When using UART0: 9600 bps
Figure 11-19. Format of Serial Standby Control Register 0 (SSC0)
Address: F0138H, F0139H After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSCm 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SSEC
0 SWC
0
SSEC
0 Selection of whether to enable or stop the generation of transfer end interrupts
0 Enable the generation of error interrupts (INTSRE0).
In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared:
• When the SWC0 bit is cleared to 0
• When the UART reception start bit is mistakenly detected
1 Stop the generation of error interrupts (INTSRE0).
In the following cases, the clock request signal (an internal signal) to the clock generator is also cleared:
• When the SWC0 bit is cleared to 0
• When the UART reception start bit is mistakenly detected
• When the transfer end interrupt generation timing is based on a parity error or framing error
SWC0 Setting the SNOOZE mode
0 Do not use the SNOOZE mode function.
1 Use the SNOOZE mode function.
When there is a hardware trigger signal in the STOP mode, the STOP mode is exited, and A/D conversion is
performed without operating the CPU (the SNOOZE mode).
• The SNOOZE mode function can only be specified when the high-speed on-chip oscillator clock is selected for
the CPU/peripheral hardware clock (fCLK). If any other clock is selected, specifying this mode is prohibited.
• Even when using SNOOZE mode, be sure to set the SWC0 bit to 0 in normal operation mode and change it to 1
just before shifting to STOP mode.
Also, be sure to change the SWC0 bit to 0 after returning from STOP mode to normal operation mode. If the
SWC0 bit is left set to 1, will not transmit/receive normally in spite of the SNOOZE or normal operation mode.
Caution Setting SSEC0, SWC0 = 1, 0 is prohibited.
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11.3.15 Noise filter enable reg i ster 0 (NFEN0)
The NFEN0 register is used to set whether the noise filter can be used for the input signal from the serial data input
pin to each channel.
Disable the noise filter of the pin us ed for CSI or simplified I 2C communication, by clearing the corres ponding bit of
this register to 0.
Enable the noise filter of the pin used for UART communication, by setting the corresponding bit of this register to
1.-
When the noise filter is enabled, CPU/ peripheral hardware clock (fCLK) is synchronized with 2-clock match
detection. When the noise filter is OFF, only synchronization is performed with the CPU/peripheral h ardware clock
(fMCK).
The NFEN0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the NFEN0 register to 00H.
Figure 11-20. Format of Noise Filter Enable Register 0 (NFEN0)
Address: F0070H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
NFEN0 0 0 0 SNFEN20 0 SNFEN10 0 SNFEN00
SNFEN20 Use of noise filter of RxD2 pin (RxD2/P14)
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN20 bit to 1 to use the RxD2 pin.
Clear the SNFEN20 bit to 0 to use other than the RxD2 pin.
SNFEN10 Use of noise filter of RxD1 pin (RxD1/P01)
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN10 bit to 1 to use the RxD1 pin.
Clear the SNFEN10 bit to 0 to use the other than RxD1 pin.
SNFEN00 Use of noise filter of RXD0 pin (RxD0/ANI17/SI00/ SDA00 TOOLRxD/P11)
0 Noise filter OFF
1 Noise filter ON
Set the SNFEN00 bit to 1 to use the RXD0 pin.
Clear the SNFEN00 bit to 0 to use the other than RxD0 pin.
Caution Be sure to clear undefined bits to “0”.
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11.3.16 Port input mode register 0, 1 (PIM0, PIM1)
This register sets the input buffer of ports 0 and 1 in 1-bit units.
The PIM0 and PIM1 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the PIM0 and PIM1 registers to 00H.
Figure 11-21. Format of Port Input Mod e Register 0, 1 (PIM0, PIM1)
20- or 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIM1 0 0 0 0 0 0 PIM11 PIM10 F0041H 00H R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PIM0 0 0 0 0 0 0 PIM01 0 F0040H 00H R/W
PIM1 PIM17 PIM16 PIM15 PIM14 PIM13 0 PIM11 PIM10 F0041H 00H R/W
PIMmn Pmn pin input buffer selection (m = 0, 1; n = 0, 1, 3 to 7)
0 Normal input buffer
1 TTL input buffer
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11.3.17 Port outp ut mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5)
These registers set the output mode of ports 1 and 4 in 1-bit units.
In addition, POM0, POM1, POM4, POM5 register is set with PUxx register, whether or not to use the on-chip pull-
up resistor (see 4.3 (3) Pull-up resistor optio n registers (PUxx)).
The POM1 and POM4 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears the POM1 and POM4 registers to 00H.
Figure 11-22. Format of Port Output Mode Registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5)
20- or 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM1 0 0 0 0 0 POM12 POM11 POM10 F0051H 00H R/W
POM4 0 0 0 0 0 0 POM41 0 F0054H 00H R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
POM0 0 0 0 0 0 0 0 POM00 F0050H 00H R/W
POM1 POM17 0 POM15 POM14 POM13 POM12 POM11 POM10 F0051H 00H R/W
POM5 0 0 0 0 0 0 0 POM50 F0055H 00H R/W
POMmn Pmn pin output buffer selection (0, 1, 4, 5 ; n = 0 to 5, 7)
0 Normal output mode
1 N-ch open-drain output (VDD tolerance) mode
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11.3.18 Port mode register s 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)
These registers set input/output of ports 0, 1, and 3 to 6 in 1-bit units.
When using the ports (such as P10/ANI16/PCLBUZ0/SCK00/SCL00) to be shared with the serial data output pin
or serial clock output pin for serial data output or serial clock output, set the port mode register (PMxx) and port
mode control register (PMCxx) bit corresponding to each port to 0. And set the port register (Pxx) bit
corresponding to each port to 1
Example: Using 20, 24-pin product P10/ANI16/PCLBUZ0/SCK00/SCL00 for serial clock output
Set the PMC10 bit of the port mode control register 1 to 0.
Set the PM10 bit of the port mode register 1 to 0.
Set the P10 bit of the port register 0 to 1.
When using the ports (such as P10/ANI16/PCLBUZ0/SCK00/SCL0 0) to be shared with the serial data input pin or
serial clock input pin for serial data input or serial clock input, set the port mode register (PMxx) bit corresponding
to each port to 1. Also set the port mode control register (PMCxx) bit corresponding to e ach port to 0. At this time,
the port register (Pxx) bit may be 0 or 1.
Example: Using 20-, 24-pin product P10/ANI16/PCLBUZ0/SCK00/SCL00 for serial data input or serial clock input
Set the PMC10 bit of the port mode control register 1 to 0.
Set the PM10 bit of port mode register 1 to 1.
Set the P10 bit of port register 1 to 0 or 1.
The PM0, PM1, and PM3 to PM6 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets the PM0, PM1, and PM3 to PM6 registers to FFH.
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Figure 11-23. Format of Po rt Mode Regi sters 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)
20- or 24-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM1 1 1 1 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM4 1 1 1 1 1 PM42 PM41 PM40 FFF24H FFH R/W
PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W
30-pin products
Symbol 7 6 5 4 3 2 1 0 Address After reset R/W
PM0 1 1 1 1 1 1 PM01 PM00 FFF20H FFH R/W
PM1 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 FFF21H FFH R/W
PM3 1 1 1 1 1 1 PM31 PM30 FFF23H FFH R/W
PM5 1 1 1 1 1 1 PM51 PM50 FFF25H FFH R/W
PM6 1 1 1 1 1 1 PM61 PM60 FFF26H FFH R/W
PMmn Selection of Pmn pin I/O mode (m = 0, 1, 3 to 6; n = 0 to 7)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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11.4 Operation Stop Mode
Each serial interface of serial array unit has the operation stop mode.
In this mode, serial communication cannot be executed, thus reducing the power consumption.
In addition, the serial interface function alternate pins can be used as port function pins in this mode.
11.4.1 Stopping the operation by units
The stopping of the operation by units is set by using peripheral enable register 0 (PER0).
The PER0 register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
To stop the operation of serial array unit 0, set bit 2 (SAU0EN) to 0. To stop the operation of serial array unit 1, set bit 3
(SAU1EN) to 0.
Figure 11-24. Peripheral Enable Register 0 (PER0) Setting When Stopping Operation by Units
Note Provided only in 30-pin products.
Cautions 1. If SAUmEN = 0, w riting to a control register of serial array unit m is ignored, and, even if the
register is read, only the default value is read
Note that this does not apply to the following regi sters.
• Noise filter enable register 0 (NFEN0)
• Port input mode register 0, 1 (PIM0, PIM1)
• Port output mode registers 0, 1, 4, 5 (POM0, POM1, POM4, POM5)
• Port mode registers 0, 1, 3 to 6 (PM0, PM1, PM3 to PM6)
• Port registers 0, 1, 3 to 6 (P0, P1, P3 to P6)
• Port mode control registers 0, 1, 4 (PMC0, PMC1, PMC4)
2. Be sure to clear the undefined bits to 0.
Remark : Setting disabled (fixed by hardware)
×: Bits not used with serial array units (depending on the settings of other peripheral functi ons)
0/1: Set to 0 or 1 depending on the usage of the user.
(a) Peripheral enable register 0 (PER0) … Set only the bit of SAU0 to be stopped to 0.
7 6 5 4 3 2 1 0
PER0 TMKAEN
×
0
ADCEN
×
IICA0EN
×
SAU1ENNote
0/1
SAU0EN
0/1
0
TAU0EN
×
Control of SAUm input clock
0: Stops supply of input clock
1: Su
pp
lies in
p
ut clock
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11.4.2 Stopping the operation by channels
The stopping of the operation by channels is set using each of the following registers.
Figure 11-25. Each Register Setting When Stopping Operation by Channels
(a) Serial channel stop register m (STm) … This register is a trigger register that is used to enable
stopping communication/count by each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STm
0
0
0
0
0
0
0
0
0
0
0
0
ST03
Note1
0/1
ST02
Note1
0/1
STm1
0/1
STm0
0/1
1: Clears the SEmn bit to 0 and stops the communication operation
* Because the STmn bit is a trigger bit, it is cleared immediately when SEmn = 0.
(b) Serial Channel Enable Status Register m (SEm) … This register indicates whether data
transmission/reception operation of each chan n el is enab led or stopped.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEm
0
0
0
0
0
0
0
0
0
0
0
0
SE03
Note1
0/1
SE02
Note1
0/1
SEm1
0/1
SEm0
0/1
0: Operation stops
* The SEm register is a read-only status register. Operation is stopped by using the STm register.
For a channel whose operation is disabled, the value of the CKOmn bit of the SOm register can be set by
software.
(c) Serial output enable register m (SOEm) … This register is a register that is used to enable or stop
output of the serial communication operation o f each ch an nel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
0/1
SOE01
Note2
0/1
SOEm0
0/1
0: Stops output by serial communication operation
* For channel n whose serial output is stopped, the SOmn bit value of the SOm register can be set by software.
(d) Serial output register m (SOm) …This register is a buffer reg ister for serial output of each channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1 CKOm0
0/1
0
0
0
0
SO03
Note1
0/1
SO02
Note1
0/1
SO01
Note2
0/1
SOm0
0/1
1: Serial clock output value is “1”
1: Serial data output value is “1”
* When using pins corresponding to each channel as port function pins, set the corresponding CKOmn, SOmn bits to “1”.
Notes 1. Provided in the serial array unit 0 of 30-pin products only.
2. 20-, 24-pin products only.
Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 0 to 3)
2. : Setting disabled (fixed by hardware), 0/1: Set to 0 or 1 depending on the usage of the user
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11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11, CSI20) Communication
This is a clocked communication functi on that uses three lines: serial clock (SCK) and serial data (SI and SO) lines.
[Data transmission/reception]
• Data length of 7 or 8 bits
• Phase control of transmit/receive data
• MSB/LSB first selectable
• Level setting of transmit/receive data
[Clock control]
• Master/slave selection
• Phase control of I/O clock
• Setting of transfer period by prescaler and internal counter of each channel
• Maximum transfer rate
During master communication (CSI00): Max. fMCK/2 Notes1, 2
During master communication (other than CSI00): Max. fMCK/4 Note2
During slave communication: Max. fMCK/6 Note2
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
[Error detection flag]
• Overrun error
Notes 1. In master communica tion (CSI0 0), maxi mum trans fer rate bec ome fMCK/2 when the following three conditions.
• 2.7 V ≤ VDD ≤ 5.5 V
• fMCK ≤ 24 MHz
• PIOR1 = 0
Other cases, maximum transfer rate become fMCK/4.
2. Use the clocks within a range satisfying the SCK cycle time (tKCY) characteristics (see CHAPTER 28
ELECTRICAL SPECIFICATIONS).
In addition, CSI00 (channel 0 of unit 0) supports the SNOOZE mode. When SCK00 pin input is detected while in the
STOP mode, the SNOOZE mode makes data reception that does not req uire the CPU possible.
The channels supporting 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) are channels 0, 1, 3 of SAU0 and cha nnel 0 of SAU1 .
20- or 24-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 UART0 IIC00Note
0 1 CSI01Note IIC01Note
30-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00
1 − UART0
−
2 − −
0
3 CSI11Note UART1Note IIC11Note
0 CSI20Note IIC20Note 1
1 − UART2 Note −
Note Provided in the R5F102 pr oducts only.
<R>
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3-wire serial I/O (CSI00, CSI01, CIS10, CIS20) performs the following seven types of communication operations.
• Master transmission (See 11.5.1.)
• Master reception (See 11.5.2.)
• Master transmission/reception (See 11.5.3.)
• Slave transmission (See 11.5.4.)
• Slave reception (See 11.5.5.)
• Slave transmission/reception (See 11.5.6.)
• SNOOZE mode function (for CSI00 only) (See 11.5.7.)
11.5.1 Master transmission
Master transmission is that the RL78/G12 outputs a transfer clock and transmits data to another device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SO00 SCK01, SO01 SCK11, SO11 SCK20, SO20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection
flag None
Transfer data
length 7 or 8 bits
Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00)
Min. fCLK/(2 × 215 × 128) [Hz] Note
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data output starts at the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCR0n register
• CKPmn = 0: Non-reverse (data output at the falling edge and data input at the rising edge of SCK)
• CKPmn = 1: Reverse (data output at the rising edge and data input at the falling edge of SCK)
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral function characteristics in
the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICAT IONS ).
Remarks 1. fCLK: S ystem clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-26. Example of Contents of Registers for Master Transmission of 3-Wire Serial I/O (CSI00, CSI01, CSI11,
CSI20)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm registe
r
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
0 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
m
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
(Operation clock (fMCK) division setting)
0
Tran smit data
(Transmit data setting)
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1 CKOm0
0/1
0
0
0
0
SO03
Note1
0/1
SO02
Note1
×
SO01
Note2
0/1
SOm0
0/1
Communication starts when these bits are 1 if the clock
phase is non-inversion (the CKPmn bit of the SCRmn = 0).
If the clock phase is inverted (CKPmn = 1), communication
starts when these bits are 0.
(e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
×
SOE01
Note2
0/1 SOEm0
0/1
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
× SS01
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products.
2. 20-, 24-pin products only.
Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user.
SIOp
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(2) Operation procedure
Figure 11-27. Initial Setting Procedure for Master Trans mission
Set an operation mode, etc.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Changing setting of the SOEm register
Setting port
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set a communication format.
Set the initial output level of the serial
clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Setting of SAU is completed.
Set transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1 : to enable operation).
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (fMCK)).
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Figure 11-28. Procedure for Stopping Master Transmission
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
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Figure 11-29. Procedure for Resuming Master Transmission
Remark If PER0 is rewritten while stopping the master transmission and the clock suppl y is stopped, wait
until the transmission target (slave) stops or transmission finishes, and then perf orm initialization
instead of restarting the transmission.
Starting setting for resumpt
Port manipulation
Changing setting of the SPSm register
Changing setting of the SMRmn register
Writing to the SSm register
Completing resumption
setting
Disable data output and clock output of
the target channel by setting a port
register and a port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (fMCK)).
Re-set the register to change serial
mode register mn (SMRmn) setting.
Set the initial output level of the serial
clock (CKOmn) and serial data (SOmn).
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Set the SSmn bit of the target channel to 1
(SEmn = 1 : to enable operation).
Setting is completed
Sets transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
(Essential)
(
Selective
)
(
Selective
)
(
Selective
)
(
Selective
)
(
Essential
)
(Essential)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(
Selective
)
Changing setting of the SCRmn register
Set the SOEmn bit to 1 and enable
output from the target channel.
(
Selective
)
Changing setting of the SOEm register
Set the SOEmn bit to 0 to stop output
from the target channel.
(
Selective
)
Changing setting of the SOEm register
Master ready?
(Essential)
Yes
No
Wait until stop the communication target
(slave) or communication operation
completed
Changing setting of the SDRmn register
Port manipulation
Changing setting of the SOm register
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(3) Processing flow (in single-transmission mode)
Figure 11-30. Timing Chart of Master Transmission (in Single-Transmission Mo de)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
STmn
SEmn
SDRmn
SCKp pin
SOp pin
Shift
register mn
INTCSIp
TSFmn
Data transmission (8-bit length)
Transmit data 3Transmit data 2Transmit data 1
Transmit data 1 Transmit data 2 Transmit data 3
Shift operation Shift operation Shift operation
Data transmission (8-bit length) Data transmission (8-bit length)
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-31. Flowchart of Master Transmission (in Single-Transmission Mode)
Star ting CS I comm uni cation
Write STmn bit to 1
Tr ansmission completed?
No
Yes
Clear SAUmEN bit of the
PER0 register to 0.
End of communication
Writing transmit data to
SIOp (=SDRmn[7:0])
When Transfer end interrupt is generated, it
moves to interrupt processing routine
Setting transmit data
For the initial setting, refer to Figure 11-27.
(Select Transfer end interrupt)
SAU default setting
Wait for transmit completes
Transfer end inte rrupt
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Disable interrupt (MASK)
Set data for transmission and the number of data. Clear communication end flag
(Storage area, Transmission data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Check completion of transmission by
verifying transmit end flag
Writing to SIOp makes SOp and
SCKp signals out
(communication starts)
Read t ransmit dat a from stor age area and write it
to SIOp. Update transmit data pointer.
Read transmit data, if any, from storage area and
write it to SIOp. Update transmit data pointer.
If not, set transmit end flag
Main routine Main routineInterrupt processing routine
Transmitting next data?
Writing tra ns mit da ta to
SIOp (=SDRmn[7:0])
No
Sets commu n ication
comple tio n flag
RETI
Yes
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(4) Processing flow (in continuous transmission mode)
Figure 11-32. Timing Chart of Master Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
INTCSIp
TSFmn
BFFmn
MDmn0
<1>
(Note)
STmn
SCKp pin
SOp pin
Shift
register mn
Transmit data 2 Transmit data 3
Transmit data 3Transmit data 2Transmit data 1
T ransmit data 1
Shift operation Shift operation Shift operation
Data transmission (8-bit length)Data transmission (8-bit length)Data transmission (8-bit length)
<6>
<2> <2> <2><3> <3> <3>
<4>
<5>
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-33. Flowchart of Master Transmission (in Continuous Transmission Mode)
Setting transmit data
Write STmn bit to 1
For the initial s etting, refer to Figure 11-27.
(Select buffer e mpty interrupt)
SAU default setting
Y
es
No
N
o
End of communication
Y
es
N
o
Communication
continued?
Y
es
Clear SAUmEN bit of the
PER 0 re gis ter to 0.
Number of
communication data > 0?
<2>
<3>
<4>
<5>
<6>
<1>
Set data for transmission and the number of data. Clear communication end flag
(Storage area, Transmission data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Clear MDmn0 bit to 0
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing transmit data to
SIOp (=SDRmn[7:0])
If transmit da ta i s left, read them from storage area then
write into SIOp, and update transmit data pointer and
number of transmit data.
If no more transmit data, clear MD mn bit if i t’s set. If n o t,
finish.
Subtract -1 from number of
transmit data
RETI
Tr ansmission completed?
Starting setting
When transfer end interrupt is generated, it moves to
inter r u pt processing rout i n e.
Buffer empty/transfer end interrupt
Write MDm n 0 bit to 1
Y
es
N
o
MDmn = 1?
Sets communication
completion int errupt flag
Wait for transmit completes
Clear inte rrupt request flag (XXIF), reset in terrupt mask (XXMK) and set
interrupt en able (E I).
Enables interrupt
Disable interru
p
t
(
MASK
)
Check completion of transmission by
verifying transmit end flag
Writing to SIOp makes SOp
and SCKp signals out
(communication starts)
Read transmit data from storag e area and write it
to SIOp. Upd a te transmit data pointer.
Main routine Main routineInterrupt processing routine
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-32. Timing Chart of Master
Transmission (in Continuous Transmission Mode).
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11.5.2 Master reception
Master reception is that the RL78/G12 outputs a transfer clock and receives data from other device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00 SCK01, SI01 SCK11, SI11 SCK20, SI20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00)
Min. fCLK/(2 × 215 × 128) [Hz]Note
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data input starts at the start of the operation of the serial clock.
• DAPmn = 1: Data input starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-inversion
• CKPmn = 1: Inverted
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. fCLK: S ystem clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-34. Example of Contents of Registers for Master Reception of 3-Wire Serial I/O (CSI00, CSI01, CSI11,
CSI20)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0 RXEmn
1 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
(Operation clock (fMCK) division setting)
0
Receive data
(Write FFH as dummy data.)
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1 CKOm0
0/1
0
0
0
0
SO03
Note 1
×
SO02
Note 1
×
SO01
Note 2
×
SOm0
×
Communication starts when these bits are 1 if the clock
phase is non-inversion (the CKPmn bit of the SCRmn = 0).
If the clock phase is inverted (CKPmn = 1), communication
starts when these bits are 0.
(e) Serial output enable register m (SOEm) … The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note 1
×
SOE02
Note 1
×
SOE01
Note 2
×
SOEm0
×
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note 1
0/1
SS02
Note 1
×
SSm1
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products.
2. 20-, 24-pin products only.
Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 11-35. Initial Setting Procedure for Master Reception
Figure 11-36. Procedure for Stopping Master Reception
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
Set an operation mode, etc.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Writing to the SSm register
End of initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set a communication format.
Set the initial output level of the serial
clock
(
CKOmn
)
.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Setting is completed.
Set dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation).
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (fMCK)).
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Figure 11-37. Procedure for Resuming Master Reception
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait
until the transmission target (slave) stops or transmission finishes, and then perform initialization
instead of restarting the transmission.
Starting setting for resumption
Port manipulation
Changing setting of the SPSm register
Changing setting of the SDR mn regis ter
Changing setting of the SMRmn register
Changing setting of the SOm register
Port manipulation
Writing to the SSm register
Completing resumption
settin
g
Disable clock output of the target
channel by setting a port register and a
port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (fMCK)).
Re-set the register to change serial
mode register mn (SMRmn) setting.
Set the initial output level of the serial
clock (CKOmn).
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation).
Setting is completed
Sets dummy data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
(
Essential
)
(
Selective
)
(
Selective
)
(
Selective
)
(
Selective
)
(
Essential
)
(Essential)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(
Selective
)
Changing setting of the SCR mn regis ter
If the OVF flag remain set, clear this
using serial flag clear trigger register mn
(SIRmn).
(
Selective
)
Clearing error flag
Completing master
p
re
p
arations?
(Essential)
Yes
No
Wait until stop the communication target
(slave) or communication operation
completed
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(3) Processing flow (in single-reception mode)
Figure 11-38. Timing Chart of Master Reception (in Single-Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
INTCSIp
TSFmn
STmn
Receive data 1
SCKp pin
SIp pin
Shift
register mn
Data reception (8-bit length)
Data reception (8-bit length) Data reception (8-bit length)
Reception & shift operation
Reception & shift operation
Reception & shift operation
Receive data 3Receive data 2
Receive data 1
Dummy data for reception Dummy data Dummy data
Receive data 2 Receive data 3
Write
Read Write
Read Read
Write
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-39. Flowchart of Master Reception (in Single-Reception Mode)
Starti ng CSI co mmunic ation
Writing dummy data to
SIOp (=SDRmn[7:0])
Write STmn bit to 1
All reception completed?
No
Yes
Clear SAUmEN bit of the
PER0 register to 0.
End of communication
Reading receive data to
SIO
p
(
=SDRmn
[
7:0
])
For the initial setting, refer to Figure 11-35.
(Select Transfer end interrupt)
SAU default setting
Wait for receive completes
When transfer end interrupt is generated, it moves
to interrupt processing routine
Writing to SIOp makes SCKp signals out
(communication starts)
RETI
Transfer end interrupt
generated?
Setting receive data
Setting storage area of the receive data, number of communication data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag ar e optionally set on the in ternal RA M by the softw are)
Read receive data then writes to storage area.
Update receive data pointer and number of
communication data.
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Disable interrupt (MASK)
Check the number of communication data
Main routine Main routine
Interrupt processing routine
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(4) Processing flow (in continuous reception mode)
Figure 11-40. Timing Chart of Master Reception (in Continuous Reception Mode) (Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
Dummy data Dummy data
Write
Write
Reception & shift operation
BFFmn
<1>
<2>
Dummy data
Write
MDmn0
Receive data 2
Receive data 1
Receive data 1
Data reception (8-bit length)
STmn
Shift
register mn
Read Read Read
Receive data 2 Receive data 3
Reception & shift operation Reception & shift operation
Data reception (8-bit length) Data reception (8-bit length)
<2> <2>
<8>
<5>
<3> <3> <4> <4><3> <6><7>
Receive data 3
Caution The MDmn0 bit can be rewritten even during operation.
How ever, rew rite it before recei ve of the last b it is started, so that it has been rewritten before the
transfer end interrupt of the last receive data.
Remarks 1. < 1> to <8> in the figure correspond to <1> to < 8> in Figure 11-41 Flowchart of Mast er Reception
(in Continuous Reception Mode).
2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-41. Flowchart of Master Reception (in Continuous Reception Mode)
Starting CSI communication
Reading receive data to SIOp
(=SDRmn[7:0])
Write STmn bit to 1
=
1
No
End of communication
Clear MDmn0 bit to 0
Communication continued?
Yes
Clear SAUmEN bit of the
PER0 register to 0
Writing dummy data to
SIOp (=SDRmn[7:0])
<2>
<3>
<5>
<6>
<7>
<4>
<8>
No
Yes
BFFmn = 1?
For the initial setting, refer to Figure 11-35.
(Select
buffer empty
interrupt)
SAU default setting
Setting receive data
Setting storage area of the receive data, number of communication data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Wait for receiv e co mp le tes
Buffer empty/ tra n s fe r end in terrupt
≥ 2
Number of communi cation
data?
Writing to SIOp makes SCKp
signals out (communication starts)
When interrupt is generated, it moves to
interrupt processing routine
Subtract -1 from number of
transmit data
<1>
Read receive data, if any, then write them to storage
area, and update receive data pointer (also subtract -1
from number of transmit data)
Writing dummy data to
SIOp (=SDRmn[7:0])
= 0
<2>
RETI
No
Number of c ommunicat ion
data = 0?
Yes
When number of communication data
becomes 0, receive completes
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Write MDmn0 bit to 1
Disable interrupt (MASK)
Main routine Main routine
Interrupt processing routine
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-40. Timing Chart of Master Recep tion
(in Continuous Reception Mode).
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11.5.3 Master transmission/reception
Master transmission/reception is that the RL78/G12 outputs a transfer clock and transmits/receives data to/from other
device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK11, SI11, SO11 SCK20, SI20, SO20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection flag Overrun error detection flag (OVFmn) only
Transfer data length 7 or 8 bits
Transfer rate Max. fCLK/2 [Hz] (CSI00), fCLK/4 [Hz] (other than CSI00)
Min. fCLK/(2 × 215 × 128) [Hz] Note
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data I/O starts at the start of the operation of the serial clock.
• DAPmn = 1: Data I/O starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-inversion
• CKPmn = 1: Inverted
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. fCLK: System clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-42. Example of Contents of Registers for Master Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI11, CSI20) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CK00 set by the SPS0 register
1: Prescaler output clock CK01 set by the SPS0 register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
1 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
(Operation clock (fMCK) division setting)
0
Transmit data setting/receive data register
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Om
0
0
0
0
1
1
CKOm1
0/1 CKOm0
0/1
0
0
0
0
SO03
Note1
0/1
SO02
Note1
×
SO01
Note2
0/1
SOm0
0/1
Communication starts when these bits are 1 if the clock
phase is non-inversion (the CKPmn bit of the SCRmn = 0).
If the clock phase is inverted (CKPmn = 1), communication
starts when these bits are 0.
(e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
×
SOE01
Note2
0/1
SOEm0
0/1
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
× SSm1
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products.
2. 20-, 24-pin products only.
Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission/reception mode
: Setting disabled (set to the initial va lue )
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 11-43. Initial Setting Procedure for Master Transmission/Reception
Set an operation mode, etc.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Changing setting of the SOEm register
Setting port
Writing to the SSm register
End of initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set a communication format.
Set the initial output level of the serial
clock (CKOmn) and serial data (SOmn).
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output and clock output of
the target channel by setting a port
register and a port mode register.
Setting is completed
Set transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and start
communication.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation).
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (fMCK)).
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Figure 11-44. Procedure for Stopping Master Transmission/Reception
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
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Figure 11-45. Procedure for Resuming Master Transmission/Reception
Starting setting for resumption
Changing set ting of the SPSm register
Changing setting of the SMRmn register
Changing setting of the SOm register
Port manipulation
Writing to the SSm registe r
Completing resumption setting
Disable data output and clock output of
the target channel by set ting a port
register and a port mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the transfer
clock by dividing the operation clock
(f
MCK
)).
Re-set the register to change s erial mode
register mn (SMRmn) setting.
Set the initial output level of the serial
clock (CKOmn) and serial data (SOmn).
Enable data output and clock output of
the target channel by set ting a port
register and a port mode register.
Set the SSmn bit of the target channel to 1
(SEmn = 1 : to enable operation).
(Essential)
(
Selective
)
(Selective)
(Selective)
(
Selective
)
(
Essential
)
(Essential)
Re-set the register to change serial
communication oper ation setting register
mn (SCRmn) setting.
(
Selective
)
Changing setting of the SCRmn register
Set the SOEmn bit to 1 and ena ble
output from the target channel.
(
Selective
)
Changi ng se ttin g of the SO Em re gist er
Set the SOEmn bit to 0 to stop output
from the target channel.
(
Selective
)
Changing setting of the SOEm register
Port manipulation
Changing setting of the SDRmn register
(Essential)
Yes
No Wait until stop the co mmunication target
(slave) or communication operation
completed
Com pleting slave
p
re
p
arations?
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
trigger register 0n (SIRmn).
Clearing error flag
(
Selective
)
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait
until the transmission target (slave) stops or transmission finishes, and then perform initialization
instead of restarting the transmission.
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(3) Processing flow (in single-transmissio n/reception mode)
Figure 11-46. Timing Chart of Master Transmission/Recep tion (in Single-Transmission/Reception Mode)
(Type 1: DAPmn =0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
Write Write
Write
SOp pin
STmn
Shift
register mn
Transmit data 1 Transmit data 2 Transmit data 3
Receive data 3
Receive data 2
Receive data 1
Receive data 2Receive data 1 Receive data 3
Transmit data 1 Transmit data 2 Transmit data 3
Reception & shift operation Reception & shift operation Reception & shift operation
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
Read Read Read
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-47. Flowchart of Master Transmission/Reception (in Single-Transmission/Reception Mode)
Starting CSI communication
Disable interrupt (MA SK)
T ransmission/reception
completed?
No
Yes
Clear SAUmEN bit of the
PER0 register to 0.
End of commu nication
Read receive data to SIOp
(=SDRmn[7:0])
Writing transmit data to
SIOp (=SDRmn[7:0])
When transfer end interrupt is generated, it
moves to interrupt proc essin g routine.
Wait for transmission/reception
completes
For the initial setting, refer to Figure 11-43.
(Select transfer end interrupt)
SAU default setting
Transfer end interrupt
Read receive data then writes to storage area, update receive
data pointer
RETI
If there are the next data, it continues
Write STmn bit to 1
Setting
transmission/reception data
Setting storage data and number of data for transmission/recepti on data
(Storage area, Transmission data pointer, Reception data pointer, Number of
communication data and Communication end flag are optionally set on the
internal RAM by the software)
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask ( XXMK) and set
interrupt enable (EI)
Writing to SIOp makes SOp
and SCKp signals out
(communication starts)
Read transmit data from sto rage area and write it
to SIOp. Update transmit data pointer.
Main routin e Main routine
Interrup t processing routine
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(4) Processing flow (in continuous transmission/reception mode)
Figure 11-48. Timing Chart of Master Transmission/Reception (in Continuous Transmission/Rec eption Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
SOp pin
BFFmn
<1>
Note 1
MDmn0
STmn
Transmit data 1 Transmit data 2 Transmit data 3Receive data 1 Receive data 2
Receive data 3
Receive data 1 Receive data 2 Receive data 3
Transmit data 1 Transmit data 2 Transmit data 3
Reception & shift operation Reception & shift operation Reception & shift operation
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
Write
Write Write
Read Read Read
<8>
<2> <2> <2><3> <2> <2><4> <4>
<5>
<6> <7>
Note 2 Note 2
Shift
register mn
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is over written.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 11-49 Flowchart of Master
Transmission/ Recep tion (in Continuous Transmission/Reception Mode).
2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-49. Flowchart of Master Transmission/Reception (in Continuous Transmission/Reception Mode)
Setting
transmission/reception data
Reading reception data to
SIOp (=SDRmn[7:0])
Write STmn bit to 1
For the initial setting, refer to Figure 11-43.
(Select buffer empty interrupt)
SAU default setting
N
o
N
o
End of communication
Y
es
Yes
No
Continuing Communication?
Y
es
Clear SAUmEN bit of the
PER0 register to 0
Number of
communication data?
Write MDmn0 bit to 1
BFFmn = 1?
<2>
<3>
<5>
<6>
<7>
<4>
<8>
<1>
Subtract -1 from number of
transmit data
Setting storage data and number of data for transmission/reception data
(Storage area, Transmission data pointer, Reception data, Number of
communication data and Communication end flag are optionally set on the
internal RAM by the software)
Clear MDmn0 bit to 0
Writing dummy data to
SIOp (=SDRmn[7:0])
Writing transmit data to
SIOp (=SDRmn[7:0])
Except for initial interrupt, read data received then write them
to storage area, and update receive data pointer
If transmit data is left (number of communication data is
equal or grater than 2), read them from storage area the n
write into SIOp, and update transmit data pointer.
If it’s waiting for the last data to receive (number of
communic at io n da t a is equa l to 1) , change interr up t timin g
to communication end
RETI
Number of co mmunicati on
data
= 0?
Starting setting
When transmission/reception interrupt is generated, i
t
moves to interrupt processing routine
Buffer empty/transfer end interrupt
Wait for transmissi on/reception
completes
≥ 2
= 0 = 1
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set interrupt
enable ( EI)
Disable interrupt (MASK)
Writing to SIOp makes SOp
and SCKp signals out
(communication starts)
Read transmit data from storage area and write it
to SIOp. Update transmit data pointer.
Main routine Main routine Interrupt processing routine
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-48 Timing Chart of Master
Transmission /Reception (in Continuous T ransmission/Reception Mode).
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11.5.4 Slave transmission
Slave transmission is that the RL78/G12 transmits data to another device in the state of a transfer clock being input
from another device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SO00 SCK01, SO01 SCK11, SO11 SCK20, SO20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection
flag Overrun error detection flag (OVFmn) only
Transfer data
length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data output starts at the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-inversion
• CKPmn = 1: Inverted
Data direction MSB or LSB first
Notes 1. Because the external serial clock input to the SCK00, SCK01, SCK11, and SCK20 pins is sampled internally
and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least
fSCK/2 as set by the SDRmn register.
2. Use this operation within a range that satisfies the conditions above and the AC charact eristics in the electrical
specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. f
MCK: Operation clock frequency of target channel
f
SCK: Serial clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-50. Example of Contents of Registers for Slave Transmissi on of 3-Wire Serial I/O (CSI00, CSI01, CSI11,
CSI20)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
0 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Baud rate setting
0
Transmit data setting
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
×
CKOm0
×
0
0
0
0
SO03
Note1
0/1
SO02
Note1
×
SO01
Note2
0/1
SOm0
0/1
(e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
×
SOE01
Note2
0/1
SOEm0
0/1
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
×
SSm1
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products.
2. 20-, 24-pin products only.
Remarks 1. mn = 00, 01, 03, 10 p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 11-51. Initial Setting Procedure for Slave Transmissio n
Set an operation mode, etc.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Changing setting of the SOEm register
Setting port
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set a communication format.
Set the initial output level of the serial
data (SOmn).
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port mode
register.
Initial setting is completed.
Set transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and wait for
a clock from the master.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1 : to enable operation).
Set bits 15 to 9 to 0000000B for baud rate
setting.
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Figure 11-52. Procedure for Stopping Slave Transmission
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
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Figure 11-53. Procedure for Resuming Slave Transmission
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait
until the transmission target (master) stops or transmission finishes, and then perform
initialization inst ead of restarting the transmission.
Starting setting for resumption
Port manipulation
Changing setting of the SPSm register
Changing setting of the SMR mn regis ter
Changing setting of the SOm reg ister
Port manipulation
Writing to the SSm register
Disable data output of the target channel
by setting a port register and a port
mode register.
Re-set the register to change the operation
clock setting.
Re-set the register to change serial
mode register mn (SMRmn) setting.
Set the initial output level of the serial
data
(
SOmn
)
.
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
(SEmn = 1 : to enable operation).
Sets transmit data to the SIOp register (bits
7 to 0 of the SDRmn register) and wait for a
clock from the master.
(
Selective
)
(
Selective
)
(
Selective
)
(
Essential
)
(
Essential
)
(Essential)
(Essential)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(
Selective
)
Changing setting of the SCRmn register
If the OVF flag remain set, clear this
using serial flag clear trigger register mn
(SIRmn).
(
Selective
)
Clearing error flag
Set the SOEmn bit to 1 and enable
output from the target channel.
(
Essential
)
Changing setting of the SOEm register
Completing resumption setting
Starting communication
Set the SOEmn bit to 0 to stop output
from the target channel.
(
Selective
)
Changing setting of the SOEm register
(Essential)
Yes
No Wait until stop the communication target
(master)
Completing master
p
re
p
arations?
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(3) Processing flow (in single-transmission mode)
Figure 11-54. Timing Chart of Slave Transmission (in Single-Tran smission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
INTCSIp
TSFmn
STmn
Shift
register mn
Transmit data 1 Transmit data 2 Transmit data 3
Transmit data 3
Transmit data 2
Transmit data 1
Shift operation Shift operation Shift operation
Data transmission (8-bit length)Data transmission (8-bit length)Data transmission (8-bit length)
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-55. Flowchart of Slave Transmission (in Single- Transmission Mode)
Starting CS I com m unication
Write STmn bit to 1
Continuing transmit?
Yes
No
Clear SAUmE N bit of the
PER0 register to 0.
End of communic a ti on
Transfer end interr upt?
No
Writing transmit data to
SIOp (=SDRmn[7:0])
Start communication when master
start providing the clock
When transmit end, interrupt is generated
Wait for tran smi t compl e tes
For the initial setting, refer to Figure 11-51.
(Select transfer end interrupt)
SAU default s ett ing
Setting transmit data
Set stora ge area and the nu mb er of data for tran s mit dat a
(Storage area, Transmission data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Transmitti ng ne xt da ta?
Yes
No
Read transmit data from storage area and write it to SIOp. Update
transmit data pointer.
Clear inter r upt request flag
Yes
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Disable interr upt (MASK)
Determine if it completes by counting number of communication data
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(4) Processing flow (in continuous transmission mode)
Figure 11-56. Timing Chart of Slave Transmission (in Continuous Transmission Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SOp pin
INTCSIp
TSFmn
BFFmn
MDmn0
STmn
Shift
register mn
T ransmit data 1
Transmit data 2 Transmit data 3
Transmit data 3Transmit data 2
Transmit data 1
Shift operation Shift operation Shift operation
Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length)
<1>
<6>
<2> <2> <2><3> <3> <3>
<4>
<5>
(Note)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started.
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-57. Flowchart of Slave Transmission (in Continuous Transmission Mode)
Setting transmit data
Write STmn b it to 1
For the initial setting, refer to Figure 11-51.
(Select buffer empty interrupt)
SAU default setting
Yes
No
No
End of communication
Yes
No
Com m unication continued
?
Yes
Clear SAUmEN bit of the
PER0 register to 0
Number of transmit
data > 1?
<2>
<3>
<4>
<5>
<6>
<1>
Set storage area and the number of data for transmit data
(Storage area, Transmission data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Clear MDmn 0 bit to 0
Writing transmit data to
SIOp (=SDRmn[7:0])
Writing transmit data to
SIOp (=SDRmn[7:0])
Reading transmit data
If transmit data is left, read them from storage area then write into
SIOp, and update transmit data pointer.
If not, change the interrupt to transmission complete
Subtract -1 from number of
transmit data
RETI
Num ber of comm unication
data = -1?
It is determined as follows depending on the number of communication data.
[No] +2 or higher: Unwritten data to SIOp
+1: Transmit data completion
0: During the last data received
[Yes] -1: All data received completion
Starting setting
Start communication when master start providing the
clock
When buffer empty/transfer end interrupt is generated,
it moves to interrupt processing routine
Wait for transmit completes
Buffer empty/transfer end interrupt
Disable interru
p
t
(
MASK
)
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Write MDmn0 bit to 1
Read transmit data from buffer and write it to SIOp. Update transmit
data pointer
Main routine Main routine
Interrupt processing routine
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-56 Timing Chart of Slave
Transmission (in Continuous Transmission Mode).
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11.5.5 Slave reception
Slave reception is that the RL78/G12 rec eives data from another device in the state of a transfer clock being inp ut from
another device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00 SCK01, SI01 SCK11, SI11 SCK20, SI20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection
flag Overrun error detection flag (OVFmn) only
Transfer data
length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2.
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data output starts at the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-inversion
• CKPmn = 1: Inverted
Data direction MSB or LSB first
Notes 1. Because the external serial cl ock input to the SCK00, SCK01, SCK11, an d SCK20 pins is sampled internall y
and used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at
least fSCK/2 as set by the SDRmn register.
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. f
MCK: Operation clock frequency of target channel
f
SCK: Serial clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-58. Example of Contents of Registers for Slave Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI11, CSI20)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0 RXEmn
1 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Baud rate setting
0
Receive data
(d) Serial output register m (SOm) …The Register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
×
CKOm0
×
0
0
0
0
SO03
Note1
×
SO02
Note1
×
SO01
Note2
×
SOm0
×
(e) Serial output enable register m (SOEm) …The Register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
×
SOE02
Note1
×
SOE01
Note2
×
SOEm0
×
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
× SSm1
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products.
2. 20-, 24-pin products only.
Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 11-59. Initial Setting Procedure for Slave Reception
Caution After setting the SAUmEN bit of peripheral enable register 0 (PER0) to 1, be sure to set serial
clock select register m (SPSm) after 4 or more fCLK clocks have elapsed.
Figure 11-60. Procedure for Stopping Slave Reception
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
Starting initial settings
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting port
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set baud rate setting (bits 15 to 9) to
0000000B.
Enable data input and clock input of the
target channel by setting a port register
and a port mode register.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation). Wait for
a clock from the master.
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Figure 11-61. Procedure for Resuming Slave Reception
Starting setting for resumption
Port manipulation
Changing setting of the SPSm register
Changin g settin g of the SMR mn regis ter
Port manipulation
Writing to the SSm register
Disable clock output of the target
channel by setting a port register and a
port mode register.
Re-set the register to change the
operation clock setting.
Re-set the register to change serial mode
register mn (SMRmn) setting.
Enable clock output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
(SEmn bit = 1: to enable operation). Wait
for a clock from the master.
(Essential)
(Selective)
(Selective)
(Essential)
(Essential)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(Selective) Changing setting of the SCRmn register
If the OVF flag remain set, clear this
using serial flag clear trigger register mn
(SIRmn).
(Selective) Clearing error flag
Completing res umption setting
(Essential)
Yes
No
Wait until stop the communication target
(master)
Completing master
p
re
p
arations?
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the
transmission target (master) stops or transmission finishes, and then perform initialization instead of
restarting the transmission.
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(3) Processing flow (in single-reception mode)
Figure 11-62. Timing Chart of Slave Reception (in Single-Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
STmn
Shift
register mn
Receive data 1 Receive data 2 Receive data 3
Receive data 1 Receive data 2Receive data 3
Reception & shift operation Reception & shift operation Reception & shift operation
Data reception (8-bit length) Data reception (8-bit length) Data reception (8-bit length)
Read Read Read
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-63. Flowchart of Slave Reception (in Sing le-Reception Mode)
Starting CS I comm unication
Write STm n bi t to 1
Reception completed?
No
Yes
Clear SAUmEN bit of the
PER0 re gister to 0
End of communic a ti o n
Reading receive data to
SIOp (=SDRmn[7:0])
For the initial setting, refer to Figure 12-59.
(Select transfer end interrupt only)
SAU default setting
Start communication when master start providing
the clock
When transmit end, interrupt i s generated
Wait for recieve completes
RETI
Transfer end interrupt
Read receive data then writes to storage area, and counts
up the number of receive data.
Upda t e rec e iv e dat a pointe r.
Check completion of number of receive data
Ready for reception
Clear storage area setting and the number of receive data
(Storage area, Reception data pointer, Number of communication data and
Communication end flag are optionally set on the internal RAM by the software)
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt m ask (XXMK) and set
interrupt enable (EI).
Disable interrupt (MASK)
Main routine Main routineInterrupt processing routine
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11.5.6 Slave transmission / recep tion
Slave transmission/reception is that the RL78/G12 transmits/receives data to/from another device in the state of a
transfer clock being input from another device.
3-Wire Serial I/O CSI00 CSI01 CSI11 CSI20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCK00, SI00, SO00 SCK01, SI01, SO01 SCK11, SI11, SO11 SCK20, SI20, SO20
INTCSI00 INTCSI01 INTCSI11 INTCSI20 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection
flag Overrun error detection flag (OVFmn) only
Transfer data
length 7 or 8 bits
Transfer rate Max. fMCK/6 [Hz]Notes 1, 2
Data phase Selectable by the DAPmn bit of the SCRmn register
• DAPmn = 0: Data output starts at the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Clock phase Selectable by the CKPmn bit of the SCRmn register
• CKPmn = 0: Non-inversion
• CKPmn = 1: Inverted
Data direction MSB or LSB first
Notes 1. Because the external serial cl ock input to the SCK00, SCK01, SCK11, SC K20 pins is sampled internal ly and
used, the fastest transfer rate is fMCK/6 [Hz]. Set up the SPSm register so that this external clock is at least
fSCK/2 as set by the SDRmn register.
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. f
MCK: Operation clock frequency of target channel
f
SCK: Serial clock frequency
2. mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-64. Example of Contents of Registers for Slave Transmission/Reception of 3-Wire Serial I/O
(CSI00, CSI01, CSI11, CSI20)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
1
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
0
MDmn1
0
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
1 DAPmn
0/1 CKPmn
0/1
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0/1
0
SLCmn1
0
SLCmn0
0
0
1
DLSmn1
1
DLSmn0
0/1
Selection of the data and clock
phase (For details about the
setting, see 11.3 Registers
Controlling Serial Array Unit.)
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
0: 7-bit data length
1: 8-bit data length
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOp)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn 0000000
Baud rate setting
0
Transmit data setting/receive data register
(d) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
×
CKOm0
×
0
0
0
0
SO03
Note1
0/1
SO02
Note1
×
SO01
Note2
0/1
SOm0
0/1
(e) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
×
SOE01
Note2
0/1
SOEm0
0/1
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
×
SSm1
0/1 SSm0
0/1
Notes 1. Provided in the serial array unit 0 of 30-pin products only.
2. 20-, 24-pin products only.
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Remarks 1. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOp
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(2) Operation procedure
Figure 11-65. Initial Setting Procedu re for Slave Transmission/Reception
Caution Be sure to set transmit data to the SlOp register before the clock from the master is started.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Changing setting of the SOEm register
Setting port
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set bits 15 to 9 to 0000000B for baud
rate setting.
Set the initial output level of the serial
data (SOmn).
Set the SOEmn bit to 1 and enable data
output of the target channel.
Enable data output of the target channel
by setting a port register and a port
mode register.
S
e
t
th
e
SS
mn
bit
o
f
th
e
t
arge
t
c
h
anne
l
t
o
1
(SEmn bit = 1: to enable operation).
I
n
iti
a
l
se
tti
ng
i
s comp
l
e
t
e
d
.
Set transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
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Figure 11-66. Procedure for Stopping Slave Transmission/Reception
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
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Figure 11-67. Procedure for Resuming Slave Transmission/Reception
Cautions 1. Be sure to set transmit data to the SlOp register before the clock from the master is started.
2. If PER0 is rewritten while stopping the master transmission and the clock supply is stopped,
wait until the transmission target (master) stops or transmission finishes, and then perform
initialization instead of restarting the transmission.
Starting setting for resumption
Port manipulation
Changing setting of the SPSm register
Changing setting of the SMR mn regis ter
Changing setting of the SOm reg ister
Port manipulation
Writing to the SSm register
Disable data output of the target channel
by setting a port register and a port
mode register.
Re-set the register to change the
operation clock setting.
Re-set the register to change serial mode
re
g
ister mn
(
SMRmn
)
settin
g
.
Set the initial output level of the serial
data (SOmn).
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SSmn bit of the target channel to 1
(SEmn = 1 : to enable operation).
(
Essential
)
(
Selective
)
(
Selective
)
(Selective)
(
Essential
)
(Essential)
Clearing error flag
(
Selective
)
If the OVF flag remain set, clear this using
serial flag clear trigger register mn
(SIRmn).
Starting communication
Completing resumption setting
Sets transmit data to the SIOp register
(bits 7 to 0 of the SDRmn register) and
wait for a clock from the master.
(Essential)
Changing setting of the SCRmn register
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
(
Selective
)
Changing setting of the SOEm register Set the SOEmn bit to 0 to stop output
from the target channel.
(Selective)
Changing setting of the SOEm register Set the SOEmn bit to 1 and enable
output from the target channel.
(Selective)
(Essential)
Yes
No Wait until stop the communication target
(master)
Completing master
p
re
p
arations?
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(3) Processing flow (in single-transmission/reception mode)
Figure 11-68. Timing Chart of Slave Transmission/Reception (in Single-Transmissio n/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
Write Write
Write
SOp pin
STmn
Shift
register mn
Transmit data 1 Transmit data 2 Transmit data 3
Receive data 3Receive data 2Receive data 1
Read
Read
Read
Receive data 1 Receive data 2 Receive data 3
Reception & shift operation Reception & shift operation Reception & shift operation
Transmit data 1
Transmit data 2 Transmit data 3
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
Remark mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-69. Flowchart of Slave Transmission/Reception (in Single- Transmission/ Reception Mode)
Starting CS I comm unication
Write STmn bit to 1
Transmission/reception
next data?
Yes
No
Clear SAUmEN bit of the
PER0 register to 0.
End of communication
Reading receive data to
SIOp (=SDRmn[7:0])
Transmission/reception
comp leted?
No
Yes
Writing transmit data to
SIOp (=SDRmn[7:0])
Start communication when master start providing the
clock
When tra nsfer end int errupt i s genera t ed, it moves to
interru pt pr o c ess ing rout i ne
W ait for transm ission/reception
completes
For the initial setting, refer to Figure 11-65
(Select Transfer end interrupt)
SAU default setting
Setting
transmission/reception data
Setting storag e a rea and numb er of dat a for transmission/reception data
(Storage area, Transmission/reception data pointer, Number of communication data
and Communi cation end flag are optio nally set on the interna l RAM by the software)
RETI
Transfer end interrupt
Enables interrupt
Clear i nterrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI).
Disable interrupt (MASK)
Read recei ve data an d write it to st orage ar ea. Update
receive data point er.
Update the number of communication data and confirm
if next transmission/reception data is available
Read transmit data from storage area and write it to SIOp.
Update transmit data pointer.
Main routine Main routineInterrupt processing routine
Caution Be sure to set tran smit data to the SlOp register before the clock from the master is started.
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(4) Processing flow (in continuous transmission/reception mode)
Figure 11-70. Timing Chart of Slave Transmission/Reception (in Continuous Transmission/Reception Mode)
(Type 1: DAPmn = 0, CKPmn = 0)
SSmn
SEmn
SDRmn
SCKp pin
SIp pin
INTCSIp
TSFmn
Write
Write
SOp pin
BFFmn
<8>
Write
MDmn0
STmn
Transmit data 1 Transmit data 2 Transmit data 3Receive data 1 Receive data 2
Receive data 3
Receive data 1 Receive data 2 Receive data 3
Transmit data 1 Transmit data 2 Transmit data 3
Data transmission/reception (8-bit length) Data transmission/reception (8-bit length)
Data transmission/reception (8-bit length)
<1>
<2> <2> <2><3> <3> <3><4> <4>
<5>
<6> <7>
Note 1 Note 2 Note 2
Read Read Read
Reception & shift operation Reception & shift operation Reception & shift operation
Shift
register mn
Notes 1. If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn
(SSRmn) is 1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is over written.
2. The transmit data can be read by reading the SDRmn register during this period. At this time, the
transfer operation is not affected.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been rewritten before
the transfer end interrupt of the last transmit data.
Remarks 1. <1> to <8> in the figure correspond to <1> to <8> in Figure 11-71 Flowchart of Slave
Transmission/ Recep tion (in Continuous Transmission/Reception Mode).
2. mn = 00, 01, 03, 10, p: CSI number (p = 00, 01, 11, 20)
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Figure 11-71. Flowchart of Slave Transmission/Reception (in Continuous Transmission /Reception Mode)
Setting
transmission/reception data
Read receive data to SIOp
(=SDRmn[7:0])
Write STmn bit t o 1
For the initial setting, refer to Figure 11-65
(Select buffer empty interrupt)
SAU default setting
No
Yes
No
= 1
End of communication
Yes
Yes
No
Communication
continued?
Yes
Clear SAUmEN bit of the
PER0 register to 0
Num ber of comm unication
data
?
Disable interrupt (MASK)
BFFmn = 1?
<3>
<5>
<6>
<7>
<4>
<8>
<1>
Subtract -1 from number of
transmit data
Setting storag e area a nd numb er of dat a for transmission/reception data
(Storage area, Trans mi ssi on/r e c e pt ion data pointer, Number of communication data
and Commu nicat ion e nd flag ar e optio nal ly set on the inte rna l RAM by th e soft war e)
Clear MDmn0 bit to 0
Writing transmit data to
SIOp (=SDRmn[7 :0 ] )
Other tha n the fir st inter rupt, read rece ption d ata then writes
to storage area, update receive data pointer
If transmit data is remai ned, read it from sto rage area and write i t to
SIOp. Update stor age pointer.
If transmit completion (number of communication data = 1), Change
the transmission completion interrupt
RETI
Num ber of comm unication
data
= 0?
Starting setting
Start communication when master start providing the
clock
When buf fer empt y/transfe r end is ge nerated , it mov es
interrupt pro ces si ng ro utin e
Wa it fo r tra n s m is s io n co mple tes
Buffer empty/transfer end interrupt
≥ 2
= 0
Enables interrupt
Write MDm n0 bit to 1
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
interrupt enable (EI)
Main routine Main routineInt errupt proces sing routine
Caution Be sure to set tran smit data to the SlOp register before the clock from the master is started.
Remark <1> to <8> in the figure correspond to <1> to <8> in Figure 11-70 Timing Chart of Slave
Transmission /Reception (in Continuous T ransmission/Reception Mode).
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11.5.7 SNOOZE mode function (only CSI00)
SNOOZE mode makes CSI operate recepti on by SCKp pin input detection while the STOP mode. Normally CSI stops
communication in the STOP mode. But, using the SNOOZE mode makes reception data unless the CPU oper ation. Only
CSI00 can be set to the SNOOZE mode.
When using the SNOOZE mode function, set the SWC0 bit of serial standby control register 0 (SSC0) to 1 before
switching to the STOP mode.
Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is
selected for fCLK.
2. The maximum tran sfer rate when using CSI00 in the SNOOZE mode is 1 Mbps.
(1) SNOOZE mode operation (once startup)
Figure 11-72. Timing Chart of SNOOZE Mode Operation (once startup) (Type 1: DAP00 = 0, CKP00 = 0)
SS00
SE00
SWC0
SSEC0 L
SDR00
SCK00 pin
SI00 pin
INTCSI00
TSF00
ST00
Clock request signal
(internal signal)
Shift
register 00
CPU operation status
STOP mode
SNOOZE modeNormal peration Normal operation
Receive data 2
Receive data 1
Receive data 2
Receive data 2
Reception & shift operation
Data reception (8-bit length)
Note 2
Receive data 1
Reception & shift operation
Data reception (8-bit length)
<7>
<2>
<5><6>
Read
Note 1
<3> <4> <11>
<9>
<1>
<10>
<8>
Notes 1. Only read received data while SWC0 = 1 and before the next edge of the SCK00 pin input is detected.
2. The transfer end interrupt (INTCSI00) is cleared either when SWC0 is cleared to 0 or when the next
edge of the SCK00 pin input is detected.
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the ST00 bit to 1 (clear th e SE00 bit, and stop the operation).
And after completion the receive operation, also clearing SWCm bit to 0 (SNOOZE mode release).
Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-73. Flowchart of SNOOZE Mode
Operation (once startup).
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Figure 11-73. Flowchart of SNOOZE Mode Operation (once startup)
SCK00 edge detected
(Entered the SNOOZE mode)
Supplying a clock to CSI00
(CSI00 is receive operation)
TSF00 = 0 for all channels?
No
Yes
Write ST00 bit to 1
SAU default setting
Setting SSCm register
(SWC0 = 1, SSEC0 = 0)
Entered th e STOP mode
Reading receive data to
SIOp (=S DR00[7:0])
Write ST00 bit to 1
Write SWC0 bit to 1
Write SSm0 bit to 1
Setting SNOOZE mode
f
CLK
supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
<8>
<9>
<10> Reset SNOOZE mode setting
<6>
The mode switches from SNOOZE to normal operation.
Become the communication wait status (SE00 = 1)
SN OO ZE m ode operation
Transfer interrupt (INTCSI00)
is generated
(CSI00 is receive completion)
End of SNOOZE mode
Write SS00 bit to 1
<11>
Become the operation STOP status (SE00 = 0)
SMR00, SCR00 : Communication setting
SDR00[15:9] : Setting 0000000B
Become the operation STOP sta tus (SE00 = 0)
It becomes communication ready state (SE00 = 1) under
normal opera tion
Clear interrupt request flag (XXIF), re set interrupt mask (XXMK)
and set interrupt enable (EI).
Enables interrupt
Normal operation SNOOZE mode
STOP mode Normal operation
Remark <1> to <11> in the figure correspond to < 1> to <11> in Figure 11-72. Timing Chart of SNOOZE Mode
Operation (once startup).
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(2) SNOOZE mode operation (continuous startup)
Figure 11-74. Timing Chart of SNOOZE Mode Operation (continuous startup) (Type 1: DAP00 = 0, CKP00 = 0)
SS00
SE00
SWC0
SSEC0 L
SDR00
SCK00 pin
SI00 pin
INTCSI00
TSF00
ST00
CPU operation status Normal peration
STOP mode
Normal peration
STOP mode
SNOOZ mode SNOOZ mode
Clock request signal
(internal signal)
Shift
register 00
Receive data 1 Receive data 2
Receive data 1 Receive data 2
Reception & shift operation Reception & shift operation
Data reception (8-bit length) Data reception (8-bit length)
Note 2
Read
Note 2
<2> <2>
<5><6> <7> <5><6>
<8>
<10>
<4>
<3>
<9>
<4>
<1> <3>
Notes 1. Only read received data while SWC0 = 1 and before the next edge of the SCK00 pin input is detected.
2. The transfer end interrupt (INTCSI00) is cleared either when SWC0 is cleared to 0 or when the next
edge of the SCK00 pin input is detected.
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, set the ST00 bit to 1 (clear th e SE00 bit, and stop the operation).
And after completion the receive operation, also clearing SWCm b i t to 0 (SNOOZE release).
Remark <1> to <10> in the figure correspond to <1> to <10> in Figure 11-75. Flowchart of SNOOZE Mode
Operation (continuous startup).
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Figure 11-75. Flowchart of SNOOZE Mode Operation (continuous startup)
SCK00 edge detected
(Entered the SNOOZE mode)
Supplying a clock to CSI00
(CSI00 is receive operation)
TSF00 = 0 for all channels?
No
Yes
Write ST00 bit to 1
Setting SSC0 register
(SWC0 = 1, SSEC0 = 0)
Entered the STOP mode
Reading receive data to
SIOp (=SDR00[7:0])
Write ST00 bit to 1
Clear SWC0 bit to 0
Write SS00 bit to 1
Setting SNOOZE mode
f
CLK
supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
<8>
<9>
<10> Reset SNOOZE mode set tin g
<6>
The mode switches from SNOOZE to normal operation.
Become the communication wait status (SE00 = 1)
SNOOZE mode operatopn
Transfer interrupt (INTCSI00)
is generated
(CSI00 is receive completion)
Become the operation STOP status (SE00 = 0)
SAU default setting SMRm0, SCRm0 : Communication setting
SDRm0[15:9] : Setting 0000000B
Enables interrupt Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt enable (EI).
Normal operation SNOOZE mode
STOP mode Normal operation
Remark <1> to <10> in the figure correspon d to <1> to < 10> in Figure 11-74. Timing Chart of SNOOZE Mode
Operation (continuous startup).
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11.5.8 Calculating transfer clo ck frequency
The transfer clock frequency for 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communication can be calculated by
the following expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (fMCK) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}Note [Hz]
Note The permissible maximum transfer clock frequency is f MCK/6.
Remark T he value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 11-2. Selection of Operation Clock For 3-Wire Serial I/O
SMRmn
Register SPS0 Register Operation Clock (fMCK) Note
CKSmn PRS
m13 PRS
m12 PRS
m11 PRS
m10 PRS
m03 PRS
m02 PRS
m01 PRS
m00 fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 kHz
X X X X 0 1 1 0 fCLK/26 312.5 kHz
X X X X 0 1 1 1 fCLK/27 156.2 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5kHz
X X X X 1 0 1 1 fCLK/211 9.77 kHz
X X X X 1 1 0 0 fCLK/212 4.88 kHz
X X X X 1 1 0 1 fCLK/213 2.44 kHz
X X X X 1 1 1 0 fCLK/214 1.22 kHz
0
X X X X 1 1 1 1 fCLK/215 610 Hz
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 kHz
0 1 1 0 X X X X fCLK/26 312.5 kHz
0 1 1 1 X X X X fCLK/27 156.2 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1
1 0 1 1 X X X X fCLK/211 9.77 kHz
1 1 0 0 X X X X fCLK/212 4.88 kHz
1 1 0 1 X X X X fCLK/213 2.44 kHz
1 1 1 0 X X X X fCLK/214 1.22 kHz
1 1 1 1 X X X X fCLK/215 610 Hz
Note When changi n g the clock selected for f CLK (by changing the system clock control registe r (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1. X: don’t care
2. m = unit number (m=0, 1), mn = 00, 01, 03, 10
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11.5.9 Procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20)
communication
The procedure for processing errors that occurred during 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20) communic ation
is described in Figure 11-77.
Figure 11-76. Processing Procedure in Case of Overrun Error
Software Manipulation Hardware Status Remark
Reads serial data register mn (SDRmn). The BFFmn bit of the SSRmn register is
set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register mn
(SSRmn). Error type is identified and the read
value is used to clear error flag.
Writes 1 to serial flag clear trigger
register mn (SIRmn). Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Remark mn = 00, 01, 03, 10
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11.6 Operation of UART (UART0 to UART2) Communication
This is a start-stop synchronization function using two lines: serial data transmission (TXD) and serial data reception
(RXD) lines. By using these two communication lines, each data frame, which consists of a start bit, data, parity bit, and
stop bit, is transferred asynchronously (using the internal baud rate) between the microcontroller and the other
communication party. Full-duplex UART communication can be performed by using a channel dedicated to transmission
(an even-numbered channel) and a channel dedic ated to reception (an odd-numbered channel).
[Data transmission/reception]
• Data length of 7, 8, or 9 bits (Only UART0 can be specified for the 9-bit data length)
• Select the MSB/LSB first
• Level setting of transmit/receive data and select of reverse (selecting whether to reverse the level)
• Parity bit appending and parity check functions
• Stop bit appending and stop bit check functions
[Interrupt function]
• Transfer end interrupt/buffer empty interrupt
• Error interrupt in case of framing error, parity error, or overrun error
[Error detection flag]
• Framing error, parity error, or overrun error
UART0 is compatible with SNOOZE mode. When RxD0 pin input is detected while in the STOP mode, the SNOOZE
mode makes data reception that does not require the CPU possible.
20- or 24-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00Note 0
1 CSI01Note
UART0
IIC01Note
30-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00Note
1 −
UART0
−
2 − −
0
3 CSI11Note
UART1
IIC11Note
0 CSI20Note IIC20Note 1
1 −
UART2 Note
−
Note Provided in the R5F102 products only.
Caution When using a serial array unit for UART, both the transmitter side (even-numbered channel) and the
receiver side (odd-numbered channel) can only be used for UART.
UART performs the following four types of communication operations.
• UART transmission (See 11.6.1.)
• UART reception (See 11.6.2.)
<R>
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11.6.1 UART transmission
UART transmission is an operation to transmit data from the RL78/G12 to another device asynchronously (start-stop
synchronization).
Of the two channels used for UART, the even-numbered channel is used for UART transmission.
UART UART0 UART1 UART2
Target channel Channel 0 of SAU0 Channel 2 of SAU0 Channel 0 of SAU1
Pins used TxD0 TxD1 TxD2
INTST0 INTST1 INTST2 Interrupt
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
Error detection
flag None
Transfer data
length 7, 8, or 9 bits (UART0 only)
Transfer rate Max. fMCK/6 [bps] (SDRmn[15:9] = 2 or greater, Min. fCLK/(2 × 215 × 128) [bps]Note
Data phase Non-inverted output (default: high level)
Inverted output (default: low level)
Parity bit The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
Stop bit The following selectable
• Appending 1 bit
• Appending 2 bits
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral function characteristics in
the electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICAT IONS ).
Remarks 1. f
MCK: Operation cloc k frequency of target channel
f
CLK: System clock frequency
2. m: Unit number (m = 0, 1) n: Channel number (n = 0, 2), mn = 00, 02, 10
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(1) Register setting
Figure 11-77. Example of Contents of Registers for UART Transmission (UART0 to UART2) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
0
0
0
1
0
0
MDmn2
0
MDmn1
1
MDmn0
0/1
Operation clock (fMCK) of channel n
0: Prescaler output clock CK00 set by the SPS0 register
1: Prescaler output clock CK01 set by the SPS0 register
Interrupt source of channel n
0: Transfer end interrupt
1: Buffer empty interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
0 DAPmn
0 CKPmn
0
0
EOCmn
0
PTCmn1
0/1
PTCmn0
0/1 DIRmn
0/1
0
SLCmn1
0/1
SLCmn0
0/1
0
1
DLSmn1
Note1
0/1
DLSmn0
0/1
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit
10B: Appending 2 bits
01B: Appending 0 parity
10B: Appending Even parity
1 1B: Appending Odd parity
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
(c) Serial data register mn (SDRmn) (lower 8 bits: TXDq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0 Note2
Transmit data setting
(d) Serial output level register m (SOLm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOLm
0
0
0
0
0
0
0
0
0
0
0
0
0
SOLm2
Note3
0/1
0 SOLm0
0/1
0: Non-inverted transmission
1: Inverted transmission
Notes 1. Provided only in SCR00 register (UART0) only. For SCR02 and SCR 10 registers, fixed as 1.
2. When performs 9-bit communication (by sett ing the DLS001 and DLS000 bits of the SMR00 register to
1), bits 0 to 8 of the SDR00 register are used as the transmission data specification area. 9-bit
communication is available only in UART0.
3. Provided only in 30-pin product serial array unit 0.
Remarks 1. q: UART number (q = 0 to 2), mn = 00, 02, 10
2. Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
0/1: Set to 0 or 1 depending on the usage of the user
TXDq
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Figure 11-77. Example of Contents of Registers for UART Transmission (UART0 to UART2) (2/2)
(e) Serial output register m (SOm) … Sets only the bits of the target channel.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1 CKOm1
×
CKOm0
×
0
0
0
0
SO03
Note 1
×
SO02
Note 1
0/1Note
2
SO01
×
SOm0
0/1Note
2
0: Serial data output value is “0”
1: Serial data output value is “1”
(f) Serial output enable register m (SOEm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note 1
×
SOE02
Note 1
0/1 SOE01
× SOEm0
0/1
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel to 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note 1
×
SS02
Note 1
0/1 SSm1
× SSm0
0/1
Notes 1. Provided only in 30-pin product serial array unit 0.
2. Before transmi ssion is started, be sure to set to 1 when the SOL00 bit of the target channel is set to 0, and
set to 0 when the SOL00 bit of the target channel is set to 1. The value varies depending on the
communication data during communication o peration.
Remarks 1. mn = 00, 02, 10
2. : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in a ny mode)
0/1: Set to 0 or 1 depe nding on the usage of the user
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(2) Operation procedure
Figure 11-78. Initial Setting Procedure for UART Transmission
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Changing setting of the SOEm register
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock
(
fMCK
))
.
Set the initial output level of the serial
data (SOm0).
Enable data output of the target channel
by setting a port register and a port mode
register.
Set the SOEm0 bit to 1 and enable data
output of the target channel.
Set the SSm0 bit of the target channel to 1
and set the SEmn bit to 1 (to enable
o
p
eration
)
.
Initial setting is completed.
Set transmit data to the TXDm register
(bits 7 to 0 of the SDRm0 register) and
start communication.
Changing setting of the SOLm register
Set an output data level.
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Figure 11-79. Procedure for Stopping UART Transmission
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Set the SOEmn bit t o 0 and stop the output o f
the target cha nnel.
Writing the STm register
Changing setting of the SOEm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
The levels of the serial clock (CKOmn) and
serial data (SOmn) on the target channel can
be changed if necessitated by an emergency.
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Changing set ting of the S Om registe r
Setting the PER0 register
(Essential)
(Selective)
(Essential)
(Selective)
(Selective)
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Figure 11-80. Procedure for Resuming UART Transmission
(Essential)
Yes
No Wait until stop the communication target
or communication operation completed
Completing master
preparations?
Port manipulation
Changing setting of the SPSm register
Changing setting of the SDRm n register
Changing setting of the SM Rm n
register
Changing setting of the SOm
register
Port manipulation
Writing to the SSm register
Completing resumption setting
Disable data output of the target channel
by setting a port register and a port mode
register.
Re-set the register to change the
operation clock setting.
Re-set the register to change the
transfer baud rate setting (setting the
transfer clock by dividing the operation
clock (f
MCK
)).
Re-set the register to change serial
mode register mn (SMRmn) setting.
Set the initial output level of the serial
data (SOmn).
Enable data output of the target channel
by setting a port registe r and a port mode
register.
Set the SSmn bit of the target channel to 1 and set
the SEmn bit to 1 (to enable operation).
Setting is completed
Sets transmit data to the TXDq re gister
(bits 7 to 0 of the SDRmn register) and
start communication.
(Selective)
(Selective)
(Selective)
Changing setting of the SOEm
register
Set the SOEmn bit to 1 and enable
output.
Changing setting of the SOEm
register
Clear the SOEmn bit to 0 and stop
output.
(Selective)
Changing setting of the SC Rmn
register
Re-set the register to change the serial
communication operation setting register
mn (SCRmn) setting.
Changing setting of the SO Lm
register
Re-set the register to change serial
output level register m (SOLm) setting.
Starting setting for resumption
(Essential)
(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until the
transmission target stops or transmission finishes, and then perform initialization instead of restarting the
transmission.
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(3) Processing flow (in single-transmission mode)
Figure 11-81. Timing Chart of UART Transmission (in Single-Transmission Mode)
SSmn
SEmn
SDRmn
TxDq pin
INTSTq
TSFmn
PSP
ST ST PSP ST PSP
STmn
Shift
register mn
Transmit data 1 Transmit data 2 Transmit data 3
Transmit data 3Transmit data 2Transmit data 1
Shift operation Shift operation Shift operation
Data transmission (8-bit length) Data transmission (8-bit length) Data transmission (8-bit length)
Remark q: UART number (q = 0 to 2), mn = 00, 02, 10
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Figure 11-82. Flowchart of UART Transmission (in Single-Transmission Mode)
S ta r tin g U A R T c omm u n ic a tion
Write STmn bit to 1
Tran smission comp leted?
No
Yes
Clear SAUmEN bit of the
PER0 register to 0.
End of communication
When Transfer end interrupt is generated, it
moves to interrupt processing routine
Setting transmit data
For the initial setting, refer to Figure 11-78.
(Select transfer end interrupt)
SAU default setting
Wait for transmit completes
Transfer end interrupt
Enables interrupt
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK) and set
inter ru pt ena bl e (EI ).
Disable interrupt (MASK)
Set data for transmission and the number of data. Clear communication end flag
(Storage area, transmission data pointer, number of communication data and
communication end flag are optionally set on the internal RAM by the software)
Check completion of transmission by
verifying transmit end flag
Read transmit data, if any, from storage area and
write it to SIOp. Update transmit data pointer.
If not, set transmit end flag
Main routine Main routineInterrupt processing routine
Transmitting next data?
Writing tra nsm it data to
SIOp (=SDRmn[7:0])
No
Sets commun ica tio n
comple tio n flag
RETI
Yes
When writing transmit data to (=SDRmn[7:0]),
start to the transmissions operation.
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(4) Processing flow (in continuous transmission mode)
Figure 11-83. Timing Chart of UART Transmission (in Continuous Transmission Mode)
SSmn
SEmn
SDRmn
TxDq pin
INTSTq
TSFmn
P
ST ST PST PSP
BFFmn
<1>
<2> <2><3>
Note <2>
<3> <5>
<6>
<3>
<4>
MDmn0
STmn
SP
SP
Transmit data 1 Transmit data 2 Transmit data 3
Shift
register mn
Transmit data 1 Transmit data 2 Transmit data 3
Shift operationShift operation
Shift operation
Data transmission (7-bit length) Data transmission (7-bit length) Data transmission (7-bit length)
Note If transmit data is written to the SDRmn register while the BFFmn bit of serial status register mn (SSRmn) is
1 (valid data is stored in serial data register mn (SDRmn)), the transmit data is overwritten.
Caution The MDmn0 bit of serial mode register mn (SMRmn) can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it will be rewritten before the
transfer end interrupt of the last transmit data.
Remark q: UART number (q = 0 to 2), mn = 00, 02, 10
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Figure 11-84. Flowchart of UART Transmission (in Continuous Transmission Mode)
Setting transmit data
Write STmn bit to 1
For the initial setting, refer to Figure 11-78.
(Select buffer empty i nterrupt)
SAU default setting
Y
es
No
N
o
End of communication
Y
es
N
o
Communication
continued?
Y
es
Clear SAUmEN bit of the
PER0 register to 0.
Number of
communication data > 0?
<2>
<3>
<4> <5>
<6>
<1>
Set data for t ransmission and the number of data. Clear communication end flag
(Storage area, T r ansmi ssion data pointe r, Number of communication dat a and
Communication end flag are optionally set on the internal RAM by the software)
Clear MDmn0 bit to 0
Writing transmit data to
TXDq (=SDRmn[7:0])
Writing transmit data to
TxDq (=SDRmn[7:0])
If transmit data is left, read them from storage area then
write into TxDq, and update transmit data pointer and
number of transmit da ta.
If no more transmit data, clear MDmn bit if it’s set. If not,
finish.
Subtract -1 from number of
transmit data
RETI
Transmission completed?
Starting UART
communication
When transfer end interrupt is generated, it moves to
interrupt processing routine.
Buffer emp ty/transfer end in te rr u p t
Write M D m n0 bit to 1
Y
es
N
o
MDmn = 1?
Sets communication
completion interrupt flag
Wait for transmit completes
Clear interrupt request flag (XXIF), reset interrupt ma sk (XXMK) and set
interrupt enable (EI).
Enables interrupt
Disable interrupt (MASK)
Check completion of transmission by
verifying transmit end flag
Communication starts by
writing to SDRmn [7:0]
Read transmit data fr om storage area and write it
to TXDq. Up date transmit data pointer.
Main routine Main routineInterrupt proces sing routine
<2>
Remark <1> to <6> in the figure correspond to <1> to <6> in Figure 11-83 Timing Chart of UART
Transmission (in Continuous Transmission Mode).
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11.6.2 UART reception
UART reception is an operation wherein the RL78/G12 asynchronously receives data from another device (start-stop
synchronization).
For UART reception, the odd-number channel of the two channels used for UART is used. The SMR register of both
the odd- and even-numbered channels must be set.
UART UART0 UART1 UART2
Target channel Channel 1 of SAU0 Channel 3 of SAU0 Channel 1 of SAU1
Pins used RxD0 RxD1 RxD2
INTSR0 INTSR1 INTSR2 Interrupt
Transfer end interrupt only (setting the buffer empty interrupt is prohibited)
Error interrupt INTSRE0 INTSRE1 INTSRE2
Error detection
flag
• Framing error detection flag (FEFmn)
• Parity error detection flag (PEFmn)
• Overrun error detection flag (OVFmn)
Transfer data
length 7, 8 or 9 bits (UART0 only)
Transfer rate Max. fMCK/6 [bps] (SDRmn [15:9] = 2 or more), Min. fCLK/(2 × 215 × 128) [bps] Note
Data phase Non-inverted output (default: high level)
Inverted output (default: low level)
Parity bit The following selectable
• No parity check
• No parity specified (0 parity)
• Appending even parity
• Appending odd parity
Stop Bit 1 bit check
Data direction MSB or LSB first
Note Use this operation within a range that satisfies the conditions above and the peripheral characteristics in the
electrical specifications (see CHAPTER 28 ELECTRICAL SPECIFICATIONS).
Remarks 1. f
MCK: Operation clock frequency of target channel
f
CLK: System clock frequenc y
2. m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11
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(1) Register setting
Figure 11-85. Example of Co n tents of Registers for UART Reception (UART0 to UART2) (1/2)
(a) Serial mode register mn (SMRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
1
0
SISmn0
0/1
1
0
0
MDmn2
0
MDmn1
1
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0
set by the SPSm register
1: Prescaler output clock CKm1
set by the SPSm register
0: Normal reception
1: Inverted reception
Operation mode of channel n
0: Transfer end interrupt
(b) Serial mode register mr (SMRmr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmr CKSmr
0/1 CCSmr
0
0
0
0
0
0
0
0
0
1
0
0
MDmr2
0
MDmr1
1
MDmr0
0/1
Same setting value as CKSmn bit Operation mode of channel r
0: Transfer end interrupt
1: Buffer empty interrupt
(c) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0 RXEmn
1 DAPmn
0 CKPmn
0
0 EOCmn
0/1
PTCmn1
0/1
PTCmn0
0/1 DIRmn
0/1
0
SLCmn1
0
SLCmn0
1
0
1
DLSmn1
Note 1
0/1
DLSmn0
0/1
Masking of error interrupt INTSREx
0: Masks INTSREx
1: Enables generation of INTSREx
Setting of parity bit
00B: No parity
01B: No parity judgment
10B: Appending Even parity
1 1B: Appending Odd parity
Selection of data transfer sequence
0: Inputs/outputs data with MSB first
1: Inputs/outputs data with LSB first.
Setting of data length
(d) Serial data register mn (SDRmn) (lower 8 bits: RXDq)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn
Baud rate setting
0 Note 2
Receive data register
RXDq
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Notes 1. Provided only in SCR0 1 register (UART0) only. For SCR03 and SCR11 registers, fixed as 1.
2. When UART0 performs 9-bit communication (by setting the DLS011 and DLS01 0 bits of the SCR01
register to 1), bits 0 to 8 of the SDR01 register are used as the transmission data specification area. 9-
bit communication is avail able only in UART0.
Caution For UART reception, be sure to set the SMRmr register of channel r that is to be paired with
channel n.
Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11
r: Channel number (r = n - 1) q: UART number (q = 0 to 2)
2. : Setting is fixed in the UART master tra nsmission mo de , : Setting disabled (set to the initial
value)
0/1: Set to 0 or 1 depending on the usage of the user
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Figure 11-85. Example of Co n tents of Registers for UART Reception (UART0 to UART2) (2/2)
(e) Serial output register m (SOm) … The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
×
CKOm0
×
0
0
0
0
SO03
Note
×
SO02
Note
×
SO01
×
SOm0
×
(f) Serial output enable register m (SOEm) …The register that not used in this mode.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note
×
SOE02
Note
×
SOE01
× SOEm0
×
(g) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note
0/1
SS02
Note
×
SSm1
0/1 SSm0
×
Note Provided only in 30-pin product serial array unit 0.
Caution For UART reception, be sure to set the SMRmr register of channel r that is to be paired with channel 0.
Remarks 1. m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11
r: Channel number (r = n - 1) q: UART number (q = 0 to 2)
2. : Setting disabled (set to the ini tial va lue )
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
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(2) Operation procedure
Figure 11-86. Initial Setting Procedure for UART Reception
Caution Afte r setting the RXEmn bit of SCRmn reg ister to 1, be su re to set SSmn to 0 after 4 or more fCLK
clocks have elapsed.
Figure 11-87. Procedure for Stopping UART Reception
Starting setting to stop
Stop setting is completed
Write 1 to the STmn bit of the target channel.
(SEmn = 0 : to operation stop status)
The master transmission is stopped.
Go to the next processing.
Writing the STm register
TSFmn = 0?
If there is any data being transferred, wait for
their completion.
(If there is an urgent must stop, do not wait)
Yes
No
To use the STOP mode, reset the serial array
unit by stopping the clock supply to it.
Setting the PER0 register
(Essential)
(Selective)
(Selective)
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn and SMRmr registers
Setting the SCRmn register
Setting the SDRmn register
Writing to the SSm register
Completing initial setting
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock (fMCK)).
Set the SSmn bit of the target channel to 1 and
set the SEmn bit to 1 (to enable operation).
Become wait for start bit detection.
Setting port Enable data input of the target channel
by setting a port register and a port
mode register.
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Figure 11-88. Procedure for Resuming UART Receptio n
Stop the target for communication or wait
Re-set the register to change the operation
clock setting.
Re-set the register to change the transfer
baud rate setting (setting the tran sfer clock
by dividing the operation clock (f
MCK
)).
Re-set the registers to change serial mode
registers mn, mr (SMRmn, SMRmr)
setting.
Set the SSmn bit of the target channel to 1 and set
the SEmn bit to 1 (to enable operation). Become
wait for start bit detection.
(Selective)
Re-set the register to change serial
communication operation setting register
mn (SCRmn) setting.
If the FEF, PEF, and OVF flags remain
set, clear them using serial flag clear
trigger register mn (SIRmn).
(Essential)
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
Enable data input of the target channel
by setting a port register and a port mode
register.
(Essential)
Starting setting for resumption
Changing setting of the SPS m register
Changing setting of the SDRmn
Writing to the SSm
register
Completing res umption setting
Changing setting of the SCRm n register
Clearing error flag
Changing setting of the SMRmn
and SMRmr registers
Setting port
(Essential)
Yes
No
Completing master
p
re
p
arations?
Caution Afte r setting the RXEmn bit of SCRmn reg ister to 1, be su re to set SSmn to 0 after 4 or more fCLK
clocks have elapsed.
Remark If PER0 is rewritten while stopping the master transmission and the clock supply is stopped, wait until
the transmission target (slave) stops or transmission finishes, and then perform initialization instead of
restarting the transmission.
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(3) Processing flow
Figure 11-89. UART Reception Timing Chart
SSmn
SEmn
SDRmn
RxDq pin
INTSRq
TSFmn
P
ST ST PST P
STmn
SP SP SP
Shift
register mn
Receive data 1
Receive data 1
Receive data 2
Receive data 2
Receive data 3
Receive data 3
Shift operation
Shift operation
Shift operation
Data reception (7-bit length) Data reception (7-bit length) Data reception (7-bit length)
Remark m: Unit number (m = 0, 1) n: Channel number (n = 1, 3), mn = 01, 03, 11
r: Channel number (r = n - 1) q: UART number (q = 0 to 2)
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Figure 11-90. Flowchart of UART Reception
Starting UAR T communi cat ion
Writing 1 to the STmn bit
End of UART comm uni cation
Reception completed?
No
Yes
No
Yes
Error processing
Clearing the SAUmEN bit of
the PER0 register to 0
Enables interrupt Clear interrupt request flag ( XXIF), reset interrupt mask
(XXMK) and set
Wait for receive completes S tarting reception if start bit is
detected
When receive c omplete, transfer end
inter rupt is generated,
Transfer end interrupt
Indi cating nor m al r eception?
R e ad in g r e ce i ve da ta to R X Dq
(=SDRmn[7:0])
Read receive data then writes to storage area.
Update receive data pointer and number of
communication data.
RETI
For th e initial setting, refe r to Figu re 1 1- 86.
(setting to mask for error interrupt)
SA U de fa ult sett in g
Set ting s torage area of the r ecei ve data, number of communication
da ta (storage area, reception data p ointer, number o f communication
data and c ommunication end f lag are optionally set on t he i nternal
R AM by the softw are)
Setting receive data
Note If the data length is 9 bits, read SDRmn[8:0] instead of the RxDq register.
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11.6.3 SNOOZE mode function (only UART0 reception)
SNOOZE mode makes UART operate reception by RxD0 pin input detection while the STOP mode. Normally UART
stops communication in the STOP mode. But, using the SNOOZE mode makes reception data unless the CPU operation.
Only UART0 can be set to the SNOOZE mode.
When using the SNOOZE mode function, set the SWC0 bit of serial standby control register 0 (SSC0) to 1 before
switching to the STOP mode.
Cautions 1. The SNOOZE mode can only be specified when the high-speed on-chip oscillator clock is selected
for fCLK.
2. The maximum transfer rate when using UART0 in the SNOOZE mode is 9600 bps.
(1) SNOOZE mode operation (Normal operation)
Figure 11-91. Timing Chart of SNOOZE Mode Operation (Normal Operation Mode)
SS01
SE01
SWC0
SSEC0 L
SDR01
INTSR0
INTSRE0 L
TSF01
<1>
<2>
<2>
<3>
<5><6> <8>
<7>
<9>
<4>
ST01
RxD0 pin PST P
SP SP
ST
<10>
<11>
<12>
CPU operation status Normal peration STOP mode SNOOZ mode Normal peration
Receive data 1 Receive data 2
Receive data 2Receive data 1
Shift operation Shift operation
Data reception (7-bit length)
Data reception (7-bit length)
Shift
register 01
Clock request signal
(internal signal)
Read
Note Onl y read rec eived data while SWC0 = 1.
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation).
And after completion the receive operation, also clearing SWC0 b i t to 0 (SNOOZE mode release).
Remark <1> to <12> in the figure correspond to <1> to <12> in Figure 11-93. Flowchart of SNOOZE Mode
Operation (Normal Operation/Abnormal Operation <1>).
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(2) SNOOZE mode operation (Abnormal Operation <1>)
Abnormal operation <1> is the operation performed when a communicati on error occurs while SSEC0 = 0.
Because SSEC0 = 0, an error interrupt (INTSRE0) is generated when a communication error occurs.
Figure 11-92. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <1>)
SS01
SE01
SWC0
SSEC0 L
SDR01
INTSR0
INTSRE0 L
TSF01
<1>
<2>
<3>
<5> <6> <8>
<7>
<4>
ST01
RxD0 pin PST P
SP SP
ST
<10>
<11>
<12>
CPU operation status Normal peration STOP mode SNOOZ mode Normal peration
Clock request signal
(internal signal)
Shift
register 01
Receive data 1
Receive data 1 Receive data 2
Receive data 2
Shift operationShift operation
Data reception (7-bit length) Data reception (7-bit length)
Caution Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation).
And after completion the receive operation, also clearing SWC0 b i t to 0 (SNOOZE mode release).
Remark <1> to <12> in the figure correspond to <1> to <12> in Figure 11-93. Flowchart of SNOOZE Mode
Operation (Normal Operation/Abnormal Operation <1>).
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Figure 11-93. Flowchart of SNOOZE Mode Operation (Normal Operation/Abnormal Operation <1>)
Setting start
Does TS
F
01 = 0 on all
channels?
No
Yes
Writing 1 to the ST01 bit
→ SE01 = 0
Setti ng SSC0 re gister
(SWC0 = 1, SSEC0 = 0)
Entered the STOP mode
Writing 1 to the SS01 bit
→ SE01 = 1
The operation of all channels is also stopped to switch to the
STOP mode.
SNOOZE mode setting
f
CLK
supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
Channel 1 is spec if i ed for UART reception.
(EOC01: set to enable error in t errupt )
<6>
Reading rec ei ve data to
RxD0 (=SDR01[7:0] )
<9>
<8>
<10>
<11>
The mode switc hes from SNOOZE to normal operat ion.
Communi c ati on wait status
SAU default setting
Clear int errup t reque st fl ag (XXIF), reset interrupt m ask (XXMK )
and set int errup t enable (EI = 1).
Enable interrupt
RxD0 edge detected
(Entered the SNOOZE mode)
Cloc k supply
(UART receive operation)
Transfer end interrupt (INTSR0) or
error interrupt (INTSRE0) generated?
Normal operation Normal operation
STOP mode SNOOZE mode
Writing 1 to the ST01 bit
Clear SWC0 bit to 0 Reset SNOOZE mode setting
To operation stop status (SE01 = 0)
INTSR0
Reading rec eive data to
RxD0 (=SDR01[7:0])
Writing 1 to the ST01 bit
Clear SWC0 bit to 0
INTSRE0
Error process ing Normal processing
To communicati o n wai t st atus (SE01 = 1)
Writing 1 to the SS01 bit <12> Writing 1 to the SS01 bit
Remark <1> to <11> in the figure correspond to < 1> to <11> in Figure 11-91. Timing Chart of SNOOZE Mode
Operation (Normal Operation Mode) and Figure 11-92. Timing Chart of SNOOZE Mode Operation
(Abnormal Operation <1>).
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(3) SNOOZE mode operation (Abnormal Operation <2>)
Abnormal operation <2> is the operation performed when a communicati on error occurs while SSEC0 = 1.
Because SSEC0 = 1, an error interrupt (INTSRE0) is not generated when a communication error occurs.
Figure 11-94. Timing Chart of SNOOZE Mode Operation (Abnormal Operation <2>)
L
<1>
<2>
<3>
<5><6> <7> <6>
<9>
<4>
Note2
PP
SP SPST
<7>,
<8>
<5>
ST
SS01
SE01
SWC0
SSEC0
SDR01
INTSR0
INTSRE0
TSF01
ST01
RxD0 pin
<10>
<11>
CPU operation status Normal peration STOP mode SNOOZ mode STOP mode SNOOZ mode
Normal peration
Receive data 1 Receive data 2
Receive data 2
Receive data 1
Shift operation
Shift operation
Shift operation
Data reception (7-bit length)
Data reception (7-bit length)
Shift
register 01
Clock request signal
(internal signal)
Read
Notes 1. Only read received data while SWC0 = 1 and before the next edge of the RxD0 pin input is detected.
2. After the reception of UART0 finishes normally in the SNOOZE mode, the normal reception operation
can be performed without changing the settings. However, FEF01 or PEF01 bit cannot be set even if
framing error or parity error is generated due to SSEC0 = 1. In addition, error interrupt (INTSRE0) is
not generated also.
Cautions 1. Before switching to the SNOOZE mode or after reception operation in the SNOOZE mode
finishes, be sure to set the ST00 bit to 1 (clear the SE00 bit to stop the operation).
And after completion the receive operation, also clearing SWC0 bit to 0 (SNOOZE mode
release).
2. When using the SNOOZE mode w hile SSEC0 is set to 1, no overrun errors occur. Therefore,
when using the SNOOZE mod e, read b its 7 to 0 (RxD0) of the SDR01 register before switching
to the STOP mode.
Remark <1> to <11> in the figure correspond to <1> to <11> in Figure 11-95. Flowchart of SNOOZE Mode
Operation (Abnormal Operation <2>).
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Figure 11-95. Flowchart of SNOOZE Mode Operation (Abnormal Operation <2>)
Setting start
Does TSF01 = 0 on all
channels? No
Yes
Writing 1 to the ST01 bit
→ SE01 = 0
Entered the STOP mode
The operation of all channels is also stopped to switch to the
STOP mode.
f
CLK
supplied to the SAU is stopped.
<1>
<2>
<3>
<4>
<5>
<7>
<6>
Reading receive data to
RxDq (=SDR01[7:0])
<9>
<8>
Writing 1 to the ST01 bit
The mode switches from SNOOZE to normal operation.
SIR01 = 0007H Clear the all error flags
If an error occurs, because the CPU switches to the
STOP status again, the error flag is not set.
Channel 1 is specified for UART reception.
(EOC01: set to enable error interrupt)
SAU default setting
Setting SSC0 register
(SWC0 = 1, SSEC0 = 1)
Writing 1 to the SS01 bit
→ SE01 = 1
SNOOZE mode setting (erro r inte rrupt generation stop)
Communication wait status
Clear interrupt request flag (XXIF), reset interrupt mask (XXMK)
and set interrupt disable (EI = 0).
Setting interrupt
Setting SSC0 register
(SWC0 = 0, SSEC0 = 0) Reset SNOOZE mode setting
Nomarl processing
To operation stop status (SE01 = 0)
RxD0 edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
RxD0 edge detected
(Entered the SNOOZE mode)
Clock supply
(UART receive operation)
Transfer end interrupt (INTSR0) generated
Normal operation Normal operati on
STOP
mode SNOOZE mode STOP mode SNOOZE mode
Reception erro r detected
<7>
<10>
<11>
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Caution When using the SNOOZE mode while SSEC0 is set to 1, no overrun errors occur. Therefore,
when using the SNOOZE mode, read bits 7 to 0 (RxD0) of the SDR01 register before switchin g to
the STOP mode.
Remark <1> to <11> in the figure correspond to < 1> to <11> in Figure 11-94. Timing Chart of SNOOZE Mode
Operation (Abnormal Operation <2>).
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11.6.4 Calculating baud rate
(1) Baud rate calculation expression
The baud rate for UART (UART0 to UART2) communication can be calculated by the following expressions.
(Baud rate) = {Operation clock (fMCK) frequency of target channel} ÷ (SDR0n[15:9] + 1) ÷ 2 [bps]
Caution Setting serial data register mn (SDRmn) SDRmn[15:9] = (0000000B to 0000001B) is pro h ibited.
Remarks 1. When UART is used, the value of SDRmn0[15:9] is the value of bits 15 to 9 of the SDR00
register (0000010B to 1111111B) and therefore is 2 to 127.
2. mn = 00 to 03, 10, 11
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial
mode register mn (SMRmn).
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Table 11-3. Selection of Operation Clock For UART
SMRmn
Register SPSm Register Operation Clock (fMCK) Note
CKSmn PRS
m13 PRS
m12 PRS
m11 PRS
m10 PRS
m03 PRS
m02 PRS
m01 PRS
m00 fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 kHz
X X X X 0 1 1 0 fCLK/26 312.5 kHz
X X X X 0 1 1 1 fCLK/27 156.2 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5 kHz
0
X X X X 1 0 1 1 fCLK/211 9.77 kHz
X X X X 1 1 0 0 fCLK/212 4.88 kHz
X X X X 1 1 0 1 fCLK/213 2.44 kHz
X X X X 1 1 1 0 fCLK/214 1.22 kHz
X X X X 1 1 1 1 fCLK/215 610 Hz
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 MHz
0 1 1 0 X X X X fCLK/26 312.5 kHz
0 1 1 1 X X X X fCLK/27 156.2 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1
1 0 1 1 X X X X fCLK/211 9.77 kHz
1 1 0 0 X X X X fCLK/212 4.88 kHz
1 1 0 1 X X X X fCLK/213 2.44 kHz
1 1 1 0 X X X X fCLK/214 1.22 kHz
1 1 1 1 X X X X fCLK/215 610 Hz
Note When changi n g the clock selected for f CLK (by changing the system clock control registe r (CKC) value), do so
after having stopped (serial channel stop register m (STm) = 000FH) the operation of the serial array unit
(SAU).
Remarks 1. X: do n’t care
2. mn = 00 to 03, 10, 11
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(2) Baud rate error during transmission
The baud rate error of UART (UART0 to UART2) communication during transmission can be calculated by the
following expression. Make sure that the baud rate at the transmission side is within the permissible baud rate
range at the reception side.
(Baud rate error) = (Calculated baud rate value) ÷ (Target baud rate) × 100 − 100 [%]
Here is an example of setting a UART baud rate at fCLK = 20 MHz.
fCLK = 20 MHz UART Baud Rate
(Target Baud Rate) Operation Clock (fMCK) SDRmn[15:9] Calculated Baud Rate Error from Target Baud Rate
300 bps fCLK/29 64 300.48 bps +0.16 %
600 bps fCLK/28 64 600.96 bps +0.16 %
1200 bps fCLK/27 64 1201.92 bps +0.16 %
2400 bps fCLK/26 64 2403.85 bps +0.16 %
4800 bps fCLK/25 64 4807.69 bps +0.16 %
9600 bps fCLK/24 64 9615.38 bps +0.16 %
19200 bps fCLK/23 64 19230.8 bps +0.16 %
31250 bps fCLK/23 39 31250.0 bps ±0.0 %
38400 bps fCLK/22 64 38461.5 bps +0.16 %
76800 bps fCLK/2 64 76923.1 bps +0.16 %
153600 bps fCLK 64 153846 bps +0.16 %
312500 bps fCLK 31 312500 bps ±0.0 %
Remark mn = 00, 02, 10
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(3) Permissible baud rate range for reception
The permissible baud rate range for rece ption during UART (UART 0 to UART2) communication can be calculated
by the following expression. Make sure that the baud rate at the transmission side is within the permissible baud
rate range at the reception side.
2 × k × Nfr
(Maximum receivable baud rate) = 2 × k × Nfr − k + 2 × Brate
2 × k × (Nfr − 1)
(Minimum receivable baud rate) = 2 × k × Nfr − k − 2 × Brate
Brate: Calculated baud rate value at the reception side (See 11.6.4 (1) Baud rate calcu latio n expression.)
k: SDRmn[15:9] + 1
Nfr: 1 data frame length [bits]
= (Start bit) + (Data length) + (Parity bit) + (Stop bit)
Remark mn = 01, 03, 11
Figure 11-96. Permissible Baud Rate Ran ge for Reception (1 Data Frame Length = 11 Bits)
FL 1 data frame (11 × FL)
(11 × FL) min.
(11 × FL) max.
Data frame length
of SAU Start
bit Bit 0 Bit 1 Bit 7 Parity
bit
Permissible minimum
data frame length
Permissible maximum
data frame length
Stop
bit
Start
bit Bit 0 Bit 1 Bit 7 Parity
bit
Latch
timing
Stop
bit
Start
bit Bit 0 Bit 1 Bit 7 Parity
bit Stop
bit
As shown in Figure 11-96 the timing of latching rec eive data is determin ed b y the div ision ratio s et by bi ts 15 to 9 of
serial data register mn (SDRmn) after the start bit is detected. If the last data (stop bit) is received before this latch
timing, the data can be correctly received.
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11.6.5 Procedure for processing errors that occurred during UART (UART0 to UART2) communication
The procedure for processing errors that occurred during UART (UART0 to UART2) communication is described in
Figures 11-97 and 11-98.
Figure 11-97. Processing Procedure in Case of Parity Error or Overrun Error
Software Manipulation Hardware Status Remark
Reads serial data register mn
(SDRmn).
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register mn
(SSRmn). Error type is identified and the read
value is used to clear error flag.
Writes 1 to serial flag clear trigger
register mn (SIRmn).
Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Figure 11-98. Processing Procedure in Case of Framing Error
Software Manipulation Hardware Status Remark
Reads serial data register mn
(SDRmn).
The BFFmn bit of the SSRmn register
is set to 0 and channel n is enabled to
receive data.
This is to prevent an overrun error if the
next reception is completed during error
processing.
Reads serial status register mn
(SSRmn). Error type is identified and the read
value is used to clear error flag.
Writes serial flag clear trigger register mn
(SIRmn). Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Sets the STmn bit of serial channel stop
register m (STm) to 1. The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operating.
Synchronization with other party of
communication Synchronization with the other party of
communication is re-established and
communication is resumed because it is
considered that a framing error has
occurred because the start bit has been
shifted.
Sets the SSmn bit of serial channel start
register m (SSm) to 1. The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Remark mn = 00 to 03, 10, 11
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11.7 Operation of Simplified I2C (IIC00, IIC01, IIC11, IIC20) Communication
This is a clocked communication function to communicate with two or more devices by using two lines: serial clock
(SCL) and serial data (SDA). This communication function is designed to execute single communication with devices such
as EEPROM, flash memory, and A/D convert er, and therefore, can be used only by the master.
Operate the control registers by software for setting the start and stop conditions while observing the specifications of
the I2C bus line.
[Data transmission/reception]
• Master transmission, master reception (only master function with a single master)
• ACK output functionNote and ACK detection function
• Data length of 8 bits
(When an address is transmitted, the address is specified by the higher 7 bits, and the least significant bit is
used for R/W control.)
• Generation of start condition and stop cond ition for software
[Interrupt function]
• Transfer end interrupt
[Error detection flag]
• ACK error
* [Functions not supported by simplified I2C]
• Slave transmission, slave reception
• Multi master function (Arbitration loss detection function)
• Wait detection function
Note When receiving the last data, ACK will not be output if 0 is written to the S OEmn (SOEm register) bit and serial
communication data output is stopped. See the processing flow in 11.7.3 (2) for details.
Remark m: Unit number (m = 0, 1) n: Channel number (n = 0, 1, 3), mn = 00, 01, 03, 10
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The channels supporting simp lified I 2C (IIC00, IIC01, IIC11, IIC20) are channel s 0, 1, 3 of SAU0 and channel 0 of SAU1.
20- or 24-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00Note 0
1 CSI01Note
UART0
IIC01Note
30-pin products
Unit Channel Used as CSI Used as UART Used as Simplified I2C
0 CSI00 IIC00Note
1 −
UART0
−
2 − −
0
3 CSI11Note
UART1Note
IIC11Note
0 CSI20Note IIC20Note 1
1 −
UART 2 Note
−
Note Provided in the R5F102 products only.
Simplified I2C (IIC00, IIC01, IIC11, IIC20) performs the following four types of communication operati ons.
• Address field transmission (See 11.7.1.)
• Data transmission (See 11.7.2.)
• Data reception (See 11.7.3.)
• Stop condition generation (See 11.7.4.)
<R>
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11.7.1 Address field transmissio n
Address field transmission is a transmissi on operation that first executes in I2C communic ation to identify the target for
transfer (slave). After a start condition is generated, an address (7 bits) and a transfer direction (1 bit) are transmitted in
one frame.
Simplified I2C IIC00 IIC01 IIC11 IIC20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCL00, SDA00Note SCL01, SDA01Note SCL11, SDA11Note SCL20, SDA20Note
INTIIC00 INTIIC01 INTIIC11 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection
flag ACK error detection flag (PEFmn)
Transfer data
length 8 bits (transmitted with specifying the higher 7 bits as address and the least significant bit as
R/W control)
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target
channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (fast mode)
• Max. 100 kHz (standard mode)
Data level Non-inversion output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (for ACK transmission/reception timing)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM11,
POM41 = 1 for 20- or 24-pin products, POM11, POM14, POM50 = 1 for 30-pin pr oducts) for the port output mode
registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and
IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD
tolerance) mode (POM10 = 1 for 20- or 24-pin products, POM10, POM15 = 1 for 30-pin products) also for the clock
input/output pins (SCL00, SCL20) (see 4.4.4 Connecting to extern al device with different po t ential (1.8 V, 2.5
V, 3 V) for details)
Remark mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-99. Example of Contents of Registers for Address Field Transmission of Simplified I2C
(IIC00, IIC01, IIC11, IIC20)
(a) Serial mode register 0n (SMR0n)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
Operation clock (fMCK) of channel n
0: Prescaler output clock CKm0 set by the SPSm register
1: Prescaler output clock CKm1 set by the SPSm register
Operation mode of channel n
0: Transfer end interrupt
(b) Serial communication operation setting register mn (SCRmn)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
0 DAPmn
0 CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
1
DLSmn1
1
DLSmn0
1
Setting of parity bit
00B: No parity
Setting of stop bit
01B: Appending 1 bit (ACK)
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
0 Transmit data setting (address + R/W)
(d) Serial output register m (SOm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1 CKOm0
0/1
0
0
0
0
SO03
Note1
0/1
SO02
Note1
×
SO01
Note2
0/1
SOm0
0/1
Start condition is generated by manipulating the SOmn bit.
(e) Serial output enable register m (SOEm)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOE03
Note1
0/1
SOE02
Note1
×
SOE01
Note2
0/1 SOEm0
0/1
SOEmn = 0 until the start condition is generated, and SOEmn =
1 after generation.
(f) Serial channel start register m (SSm) … Sets only the bits of the target channel is 1.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SS03
Note1
0/1
SS02
Note1
× SSm1
0/1 SSm0
0/1
SSmn = 0 until the start condition is generated, and SSmn = 1
after generation.
Notes 1. Provided only in 30-pin product serial array unit 0.
2. Only for 20, 24-pin product
Remarks 1. mn = 00, 01, 03, 10, r: IIC number (r = 00, 01, 11, 20)
2. : Setting is fixed in the CSI master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Operation procedure
Figure 11-100. Initial Setting Proced ure for simplified I2C Address Field Tran smission
Remark At the end of the initial setting, the simplified I2C (IIC00, IIC01, IIC11, IIC20) must be set so that
output is disabled and operations are stopped.
Starting initial setting
Setting the PER0 register
Setting the SPSm register
Setting the SMRmn register
Setting the SCRmn register
Setting the SDRmn register
Setting the SOm register
Setting port
Release the serial array unit from the
reset status and start clock supply.
Set the operation clock.
Set an operation mode, etc.
Set a communication format.
Set a transfer baud rate (setting the
transfer clock by dividing the operation
clock
(
fMCK
))
.
Set the initial output level (1) of the serial
data (SOmn) and serial clock (CKOmn).
Enable data output, clock output, and N-ch open-
drain output (VDD tolerance) mode of the target
channel by setting the port register, port mode
register, and port output mode register.
Completing initial setting
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(3) Processing flow
Figure 11-101. Timing Chart of Addr ess Field Transmission
D7 D6 D5 D4 D3 D2 D1 D0
R/W
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Address
Shift operation
Address field transmission
SOmn bit manipulation
CKOmn
bit manipulation
Remark mn = 00, 01, 03, 10, r: IIC number (r = 00, 01, 11, 20)
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Figure 11-102. Flowchart of simplified I2C Address Field Transmissio n
For the initial setting, refer to Figure 11-100
No
Yes
Yes Communication error
processing
To data transmission flow
and data reception flow
Writing 0 to the SOmn bit
Address field
transmission completed
Transfer end interrupt
g
enerated?
Writing address and R/W
data to SIOr (SDRmn[7:0])
Writing 1 to the SSmn bit
Responded ACK?
Writing 1 to the SOEmn bit
Writing 0 to the CKOmn bit
Default setting
Wait
No
Transmitting address field
Wait for address field transmission
complete.
(Clear the interrupt request flag)
Transmitting address field
To serial operation enable status
Enable serial output
Prepare to communicate the SCL signal is
fall
To secure a hold time of SCL signal
Start condition generate
Setting 0 ot the SOmn bit
ACK response from the slave
will be confirmed in PEFmn bit.
if ACK (PEFmn = 0), to the next
processing, if NACK (PEFmn =
1) to error processing.
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11.7.2 Data transmission
Data transmission is an operation to transmit data to the target for transfer (slave) after transmission of an address field.
After all data are transmitted to the slave, a stop condition is generated and the bus is released.
Simplified I2C IIC00 IIC01 IIC11 IIC20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCL00, SDA00 Note SCL01, SDA01 Note SCL11, SDA11Note SCL20, SDA20Note
INTIIC00 INTIIC01 INTIIC11 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection
flag ACK error detection flag (PEFmn)
Transfer data
length 8 bits
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target
channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (fast mode)
• Max. 100 kHz (standard mode)
Data level Non-inversion output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (for ACK reception timing)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM11,
POM41 = 1 for 20- or 24-pin products, POM11, POM14, POM50 = 1 for 30-pin pro ducts) for the port output mode
registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and
IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD
tolerance) mode (POM10 = 1 for 20- or 24-pin prod ucts, POM10, POM15 = 1 for 30-pin products) also for the clock
input/output pins (SCL00, SCL20) (see 4.4.4 Con necting to external device with different potential (1.8 V, 2.5
V, 3 V) for details)
Remark mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-103. Example of Contents of Registers for Data Transmission of Simplified I2C (IIC00, IIC01, IIC11, IIC20)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, exc ept the TXEmn and
RXEmn bits, during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
1 RXEmn
0 DAPmn
0 CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
1
DLSmn1
1
DLSmn0
1
(c) Serial data register mn (SDRmn) …During d ata transmission/reception, valid only lower 8-bits (SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
0 Transmit data setting
(d) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1
Note 2
CKOm0
0/1
Note 2
0
0
0
0
SOm3
Note 1
0/1
Note 3
SOm2
Note 1
×
SOm1
Note 2
0/1
Note 3
SOm0
0/1
Note 3
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOEm3
Note 1
0/1
SOEm2
Note 1
×
SOEm1
Note 2
1
SOEm0
1
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
Note 1
0/1
SSm2
Note 1
×
SSm1
Note 2
0/1
SSm0
0/1
Notes 1. Provided only in 30-pin produ c t serial array unit 0.
2. Only for 20, 24-pin product
3. The values may change during operation, depending on the communication data.
Remarks 1. mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20)
2. : Setting is fixed in the IIC master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Processing flow
Figure 11-104. Timing Chart of Data Transmission
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
D5 D4 D3 D2 D1 D0
ACK
Shift operation
“L”
“H”
“H”
Transmit data 1
Figure 11-105. Flowchart of Simplified I2C Data Transmission
Starting data transmission
Data transmission
completed
Transfer end interrupt
g
enerated? No
Yes
Writing data to SIOr
(SDRmn[7:0])
No
Yes
Stop condition generation
Data transfer completed?
Yes
No
Address field
transmission completed
Responded A CK?
Communication error
processing
Wait for transmission complete.
(Clear the interrupt request flag)
Transmission start by writing
A
CK acknowledgment from the slave
If ACK (PEF = 0), to the next process
if NACK (PEF = 1), to error handling
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11.7.3 Data reception
Data reception is an operation to receive data to the target for transfer (slave) after transmission of an address field.
After all data are received to the slave, a stop condition is generated and the bus is released.
Simplified I2C IIC00 IIC01 IIC11 IIC20
Target channel Channel 0 of SAU0 Channel 1 of SAU0 Channel 3 of SAU0 Channel 0 of SAU1
Pins used SCL00, SDA00Note SCL01, SDA01Note SCL11, SDA11Note SCL20, SDA20Note
INTIIC00 INTIIC01 INTIIC11 INTIIC20 Interrupt
Transfer end interrupt only (Setting the buffer empty interrupt is prohibited.)
Error detection
flag ACK error detection flag (OVFmn)
Transfer data
length 8 bits
Transfer rate Max. fMCK/4 [Hz] (SDRmn[15:9] = 1 or more) fMCK: Operation clock frequency of target
channel
However, the following condition must be satisfied in each mode of I2C.
• Max. 400 kHz (fast mode)
• Max. 100 kHz (standard mode)
Data level Non-inversion output (default: high level)
Parity bit No parity bit
Stop bit Appending 1 bit (ACK transmission)
Data direction MSB first
Note To perform communication via simplified I2C, set the N-ch open-drain output (VDD tolerance) mode (POM11,
POM41 = 1 for 20- or 24- pin products, POM11, POM14, POM50 = 1 for 30-pin products) for the port output mode
registers (POM1, POM4, POM5) (see 4.3 Registers Controlling Port Function for details). When IIC00 and
IIC20 can communicate with an external device with a different potential, set the N-ch open-drain output (VDD
tolerance) mode (POM10 = 1 for 20- or 24- pin products, POM10, POM15 = 1 for 30-pin products) also for the
clock input/output pins (SCL00, SCL20) (see 4.4.4 Connecting to external device with different potential (1.8
V, 2.5 V, 3 V) for details).
Remark mn = 00, 01, 03, 10
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(1) Register setting
Figure 11-106. Example of Contents of Registers for Data Reception of Simplified I2C (IIC00, IIC01, IIC11, IIC20)
(a) Serial mode register mn (SMRmn) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMRmn CKSmn
0/1 CCSmn
0
0
0
0
0
0
STSmn
0
0
SISmn0
0
1
0
0
MDmn2
1
MDmn1
0
MDmn0
0
(b) Serial communication operation setting register mn (SCRmn) … Do not manipulate the bits of this
register, exc ept the TXEmn and
RXEmn bits, during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCRmn TXEmn
0 RXEmn
1 DAPmn
0 CKPmn
0
0
EOCmn
0
PTCmn1
0
PTCmn0
0
DIRmn
0
0
SLCmn1
0
SLCmn0
1
0
1
DLSmn1
1
DLSmn0
1
(c) Serial data register mn (SDRmn) (lower 8 bits: SIOr)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDRmn Baud rate setting
0 Dummy transmit data setting (FFH)
(d) Serial output register m (SOm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOm
0
0
0
0
1
1
CKOm1
0/1
Note 2
CKOm0
0/1
Note 2
0
0
0
0
SOm3
Note 1
0/1
Note 3
SOm2
Note 1
×
SOm1
Note 2
0/1
Note 3
SOm0
0/1
Note 3
(e) Serial output enable register m (SOEm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SOEm
0
0
0
0
0
0
0
0
0
0
0
0
SOEm3
Note 1
0/1
SOEm2
Note 1
×
SOEm1
Note 2
0/1
SOEm0
0/1
(f) Serial channel start register m (SSm) … Do not manipulate this register during data
transmission/reception.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SSm
0
0
0
0
0
0
0
0
0
0
0
0
SSm3
Note 1
0/1
SSm2
Note 1
×
SSm1
0/1 SSm0
0/1
Notes 1. Provided only in 30-pin pro du c ts serial array unit 0.
2. Only for 20, 24-pin products.
3. The values ma y change during operation, de pending on the communication data.
Remarks 1. mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20)
2. : Setting is fixed in the IIC master transmission mode, : Setting disabled (set to the initial value)
×: Bit that cannot be used in this mode (set to the initial value when not used in any mode)
0/1: Set to 0 or 1 depending on the usage of the user
SIOr
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(2) Processing flow
Figure 11-107. Timing Chart of Data Reception
(a) When starting data reception
D7 D6 D5 D4 D3 D2 D1 D0
SSmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
ACK
STmn
TXEmn = 0 / RXEmn = 1
TXEmn,
RXEmn TXEmn = 1 / RXEmn = 0
Shift operation
“H”
Dummy data (FFH)
Receive data
(b) When receiving last data
D7 D6 D5 D4 D3 D2 D1 D0D2 D1 D0
STmn
SEmn
SOEmn
SDRmn
SCLr output
SDAr output
SDAr input
Shift
register mn
INTIICr
TSFmn
Receive data
Receive data
Output is enabled by serial
communication operation
Output is stopped by serial communication operation
NACKACK
TXEmn = 0 / RXEmn = 1
TXEmn,
RXEmn
Step condition
Reception of last byte
IIC operation stop
SOmn bit
manipulation
CKOmn bit
manipulation
SOmn bit
manipulation
Shift operation
Dummy data (FFH)
Shift operation
Dummy data (FFH)
Remark mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20)
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Figure 11-108. Flowchart of Data Reception
Caution ACK is not output w hen the last data is received (NACK). Communication is then completed by
setting “1” to the STmn bit of serial channel stop register m (STm) to stop operation and
generating a stop condition.
No
Yes
Stop condition
g
eneration
Yes
No
Address field transmission completed
Yes
No
Data r eception com pleted
Writing dummy data (FFH) to
SIOr (SDRmn[7:0])
Reading SIOr (SDRmn[7:0])
Writing 1 to the STmn bit
Writing 0 to the TXEmn bit, and 1 to the RXEmn bit
Writing 1 to the SSmn bit
Last byte received?
Writing 0 to the SOEmn bit
Data transfer completed?
Transfer end interrupt
generated?
Data r eception com pleted
Stop operation for rewriting SCRmn
register.
Set to receive only the operating
mode of the channel.
Operation restart
Disable output so that not the ACK
response to the last received data.
Starting reception operation
Wait for the completion of reception.
(Clear the interrupt request flag)
Reading receive data, perform
processing (stored in the RAM etc.).
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11.7.4 Stop condition generation
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is released.
(1) Processing flow
Figure 11-109. Timing Chart of Stop Condition Generation
Stop condition
STmn
SEmn
SOEmn
SCLr output
SDAr output
Operation
stop
SOmn
bit manipulation
CKOmn
bit manipulation
SOmn
bit manipulation
Note
Note During a receive operation, the SOEmn bit of serial output enable register m (SOEm) is cleared to 0 before
receiving the last data.
Figure 11-110. Flowchart of Stop Condition Generation
Starting generation of stop condition.
End of IIC communication
Writing 1 to the ST mn bit to clear
(the SEmn bit is cleared to 0)
Writing 0 to the SOEmn bit
Writing 1 to the SOmn bit
Writing 1 to the CKOmn bit
Writing 0 to the SOmn bit
Completion of data
transmission/data reception
Wait Secure a wait time so that the specifications of
I2C on the slave side are satisfied.
Operation is stopped
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11.7.5 Calculating transfer rate
The transfer rate for simplified I2C (IIC00, IIC01, IIC11, IIC20) communication can be calculated by the following
expressions.
(Transfer rate) = {Operation clock (fMCK) frequenc y of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2
Caution SDRmn [15:9] must n ot be set to 00000000B. Be su re to set a value of 00000001B or greater fo r
SDRmn[15:9]. The duty ratio of the SCL signal output by the simplified I2C is 50%. The I2C bus
specifications define that the low-level width of the SCL signal is longer than the highlevel
width. If 400 kbps (fast mode) or 1 Mbps (fast mode plus) is specified, therefore, the lowlevel
width of the SCL output signal becomes shorter than the value specified in the I2C bus
specifications. Make sure that the SDRmn[15:9] value satisfies the I2C bus specifications.
Remarks 1. The value of SDRmn[15:9] is the value of bits 15 to 9 of the SDRmn register (0000001B to
1111111B) and therefore is 1 to 127.
2. mn = 00, 01, 03, 10
The operation clock (fMCK) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
register mn (SMRmn).
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Table 11-4. Selection of Operation Clock for Simplified I2C
SMRmn
Register SPS0 Register Operation Clock (fMCK) Note
CKSmn PRS
m13 PRS
m12 PRS
m11 PRS
m10 PRS
m03 PRS
m02 PRS
m01 PRS
m00 fCLK = 20 MHz
X X X X 0 0 0 0 fCLK 20 MHz
X X X X 0 0 0 1 fCLK/2 10 MHz
X X X X 0 0 1 0 fCLK/22 5 MHz
X X X X 0 0 1 1 fCLK/23 2.5 MHz
X X X X 0 1 0 0 fCLK/24 1.25 MHz
X X X X 0 1 0 1 fCLK/25 625 KHz
X X X X 0 1 1 0 fCLK/26 312.5 kHz
X X X X 0 1 1 1 fCLK/27 156.2 kHz
X X X X 1 0 0 0 fCLK/28 78.1 kHz
X X X X 1 0 0 1 fCLK/29 39.1 kHz
X X X X 1 0 1 0 fCLK/210 19.5 kHz
X X X X 1 0 1 1 fCLK/211 9.77 kHz
X X X X 1 1 0 0 fCLK/212 4.87 kHz
X X X X 1 1 0 1 fCLK/213 2.44 kHz
X X X X 1 1 1 0 fCLK/214 1.22 kHz
0
X X X X 1 1 1 1 fCLK/215 610 Hz
0 0 0 0 X X X X fCLK 20 MHz
0 0 0 1 X X X X fCLK/2 10 MHz
0 0 1 0 X X X X fCLK/22 5 MHz
0 0 1 1 X X X X fCLK/23 2.5 MHz
0 1 0 0 X X X X fCLK/24 1.25 MHz
0 1 0 1 X X X X fCLK/25 625 KHz
0 1 1 0 X X X X fCLK/26 312.5 KHz
0 1 1 1 X X X X fCLK/27 156.2 kHz
1 0 0 0 X X X X fCLK/28 78.1 kHz
1 0 0 1 X X X X fCLK/29 39.1 kHz
1 0 1 0 X X X X fCLK/210 19.5 kHz
1 0 1 1 X X X X fCLK/211 9.76 kHz
1 1 0 0 X X X X fCLK/212 4.87 kHz
1 1 0 1 X X X X fCLK/213 2.44 kHz
1 1 1 0 X X X X fCLK/214 1.22 kHz
1
1 1 1 1 X X X X fCLK/215 610 Hz
Note When changing the clock selected for fCLK (by changing the system clock control register (CKC) value), do so
after having stop ped (serial channel stop register m(STm) = 000FH) the operation of the serial array un it (SAU).
Remarks 1. X: do n’t care
2. mn = 00, 01, 03, 10
Here is an example of setting an IIC transfer rate where fMCK = fCLK = 20 MHz.
fCLK = 20 MHz IIC Transfer Mode
(Desired T ransfer Rate) Operation Clock (fMCK) SDRmn[15:9] Calculated
Transfer Rate Error from Desired Transfer
Rate
100 kHz fCLK/2 49 100 kHz 0.0%
400 kHz fCLK 25 384.6 kHz 3.8%Note
Note The error cannot be set to about 0% becaus e the dut y ratio of the SCL sig nal is 50%.
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11.7.6 Procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC11, IIC20)
communication
The procedure for processing errors that occurred during simplified I2C (IIC00, IIC01, IIC11, IIC20) communication is
described in Figure 11-111.
Figure 11-111. Processing Procedure in Case of ACK error in Simplified I2C Mode
Software Manipulation Hardware Status Remark
Reads serial status register mn (SSRmn). Error type is identified and the read
value is used to clear error flag.
Writes serial flag clear trigger register mn
(SIRmn). Error flag is cleared. Error can be cleared only during
reading, by writing the value read from
the SSRmn register to the SIRmn
register without modification.
Sets the STmn bit of serial channel stop
register m (STm) to 1. The SEmn bit of serial channel enable
status register m (SEm) is set to 0 and
channel n stops operation.
Creates stop condition.
Creates start condition.
Slave is not ready for reception
because ACK is not returned.
Therefore, a stop condition is created,
the bus is released, and
communication is started again from
the start condition. Or, a restart
condition is generated and
transmission can be redone from
address transmission.
Sets the SSmn bit of serial channel start
register m (SSm) to 1. The SEmn bit of serial channel enable
status register m (SEm) is set to 1 and
channel n is enabled to operate.
Remark mn = 00, 01, 03, 10 r: IIC number (r = 00, 01, 11, 20)
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CHAPTER 12 SERIAL INTERFACE IICA
12.1 Functions of Serial Interface IICA
Serial interface IICA has the following three modes.
(1) Operation stop mode
This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
(2) I2C bus mode (multimaster supported)
This mode is used for 8-bit data transfers with several devices via two lines: a serial clock (SCLA0) line and a
serial data bus (SDAA0) line.
This mode complies with the I2C bus format and the master device can generated “start condition”, “address”,
“transfer direction specification”, “data”, and “stop condition ” data to the slave device, via the seria l data bus. The
slave device automatically detects these received status and data by hardware. This function can sim plify the part
of application program that controls the I2C bus.
Since the SCLA0 and SDAA0 pins are used for open drain outputs, serial interface IICA requires pull-up resistors
for the serial clock line and the serial data bus line.
(3) Wakeup mode
The STOP mode can be released by generating an interrupt request signal (INTIICA0) when an extension code
from the master device or a local address has been received while in STOP mode. This can be set by using the
WUP0 bit of IICA control register 01 (IICCT L01).
Figure 12-1 shows a block diagram of serial interface IICA.
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Figure 12-1. Block Diagram of Serial In terface IICA
IICE0
DQ
DFC0
SDAA0/
P61
SCLA0/
P60 INTIICA0
IICCTL00.STT0, SPT0
IICCTL01.PRS0
IICS0.MSTS0, EXC0, COI0
IICS0.MSTS0, EXC0, COI0
fCLK
fCLK/2
LREL0
WREL0
SPIE0
WTIM0
ACKE0
STT0 SPT0
MSTS0
ALD0 EXC0 COI0 TRC0
ACKD0
STD0SPD0
STCF0
IICBSY0 STCEN0IICRSV0
WUP0
CLD0 DAD0 DFC0 PRS0SMC0
PM60
Internal bus
IICA status register 0 (IICS0)
IICA control register 00
(IICCTL00)
Slave address
register 0 (SVA0)
Noise
eliminator
Match
signal
Match signal
IICA shift
register 0 (IICA0)
SO latch
Set
Clear
IICWL0
TRC0
DFC0
Data hold
time correction
circuit
Start
condition
generator
Stop
condition
generator
ACK
generator Wakeup
controller
N-ch open-
drain output
PM61
Noise
eliminator
Bus status
detector
ACK detector
Stop condition
detector
Serial clock
counter
Interrupt request
signal generator
Serial clock
controller
Serial clock
wait controller
Start condition
detector
Internal bus
IICA flag register 0
(IICF0)
IICA control register 01
(IICCTL01)
N-ch open-
drain output
Output
latch
(P60)
Output
latch
(P61)
WUP0
Sub-circuit
for standby
Filter
Filter
Output control
IICA shift register 0 (IICA0)
Counter
IICA low-level width
setting register 0 (IICWL0)
IICA high-level width
setting register 0 (IICWH0)
Selector
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Figure 12-2 shows a serial bus configur ation example.
Figure 12-2. Serial Bus Configuration Example Using I2C Bus
Master CPU1
Slave CPU1
Address 0
SDAA0
SCLA0
Serial data bus
Serial clock
+ VDD + VDD
SDAA0
SCLA0
SDAA0
SCLA0
SDAA0
SCLA0
SDAA0
SCLA0
Master CPU2
Slave CPU2
Address 1
Slave CPU3
Address 2
Slave IC
Address 3
Slave IC
Address N
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12.2 Configuration of Serial Interface IICA
Serial interface IICA includes the foll owing hardware.
Table 12-1. Configuration of Serial Interface IICA
Item Configuration
Registers IICA shift register 0 (IICA0)
Slave address register 0 (SVA0)
Control registers Peripheral enable register 0 (PER0)
IICA control register 00 (IICCTL00)
IICA status register 0 (IICS0)
IICA flag register 0 (IICF0)
IICA control register 01 (IICCTL01)
IICA low-level width setting register 0 (IICWL0)
IICA high-level width setting register 0 (IICWH0)
Port mode register 6 (PM6)
Port register 6 (P6)
(1) IICA shift register 0 (IICA0)
The IICA0 register is used to convert 8-bit serial data to 8-bit parallel data and vice versa in synchronization with
the serial clock. The IICA0 register can be used for both transmission and reception.
The actual transmit and receive operations can be controll e d by writing and readi ng oper ations to the IICA0 register.
Cancel the wait state and start data transfer by writing data to the IICA0 register during th e wait period.
The IICA0 register can be set by an 8-bit memor y manipula tion instruction.
Reset signal generation clears IICA0 to 00H.
Figure 12-3. Format of IIC A Shift Register 0 (IICA0)
Symbol
IICA0
Address: FFF50H After reset: 00H R/W
76543210
Cautions 1. Do not write data to the IICA0 register during data transfer.
2. Write or read the IICA0 register only during the wait period. Accessing the IICA0 register in a
communication state other than during the wait period is prohibited. When the device serves
as the master, however, the IICA0 register can be written only once after the communication
trigger bit (STT0) is set to 1.
3. When communicatio n is reserved, write data to the IICA0 register after the interrupt triggered
by a stop condition is detected.
(2) Slave address register 0 (SVA0)
This register stores seven bits of local addresses {A6, A5, A4 , A3, A2, A1, A0} when in slave mode.
The SVA0 register can be set by an 8-bit memory manipulation instruction.
However, rewriting to this register is prohibited while STD0 = 1 (while the start condition is detected).
Reset signal generation clears the SVA0 reg ister to 00H.
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Figure 12-4. Format of Slave Address Register 0 (SVA0)
Symbol
SVA0
Address: F0234H After reset: 00H R/W
76543210
0
Note
A0A1A2A3A4A5A6
Note Bit 0 is fixed to 0.
(3) SO latch
The SO latch is used to retain the SDAA0 pin’s output level.
(4) Wakeup controller
This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the
address value set to the slave address register 0 (SVA0) or when an extension code is received.
(5) Serial clock counter
This counter counts the serial clocks that are output or input during transmit/receive operations and is used to verify
that 8-bit data was transmitted or received.
(6) Interrupt request signal generator
This circuit controls the generation of interr upt request signals (INTIICA0).
An I2C interrupt request is generated by the following two triggers.
• Falling edge of eighth or ninth clock of the serial clock (set by the WTIM0 bit)
• Interrupt request generated when a stop condition is detected (set by the SPIE0 bit)
Remark WTIM0 bit: Bit 3 of IICA control register 00 (IICCTL00)
SPIE0 bit: Bit 4 of IICA control register 00 (IICCTL00)
(7) Serial clock controller
In master mode, this circuit generates the clock output via the SCLA0 pin from a sampling clock.
(8) Serial clock wait controller
This circuit controls the wait timing.
(9) ACK generator, stop condition detector, start condition detector, and ACK detector
These circuits generate and detect each status.
(10) Data hold time correction circuit
This circuit generates the hold time for data corresponding t o the falling edge of the serial clock.
(11) Start condition generator
This circuit generates a start condition when the STT0 bit is set to 1.
However, in the communication reservation disabled status (IICRSV0 bit = 1), when the bus is not released
(IICBSY0 bit = 1), start condition requests are ignored and the STCF bit is set to 1.
(12) Stop condition generator
This circuit generates a stop condition when the SPT0 bit is set to 1.
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(13) Bus status detector
This circuit detects whether or not the bus is released by detecting start conditions and s t op conditions.
However, as the bus status cannot be detected immediately following operation, the initial status is set by the
STCEN bit.
Remark STT0 bit: Bit 1 of IICA control register 00 (IICCTL00)
SPT0 bit: Bit 0 of IICA control register 00 (IICCTL00)
IICRSV0 bit: Bit 0 of IICA flag register 0 (IICF0)
IICBSY0 bit: Bit 6 of IICA flag register 0 (IICF0)
STCF0 bit: Bit 7 of IICA flag register 0 (IICF0)
STCEN0 bit: Bit 1 of IICA flag register 0 (IICF0)
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12.3 Registers Controlling Serial Interface IICA
Serial interface IICA is controlled b y the following eight registers.
• Peripheral enable register 0 (PER0)
• IICA control register 00 (IICCTL00)
• IICA flag register 0 (IICF0)
• IICA status register 0 (IICS0)
• IICA control register 01 (IICCTL01)
• IICA low-level width setting register 0 (IICWL0)
• IICA high-level width setting register 0 (IICWH0)
• Port mode register 6 (PM6)
• Port register 6 (P6)
12.3.1 Peripheral enable register 0 (PER0)
This register is used to enable or disable supplying the clock to the peripheral hardware. Clock supply to a
hardware macro that is not used is stopped in order to reduce the power consumption and noise.
When serial interface IICA is used, be sure to set bit 4 (IICA0EN) of this register to 1.
The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 12-5. Format of Peripheral Enable Register 0 (PER0)
Address: F00F0H After reset: 00H R/W
Symbol <7> 6 <5> <4> <3> <2> 1 <0>
PER0 TMKAEN 0 ADCEN IICA0EN SAU1EN SAU0EN 0 TAU0EN
IICA0EN Control of serial interface IICA input clock supply
0 Stops input clock supply.
• SFR used by serial interface IICA cannot be written.
• Serial interface IICA is in the reset status.
1 Enables input clock supply.
• SFR used by serial interface IICA can be read/writt en.
Cautions 1. When setting serial interface IICA, be sure to set the IICA0EN bit to 1 first. If IICA0EN = 0,
writing to a control register of serial interface IICA is ignored, and, even if the register is read,
only the default value is read (except for port mode register 6 (PM6) and port register 6 (P6)).
2. Be sure to clear the undefined bits to 0.
12.3.2 IICA c ontrol register 00 (IICCTL00)
This register is used to enable/stop I2C operations, set wait timing, and set other I2C operations.
The IICCTL00 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, set the SPIE0,
WTIM0, and ACKE0 bits while IICE0 = 0 or during the wait period. These bits can be set at the same time when
the IICE0 bit is set from “0” to “1”.
Reset signal generation clears this register to 00H.
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Figure 12-6. Format of IIC A Control Regi ster 00 (IICCTL00) (1/4)
Address: F0230H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICCTL00 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0
IICE0 I2C operation enable
0 Stop operation. Reset the IICA status register 0 (IICS0)Note 1. Stop internal operation.
1 Enable operation.
Be sure to set this bit (1) while the SCLA0 and SDAA0 lines are at high level.
Condition for clearing (IICE0 = 0) Condition for setting (IICE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
LREL0Notes 2,
3 Exit from communications
0 Normal operation
1 This exits from the current communications and sets standby mode. This setting is automatically cleared
to 0 after being executed.
Its uses include cases in which a locally irrelevant extension code has been received.
The SCLA0 and SDAA0 lines are set to high impedance.
The following flags of IICA control register 00 (IICCTL00) and the IICA status register 0 (IICS0) are
cleared to 0.
• STT0 • SPT0 • MSTS0 • EXC0 • COI0 • TRC0 • ACKD0 • STD0
The standby mode following exit from communications remains in effect until the following communications entry
conditions are met.
• After a stop condition is detected, restart is in master mode.
• An address match or extension code reception occurs after the start condition.
Condition for clearing (LREL0 = 0) Condition for setting (LREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
WREL0Notes 2,
3 Wait cancellation
0 Do not cancel wait
1 Cancel wait. This setting is automatically cleared after wait is canceled.
When the WREL0 bit is set (wait canceled) during the wait period at the ninth clock pulse in the transmission status
(TRC0 = 1), the SDAA0 line goes into the high impedance state (TRC0 = 0).
Condition for clearing (WREL0 = 0) Condition for setting (WREL0 = 1)
• Automatically cleared after execution
• Reset
• Set by instruction
Notes 1. The IICA status register 0 (IICS0), the ST CF and IICBSY bits of the IICA flag register 0 (IICF0), and
the CLD0 and DAD0 bits of IICA control register 01 (IICCTL01) are reset.
2. T he signal of this bit is invalid while IICE0 is 0.
3. When the LREL0 and WREL0 bits are read, 0 is always read.
Caution If the operation of I2C is enabled (IICE0 = 1) when the SCLA0 line is high level, the SDAA0
line is low level, and the digital filter is turned on (DFC0 bit of IICCTL01 register = 1), a start
condition will be inadvertently detected immediately. In this case, set (1) the LREL0 bit by
using a 1-bit memory manipulation instruction immediately after enabling operation of I2C
(IICE0 = 1).
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Figure 12-6. Format of IIC A Control Regi ster 00 (IICCTL00) (2/4)
SPIE0Note 1 Enable/disable generation of interrupt req uest when stop condition is detected
0 Disable
1 Enable
If the WUP0 bit of IICA control register 01 (IICCTL01) is 1, no stop condition interrupt will be generated even if SPIE0
= 1.
Condition for clearing (SPIE0 = 0) Condition for setting (SPIE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
WTIM0Note 1 Control of wait and interrupt request generation
0 Interrupt request is generated at the eighth clock’s falling edge.
Master mode: After output of eight clocks, clock output is set to low level and wait is set.
Slave mode: After input of eight clocks, the clock is set to low level and wait is set for master device.
1 Interrupt request is generated at the ninth clock’s falling edge.
Master mode: After output of nine clocks, clock output is set to low level and wait is set.
Slave mode: After input of nine clocks, the clock is set to low level and wait is set for master device.
An interrupt is generated at the falling edge of the ninth clock during address transfer independently of the setting of
this bit. The setting of this bit is valid when the address transfer is completed. When in master mode, a wait is
inserted at the falling edge of the ninth clock during address transfers. For a slave device that has received a local
address, a wait is inserted at the falling edge of the ninth clock after an acknowledge (ACK) signal is issued.
However, when the slave device has received an extension code, a wait is inserted at the falling edge of the eighth
clock.
Condition for clearing (WTIM0 = 0) Condition for setting (WTIM0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
A
CKE0Notes 1,
2 Acknowledgment control
0 Disable acknowledgment.
1 Enable acknowledgment. During the ninth clock period, the SDAA0 line is set to low level.
Condition for clearing (ACKE0 = 0) Condition for setting (ACKE0 = 1)
• Cleared by instruction
• Reset
• Set by instruction
Notes 1. The signal of this bit is invalid while IICE0 is 0. Set this bit during that period.
2. The set value is invalid during address transfer and if the code is not an extension code.
When the device serves as a slave and the addresses match, an acknowledgment is generated
regardless of the set value.
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Figure 12-6. Format of IIC A Control Regi ster 00 (IICCTL00) (3/4)
STT0Note Start condition trigger
0 Do not generate a start condition.
1 When bus is released (in standby state, when IICBSY = 0):
If this bit is set (1), a start condition is generated (startup as the master).
When a third party is communicating:
• When communication reservation function is enabled (IICRSV = 0)
Functions as the start condition reservation flag. When set to 1, automatically generates a start
condition after the bus is released.
• When communication reservation function is disabled (IICRSV = 1)
Even if this bit is set (1), the STT0 bit is cleared and the STT0 clear flag (STCF) is set (1). No start
condition is generated.
In the wait state (when master device):
Generates a restart condition after releasing the wait.
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when the
ACKE0 bit has been cleared to 0 and slave has been notified of final reception.
• For master transmission: A start condition cannot be generated normally during the acknowledge period. Set to 1
during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as stop condition trigger (SPT0).
• Setting the STT0 bit to 1 and then setting it again before it is cleared condition is prohibited.
Condition for clearing (STT0 = 0) Condition for setting (STT0 = 1)
• Cleared by setting the STT0 bit to 1 while
communication reservation is prohibited.
• Cleared by loss in arbitration
• Cleared after start condition is generated by master
device
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Note The signal of this bit is invalid while IICE0 is 0.
Remarks 1. Bit 1 (STT0) becomes 0 when it is read after data setting.
2. IICRSV0: Bit 0 of IIC flag register 0 (IICF0)
STCF0: Bit 7 of IIC flag register 0 (IICF0)
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Figure 12-6. Format of IIC A Control Regi ster 00 (IICCTL00) (4/4)
SPT0 Stop condition trigger
0 Stop condition is not generated.
1 Stop condition is generated (termination of master device’s transfer).
Cautions concerning set timing
• For master reception: Cannot be set to 1 during transfer.
Can be set to 1 only in the waiting period when the ACKE0 bit has been cleared to 0 and
slave has been notified of final reception.
• For master transmission: A stop condition cannot be generated normally during the acknowledge period.
Therefore, set it during the wait period that follows output of the ninth clock.
• Cannot be set to 1 at the same time as start condition trigger (STT0).
• The SPT0 bit can be set to 1 only when in master mode.
• When the WTIM0 bit has been cleared to 0, if the SPT0 bit is set to 1 during the wait period that follows output of
eight clocks, note that a stop condition will be generated during the high-level period of the ninth clock. The WTIM0
bit should be changed from 0 to 1 during the wait period following the output of eight clocks, and the SPT0 bit should
be set to 1 during the wait period that follows the output of the ninth clock.
• Setting the SPT0 bit to 1 and then setting it again before it is cleared c ondition is prohibited.
Condition for clearing (SPT0 = 0) Condition for setting (SPT0 = 1)
• Cleared by loss in arbitration
• Automatically cleared after stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When IICE0 = 0 (operation stop)
• Reset
• Set by instruction
Caution When bit 3 (TRC0) of the IICA status register 0 (IICS0) is set to 1 (transmission status), bit 5
(WREL0) of IICA control register 00 (IICCTL00) is set to 1 during the ninth clock and wait is
canceled, after which the TRC0 bit is cleared (receptio n status) and the SDAA0 line is set to
high impedance. Release the wait performed while the TRC0 bit is 1 (transmission status)
by writing to the IICA shift register 0.
Remark Bit 0 (SPT0) becomes 0 when it is read after data setting.
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12.3.3 IICA status register 0 (IICS0)
This register indicates the status of I2C.
The IICS0 register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the
wait period.
Reset signal generation clears this register to 00H.
Caution Reading the IICS0 register while the address match wakeup function is enabled (WUP0 = 1) in
STOP mode is prohibited. When the WUP0 bit is changed from 1 to 0 (wakeup operation is
stopped), regardless of the INTIICA0 interrupt request, the change in status is not reflected until
the next start condition or stop condition is detected. To use the wakeup function, therefore,
enable (SPIE0 = 1) the interrupt generated by detecting a stop condition and read the IICS0
register after the interrupt has been detected.
Remark STT0: bit 1 of IICA control register 00 (IICCTL00)
WUP0: bit 7 of IICA control register 01 (IICCTL01)
Figure 12-7. Format of IIC A Status Register 0 (IICS0) (1/3)
Address: FFF51H After reset: 00H R
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IICS0 MSTS0 ALD0 EXC0 COI0 TRC0 ACKD0 STD0 SPD0
MSTS0 Master status check flag
0 Slave device status or communication standby status
1 Master device communication status
Condition for clearing (MSTS0 = 0) Condition for setting (MSTS0 = 1)
• When a stop condition is detected
• When ALD0 = 1 (arbitration loss)
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When a start condition is generated
ALD0 Detection of arbitration loss
0 This status means either that there was no arbitration or that the arbitration result was a “win”.
1 This status indicates the arbitration result was a “loss”. The MSTS0 bit is cleared.
Condition for clearing (ALD0 = 0) Condition for setting (ALD0 = 1)
• Automatically cleared after the IICS0 register is
readNote
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When the arbitration result is a “loss”.
Note T his register is also cleared when a 1-bit memory manipulation instruction is exec uted for bits other
than the IICS0 register. Therefore, when using the ALD0 bit, read the data of this bit before the data
of the other bits.
Remark LREL0: Bit 6 of IICA control register 00 (IICCTL00)
IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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Figure 12-7. Format of IIC A Status Register 0 (IICS0) (2/3)
EXC0 Detection of extension code reception
0 Extension code was not received.
1 Extension code was received.
Condition for clearing (EXC0 = 0) Condition for setting (EXC0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When the higher four bits of the received address
data is either “0000” or “1111” (set at the rising edge
of the eighth clock).
COI0 Detection of matching addresses
0 Addresses do not match.
1 Addresses match.
Condition for clearing (COI0 = 0) Condition for setting (COI0 = 1)
• When a start condition is detected
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When the received address matches the local
address (slave address register 0 (SVA0))
(set at the rising edge of the eighth clock).
TRC0 Detection of transmit/receive status
0 Receive status (other than transmit status). The SDAA0 line is set for high impedance.
1 Transmit status. The value in the SO0 latch is enabled for output to the SDAA0 line (valid starting at
the falling edge of the first byte’s ninth clock).
Condition for clearing (TRC0 = 0) Condition for setting (TRC0 = 1)
<Both master and slave>
• When a stop condition is detected
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Cleared by WREL0 = 1Note (wait cancel)
• When the ALD0 bit changes from 0 to 1 (arbitration
loss)
• Reset
• When not used for communication (MSTS0, EXC0, COI0
= 0)
<Master>
• When “1” is output to the first byte’s LSB (transfer
direction specification bit)
<Slave>
• When a start condition is detected
• When “0” is input to the first byte’s LSB (transfer
direction specification bit)
<Master>
• When a start condition is generated
• When 0 (master transmission) is output to the LSB
(transfer direction specification bit) of the first byte
(during address transfer)
<Slave>
• When 1 (slave transmission) is input to the LSB
(transfer direction specification bit) of the first byte
from the master (during address transfer)
Note When bit 3 (TRC0) of the IICA status register 0 (IICS0) is set to 1 (transmission status), bit 5
(WREL0) of IICA control register 00 (IICCTL00) is set to 1 during the ninth clock and wait is
canceled, after which the TRC0 bit is cleared (reception status) and the SDAA0 line is set to high
impedance. Release the wait performed while the T RC0 bit is 1 (transmission status) by writing to
the IICA shift register 0.
Remark LREL0: Bit 6 of IICA control register 00 (IICCT L00)
IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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Figure 12-7. Format of IIC A Status Register 0 (IICS0) (3/3)
ACKD0 Detection of acknowledge (ACK)
0 Acknowledge was not detected.
1 Acknowledge was detected.
Condition for clearing (ACKD0 = 0) Condition for setting (ACKD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• After the SDAA0 line is set to low level at the rising
edge of SCLA0 line’s ninth clock
STD0 Detection of start condition
0 Start condition was not detected.
1 Start condition was detected. This indicates that the address transfer period is in effect.
Condition for clearing (STD0 = 0) Condition for setting (STD0 = 1)
• When a stop condition is detected
• At the rising edge of the next byte’s first clock
following address transfer
• Cleared by LREL0 = 1 (exit from communications)
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When a start condition is detected
SPD0 Detection of stop condition
0 Stop condition was not detected.
1 Stop condition was detected. The master device’s communication is terminated and the bus is
released.
Condition for clearing (SPD0 = 0) Condition for setting (SPD0 = 1)
• At the rising edge of the address transfer byte’s first
clock following setting of this bit and detection of a
start condition
• When the WUP0 bit changes from 1 to 0
• When the IICE0 bit changes from 1 to 0 (operation
stop)
• Reset
• When a stop condition is detected
Remark LREL0: Bit 6 of IICA control register 00 (IICCT L00)
IICE0: Bit 7 of IICA control register 0 0 (IICCTL00)
12.3.4 IICA fl a g register 0 (IICF0)
This register sets the operation mode of I2C and indicates the status of the I2C bus.
The IICF0 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the STT0 clear flag
(STCF) and I2C bus status flag (IICBSY) bits are read-only.
The IICRSV bit can be used to enable/disa ble the communication reservation function.
The STCEN bit can be used to set the initial value of the IICBSY bit.
The IICRSV and STCEN bits can be written only when the operation of I2C is dis abled (bit 7 (IICE0) of IICA control
register 00 (IICCTL00) = 0). When operation is enabled, the IICF0 register can be read.
Reset signal generation clears this register to 00H.
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Figure 12-8. Format of IIC A Flag Register 0 (IICF0)
<7>
STCF0
Condition for clearing (STCF0 = 0)
- Cleared by STT0 = 1
- When IICE0 = 0 (operation stop)
- Reset
Condition for setting (STCF0 = 1)
- Generating start condition unsuccessful and the
STT0 bit cleared to 0 when communication
reservation is disabled (IICRSV0 = 1).
STCF0
0
1
Generate start condition
Start condition generation unsuccessful: clear the STT0 flag
STT0 clear flag
IICF0
Symbol <6>
IICBSY0
5
0
4
0
3
0
2
0
<1>
STCEN0
<0>
IICRSV0
Address: FFF52H After reset: 00H R/W
Note
Condition for clearing (IICBSY0 = 0)
- Detection of stop condition
- When IICE0 = 0 (operation stop)
- Reset
Condition for setting (IICBSY0 = 1)
- Detection of start condition
- Setting of the IICE0 bit when STCEN0 = 0
IICBSY0
0
1
Bus release status (communication initial status when STCEN0 = 1)
Bus communication status (communication initial status when STCEN0 = 0)
I
2
C bus status flag
Condition for clearing (STCEN0 = 0)
- Cleared by instruction
- Detection of start condition
- Reset
Condition for setting (STCEN0 = 1)
- Set by instruction
STCEN0
0
1
After operation is enabled (IICE0 = 1), enable generation of a start condition upon detection of
a stop condition.
After operation is enabled (IICE0 = 1), enable generation of a start condition without detecting
a stop condition.
Initial start enable trigger
Condition for clearing (IICRSV0 = 0)
- Cleared by instruction
- Reset
Condition for setting (IICRSV0 = 1)
- Set by instruction
IICRSV0
0
1
Enable communication reservation
Disable communication reservation
Communication reservation function disable bit
Note Bits 6 and 7 are read-only.
Cautions 1. Write to the STCEN bit only when the operation is stopped (IICE0 = 0).
2. As the bus release status (IICBSY = 0) is recognized regardless of the actual bus status
when STCEN = 1, when generating the first start condition (STT0 = 1), it is necessary to
verify that no third party communications are in progress in order to prevent such
communications from being destroyed.
3. Write to IICRSV only when the operation is stopped (IICE0 = 0).
Remark STT0: Bit 1 of IICA control register 00 (IICCTL00)
IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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12.3.5 IICA control register 01 (IICCTL01)
This register is used to set the operation mode of I2C and detect the statuses of the SCLA0 and SDAA0 pins.
The IICCTL01 register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and
DAD0 bits are read-only.
Set the IICCTL01 register, except the WUP0 bit, while operation of I2C is disabled (bit 7 (IICE0) of IICA control
register 00 (IICCTL00) is 0).
Reset signal generation clears this register to 00H.
Figure 12-9. Format of IIC A Control Regi ster 01 (IICCTL01) (1/2)
Address: F0231H After reset: 00H R/WNote 1
Symbol 7 6 <5> <4> <3> <2> 1 <0>
IICCTL01 WUP0 0 CLD0 DAD0 SMC0 DFC0 0 PRS0
WUP0 Control of address match wakeup
0 Stops operation of address match wakeup function in STOP mode.
1 Enables operation of address match wakeup function in STOP mode.
To shift to STOP mode when WUP0 = 1, execute the STOP instruction at least three clocks after setting (1) the
WUP0 bit (see Figure 12-22 Flow When Setting WUP0 = 1).
Clear (0) the WUP0 bit after the address has matched or an extension code has been received. The
subsequent communication can be entered by the clearing (0) WUP0 bit. (The wait must be released and
transmit data must be written after the WUP0 bit has been cleared (0).)
The interrupt timing when the address has matched or when an extension code has been received, while WUP0
= 1, is identical to the interrupt timing when WUP0 = 0. (A delay of the difference of sampling by the clock will
occur.) Furthermore, when WUP0 = 1, a stop condition interrupt is not generated even if the SPIE0 bit is set to
1.
When WUP0 = 0 is set by a source other than an interrupt from serial interface IICA, operation as the master
device cannot be performed until the subsequent start condition or stop condition is detected. Do not output a
start condition by setting (1) the STT0 bit, without waiting for the detection of the subsequent start condition or
stop condition.
Condition for clearing (WUP0 = 0) Condition for setting (WUP0 = 1)
• Cleared by instruction (after address match or
extension code reception)
• Set by instruction (when the MSTS0, EXC0, and
COI0 bits are “0”, and the STD0 bit also “0”
(communication not entered))Note 2
Notes 1. Bits 4 and 5 are read-only.
2. The status of the IICA status register 0 (IICS0) must be checked and the WUP0 bit must be set
during the period shown below.
SCLA0
<1> <2>
SDAA0 A6 A5 A4 A3 A2 A1 A0
The maximum time from reading IICS0 to setting
WUP0 is the period from <1> to <2>.
Check the IICS0 operation status and set
WUP0 during this period.
R/W
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Figure 12-9. Format of IIC A Control Regi ster 01 (IICCTL01) (2/2)
CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1)
0 The SCLA0 pin was detected at low level.
1 The SCLA0 pin was detected at high level.
Condition for clearing (CLD0 = 0) Condition for setting (CLD0 = 1)
• When the SCLA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SCLA0 pin is at high level
DAD0 Detection of SDAA0 pin level (valid only when IICE0 = 1)
0 The SDAA0 pin was detected at low level.
1 The SDAA0 pin was detected at high level.
Condition for clearing (DAD0 = 0) Condition for setting (DAD0 = 1)
• When the SDAA0 pin is at low level
• When IICE0 = 0 (operation stop)
• Reset
• When the SDAA0 pin is at high level
SMC0 Operation mode switching
0 Operates in standard mode (fastest transfer rate: 100 kbps).
1 Operates in fast mode (fastest transfer rate: 400 kbps).
DFC0 Digital filter operation control
0 Digital filter off.
1 Digital filter on.
Digital filter can be used only in fast mode.
In fast mode, the transfer clock does not vary, regardless of the DFC0 bit being set (1) or cleared (0).
The digital filter is used for noise elimination in fast mode.
PRS0 Division of the operation clock
0 Selects fCLK as operation clock.
1 Selects fCLK/2 as operation clock.
Caution The fastest operation frequency of the operation clock of the serial interface IICA is 20
MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 b y setting the PRS0 bit to
1.
Remark IICE0: Bit 7 of IICA control register 00 (IICCTL00)
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12.3.6 IICA low-level width setting register 0 (IICWL0)
This register is used to set the lo w-level width (tLOW) of the SCLA0 pin signal that is outp ut by serial interface IICA.
The IICWL0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWL0 register while operation of I2C is disab le d (bit 7 (IICE0) of IICA control re gister 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
For details about setting the IICWL0 register, see 12.4.2 Setting transfer clock by using IICWL0 and IICWH0
registers.
Figure 12-10. Format of IICA Low-Level Width Setting Register 0 (IICWL0)
Address: F0232H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWL0
12.3.7 IICA high-level width setting register 0 (IICWH0)
This register is used to set the high-level width of the SCLA0 pin signal that is output by serial interface IICA.
The IICWH0 register can be set by an 8-bit memory manipulation instruction.
Set the IICWH0 register while operation of I2C is disab le d (bit 7 (IICE0) of IICA control re gister 00 (IICCTL00) is 0).
Reset signal generation sets this register to FFH.
Figure 12-11. Format of IICA High-Level Width Setting Register 0 (IICWH0)
Address: F0233H After reset: FFH R/W
Symbol 7 6 5 4 3 2 1 0
IICWH0
Remark For how to set the transfer clock by using the IICWL0 and IICWH0 registers, see 12.4.2 Setting
transfer clock by using IICWL0 an d IICWH0 registers.
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12.3.8 Port mode register 6 (PM6)
This register sets the input/output of port 6 in 1-bit units.
When using the P60/SCLA0 pin as clock I/O and the P61/SDAA0 pin as serial data I/O, clear PM60 and PM61, and
the output latches of P60 and P61 to 0.
Set the IICE0 bit (bit 7 of IICA control register 00 (IICCTL00)) to 1 before setting the output mode because the
P60/SCLA0 and P61/SDAA0 pins output a lo w level (fixed) when the IICE0 bit is 0.
The PM6 register can be set by a 1-bit or 8-bit memor y manipulati on instruction.
Reset signal generation sets this register to FFH.
Figure 12-12. Format of Port Mode Register 6 (PM6)
PM60PM61111111
P6n pin I/O mode selection (n = 0, 1)
Output mode (output buffer on)
Input mode (output buffer off)
PM6n
0
1
01234567
PM6
Address: FFF26H After reset: FFH R/W
Symbol
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12.4 I2C Bus Mode Functions
12.4.1 Pin configuration
The serial clock pin (SCLA0) and the serial data bus pin (SDAA0) are configured as follows.
(1) SCLA0 ....This pin is used for serial clock input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
(2) SDAA0....This pin is used for serial data input and output.
This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input.
Since outputs from the serial clock line and the serial data bus line are N-ch open-drain outputs, an external pull-up
resistor is required.
Figure 12-13. Pin Configuration Diagram
Master device
Clock output
(Clock input)
Data output
Data input
V
SS
V
SS
SCLA0
SDAA0
V
DD
V
DD
(Clock output)
Clock input
Data output
Data input
V
SS
V
SS
Slave device
SCLA0
SDAA0
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12.4.2 Setting transfer clock by using IICWL0 and IICWH0 registers
(1) Setting transfer clock on master side
Transfer clock = fCLK
IICWL0 + IICWH0 + fCLK (tR + tF)
At this time, the optimal setting values of the IICWL0 and IICWH0 registers are as follows.
(The fractional parts of all setting values are rounded up.)
• When the fast mode
IICWL0 = 0.52
Transfer clock × fCLK
IICWH0 = ( 0.48
Transfer clock − tR − tF) × fCLK
• When the normal mode
IICWL0 = 0.47
Transfer clock × fCLK
IICWH0 = ( 0.53
Transfer clock − tR − tF) × fCLK
(2) Setting IICWL0 and IICWH0 registers o n slave side
(The fractional parts of all setting values are truncated.)
• When the fast mode
IICWL0 = 1.3
μ
s × fCLK
IICWH0 = (1.2
μ
s − tR − tF) × fCLK
• When the normal mode
IICWL0 = 4.7
μ
s × fCLK
IICWH0 = (5.3
μ
s − tR − tF) × fCLK
Caution Note the minimum fCLK operation frequency when setting the transfer clock. The minimum fCLK
operation frequency for serial interface IICA is determined accord ing to the mode.
Fast mode: fCLK = 3.5 MHz (MIN.)
Normal mode: fCLK = 1 MHz (MIN.)
In addition, the fast est operation frequency of the oper ation clock of the serial interface IIC A is 20
MHz (Max.). If the fCLK exceeds 20 MHz, set the clock to fCLK/2 by setting the PRS0 bit of IICCTL01
register to 1.
Remarks 1. Calculate the rise time (tR) and fall time (tF) of the SDAA0 and SCLA0 signals separately, because
they differ depending on the pull-up resistance and wire load.
2. IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal fal ling times
t
R: SDAA0 and SCLA0 signal rising times
f
CLK: CPU/peripheral hardware clock frequency
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12.5 I2C Bus Definitions and Control Methods
The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus.
Figure 12-14 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C
bus’s serial data bus.
Figure 12-14. I2C Bus Serial Data Transfer Timing
SCLA0
SDAA0
Start
condition Address R/W ACK Data
1-7 8 9 1-8
ACK Data ACK Stop
condition
9 1-8 9
The master device generates the start condition, slave address, and stop condition.
The acknowledge (ACK) can be generated by either the master or slave device (normally, it is output by the device that
receives 8-bit data).
The serial clock (SCLA0) is continuously output by the mas t er device. Ho wever, i n the slave device, the SCLA0 pin low
level period can be extended and a wait can be inserted.
12.5.1 Start conditions
A start condition is met when the SCLA0 pin is at high level and the SDAA0 pin changes from high level to low level.
The start conditions for the SCLA0 pin and SDAA0 pin are signals that the master device generates to the slave device
when starting a serial transfer. When the device is used as a slave, start conditions can be detected.
Figure 12-15. Start Conditions
SCLA0
SDAA0
H
A start condition is output when bit 1 (STT0) of IICA control register 00 (IICCT L00) is set (1) after a stop condition has
been detected (SPD0: Bit 0 of the IICA status register 0 (IICS0) = 1). When a start condition is detected, bit 1 (ST D0) of
the IICS0 register is set (1).
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12.5.2 Addresses
The address is defined by the 7 bits of data that follow the start condition.
An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the
master device via the bus lines. Theref ore, each slave device connected via the bus l ines must have a unique address.
The slave devices include hardware that detects the start condition and checks whether or not the 7-bit address data
matches the data values stored in the slave address register 0 (SVA0). If the address data matches the SVA0 register
values, the slave device is selected and communicates with the master device until the master device generates a start
condition or stop condition.
Figure 12-16. Address
SCLA0
SDAA0
INTIICA0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Address
Note
Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device
operation.
Addresses are output when a total of 8 bits consisting of the slave address and the transfer direction described in
12.5.3 Transfer direction specification are written to the IICA shift register 0 (IICA0). The received addresses are
written to the IICA0 register.
The slave address is assigned to the hig her 7 bits of the IICA0 register.
12.5.3 Transfer direction specification
In addition to the 7-bit address data, the master device sends 1 bit that specifies the transfer direction.
When this transfer direction specificati on bit has a value of “0”, it indicates that the master device is transmitting data to
a slave device. When the transfer direction specification bit has a value of “1”, it indicates that the master device is
receiving data from a slave device.
Figure 12-17. Transfer Direction Specification
SCLA0
SDAA0
INTIICA0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W
Transfer direction specification
Note
Note INTIICA0 is not issued if data other than a local address or extension code is received during slave device
operation.
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12.5.4 Acknow ledge (ACK)
ACK is used to check the status of serial data at the transmission and reception sides.
The reception side returns ACK each time it has received 8-bit data.
The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side,
it is assumed that reception has been correc tly performed and processing is c ontinued. Whether ACK has been detected
can be checked by using bit 2 (ACKD0) of the IICA status register 0 (IICS0).
When the master receives the last data item, it does not return ACK and instead generat es a stop condition. If a slave
does not return ACK after receiving d ata, the master outputs a stop condition or restart condition an d stops transmission.
If ACK is not returned, the possible causes are as follows.
<1> Reception was not performed normally.
<2> The final data item was received.
<3> The reception side specified by the address does not exist.
To generate ACK, the reception side makes the SDAA0 line low at the ninth clock (indicating normal rec eption).
Automatic generation of ACK is enabled by setting bit 2 (ACKE0) of IICA control register 00 (IICCTL00) to 1. Bit 3
(TRC0) of the IICS0 register is set by the data of the eighth bit that follows 7-bit address information. Usually, set the
ACKE0 bit to 1 for reception (TRC0 = 0).
If a slave can receive no more data during r eception (TRC0 = 0) or does not require the next d ata item, then the slave
must inform the master, by clearing the ACKE0 bit to 0, that it will not receive any more data.
When the master does not require the next data item during receptio n (TRC0 = 0), it must clear the ACKE0 bit to 0 so
that ACK is not generated. In this way, the master informs a slave at the transmission side that it does not require any
more data (transmission will be stopped).
Figure 12-18. ACK
SCLA0
SDAA0
123456789
A6 A5 A4 A3 A2 A1 A0 R/W ACK
When the local addr ess is received, ACK is automatically generated, regardless of th e value of the ACKE0 bit. When
an address other than that of the local address is receive d, ACK is not gen erated (NACK).
When an extension code is received, ACK is generated if the ACKE0 bit is set to 1 in advance.
How ACK is generated when data is received differs as follows depending on the setting of the wait timing.
• When 8-clock wait state is selected (bit 3 (WTIM0) of IICCTL00 register = 0):
By setting the ACKE0 bit to 1 before releasing the wait state, ACK is generated at the falling edge of the eighth clock
of the SCLA0 pin.
• When 9-clock wait state is selected (bit 3 (WTIM0) of IICCTL00 register = 1):
ACK is generated by setting the ACKE0 bit to 1 in advance.
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12.5.5 Stop condition
When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level gen erates a stop condition.
A stop condition is a signal that the master device generates to the slave device when serial transfer has been
completed. When the device is used as a slave, stop con di tions can be detected.
Figure 12-19. Stop Condition
SCLA0
SDAA0
H
A stop condition is generated when bit 0 (SPT0) of IICA control register 00 (IICCTL00) is set to 1. When the stop
condition is detected, bit 0 (SPD0) of the IICA status register 0 (IICS0) is set to 1 and INTIICA0 is generated when bit 4
(SPIE0) of the IICCTL00 register is set to 1.
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12.5.6 Wait
The wait is used to notify the communication partner that a device (master or slave) is prepari ng to transmit or receive
data (i.e., is in a wait state).
Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been
canceled for both the master and slave devic es, the next data transfer can begin.
Figure 12-20. Wait (1/2)
(1) When master device has a nine-clock wait and slave device has an eight-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IICA0
SCLA0
Slave
IICA0
SCLA0
ACKE0
Transfer lines
SCLA0
SDAA0
6789 123
Master returns to high
impedance but slave
is in wait state (low level). Wait after output
of ninth clock IICA0 data write (cancel wait)
Wait after output
of eighth clock
Wait from slave Wait from master
FFH is written to IICA0 or WREL0 is set to 1
678 9 123
D2 D1 D0 D7 D6 D5ACK
H
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Figure 12-20. Wait (2/2)
(2) When master and slave devices both have a nine-clock wait
(master transmits, slave receives, and ACKE0 = 1)
Master
IICA0
SCLA0
Slave
IICA0
SCLA0
ACKE0
Transfer lines
SCLA0
SDAA0
H
6789 1 23
Master and slave both wait
after output of ninth clock
Wait from
master and
slave Wait from slave
IICA0 data write (cancel wait)
FFH is written to IICA0 or WREL0 is set to 1
6789 123
D2 D1 D0 ACK D7 D6 D5
Generate according to previously set ACKE0 value
Remark ACKE0: Bit 2 of IICA control register 0 0 (IICCTL00)
WREL0: Bit 5 of IICA control register 00 (IICCTL00)
A wait may be automatically generated depe nding on the s etting of bit 3 ( WT IM0) of IICA control regist er 00 (IICCT L0 0).
Normally, the receiving side cancels the wait state when bit 5 (WREL0) of the IICCTL00 register is set to 1 or when
FFH is written to the IICA shift register 0 (IICA0), and the transmitting side cancels the wait state when data is written to
the IICA0 register.
The master device can also cancel the wait state via either of the following methods.
• By setting bit 1 (STT0) of the IICCTL00 regist er to 1
• By setting bit 0 (SPT0) of the IICCTL00 register to 1
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12.5.7 Canceling wait
The I2C usually cancels a wait state by the following processing.
• Writing data to the IICA shift register 0 (IICA0)
• Setting bit 5 (WREL0) of IICA control register 00 (IICCT L00) (canceling wait)
• Setting bit 1 (STT0) of the IICCTL00 register (generating start condition)Note
• Setting bit 0 (SPT0) of the IICCTL00 register (generating stop condition)Note
Note Master only
When the above wait canc eling processing is executed, the I2C cancels the wait state and communication is resumed.
To cancel a wait state and transmit data (including addresses), write the data to the IICA0 register.
To receive data after canceling a wait state, or to complete data transmission, set bit 5 (WREL0) of the IICCTL00
register to 1.
To generate a restart condition after cancel ing a wait state, set bit 1 (STT0) of the IICCTL00 register to 1.
To generate a stop condition after canceling a wait state, set bit 0 (SPT0) of the IICCTL00 register to 1.
Execute the canceling processing only once for one wait state.
If, for example, data is written to the IICA0 register after canceling a wait state by setting the WREL0 bit to 1, an
incorrect value may be output to SDAA0 line becaus e the timing for changing the SDAA0 line conflicts with the timing for
writing the IICA0 register.
In addition to the above, communication is stopped if the IICE0 bit is cleared to 0 when communication has been
aborted, so that the wait state can be canceled.
If the I2C bus has deadlocked due to noise, processing is saved from communication by setting bit 6 (LREL0) of the
IICCTL00 register, so that the wait state can be canc eled.
Caution If a processing to cancel a wait state is executed when WUP0 = 1, the wait state will not be
canceled.
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12.5.8 Interrupt request (INTIICA0) generation timing and wait control
The setting of bit 3 (WTIM0) of IICA control register 00 (IICCTL00) determines the timing by which INTIICA0 is
generated and the corresponding wait control, as shown in Table 12-2.
Table 12-2. INTIICA0 Generation Timing and Wait Control
During Slave Device Operation During Master Device Operation WTIM0
Address Data Reception Data Transmission Address Data Reception Data Transmission
0 9Notes 1, 2 8
Note 2 8
Note 2 9 8 8
1 9Notes 1, 2 9
Note 2 9
Note 2 9 9 9
Notes 1. The slave device’s INTIICA0 signal and wait period occurs at the falling edge of the ninth clock only when
there is a match with the address set to the slave address register 0 (SVA0).
At this point, ACK is generated regardless of the value set to the IICCTL00 register ’s bit 2 (ACKE0). For a
slave device that has received an extension code, INTIICA0 occurs at the falling edge of the eighth clock.
However, if the address does not match after restart, INTIICA0 is generated at the falling edge of the 9th
clock, but wait does not occur.
2. If the received address does not match the contents of the slave address register 0 (SVA0) and extension
code is not received, neither INTIICA0 nor a wait occurs.
Remark The numbers i n the table indicate the number of the serial clock’s clock signals. Interrupt requests and wait
control are both synchronized with the falling edge of these clock signals.
(1) During address transmission/reception
• Slave device operation: Interrupt and wait timing are determined depending on the conditions described in
Notes 1 and 2 above, regardless of the WTIM0 bit.
• Master device operation: Interrupt and wait timing occur at the falling edge of the ninth clock regardless of the
WTIM0 bit.
(2) During data reception
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(3) During data transmission
• Master/slave device operation: Interrupt and wait timing are determined according to the WTIM0 bit.
(4) Wait cancellation method
The four wait cancellation methods are as follows.
• Writing data to the IICA shift register 0 (IICA0)
• Setting bit 5 (WREL0) of IICA control register 00 (IICCTL00) (canceling wait)
• Setting bit 1 (STT0) of IICCTL00 register (generating start condition)Note
• Setting bit 0 (SPT0) of IICCTL00 register (generating stop condition)Note
Note Master only.
When an 8-clock wait has been selected (WTIM0 = 0), the presence/absence of ACK generation must be
determined prior to wait cancellati on.
(5) Stop condition detection
INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1).
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12.5.9 Address match detection method
In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave
address.
Address match can be detected autom atically by hardware. An interrupt request (INTIICA0) occurs when the address
set to the slave address register 0 (SVA0) matches the slave address sent by the master device, or when an extension
code has been received.
12.5.10 Error detection
In I2C bus mode, the status of the serial data bus (SDAA0) during data transmission is captured by the IICA shift
register 0 (IICA0) of the transmitting device, so the IICA data prior to transmission can be compared with the transmitted
IICA data to enable detection of transmission errors. A transmission error is judged as having occurred when the
compared data values do not match.
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12.5.11 Extension co d e
(1) When the higher 4 b its of the receive addres s are either “0000” or “1111”, t he extensio n code r eception f lag (EXC 0)
is set to 1 for extension code reception and an interrupt request (INTIICA0) is issued at the falling edge of the
eighth clock. The local address stored in the slave address register 0 (SVA0) is not affected.
(2) The settings belo w are specified if 11110xx0 is transferred from the master b y using a 10-bit address transfer when
the SVA0 register is set to 11110xx0. Note that INTIICA0 occurs at the falling edge of the eighth clock.
• Higher four bits of data match: EXC 0 = 1
• Seven bits of data match: COI0 = 1
Remark EXC0: Bit 5 of IICA status register 0 (IICS0)
COI0: Bit 4 of IICA status register 0 (IICS0)
(3) Since the pr oc essing after the interrupt re qu est occurs differs according to the d ata that follows the extension code,
such processing is performed by software.
If the extension code is received while a slave device is operating, then the slave device is participating in
communication even if its address does not match.
For example, after the extension code is rece ived, if yo u do not wish to operate the target device as a slave dev ice,
set bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 to set the standby mode for the next communication
operation.
Table 12-3. Bit Definitions of Major Extension Cod es
Slave Address R/W Bit Description
0 0 0 0 0 0 0 0 General call address
1 1 1 1 0 x x 0 10-bit slave address specification (during address
authentication)
1 1 1 1 0 x x 1 10-bit slave address specification (after address match, when
read command is issued)
Remark See the I2C bus specifications issued by NXP Semiconductors for details of extension codes other than
those described above.
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12.5.12 Arbitration
When several master devices simultaneousl y generate a st art condition ( when the STT0 bit is set to 1 before the ST D0
bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the da ta
differs. This kind of operation is called arbitration.
When one of the master devi ces loses in arbitration, an ar bitration loss flag (ALD0) in the IICA status register 0 (IICS 0)
is set (1) via the timing by which the arbitration loss occurred, and the SCLA0 and SDAA0 lines are both set to high
impedance, which releases th e bus.
The arbitration loss is detecte d based on the timing of the n ext interrupt request (the eigh th or ninth clock, when a stop
condition is detected, etc.) and the ALD0 = 1 setting that has been made by software.
For details of interrupt request timing, see 12.5.8 Interrupt request (INTIICA0) generation timing and wait control.
Remark STD0: Bit 1 of IICA status register 0 (IICS0)
STT0: Bit 1 of IICA control register 00 (IICCTL00)
Figure 12-21. Arbitration Timing Example
SCLA0
SDAA0
SCLA0
SDAA0
SCLA0
SDAA0
Hi-Z
Hi-Z
Master 1 loses arbitration
Master 1
Master 2
Transfer lines
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Table 12-4. Status During Arbitration and Interrupt Request Generation Timing
Status During Arbitration Interrupt Request Generation Timing
During address transmission
Read/write data after address transmission
During extension code transmission
Read/write data after extension code transmission
During data transmission
During ACK tran sfer period after data transmission
When restart condition is detected during data transfer
At falling edge of eighth or ninth clock following byte transferNote
1
When stop condition is detected during data transfer When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a restart
condition At falling edge of eighth or ninth clock following byte transferNote
1
When stop condition is detected while attempting to generate a
restart condition When stop condition is generated (when SPIE0 = 1)Note 2
When data is at low level while attempting to generate a stop
condition
When SCLA0 is at low level while attempting to generate a
restart condition
At falling edge of eighth or ninth clock following byte transferNote
1
Notes 1. When the WTIM0 bit (bit 3 of IICA control register 00 (IICCTL00)) = 1, an interrupt request occurs at the
falling edge of the ninth clock. When WTIM0 = 0 and the extension code’s slave address is received, an
interrupt request occurs at the falling edge of the eighth clock.
2. W hen there is a chance that arbitration will occur, set SPIE0 = 1 for master device operation.
Remark SPIE0: Bit 4 of IICA control register 00 (IICC TL00)
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12.5.13 Wakeup function
The I2C bus slave function is a function that generates a n interrupt request signal (INT IICA0) when a local address and
extension code have been received.
This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when
addresses do not match.
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave devic e.
To use the wakeup function in the STOP mode, set the WUP0 bit to 1. Addresses can be received regardless of the
operation clock. An interrupt requ est signal (INTIICA0) is also generated when a local address and extension cod e have
been received. Operation returns to normal operation by using an instruction to clear (0) the WUP0 bit after this interrupt
has been generated.
Figure 12-22 shows the flow for setting WUP0 = 1 and Figure 12-23 shows the flow for setting WUP0 = 0 upon an
address match.
Figure 12-22. Flow When Setting WUP0 = 1
Waits for 3 clocks.
Yes
No
START
WUP0 = 1
Wait
STOP instruction execution
MSTS0 = STD0 = EXC0 = COI0 =0?
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Figure 12-23. Flow When Setting WUP0 = 0 upon Address Match (Including Extension Code Reception)
Waits for 5 clocks.
Executes processing corresponding to the operation to be executed
after checking the operation state of serial interface IICA.
STOP mode state
No
Yes
WUP0 = 0
Wait
Reading IICS0
INTIICA0 = 1?
Use the following flows to perform the processing to release the STOP mode other than by an interrupt request
(INTIICA0) generated from serial interface IICA.
• Master device operation: Flow shown in Figure 12-24
• Slave device operation: Same as the flow in Figure 12-23
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Figure 12-24. When Operating as Master Device after Releasing STOP Mode other than by INTIICA0
Executes processing corresponding to the operation to be executed
after checking the operation state of serial interface IICA.
No
Yes
Releases STOP mode by an interrupt other than INTIICA0.
Generates a STOP condition or selects
as a slave device.
START
WUP0 = 1
SPIE0 = 1
Releasing STOP mode
STOP instruction
WUP0 = 0
Reading IICS0
INTIICA0 = 1?
STOP mode state
Waits for 5 clocks.
Wait
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12.5.14 Communication reservation
(1) When communication reservation function is enabled (b it 0 (IICRSV) o f IICA flag register 0 (IICF0) = 0)
To start master device communications when not currently using a bus, a communication reservation can be made
to enable transmission of a start condition when the bus is releas ed. There are two modes under which the bus is
not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL0) of IICA control register 00 (IICCTL00) to 1 and saving communication).
If bit 1 (STT0) of the IICCTL00 register is set to 1 while the bus is not used (after a stop condition is detected), a
start condition is automatically generated and wait state is set.
If an address is written to the IICA shift register 0 (IICA0) after bit 4 (SPIE0) of the IICCT L00 register was set to 1,
and it was detected by generation of an interrupt request signal (INTIICA0) that the bus was released (detection of
the stop condition), then the device automatically starts communication as the master. Data written to the IICA0
register before the stop condition is detected is invalid.
When the STT0 bit has been set to 1, the operation mode (as start condition or as communication reservation) is
determined according to the bus status.
• If the bus has been released ........................................a start condition is generated
• If the bus has not been released (standby mode).........communication reservation
Check whether the communication reservation operates or not by using the MSTS0 bit (bit 7 of the IICA status
register 0 (IICS0)) after the STT0 bit is set to 1 and the wait time elapses.
Use software to secure the wait time calculated by the following expression.
Wait time from setting STT0 = 1 to checking the MSTS0 flag:
(IICWL0 setting value + IICWH0 setting value + 4) + tF × 2 × fCLK [clocks]
Remark IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
t
F: SDAA0 and SCLA0 signal falling times
fCLK: CPU/peripheral hardware cloc k frequency
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Figure 12-25 shows the communicati on reservation timing.
Figure 12-25. Communication Reservation Timing
21 3456 21 3456789
SCLA0
SDAA0
Program processing
Hardware processing
Write to
IICA0
Set SPD0
and
INTIICA0
STT0 = 1
Communi-
cation
reservation
Set
STD0
Generate by master device with bus mastership
Remark IICA0: IICA shift register 0
STT0: Bit 1 of IICA control register 00 (IICCTL00)
STD0: Bit 1 of IICA status register 0 (IICS0)
SPD0: Bit 0 of IICA status register 0 (IICS0)
Communication reservations are accepted via the timing shown in Figure 12-26. After bit 1 (STD0) of the IICA
status register 0 (IICS0) is set to 1, a communication reservation can be made by setting bit 1 (STT0) of IICA
control register 00 (IICCTL00) to 1 before a s top condition is detected.
Figure 12-26. Timing for Accepting Communication Reservations
SCLA0
SDAA0
STD0
SPD0
Standby mode (Communication can be reserved by setting STT0 to 1 during this period.)
Figure 12-27 shows the communicati on reservation protocol.
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Figure 12-27. Communi cation Reservation Protocol
DI
SET1 STT0
Define communication
reservation
Wait
MSTS0 = 0?
(Communication reservation)
Note 2
Yes
No
(Generate start condition)
Cancel communication
reservation
MOV IICA0, #××H
EI
Sets STT0 flag (communication reservation)
Defines that communication reservation is in effect
(defines and sets user flag to any part of RAM)
Secures wait timeNote 1 by software.
Confirmation of communication reservation
Clear user flag
IICA0 write operation
Notes 1. The wait time is calculated as follows.
(IICWL0 setting value + IICWH0 setting value + 4) + t F × 2 × fCLK [clocks]
2. The communication reservation operation executes a write to the IICA shift register 0 (IICA0) when a
stop condition interrupt request occurs.
Remark STT 0: Bit 1 of IICA control register 00 (IICCTL00)
MSTS0: Bit 7 of IICA status register 0 (IICS0)
IICA0: IICA shift register 0
IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
tF: SDAA0 and SCLA0 signa l falling times
f
CLK: CPU/peripheral hardware clock frequency
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(2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICF0) = 1)
When bit 1 (STT 0) of IICA control r egister 00 (IICCTL00) is set to 1 when the bus is not used i n a communicati on
during bus communication, this request is rejected and a start condition is not generated. The following two
statuses are included in the status where bus is not used.
• When arbitration results in neither master nor slave operation
• When an extension code is received and slave operation is disabled (ACK is not returned and the bus was
released by setting bit 6 (LREL0) of the IICCTL00 register to 1 and saving communication)
To confirm whether the start condition was generated or request was rejected, check STCF (bit 7 of the IICF0
register). It takes up to 5 clocks until the STCF bit is set to 1 after setting STT0 = 1. Therefore, secure the time by
software.
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12.5.15 Cautions
(1) When STCEN = 0
Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (IICBSY = 1) is recognized
regardless of the actual bus status. When changing from a mode in which no stop c ondition has been detected to
a master device communication mode, first generate a stop condition to release the bus, then perform master
device communication.
When using multiple masters, it is not possible to perform master device communication when the bus has not
been released (when a stop condition has not been detected).
Use the following sequence for gen erating a stop condition.
<1> Set IICA control register 01 (IICCTL01).
<2> Set bit 7 (IICE0) of IICA control register 00 (IICCTL00) to 1.
<3> Set bit 0 (SPT0) of the IICCTL00 regist er to 1.
(2) When STCEN = 1
Immediately after I2C operation is enabled (IICE0 = 1), the bus released status (IICBSY = 0) is recognized
regardless of the actual bus status. To generate the first st art condition (STT0 = 1), it is necessary to confirm that
the bus has been released, so as to not disturb other communications.
(3) If other I2C communications are already in progress
If I2C operation is enabled and the device participates in communication already in progress when the SDAA0 pin
is low and the SCLA0 pin is high, the macro of I2C recognizes that the SDAA0 pin has gone low (detects a start
condition). If the value on the bus at this time can be recognized as an extension code, ACK is returned, but this
interferes with other I2C communications. To avoid this, start I2C in the following sequence.
<1> Clear bit 4 (SPIE0) of the IICCTL00 register to 0 to disable generation of an interrupt request signal
(INTIICA0) when the stop condition is detected.
<2> Set bit 7 (IICE0) of the IICCTL00 register to 1 to enable the operation of I2C.
<3> Wait for detection of the start condition.
<4> Set bit 6 (LREL0) of the IICCTL00 register to 1 before ACK is returned (4 to 80 clocks after setting the IICE0
bit to 1), to forcibly disable detection.
(4) Setting the STT 0 and SPT0 bits (bits 1 and 0 of the IICCTL00 register) again after they are set and before they are
cleared to 0 is prohibited.
(5) When transmission is reserved, set the SPIE0 bit (bit 4 of the IICTL0 register) to 1 so that an interrupt request is
generated when the stop condition is detected. Transfer is started when communication data is written to the IICA
shift register 0 (IICA0) after the interrupt request is generated. Unless the interrupt is generated when the stop
condition is detected, the device stops in the wait state because the interrupt request is not generated when
communication is started. However, it is not necess ary to set the SPIE0 bit to 1 when the MSTS0 bit (bit 7 of the
IICA status register 0 (IICS0)) is detected by software.
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12.5.16 Communication operatio n s
The following shows three operation proced ures with the flowchart.
(1) Master operation in single master system
The flowchart when using the RL78/G12 as the master in a single master system is shown below.
This flowchart is broadly divid ed into the initial settings and communication processin g. Execute the initial settings
at startup. If communication with the slave is required, prepare the communication and then execute
communication processing.
(2) Master operation in multimaster system
In the I2C bus multimaster system, whether the bus is released or used cannot be judged by the I2C bus
specifications when the bus takes part in a communication. Here, when data and clock are at a high level for a
certain period (1 frame), the RL78/G12 takes part in a communication with bus released state.
This flowchart is broadly divided into the initial settings, communication waiting, and communication processing.
The processing when the RL78/G12 looses in arbitration and is specified as t he slave is omitted her e, and only the
processing as the master is shown. Execute the initial settings at startup to take part in a communication. Then,
wait for the communication request as the master or wait for the specification as the slave. The actual
communication is performed in the communication processing, and it supports the transmission/reception with the
slave and the arbitration with other masters.
(3) Slave operation
An example of when the RL78/G12 is used as the I2C bus slave is shown below.
When used as the slave, operation is started by an interrupt. Execute the initial settings at startup, then wait for the
INTIICA0 interrupt occurrence (communication waiting). When an INTIICA0 interrupt occurs, the communication
status is judged and its result is passed as a flag over to the main processing.
By checking the flags, necessary communication processing is performed.
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(1) Master operation in single-master system
Figure 12-28. Master Operatio n in Single-Master System
SPT0 = 1
SPT0 = 1
WREL0 = 1
START
END
ACKE0 = 0
WTIM0 = WREL0 = 1
No
No
Yes
No No
No
Yes
Yes Yes
Yes
STCEN0 = 1?
ACKE0 = 1
WTIM0 = 0
TRC0 = 1?
ACKD0 = 1?
ACKD0 = 1?
No
Yes
No
Yes
Yes
No
Yes
No
Yes
No
Yes
No
Yes
No
STT0 = 1
IICWL0, IICWH0 ← XXH
IICF0 ← 0XH
Setting STCEN0, IICRSV0 = 0
IICCTL00 ← 1XX111XXB
IICE0 = 1
IICCTL00 ← 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
Setting port
Initializing I
2
C bus
Note
SVA0 ← XXH
Writing IICA0
Writing IICA0
Reading IICA0
INTIICA0
interrupt occurs?
End of transfer?
End of transfer?
Restart?
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6
)).
Setting port Set the port from input mode to output mode and enable the output of the I
2
C bus
(see 12.3 (8) Port mode register 6 (PM6)).
Sets a transfer clock.
Sets a local address.
Sets a start condition.
Prepares for starting communication
(generates a start condition).
Starts communication
(specifies an address and transfer
direction).
Waits for detection of acknowledge.
Waits for data transmission.
Starts transmission.
Communication processing
Initial setting
Starts reception.
Waits for data
reception.
INTIICA0
interrupt occurs?
Waits for detection
of acknowledge.
Prepares for starting communication
(generates a stop condition).
Waits for detection of the stop condition.
INTIICA0
interrupt occurs?
INTIICA0
interrupt occurs?
INTIICA0
interrupt occurs?
Setting IICCTL01
Note Release (SCL A0 and SDAA0 pins = high level) the I 2C bus in conform ance with the specifications of the product
that is communicating. If EEPROM is outputting a low level to the SDAA0 pin, for example, set the SCLA0 pin in
the output port mode, and output a clock pulse from the output port until the SDAA0 pin is constantly at high
level.
Remark Conform to the specifications of the product that is communicating, with respect to the transmission and
reception formats.
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(2) Master operation in multi-master system
Figure 12-29. Master Operatio n in Multi-Master System (1/3)
IICWL0, IICWH0 ← XXH
IICF0 ← 0XH
Setting STCEN0 and IICRSV0
Setting port
SPT0 = 1
SVA0 ← XXH
SPIE0 = 1
START
Slave operation
Slave operation
Releases the bus for a specific period.
Bus status is
being checked.
Yes
Checking bus status
Note
Master operation
starts?
Enables reserving
communication. Disables reserving
communication.
SPD0 = 1?
STCEN0 = 1?
IICRSV0 = 0?
A
Selects a transfer clock.
Sets a local address.
Sets a start condition.
(Communication start request)
(No communication start request)
• Waiting to be specified as a slave by other master
• Waiting for a communication start request (depends on user program)
Prepares for starting
communication
(generates a stop condition
).
Waits for detection
of the stop condition.
No
Yes
Yes
No
INTIICA0
interrupt occurs?
INTIICAn
interrupt occurs?
Yes
No Yes
No
SPD0 = 1?
Yes
No
Slave operation
No
INTIICA0
interrupt occurs?
Yes
No
1
B
SPIE0 = 0
Yes
No
Waits for a communication request.
Waits for a communication Initial setting
IICCTL00 ← 1XX111XXB
IICE0 = 1
IICCTL00 ← 0XX111XXB
ACKE0 = WTIM0 = SPIE0 = 1
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6)).
Setting port Set the port from input mode to output mode and enable the output of the I
2
C bus
(see 12.3 (8) Port mode register 6 (PM6)).
Setting IICCTL01
Note Confirm that th e bus is released (CLD0 bit = 1, DAD0 bit = 1) for a specifi c period (for example, for a period of
one frame). If the SDAA0 pin is constantly at low level, decide whether to release the I2C bus (SCLA0 and
SDAA0 pins = high level) in conformance with the specifications of the product that is communicating.
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Figure 12-29. Master Operatio n in Multi-Master System (2/3)
STT0 = 1
Wait
Slave operation
Yes
MSTS0 = 1?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Secure wait time
Note
by software.
Waits for bus release
(communication being reserved).
Wait state after stop condition
was detected and start condition
was generated by the communication
reservation function.
No
INTIICA0
interrupt occurs?
Yes
Yes
No
No
A
C
STT0 = 1
Wait
Note
Slave operation
Yes
IICBSY0 = 0?
EXC0 = 1 or COI0 =1?
Prepares for starting communication
(generates a start condition).
Disables reserving communication.
Enables reserving communication.
Waits for bus release
Detects a stop condition.
No
No
INTIICA0
interrupt occurs?
Yes
Yes
No
Yes
STCF0 = 0? No
B
D
C
D
Communication processing Communication processing
Note The wait time is calculated as follows.
(IICWL0 setting valu e + IICWH0 setting value + 4) × fCLK + tF × 2 [clocks]
Remark IICWL0: IICA low-level width setting register 0
IICWH0: IICA high-level width setting register 0
tF: SDAA0 and SCLA0 signal falling times
f
CLK: CPU/peripheral hardware clock frequency
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Figure 12-29. Master Operatio n in Multi-Master System (3/3)
Writing IICA0
WTIM0 = 1
WREL0 = 1
Reading IICA0
ACKE0 = 1
WTIM0 = 0
WTIM0 = WREL0 = 1
ACKE0 = 00
Writing IICA0
Yes
TRC0 = 1?
Restart?
MSTS0 = 1?
Starts communication
(specifies an address and transfer direction).
Starts transmission.
No
Yes
Waits for data reception.
Starts reception.
Yes
No
INTIICA0
interrupt occurs?
Yes
No
Transfer end?
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Waits for data transmission.
Does not participate
in communication.
Yes
No
INTIICA0
interrupt occurs?
No
Yes
ACKD0 = 1?
No
Yes
No
C
2
Yes
MSTS0 = 1? No
Yes
Transfer end?
No
Yes
ACKD0 = 1? No
2
Yes
MSTS0 = 1? No
2
Waits for detection of ACK.
Yes
No
INTIICA0
interrupt occurs?
Yes
MSTS0 = 1? No
C
2
Yes
EXC0 = 1 or COI0 = 1? No
1
2
SPT0 = 1
STT0 = 1
Slave operation
END
Communication processingCommunication processing
Remarks 1. Conform to the specificati ons of the product that is communicating, with respect to the transmission and
reception formats.
2. To use the devi ce as a master in a multi-master s ystem, read the MSTS0 bit each tim e interrupt INTIICA0
has occurred to check the arbitration result.
3. To use the device as a slave in a multi-master s ystem, check the status by using the IICA status register
0 (IICS0) and IICA flag register 0 (IICF0) each time interrupt INTIICA0 has occurred, and determine the
processing to be performed next.
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(3) Slave operation
The processing procedure of the slave operation is as follows.
Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that
must substantially change the operation status such as detection of a stop condition during communication) is
necessary.
In the following explanation, it is assumed that the extension code is not supported for data communication. It is
also assumed that the INTIICA0 interrupt servicing only performs status transition proc essing, and that actual data
communication is performed by the main processing.
IICA
Interrupt servicing
Main processing
INTIICA0 Flag
Setting
Data
Setting
Therefore, data communication processing i s performed by pr eparing the follo wing three flags and passing them to
the main processing instead o f INT IICA0.
<1> Communication mode flag
This flag indicates the following two communication statuses.
• Clear mode: Status in which data communication is not performed
• Communication mode: Status in which data communication is performed (from valid address detection to
stop condition detection, no detection of ACK from master, address mismatch)
<2> Ready flag
This flag indicates that data communic ation is enabled. Its function is the same as the INT IICA0 interrupt for
ordinary data communication. This flag is set by interrupt servicing and cleared by the main processing.
Clear this flag by interrupt servicing when communication is started. However, the ready flag is not set by
interrupt servicing when the first data is transmitted. Therefore, the first data is transmitted without the flag
being cleared (an address match is interpreted as a request for the next data).
<3> Communication direction flag
This flag indicates the direction of communication. Its value is the same as the TRC0 bit.
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The main processing of the slave operation is explained next.
Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute
communication by using the communication mode flag and ready flag (processing of the stop condition and start
condition is performed by an interrupt. Here, check the status by using the flags).
The transmission operation is repeated until the master no longer returns ACK. If ACK is not returned from the
master, communication is complete d.
For reception, the necessary amou nt of data is received. When communication is completed, ACK is not returned
as the next data. After that, the master generates a stop condition or restart condition. Exit from the
communication status occurs in this way.
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Figure 12-30. Slave Operation Flowchart (1)
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
WREL0 = 1
ACKD0 = 1?
No
Yes
No
Yes
No
START
Communication
mode flag = 1?
Communication
mode flag = 1?
Communication
direction flag = 1?
Ready flag = 1?
Communication
direction flag = 1?
Reading IICA0
Clearing ready flag
Clearing ready flag
Communication
direction flag = 1?
Clearing communication
mode flag
WREL0 = 1
Writing IICA0
SVA0 ← XXH Sets a local address.
IICWL0, IICWH0 ← XXH Selects a transfer clock.
IICF0 ← 0XH
Setting IICRSV0 Sets a start condition.
Starts
transmission.
Starts
reception.
Communication
mode flag = 1?
Ready flag = 1?
Setting port
Setting port
Communication processing
Initial setting
Setting of the port used alternatively as the pin to be used.
First, set the port to input mode and the output latch to 0 (see 12.3 (8) Port mode register 6 (PM6
)).
Set the port from input mode to output mode and enable the output of the I
2
C bus
(see 12.3 (8) Port mode register 6 (PM6)).
IICCTLn0 ← 0XX011XXB
ACKE0 = WTIM0 = 1, SPI0 = 0
IICCTL00 ← 1XX011XXB
IICE0 = 1
Setting IICCTL01
Remark Conform to the specifications of the product that is in communication, regarding the transmission and
reception formats.
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An example of the processing proced ure of the slave with the INTIICA0 interrupt is expla ined below (processing is
performed assuming that no extensi on code is used). The INTIICA0 interrupt checks the status, and the following
operations are performed.
<1> Communication is stopped if the stop condition is issued.
<2> If the start condition is issued, the address is checked and communication is completed if the address does
not match. If the address matches, the communication mode is set, wait is cancelled, and processi ng returns
from the interrupt (the ready flag is cleared).
<3> For data transmit/receive, only the ready flag is set. Processing returns from the interrupt with the I2C bus
remaining in the wait state.
Remark <1> to <3> above correspond to <1> to <3> in Figure 12-31 Slave Operation Flowchart (2).
Figure 12-31. Slave Operation Flowchart (2)
Yes
Yes
Yes
No
No
No
INTIICA0 generated
Set ready flag
Interrupt servicing completed
SPD0 = 1?
STD0 = 1?
COI0 = 1?
Communication direction flag
← TRC0
Set communication mode flag
Clear ready flag
Clear communication direction
flag, ready flag, and
communication mode flag
<1>
<2>
<3>
12.5.17 Timing of I2C interrupt request (INTIICA0) occurrence
The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the
IICA status register 0 (IICS0) when the INTIICA0 signal is generated are shown below.
Remark ST: Start condition
AD6 to AD0: Address
R/W: Transfer direction specification
ACK: Acknowledge
D7 to D0: Data
SP: Stop condition
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(1) Master device operation
(a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B
3: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note
4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)Note
5: IICS0 = 00000001B
Note To generate a stop cond ition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B
3: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Ad dress ~ Data ~ Stop (restart)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓SPT0 = 1
↓
3 4 7 2 1 5 6
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 1
3: IICS0 = 1000××00B (Clears the WT IM0 bit to 0Note 2, sets the STT0 bit to 1)
4: IICS0 = 1000×110B
5: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)Note 3
6: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
7: IICS0 = 00000001B
Notes 1. To generate a start condition, set the WTIM0 bit to 1 and change the timing for generating the
INTIICA0 interrupt request signal.
2. Clear th e WTIM0 bit to 0 to restore the original setting.
3. To generate a stop condition, set the WTIM0 bit to 1 and change the timing for generating the
INTIICA0 interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
STT0 = 1
↓SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets the STT0 bit to 1)
3: IICS0 = 1000×110B
4: IICS0 = 1000××00B (Sets the SPT0 bit to 1)
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Code ~ Data ~ Data ~ Stop (extension co de transmission)
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×000B
3: IICS0 = 1010×000B (Sets the WTIM0 bit to 1)Note
4: IICS0 = 1010××00B (Sets the SPT0 bit to 1)
5: IICS0 = 00000001B
Note To generate a stop cond ition, set the WTIM0 bit to 1 and change the timing for generating the INTIICA0
interrupt request signal.
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1010×110B
2: IICS0 = 1010×100B
3: IICS0 = 1010××00B (Sets the SPT0 bit to 1)
4: IICS0 = 00001001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(2) Slave device operation (slave address data reception)
(a) Start ~ Address ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3
4
2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Address ~ Data ~ Start ~ Ad dress ~ Data ~ Stop
(i) Wh en WTIM0 = 0 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, matches with SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0001×110B
4: IICS0 = 0001××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= extensio n code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, does not match address (= extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 5 6 2 1 4
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 0010×010B
4: IICS0 = 0010×110B
5: IICS0 = 0010××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(d) Start ~ Address ~ Data ~ Start ~ Ad dress ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= no t extensio n code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001×000B
3: IICS0 = 00000×10B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0001×110B
2: IICS0 = 0001××00B
3: IICS0 = 00000×10B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(3) Slave device operation (when receiving extension code)
The device is al ways participating in communication when it receives an extension code.
(a) Start ~ Code ~ Data ~ Data ~ Stop
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0001×110B
4: IICS0 = 0001×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, matches SVA0)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 6 2 1 5
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0001×110B
5: IICS0 = 0001××00B
6: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×010B
4: IICS0 = 0010×000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, extension code reception)
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 7 2 1 5 6
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 0010×010B
5: IICS0 = 0010×110B
6: IICS0 = 0010××00B
7: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop
(i) When WTIM0 = 0 (after restart, does not match address (= no t extensio n code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×000B
3: IICS0 = 00000×10B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WT IM0 = 1 (after restart, does not match address (= not extension code))
ST AD6 to AD0 R/W ACK D7 to D0 AD6 to AD0ACK ACK SPST R/W D7 to D0 ACK
3 4 5 2 1
1: IICS0 = 0010×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010××00B
4: IICS0 = 00000×10B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(4) Operation without communication
(a) Start ~ Code ~ Data ~ Data ~ Stop
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
1
1: IICS0 = 00000001B
Remark : Generated only when SPIE0 = 1
(5) Arbitration loss operation (operation as slave after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIICA0 has occurred to check the a r bitration result.
(a) When arbitration loss occurs during transmission of slave address data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×000B
3: IICS0 = 0001×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0101×110B
2: IICS0 = 0001×100B
3: IICS0 = 0001××00B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(b) When arb itration loss occurs during transmission of extension code
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×000B
3: IICS0 = 0010×000B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 4 5 2 1
1: IICS0 = 0110×010B
2: IICS0 = 0010×110B
3: IICS0 = 0010×100B
4: IICS0 = 0010××00B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(6) Operation when arbitration loss occurs (no communication after arbitration loss)
When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request
signal INTIICA0 has occurred to check the a r bitration result.
(a) When arbitration loss occurs during transmission of slave address data (when WTIM0 = 1)
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 01000110B
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
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(b) When arb itration loss occurs during transmission of extension code
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
2 1
1: IICS0 = 0110×010B
Sets LREL0 = 1 by software
2: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(c) W h en arbitration loss occurs during transmission of data
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000000B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
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(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK ACK SP
3 2 1
1: IICS0 = 10001110B
2: IICS0 = 01000100B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
(d) When loss occurs due to restart condition during data transfer
(i) Not extension code (Example: unmatches with SVA0)
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01000110B
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
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(ii) Extension code
ST AD6 to AD0 R/W ACK D7 to Dn AD6 to AD0 ACK SPST R/W D7 to D0 ACK
3 2 1
1: IICS0 = 1000×110B
2: IICS0 = 01100010B
Sets LREL0 = 1 by software
3: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
(e) When loss occurs due to stop condition during data transfer
ST AD6 to AD0 R/W ACK D7 to Dn SP
2
1
1: IICS0 = 10000110B
2: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
n = 6 to 0
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(f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
3: IICS0 = 1000×100B (Clears the W T IM0 bit to 0)
4: IICS0 = 01000000B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets the STT0 bit to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
3: IICS0 = 1000××00B (Sets the STT0 bit to 1)
4: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 ACK SP
STT0 = 1
↓
2 3 1
1: IICS0 = 1000×110B
2: IICS0 = 1000××00B (Sets the STT0 bit to 1)
3: IICS0 = 01000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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(h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition
(i) When WTIM0 = 0
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 5 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×000B (Sets the WTIM0 bit to 1)
3: IICS0 = 1000×100B (Clears the W T IM0 bit to 0)
4: IICS0 = 01000100B
5: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
(ii) When WTIM0 = 1
ST AD6 to AD0 R/W ACK D7 to D0 D7 to D0ACK SPACK D7 to D0 ACK
SPT0 = 1
↓
3 4 2 1
1: IICS0 = 1000×110B
2: IICS0 = 1000×100B (Sets the SPT0 bit to 1)
3: IICS0 = 01000100B
4: IICS0 = 00000001B
Remark : Always generated
: Generated only when SPIE0 = 1
×: Don’t care
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12.6 Timing Charts
When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave
devices as its communication partner.
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICS0)),
which specifies the data transfer directio n, and then starts serial communication with the slave device.
Figures 12-32 and 12-33 sho w timing charts of the data communication.
The IICA shift register 0 (IICA0)’s shift operation is s ynchronized with the falling e dge of the serial clock (SCLA0). The
transmit data is transferred to the SO latch and is output (MSB first) via the SDAA0 pin.
Data input via the SDAA0 pin is captured into IICA0 at the rising edge of S CLA0.
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Figure 12-32. Example of Master to Slave Communication
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/4)
(1) Start condition ~ address ~ data
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
W
ACK
<2>
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
Master side
Bus line
Slave side Slave address
L
L
H
L
H
H
H
L
AD5 AD4 AD3 AD2 AD1 AD0
WTIM0
(8 or 9 clock wait)
Note 1
Start condition
D17
AD6
Note 2
Note 3
<5>
<1>
<4>
<3>
<6>
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write dat a to IICA0, not setting the WREL0 bi t, in order to cancel a w ait st a te during transmi ssion by a master
device.
2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is
at least 4.0
μ
s when specifying standard mode and at least 0.6
μ
s when specifying fast mode.
3. For releasi ng wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
The meanings of <1> to <6> in (1) Start condition ~ address ~ data in Figure 12- 32 are explained below.
<1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (SDAA0 = 0 and
SCLA0 = 1) is generated once the bus data line goes low (SDAA0 = 0). When the start condition is
subsequently detected, the master device enters the master device communication status (MSTS0 = 1).
The master device is ready to communicate once the bus clock line goes low (SCLA0 = 0) after the hold
time has elapsed.
<2> T he master device writes the address + W (transmission) to the IICA shift register 0 (IICA0) and transmits
the slave address.
<3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that
slave device sends an ACK by hard ware to the master device. The ACK is detected by the master device
(ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INT IICA0: end of address transmis sion) at the fall i ng edge of the 9th
clock. The slave device whose address matched the transmitted slave ad dress sets a wait status (SCLA0 =
0) and issues an interrupt (INTIICA0: address match)Note.
<5> The master device writes the data to transmit to the IICA0 register and releases the wait status that it set by
the master device.
<6> If the slave device releases the wait status (WREL0 = 1), the master device starts transferring data to the
slave device.
Note If the transmitted a ddress does not match the address of the slave device, the slav e device does not r eturn
an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0
interrupt (address match) and do es not set a wait status. The master device, ho wever, issues the INT IICA0
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <15> in Figure 12-32 following descriptions the entire procedure for communicating data using
the I2C bus.
Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
Figure 12-32. Example of Master to Slave Communication
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/4)
(2) Address ~ data ~ data
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
W ACK
Master side
Bus line
Slave side
H
H
L
H
L
L
L
H
H
L
L
D16 D15 D14 D13 D12 D11 D10
D17 D27
ACK
H
Note 2 <10>
<6>
<7>
<8>
<3>
<4>
Note 1 Note 1
<9>
<5>
Note 2
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a
master device.
2. For releasi ng wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
The meanings of <3> to <10> in (2) Address ~ data ~ data in Figure 12-32 are explained below.
<3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that
slave device sends an ACK by hard ware to the master device. The ACK is detected by the master device
(ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INT IICA0: end of address transmis sion) at the fall i ng edge of the 9th
clock. The slave device whose address matched the transmitted slave ad dress sets a wait status (SCLA0 =
0) and issues an interrupt (INTIICA0: address match)Note.
<5> The master device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait
status that it set by the master device.
<6> If the slave device releases the wait status (WREL0 = 1), the master device starts transferring data to the
slave device.
<7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the
master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edg e of the 9th clock.
<8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<9> The master device writes the data to transmit to the IICA0 register and releases the wait status that it set by
the master device.
<10> The slave device reads the received data and releases the wait status (WREL0 = 1). The master device
then starts transferring data to the slave device.
Note If the transmitted a ddress does not match the address of the slave device, the slav e device does not r eturn
an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0
interrupt (address match) and do es not set a wait status. The master device, ho wever, issues the INT IICA0
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <15> in Figure 12-32 following descriptions the entire procedure for communicating data using
the I2C bus.
Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
Figure 12-32. Example of Master to Slave Communication
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
(3) Data ~ data ~ Stop condition
Master side
D161
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
D162
D163D164D165D160D166
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
D150
D167
Bus line
Slave side
L
L
H
H
L
L
H
H
L
ACK ACK
Note 1
Stop condition
<14>
<9>
Note 2
<8> <12>
<7> <11> <15>
<10> <13>
Note 3 Note 3
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Write dat a to IICA0, not setting the WREL0 bi t, in order to cancel a w ait st a te during transmi ssion by a master
device.
2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop
condition after a stop condition has been issued is at least 4.0
μ
s when specifying standard mode and
at least 0.6
μ
s when specifying fast mode.
3. For releasi ng wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
The meanings of <7> to <15> in (3) Data ~ data ~ stop condition in Figure 12-32 are explained below.
<7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the
master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edg e of the 9th clock.
<8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<9> The master device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait
status that it set by the master device.
<10> The slave device reads the received data and releases the wait status (WREL0 = 1). The master device
then starts transferring data to the slave device.
<11> When data transfer is complete, the slave device (ACKE0 =1) sends an ACK by hardware to the master
device. The ACK is detected by the master device (ACKD0 = 1) at the rising edge of the 9th clock.
<12> T he master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<13> The slave device reads the received data and releases the wait status (WREL0 = 1).
<14> By the master device s etting a stop condition trigger (SPT0 = 1), the bus data line is cleared (S DAA0 = 0)
and the bus clock line is set (SCLA0 = 1). After the stop condition setup time has elapsed, by setting the
bus data line (SDAA0 = 1), the stop condition is then generated (i.e. SC LA0 =1 changes SDAA0 from 0 to
1).
<15> When a stop condition is generated, the slave device detects the stop condition and issues an interrupt
(INTIICA0: stop condition).
Remark <1> to <15> in Figure 12-32 represent the entire procedure for communicating data using the I2C bus.
Figure 12-32 (1) Start condition ~ address ~ data shows the processing from <1> to <6>, Figure 12-32
(2) Address ~ data ~ data shows the processing from <3> to <10>, and Figure 12-32 (3) Data ~ data ~
stop condition shows the processing from <7> to <15>.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
R01UH0200EJ0110 Rev.1.10 573
Sep. 28, 2012
Figure 12-32. Example of Master to Slave Communication
(9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (4/4)
(4) Data ~ restart condition ~ address
L
H
L
H
L
H
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
AD6
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
Master side
Bus line
Slave side Slave address
D
1
3 ACK
<i>
L
H
H
L
H
Restart condition
D
1
2 D
1
1 D
1
0 AD5 AD4 AD3 AD2
AD1
<ii>
<iii>
<7>
<8>
Note 2
Note 1
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the start
condition after a restart condition has been is sued is at least 4.7
μ
s when specifying standard mod e and
at least 0.6
μ
s when specifying fast mode.
2. For releasi ng wait state during reception of a slave device, write “FFH” to IICA0 or set the WREL0 bit.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
The following describes the operations in F igure 12-32 (4) Data ~ restart condition ~ address. After the operations
in steps <7> and <8>, the operations in steps <1> to <3> are performed. These steps return the processing to step
<3>, the data transmission step.
<7> After data transfer is completed, because of ACKE0 = 1, the slave device sends an ACK by hardware to the
master device. The ACK is detected by the master device (ACKD0 = 1) at the rising edg e of the 9th clock.
<8> The master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<i> The slave devic e reads the received data and releases the wait status (WREL0 = 1).
<ii> The start condition trigger is set again b y the master dev ice (ST T 0 = 1) and a start condition (i.e. SCLA 0 =1
changes SDAA0 from 1 to 0) i s generated once the bus cloc k line goes hig h (SCLA0 = 1) and th e bus data
line goes low (SDAA0 = 0) after the restart condition setup time has elapsed. When the start condition is
subsequently detected, the master device is ready to communicate once the bus clock line goes low
(SCLA0 = 0) after the hold time has elapsed.
<iii> The master device writing the address + R/W (transmission) to the IICA shift register (IICA0) enables the
slave address to be transmitted.
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Sep. 28, 2012
Figure 12-33. Example of Slave to Master Communication
(8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (1/3)
(1) Start condition ~ address ~ data
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(A CK detection)
WTIM0
(8 or 9 cl ock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
AD6 D
1
7
R ACK
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
Master side
Bus line
Slave side Slave address
L
L
H
H
H
L
AD5 AD4 AD3 AD2 AD1 AD0
Start condition
Note 2
Note 1
Note 3
<2>
<5>
<1>
<7>
<3>
<4>
<6>
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. For releasing wait state during reception of a master device, write “FFH” to IICA0 or set the WREL0 bit.
2. Make sure that the time between the fall of the SDAA0 pin signal and the fall of the SCLA0 pin signal is
at least 4.0
μ
s when specifying standard mode and at least 0.6
μ
s when specifying fast mode.
3. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a
slave device.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
R01UH0200EJ0110 Rev.1.10 576
Sep. 28, 2012
The meanings of <1> to <7> in (1) Start condition ~ address ~ data in Figure 12- 33 are explained below.
<1> The start condition trigger is set by the master device (STT0 = 1) and a start condition (i.e. SCLA0 =1
changes SDAA0 from 1 to 0) is generated once the bus data line goes low (SDAA0). When the start
condition is subsequently detected, the master device enters the master device communication status
(MSTS0 = 1). The master device is ready to communicate once the bus clock line goes low (SCLA0 = 0)
after the hold time has elapsed.
<2> T he master device writes the address + R (reception) to the IICA shift register 0 (IICA0) and transmits the
slave address.
<3> In the slave device if the address received matches the address (SVA0 value) of a slave device Note, that
slave device sends an ACK by hard ware to the master device. The ACK is detected by the master device
(ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INT IICA0: end of address transmis sion) at the fall i ng edge of the 9th
clock. The slave device whose address matched the transmitted slave ad dress sets a wait status (SCLA0 =
0) and issues an interrupt (INTIICA0: address match) Note.
<5> The timing at which the master device sets the wait status changes to the 8th clock (WTIM0 = 0).
<6> The slave device writes the data to transmit to the IICA0 register and releases the wait status that it set by
the slave device.
<7> The master device releases t he wait status (WREL0 = 1) and starts transferring data from the slave device
to the master device.
Note If the transmitted a ddress does not match the address of the slave device, the slav e device does not r eturn
an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0
interrupt (address match) and do es not set a wait status. The master device, ho wever, issues the INT IICA0
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using
the I2C bus.
Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
R01UH0200EJ0110 Rev.1.10 577
Sep. 28, 2012
Figure 12-33. Example of Slave to Master Communication
(8-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (2/3)
(2) Address ~ data ~ data
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
IICA0
STD0
(ST detection)
SPD0
(SP dete ction)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication statu s)
TRC0
(transmit/receive)
WREL0
(wait cancella ti on)
INTIICA0
(interrupt)
R ACK ACK
Master side
Bus line
Slave side
H
H
L
H
L
L
H
L
H
L
L
D
1
7 D
1
6D
1
5D
1
4D
1
3D
1
2D
1
1D
1
0D
2
7
Note 1 Note 1
<5>
<7> <9>
Note 2 Note 2
<4> <8> <11>
<10>
<12>
<6>
<3>
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. For releasing wait state during reception of a master device, write “FFH” to IICA0 or set the WREL0 bit.
2. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during transmission by a
slave device.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
The meanings of <3> to <12> in (2) Address ~ data ~ data in Figure 12-33 are explained below.
<3> In the slave device if the address received matches the address (SVA0 value) of a slave deviceNote, that
slave device sends an ACK by hard ware to the master device. The ACK is detected by the master device
(ACKD0 = 1) at the rising edge of the 9th clock.
<4> The master device issues an interrupt (INT IICA0: end of address transmis sion) at the fall i ng edge of the 9th
clock. The slave device whose address matched the transmitted slave ad dress sets a wait status (SCLA0 =
0) and issues an interrupt (INTIICA0: address match)Note.
<5> The master device changes the timing of the wait status to the 8th clock (WTIM0 = 0).
<6> The slave device writes the data to transmit to the IICA shift register 0 (IICA0) and releases the wait status
that it set by the slave device.
<7> The master device releases t he wait status (WREL0 = 1) and starts transferring data from the slave device
to the master device.
<8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICA0: end of transfer). Because of ACKE0 = 1 in the master device, the master device then
sends an ACK by hardware to the slave device.
<9> The master device reads the receive d data and releases th e wait status (WREL0 = 1).
<10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device
issue an interrupt (INTIICA0: end of transfer).
<12> By the slave device writing the data to transmit to the IICA0 register, the wait status set by the slave device
is released. The slave device then starts transferring data to the master device.
Note If the transmitted a ddress does not match the address of the slave device, the slav e device does not r eturn
an ACK to the master device (NACK: SDAA0 = 1). The slave device also does not issue the INTIICA0
interrupt (address match) and do es not set a wait status. The master device, ho wever, issues the INT IICA0
interrupt (end of address transmission) regardless of whether it receives an ACK or NACK.
Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using
the I2C bus.
Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
RL78/G12 CHAPTER 12 SERIAL INTERFACE IICA
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Sep. 28, 2012
Figure 12-33. Example of Slave to Master Communication
(8-Clock and 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/3)
(3) Data ~ data ~ stop condition
IICA0
STT0
(ST trigger)
SPT0
(SP trigger)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication status)
TRC0
(transmit/receive)
SCLA0 (bus)
(clock line)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
SDAA0 (bus)
(data line)
IICA0
STD0
(ST detection)
SPD0
(SP detection)
ACKD0
(ACK detection)
WTIM0
(8 or 9 clock wait)
ACKE0
(ACK control)
MSTS0
(communication
status)
TRC0
(transmit/receive)
WREL0
(wait cancellation)
INTIICA0
(interrupt)
D
15
0
Master side
Bus line
Slave side
H
L
H
L
L
L
ACK NACK
D
16
7D
16
6D
16
5D
16
4D
16
3D
16
2D
16
1D
16
0
Stop conditon
Note 1 Note 1
Note 3
N ote 2
Notes 1, 4
Note 4
<14>
<9>
<8> <11>
<10>
<12>
<13> <16>
<19>
<15>
<17>
<18>
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
Notes 1. To cancel a wait state, write “FFH” to IICA0 or set the WREL0 bit.
2. Make sure that the time between the rise of the SCLA0 pin signal and the generation of the stop
condition after a stop condition has been iss ued is at least 4.0
μ
s when specifying standard mode and at
least 0.6
μ
s when specifying fast mode.
3. Write data to IICA0, not setting the WREL0 bit, in order to cancel a wait state during slave transmissio n.
4. If a wait state during transmission by a slave device is can celed by setting the WREL0 bit, the TRC0 bit
will be cleared.
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The meanings of <8> to <19> in (3) Data ~ data ~ stop condition in Figure 12-33 are explained below.
<8> The master device sets a wait status (SCLA0 = 0) at the falling edge of the 8th clock, and issues an
interrupt (INTIICA0: end of transfer). Because of ACKE0 = 0 in the master device, the master device then
sends an ACK by hardware to the slave device.
<9> The master device reads the receive d data and releases th e wait status (WREL0 = 1).
<10> The ACK is detected by the slave device (ACKD0 = 1) at the rising edge of the 9th clock.
<11> The slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and the slave device
issue an interrupt (INTIICA0: end of transfer).
<12> B y the slave device writing the data to transmit to the IICA register, the wait status set by the slave device is
released. The slave device then starts transferring data to the master device.
<13> The master device issues an interrupt (INTIICA0: end of transfer) at the falling edge of the 8th clock, and
sets a wait status (SCLA0 = 0). Because ACK control (ACKE0 = 1) is performed, the bus data line is at the
low level (SDAA0 = 0) at this stage.
<14> The master device sets NACK as the response (ACKE0 = 0) and changes the timing at which it sets the
wait status to the 9th clock (WTIM0 = 1).
<15> If the master device releases the wait status (WREL0 = 1), the slave device detec ts the NACK (ACK = 0) at
the rising edge of the 9th clock.
<16> T he master device and slave device set a wait status (SCLA0 = 0) at the falling edge of the 9th clock, and
both the master device and slave device issue an interrupt (INTIICA0: end of transfer).
<17> When the master devic e issues a stop condition (SPT0 = 1), the bu s data line is cleared (SDAA0 = 0) and
the master device releases the wait status. The master device then waits until the bus clock line is set
(SCLA0 = 1).
<18> The slave device acknowled ges the NACK, halts transmission, and releas es the wait status (WREL0 = 1) to
end communication. Once the slave device releases the wait status, the bus clock line is set (SCLA0 = 1).
<19> Once the master device recognizes that the bus clock line is set (SCLA0 = 1) and after the stop condition
setup time has elapsed, the master device sets the bus data line (SDAA0 = 1) and issues a stop condition
(i.e. SCLA0 =1 changes SDAA0 from 0 to 1). The slave device detects the generated stop condition and
slave device issue an interrupt (INTIICA0: stop condition).
Remark <1> to <19> in Figure 12-33 following descriptions the entire procedure for communicating data using
the I2C bus.
Figure 12-33 (1) Start condition ~ address ~ data shows the processing from <1> to <7>, Figure 12-33
(2) Address ~ data ~ data shows the processing from <3> to <12>, and Figure 12-33 (3) Data ~ data ~
stop condition shows the processing from <8> to <19>.
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CHAPTER 13 MULTIPLIER AND DIVIDER/MULTIPLY-ACCUMULATOR
13.1 Functions of Multiplier and Divider/Multiply-Accumulator
The multiplier and divider/multiply-accumulator has the following functions.
• 16 bits × 16 bits = 32 bits (Unsigned)
• 16 bits × 16 bits = 32 bits (Signed)
• 16 bits × 16 bits + 32 bits = 32 bits (Unsigned)
• 16 bits × 16 bits + 32 bits = 32 bits (Signed)
• 32 bits ÷ 32 bits = 32 bits, 32-bits remainder (Unsigned)
13.2 Configuration of Multiplier and Divider/Multiply-Accumulator
The multiplier and divider/multiply-accumulator consists of the following hard ware.
Table 13-1. Configuration of Multiplier and Divider/Multiply-Accumulator
Item Configuration
Registers Multiplication/division data register A (L) (MDAL)
Multiplication/division data register A (H) (MDAH)
Multiplication/division data register B (L) (MDBL)
Multiplication/division data register B (H) (MDBH)
Multiplication/division data register C (L) (MDCL)
Multiplication/division data register C (H) (MDCH)
Control register Multiplication/division control register (MDUC)
Figure 13-1 shows a block diagram of the m ultiplier and divider/multiply-accumulator.
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Figure 13-1. Block Diagram of Multiplier and Divider/Multiply-Accumulator
f
PRS
MDCH MDCL
MDSM
DIVMODE
MACMODE
DIVST
INTMD
MDAH MDAL
MDBH MDBL
MACSFMACOF
Multiplication result (product) or
multiplication result (product) while in
multiply-accumulator mode
Multiplication/division data register B
Divisor
Controller Controller
Multiplier Dividend
Multiplication/division block
Controller
Accition block
Multiplicand
Multiplication/division data register A
Division result
(quotient)
Multiply-
accumulation
result
(accumulated)
Division
result
(remainder)
Internal bus
Multiplication/division
control register (MDUC)
Start
Clear
Counter
Data flow during division
Data flow during multiplication and multiply-accumulation
Multiplication/division data register C
(1) Multiplication/division data register A (MDAH, MDAL)
The MDAH and MDAL registers set the values that are used for a multiplication or divis ion operation and store the
operation result. They set the multiplier and multiplicand data in the multiplication mode or multiply-accumulator
mode, and set the dividend d ata in the division mode. Furthermore, the operation result (quotient) is stored in the
MDAH and MDAL registers in the division mode.
The MDAH and MDAL registers can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 13-2. Format of Multiplication/Division Data Register A (MDAH, MDAL)
FFFF3H FFFF2H
MDAH MDAH
15
MDAH
14
MDAH
13
MDAH
12
MDAH
11
MDAH
10
MDAH
9
MDAH
8
MDAH
7
MDAH
6
MDAH
5
MDAH
4
MDAH
3
MDAH
2
MDAH
1
MDAH
0
FFFF1H FFFF0H
MDAL MDAL
15
MDAL
14
MDAL
13
MDAL
12
MDAL
11
MDAL
10
MDAL
9
MDAL
8
MDAL
7
MDAL
6
MDAL
5
MDAL
4
MDAL
3
MDAL
2
MDAL
1
MDAL
0
Address: FFFF0H, FFFF1H, FFFF2H, FFFF3H After reset: 0000H, 0000H R/W
Symbol
Symbol
Cautions 1. Do not rewrite the MDAH and MDAL registers values during division processing (when the
multiplication/division control register (MDUC) value is 81H or C1H). The operation will be
executed in this case, but the operation result will be an undefined value.
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2. The MDAH and MDAL registers values read during division processing (when the MDUC
register value is 81H or C1H) will not be guaranteed.
3. The data is in the two's complement format in either the multiplication mode (signed) or
multiply-accumulator mode (signed).
The following table shows the functions of the MDAH and MDAL registers during operation execution.
Table 13-2. Functions of MDAH and MDAL Registers During Operation Execu tion
Operation Mode Setting Operation Result
Multiplication mode (unsigned)
Multiply-accumulator mode (unsigned) MDAH: Multiplier (unsigned)
MDAL: Multiplicand (unsigned)
−
Multiplication mode (signed)
Multiply-accumulator mode (signed) MDAH: Multiplier (signed)
MDAL: Multiplicand (signed)
−
Division mode (unsigned) MDAH: Dividend (higher 16 bits)
MDAL: Dividend (lower 16 bits) MDAH: Division result (quotient)
Higher 16 bits
MDAL: Division result (quotient)
Lower 16 bits
(2) Multiplication/division data register B (MDBL, MDBH)
The MDBH and MDBL registers set the values that are used for multiplication or division operation and store the
operation result. They store the operation result (product) in the multiplication mode and multiply-accumulator
mode, and set the divisor data in the division mode.
The MDBH and MDBL registers can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 13-3. Format of Multiplication/Division Data Register B (MDBH, MDBL)
Address: FFFF4H, FFFF5H, FFFF6H, FFFF7H After reset: 0000H, 0000H R/W
Symbol FFFF7H FFFF6H
MDBH MDBH
15
MDBH
14
MDBH
13
MDBH
12
MDBH
11
MDBH
10
MDBH
9
MDBH
8
MDBH
7
MDBH
6
MDBH
5
MDBH
4
MDBH
3
MDBH
2
MDBH
1
MDBH
0
Symbol FFFF5H FFFF4H
MDBL MDBL
15
MDBL
14
MDBL
13
MDBL
12
MDBL
11
MDBL
10
MDBL
9
MDBL
8
MDBL
7
MDBL
6
MDBL
5
MDBL
4
MDBHL
3
MDBL
2
MDBL
1
MDBL
0
Cautions 1. Do not rewrite the MDBH and MDBL registers values during division processing (when the
multiplication/division control register (MDUC) value is 81H or C1H) or multiply-accumulation
processing. The operation result will be an undefined value.
2. Do not set the MDBH and MDBL registers to 0000H in the division mode. If they are set, the
operation result will be an undefined value.
3. The data is in the two's complement format in either the multiplication mode (signed) or
multiply-accumulator mode (signed).
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The following table shows the functions of the MDBH and MDBL registers during operation execution.
Table 13-3. Functions of MDBH and MDBL Registers During Operation Execution
Operation Mode Setting Operation Result
Multiplication mode (unsigned)
Multiply-accumulator mode (unsigned)
− MDBH: Multiplication result (product) (unsigned)
Higher 16 bits
MDBL: Multiplication result (product) (unsigned)
Lower 16 bits
Multiplication mode (signed)
Multiply-accumulator mode (signed)
− MDBH: Multiplication result (product) (signed)
Higher 16 bits
MDBL: Multiplication result (product) (signed)
Lower 16 bits
Division mode (unsigned) MDBH: Divisor (higher 16 bits)
MDBL: Divisor (lower 16 bits)
−
(3) Multiplication/division data register C (MDCL, MDCH)
The MDCH and MDCL registers are used to store the accumulated result while in the multiply-accumulator mode or
the remainder of the operation result while in the division mode. These registers are not used while in the
multiplication mode.
The MDCH and MDCL registers can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Figure 13-4. Format of Multiplication/Division Data Register C (MDCH, MDCL)
Address: F00E0H, F00E1H, F00E2H, F00E3H After reset: 0000H, 0000H R/W
F00E3H F00E2H
MDCH MDCH
15
MDCH
14
MDCH
13
MDCH
12
MDCH
11
MDCH
10
MDCH
9
MDCH
8
MDCH
7
MDCH
6
MDCH
5
MDCH
4
MDCH
3
MDCH
2
MDCH
1
MDCH
0
F00E1H F00E0H
MDCL MDCL
15
MDCL
14
MDCL
13
MDCL
12
MDCL
11
MDCL
10
MDCL
9
MDCL
8
MDCL
7
MDCL
6
MDCL
5
MDCL
4
MDCL
3
MDCL
2
MDCL
1
MDCL
0
Symbol
Symbol
Cautions 1. The MDCH and MDCL registers values read during division processing (when the
multiplication/division control register (MDUC) value is 81H or C1H) will not be guaranteed.
2. During multiply-accumulator processing, do not use software to rewrite the values of the
MDCH and MDCL registers. If this is done, the operation result will be undefined.
3. The data is in the two's complement format in the multiply-accumulator mode (signed).
Table 13-4. Functions of MDCH and MDCL Registers During Operation Execution
Operation Mode Setting Operation Result
Multiplication mode (unsigned − −
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or signed)
Multiply-accumulator mode
(unsigned) MDCH: Initial accumulated value (unsigned)
(higher 16 bits)
MDCL: Initial accumulated value (unsigned)
(lower 16 bits)
MDCH: accumulated value (unsigned)
(higher 16 bits)
MDCL: accumulated value (unsigned)
(lower 16 bits)
Multiply-accumulator mode
(signed) MDCH: Initial accumulated value (signed)
(higher 16 bits)
MDCL: Initial accumulated value (signed)
(lower 16 bits)
MDCH: accumulated value (signed)
(higher 16 bits)
MDCL: accumulated value (signed)
(lower 16 bits)
Division mode (unsigned) − MDCH: Remainder (higher 16 bits)
MDCL: Remainder (lower 16 bits)
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The register configuration differs between when multiplication is executed and when division is executed, as follows.
• Register configuration during multipl icatio n
<Multiplicand A> <Multiplier B> <Product>
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) = [MDBH (bits 15 to 0), MDBL (bits 15 to 0)]
• Register configuration during multiply- accumulatio n
< Multiplicand A > <Multiplier B> < accumulated value > < accumulated result >
MDAL (bits 15 to 0) × MDAH (bits 15 to 0) + MDC (bits 31 to 0) = [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
(The multiplication res ult is stored in the MDBH (bits 15 to 0) and MDBL (bits 15 to 0).)
• Register configuration during divisi on
<Dividend> <Divisor>
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ÷ [MDBH (bits 15 to 0), MDBL (bits 15 to 0)] =
<Quotient> <Remainder>
[MDAH (bits 15 to 0), MDAL (bits 15 to 0)] ⋅⋅⋅ [MDCH (bits 15 to 0), MDCL (bits 15 to 0)]
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13.3 Register Controlling Multiplier and Divider/Multiply-Accumulator
The multiplier and divider/multiply-accumulator is controlled by using the multiplication/division control re gister (MDUC).
13.3.1 Multiplication/division control register (MDUC)
The MDUC register is an 8-bit register that controls the operation of the multiplier and divider/multiply-accumulator.
The MDUC register can be set by a 1-bit or 8- bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 13-5. Format of Multiplication/Division Control Register (MDUC)
Address: F00E8H After reset: 00H R/W
Symbol <7> <6> 5 4 <3> <2> <1> <0>
MDUC DIVMODE MACMODE 0 0 MDSM MACOF MACSF DIVST
DIVMODE MACMODE MDSM Operation mode selection
0 0 0 Multiplication mode (unsigned) (default)
0 0 1 Multiplication mode (signed)
0 1 0 Multiply-accumulator mode (unsigned)
0 1 1 Multiply-accumulator mode (signed)
1 0 0
Division mode (unsigned), generation of a division completion
interrupt (INTMD)
1 1 0
Division mode (unsigned), not generation of a division completion
interrupt (INTMD)
Other than above Setting prohibited
MACOF Overflow flag of multiply-accumulation result (accumulated value)
0 No overflow
1 With over flow
<Set condition>
• For the multiply-accumulator mode (unsigned)
The bit is set when the accumulated value goes outside the range from 00000000h to FFFFFFFFh.
• For the multiply-accumulator mode (signed)
The bit is set when the result of adding a positive product to a positive accumulated value exceeds
7FFFFFFFh and is negative, or when the result of adding a negative product to a negative accumulated
value exceeds 80000000h and is positive.
MACSF Sign flag of multiply-accumulation result (accumulated value)
0 The accumulated value is positive.
1 The accumulated value is negative.
Multiply-accumulator mode (unsigned): The bit is always 0.
Multiply-accumulator mode (signed): The bit indicates the sign bit of the accumulated value.
DIVSTNote Division operation start/stop
0 Division processing complete
1 Starts division/division processing in progress
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Note The DIVST bit can only be set (1) in the division mode. In the division mode, division operation is started by
setting (1) the DIVST bit. The DIVST bit is automatically cleared (0) when the operation ends. In the
multiplication mode, operation is automatically started by setting the multiplier and multiplicand to
multiplication/division data register A (MDAH, MDAL), respectively.
Cautions 1. Do not rewrite the DIVMODE, MDSM bits during operation processing (while the DIVST bit is
1). If it is rewritten, the operation result will be an undefined value.
2. The DIVST bit cannot be cleared (0) by using software during division processing (while the
DIVST bit is 1).
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13.4 Operations of Multiplier and Divider/Multiply-Accumulator
13.4.1 Multiplication (unsigned) operation
• Initial setting
<1> Set the multiplication/d ivision control register (MDUC) to 00H.
<2> Set the multipli c and to multiplication/division data register A (L) (MDAL).
<3> Set the multiplier to multiplic ation/division data register A (H) (MDAH).
(There is no preference in the order of executing steps <2> and <3>. Multiplication is automatically started
when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.)
• During operation processin g
<4> Wait for at least one clock. The operation will end when one clock has been issued.
• Operation end
<5> Read the prod uct (lower 16 bits) from multiplication/division data register B (L) (MDBL).
<6> Read the prod uct (higher 16 bits) from multiplication/division data register B (H) (MDBH).
(There is no preference in the order of e xecuting steps <5> and <6>.)
• Next operation
<7> The next time multiplication, multiply-accum ulation, or division is performed, start with the initial settings of each
step.
Remark Steps <1> to <7> correspond to <1> to <7> in Figure 13-6.
Figure 13-6. Ti ming Diagram of Multiplication (Unsigned) Operation (2 × 3 = 6)
MDAL 0002H
0003H
0000H
0006H
FFFFH
FFFFH
FFFEH
0001H
0002H
FFFDH
<2>
<1>
<3> <5>, <6>
<4>
00H
MDAH
MDBH
MDBL
MDUC
MDSM L
<7>
0000H
0000H
0000H
0000H
Operation clock
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13.4.2 Multiplication (signed) operation
• Initial setting
<1> Set the multiplication/d ivision control register (MDUC) to 08H.
<2> Set the multipli c and to multiplication/division data register A (L) (MDAL).
<3> Set the multiplier to multiplic ation/division data register A (H) (MDAH).
(There is no preference in the order of executing steps <2> and <3>. Multiplication operation is automatically
started when the multiplier and multiplicand are set to the MDAH and MDAL registers, respectively.)
• During operation processin g
<4> Wait for at least one clock. The operation will end when one clock has been issued.
• Operation end
<5> Read the prod uct (lower 16 bits) from multiplication/division data register B (L) (MDBL).
<6> Read the prod uct (higher 16 bits) from multiplication/division data register B (H) (MDBH).
(There is no preference in the order of e xecuting steps <5> and <6>.)
• Next operation
<7> To execute multiplication (signed) operation next, start from the “Initial setting” for multiplication (signed)
operation.
<8> The next time multiplication, multiply-accumulation (signed), or division is performed, start with the initial
settings of each step.
Caution The data is in the two's complement format in multiplication mode (signed).
Remark Steps <1> to <7> correspond to <1> to <7> in Figure 13-7.
Figure 13-7. Ti ming Diagram of Multiplication (Signed) Operation (−2 × 32767 = −65534)
MDAL FFFFH
FFFFH
0000H
0001H
FFFEH
7FFFH
FFFFH
0002H
00H 08H
MDAH
MDBL
MDBH
MDUC
MDSM
8001H
FFFFH
<2>
<1>
<3> <5>, <6>
<4> <7>
0000H
0000H
0000H
0000H
Operation clock
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13.4.3 Multiply-accumulation (unsigned) operation
• Initial setting
<1> Set the multiplication/d ivision control register (MDUC) to 40H.
<2> Set the initial a ccumulated value of higher 16 bits to multiplication/division d ata register C (L) (MDCL).
<3> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (H) (MDCH).
<4> Set the multipli c and to multiplication/division data register A (L) (MDAL).
<5> Set the multiplier to multiplic ation/division data register A (H) (MDAH).
(There is no preference in the order of executing steps <2>, <3>, and <4>. Multiplication operation is
automatically started when the multiplier is set to the MDAH register, respectively.)
• During operation processin g
<6> T he multiplication finishes in one clock cycle.
(The multiplication res ult is stored in multiplic ation/division d ata register B (L) (MDBL) and multiplication/ division
data register B (H) (MDBH).)
<7> After <6>, the multiply-accum ulation operation finis hes in one additi onal clock cycle. (T here is a wait of at least
two clock cycles after specifying the initial settings is finished (<5> ).)
• Operation end
<8> Read the accu mulated value (lower 16 bits) from the MDCL register.
<9> Read the accu mulated value (higher 16 bits) from the MDCH register.
(There is no preference in the order of e xecuting steps <8> and <9>.)
(<10> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD
signal is occurred.)
• Next operation
<11> T he next time multiplication, multiply-accum ulation, or division is performed, start with the initial settings of each
step.
Remark Steps <1> to <10> correspond to <1> to <10> in Figure 13- 8.
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Figure 13-8. Ti ming Diagram of Multiply-Accumulation (Unsigned) Operation
(2 × 3 + 3 = 9 → 32767 × 2 + 429401762 = 0 (over flow generated))
<2> <3> <5> <6><4>
00H 44H
MDCH FFFFH 0000H
MDUC
MDSM L
<7> <2> <3> <5> <6><4> <7>
<8>, <9>
<10>
40H
0000H
MDCL 0000H0000H 0003H 0009H 0002H
MDAH
0000H 0002H 7FFFH
MDAL
INTMD
0000H 0003H 0002H
MDBH
MDBL
0000H
0000H 0000H
0006H 0000H
FFFEH
MACOF
MACSF L
<1>
Operation clock
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13.4.4 Multiply-accumulation (signed) operation
• Initial setting
<1> Set the multiplication/d ivision control register (MDUC) to 48H.
<2> Set the initial accumulated value of higher 16 bits to multiplication/division data register C (H) (MDCH).
(<3> If the accumulated value in the MDCH register is negative, the MACSF bit is set to 1.)
<4> Set the initial accumulated value of lower 16 bits to multiplication/division data register C (L) (MDCL).
<5> Set the multipli c and to multiplication/division data register A (L) (MDAL).
<6> Set the multiplier to multiplic ation/division data register A (H) (MDAH).
(There is no preference in the order of executing steps <2>, <4>, and <5>. Multiplication operation is
automatically started when the multiplier is set to the MDAH register, respectively.)
• During operation processin g
<7> The multiplication operation finishes in one clock cycle.
(The multiplication res ult is stored in multiplic ation/division d ata register B (L) (MDBL) and multiplication/ divisio n
data register B (H) (MDBH).)
<8> After <7>, the multiply-accum ulation operation finis hes in one additi onal clock cycle. (T here is a wait of at least
two clock cycles after specifying the initial settings is finished (<6> ).)
• Operation end
<9> If the accumulated valu e stored in the MDCL and MDCH registers is positive, the MACSF bit is cleared to 0.
<10> Read the accumulated value (lower 16 bits) from the MDCL register.
<11> Read the accumulated value (higher 16 bits) from the MDCH register.
(There is no preference in the order of executing steps <10> and <11>.)
(<12> If the result of the multiply-accumulation operation causes an overflow, the MACOF bit is set to 1, INTMD
signal is occurred.)
• Next operation
<13> T he next time multiplication, multiply-accum ulation, or division is performed, start with the initial settings of each
step.
Caution The data is in the two's complement format in multiply-accumulation (signed) operation.
Remark Steps <1> to <12> correspond to <1> to <12> in Figure 13- 9.
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Figure 13-9. Ti ming Diagram of Multiply-Accumulation (signed) Operation
(2 × 3 + (−4) = 2 → 32767 × (−1) + (−2147483647) = −2147450882 (overflow occurs.))
<1>
<3> <3>
<3> <3>
<2> <5> <6><4>
00H
MDCH 0000H 8000H 7FFFH
MDUC
MDSM L
<7> <8> <2> <5> <6><4> <7> <8>
<10>, <11>
<12>
<9>
48H
0000H FFFFH
MDCL 8002H
0000H FFFCH 0002H 0001H
MDAL 0000H 0002H 7FFFH
MDAH
INTMD
0000H 0003H FFFFH
MDBH
MDBL
0000H
0000H 0000H
0006H FFFFH
8001H
MACOF
MACSF L
4AH
Operation clock
4CH
<9>
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13.4.5 Division operation
• Initial setting
<1> Set the multiplication/d ivision control register (MDUC) to 80H.
<2> Set the dividend (higher 16 bits) to multiplication/division data register A (H) (MDAH).
<3> Set the dividend (lower 16 bits) to multiplication/divis ion data register A (L) (MDAL).
<4> Set the divisor (higher 16 bits) to multiplication/division data register B (H) (MDBH).
<5> Set the divisor (lower 16 bits) to multiplication/divisio n data register B (L) (MDBL).
<6> Set bit 0 (DIVST) of the MDUC register to 1.
(There is no preference in the order of execut ing steps <2> to <5>.)
• During operation processin g
<7> The operation will end when one of the fol lowing processing is completed.
• A wait of at least 16 clocks (The operatio n will end when 16 clocks have been issued.)
• A check whether the DIVST bit has been cleared
(The read values of the MDBL, MDBH, MDCL, and MDCH registers during operation processing are not
guaranteed.)
• Operation end
<8> The DIVST bit is cleared and the operation ends. At this time, an interrupt request signal (INTMD) is generate d
if the operation was performed with MACMODE = 0.
<9> Read the qu otient (lower 16 bits) from the MDAL register.
<10> Read the quotient (hig her 16 bits) from the MDAH register.
<11> Read the remainder (lower 16 bits) from multiplication/division data register C (L) (MDCL).
<12> Read the remainder (higher 16 bits) from multiplication/division data register C (H) (MDCH).
(There is no preference in the order of executing steps <9> to <12>.)
• Next operation
<13> T he next time multiplication, multiply-accum ulation, or division is performed, start with the initial settings of each
step.
Remark Steps <1> to <12> correspond to <1> to <12> in Figure 13-10.
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Operation clock
Counter Undefined
<1> <2> <3> <4> <5> <6> <7> <9>, <10> <11>, <12>
<8>
<8>
MDAH,
MDAL
0000H
008CH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0006H
XXXXH
XXXXH
0000H
0230H 0000H
08C0H 0000H
2300H 0000H
8C00H 0002H
3000H 0008H
C000H 0023H
0000H 008CH
0000H 0230H
0000H 08C0H
0000H 2300H
0000H 8C00H
0000H 3000H
0000H C000H
0001H
0000H
0002H 0000H
0005H
0000H
0005H
MDUC
DIVST
INTMD
MDBH,
MDBL
XXXXH
XXXXH
MDCH,
MDCL
XXXXH
XXXXH
1H 2H 3H 4H 5H 6H 7H 8H 9H AH BH CH DH EH FH0H 0H
80H 80H81H
0000H
0023H
Figure 13-10. Timing Diagram of Division Operation (Example: 35 ÷ 6 = 5, Remainder 5)
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CHAPTER 14 DMA CONT ROLLER
The R5F102 products of the R L78/G12 have an internal DMA (Direct Memory Access) controller.
Data can be automatically transferred between the peripheral hardware supporting DMA, SFRs, and internal RAM
without via CPU.
As a result, the normal internal operation of the CPU and data transfer can be executed in parallel with transfer
between the SFR and internal RAM, and therefore, a large capacity of data can be processed. In addition, real-time
control using communication, timer, and A/D can also be realized.
14.1 Functions of DMA Controller
Number of DMA channels: 2 channels (R5F102 products)
Transfer unit: 8 or 16 bits
Maximum transfer unit: 1024 times
Transfer type: 2-cycle transfer (One transfer is processed in 2 clocks and the CPU stops during that
processing.)
Transfer mode: Single-transfer mode
Transfer request: Selectable from the following peripheral hardware interrupts
• A/D converter
• Serial interface (CSI00, CSI01, CSI11, CSI20, UART0 to UART2)
• Timer (channel 0, 1, 2, 3)
Transfer target: Between SFR and internal RAM
Here are examples of functions using DMA.
• Successive transfer of serial interface
• Batch transfer of analog data
• Capturing A/D conversion result at fixed interval
• Capturing port value at fixed interval
<R>
<R>
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14.2 Configuration of DMA Controller
The DMA controller includes the following hardware.
Table 14-1. Configuration of DMA Controller
Item Configuration
Address registers • DMA SFR address registers 0, 1 (DSA0, DSA1)
• DMA RAM address registers 0, 1 (DRA0, DRA1)
Count register • DMA byte count registers 0, 1 (DBC0, DBC1)
Control registers • DMA mode control registers 0, 1 (DMC0, DMC1)
• DMA operation control register 0, 1 (DRC0, DRC1)
(1) DMA SFR address register n (DSAn)
This is an 8-bit register that is used to set an SFR address that is the transfer source or destination of DMA
channel n.
Set the lower 8 bits of the SFR addresses FFF00H to FFFFFH.
This register is not automatically incremented but fixed to a specific val ue.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DSAn register can be read or written in 8-bit units. However, it cannot be written during DMA transfer.
Reset signal generation clears this register to 00H.
Figure 14-1. Format of DMA SFR Address Register n (DSAn)
Address: FFFB0H (DSA0), FFFB1H (DSA1) After reset: 00H R/W
7 6 5 4 3 2 1 0
DSAn
Remark n: DMA channel number (n = 0, 1)
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(2) DMA RAM address register n (DRAn)
This is a 16-bit register that is used to set a RAM address that is the transfer source or destination of DMA
channel n.
Addresses of the internal RAM area other than the general-purpose registers (see table 14-2) can be set to this
register.
Set the lower 16 bits of the RAM address.
This register is automatically increment ed when DMA transfer has been started. It is incremented by +1 in the 8-
bit transfer mode and by +2 in the 16-bit transfer mode. DMA transfer is started from the address set to this
DRAn register. When the data of the last a d dress has be en transferre d, the DRAn reg ister stops with the value of
the last address +1 in the 8-bit transfer mode , and the last address +2 in the 16-bit transfer mode.
In the 16-bit transfer mode, the least significant bit is ignored and is treated as an even address.
The DRAn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA
transfer.
Reset signal generation clears this register to 0000H.
Figure 14-2. Format of DMA RAM Address Register n (DRAn)
Address: FFFB2H, FFFB3H (DRA0), FFFB4H, FFFB5H (DRA1) , After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRAn
Remark n: DMA channel number (n = 0, 1)
Table 14-2 Internal R AM Area other than the General-purpose Registers
Part Number Internal RAM Area other than the General-purpose Registers
R5F10x66 256 × 8 bits (FFE00H to FFEDFH)
R5F10x67, R5F10x77, R5F10xA7 512 × 8 bits (FFD00H to FFEDFH)
R5F10x68, R5F10x78, R5F10xA8 768 × 8 bits (FFC00H to FFEDFH)
R5F10x69, R5F10x79, R5F10xA9 1024 × 8 bits (FFB00H to FFEDFH)
R5F10x6A, R5F10x7A 1536 × 8 bits (FF900H to FFEDFH)
R5F10xAA 2048 × 8 bits (FF700H to FFEDFH)
(x = 2, 3)
DRA0H: FFFB3H
DRA1H: FFFB5H DRA0L: FFFB2H
DRA1L: FFFB4H
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(3) DMA byte count register n (DBCn)
This is a 10-bit register that is used to set the number of times DMA channel n e xecutes transfer. Be sure to set
the number of times of transfer to this DBCn register before executing DMA transfer (up to 1024 times).
Each time DMA transfer has been executed, this register is automatically decremented. By reading this DBCn
register during DMA transfer, the remaining number of times of transfer can be lear ned.
The DBCn register can be read or written in 8-bit or 16-bit units. However, it cannot be written during DMA
transfer.
Reset signal generation clears this register to 0000H.
Figure 14-3. Format of DMA Byte Count Register n (DBCn)
Address: FFFB6H, FFFB7H (DBC0), FFFB8H, FFFB9H (DBC1) After reset: 0000H R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DBCn 0 0 0 0 0 0
DBCn[9:0]
Number of Times of Transfer
(When DBCn is Written) Remaining Number of Times of Transfer
(When DBCn is Read)
000H 1024 Completion of transfer or waiting for 1024 times of DMA transfer
001H 1 Waiting for remaining one time of DMA transfer
002H 2 Waiting for remaining two times of DMA transfer
003H 3 Waiting for remaining three times of DMA transfer
•
•
•
•
•
•
•
•
•
3FEH 1022 Waiting for remaining 1022 times of DMA transfer
3FFH 1023 Waiting for remaining 1023 times of DMA transfer
Cautions 1. Be sure to clear bits 15 to 10 to 0.
2. If the general-purpose register is specified or the internal RAM space is exceeded as a
result of continuous transfer, the general-purpose register or SFR space are written or read,
resulting in loss of data in these spaces. Be sure to set the nu mber of times of transfer that
is within the internal RAM space.
Remark n: DMA channel number (n = 0, 1)
DBC0H:FFFB7H
DBC1H:FFFB9H DBC0L:FFFB6H
DBC1L:FFFB8H
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14.3 Registers Controlling DMA Controller
DMA controller is controlled by the following registers.
• DMA mode control register n (DMCn)
• DMA operation control register n (DRCn)
Remark n: DMA channel number (n = 0, 1)
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14.3.1 DMA mode contro l reg ister n (DMCn)
The DMCn register is a register that is used to set a transfer mode of DMA channel n. It is used to select a
transfer direction, data size, setting of pending, and start source. Bit 7 (STGn) is a software trigger that starts
DMA.
Rewriting bits 6, 5, and 3 to 0 of the DMCn register is prohibited d urin g operation (when DSTn = 1).
The DMCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-4. Format of DMA Mode Control Register n (DMCn) (1/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
STGnNote 1 DMA transfer start software trigger
0 No trigger operation
1 DMA transfer is started when DMA operation is enabled (DENn = 1).
DMA transfer is performed once by writing 1 to the STGn bit when DMA operation is enabled (DENn = 1).
When this bit is read, 0 is always read.
DRSn Selection of DMA transfer direction
0 SFR to internal RAM
1 Internal RAM to SFR
DSn Specification of transfer data size for DMA transfer
0 8 bits
1 16 bits
DWAITn Note
2 Pending of DMA transfer
0 Executes DMA transfer upon DMA start request (not held pending).
1 Holds DMA start request pending if any.
DMA transfer that has been held pending can be started by clearing the value of the DWAITn bit to 0.
It takes 2 clocks to actually hold DMA transfer pending when the value of the DWAITn bit is set to 1.
Notes 1. The soft ware trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
2. When DMA transfer is held pending while using two or more DMA channels, be sure to hold the DMA
transfer pending for all channels (by setting the DWAIT0, DWAIT1, DWAIT2, and DWAIT 3 bits to 1).
Remark n: DMA channel number (n = 0, 1)
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Figure 14-4. Format of DMA Mode Control Register n (DMCn) (2/2)
Address: FFFBAH (DMC0), FFFBBH (DMC1) After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 2 1 0
DMCn STGn DRSn DSn DWAITn IFCn3 IFCn2 IFCn1 IFCn0
Selection of DMA start sourceNote IFCn3 IFCn2 IFCn1 IFCn0
Trigger signal Trigger contents
0 0 0 0 − Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
0 0 0 1 INTAD A/D conversion end interrupt
0 0 1 0 INTTM00 End of timer channel 0 count or capture
end interrupt
0 0 1 1 INTTM01 End of timer channel 1 count or capture
end interrupt
0 1 0 0 INTTM02 End of timer channel 2 count or capture
end interrupt
0 1 0 1 INTTM03 End of timer channel 3 count or capture
end interrupt
0 1 1 0 INTST0/INTCSI00 UART0 transmission transfer end or
buffer empty interrupt/CSI00 transfer end
or buffer empty interrupt
0 1 1 1 INTSR0/INTCSI01 UART0 reception transfer end
interrupt/CSI01 transfer end or buffer
empty interrupt
1 0 0 0 INTST1 UART1 transmission transfer end or
buffer empty interrupt
1 0 0 1 INTSR1/INTCSI11 UART1 reception transfer end
interrupt/CSI11 transfer end or buffer
empty interrupt
1 0 1 0 INTST2/INTCSI20 UART2 transmission transfer end or
buffer empty interrupt/CSI20 transfer end
or buffer empty interrupt
1 0 1 1 INTSR2 UART2 reception transfer end interrupt
Other than above Setting prohibited
Note T he software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 bits values.
Remark n: DMA channel number (n = 0, 1)
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14.3.2 DMA operation control register n (DRCn)
The DRCn register is a register that is used to enable or disable transfer of DMA channel n.
Rewriting bit 7 (DENn) of this register is prohibited during o peration (when DSTn = 1).
The DRCn register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 14-5. Format of DMA Operation Control Register n (DRCn)
Address: FFFBCH (DRC0), FFFBDH (DRC1) After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 <0>
DRCn DENn 0 0 0 0 0 0 DSTn
DENn DMA operation enable flag
0 Disables operation of DMA channel n (stops operating cock of DMA).
1 Enables operation of DMA channel n.
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
DSTn DMA transfer mode flag
0 DMA transfer of DMA channel n is completed.
1 DMA transfer of DMA channel n is not completed (still under execution).
DMAC waits for a DMA trigger when DSTn = 1 after DMA operation is enabled (DENn = 1).
When a software trigger (STGn) or the start source trigger set by the IFCn3 to IFCn0 bits is input, DMA transfer is
started.
When DMA transfer is completed after that, this bit is automatically cleared to 0.
Write 0 to this bit to forcibly terminate DMA transfer under execution.
Caution The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is terminated
without waiting for generation of the interrupt (INTDMAn) of DMAn, therefore, set the DSTn bit
to 0 and then the DENn bit to 0 (for details, refer to 14.5.5 Forced termination by software).
Remark n: DMA channel number (n = 0, 1)
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No
No
DSTn = 1
DSTn = 0
INTDMAn = 1
DMA trigger = 1?
DBCn = 0000H ?
Yes
Yes
DENn = 1
Setting DSAn, DRAn, DBCn, and DMCn
Transmitting DMA request
Receiving DMA acknowledge
DMA transfer
DRAn = DRAn + 1 (or + 2)
DBCn = DBCn − 1
DENn = 0
Set by software program
Operation by DMA
controller (hardware)
Set by software program
14.4 Operation of DMA Controller
14.4.1 Operation procedu re
<1> The DMA controller is enabled to operate when DENn = 1. Before writing the other registers, be sure to set the
DENn bit to 1. Use 80H to write with an 8-bit manipulation instruction.
<2> Set an SFR address, a RAM address, the number of times of transfer, and a transfer mode of DMA transfer to
DMA SFR address register n (DSAn), DMA RAM address register n (DRAn), DMA byte count register n (DBCn),
and DMA mode control register n (DMCn).
<3> The DMA controller waits for a DMA trigger when DSTn = 1. Use 81H to write with an 8-bit manipulation
instruction.
<4> When a software trigger (STGn) or a start source trigger specified by the IFCn3 to IFCn0 bits is input, a DMA
transfer is started.
<5> Transfer is completed when the number of times of transfer set by the DBCn register reaches 0, and transfer is
automatically terminated by occurrence of an interrupt (INTDMAn).
<6> Stop the operation of the DMA controller b y clearing the DENn bit to 0 when the DMA controller is not used.
Figure 14-6. Operation Procedu re
Remark n: DMA channel number (n = 0, 1)
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14.4.2 Transfer mode
The following four modes can be selected for DMA transfer by using bits 6 and 5 (DRSn and DSn) of DMA mode
control register n (DMCn).
DRSn DSn DMA Transfer Mode
0 0 Transfer from SFR of 1-byte data (fixed address) to RAM (address is incremented by +1)
0 1 Transfer from SFR of 2-byte data (fixed address) to RAM (address is incremented by +2)
1 0 Transfer from RAM of 1-byte data (address is incremented by +1) to SFR (fixed address)
1 1 Transfer from RAM of 2-byte data (address is incremented by +2) to SFR (fixed address)
By using these transfer mode s, up to 1024 bytes of data can be consec utively transferred by using the serial interface,
data resulting from A/D conversion can be consecutively transferre d, and port data can be scanned at fixed time intervals
by using a timer.
14.4.3 Termination of DMA transfer
When DBCn = 00H and DMA transfer is completed, the DSTn bit is automatically cleared to 0. An interrupt request
(INTDMAn) is generated and transfer is terminated.
When the DSTn bit is cleared to 0 to forcibly terminate DMA transfer, DMA byte count register n (DBC n) and DMA RAM
address register n (DRAn) ho ld the value when transfer is terminated.
The interrupt request (INTDMAn) is not generated if transfer is forcibly terminated.
Remark n: DMA channel number (n = 0, 1)
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14.5 Example of Setting of DMA Controller
14.5.1 CSI consecutive transmission
A flowchart showing an example of setting for CSI consecutiv e transmission is shown below.
• Consecutive transmission of CSI10 (256 bytes)
• DMA channel 0 is used for DMA transfer.
• DMA start source: INTCSI10 (software trigger (STG0) only for the first start source)
• Interrupt of CSI10 is specified by IFC03 to IFC00 = 1000B.
• Transfers FFB00H to FFBFFH (256 bytes) of RAM to FFF44H of the data register (SIO10) of CSI.
Remark IFC03 to IFC00: Bits 3 to 0 of DMA mode control registers 0 (DMC0)
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Figure 14-7. Example of Setting for CSI Consecutive Transmission
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the int errupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details,
refer to 14.5.5 Forced termination by software).
The first trigger for consecutive transmission is not started by the interrupt of CSI. In this example, it start by a software
trigger.
CSI transmission of the second time and onward is automatically executed.
A DMA interrupt (INTDMA0) occurs when the last transmit data has been written to the data register.
Setting for CSI transfer
DEN0 = 1
DSA0 = 44H
DRA0 = FB00H
DBC0 = 0100H
DMC0 = 48H
DEN0 = 0
DST0 = 1
STG0 = 1
Start
DMA is started.
INTCSI10 occurs.
RETI
End
User program
processing
Occurrence of
INTDMA0
DST0 = 0Note
DMA0 transfer
CSI
transmission
Hardware operation
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14.5.2 Consecutive capturing of A/D conversion results
A flowchart of an example of setting for consecutively capturing A/D conversion results is shown below.
• Consecutive capturing of A/D conversion results.
• DMA channel 1 is used for DMA transfer.
• DMA start source: INTAD
• Interrupt of A/D is specified by IFC13 to IFC10 = 0001B.
• Transfers FFF1EH and FFF1FH (2 bytes) of the 10-bit A/D conversion result register (ADCR) to 512 bytes of
FFCE0H to FFEDFH of RAM.
Remark IFC13 to IFC10: Bits 3 to 0 of DMA mode control registers 1 (DMC1)
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Figure 14-8. Example of Setting of Consecutively Capturing A/D Conversion Results
Note The DST1 flag is automatically cleared to 0 when a DMA transfer is comp leted.
Writing the DEN1 flag is enabled only when DST1 = 0. To terminate a DMA transfer without waiting for
occurrence of the int errupt of DMA1 (INTDMA1), set the DST1 bit to 0 and then the DEN1 bit to 0 (for details,
refer to 14.5.5 Forced termination by software).
Hardware operation
DEN1 = 1
DSA1 = 1EH
DRA1 = FCE0H
DBC1 = 0100H
DMC1 = 21H
DST1 = 1
Starting A/D conversion
DEN1 = 0
RETI
End
INTDMA1 occurs.
DST1 = 0Note
INTAD occurs.
DMA1 transfer
Start
User program
processing
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14.5.3 UART consecutive reception + ACK transmission
A flowchart illustrating an example of setting for UART consecutive reception + ACK transmission is shown below.
• Consecutively receives data from UART0 and outputs ACK to P10 on completion of reception.
• DMA channel 0 is used for DMA transfer.
• DMA start source: Software trigger (DMA transfer on occurrence of an interrupt is disabled.)
• Transfers FFF12H of UART receive data register 0 (RXD0) to 64 bytes of FFE00H to FFE3FH of RAM.
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DEN0 = 1
DSA0 = 12H
DRA0 = FE00H
DBC0 = 0040H
DMC0 = 00H
DEN0 = 0Note
Setting for UART reception
DST0 = 1
User program
processing
STG0 = 1
P10 = 1
P10 = 0
INTSR0 occurs.
INTDMA0
occurs.
DST0 = 0
DMA0 transfer
RETI
Hardware operation
Start
End
RETI
INTSR0 interrupt routine
Figure 14-9. Example of Setting fo r UART Consecutive Reception + ACK Transmission
Note The DST0 flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DEN0 flag is enabled only when DST0 = 0. To terminate a DMA transfer without waiting for
occurrence of the int errupt of DMA0 (INTDMA0), set the DST0 bit to 0 and then the DEN0 bit to 0 (for details,
refer to 14.5.5 Forced termination by software).
Remark This is an exam ple where a software trigger is used as a DMA start source.
If ACK is not transmitted and if only data is consecutively received from UART, the UART reception end
interrupt (INTSR0) can be used to start DMA for data reception.
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Starting DMA transfer
DWAITn = 0
DWAITn = 1
Wait for 2 clocks
P10 = 1
Wait for 9 clocks
P10 = 0
Main program
14.5.4 Holding DMA transfer pending by DWAITn bit
When DMA transfer is started, transfer is performed while an instruction is executed. At this time, the operation of the
CPU is stopped and delayed for the duration of 2 clocks. If this poses a problem to the operation of the set system, a
DMA transfer can be held pending by setting the DWAITn bit to 1. The DMA transfer for a transfer trigger that occurred
while DMA transfer was held pending is executed after the pending status is canceled. However, because only one
transfer trigger can be held pending for each channel, even if multiple transfer triggers occur for one channel during the
pending status, only one DMA transfer is executed after the pending status is canceled.
To output a pulse with a width of 10 clocks of the operating frequency from the P10 pin, for example, the clock width
increases to 12 if a DMA transfer is started midway. In this case, the DMA transfer can be held pending by setting the
DWAITn bit to 1.
After setting the DWAITn bit to 1, it takes two clocks until a DMA transfer is held pending.
Figure 14-10. Example of Setting for Holding DMA Transfer Pending by DWAITn Bit
Caution When DMA transfer is held pending while using two or more DMA channels, be sure to held the
DMA transfer pending for all channels (by setting DWAIT0, DWAIT1, DWAIT2, and DWAIT3 to 1). If
the DMA transfer of on e channel is executed while that of the other chan nel is held pending, DMA
transfer might not be held pending for the latter channel.
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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DSTn = 0
DENn = 0
DSTn = 0 ? No 2 clock wait
Yes
DSTn = 0
DENn = 0
14.5.5 Forced termination by software
After the DSTn bit is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and the DSTn
bit is set to 0. To forcibly terminate a DMA transfer by software without waiting for occurrence of the int errupt (INTDMAn)
of DMAn, therefore, perform either of the following processes.
<When using one DMA cha nnel>
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipul ation instruction) by soft ware, confirm by polling
that the DSTn bit has actually bee n cleared to 0, and then set the DENn bi t to 0 (use DRCn = 00 H to write with an 8-
bit manipulation instruction).
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the
DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
<When using two DMA channels>
• T o forcibly terminate DMA transfer by software when using two DMA channels (by setting DST n to 0), clear the DSTn
bit to 0 after the DMA transfer is held pending by setting the DWAITn bits of both using channels to 1. Next, clear the
DWAITn bits of both using channels to 0 to cancel the pending status, and then clear the DENn bit to 0.
Figure 14-11. Forced Termination of DMA Transfer (1/2)
Exam ple 1 Example 2
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
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DWAIT0 = 1
DWAIT1 = 1
DST0 = 0
DST1 = 0
DEN0 = 0
DEN1 = 0
DWAIT0 = 0
DWAIT1 = 0
DWAIT0 = 1
DWAIT1 = 1
DSTn = 0
DENn = 0
DWAIT0 = 0
DWAIT1 = 0
Figure 14-11. Forced Termination of DMA Transfer (2/2)
Example 3
• Procedure for forcibly terminating the DMA • Procedure for forcibly terminating the DMA
transfer for one channel if both channels are used transfer for both channels if both channels are used
Remarks 1. n: DMA channel number (n = 0, 1)
2. 1 clock: 1/fCLK (fCLK: CPU clock)
In example 3, the system is not required to wait two clock cycles after the DWAITn bit is set to 1. In addition, the
system does not have to wait t wo clock cycles after clearin g t he DST n bit t o 0, becaus e more than two clock cycles elapse
from when the DSTn bit is cleared to 0 to when the DENn bit is cleared to 0 .
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14.6 Cautions on Using DMA Controller
(1) Priority of DMA
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is co mpleted. If t wo or more DMA requests are gener ated
at the same time, however, their priority are DMA channel 0 > DMA channel 1 > DMA chan nel 2 > DMA chann el 3.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
(2) DMA response time
The response time of DMA transfer is as follows.
Table 14-2. Response Time of DMA Transfer
Minimum Time Maximum Time
Response time 3 clocks 10 clocksNote
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
transfer.
2. When executing a DMA pending instruction (see 14.6 (4)), the maximum response
time is extended by the execution time of that instruction to be held pending.
3. Do not specify successi ve transfer triggers for a channel within a perio d equal to the
maximum response time plus one clock cycle, because they might be ignored.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
(3) Operation in standby mode
The DMA controller operates as follows in the standby mode.
Table 14-3. DMA Operation in Standby Mode
Status DMA Operation
HALT mode Normal operation
STOP mode Stops operation.
If DMA transfer and STOP instruction execution contend, DMA transfer may be
damaged. Therefore, stop DMA before executing the STOP instruction.
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(4) DMA pending forwarding
Even if a DMA request is generated, DMA transfer is held pending immediately after the following instructions.
• CALL !addr16
• CALL $!addr20
• CALL !!addr20
• CALL rp
• CALLT [addr5]
• BRK
• Bit manipulation instructions for registers IF0L, IF0H, IF1L, IF1H, IF 2L, IF2H, IF3L, MK0L, MK0H, MK1L, MK1H,
MK2L, MK2H, MK3L, PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR03L, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H, PR13L, and PSW each.
• Instruction for accessing the data flash memory
(5) Operation if address in general-pu rp ose register area or other than those of intern al RAM area is specified
The address indicated by DMA RAM address register n (DRAn) is incremented during DMA transfer. If the
address is incremented to an address in the general-purpose register area or exceeds the area of the internal
RAM, the following operation is performed.
In mode of transfer from SFR to RAM
The data of that address is lost.
In mode of transfer from RAM to SFR
Undefined data is transferred to SFR.
In either case, malfunctioning may occur or damage may be done to the system. Therefore, make sure that the
address is within the internal RAM area other than the general-purpose register area.
Internal RAM
General-purpose registers
DMA transfer enabled area
FFF00H
FFEFFH
FFEE0H
FFEDFH
(6) Operation if instructions for accessing the data flash area
• Because DMA transfer is suspended to access to the data flash area, be sure to add the DMA pending
instruction.
If the data flash area is accessed after an next instruction execution from start of DMA transfer, a 3-clock wait
will be inserted to the next instruction.
Instruction 1
DMA transfer
Instruction 2 The wait of three clock cycles occurs.
MOV A, ! DataFlash area
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CHAPTER 15 INTERRUPT FUNCTIONS
The interrupt function s witches the program execution to other processin g. When the branch processing is finished, the
program returns to the interrupted processing.
The number of interrupt sources differs, depending on the product.
20-, 24-pin products 30-pin products
R5F102 R5F103 R5F102 R5F103
External 5 6
Maskable interrupts
Internal 18 16 26 19
15.1 Interrupt Function Types
The following two types of interrupt functions are used.
(1) Maskable interrupts
These interrupts undergo mask control. Maskable interrupts can be divided into four priority groups by setting the
priority specification flag registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L).
Multiple interrupt servicing can be applied to low-priority interrupts when high-pr iority interrupts are generated. If two
or more interrupt requests, each having the same priority, are simultaneously generated, then they are processed
according to the priority of vectored interrupt servicing. For the priority order, see Table 15-1 and Tabl e 15-2.
A standby release signal is generated and STOP, HALT, and SNOOZE modes are released.
External interrupt requests and internal interrupt requests are provided as maskable interrupts.
(2) Software interrupt
This is a vectored interrupt generated by executing the BRK instruction. It is acknowledged even when interrupts are
disabled. The software interrupt does not undergo interrupt priority control.
15.2 Interrupt Sources and Configur ation
Interrupt sources include maskable interrupts and software interrupts. In addition, they also have up to seven reset
sources (see Table 15-1 or 15-2). The vector codes that store the program start address when branching due to the
generation of a reset or various interrupt requ ests are two bytes each, so interrupts jump to a 64 K address of 00000H to
0FFFFH.
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Table 15-1. Interrupt Source List (20-, 24-pin products) (1/2)
Interrupt Source
Interrupt Type
Default Priority Note 1
Name Trigger
Internal/External
Vector Table Address
Basic Configuration Type No te 2
R5F102
R5F103
0 INTWDTI Watchdog timer interval Note 3 (75%+1/2fIL of overflow
time) Internal 0004H (A)
1 INTLVI Voltage detection
Note 4 0006H
Maskable
2 INTP0 Pin input edge detection External 0008H (B)
3 INTP1 000AH
4 INTP2 000CH
5 INTP3 000EH
6 INTDMA0 End of DMA0 transfer Internal 0010H (A) −
7 INTDMA0 End of DMA1 transfer 0012H −
8 INTST0/
INTCSI00/
INTIIC00
UART0 transmission transfer end or buffer empty
interrupt/CSI00 transfer end or buffer empty
interrupt
/IIC00 transfer end
0014H
−
−
9 INTSR0/
INTCSI01/
INTIIC01
UART0 reception transfer end/CSI01 transfer end or
buffer empty interrupt
/IIC01 transfer end
0016H
−
10 INTSRE0 U A R T 0 r e c e p t i o n co m m u n i c a t i o n e r r o r oc c u r r e n c e 0018H
11 INTTM01H End of timer channel 1 count or capture (at higher 8-bit
timer operation)
001AH
12 INTTM03H End of timer channel 3 count or capture (at higher 8-bit
timer operation)
001CH
13 INTIICA0 End of IICA0 communication 001EH
14 INTTM00 End of timer channel 0 count or capture (16 bit/at lower
8-bit timer operation)
0020H
15 INTTM01 End of timer channel 1 count or capture (16 bit/at lower
8-bit timer operation) 0022H
16 INTTM02 End of timer channel 2 count or capture (16 bit/at lower
8-bit timer operation) 0024H
17 INTTM03 End of timer channel 3 count or capture (16 bit/at lower
8-bit timer operation) 0026H
18 INTAD End of A/D conversion 0028H
19 INTIT Interval signal detection from 12-bit Interval timer 002AH
20 INTKR Key return signal detection External 002CH (C)
21 INTMD End of division operation / overflow occurrence 002EH
22 INTFL End of sequencer interrupt Note 5
Internal
0030H
(A)
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. 0 indicates the highest priority and 22 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVI MD) of the voltage detection level register (LVIS) is cleared to 0.
5. Only for using self programming library
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Table 15-1. Interrupt Source List (20-, 24-pin products) (2/2)
Interrupt Source
Interrupt Type
Default Priority Note 1
Name Trigger
Internal/External
Vector Table Address
Basic Configuration Type No te 2
R5F102
R5F103
Software
− BRK Execution of BRK instruction − 007EH (D)
RESET RESET pin input
POR Power-on-reset
LVD Voltage detectionNote 3
WDT Overflow of watchdog timer
TRAP Execution of illegal instructionNote 4
IAW Illegal memory access
Reset
−
RPE RAM parity error
− 0000H −
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur ｖ
simultaneously. Zero indicates the high est priority and 22 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1.
3. When bit 7 (LVI MD) of the voltage detection level register (LVIS) is cleared to 1.
4. When the instruction code in FFH is executed.
No reset is issued even if an illegal instruction is executed during emulation with the in-circuit emulator or
on-chip debug emulator.
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Table 15-2. Interrupt Source List (30-pin products) (1/2)
Interrupt Source
Interrupt Type
Default Priority Note 1
Name Trigger
Internal/External
Vector Table
Address
Basic Configuration
Type Note 2
R5F102
R5F103
0 INTWDTI
Watchdog timer interval Note 3 (75% + 1/2fIL of
overflow time) Internal 0004H (A)
1 INTLVI Voltage detection Note 4 0006H
Maskable
2 INTP0 Pin input edge detection External 0008H (B)
3 INTP1 000AH
4 INTP2 000CH
5 INTP3 000EH
6 INTP4 0010H
7 INTP5 0012H
8 INTST2/
INTCSI20/
INTIIC20
UART2 transmission transfer end, buffer empty
interrupt/CSI20 transfer end or buffer empty
interrupt/IIC20 transfer end
Internal 0014H (A) −
9 INTSR2 UART2 reception transfer end 0016H −
10 INTSRE2 UART2 reception communication error occurrence 0018H −
11 INTDMA0 DMA0 transfer end 001AH −
12 INTDMA1 DMA1 transfer end 001CH −
13 INTST0/
INTCSI00/
INTIIC00
UART0 transmission transfer end, buffer empty
interrupt/CSI00 transfer end or buffer empty
interrupt/IIC00 transfer end
001EH
−
14 INTSR0 UART0 reception transfer end 0020H
INTSRE0 UART0 reception communication error occurrence
15
INTTM01H End of timer channel 1 count or capture (at higher 8-
bit timer operation)
0022H
16 INTST1 UART1 transmission transfer end 0024H −
17 INTSR1/
INTCSI11/
INTIIC11
UART1 reception transfer end/CSI11 transfer end or
buffer empty interrupt/IIC11 transfer end 0026H −
INTSRE1 UART1 reception communication error occurrence
−
18
INTTM03H End of timer channel 3 count or capture (at higher 8-
bit timer operation)
0028H
19 INTIICA0 IICA0 communication end 002AH
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. 0 indicates the highest priority and 31 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1 respectively.
3. When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
4. When bit 7 (LVI MD) of the voltage detection level register (LVIS) is cleared to 0.
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Table 15-2. Interrupt Source List (30-pin products) (2/2)
Interrupt Source
Interrupt Type
Default Priority Note 1
Name Trigger
Internal/External
Vector Table
Address
Basic Configuration
Type Note 2
R5F102
R5F103
20 INTTM00 End of timer channel 0 count or capture (16 bit / at
lower 8-bit timer operation) Internal 002CH (A)
Maskable
21 INTTM01 End of timer channel 1 count or capture (16 bit / at
lower 8-bit timer operation) 002EH
22 INTTM02 End of timer channel 2 count or capture (16 bit / at
lower 8-bit timer operation) 0030H
23 INTTM03 End of timer channel 3 count or capture (16 bit / at
lower 8-bit timer operation) 0032H
24 INTAD End of A/D conversion 0034H
25 INTIT Interval signal detection from 12-bit interval timer 0038H
26 INTTM04 End of timer channel 4 count or capture (16 bit / at
lower 8-bit timer operation) 0042H
27 INTTM05 End of timer channel 5 count or capture (16 bit / at
lower 8-bit timer operation) 0044H
28 INTTM06 End of timer channel 6 count or capture (16 bit / at
lower 8-bit timer operation) 0046H
29 INTTM07 End of timer channel 7 count or capture (16 bit / at
lower 8-bit timer operation) 0048H
30 INTMD End of division operation / overflow occurrence 005EH
31 INTFL End of sequencer interrupt Note 3 0062H
Software
− BRK Execution of BRK instruction − 007EH (D)
− RESET RESET pin input − 0000H −
POR Power-on-reset
LVD Voltage detectionNote 4
Reset
WDT Overflow of watchdog timer
TRAP Execution of illegal instructionNote 5
IAW Illegal memory access
RPE RAM parity error
Notes 1. The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. 0 indicates the highest priority and 31 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 15-1 respectively.
3. Only for using self programming library.
4. When bit 7 (LV I MD) of the voltage detection level register (LVIS) is cleared to 0.
5. When the instr uction code in FFH is executed.
No reset is issued even if an illegal instruction is executed during emulation with the in-circuit emulator or
on-chip debug emulator.
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Figure 15-1. Basic Configuration of Interrupt Function (1/2)
(a) Internal maskable interrupt
IF
MK IE PR1 ISP1
PR0 ISP0
Internal bus
Interrupt
request Priority controller
Vector table
address generator
Standby release
signal
(b) External maskable interrupt (INTPn)
IF
MK IE PR1 ISP1
PR0 ISP0
Internal bus
External interrupt edge
enable register
(EGP, EGN)
INTPn pin input Edge
detector Priority controller
Vector table
address generator
Standby release
signal
IF: Interrupt request flag
IE: Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
Remark 20, 24-pin pro duct : n = 0 to 3
30-pin product : n = 0 to 5
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Figure 15-1. Basic Configuration of Interrupt Function (2/2)
(c) External maskable interrupt (INTKR)
IF
MK
KRMn
IE PR1 ISP1
PR0 ISP0
Internal bus
K
Rn pin input Priority controller
Vector table
address generato
r
Standby release
signal
Key
interrupt
detector
Key return mode
register (KRM0, KRM1)
IF: Interrupt request flag
IE: Interrupt enable flag
ISP0: In-service priority flag 0
ISP1: In-service priority flag 1
MK: Interrupt mask flag
PR0: Priority specification flag 0
PR1: Priority specification flag 1
Remark 24-pin product : n = 0 to 9
20-pin product : n = 0 to 5
(d) Software interrupt
Vector table
address generator
Internal bus
I
nterrupt
r
equest
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15.3 Registers Controlling Interrupt Functions
The following 6 types of registers are used to control the interrupt functio n s.
• Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L , IF2H)
• Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H)
• Priority specification flag registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
• External interrupt rising edge enable register (EGP0)
• External interrupt falling edge enable register (EGN0)
• Program status word (PSW)
Tables 15-3 and 15-4 show a list of interrupt request flags, interrupt mask flags, and priority specification flags
corresponding to interrupt request sources.
Table 15-3. Flags Corresponding to Interrupt Request Sources (20-, 24-pin products) (1/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source
Register
Register
Register
R5F102
R5F103
INTWDTI WDTIIF WDTIMK WDTIPR0, WDTIPR1
INTLVI LVIIF LVIMK LVIPR0, LVIPR1
INTP0 PIF0 PMK0 PPR00, PPR10
INTP1 PIF1 PMK1 PPR01, PPR11
INTP2 PIF2 PMK2 PPR02, PPR12
INTP3 PIF3 PMK3 PPR03, PPR13
INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10 −
INTDMA1 DMAIF1
IF0L
DMAMK1
MK0L
DMAPR01, DMAPR11
PR00L,
PR10L
−
INTST0 Note 1
INTCSI00 Note
1
INTIIC00 Note 1
STIF0 Note 1
CSIIF00 Note
1
IICIF00 Note
1
STMK0 Note 1
CSIMK00 Note 1
IICMK00 Note 1
STPR00, STPR10 Note 1
CSIPR000, CSIPR100 Note 1
IICPR000, IICPR100 Note 1 −
−
INTSR0 Note 2
INTCSI01 Note
2
INTIIC01 Note 2
SRIF0 Note 2
CSIIF01 Note
2
IICIF01 Note
2
SRMK0 Note 2
CSIMK01 Note 2
IICMK01 Note 2
SRPR00, SRPR10 Note 2
CSIPR001, CSIPR101 Note 2
IICPR001, IICPR101 Note 2 −
INTSRE0 SREIF0 SREMK0 SREPR00, SREPR10
INTTM01H TMIF01H TMMK01H TMPR001H, TMPR101H
INTTM03H TMIF03H TMMK03H TMPR003H, TMPR103H
INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10
INTTM00 TMIF00 TMMK00 TMPR000, TMPR100
INTTM01 TMIF01
IF0H
TMMK01
MK0H
TMPR001, TMPR101
PR00H,
PR10H
INTTM02 TMIF02 TMMK02 TMPR002, TMPR102
INTTM03 TMIF03
IF1L
TMMK03
MK1L
TMPR003, TMPR103
PR01L,
PR11L
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Table 15-3. Flags Corresponding to Interrupt Request Sources (20-, 24-pin products) (2/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source
Register
Register
Register
R5F102
R5F103
INTAD ADIF ADMK ADPR0, ADPR1
INTIT TMKAIF TMKAMK TMKAPR0, TMKAPR1
INTKR KRIF KRMK KRPR0, KRPR1
INTMD MDIF MDMK MDPR0, MDPR1
INTFL FLIF
IF1L
FLMK
MK1L
FLPR0, FLPR1
PR01L,
PR11L
Notes 1. If interrupt source INTST0, INTCSI00, or INTIIC00 occurs, bit 5 of the IF0H register is set to 1. Bit 5 of the
MK0H, PR00H, and PR10H registers corresponds these th ree interrupt sources.
2. If interrupt source INTSR0, INTCSI01, or INTIIC01 occurs, bit 6 of the IF0H register is set to 1. Bit 6 of the
MK0H, PR00H, and PR10H registers corresponds these three interrupt sources.
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Table 15-4. Flags Corresponding to Interrupt Request Sources (30-pin products) (1/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source
Register
Register Register
R5F102
R5F103
INTWDTI WDTIIF WDTIMK WDTIPR0, WDTIPR1
INTLVI LVIIF LVIMK LVIPR0, LVIPR1
INTP0 PIF0 PMK0 PPR00, PPR10
INTP1 PIF1 PMK1 PPR01, PPR11
INTP2 PIF2 PMK2 PPR02, PPR12
INTP3 PIF3 PMK3 PPR03, PPR13
INTP4 PIF4 PMK4 PPR04, PPR14
INTP5 PIF5
IF0L
PMK5
MK0L
PPR05, PPR15
PR00L,
PR10L
INTST2Note1 STIF2Note1 STMK2Note1 STPR02, STPR12Note1 −
INTCSI20Note1 CSIIF20Note1 CSIMK20Note1 CSIPR020, CSIPR120Note1
INTIIC20Note1 IICIF20Note1 IICMK20Note1 IICPR020, IICPR120Note1
INTSR2 SRIF2 SRMK2 SRPR02, SRPR12 −
INTSRE2 SREIF2 SREMK2 SREPR02, SREPR12 −
INTDMA0 DMAIF0 DMAMK0 DMAPR00, DMAPR10 −
INTDMA1 DMAIF1 DMAMK1 DMAPR01, DMAPR11 −
INTST0Note2 STIF0Note2 STMK0Note2 STPR00, STPR10 Note2
INTCSI00Note2 CSIIF00Note2 CSIMK00Note2 CSIPR000, CSIPR100 Note2
INTIIC00Note2 IICIF00Note2 IICMK00Note2 IICPR000, IICPR100 Note2
INTSR0 SRIF0 SRMK0 SRPR00, SRPR10
INTSRE0Note3 SREIF0Note3 SREMK0Note3 SREPR00, SREPR10Note3
INTTM01HNote3 TMIF01HNote3
IF0H
TMMK01HNote3
MK0H
TMPR001H, TMPR101HNote3
PR00H,
PR10H
INTST1 STIF1 STMK1 STPR01, STPR11 −
INTSR1Note4 SRIF1Note4 SRMK1Note4 SRPR01, SRPR11 Note4 −
INTCSI11Note4 CSIIF11Note4 CSIMK11Note4 CSIPR011, CSIPR111 Note4
INTIIC11Note4 IICIF11Note4 IICMK11Note4 IICPR011, IICPR111 Note4
INTSRE1Note5 SREIF1Note5 SREMK1Note5 SREPR01, SREPR11 Note5 −
INTTM03HNote5 TMIF03HNote5 TMMK03HNote5 TMPR003H, TMPR103H Note5
INTIICA0 IICAIF0 IICAMK0 IICAPR00, IICAPR10
INTTM00 TMIF00 TMMK00 TMPR000, TMPR100
INTTM01 TMIF01 TMMK01 TMPR001, TMPR101
INTTM02 TMIF02 TMMK02 TMPR002, TMPR102
INTTM03 TMIF03
IF1L
TMMK03
MK1L
TMPR003, TMPR103
PR01L,
PR11L
INTAD ADIF ADMK ADPR0, ADPR1
INTIT TMKAIF TMKAMK TMKAPR0, TMKAPR1
INTTM04 TMIF04
IF1H
TMMK04
MK1H
TMPR004, TMPR104
PR01H,
PR11H
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Table 15-4. Flags Corresponding to Interrupt Request Sources (30-pin products) (2/2)
Interrupt Request Flag Interrupt Mask Flag Priority Specification Flag
Interrupt
Source
Register
Register Register
R5F102
R5F103
INTTM05 TMIF05 TMMK05 TMPR005, TMPR105
INTTM06 TMIF06 TMMK06 TMPR006, TMPR106
INTTM07 TMIF07
IF2L
TMMK07
MK2L
TMPR007, TMPR107
PR02L,
PR12L
INTMD MDIF MDMK MDPR0, MDPR1
INTFL FLIF
IF2H
FLMK
MK2H
FLPR0, FLPR1
PR02H,
PR12H
Notes 1. If interrupt source INTST2, INTCSI20, or INTIIC20 occurs, bit 0 of the IF0H register is set to 1. In addition, bit
0 of the MK0H, PR00H, and PR10H registers corresponds to these three interrupt source s.
2. If interrupt sour ce INT ST0, INTCSI00, or INTIIC00 occurs, bit 5 of the IF0H register is set to 1. In addition, bit
5 of the MK0H, PR00H, and PR10H registers corresponds to these three interrupt sources.
3. Do not use channel 1 (at upper level 8-bit timer oper ation) of UART0 and channel (at 8-bit timer operation) 1
of TAU0at the same time because they share flags for the interrupt request sources. If interrupt source
INTSRE0 or INTTM01H occurs, bit 7 of the IF0H register is set to 1. Bit 7 of the MK0H, PR00H, and PR10H
registers corresponds to both interrupt sources.
4. If interrupt source INTST1, INTCSI11, or INTIIC11 occurs, bit 1 of the IF1L register is set to 1. Bit 1 of the
MK1L, PR01L, and PR11L registers corresponds to these three interrupt sources.
5. Do not use channel 3 (at upper level 8-bit timer operation) of UART1 and channel 3 of TAU0 at the s ame time
because they share flags for the interrupt request sources. If interrupt source INTT M03H occurs, bit 2 of the
IF1L register is set to 1. Bit 2 of the MK1L, PR01L and PR11L registers corresponds to these two interrupt
sources.
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15.3.1 Interrupt request flag reg i sters (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when the interrupt request is acknowledged, a reset signal is generated, or an
instruction is executed.
When an interrupt is ackno wledged, the interrupt req uest flag is automaticall y cleared and then t he interrupt routi ne is
entered.
IF0L, IF0H, IF1L, IF1H, and IF2H registers ca n be set by a 1-bit or 8-bit memory manipulation instruction. When the
IF0L and IF0H registers are combined to form 16-bit register IF0, they can be set by a 16-bit memory manipulation
instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 15-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L) (20-, 24-pin product)
Address: FFFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L DMAIF1Note DMAIF0Note PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H TMIF01 TMIF00 IICAIF0 DMAIF1 MIF01H SREIF0 SRIF0
CSIIF01Note
IICIF01Note
STIF0
CSIIF00
IICIF00Note
Address: FFFE2H After reset: 00H R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
IF1L 0 FLIF MDIF KRIF TMKAIF ADIF TMIF03 TMIF02
XXIFXX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
Note Provided in the R5F102 products only.
(Cautions are listed on the ne xt page)
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Figure 15-3. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (30-pin product)
Address: FFFE0H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0L PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 LVIIF WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF0H SREIF0
TMIF01H
SRIF0 STIF0
CSIIF00
IICIF00Note
DMAIF1Note DMAIF0Note SREIF2Note SRIF2Note STIF2Note
CSIIF20Note
IICIF20Note
Address: FFFE2H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1L TMIF03 TMIF02 TMIF01 TMIF00 IICAIF0 SREIF1Note
TMIF03H
SRIF1Note
CSIIF11Note
IICIF11Note
STIF1Note
Address: FFFE3H After reset: 00H R/W
Symbol <7> 6 5 4 3 <2> 1 <0>
IF1H TMIF04 0 0 0 0 TMKAIF 0 ADIF
Address: FFFD0H After reset: 00H R/W
Symbol 7 6 5 4 3 <2> <1> <0>
IF2L 0 0 0 0 0 TMIF07 TMIF06 TMIF05
Address: FFFD1H After reset: 00H R/W
Symbol 7 6 <5> 4 3 2 1 0
IF2H FLIF 0 MDIF 0 0 0 0 0
XXIFXX Interrupt request flag
0 No interrupt request signal is generated
1 Interrupt request is generated, interrupt request status
Note Provided in the R5F102 products only.
Cautions 1. Do not change undefined bit data.
2. When manipulating a flag of the interrup t request flag register, use a 1-bit memory mani pulation
instruction (CLR1). When describing in C language, use a bit manipulation instruction such as
IF0L.0 = 0; or _asm(“clr1 IF0L, 0”); because the compiled assembler must be a 1-bit memory
manipulation instruction (CLR1).
If a program is d escribed in C langu age using an 8-b it memory manip ulation in struction su ch as
IF0L &= 0xfe; and compiled, it becomes the assembler of three instructions.
mov a, IF0L
and a, #0FEH
mov IF0L, a
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In this case, even if the req uest flag of the anoth er bit of the same interrupt req uest flag regi ster
(IF0L) is set to 1 at the timing between mov a, IF0L and mov IF0L, a, the flag is cleared to 0 at
mov IF0L, a. Therefore, care must be exercised when using an 8-bit memory manipulation
instruction in C language.
15.3.2 Interrupt mask flag registers (MK0L, MK0H, MK1L , MK1H, MK2L , MK2H)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing.
TheMK0L, MK0H, MK1L, MK1H, and MK2H registers can be set by a 1-bit or 8-bit memory manipulation instruction.
When the MK0L and MK0H registers are combined to form 16-bit register MK0, they can be set by a 16-bit memory
manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 15-4. Format of Interrupt Mask Flag Registers (MK0L, MK0H, MK1L) (20, 24-pin product)
Address: FFFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L DMAMK1Note DMAMK0Note PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK
Address: FFFE5H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H TMMK01 TMMK00 CAMK0 TMMK03H TMMK03H SREMK0 RMK0
CSIMK01Note
IICMK01Note
TMK0
CSIMK00
IICMK00Note
Address: FFFE6H After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
MK1L 1 FLMK MDMK KRMK TMKAMK ADMK TMMK03 TMMK02
XXMKXX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Note Provided in the R5F102 products only.
Caution Do not change undefined bit data.
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Figure 15-5. Format of In terrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L , MK2H) (30-pin product)
Address: FFFE4H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0L PMK5 PMK4 PMK3 PMK2 PMK1 PMK0 LVIMK WDTIMK
Address: FFFE5H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK0H SREMK0
TMMK01H
SRMK0 STMK0
CSIMK01
IICMK01Note
DMAMK1Note DMAMK0Note SREMK2Note
SRMK2Note STMK2Note
CSIMK20
Note
IICMK20Note
Address: FFFE6H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
MK1L TMMK03 TMMK02 TMMK01 TMMK00 IICAMK0 SREMK1Note
TMMK03H
SRMK1Note
CSIMK11
Note
IICMK11Note
STMK1Note
Address: FFFE7H After reset: FFH R/W
Symbol <7> 6 5 4 3 <2> 1 <0>
MK1H TMMK04 1 1 1 1 TMKAMK 1 ADMK
Address: FFFD4H After reset: FFH R/W
Symbol 7 6 5 4 3 <2> <1> <0>
MK2L 1 1 1 1 1 TMMK07 TMMK06 TMMK05
Address: FFFD5H After reset: FFH R/W
Symbol 7 6 <5> 4 3 2 1 0
MK2H FLMK 1 MDMK 1 1 1 1 1
XXMKXX Interrupt servicing control
0 Interrupt servicing enabled
1 Interrupt servicing disabled
Note Provided in the R5F102 products only.
Caution Do not change undefined bit data.
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15.3.3 Priority specification flag registers (PR00L, PR00H, PR01L , PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,
PR11H, PR12L, PR12H)
The priority specification flag registers are used to set the priority level of the corresponding maskable interrupt.
A priority level is set by using the PR0xy and PR1xy registers in combination (xy = 0L, 0H, 1L).
The PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H, PR12L, and PR12H L
registers can be set by a 1-bit or 8-bit memory manipulation instruction. If the PR00L and PR00H registers, and the
PR10L and PR10H registers are combined to form 16-bit registers PR00 and PR10, they can be set by a 16-bit
memory manipulation instruction.
Reset signal generation sets these registers to FFH.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
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Figure 15-6. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) (20-,
24-pin product)
Address: FFFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L DMAPR01NoteDMAPR01Note PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0
Address: FFFECH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L DMAPR11 DMAPR10 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1
Address: FFFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00H TMPR001 TMPR000 ICAPR00 TMPR003H TMPR001H SREPR00 SRPR00
CSIPR001Note
IICPR001Note
STPR00
CSIPR000
IICPR000Note
Address: FFFEDH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10H TMPR101 TMPR100 ICAPR10 TMPR103H TMPR101H SREPR10 SRPR10
CSIPR101
IICPR101
STPR10
CSIPR100
IICPR100
Address: FFFEAH After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
PR01L 1 FLPR0 MDPR0 KRPR0 TMKAPR0 ADPR0 TMPR003 TMPR002
Address: FFFEEH After reset: FFH R/W
Symbol 7 <6> <5> <4> <3> <2> <1> <0>
PR11L 1 FLPR1 MDPR1 KRPR1 TMKAPR1 ADPR1 TMPR001 TMPR102
XXPR1X XXPR0X Priority Level Selection
0 0 Specifying level 0 (high priority)
0 1 Specifying level 1
1 0 Specifying level 2
1 1 Specifying level 3 (low priority)
Note Provided in the R5F102 products only.
Caution Do not change undefined bit data.
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Figure 15-7. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (30-pin product) (1/2)
Address: FFFE8H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00L PPR05 PPR04 PPR03 PPR02 PPR01 PPR00 LVIPR0 WDTIPR0
Address: FFFECH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10L PPR15 PPR14 PPR13 PPR12 PPR11 PPR10 LVIPR1 WDTIPR1
Address: FFFE9H After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR00H SREPR00
TMPR001H
SRPR00 STPR00
CSIPR000
IICPR000
Note
DMAPR01
Note
DMAPR00
Note
SREPR02
Note
SRPR02
Note STPR02Note
CSIPR020
Note
IICPR020
Note
Address: FFFEDH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR10H
SREPR10
TMPR101H
SRPR10
STPR10
CSPR100
IICPR100
Note
DMAPR11
Note
DMAPR10
Note
SREPR12
Note
SRPR12
Note
STPR12
Note
CSIPR120
Note
IICPR120
Note
Address: FFFEAH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR01L
TMPR003 TMPR002 TMPR001 TMPR000 IICAPR00
SREPR01
Note
TMPR003H SRPR01
Note
CSIPR011
Note
IICPR011
Note
STPR01
Note
Address: FFFEEH After reset: FFH R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
PR11L TMPR103 TMPR102 TMPR101 TMPR100 IICAPR10 SREPR11Note
TMPR103H
SRPR11Note
CSIPR111
Note
IICPR111Note
STPR11Note
Address: FFFEBH After reset: FFH R/W
Symbol <7> 6 5 4 3 <2> 1 <0>
PR01H TMPR004 1 1 1 1 TMKAPR0 1 ADPR0
Address: FFFEFH After reset: FFH R/W
Symbol <7> 6 5 4 3 <2> 1 <0>
PR11H TMPR104 1 1 1 1 TMKAPR1 1 ADPR1
Note Provided in the R5F102 products only.
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Figure 15-7. Format of Priority Specification Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H) (30-pin product) (2/2)
Address: FFFD8H After reset: FFH R/W
Symbol 7 6 5 4 3 <2> <1> <0>
PR02L 1 1 1 1 1 TMPR007 TMPR006 TMPR005
Address: FFFDCH After reset: FFH R/W
Symbol 7 6 5 4 3 <2> <1> <0>
PR12L 1 1 1 1 1 TMPR107 TMPR106 TMPR105
Address: FFFD9H After reset: FFH R/W
Symbol 7 6 <5> 4 3 2 1 0
PR02H FLPR0 1 MDPR0 1 1 1 1 1
Address: FFFDDH After reset: FFH R/W
Symbol 7 6 <5> 4 3 2 1 0
PR12H FLPR1 1 MDPR1 1 1 1 1 1
XXPR1X XXPR0X Priority Level Selection
0 0 Specifying level 0 (high priority)
0 1 Specifying level 1
1 0 Specifying level 2
1 1 Specifying level 3 (low priority)
Caution Do not change undefined bit data.
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15.3.4 External interrupt rising edg e en ab le reg ister (EGP0), external interrupt falling edge en able register (EGN0)
These registers specif y the valid edge for INTP0 to INTP3.
The EGP0 and EGN0 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 15-8. Format of External Interrupt Rising Edge Enable Register (EGP0) and External Interrupt Falling Edge
Enable Register (EGN0)
20-, 24-pin products
Address: FFF38H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP0 0 0 0 0 EGP3 EGP2 EGP1 EGP0
Address: FFF39H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN0 0 0 0 0 EGN3 EGN2 EGN1 EGN0
30-pin products
Address: FFF38H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP0 0 0 EGP5 EGP4 EGP3 EGP2 EGP1 EGP0
Address: FFF39H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN0 0 0 EGN5 EGN4 EGN3 EGN2 EGN1 EGN0
EGPn EGNn INTPn pin valid edge selection (n = 0 to 5)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Caution Select the port mode by clearing the EGPn and EGNn bits to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
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15.3.5 Program status word (PSW)
The program status word is a register used to hold the instruction execution result and the current status for an
interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP0 and ISP1 flags that controls
multiple interrupt servicing are mapped to the PSW .
Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated
instructions (EI and DI). When a vectored interrupt request is acknowledged, if the BRK instruction is executed, the
contents of the PSW are automatically saved into a stack and the IE flag is re set to 0. If a maskable interrupt request
is acknowledged, the contents of the priority specification flag of the acknowledged interrupt are transferred to the
ISP0 and ISP1 flags. The PSW contents are also saved into the stack with the PUSH PSW instruction. They are
restored from the stack with the RETI, RETB, and POP PSW instructions.
Reset signal generation sets PSW to 06H.
Figure 15-9. Configuration of Program Status Word
<7>
IE
<6>
Z
<5>
RBS1
<4>
AC
<3>
RBS0
<2>
ISP1
<1>
ISP0
0
CYPSW
After reset
06H
ISP1
0
0
1
1
Enables interrupt of level 0
(while interrupt of level 1 or 0 is being serviced).
Enables interrupt of level 0 and 1
(while interrupt of level 2 is being serviced).
Enables interrupt of level 0 to 2
(while interrupt of level 3 is being serviced).
Enables all interrupts
(waits for acknowledgment of an interrupt).
IE
0
1
Disabled
Enabled
Priority of interrupt currently being serviced
Interrupt request acknowledgment enable/disable
Used when normal instruction is executed
ISP0
0
1
0
1
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15.4 Interrupt Servicing Operations
15.4.1 Maskable interrupt request ackn owledgment
A maskable interrupt request becomes ackno wledgeable when the interrupt request flag is set to 1 and the mask (MK)
flag corresponding to that int errupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are
in the interrupt enabled state (when the IE flag is set to 1). However, a low-priority interrupt request is not acknowledged
during servicing of a higher pr iority interrupt request.
The times from generation of a maskable interrupt request until vectored interrupt servicing is performed are listed in
Table 15-5 below.
For the interrupt request acknowledgment timing, see Figures 15-11 and 15-12.
Table 15-5. Time from Generation of Maskable Interrupt Until Servicing
Minimum Time Maximum TimeNote
Servicing time 9 clocks 16 clocks
Note Maximum time does not apply when an instruction from the internal RAM area is executed.
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
If two or more maskable interrupt requests are generated simultaneously, the request with a higher priority level
specified in the priority specification flag is acknowledged first. If two or more interrupts requests have the same priority
level, the request with the highest default priority is acknowledged first.
An interrupt request that is held pending is acknowledged when it becomes acknowledgeable.
Figure 15-10 shows the interrupt requ est acknowledgment algorithm.
If a maskable interrupt request is acknowledged, the contents are saved into the stacks in the order of PSW, then PC,
the IE flag is reset (0), and the contents of the priority specification flag corresponding to the acknowledged interrupt are
transferred to the ISP1 and ISP0 flags. T he vector table data determined for eac h interrupt request is the loaded into the
PC and branched.
Restoring from an interrupt is possible by using the RETI instruction.
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Figure 15-10. Interrupt Request Acknowledgment Processing Algorithm
Ye s
No
Ye s
No
Ye s
No
No
Ye s
No
IE = 1?
Vectored interrupt servicing
Start
xxIF = 1?
xxMK = 0?
(xxPR1, xxPR0)
< (ISP1, ISP0)
Yes (interrupt request generation)
Yes (High priority)
No (Low priority)
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Interrupt request held pending
Higher priority
than other interrupt requests
simultaneously
generated?
Higher default priorityNote
than other interrupt requests
simultaneously
generated?
××IF: Interrupt request flag
××MK: Interrupt mask flag
××PR0: Priority specification flag 0
××PR1: Priority specification flag 1
IE: Flag that controls acknowledgment of maskable interrupt request (1 = Enable, 0 = Disable)
ISP0, ISP1: Flag that ind icates the priority level of the interrupt currently being serviced (see Figure 15-9)
Note For the default priority, refer to Table 15-1 and 15-2 Interrupt Sou rce List.
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Figure 15-11. Interrupt Request Acknowledgment Timing (Minimum Time)
xxIF
9 clocks
Instruction InstructionCPU processing
6 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
Figure 15-12. Interrupt Request Acknowledgment Timing (Maximum Time)
xxIF
16 clocks
Instruction Previous interrupt
instruction
CPU processing
6 clocks8 clocks
PSW and PC saved,
jump to interrupt
servicing
Interrupt servicing
program
Remark 1 clock: 1/fCLK (fCLK: CPU clock)
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15.4.2 Software interrupt request acknowledgment
A software interrupt request is acknowledged by BRK instruction execution. Software interrupts cannot be disabled.
If a software interrupt request is acknowledged, the contents are saved into the stacks in the order of the program
status word (PSW), then program counter (PC), the IE flag is reset (0), and the contents of the vector table (0007EH,
0007FH) are loaded into the PC and branched.
Restoring from a software interrupt is possible by using the RET B instruction.
Caution Can not use the RETI instruction for restoring from the software interrupt.
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15.4.3 Multiple interrupt servicing
Multiple interrupt servicing occurs when anot her interrupt request is acknowledged during execution of an interrupt.
Multiple interrupt servicing does not occur unless the int errupt request acknowledgment enabled state is selected (IE =
1). When an interrupt request is ackno wledged, interrupt r equest ackno wledgment b ecomes disabled (IE = 0). Therefore,
to enable multiple interrupt servicing, it is ne cessar y to set (1) the IE flag with the EI instruction dur ing int errupt servic ing to
enable interrupt ackno wledgment.
Moreover, even if interrupts are enabled, multiple interrupt servicing may not be enabled, this being subject to interrupt
priority control. Two types of priority control are available: default priority control and programmable priority control.
Programmable priority control is used for mult iple interrupt servicing.
In the interrupt enable d state, if an interrupt request with a priorit y equal to or higher than that of the i nterrupt currently
being serviced is generate d, it is ackno wledged for multi ple i nterrupt servic ing. If an interr upt with a priority lower than that
of the interrupt currently bei ng serviced is ge nerated during interrupt s ervicing, it is not ack nowledged for multipl e interrupt
servicing. Interrupt requests that are not enabled because interrupts are in the interrupt disabled state or because they
have a lower priority are held pending. When servicing of the current interrupt ends, the pending interrupt request is
acknowledged following execution of at least one main processing instruction e xec ution.
Table 15-6 shows relationship between interrupt requests enabled for multiple interrupt servicing and Figure 15-13
shows multiple interrupt servicing examples.
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Table 15-6. Relationship Between Interrupt Requests Enabled for Multiple Interrupt Servicing
During Interrupt Servicing
Maskable Interrupt Request
Priority Level 0
(PR = 00) Priority Level 1
(PR = 01) Priority Level 2
(PR = 10) Priorit y Level 3
(PR = 11)
Multiple Interrupt Request
Interrupt Being Serviced IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0 IE = 1 IE = 0
Software
Interrupt
Request
ISP1 = 0
ISP0 = 0
× × × × × × ×
ISP1 = 0
ISP0 = 1
× × × × × ×
ISP1 = 1
ISP0 = 0
× × × × ×
Maskable interrupt
ISP1 = 1
ISP0 = 1
× × × ×
Software interrupt × × × ×
Remarks 1. : Multiple interrupt servicing enabled
2. ×: Multiple interrupt servicing disabled
3. ISP0, ISP1, and IE are flags contained in the PSW.
ISP1 = 0, ISP0 = 0: An interrupt of level 1 or level 0 is being serviced.
ISP1 = 0, ISP0 = 1: An interrupt of level 2 is being serviced.
ISP1 = 1, ISP0 = 0: An interrupt of level 3 is being serviced.
ISP1 = 1, ISP0 = 1: Wait for An interrupt acknowledgment.
IE = 0: Interrupt request acknowledgment is disabled.
IE = 1: Interrupt request acknowledgment is enabled.
4. PR is a flag contained in the PR00L, PR00H, PR01L, PR10L, PR1 0H, PR11L registers.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher priority level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
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Figure 15-13. Examples of Multiple Interrupt Servicing (1/2)
Example 1. Multiple interrupt servicing occurs twice
Main processing INTxx servicing INTyy servicing INTzz servicing
EI EI EI
RETI RETI
RETI
INTxx
(PR = 11) INTyy
(PR = 10) INTzz
(PR = 01)
IE = 0 IE = 0 IE = 0
IE = 1 IE = 1 IE = 1
During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt
servicing takes place. Before each interrupt requ est is acknowledged, the EI instruction must al ways be issued to enable
interrupt request acknowledgment.
Example 2. Multiple interrupt servicing does not occur due to priority control
Main processing INTxx servicing INTyy servicing
INTxx
(PR = 10) INTyy
(PR = 11)
EI
RETI
IE = 0
IE = 0
EI
1 instruction execution
RETI
IE = 1
IE = 1
Interrupt request INTyy issue d during servicing of i nterrupt INTxx is not acknowledged because its prior ity is lo wer than
that of INTxx, and multiple interrupt servicing does not take place. The INTyy interrupt request is held pending, and is
acknowledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher prior ity level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled
IE = 1: Interrupt request acknowledgment is enabled.
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Figure 15-13. Examples of Multiple Interrupt Servicing (2/2)
Example 3. Multiple interrupt servicing does not occur because interru pts are not enabled
Main processing INTxx servicing INTyy servicin
g
EI
1 instruction execution
RETI
RETI
INTxx
(
PR = 11)
INTyy
(PR = 00)
IE = 0
IE = 0
IE = 1
IE = 1
Interrupts are not enabled during servicing of interrupt INTxx (EI instruction is not issued), therefore, interrupt request
INTyy is not acknowledged and multiple interrupt servicing does not take place. The INTyy interrupt request is held
pending, and is ackno wledged following execution of one main processing instruction.
PR = 00: Specify level 0 with ××PR1× = 0, ××PR0× = 0 (higher prior ity level)
PR = 01: Specify level 1 with ××PR1× = 0, ××PR0× = 1
PR = 10: Specify level 2 with ××PR1× = 1, ××PR0× = 0
PR = 11: Specify level 3 with ××PR1× = 1, ××PR0× = 1 (lower priority level)
IE = 0: Interrupt request acknowledgment is disabled
IE = 1: Interrupt request acknowledgment is enabled.
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15.4.4 Interrupt request hold
There are instructions where, even if an interrupt request is issued while the instructions are being executed, interrupt
request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt
request hold instructions) are listed b elow.
• MOV PSW, #byte
• MOV PSW, A
• MOV1 PSW. bit, CY
• SET1 PSW. bit
• CLR1 PSW. bit
• RETB
• RETI
• POP PSW
• BTCLR PSW . bit, $addr 20
• EI
• DI
• SKC
• SKNC
• SKZ
• SKNZ
• SKH
• SKNH
• Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR00L, PR00H, PR01L, PR10L, PR10H,
and PR11L registers
Figure 15-14 shows the timing at which inter r upt requests are held pending.
Figure 15-14. Interrupt Request Ho ld
Instruction N Instruction M PSW and PC saved, jump
to interrupt servicing Interrupt servicing
program
CPU processing
××IF
Remarks 1. Instruction N: Interrupt req uest hold instruction
2. Instruction M: Instruction other than interrupt request hold instruction
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CHAPTER 16 KEY INTERRUPT FUNCTION
16.1 Functions of Key Interrupt
In 20- and 24-pin products, a key interrupt (INTKR) can be generated by setting the key return mode register (KRM)
and inputting a rising edge/fall ing e dge to the key interrupt input pins (KR0 to KR9).
Table 16-1. Assignment of Key Interrupt Detection Pins
Flag Description
KRM00 Controls KR0 signal in 1-bit units.
KRM01 Controls KR1 signal in 1-bit units.
KRM02 Controls KR2 signal in 1-bit units.
KRM03 Controls KR3 signal in 1-bit units.
KRM04 Controls KR4 signal in 1-bit units.
KRM05 Controls KR5 signal in 1-bit units.
KRM06Note Controls KR6 signal in 1-bit units.
KRM07Note Controls KR7 signal in 1-bit units.
KRM08Note Controls KR8 signal in 1-bit units.
KRM09Note Controls KR9 signal in 1-bit units.
Note Provide d in 2 4-pin products only.
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16.2 Configuration of Key Interrupt
The key interrupt includes the following hardware.
Table 16-2. Configuration of Key Interrupt
Item Configuration
Input KR0 to KR9
Control register Key return control register (KRCTL)
Key return mode control registers (KRM0, KRM1)
Key return flag register (KRF)
Port mode registers 0, 4, 6, and 12 (PM0, PM4,PM6, PM12)
Port register 0, 4, 6, and 12 (P0, P4, P6, P12)
Figure 16-1. Block Diagram of Key Interrupt
INTKR
Key return mode registers KRM0, KRM1
KRM7KRM8KRM9 KRM6 KRM5 KRM4 KRM3 KRM2 KRM1 KRM0
KR9
KR8
KR7
KR6
KR5
KR4
KR3
KR2
KR1
KR0
16.3 Register Controlling Key Interrupt
The key interrupt function is controlled by the following five registers:
• Key return control register (KRCTL)
• Key return mode control registers (KRM0, KRM1)
• Key return flag register (KRF)
• Port mode registers 0, 4, 6, and 12 (PM0, PM4, PM6, PM12)
• Port registers 0, 4, 6, and 12 (P0, P4, P6, P12)
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16.3.1 Key return cont rol register (KRCTL)
This register controls the usage of the key return flags (KR F0 to KRF5) and sets the detection edge.
The KRCTL register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 16-2. Format of Key Return Control Register (KRCTL)
Address: FFF34H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRCTL KRMD 0 0 0 0 0 0 KREG
KRMD Usage of Key Return Flags (KRF0 to KRF5)
0 Does not use key return flags
1 Uses key return flags
KREG Selection of Detection Edge (KR0 to KR9)
0 Falling edge
1 Rising edge
16.3.2 Key return mode control registers (KRM0, KRM1)
These registers set the key interrupt mode.
The KRM0 and KRM1 registers can be set b y a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 16-3. Format of Ke y Return Control Registers (KRM0, KRM1)
20-pin products
Address: FFF37H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM0 0 0 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00
24-pin products
Address: FFF37H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM0 KRM07 KRM06 KRM05 KRM04 KRM03 KRM02 KRM01 KRM00
Address: FFF36H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
KRM1 0 0 0 0 0 0 KRM09 KRM08
KRM0n Key interrupt mode control
0 Does not detect key interrupt signal
1 Detects key interrupt signal
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Cautions 1. When the bits to be used among the KRM0 to KRM9 bits are set to 1, pull up the relevant input
pins to VDD by an external resistor. For the KR1, KR6 to KR9 pins, the internal pull-up resistor
can be used by setting the relevant bits to 1 in the input pins PU125, PU00 to PU03 (pull-up
resistor registers 12 and 0 (th e bit 5 of PU12 and bits 0 to 3 of PU0)).
2. An interrupt is generated if the target bit of the KRF register is set while the low level is input to
the key interrupt input pin. If no want to generate this interrupt, set the KRM register after
disabling interrupt servicing by using the interrupt mask flag. After waiting for the key interrupt
input low-level width (at least 250 ns), clear the interrupt request flag and enable interrupt
servicing .
2. The bits no t used in th e key interrupt mode can be used as normal ports.
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16.3.3 Key return flag register (KRF)
This register controls the key return flags (KRF0 to KRF5).
The KRF register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 16-4. Format of Ke y Return F lag Register (KRF)
Address: FFF35H After reset: 00H R/W Note
Symbol 7 6 5 4 3 2 1 0
KRF 0 0 KRF5 KRF4 KRF3 KRF2 KRF1 KRF0
KRFn Key interrupt flag
0 No key interrupt signal has been detected.
1 A key interrupt signal has been detected.
Note Writing to 1 is invalid. To clear KRFn, write “0” to the target bits and write “1” to other bits, with the 8-bit
memory manipulation instruction.
Cautions 1. When KRMD = 0, prohibition of set to KRFn = 1.
2. When KRFn bits are 1 and input to the KR6 to KR9 pins exists, keep the input to KR6 to KR9
pins. If clearing KRFn bits is delayed, INTKR does not occur.
For KR6 to KR9, identify channels b y sequentially verifying the input levels.
16.3.4 Port mode registers 0, 4, 6, 12 (PM0, PM4, PM6, PM12)
These registers set the input and output of Port 0, 4, 6, 12 in 1-bit units.
Set 1 to the bit of port mode register (PM0) corresponding to each port when using P00/KR6 to P03/KR9 as a ke y
input in a 24-pin product. Similarly, set 1 to the bit corresponding to each port of PM4, PM12, and PM6 to use
P40/KR0, P125/KR1, P122/KR2, P121/KR3, P60/KR4, and P61/KR5 as a key input.
In addition, set 1 to the bits corresponding with port registers 0, 4, 6, and 12 (P0, P4, P6, P12).
The PM0, PM4, PM6, PM12 registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to FFH.
Figure 16-5. Format of Port Mod e Reg i ster 0 (PM0)
Address: FFF20H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PM0 1 1 1 1 PM03 PM02 PM01 PM00
PM0n I/O mode selection for P0n/KRm pin (n = 0 to 3, m = 6 to 9)
0 Output mode (output buffer on)
1 Input mode (output buffer off)
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CHAPTER 17 STANDBY FUNCTION
17.1 Standby Function and Configuration
17.1.1 Standby function
The standby function reduces the oper ating current of the system, and the following three modes are available.
(1) HALT mode
HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operati on clock is sto pped. If the high-
speed system clock oscillator or high-spee d on-chip oscillator is operati ng before the HALT mode is set, oscillation of
each clock continues. In this mode, the operating current is not decreased as much as in the STOP mode, but the
HALT mode is effective for restarting operation immediately upon interrupt request generation and carrying out
intermittent operations frequently.
(2) STOP mode
STOP instruction execution sets the STOP mode. In the STOP mode, the high-speed system clock oscillator and
high-speed on-chip oscillator stop, stopping the whole system, thereby considerably reducing the CPU operating
current.
Because this mode can be cleared by an interrupt request, it enables intermittent operations to be carried out.
However, because a wait time is required to secure the oscillation stabilization time after the STOP mode is released
when the X1 clock is selected, select the HALT mode if it is necessar y to start processing immediately upon interrupt
request generation.
(3) SNOOZE mode
In the case of CSI00 or UART 0 data recepti on and an A/D conversion r equest by the tim er trigger signal (the i nterrupt
request signal (INTIT)), the STOP mode is exited, the CSI00 or UART0 data is received without operating the CPU,
and A/D conversion is perform ed. This can only b e specified when the high-speed on-chip osc illator clock is selected
for the CPU/peripheral hardware clock (fCLK).
In either of these two modes, all the contents of registers, flags and data memory just before the standby mode is set
are held. The I/O port output latches and output buffer statuses are also held.
Cautions 1. When shifting to the STOP mode, be sure to stop the peripheral hardware operation operating
with X1 oscillation or EXCLK input before executing STOP instruction (other than SNOOZE mode
setting unit).
2 When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby
control register 0 (SSC0) and A/D con verter mode regi st er 2 ( ADM2) befo re sw itch ing to the ST OP
mode. For details, see 11.3 Registers Controlling Serial Array Unit and 10.3 Registers Used in
A/D Converter.
3. The following sequence is recommended for operating current reduction of the A/D converter
when the standby function is used: First clear bit 7 (ADCS) and bit 0 (ADCE) of A/D converter
mode register 0 (ADM0) to 0 to stop the A/D conversion operation, and then execute the STOP
instruction.
4. It can be selected by the option byte whether the low-speed on-chip oscillator continues
oscillating or stops in the HALT or STOP mode. For details, see CHAPTER 23 OPTION BYTE.
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17.1.2 Registers controlling standby function
The standby function is controlled by the following two registers.
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
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(1) Oscillation stabilization time counter status register (OSTC)
This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the follo wing case.
• If the X1 clock starts oscillation while the hig h-spe ed on-chip oscillator clock is being used as the CPU clock.
• If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as
the CPU clock. And the X1 clock is oscillating.
The OSTC register can be read b y a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POR, LVD, WDT, and executing an illegal instruction), the STOP
instruction and MSTOP bit (bit 7 of clock operation status control register (CSC)) = 1 clear this register to 00H.
Figure 17-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFFA2H After reset: 00H R
Symbol 7 6 5 4 3 2 1 0
OSTC MOST
8 MOST
9 MOST
10 MOST
11 MOST
13 MOST
15 MOST
17 MOST
18
Oscillation stabilization time status
MOST
8 MOST
9 MOST
10 MOST
11 MOST
13 MOST
15 MOST
17 MOST
18 fX = 10 MHz fX = 20 MHz
0 0 0 0 0 0 0 0 28/fX max. 25.6
μ
s max. 12.8
μ
s max.
1 0 0 0 0 0 0 0 28/fX min. 25.6
μ
s min. 12.8
μ
s min.
1 1 0 0 0 0 0 0 29/fX min. 51.2
μ
s min. 25.6
μ
s min.
1 1 1 0 0 0 0 0 210/fX min. 102.4
μ
s min. 51.2
μ
s min.
1 1 1 1 0 0 0 0 211/fX min. 204.8
μ
s min. 102.4
μ
s min.
1 1 1 1 1 0 0 0 213/fX min. 819.2
μ
s min. 409.6
μ
s min.
1 1 1 1 1 1 0 0 215/fX min. 3.27 ms min. 1.64 ms min.
1 1 1 1 1 1 1 0 217/fX min. 13.11 ms min. 6.55 ms min.
1 1 1 1 1 1 1 1 218/fX min. 26.21 ms min. 13.11 ms min.
Cautions 1. After the abo ve time has elapsed, the bits are set to 1 in order from th e MOST8
bit and remain 1.
2. The oscillation stabilization time counter counts up to the oscillation
stabilization time set by the oscillation stabilization time select register (OSTS).
If the STOP mode is entered and then released while the high-speed on-chip
oscillator clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
• Desired OSTC register oscillation stabilization time ≤ Oscillation
stabilization time set by OSTS register
Note, therefore, that only the status up to the oscillation stabilization time set
by the OSTS register is set to the OSTC register after STOP mode is released .
3. The X1 clock oscillation stabilization wait time does not include the time until
clock oscillation starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
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(2) Oscillation stabilization time select register (OSTS)
This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released.
When the X1 clock is selected as the CPU cl ock, the operation waits for the time set using the OSTS register after the
STOP mode is released.
When the high-speed on-chip oscillator clock is selected as the CPU clock, confirm with the oscillation stabilization
time counter status register (OST C) that the desired oscill ation stabilization ti me has elapsed after the STOP mode is
released. The oscillation stabi lization time can be checked up to the time set using the OSTC register.
The OSTS register can be set b y an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 07H.
Figure 17-2. Format of Oscillation Stabilization Time Select Register (OSTS)
Address: FFFA3H After reset: 07H R/W
Symbol 7 6 5 4 3 2 1 0
OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0
Oscillation stabilization time selection
OSTS2 OSTS1 OSTS0
fX = 10 MHz fX = 20 MHz
0 0 0 28/fX 25.6
μ
s 12.8
μ
s
0 0 1 29/fX 51.2
μ
s 25.6
μ
s
0 1 0 210/fX 102.4
μ
s 51.2
μ
s
0 1 1 211/fX 204.8
μ
s 102.4
μ
s
1 0 0 213/fX 819.2
μ
s 409.6
μ
s
1 0 1 215/fX 3.27 ms 1.64 ms
1 1 0 217/fX 13.11 ms 6.55 ms
1 1 1 218/fX 26.21 ms 13.11 ms
Cautions 1. To set the STOP mode w hen the X1 clo ck is used as the CPU clock, set th e OSTS register befor e
executing the STOP in struction.
2. Before changing the setting of the OSTS register, confirm that the count operation of the OSTC
register is completed.
3. Do not change the value of the OSTS register during the X1 clock oscillation stabilization time.
4. The oscillation stabilization time counter counts up to the oscillation stabilization time set by
the OSTS register. If the STOP mode is en tered and then relea sed while the h igh-speed on-chip
oscillator clock is being used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC register oscillation stabilization time ≤ Oscillation stabilization time set by
OSTS register
Note, therefore, that only the status up to the oscillation stabilization time set by the OSTS
register is set to the OSTC reg i ster after STOP mode is released.
5. The X1 clock oscillation stabilization wait time does not include the time until clock oscillation
starts (“a” below).
STOP mode release
X1 pin voltage
waveform
a
Remark f
X: X1 clock oscillation frequency
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17.2 Standby Function Operation
17.2.1 HALT mode
(1) HALT mode
The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU
clock before the setting was the high-speed system clock or the high-speed on-chip oscill ator clock.
The operating statuses in the HALT mode are shown below.
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Table 17-1. Operating Statuses in HALT Mode
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock HALT Mode Setting
Item
When CPU Is Operating on
High-speed On-chip Oscillator
Clock (fIH)
When CPU Is Operating on
X1 Clock (fX) When CPU Is Operating on
External Main System Clock
(fEX)
System clock Clock supply to the CPU is stopped
fIH Operation continues (cannot
be stopped) Operation disabled
fX Operation continues (cannot
be stopped) Cannot operate
Main system clock
fEX
Operation disabled
Cannot operate Operation continues (cannot
be stopped)
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
• WUTMMCK0 = 1: Oscillates
• WUTMMCK0 = 0 and WDTON = 0: Stops
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK0 = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU Operation stopped
Code flash memory
Data flash memory
RAM
Operation stopped
Port (latch) Status before HALT mode was set is retained
Timer array unit
12-bit interval timer
Operable
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
• WDSTBYON = 0: Operation stopped
• WDSTBYON = 1: Operation continues (cannot be stopped)
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier and
divider/multiplyaccumulator
DMA controller
Power-on-reset function
Voltage detection function
External interrupt
Key interrupt function
Operable
CRC operation function In the calculation of the RAM area, operable when DMA is executed only
RAM parity error detection
function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Operable when DMA is executed only
Remark Operation stopped: Operation is automatically stopped before switching to the HALT mode.
Operation disabled: Operation is stopped before switching to the HALT mode.
f
IH: High-speed on-chip oscillator clock
f
IL: Low-speed on-chip oscillator clock
fX: X1 clock
fEX: External main system clock
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(2) HALT mode release
The HALT mode can be releas ed by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is
enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address
instruction is executed.
Figure 17-3. HALT Mode Release by Interrupt Request Generation
HALT
instruction
Operating modeHALT modeOperating mode
Oscillation
High-speed system clock or
High-speed on-chip oscillator clock
Status of CPU
Standby release
signal
Note 1
Interrupt
request
Wait
Note 2
Notes 1. Refer to Figure 15-1. Basic Configuration of Interrupt Function
2. Wait time for HALT mode release
• When vectored interrupt servicing is carried out: 15 to 16 clock
• When vectored interrupt servicing is not carried out: 9 to 10 clock
Remark The broken lines indicate the case when the interrupt reque st which has released the stan dby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 17-4. HALT Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
(2) When high-speed on-chip oscillator clock is used as CPU clock
Note For reset processing time, see CHAPTER 18 RESET FUNCTION. For reset processing time for Power-
on-reset circuit (POR) and Voltage detection (LVD) circuit, see CH APTER 19 POWER-ON-RESET
CIRCUIT.
<R>
<R>
<R>
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17.2.2 STOP mode
(1) STOP mode setting and operating statuses
The STOP mode is set by executing the STOP instruction, and it can be set only when the CPU clock before the
setting was the internal high-speed oscil latio n clock, X1 clock, or external main system clock.
Cautions 1. Because the interrupt request signal is used to clear the STOP mode, if there is an interrupt
source with the interrupt request flag set and the interrupt mask flag reset, the STOP mode is
immediately cleared if set. Thus, when a STOP instruction is executed in this situation, the
system returns to its normal operating mode as soon as the wait time set by using the
oscillation stabilization time select register (OSTS) has elapsed. Note that the operating current
during this period is the same as in the HALT mode because the clock is not sto pp ed .
2. When using CSI00, UART0, or the A/D converter in the SNOOZE mode, set up serial standby
control register 0 (SSC0) and A/D converter mode register 2 (ADM2) before switching to the
STOP mode. For details, see 11.3 Registers Controlling Serial Array Unit and 10.3 Registers
Used in A/D Converter.
The operating statuses in the STOP mode are shown below.
<R>
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Table 17-2. Operating Statuses in ST OP Mod e
When STOP Instruction Is Executed While CPU Is Operating on Main System Clock STOP Mode Setting
Item
When CPU Is Operating on
High-speed On-chip Oscillator
Clock (fIH)
When CPU Is Operating on
X1 Clock (fX) When CPU Is Operating on
External Main System Clock
(fEX)
System clock Clock supply to the CPU is stopped
fIH
fX
Main system clock
fEX
Stopped
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
• WUTMMCK = 1: Oscillates
• WUTMMCK = 0 and WDTON = 0: Stops
• WUTMMCK = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU
Code flash memory
Operation stopped
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) Status before STOP mode was set is retained
Timer array unit Operation disabled
12-bit interval timer Operable
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
• WDSTBYON = 0: Operation stopped
• WDSTBYON = 1: Operation continues (cannot be stopped)
Clock output/buzzer output Operation disabled
A/D converter Wakeup operation is enabled (switching to the SNOOZE mode)
Serial array unit (SAU) Wakeup operation is enabled only for CSI00 and UART0 (switching to the SNOOZE mode)
Operation is disabled for anything other than CSI00 and UART0
Serial interface (IICA) Wakeup by address match opera ble
Multiplier and divider/multiply-
accumulator
DMA controller
Operation disabled
Power-on-reset function
Voltage detection function
External interrupt
Key interrupt function
Operable
CRC operation function
RAM parity error
detection function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Operation stopped
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
fIH: High-speed on-chip osci llator clock
f
IL: Low-speed on-chip oscillator clock
f
X: X1 clock
fEX: External main system clock
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Cautions 1. To stop the low-speed on-chip oscillator clock clock in the STOP mode, must previously be set an
option byte to stop the watchdog timer operation in the HALT/STOP mode (bit 0 (WDSTBYON) of
000C0H = 0).
2. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the high-
speed on-chip oscillator clock before the execution of the STOP instruction. Before changing the
CPU clock from the high-speed on-chip oscillator clock to the high-speed system clock (X1
oscillation) after the STOP mode is released, check the oscillation stabilization time with the
oscillation stabilization time counter status register (OSTC).
(2) STOP mode release
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt requ est is generated, the ST OP mode is released. After the oscill ation stabilization
time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt
acknowledgment is disabled, the next address instruction is executed.
Figure 17-5. STOP Mode Release by Interrupt Request Generation (1/2)
(1) When high-speed system clock (X1 oscillation) is used as CPU clock
Normal operation
(high-speed
system clock)
Normal operatio
n
(high-speed
system clock)
OscillatesOscillates
STOP
instruction
STOP mode
S
tandby release
signal
Note 1
Oscillation stopped
High-speed
system clock
(X1 oscillation)
Status of CPU Supply of the
clock is stopped
Interrupt
request
Wait
ST OP mode release time Note 2
Notes 1. Refer to Figure 15-1. Basic Configuration of Interrupt Function
2. Time for STOP mode release
Supply of the clock is stopped: 18.96
μ
s to “whichever is longer 28.95
μ
s and the oscillation
stabilization time (set by OSTS)”
Wait
• When vectored interrupt servicing is carried out: 10 to 11 clock
• When vectored interrupt servicing is not carried out: 4 to 5 clock
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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Figure 17-5. STOP Mode Release by Interrupt Request Generation (2/2)
(2) When high-speed s ystem clock (external clock input) is used as CPU clock
Interrupt
request
STOP
instruction
Standby release signal
Note 1
Status of CPU
High-speed
system clock
(external clock input)
Oscillates
Normal operation
(high-speed
system clock) STOP mode
Oscillation stopped Oscillates
Normal operation
(high-speed
system clock)
Wait
Supply of the
clock is stopped
STOP mode release tuime Note 2
(3) When high-speed on-chip oscillator clock is used as CPU clock
Standby release signal
Note 1
Status of CPU
High-speed on-chip
oscillator clock
Normal operation
(high-speed
on-chip
oscillator clock)
Normal operation
(high-speed on-chip
oscillator clock)
Oscillates
STOP mode
Oscillation stopped
Wait for oscillation
accuracy stabilization
Interrupt
request
STOP
instruction
Oscillates
Wait
Supply of the
clock is stopped
STOP mode release tuime
Note 2
Notes 1. Refer to Figure 15-1. Basic Configuration of Interrupt Function
2. STOP mode release time
Supply of the clock is stopped:19.08 to 32.99
μ
s
Wait
• When vectored interrupt servicing is carried out: 7 clock
• When vectored interrupt servicing is not carried out: 1 clock
Remark The broken lines indicate the case when the interrupt request that has released the standby mode is
acknowledged.
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(b) Release by reset signal generation
When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset
operation, the program is executed after branching to the reset vector address.
Figure 17-6. STOP Mode Release by Reset
(1) When high-speed system clock is used as CPU clock
(2) When high-speed on-chip oscillator clock is used as CPU clock
Note For reset processing time, see CHAPTER 18 RESET FUNCTION. For reset processing time for Power-
on-reset circuit (POR) and Voltage detection (LVD) circuit, see CH APTER 19 POWER-ON-RESET
CIRCUIT.
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17.2.3 SNOOZE mode
(1) SNOOZE mode setting and operating statuses
The SNOOZE mode can only be specified for CSI00, UART0, or the A/D converter. Note that this mode can only be
specified if the CPU clock is the high-speed on-chip oscillator clock.
When using CSI00 or UART0 in the SNOOZE mode, set up serial standby control register 0 (SSC0) before s witching
to the STOP mode. For details, see 11.3 Registers Controllin g Serial Array Unit.
When using the A/D converter in the SNOOZE mode, set up A/D convert er mode register 2 (ADM2) before switching
to the STOP mode. For details, see 10.3 Registers Used in A/D Converter.
In SNOOZE mode rerease, wait status to be only following time.
From STOP to SNOOZE
HS (high-speed main) mode : 18.96 to 28.95
μ
s
LS (low-speed main) mode : 20.24 to 28.95
μ
s
From SNOOZE to normal operation
• When vectored interrupt ser vicing is carried out:
HS (high-speed main) mode : 6.79 to 12.4
μ
s + 7 clock
LS (low-speed main) mode : 2.58 to 7.8
μ
s + 7 clock
• When vectored interrupt ser vicing is not carried out:
HS (high-speed main) mode : 6.79 to 12.4
μ
s + 1 clock
LS (low-speed main) mode : 2.58 to 7.8
μ
s + 1 clock
The operating statuses in the SNOOZE mode are shown below.
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Table 17-3. Operating Statuses in SNOOZE Mode
When Inputting CSI00/UART0 Data Reception Signal or A/D Converter Timer Trigger Signal
While in STOP Mode
STOP Mode Setting
Item When CPU Is Operating on High-speed On-chip Oscillator Clock (fIH)
System clock Clock supply to the CPU is stopped
fIH Operation started
fX
Main system clock
fEX
Stopped
fIL Set by bits 0 (WDSTBYON) and 4 (WDTON) of option byte (000C0H), and WUTMMCK0 bit of
operation speed mode control register (OSMC)
• WUTMMCK = 1: Oscillates
• WUTMMCK = 0 and WDTON = 0: Stops
• WUTMMCK = 0, WDTON = 1, and WDSTBYON = 1: Oscillates
• WUTMMCK = 0, WDTON = 1, and WDSTBYON = 0: Stops
CPU
Code flash memory
Data flash memory
RAM
Operation stopped
Port (latch) Status while in STOP mode continues
Timer array unit Operation disabled
12-bit interval timer Operable
Watchdog timer Set by bit 0 (WDSTBYON) of option byte (000C0H)
• WDSTBYON = 0: Operation stopped
• WDSTBYON = 1: Operation continues (cannot be stopped)
Clock output/buzzer output Operation stopped
A/D converter Operable
Serial array unit (SAU) Operable only CSI00 and UART0 only.
Operation disabled other than CSI00 and UART0.
Serial interface (IICA)
Multiplier and divider/multiply-
accumulator
DMA controller
Operation disabled
Power-on-reset function
Voltage detection function
External interrupt
Key interrupt function
Operable
CRC operation function
RAM parity error
detection function
RAM guard function
SFR guard function
Illegal-memory access
detection function
Operation disabled
Remark Operation stopped: Operation is automatically stopped before switching to the STOP mode.
Operation disabled: Operation is stopped before switching to the STOP mode.
f
IH: High-speed on-chip oscillator clock
f
IL: Low-speed on-chip oscillator clock
f
X: X1 clock
f
EX: External main system clock
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CHAPTER 18 RESET FUNCTION
The following seven operations are available to generate a reset signal.
(1) External reset input via RESET pin
(2) Internal reset by watchdog timer program loop detection
(3) Internal reset by comparison of supply voltage and detection voltage of power-on-reset (POR) circuit
(4) Internal reset by comparison of suppl y voltage of the voltage detector (LVD) and detection voltage
(5) Internal reset by execution of illegal instructionNote
(6) Internal reset by RAM parity error
(7) Internal reset by illegal-memory access
External and internal resets start program execution from the address at 0000H and 0001H when the reset signal is
generated.
A reset is effected when a low level is input to the RESET pin, the watchdog timer overflows, or by POR and LVD
circuit voltage detection, execution of illegal instructionNote, RAM parity error or illegal-memory access, and each item of
hardware is set to the status shown in Tables 18-1.
When a low level is input to the RESET pin, the devic e is reset. It is released from the reset status when a high level is
input to the RESET pin and program execution is started with the high-speed on-chip oscillator clock after reset
processing. A reset by the watchdog timer is automatically released, and program execution starts using the high-speed
on-chip oscillator clock (see Figures 18-2 to 18-4) after reset processing. Reset by POR and LVD circuit supply voltage
detection is automatically released when VDD ≥ VPOR or VDD ≥ VLVD after the reset, and program execution starts using the
high-speed on-chip oscillator clock (see CHAPTER 19 POWER-ON-RESET CIRCUIT and CHAPTER 20 VOLTAGE
DETECTOR) after reset processing.
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip debug
emulator.
Cautions 1. For an external reset, input a low level for 10
μ
s or more to the RESET pin.
(To perform an external reset upon power application, a low level of at least 10
μ
s must be
continued during the period in which the supply voltage is within the operating range (VDD ≥ 1.8
V).)
2. During reset input, the X1 clock, high-speed on-chip oscillator clock, and low-speed on-chip
oscillator clock stop oscillating, and external main system clock input is invalid.
3. Each of the SFRs an d 2nd SFRs are initialized when a reset is applied, so port pin P125 is set for
low-level output (in the case o f an external reset) and P40 becomes hi gh-impedance (in the case
of an external reset or POR reset) or is pulled-up (in the case of other types of reset), and the
other port pins become high impedance.
Remark V
POR: POR power supply rise detection voltage
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Figure 18-1. Block Diagram of Reset Function
Internal bus
Reset control flag
register (RESF)
Set Set Set Set Set
ClearClearClearClearClear
Reset signal to LVIM/LVIS register
Reset signal
Voltage detector reset signal
Power-on reset circuit reset signal
RESF register read signal
Reset signal by execution of illegal instruction
Reset signal by RAM parity error
Reset signal by illegal-memory access
Watchdog timer reset signal
RPERF IAWRFWDTRF
RESET
TRAP LVIRF
Caution An LVD circuit internal reset does not reset the LVD circu i t.
Remarks 1. LVIM: Voltage detection register
2. LVIS: Voltage detection level register
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Figure 18-2. Timing of Reset by RESET Input
Delay
Hi-Z
Normal operationCPU status Normal operation
(high-speed on-chip oscillator clock)
RESET
Internal reset signal
Port pin
High-speed system clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specied by software.
Reset processing for release from the external reset state
Wait for oscillation
accuracy stabilization
Reset period
Note
Note Reset times (times for release from the external reset state)
After the first release of the POR: 0.672 ms (typ.), 0.832 ms (max.) when the LVD is in use.
0.399 ms (typ.), 0.519 ms (max.) when the LVD is off.
After the second release of the POR: 0.531 ms (typ.), 0.675 ms (max.) when the LVD is in use.
0.259 ms (typ.), 0.362 ms (max.) when the LVD is off.
After power is supplied, a voltage stabilization waiting time of about 0.99 ms (typ.) and up to 2.30 ms (max.) is required
before reset processing starts after release of the external reset.
Figure 18-3. Timing of Reset Due to Execution of Illegal Instruction or Watchdog Timer Overflow
Normal operat ion
Re set p e r i o d
(osci l l at ion st op )
CPU st at u s
Internal reset signal
Hi-Z
High-speed syst em clock
(when X1 oscillation is selected)
High-speed on-chip
oscillator clock
Starting X1 oscillation is specified by software.
Normal operat ion
(high-speed on-chip oscillator clock)
Wait for oscillation
accuracy stabilization
Reset processing
Po r t p i n
Watchdog timer overflow
Execution of Illegal
Instruction/
RAM parity error detection/
Illegal-memory access detection
0.0629 ms (typ.)
0.0701 ms (max.)
Caution A w atch do g timer internal reset resets th e watchdog timer.
Remark For the reset timing of the power-on-reset circuit and voltage detector, see CHAPTER 19 POWER-
ONRESET CIRCUIT and CHAPTER 20 VOLTAGE DETECTOR.
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Table 18-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fIH Operation stopped
fX Operation stopped (the X1 and X2 pins are input port mode)
Main system clock
fEX Clock input invalid (the pin is input port mode)
fIL
CPU
Operation stopped
Code flash memory Operation stopped
Data flash memory Operation stopped
RAM Operation stopped
Port (latch) P125 is set to low-level output (in the case of an external reset) or high-impedance (in the case
of a reset other than external reset)
P40 becomes high impedance (in the case of an external reset or POR reset) or pulled-up (in
the case of a reset other than external reset and POR reset)
The port pins except for P125 and P40 become high impedance.
Timer array unit
12-bit Interval timer
Watchdog timer
Clock output/buzzer output
A/D converter
Serial array unit (SAU)
Serial interface (IICA)
Multiplier & divider, multiply-
accumulator
DMA controller
Operation stopped
Power-on-reset function Detection operation possible
Voltage detection function Operation stopped
External interrupt
Key interrupt function
CRC operation function
RAM parity error detection function
RAM guard function
SFR guard function
Illegal-memory access detection
function
Operation stopped
Remark f
IH: High-speed on-chip oscillator clock
fX: X1 oscillation clock
f
EX: External main system clock
f
IL: Low-speed on-chip oscillator clock
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Table 18-2. Hardware Statuses After Reset Acknowledgment (1/3)
Hardware After Reset
AcknowledgmentNote 1
Program counter (PC) The contents of the reset
vector table (0000H,
0001H) are set.
Stack pointer (SP) Undefined
Program status word (PSW) 06H
Data memory Undefined RAM
General-purpose registers Undefined
Processor mode control register (PMC) 00H
Port registers (P0 to P6, P12 to P14 (output latches)) 00H
Port mode registers (PM0 to PM6, PM12, PM14) FFH
Port mode control registers 1, 4 (PMC0, PMC1, PMC4, PMC12, PMC14) FFH
Port input mode registers 1 (PIM0, PIM1) 00H
Port output mode registers 0, 1, 4 (POM0, POM1, POM4, POM5) 00H
Pull-up resistor option registers (PU0, PU1, PU3 to PU5, PU12, PU14) 00H (PU4 is 01H
PU12 of 20-, 24-pin is 2 0H)
Peripheral I/O redirection register (PIOR) 00H
Clock operation mode control register (CMC) 00H
Clock operation status control register (CSC) C0H
System clock control register (CKC) 00H
Oscillation stabilization time counter status register (OSTC) 00H
Oscillation stabilization time select register (OSTS) 07H
Noise filter enable registers 0 (NFEN0) 00H
Peripheral enable register 0 (PER0) 00H
High-speed on-chip oscillator frequency select register (HOCODIV) Undefined
High-speed on-chip oscillator trimming register (HIOTRM) Undefined Note 2
Operation speed mode control register (OSMC) 00H
Timer data registers 00 to 07 (TDR00 to TDR07) 0000H
Timer mode registers 00 to 07 (TMR00 to TMR07) 0000H
Timer status registers 00 to 03 (TSR00 to TSR03) 0000H
Timer input select register 0 (TIS0) 00H
Timer counter registers 00 to 07 (TCR00 to TCR07) FFFFH
Timer channel enable status register 0 (TE0) 0000H
Timer channel start register 0 (TS0) 0000H
Timer channel stop register 0 (TT0) 0000H
Timer clock select register 0 (TPS0) 0000H
Timer output register 0 (TO0) 0000H
Timer output enable register 0 (TOE0) 0000H
Timer output level register 0 (TOL0) 0000H
Timer array unit
Timer output mode registers 0 (TOM0) 0000H
12-bit interval timer Control register (ITMC) 0FFFH
Clock output/buzzer
output Clock output select registers 0, 1 (CKS0, CKS1) 00H
Watchdog timer Enable register (WDTE) 1AH/9AHNote 3
Notes 1. During reset signal generati on or oscillation stabilization time wait, only the PC content s among the hardware
statuses become undefined. All other hardware statuses r emain unchanged after reset.
2. The value after a reset is adjusted at the time of shipment..
3. The reset value of WDT E is decided by the settings of the option bite (WDTON bit).
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Table 18-2. Hardware Statuses After Reset Acknowledgment (2/3)
Hardware After Reset
AcknowledgmentNote 1
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
Mode registers 0 to 2 (ADM0 to ADM2) 00H
Conversion result comparison upper limit setting register (ADUL) FFH
Conversion result comparison lower limit setting register (ADLL) 00H
A/D test register (ADTES) 00H
Analog input channel specification register (ADS) 00H
A/D converter
A/D port configuration register (ADPC) 00H
Serial data registers 00 to 03, 10, 11 (SDR00 to SDR03, SDR10, SDR11) 0000H
Serial status registers 00 to 03, 10, 11 (SSR00 to SSR03, SSR10, SSR11) 0000H
Serial flag clear trigger registers 00 to 03, 10, 11 (SIR00 to SIR03, SIR10,
SIR10) 0000H
Serial mode registers 00 to 03, 10, 11 (SMR00 to SMR03, SMR10, SMR11) 0020H
Serial communication operation setting registers 00 to 03, 10, 11 (SCR00 to
SCR03, SCR10, SCR11) 0087H
Serial channel enable status registers 0, 1 (SE0, SE1) 0000H
Serial channel start registers 0, 1 (SS0, SS1) 0000H
Serial channel stop registers 0, 1 (ST0, ST1) 0000H
Serial clock select registers 0, 1 (SPS0, SPS1) 0000H
Serial output registers 0, 1 (SO0, SO1) 0F0FH
Serial output enable registers 0, 1 (SOE0, SOE1) 0000H
Serial output level registers 0, 1 (SOL0, SOL1) 0000H
Serial array unit (SAU)
Serial standby control register 0 (SSC0) 0000H
IICA shift register 0 (IICA0) 00H
IICA status register 0 (IICS0) 00H
IICA flag register 0 (IICF0) 00H
IICA control register 00 (IICCTL00) 00H
IICA control register 01 (IICCTL01) 00H
IICA low-level width setting register 0 (IICWL0) FFH
IICA high-level width setting register 0 (IICWH0) FFH
Serial interface IICA
Slave address register 0 (SVA0) 00H
Multiplication/division data register A (L) (MDAL) 0000H
Multiplication/division data register A (H) (MDAH) 0000H
Multiplication/division data register B (L) (MDBL) 0000H
Multiplication/division data register B (H) (MDBH) 0000H
Multiplication/division data register C (L) (MDCL) 0000H
Multiplication/division data register C (H) (MDCH) 0000H
Multiplier & divider,
multiply-accumulator
Multiplication/division control register (MDUC) 00H
Key return control register (KRTCL) 00H
Key return mode register (KRM0, KRM1) 00H
Key interrupt
Key return flag register (KRF) 00H
Note During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses r emain unchanged after reset.
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Table 18-2. Hardware Statuses After Reset Acknowledgment (3/3)
Hardware After Reset
AcknowledgmentNote 1
Reset function Reset control flag register (RESF) Note 2
Voltage detection register (LVIM) Note 2 Voltage detector (LVD) Voltage detection level register (LVIS) Notes 2, 3
SFR address registers 0, 1 (DSA0, DSA1) 00H
RAM address registers 0, 1 (DRA0, DRA1) 00H
Byte count registers 0, 1 (DBC0, DBC1) 00H
Mode control registers 0, 1 (DMC0, DMC1) 00H
DMA controller
Operation control registers 0, 1 (DRC0, DRC1) 00H
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H, IF2L,
IF2H) 00H
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,MK1H, MK2L,
MK2H) FFH
Priority specification flag registers 00L, 00H, 01L, PR01H, PR02L, PR02H,
PR10L, PR10H, PR11L, PR11H, PR12L, PR12H (PR00L, PR00H, PR01L,
PR01H, PR02L, PR02H, PR10L, PR10H, PR11L,PR11H, PR12L, PR12H)
FFH
External interrupt rising edge enable register 0, 1 (EGP0, EGP1) 00H
Interrupt
External interrupt falling edge enable register 0,1 (EGN0, EGN1) 00H
Flash memory CRC control register (CRC0CTL) 00H
Flash memory CRC operation result register (PGCRCL) 0000H
CRC input register 00H
CRC data register 0000H
Invalid memory access detection control register (IAWCTL) 00H
Safety functions
RAM parity error control register (RPECTL) 00H
Flash memory Data flash control register (DFLCTL) 00H
BCD correction circuit BCD correction result register (BCDAJ) Undefined
Notes 1. During reset signal generation or oscillati on stabilization time wait, only the PC content s among the hardware
statuses become undefined. All other hardware statuses r emain unchanged after reset.
2. These values vary depend ing on the reset source.
Reset Source
Register
RESET Input Reset by
POR Reset by
Execution of
Illegal
Instruction
Reset by
WDT Reset by
RAM parity
error
Reset by
illegal-
memory
access
Reset by
LVD
TRAP bit Set (1) Held
WDTRF bit Held Set (1) Held
RPERF bit Held Set (1) Held
IAWRF bit Held Set (1)
Held
RESF
LVIRF bit
Cleared (0)
Held Set (1)
LVISEN bit Cleared (0)
LVIOMSK bit
LVIM
LVIF bit Held
LVIS Cleared (00H/01H/81H)
Held
3. The generation of reset signal other than an LVD reset sets as follows.
• When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
• When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
• When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
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18.1 Register for Confirming Reset Source
18.1.1 Reset Control Flag Register (RESF)
Many internal reset generation sources exist in the RL78/G12. The reset control flag register (RESF) is used to store
which source has generated the reset reque st.
The RESF register can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-reset (POR) circuit, and reading the RESF register clear TRAP, WDTRF, RPERF,
IAWRF, and LVIRF flags.
Figure 18-5. Format of Rese t Control Flag Register (RESF)
Address: FFFA8H After reset: 00H Note 1 R
Symbol 7 6 5 4 3 2 1 0
RESF TRAP 0 0 WDTRF 0 RPERF IAWRF LVIRF
TRAP Internal reset request by execution of illegal instructionNote 2
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
WDTRF Internal reset request by watchdog timer (WDT)
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
RPERF Internal reset request t by RAM parity
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
IAWRF Internal reset request t by illegal-memory access
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
LVIRF Internal reset request by voltage detector (LVD)
0 Internal reset request is not generated, or the RESF register is cleared.
1 Internal reset request is generated.
Notes 1. The value after reset varies depending on the reset source.
2. T he illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
Caution 1. Do not read data by a 1-bit memory manipulation instruction.
2. While RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize RAM areas where
data access is to pro ceed and the RAM area + 10 bytes when instructions are fetched from RAM
areas, respectively. Reset signal generation sets R AM parity error resets to enabled (RPERDIS =
0). For details, see 21.3.2 RAM parity error d etectio n fu nction.
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The status of the RESF register when a reset request is generated is sho wn in Table 18-3.
Table 18-3. RESF Register Status When Reset Requ es t Is Gen erated
Reset Source
Flag
RESET Input Reset by
POR Reset by
Execution of
Illegal
Instruction
Reset by
WDT Reset by
RAM parity
error
Reset by
illegal-
memory
access
Reset by
LVD
TRAP bit Set (1) Held Held Held Held
WDTRF bit Held Set (1) Held Held Held
RPERF bit Held Held Set (1) Held Held
IAWRF bit Held Held Held Set (1) Held
LVIRF bit
Cleared (0) Cleared (0)
Held Held Held Held Set (1)
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
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CHAPTER 19 POWER-ON-RESET CIRCUIT
19.1 Functions of Power-on-reset Circuit
The power-on-reset circuit (POR) has the follo wing functions.
• Generates internal reset signal at power on.
The reset signal is released when the supply voltage (VDD) exceeds 1.51 V ±0.03 V. However, keep on the reset
status until the operation v oltage range shown in 28.4 AC Characteristics with the voltage d etector or the external
reset pin.
• Compares supply voltage (V DD) and detection voltage (VPDR = 1.50 V ±0.0 3 V), generates internal reset signal when
VDD < VPDR. However, if the operation voltage drops, enter the STOP mode or execute areset with the voltage
detector or the reset pin, before falling below the operation voltage range.
Caution If an internal reset signal is generated in the POR circuit, TRAP, WDTRF, RPERF, IAWRF, and
LVIRF flags of the reset control flag register (RESF) is cleared.
Remark This product incorporates multiple hardware functions that generate an internal reset signal. A flag that
indicates the reset source is located in the reset control flag register (RESF) for when an internal reset
signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illegal instruction execution,
RAM parity error, or illegal-m emor y access. The RESF register is not clea red to 00H and the flag is set to
1 when an internal reset signal is generated by the watchdog timer (WDT), voltage-detector (LVD), illega l
instruction execution, RAM parity error, or illegal-memory access.
For details of the RESF register, see CH APTER 18 RESET FUNCTION.
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19.2 Configuration of Po wer-on-reset Circuit
The block diagram of the power-on-reset circuit is shown in Figure 19-1.
Figure 19-1. Block Diagram of Power-on-reset Circuit
−
+
Reference
voltage
source
Internal reset signal
VDD
VDD
19.3 Operation of Power-on-reset Circuit
• An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection
voltage (VPDR = 1.51 V ±0.03 V), the reset status is released. However, keep on the reset status until the operation
voltage range shown in 28.4 AC Ch aracteristics with the voltage detector or the exter nal reset pin
• The supply voltage (VDD) and detection voltage (VPDR = 1.50 V ±0.03 V) are compared. When VDD < VPDR, the
internal reset signal is generated. Ho wever, if the operation voltage drops, enter the STOP mode or exec ute areset
with the voltage detector or the reset pin, before falling below the operation voltage range.
The timing of generation of the intern al reset signal by the power-on-reset circuit and voltage detector is shown below.
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
R01UH0200EJ0110 Rev.1.10 679
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Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (1/3)
(1) When the external reset input via RESET pin is used
V
PDR
=
1.50 V (TYP.)
V
POR
=
1.51 V (TYP.)
CPU
0V
Supply voltage
(V
DD
)
Operating voltage range
lower limit setting
10 s min.
RESET signal
High-speed on-chip
oscillator clock (fIH)
High-speed
system clock (fMX)
(when X1 oscillation
is selected)
Operation
stops
Internal reset signal
Normal operation
(high-speed on-chip
oscillator clock)Note 2
Starting oscillation is
specified by software
Operation stops
Normal operation
(high-speed on-chip oscillator clock)Note 2
Reset
period
(oscillation
stop)
Reset processing time
by the external reset release
Starting oscillation is
specified by software
Voltage stabilization wait time 0.99 ms (TYP.), 2.30 ms (MAX.) Voltage stabilization wait time 0.99 ms (TYP.), 2.30 ms (MAX.)
Note 3
Reset processing time
by the external reset
release
Note 3
Wait for oscillation
accuracy stabilizationNote 1
Wait for oscillation
accuracy stabilizationNote 1
Notes 1. The internal reset processing time includes the oscillation accuracy stabilization time of the hi gh-speed on-
chip oscillator clock.
2. T he high-speed on-chip oscillator clock ca n be switched to the high-sp eed system clock as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
3. The time until normal operation is started require the following “the reset processing time by the external
reset release” required after RESET signal has been set to high-level(1), in addition to “the voltage
stabilization wait time” required after the voltage has reached VPOR (1.51 V (TYP.)).
Reset processing time by the external reset release:
0.672 ms (TYP.), 0.832 ms (MAX.) (When LVD is used)
0.399 ms (TYP.), 0.519 ms (MAX.) (When LVD off)
Remark V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
<R>
<R>
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
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Sep. 28, 2012
Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (2/3)
(2) LVD interrupt & reset mode (option byte 000C1H/L VIMDS1, L VIMDS0 = 1, 0)
High-speed on-chip
oscillator clock (f
IH
)
High-speed
syst em cl ock (f
MX
)
(when X1 oscillation
is selected)
Op erat i on
st op s
Su p p l y v o l t ag e
(V
DD
)
Wait for oscillation accuracy stabilization
Normal operation
(High-speed on-chip
oscillator clock)Note 1
Normal operation
(High-speed on-chip
oscillator clock)
Note 1
Operat ion st ops
Re se t
period
(oscillation
st op )
Internal reset signal
V
PDR
= 1.50 V (TYP.)
V
LVDH
V
POR
= 1.51 V (TYP.)
CPU
INTLVI
0 V
V
LVDL
Note 3
Starting oscillation is
specified by software
Starting oscillation is
specified by software
Reset processing time by LVD
Note 4
Voltage stabilization wait time and reset processing time by POR
1.64 ms( TYP.), 3.10 msM (AX.)
Note 2
Operating voltage range lower limit setting
Note 2
Wait for oscillation accuracy stabilization
Voltage stabilization wait time and
reset processing time by POR
1.64 ms( TYP.), 3.10 msM (AX.)
Reset processing time by LVD
Note 4
Notes 1. The high-speed on-chip oscill ator clock can be switched to the hig h-speed system clock as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
2. The internal r eset processing time includes the osc illation accuracy stabiliz ation time of the high-speed on-
chip oscillator clock.
3. After the first interrupt request signal (INTLVI) is generated, the LVIL and LVIMD bits of the voltage
detection level register (LVIS) are automaticall y set to 1. If the operating voltag e returns to 1.8 V or higher
without falling below the voltage detection level (VLVDL), after INTLVI is generated, perform the required
backup processing, and then use software to specify the initial settings in order. (see Figure 20-8 Initial
Setting of Interrupt and Reset Mode)
4. T he time until normal operation is started r equire the following “the r eset processing time by LVD” required
after the voltage has reach ed LVD d etection l evel (V LVDH), in addition t o “the reset pr oces sing tim e by PO R”
and “the voltage stabilization wait time” required after the voltage has reached VPOR (1.51 V (TYP.)).
Reset processing time by LVD: 0 ms to 0.0701 ms (MAX.)
Remark VLVDH, VLVDL: LVD detection voltage
V
POR: POR power supply rise detection voltage
V
PDR: POR power supply fall detection voltage
<R>
<R>
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
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Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (3/3)
(3) LVD reset mode (option byte 000C1H/ LVIMDS1, LVIMDS0 = 1, 1)
V
PDR
= 1.50 V (TYP.)
V
POR
= 1.51 V (TYP.)
CPU
0 V
V
LVD
Reset processing time by LVD
Note 3
Normaloperation
(High-speedon-chip
oscillatorclock)
Note1
Operationstops
Reset
period
(oscillation
stop)
Normaloperation
(High-speedon-chip
oscillatorclock)
Note1
Waitforoscillation
accuracystabilization
Note2
Waitforoscillation
accuracystabilization
Note2
Reset
period
(oscillation
stop)
Supplyvoltage
(V
DD)
Internal reset signal
High-speed
systemclock(f
MX
)
(whenX1oscillation
isselected)
High-speedon-chip
oscillatorclock(f
IH
)
Operation
stops
Normaloperation
(High-speedon-chip
oscillatorclock)
Note1
Waitforoscillation
accuracystabilization
Note2
Operating voltage range
lower limit setting
Voltage stabilization wait time and
Reset processing time by POR
1.64 ms (TYP.), 3.10 ms (MAX.)
Voltage stabilization wait time and
Reset processing time by POR
1.64 ms (TYP.), 3.10 ms (MAX.)
Reset processing time by LVD
Note 3
Resetprocessingtime
Note4
Notes 1. The high-speed on-chip oscill ator clock can be switched to the hig h-speed system clock as the CPU clock.
To use the X1 clock, use the oscillation stabilization time counter status register (OSTC) to confirm the
lapse of the oscillation stabilization time.
2. The internal r eset processing time includes the osc illation accuracy stabiliz ation time of the high-speed on-
chip oscillator clock.
3. The time until normal operation is started require th e following “the reset processing time b y LVD” required
after the voltage has reached LVD detection level (VLVD), in addition to “the reset processing time by POR”
and “the voltage stabilization wait time” required after the voltage has reached VPOR (1.51 V (TYP.)).
Reset processing time by LVD: 0 ms to 0.0701 ms (MAX.)
4. When supply voltage falls and returns after only an internal reset occurs by the voltage detection circuit
(LVD), the following “the reset processing time by LVD” is required after the voltage has reached LVD
detection level (VLVD).
Reset processing time by LVD: 0.0629 ms (TYP.), 0.0701 ms (MAX.)
<R>
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
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19.4 Cautions for Power-on-reset Cir cuit
In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POR detection voltage
(VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release
of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
<Action>
After releasing the reset signal, wait for the supply voltage fl uctuation perio d of each system by that uses a timer, and
then initialize the ports.
Figure 19-3. Example of Software Processing After Reset Release (1/2)
(a) If supply voltage fluctuation is 50 ms or less in vicinity of POR detection voltage
; Check the reset source, etc.
Note 2
Note 1
Reset
Initialization
processing <1>
50 ms has passed?
(TMIF0n = 1?)
Initialization
processing <2>
Setting timer array unit
(to measure 50 ms)
; Initial setting for port.
Setting of division ratio of system clock,
such as setting of timer or A/D converter.
Ye s
No
Power-on-reset
Clearing WDT
; f
CLK
= High-speed on-chip oscillator clock (4 MHz)
Source: f
MCK
(4 MHz) /2
7
,
where comparison value = 789: Approx. 50 ms
Timer starts (TS0n = 1).
Notes 1. If reset is generated ag ain during this period, initialization processing <2> is not started.
2. A flowchart is shown on the next page.
Remark n = 0 to 7
RL78/G12 CHAPTER 19 POWER-ON-RESET CIRCUIT
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Figure 19-3. Example of Software Processing After Reset Release (2/2)
(b) Checking reset source
Yes
No
No
Check reset source
Power-on-reset/external
reset generated
Reset processing by
watchdog timer
Reset processing by
voltage detector
No
WDTRF of RESF
register = 1?
Yes
No Reset processing by
illegal instruction execution
Note
TRAP of RESF
register = 1?
Yes
Reset processing by
RAM parity error
Yes
LVIRF of RESF
register = 1?
RPERF of RESF
register = 1?
No Reset processing by
illegal-memory access
Yes
IAWRF of RESF
register = 1?
Note The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
RL78/G12 CHAPTER 20 VOLTAGE DETECTOR
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CHAPTER 20 VOLTAGE DETECTOR
20.1 Functions of Voltage Detector
The voltage detector (LVD) has the following functions.
• The LVD circuit compares the supply voltage (VDD) with the detection voltage (VLVDH, VLVDL), and generates an
internal reset or internal interrupt signal.
• The detection level for the power sup ply detection voltage (V LVDH, VLVDL) can be selected by usin g the option byte as
one of 12 levels (For details, see CHAPTER 23 OPTION BYTE).
• Operable in ST OP mode.
• The following three operation modes can be selected b y using the option byte.
(a) Interrupt & reset mode (option byte LVIMDS1, LVIMDS0 = 1, 0)
For the two detection voltag es selected by the optio n b yte 000C1H, the high-volta ge detection lev el (VLVDH) is used
for generating interrupts and endin g resets, a nd the low-voltage detection level (VLVDL) is used for triggering resets.
(b) Reset mode (option byte LVIMDS1, LVIMDS0 = 1, 1)
The detection voltage (VLVD) selected by the option byte 000C1H is used for triggeri ng and ending resets.
(c) Interrupt mode (option byte LVIMDS1, LVIMDS0 = 0, 1)
The detection voltage (VLVD) selected by the option byte 000C1H is used for generating interrupts/reset release.
Two detection voltages (VLVDH, VLVDL) can be specified in the interrupt & reset mode, and one (VLVD) can be sp ecified in
the reset mode and interrupt mode.
The reset and interrupt signals are generated as follows according to the option byte (LVIMDS0, LVIMDS1) selecti on.
Interrupt & reset mode
(LVIMDS1, LVIMDS0 = 1, 0)
Reset mode
(LVIMDS1, LVIMDS0 = 1, 1)
Interrupt mode
(LVIMDS1, LVIMDS0 = 0, 1)
Generates an internal interrupt signal
when VDD < VLVDH, and an internal reset
when VDD < VLVDL.
Releases the reset signal when VDD ≥
VLVDH.
Generates an internal reset signal when
VDD < VLVD and releases the reset signal
when VDD ≥ VLVD.
Generates an internal interrupt signal
when VDD drops lower than VLVD (VDD <
VLVD) or when VDD becomes VLVD or
higher
(VDD ≥ VLVD).
Releases the reset signal when VDD ≥
VLVD at power on.
While the voltage detector is oper ating, whether the supply voltage is m ore than or l ess than the detection level can be
checked by reading the voltage detection flag (LVIF: bit 0 of the voltage detection register (LVIM)).
Bit 0 (LVIRF) of the reset control flag r egister (RESF) is set to 1 if reset occurs. For details of the RESF register, see
CHAPTER 18 RESET FUNCTION.
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20.2 Configuration of Voltage Detector
The block diagram of the voltage detector is shown in Figure 20-1.
Figure 20-1. Block Diagram of Voltage Detector
Voltage detection
level register (LVIS)
Voltage detection
register (LVIM)
VDD
LVIOMSK
INTLVI
Internal reset signal
VDD
LVILV
LVIMD
LVIF
VLVDH
VLVDL
Voltage detection
level selector
Reference
voltage
source
Selector
Internal bus
Controller
Option byte (000C1H)
VPOC2 to VPOC0
-
+
N-ch
Option byte (000C1H)
LVIS1, LVIS0
LVISEN
20.3 Registers Controlling Voltage Detector
The voltage detector is controlled by the following registers.
• Voltage detection reg ister (LVIM)
• Voltage detection level register (LVIS)
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20.3.1 Voltage detection register (LVIM)
This register is used to specify whether to enable or disable rewriting the voltage detection level register (LVIS), as
well as to check the LVD output mask status.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 20-2. Format of Voltage Detection Register (L VIM)
Address: FFFA9H After reset: Note 1 R/W Note 2
Symbol <7> 6 5 4 3 2 <1> <0>
LVIM LVISEN 0 0 0 0 0 LVIOMSK LVIF
LVISEN
Specification of whether to enable or disa ble rewriting the voltage detection level
register (LVIS)
0 Disabling rewriting
1
Enabling rewriting Note 3
LVIOMSK Mask status flag of LVD output
0 Mask is invalid
1
Mask is valid Notes 3, 4
LVIF Voltage detection flag
0 Supply voltage (VDD) ≥ detection voltage (VLVD), or when LVD operation is disabled
1 Supply voltage (VDD) < detection voltage (VLVD)
Notes 1. The reset value changes depending on the reset source.
If the LVIS register is reset by LVD, it is not reset but holds the current value. The value of this LVISEN is
reset to “0” if a reset other than by LVD is effected.
2. Bits 0 and 1 are read-only.
3. T his can only be used when LVIMDS1 and LVIMDS0 are se t to 1 and 0 (interrupt and reset mode) by the
option byte (other mode is invalid).
4. LVIOMSK bit is automatically set to “1” in the following periods and reset or interruption by LVD is masked.
• Period during LVISEN = 1
• Waiting period from the time when LVD interrupt is generated until LVD detection voltage becomes
stable
• Waiting period from the time when the val ue of LVILV bit changes until LVD detection v oltage becomes
stable
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20.3.2 Voltage detection level register (LVIS)
This register selects the voltage detection level.
This register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation input sets this register to 00H/01H/81H Note 1.
Figure 20-3. Format of Voltage Detection Level Select Register (LVIS)
Address: FFFAAH After reset: 00H/01H/81H Note 1 R/W
Symbol <7> 6 5 4 3 2 1 <0>
LVIS LVIMD 0 0 0 0 0 0 LVILV
LVIMD Note
2 Operation mode of voltage detection
0 Interrupt mode
1 Reset mode
LVILV Note 2 LVD detection level
0 High-voltage detection level (VLVDH)
1
Low-voltage detection level (VLVDL or VLVD)
Notes 1. The reset value changes depending on the reset source and the setting of the option byte.
This register is not cleared (00H) by LVD reset.
The generation of reset signal other than an LVD reset sets as follo ws.
• When option byte LVIMDS1, LVIMDS0 = 1, 0: 00H
• When option byte LVIMDS1, LVIMDS0 = 1, 1: 81H
• When option byte LVIMDS1, LVIMDS0 = 0, 1: 01H
2. Writing “0” can only be allowed when LVIMDS1 and LVIMDS0 are set to 1 and 0 (interrupt and reset
mode) by the option byte. In other cases, writing is not allowed and the value is switched automatically
when reset or interrupt is generated.
Cautions 1. Only rewrite the value of the LVIS register after setting the LVISEN bit (bit 7 of the LVIM register) to 1.
2. Specify the LVD operation mode and detection voltage (VLVDH, VLVDL) by using the option byte
(000C1H). Table 20-1 shows the option byte (000C1H ) settings. For details about the option byte, see
CHAPTER 23 OPTION BYTE.
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Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (1/2)
Address: 000C1H
7 6 5 4 3 2 1 0
VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0
• When used as interrupt & reset mode
Detection voltage Option byte Setting Value
VLVDH VLVD Mode setting
Rising
edge Falling
edge Falling
edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.98 V 1.94 V 1 0
2.09 V 2.04 V 0 1
3.13 V 3.06 V
1.84 V 0 1
0 0
2.61 V 2.55 V 1 0
2.71 V 2.65 V 0 1
3.75 V 3.67 V
2.45 V 1 0
0 0
2.92 V 2.86 V 1 0
3.02 V 2.96 V 0 1
4.06 V 3.98 V
2.75 V
1 0 0
1 1
0 0
Other than above Setting prohibited
• When used as reset mode
Detection voltage Option byte Setting Value
VLVD Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V
1 1 0
1 1 0 0
Other than above Setting prohibited
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Table 20-1. LVD Operation Mode and Detection Voltage Settings for User Option Byte (000C1H) (2/2)
Address: 000C1H
7 6 5 4 3 2 1 0
VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0
• When used as interrupt mode
Detection voltage Option byte Setting Value
VLVD Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V
0 1 0
1 1 0 0
Other than above Setting prohibited
• When LVDOFF
Detection voltage Option byte Setting Value
VLVDH Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0 VPOC2
VPOC1 VPOC0 LVIS1 LVIS0
− − × 1 1 × × × ×
Caution To set the LVD off, execute the external reset when the power supply is turned on, and then release the
reset in the operation voltage range.
HS (high-speed main) mode: VDD = 2.7 to 5.5 V@1 to 24 M Hz
VDD = 2.4 to 5.5 V@1 to 16 MHz
LS (low-speed main) mode: VDD = 1.8 to 5.5 V@1 to 8 MHz
Remark ×: don’t care
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20.4 Operation of Voltage De tector
20.4.1 When used as reset mode
• When
starting operation
Start in the following initial setting state.
Specify the operation mode (the reset mode (LVIMDS1, LVIMDS0 = 1, 1)) and the detection voltage (VLVD) by
using the option byte 000C1H .
• Clear bit 7 (LVISEN) of the voltage detection register (LV IM) to 0 (disable rewriting of voltage detection level
register (LVIS))
• When the option byte LVIMDS1 and LVIMDS0 are set to 1, the initial value of the LVIS register is set to 81H.
Bit 7 (LVIMD) is 1 (reset mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD).
Figure 20-4 shows the timing of the internal reset signal generated by the voltage detector.
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Figure 20-4. Timing of Voltage Detector Internal Reset Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 1)
H
H
Supply voltage (V
DD
)
LVIRF flag
(RESF register)
LVD reset signal
POR reset signal
Internal reset signal
LVIMD flag
LVIF flag
V
LVD
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
LVILV flag
Cleared by
software Cleared by
software
Not cleared
Not cleared
Not
cleared
Not
cleared
Time
Cleared
Cleared
Remark V
POR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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20.4.2 When used as interrupt mode
• When starting operation
Specify the operation mode (the interrupt mode (LVIMDS1, LVIMDS0 = 0, 1)) and the detection voltage (VLVD)
by using the option byte 000C1H.
Start in the following initial setting state.
• Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
• When the option b yte LVIMDS1 is cl ear to 0 and LVIMDS0 is set to 1, the initial valu e of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 1 (low-voltage detection level: VLVDL or VLVD).
Figure 20-5 shows the timing of the internal interrupt signal generated by the voltage detector.
RL78/G12 CHAPTER 20 VOLTAGE DETECTOR
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Figure 20-5. Timing of Voltage Detector Internal Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 0, 1)
H
INTLVI
LVIIF flag
Supply voltage (V
DD
)
V
LVD
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
LVIMK flag
(set by software)
LVIMD flag
LVIF flag
LILV flag
Time
Cleared
LVD reset signal
POR reset signal
Internal reset signal
H
Note
Cleared by
software
Note The LVIMK flag is set to “1” by reset signal generation.
Remark V
POR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
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20.4.3 When used as interrupt and reset mode
• When starting operation
Specify the operation mode (the interrupt and reset (LVIMDS1, LVIMDS0 = 1, 0)) and the detection voltage
(VLVDH, VLVD) by using the option byte 000C1H.
Start in the following initial setting state.
• Set bit 7 (LVISEN) of the voltage detection register (LVIM) to 0 (disable rewriting of voltage detection level
register (LVIS))
• When the option b yte LVIMDS1 is s et to 1 and LVIMDS0 is clear to 0, the initial value of the LVIS register is
set to 00H.
Bit 7 (LVIMD) is 0 (interrupt mode).
Bit 0 (LVILV) is 0 (high-voltage detection level: VLVDH).
Figure 20-6 shows the timing of the internal reset signal and interrupt signa l generated by the voltage detector.
Perform the processing according to Figure 20-7 Processing Procedure After an Interrupt Is Generated in
interrupt and reset mode and Fig ure 20- 8 In it ial Sett ing of I nterru p t and Reset M o d e i n int erru p t and reset
mode.
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Figure 20-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (1/2)
H
Note 1
V
LVDL
V
LVDH
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
Supply voltage (V
DD
)
INTLVI
LVIIF flag
Operation status
Internal reset signal
LVIMK flag
(set by software)
LVD reset signal
POR reset signal
LVIRF flag
LVIMD flag
LVILV flag
LVIF flag
LVIOMSK flag
LVISEN flag
(set by software)
Cleared by
software
Note 2
Cleared by
software
Note 3
Cleared
Cleared
Normal
operation
RESET RESET Normal
operation
Save
processing
Cleared by
software
Wait for stabilization by software (400 μ s or 5 clocks of f
IL
)
Note 3
Cleared by software
Time
RESET
Normal
operation
If a reset is not generated after releasing the mask,
determine that a condition of V
DD
becomes V
DD
≥
V
LVDH
,
clear LVIMD bit to 0, and the MCU shift to normal operation.
Save processing
{
(Notes and Remark are listed on the next page.)
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Figure 20-6. Timing of Voltage Detector Reset Signal and Interrupt Signal Generation
(Option Byte LVIMDS1, LVIMDS0 = 1, 0) (2/2)
H Note 1
VLVDL
VLVDH
V
POR
= 1.51 V (TYP.)
V
PDR
= 1.50 V (TYP.)
Supply voltage (VDD)
LVIMK flag
(set by software)
Operation status
INTLVI
LVIIF flag
Internal reset signal
LVD reset signal
POR reset signal
LVIRF flag
LVIF flag
LVIOMSK flag
LVISEN flag
(set by software)
Cleared by
software
Normal
operation
RESET
Cleared by
software Note 2
Cleared by
software Note 3
Time
Cleared by software
RESET RESET
Normal
operation
Save
processing
Save processing
Wait for stabilization by software (400 μ s or 5 clocks of f
IL
)
Note 3
Cleared
Cleared
When a condition of VDD is VDD < VLVDH after releasing the mask,
a reset is generated because of LVIMD = 1 (reset mode).
LVIMD flag
LVILV flag
(Notes and Remark are listed on the next page.)
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Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. After an interrupt is generated, perform the processing according to Figure 20-7 Processing Procedure
After an Interrupt Is Generated in interrupt and reset mode.
3. After a reset is released, p erform the process ing according to Figure 20-8 Initial Setting of Interrupt and
Reset Mode in interrupt and reset mode.
Remark V
POR: POR power supply rise detection voltage
VPDR: POR power supply fall detection voltage
Figure 20-7. Processing Procedure After an Interrupt Is Generated
Perform required save processing.
INTLVI generated
LVISEN = 1 Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1).
LVISEN = 0 Set the LVISEN bit to 0 to enable voltage
detection.
Save processing
Yes
No
LVD res et generat ed
The MCU returns to normal operation when
internal reset by voltage detector (LVD) is not
generated, since a condition of VDD becomes
VDD ≥ VLVDH.
Set the LVILV bit to 0 to set the high-voltage
detection level (VLVDH).
LVILV = 0
Normal operation
LVISEN = 1 Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
LVISEN = 0 Set the LVISEN bit to 0 to enable voltage
detection.
Set the LVIMD bit to 0 to set interrupt mode.
LVIMD = 0
Reset
No
Yes
LVIOMSK = 0
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When setting an interrupt and reset mode (LVIMDS1, LVIMDS0 = 1, 0), voltage detection stabilization wait time for 400
μ
s or 5 clocks of fIL is necessary after LVD reset is releas ed (LVIRF = 1). After waiting until voltage detection stabilizes,
(0) clear the LVIMD bit for initialization. While voltage detection stabilization wait time is being counted and when the
LVIMD bit is rewritten, set LVISEN to 1 to mask a reset or interrupt generation by LVD.
Figure 20-8. shows the procedure for initial setting of interrupt and reset mode.
Figure 20-8 Initial Setting of Interrupt and Reset Mode
Remark f
IL: Low-speed on-chip oscilla t or clock frequency
Set the LVIMD bit to 0 to set interrupt mode.
Refer to Figure 20-9. Checking reset source.
Power application
LVISEN = 1
Voltage detection stabilization
wait time
LVIMD = 0
Set the LVISEN bit to 1 to mask voltage detection
(LVIOMSK = 1)
LVISEN = 0
Normal operation
Set the LVISEN bit to 0 to enable voltage detection.
Reset source determine
Count 400
μ
s or 5 clocks of fIL by software.
Yes
No LVIRF = 1? Check internal reset generation by LVD circuit
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20.5 Cautions for Voltage Detector
(1) Checking reset source
When a reset occurs, check the reset source by using the fol lowing method.
Figure 20-9. Checking reset so urce
Yes
No
No
Check reset source
Power-on-reset/external
reset generated
Reset processing by
watchdog timer
Reset processing by
voltage detector
No
WDTRF of RESF
register = 1?
Yes
No Reset processing by
illegal instruction execution Note
TRAP of RESF
register = 1?
Yes
Reset processing by
RAM parity error
Yes
LVIRF of RESF
register = 1?
RPERF of RESF
register = 1?
No Reset processing by
illegal-memory access
Yes
IAWRF of RESF
register = 1?
Note When instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
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(2) Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
There is some delay from the time supply voltage (VDD) < LVD detection voltage (VLVD) until the time LVD reset has
been generated.
In the same way, there is also some delay from the time LVD detection voltage (VLVD) ≤ supply voltage (VDD) until the
time LVD reset has been released (see F igure 20-10).
Figure 20-10. Delay from the time LVD reset source is generated until the time LVD reset has been generated or released
V
LVD
Supply voltage (V
DD
)
LVD reset signal
<1>
Time
<1>
<1>: Detection del ay (300
μ
s (MAX.))
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CHAPTER 21 SAFETY FUNCTIONS
21.1 Overvie w of Safety Functions
The following safety functions are provided in the RL78/G12 to comply with the IEC60730 and IEC61508 safety
standards.
These functions enable the microcontroller to self-diagnose abnormalities and stop operating if an abnormality is
detected.
(1) Flash memory CRC operation function
This detects data errors in the flash memory by performing CRC operations.
This can be used for checking various data in addition to the code flash memory area while the CPU is running.
This function is available in the R5F 10 2 prod ucts.
(2) RAM parity error detection function
This detects parity errors when reading RAM is read.
(3) RAM guard function
This prevents RAM data from being rewritten when the CPU freezes.
This function is available in the R5F 10 2 prod ucts.
(4) SFR guard function
This prevents SFRs from being rewritten when the CPU freezes.
This function is available in the R5F 10 2 prod ucts.
(5) Invalid memory access detection function
This detects illegal accesses to invalid memory areas (such as areas where no memory is allocated and areas to
which access is restricted).
(6) Frequency detection function
This uses TAU to detect the oscillation freq uency.
(7) A/D test function
This is used to perform a self-check of A/D conversion by performing A/D conversion on the internal reference
voltage.
Remark See the application note (R01AN0749) for the features required to comply with the IEC60730 standards.
<R>
<R>
<R>
<R>
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21.2 Registers Used by Safety Functions
The safety functions use the following registers for each function.
Register Each Function of Safety Function
• CRC input register (CRCIN) Note
• CRC data register (CRCD) Note
CRC operation function
(general-purpose CRC)
• RAM parity error control register (RPECTL) RAM parity error detection function
RAM guard function
SFR guard function
• Invalid memory access detection control register (IAWCTL)
Invalid memory access detection function
• Timer input select register 0 (TIS0) Frequency detection function
• A/D test register (ADTES) A/D test function
Note Integrated in the R5F102 products.
21.3 Operation of Safety Functions
21.3.1 CRC operation function (general-purpose CRC)
In order to guarantee safety during operation, the IEC61508 standard mandates the checking of data even while the
CPU is operating.
In the RL78/G12, a gen eral CRC operation can b e executed as a peripheral function while the CPU is operating. T he
general CRC can be used for checking various data in addition to the code flash memory area. The data to be checked
can be specified by using software (a user-created program). CRC calculation function in the HALT mode can be used
only during the DMA transmission
The CRC generator polynomial used is “X16 + X12 + X5 + 1” of CRC-16-CCITT. The data to be input is inverted in bit
order and then calculated to a llow for LSB-firs t communication. F or example, if the data 1234 5678H is sent from the LSB,
values are written to the CRCIN register in the order of 78H, 56H, 34H, and 12H, enabling a value of 08F6H to be
obtained from the CRCD register. This is the result obtain ed by executing a CRC operation on the bit ro ws shown below,
which consist of the data 12345678H inverted in bit order.
CRCIN setting data 78H 56H 34H 12H
Bit representation data 0111 1000 0101 0110 0011 0100 0001 0010
Bit reverse data 0001 1110 0110 1010 0010 1100 0100 1000
Result data 0110 1111 0001 0000
CRCD data 0000 1000 1111 0110 Obtained result
(08F6H)
Caution Because the debugger rewrites the soft ware break setting line to a break in struction during program
execution, the CRC operation result differs if a software break is set in the CRC operation target area.
Bit reverse
Bit reverse
Operation with polynomial
<R>
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<Control register>
(1) CRC input register (CRCIN)
CRCIN register is an 8-bit register that is used to set the CRC operation data.
The possible setting range is 00H to F FH.
The CRCIN register can be set by an 8-bit memory manip ulatio n instructi on.
Reset signal generation clears this register to 00H.
Figure 21-1. Format of CRC Input Register (CRCIN)
Address: FFFACH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
CRCIN
Bits 7 to 0 Function
00H to FFH Data input.
(2) CRC data register (CRCD)
This register is used to store the CRC operation res ult.
The setting range is 0000H to FFFFH.
After 1 clock of CPU/peripheral hardware clock (fCLK) has elapsed from the time CRCIN register is written, the CRC
operation result is stored to the CRCD re gister.
The CRCD register can be set b y a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Figure 21-2. Format of CRC Data Register (CRCD)
Address: F02FAH After reset: 0000H R/W
Symbol 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CRCD
Cautions 1. Read the value written to CRCD register before writing to CRCIN register.
2. If conflict between writing and storing operation result to CRCD register occurs, the writing is
ignored.
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<Operation flow>
Figure 21-3. CRC Operation Function (General-Purpose CRC)
START
Write CRCD register to 0000H
Yes
No
End
Last address?
Address+1
Read CRCD register
Specify the start and end addresses ; Store the start and end addre sses in a
; general-purpose register.
; Initialize CRCD register
; Read 8-bit data of corresponding address
; Execute CRC calculation for 8-bit data
Store data to CRCIN register
Read data
; Get CRC result
; Compare the value
; with the stored
; expected value and
; make sure that the
; values match.
1 clock wait (fCLK)
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21.3.2 RAM parity error detection fun ction
The IEC60730 standard man dates the checking of RAM data. A single-bit parity bit is th erefore added to all 8-bit data
in the RL78/G12’s RAM. By using th is RAM parit y error det ection function, the par ity bit is app ended when data is written,
and the parity is checked when the data is read. This function can also be used to trigger a reset when a parity error
occurs.
<Control register>
• RAM parity error control register (RPECTL)
This register is used to control parit y error generation check bit and reset generation due to parity errors.
The RPECTL register can be set by a 1-bit or 8-bit memor y manipul ation i nstruction.
Reset signal generation clears this register to 00H.
Figure 21-4. Format of RAM Parity Error Control Register (RPECTL)
Address: F00F5H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 <0>
RPECTL RPERDIS 0 0 0 0 0 0 RPEF
RPERDIS Parity error reset mask flag
0 Enable parity error resets.
1 Disable parity error resets.
RPEF Parity error status flag
0 No parity error has occurred.
1 A parity error has occurred.
Caution The parity bit is appended when data is written, and the parity is checked when the data is read.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize R AM areas
where data access is to proceed before reading data.
The RL78’s CPU executes look-ahead due to the pipeline operation, the CPU might read an
uninitialized RAM area that is allocated beyond the RAM used, which causes a RAM parity error.
Therefore, while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM
area + 10 bytes when instructions are fetched from RAM areas. When using the self-programming
function while RAM parity error resets are enabled (RPERDIS = 0), be sure to initialize the RAM area
to overwrite + 10 bytes before overw ritin g.
Remarks 1. The RAM parity check is always on, and the result can be confirmed by checking the PREF flag.
2. The parity error reset is enabled by default (RPERDIS = 0).
Even if the parity error reset is disabled (RPERDIS = 1), the RPEF flag will be set (1) if a parity error
occurs.
3. The RPEF flag is set (1) by RAM parity errors and clear ed (0) by writing 0 to it or by any reset source.
When RPEF = 1, the value is retained even if RAM for which no parity error has occurred is read.
<R>
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21.3.3 RAM guard function
In order to guarantee safety during operation , the IEC61508 standard mandates that important data stored in the RAM
be protected, even if the CPU freezes.
This RAM guard function is used to protect data in the specified memory space.
If the RAM guard function is specified, writing to the specified RAM spac e is disabled, but reading from the space can
be carried out as usual.
<Control register>
• Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
GRAM1 and GRAM0 bits are used in RAM guard function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 21-5. Format of Invalid Memory Acces s Detection Control Register (IAWCTL)
Address: F0078H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC
GRAM1 GRAM0 RAM guard space Note
0 0 Disabled. RAM can be written to.
0 1 The 128 bytes starting at the beginning RAM address
1 0 The 256 bytes starting at the beginning RAM address
1 1
The 512 bytes starting at the beginning RAM address (setting prohibited for R5F10266,
R5F10366)
Note The RAM start address differs depending on the size of the RAM provided with the product.
Furthermore, the general-purpose register a r ea (FFEE0H to FFEFFH) is not guarded.
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21.3.4 SFR guard function
In order to guarantee safety during operation, the IEC61508 standard mandates that important SFRs be protected from
being overwritten, even if the CPU freezes.
This SFR guard function is used to protect data in the control registers used by the port function, interrupt function,
clock control function, voltage detection function, and RAM parity error detection function.
If the SFR guard function is specified, writing to the specified SFRs is disabled, but reading from the SFRs can be
carried out as usual.
<Control register>
• Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
GPORT, GINT and GCSC bits are used in SFR guard function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 21-6. Format of Invalid Memory Acces s Detection Control Register (IAWCTL)
Address: F0078H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC
GPORT Control registers of port function guard
0 Disabled. Control registers of port function can be read or written to.
1 Enabled. Writing to control registers of port function is disabled. Reading is enabled.
[Guarded SFR] PMxx, PUxx, PIMxx, POMxx, PMCxx, ADPC, PIOR Note 1
GINT Registers of interrupt function guard
0 Disabled. Registers of interrupt function can be read or written to.
1 Enabled. Writing to registers of interrupt function is disabled. Reading is enabled.
[Guarded SFR] IFxx, MKxx, PRxx, EGPx, EGNx
GCSC Notes 2 Control registers of clock control function, voltage detector and RAM parity error detection function guard
0 Disabled. Control registers of clock control function, voltage detector and RAM parity error detection
function can be read or written to.
1 Enabled. Writing to control registers of clock control function, voltage detector and RAM parity error
detection function is disabled. Reading is enabled.
[Guarded SFR] CMC, CSC, OSTS, CKC, PERx, OSMC, LVIM, LVIS, RPECTL
Notes 1. Pxx (Port register) is not guarded.
2. Clear GCSC bit to 0, during self programming /serial programming.
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21.3.5 Invalid memory access detection function
The IEC60730 standard mandates checking that the CPU and interrupts are operating correctly.
The illegal memory access detection function triggers a reset if a memory space specified as access-prohibited is
accessed.
The illegal memory access detection function applies to the areas indicated by NG in Figure 21- 7.
Figure 21-7. Invalid access detection area
Special function register (SFR)
256 byte
F F F F F H
0 0 0 0 0 H
F F F 0 0 H
F F E F F H
F F E E 0 H
F F E D F H
RAM
Note
General-purpose register
32 byte
Code flash memory
Note
F 0 8 0 0 H
F 0 7 F F H
Special function register (2nd SFR)
2 Kbyte
F 0 0 0 0 H
E F F F F H
F 1 0 0 0 H
F 0 F F F H
Reserved
Reserved
Mirror
Data flash memory
Read Write
Fetching
instructions
(execute)
Possibility access
OK
OK
OK
OK
OK
OK
OKOK
NGNG
NG
NG
NGNG
NG
E F 0 0 0 H
E E F F F H
x x x x x H
y y y y y H
Reserved
1 0 0 0 0 H
0 F F F F H
Reserved
F 2 0 0 0 H
F 1 F F F H
F 1 8 0 0 H
F 1 7 F F H
F 4 0 0 0 H
F 3 F F F H
Note Code flash memory and RAM address of each product are as follows.
Products (x = 2, 3) Code flash memory
(00000H to xxxxxH) RAM
(yyyyyH to FFEFFH)
R5F10x66
2048 × 8 bit (00000H to 007FFH) 256 × 8 bit (FFE00H to F FEFFH)
R5F10x67, R5F10x77, R5F10xA7 4096 × 8 bit (00000H to 00FFFH) 512 × 8 bit (FFD00H to FFEFFH)
R5F10x68, R5F10x78, R5F10xA8 8192 × 8 bit (00000H to 01FFFH) 768 × 8 bit (FFC00H to FFEFFH)
R5F10x69, R5F10x79, R5F10xA9 12288 × 8 bit (00000H to 02FFFH) 1024 × 8 bit (FFB00H to FFEFFH)
R5F10x6A, R5F10x7A 16384 × 8 bit (00000H to 03FFFH) 1536 × 8 bit (FF900H to FFEFFH)
R5F10xAA 2048 × 8 bit (FF700H to FFEFFH)
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<Control register>
• Invalid memory access detection control register (IAWCTL)
This register is used to control the detection of invalid memory access and RAM/SFR guard function.
IAWEN bit is used in invalid memory access detection function.
The IAWCTL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 21-8. Format of Invalid Memory Acces s Detection Control Register (IAWCTL)
Address: F0078H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
IAWCTL IAWEN 0 GRAM1 GRAM0 0 GPORT GINT GCSC
IAWEN Note Control of invalid memory access detection
0 Disable the detection of invalid memory access.
1 Enable the detection of invalid memory access.
Note Only writing 1 to the IAWEN bit is enabled, not writing 0 to it after setting it to 1.
Remark By specifying WDTON = 1 for the option byte (watchdog timer operation enable), the invalid memory
access detection function is enabled ev en IAWEN = 0.
21.3.6 Frequency detection function
The IEC60730 standard mandates checki ng that the oscillation frequency is correct.
The frequency detection function can detect wheth er the clock is operatin g on an abnorm a l freque nc y by comparing the
internal high-speed on-c hip oscillation clock or external X1 oscill ation clock with the internal low-speed on-chip oscillation
clock (15 kHz).
Figure 21-9. Configuration of Frequency Detection Function
Timer array unit 0
(TAU0)
TI05
fCLK
Selector
X1
X2
Selector
Low-speed on-chip
oscillator
(fIL = 15 kHz)
X1 oscillator
(fMX)
High-speed on-chip
ossiratopr (f
IH
)
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<Operation >
Whether the clock frequency is correct or not can be judged by measuring the pulse interval under the following
conditions:
• The internal high-speed oscillation clock (fIH) or the external X1 oscillation clock (fMX) is selected as the
CPU/peripheral hardware clock (fCLK).
• T he internal low-speed oscillation cl ock (fIL: 15 kHz) is selected as the timer input for channel 5 of timer array unit 0
(TAU0).
If pulse interval measurement results in an abnormal value, it can be concluded that the clock frequency is abnormal.
For how to execute pulse interval measurement, see 6.7.4 Operation as input pulse interval measurement.
<Control register>
• Timer input select register 0 (TIS0)
This register is used to select the timer input of channel 5 by 20- and 24-pin products.
By selecting the low-speed o n-chip oscillation clock for the timer input, its puls e width can be measured to determine
whether the proportional relationship between the low-speed on-chip oscillator clock and the timer operation clock is
correct.
The TIS0 register can be set by an 8-bit memor y manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 21-10. Format of Timer Input Select Register 0 (TIS0)
Address: F0074H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TIS0 0 0 0 0 0 0 TIS01 TIS00
TIS01 TIS00 Selection of timer input used with channel 1
× 0 Input signal of timer input pin (TI01)
0 1 Low-speed on-chip oscillator clock (fIL)
1 1 Setting prohibited
Remark ×: don’t care
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21.3.7 A/D test function
The IEC60730 standard mandates testing the A/D converter. The A/D test function is used to check whether the A/D
converter is operating normally by executing A/D conversions of an internal voltage of 0 V, the AVREF voltage, and the
internal reference voltage (1.45 V).
Figure 21-11. Configuration of A/D Test Function
<Control register>
(1) A/D test register (ADTES)
This register is used to select the A/D converter’s positive reference voltage AVREFP, the A/D converter’s negative
reference voltage AVREFM, or the analog input channel (ANIxx) as the target of A/D conversion.
When using the A/D test function, specify th e following settings:
• Select AVREFM as the target of A/D conversio n when convert ing the internal 0 V.
• Select AVREFP as the target of A/D conversion when converting AVREF.
The ADTES register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Temperature
sensor
+ side reference
voltage source
(AVREF+)
- side reference
voltage source
(AVREF-)
A/D convertor
ANI0/AVREFP
ANI1/AVREFM
ANIx
ANIx
VDD
VSS
Internal reference
voltage (1.45 V)
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Figure 21-12. Format of A/D Test Register (ADTES)
Address: F0013H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADTES 0 0 0 0 0 0 ADTES1 ADTES0
ADTES1 ADTES0 A/D conversion target
0 0
ANIxx / temperature sensor output / internal reference voltage (1.45 V) (This is specified
using the analog input channel specification register (ADS).) Note
1 0 AVREFM
1 1 AVREFP
Other than the above Setting prohibited
Note Temperature sensor output/internal reference voltage (1.45 V) can be used only in HS (high-speed
main) mode.
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(2) Analog input channel specification register (ADS)
This register specifies the input channel of the analog voltage to be A/D converted.
Set A/D test register (ADTES) to 00H when measuring the ANIxx/temperature sensor output /internal reference
voltage (1.45 V).
The ADS register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 21-16. Format of Analog Input Channel Specification Register (ADS) (1/2)
Address: FFF31H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
ADS ADISS 0 0 ADS4 ADS3 ADS2 ADS1 ADS0
Select mode (ADMD = 0)
ADISS ADS4 ADS3 ADS2 ADS1 ADS0 Analog input
channel Input sourceNote1
0 0 0 0 0 0 ANI0 P20/ANI0/AVREFP pin
0 0 0 0 0 1 ANI1 P21/ANI1/AVREFM pin
0 0 0 0 1 0 ANI2 P22/ANI2 pin
0 0 0 0 1 1 ANI3 P23/ANI3 pin
0 1 0 0 0 0 ANI16 P10/ANI16 pin
P01/ANI16 pin
0 1 0 0 0 1 ANI17 P11/ANI17 pin
P00/ANI17 pin
0 1 0 0 1 0 ANI18 P12/ANI18 pin
P147/ANI18 pin
0 1 0 0 1 1 ANI19 P13/ANI19 pin
P120/ANI19 pin
0 1 0 1 0 0 ANI20 P14/ANI20 pin
−
0 1 0 1 0 1 ANI21 P42/ANI21 pin
−
0 1 0 1 1 0 ANI22 P41/ANI22 pin
−
1 0 0 0 0 0 − Temperature sensor output
Note 2
1 0 0 0 0 1 − Internal reference voltage
output (1.45 V) Note 2
Other than the above Setting prohibited
Notes 1. Upper: 20-, 24-pin products, lower: 30 pin products
2. T his setting can be use d on ly in HS (high-speed main) mode.
Cautions 1. Be sure to clear bits 5 and 6 to 0.
2. Only rew rite the value of the ADISS bit while A/D voltage comparator operation is stopped
(which is indicated by the ADCE bit o f A/D converter mode register 0 ( ADM0) being 0).
3. If using AVREFP as the + side reference voltage source ( AVREF+) of the A/D converter, do
not select ANI0 as an A/D conversion channel.
4. If using AVREFM as the − side reference voltage source (AVREF-) of the A/D converter, do
not select ANI1 as an A/D conversion channel.
5. If ADISS is set to 1, the internal reference voltage (1.45 V) cannot be used for the + side
reference voltage source (AVREF+).
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< Check of analog multiplexer >
The analog multiplexer can be checked using the following procedure.
(1) Perform A/D conversion for the ANIx pin (conversion result 1).
(2) Select AVREFM using the ADTES register, perform A/D conversion, and then set the voltage potential difference
between the terminals of the sampling capacitor of the A/D converter to 0 V.
(3) Perform A/D conversion for the ANIx pin (conversion result 2).
(4) Select AVREFP using the ADTES register, perform A/D conversion, and then set the voltage potential difference
between the terminals of the sampling ca pacitor of the A/D converter to AVREF.
(5) Perform A/D conversion for the ANIx pin (conversion result 3).
(6) Make sure that conversion results 1, 2, and 3 are equal.
Using the procedure above can confirm that the analog multiplexer is selected and all wiring is connected.
Remarks 1. If the analog input voltage is variable during A/D conversion in steps <1> to <5> above, use another
method to check the analog multiple xer.
2. T he conversion results might contain an error. Cons ider an appropriate level of error when comparing the
conversion results.
RL78/G12 CHAPTER 22 REGULATOR
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CHAPTER 22 REGUL ATOR
22.1 Overview of Regulators
The 30-pin product of the RL78/G12 incorporates the circuit for constant voltage operation in the device. To stabilize
the regulator output, connect the REGC pin to Vss via a capacitor (0.47 to 1
μ
F) for regulator stabilization. Use a
capacitor with good character istics because it is used for stabilization of internal voltage.
Caution Keep the wiring length as sho rt as possible for the broken-line part in th e above figure.
The regulator output voltage, see table 22-1.
Table 22-1. Regulator Output Voltage Conditions
Mode Output
voltage Condition
LS (low-speed
main) mode 1.8 V −
1.8 V In the STOP mode
HS (high-speed
main) mode 2.1 V Other than STOP mode (include during OCD mode) Note
Note W hen it shifts to the subsystem clock op eration or STOP mode during the on-chip debu gging, th e regul ator output
voltage is kept at 2.1 V (not decline to 1.8 V).
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CHAPTER 23 OPTION BYTE
23.1 Functions of Option By tes
Addresses 000C0H to 000C3H of the flash memory of the RL78/G12 form an optio n byte area.
Option bytes consist of user option byte (000C0H to 000C2H) and on-chip debug option byte (000C3H).
Upon power applicatio n or resetting and starting, an option byte is automaticall y referenced and a specified function is
set. When using the product, be sure to set the following functions by using the option bytes.
For the bits to which no function is allocated, be sure to set the value specified in this manual.
23.1.1 User option byte (000C0H to 000C2H)
(1) 000C0H
Operation of watchdog timer
• Operation is stopped or enabled in the HALT or STOP mode.
Setting of interval time of watchdog timer
Operation of watchdog timer
• Operation is stopped or enabl ed.
Setting of window open period of watchdog timer
Setting of interval interrupt of watchdog timer
• Used or not used
(2) 000C1H
Setting of LVD operation mode
• Interrupt & reset mode.
• Reset mode.
• Interrupt mode.
Setting of LVD detection level (VLVDH, VLVDL, VLVD)
Controlling of P125/RESET pin
• P125/KR1/SI01 or RESET
(3) 000C2H
Setting of flash operation mode
• LS (low speed main) mode
• HS (high speed main) mode
Setting of the frequency of the high-speed on-chip osci llator
• Select from 1 to 24 MHz.
<R>
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23.1.2 On-chip debug option byte (000C3H)
Control of on-chip debug operation
• On-chip debug operation is di sabled or enabled.
Handling of data of flash memory in case of failure in on-chip debug security ID authentication
• Data of flash memory is erased or not erased in case of failure in on-chip debug security ID authentication.
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23.2 Format of User Option Byte
The format of user option byte is shown below.
Figure 23-1. Format of User Option Byte (000C0H)
Address: 000C0H
7 6 5 4 3 2 1 0
WDTINIT WINDOW1 WINDOW0 WDTON WDCS2 WDCS1 WDCS0 WDSTBYON
WDTINIT Use of interval interrupt of watchdog timer
0 Interval interrupt is not used.
1 Interval interrupt is generated when 75% + 1/2 fIL of the overflow time is reached.
WINDOW1 WINDOW0 Watchdog timer window open periodNote
0 0 Setting prohibited
0 1 50%
1 0 75%
1 1 100%
WDTON Operation control of watchdog timer counter
0 Counter operation disabled (counting stopped after reset)
1 Counter operation enabled (counting started after reset)
WDCS2 WDCS1 WDCS0 Watchdog timer overflow time
(fIL = 17.25 kHz (MAX.))
0 0 0 26/fIL (3.71 ms)
0 0 1 27/fIL (7.42 ms)
0 1 0 28/fIL (14.84 ms)
0 1 1 29/fIL (29.68 ms)
1 0 0 211/fIL (118.72 ms)
1 0 1 213/fIL (474.90 ms)
1 1 0 214/fIL (949.80 ms)
1 1 1 216/fIL (3799.19m s)
WDSTBYON Operation control of watchdog timer counter (HALT/STOP mode)
0 Counter operation stopped in HALT/STOP modeNote
1 Counter operation enabled in HALT/STOP mode
Note The window open period is 100% when WDSTBYON = 0, regardless the value of the WINDOW1 and
WINDOW0 bits.
Caution The watchdog timer continues its operation even during self-programming or data flash rewrite.
During processing, the interrupt acknowledge time is delayed. Set the overflow time and window
size taking this delay into consideration.
Remark fIL: Low-speed on-chip oscillator clock frequency
<R>
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Figure 23-2. Format of User Option Byte (000C1H) (1/2)
Address: 000C1H
7 6 5 4 3 2 1 0
VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0
• LVD setting (interrupt mode & reset mode)
Detection voltage Option byte Setting Value
VLVDH VLVDL Mode setting
Rising
edge Falling
edge Falling
edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.98 V 1.94 V 1 0
2.09 V 2.04 V 0 1
3.13 V 3.06 V
1.84 V 0 1
0 0
2.61 V 2.55 V 1 0
2.71 V 2.65 V 0 1
3.75 V 3.67 V
2.45 V 1 0
0 0
2.92 V 2.86 V 1 0
3.02 V 2.96 V 0 1
4.06 V 3.98 V
2.75 V
1 0 0
1 1
0 0
Other than above Setting prohibited
• LVD setting (reset mode)
Detection voltage Option byte Setting Value
VLVD Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V
1 1 0
1 1 0 0
Other than above Setting prohibited
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Figure 23-2. Format of User Option Byte (000C1H) (2/2)
Address: 000C1H
7 6 5 4 3 2 1 0
VPOC2 VPOC1 VPOC0 PORTSELB LVIS1 LVIS0 LVIMDS1 LVIMDS0
• LVD setting (interrupt mode)
Detection voltage Option byte Setting Value
VLVD Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0
VPOC2 VPOC1 VPOC0 LVIS1 LVIS0
1.88 V 1.84 V 0 1 1 1
1.98 V 1.94 V 0 1 1 0
2.09 V 2.04 V 0 1 0 1
2.50 V 2.45 V 1 0 1 1
2.61 V 2.55 V 1 0 1 0
2.71 V 2.65 V 1 0 0 1
2.81 V 2.75 V 1 1 1 1
2.92 V 2.86 V 1 1 1 0
3.02 V 2.96 V 1 1 0 1
3.13 V 3.06 V 0 1 0 0
3.75 V 3.67 V 1 0 0 0
4.06 V 3.98 V
0 1 0
1 1 0 0
Other than above Setting prohibited
Remark Refer to LVD setting, see 20.1 Functions of Voltage Detector.
• Setting of LVDOFF
Detection voltage Option byte Setting Value
VLVD Mode setting
Rising edge Falling edge LVIMDS1 LVIMDS0 VPOC2
VPOC1 VPOC0 LVIS1 LVIS0
− − × 1 1 × × × ×
Caution To set the LVD off, execute the external reset when the pow er supply is turned on, and th en release
the reset in the operation voltage range.
HS (high-speed main) mode: VDD = 2.7 to 5.5 V@1 to 24 MHz
VDD = 2.4 to 5.5 V@1 to 16 MHz
LS (low-speed main) mode: VDD = 1.8 to 5.5 V@1 to 8 MHz
Remark ×: don’t care
• Setting of the P125 (20-, 24-pin products)
PORTSELB P125/RESET pin control
0 Port function (P125/KR1/SI01)
1 RESET input (PU125 is set to 1 and internal pull-up resistor can be connected.)
Caution In the 30-pin products, be sure to set bit 4 (PORTSELB) to 1.
<R>
<R>
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Figure 23-3. Format of Option Byte (000C2H)
Address: 000C2H
7 6 5 4 3 2 1 0
CMODE1 CMODE0 1 0 FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0
CMODE1 CMODE0 Setting of flash operation mode
Operating
Frequency Range Operating Voltage
Range
1 0
LS (low speed main) mode 1 to 8 MHz 1.8 to 5.5 V
1 1
HS (high speed main) mode 1 to 16 MHz 2.4 to 5.5 V
1 to 24 MHz 2.7 to 5.5 V
Other than above Setting prohibited
FRQSEL3 FRQSEL2 FRQSEL1 FRQSEL0 Frequency of the high-speed on-chip oscillator
0 0 0 0
24 MHz
1 0 0 1
16 MHz
0 0 0 1
12 MHz
1 0 1 0
8 MHz
1 0 1 1
4 MHz
1 1 0 1
1 MHz
Other than above Setting prohibited
Caution Be sure to set bit 5 to “1" and bit 4 to “0”.
<R>
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23.3 Format of On-chip Debug Option By te
The format of on-chip debug option byte is shown below.
Figure 23-4. Format of On-chip Debug Option Byte (000C3H)
Address: 000C3H
7 6 5 4 3 2 1 0
OCDENSET 0 0 0 0 1 0 OCDERSD
OCDENSET OCDERSD Control of on-chip debug operation
0 0 Disables on-chip debug operation.
0 1 Setting prohibited
1 0 Enables on-chip debugging.
Erases data of flash memory in case of failures in authenticating on-chip debug
security ID.
1 1 Enables on-chip debugging.
Does not erases data of flash memory in case of failures in authenticating on-chip
debug security ID.
Caution Bits 7 and 0 (OCDENSET and OCDERSD) can only be specified a value.
Be sure to set 000010B to bi ts 6 to 1.
Remark The value on bits 3 to 1 will be writ ten over when the on-c hip de bug function is in use an d thus it will become
unstable after the setting.
However, be sure to set the default values (0, 1, and 0) to bits 3 to 1 at setting.
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23.4 Setting of Option Byte
The user option byte an d on-chip debug option byte can be set using th e assembler or linker option of CubeSuite+, in
addition to describing to the source.
A software description example of the option byte setting is shown below.
OPT CSEG OPT_BYTE
DB 36H ; Does not use interval interrupt of watchdog timer,
; Enables watchdog timer operation,
; Window open period of watchdog timer is 50%,
; Overflow time of watchdog timer is 29/fIL,
; Stops watchdog timer operation during HALT/STOP mode
DB 2AH ; Select 1.84 V for VLVDL
; Select 1.94 V for VLVDH
; Select the interrupt & reset mode as the LVD operation mode
; Do not use reset input
DB EDH ; Select the HS (high-speed main) mode as the flash operation mode
and 1 MHz as the frequency of the high-speed on-chip oscill ator clock
DB 85H ; Enables on-chip debug op eration, does not erase flash memory
data when security ID authorization fails
Caution To specify the option byte by using assembly language, use OPT_BYTE as the relocation attribute
name of the CSEG pseudo instruction.
RL78/G12 CHAPTER 24 FLASH MEMORY
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CHAPTER 24 FLASH MEMORY
The RL78/G12 incorporates the flash memory to which a program can be written, erased, and overwritten while
mounted on the board. The flash memory includes the “cod e flash memory”, in which programs can be executed, and the
“data flash memory”, an area for storing data (provided oly in the R5F102 products).
Special function register (SFR)
256 bytes
RAM
2 KB to 256 bytes
General-purpose register
32 bytes
Special function register (2nd SFR)
2 KB
Reserved
Reserved
Reserved
Mirror
FFFFFH
FFF00H
FFEFFH
FFEE0H
FFEDFH
F2000H
F1FFFH
F1800H
F17FFH
F1000H
F0FFFH
F0800H
F07FFH
F0000H
FFFFFH
00000H
The following three methods for programmin g the flash me mory are available:
• Writing to flash memory by using flash memory programmer (see 24.1)
• Writing to flash memory by using external device (that Incorporates UART) (see 24.2)
• Self-programming (see 24.7)
<R>
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24.1 Writing to Flash Memory by Using Flash Me mory Programmer
The following dedicated flash memory programmer can be used to write data to the internal flash memory of the
RL78/G12.
• PG-FP5, FL-PR5
• E1 on-chip debugging emulator
Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer.
(1) On-board programming
The contents of the flash memor y can be rewritten after the RL78/G12 has be en mounted on the target s ystem. The
connectors that connect the dedicat ed flash memory programmer must be mounted on the target system.
(2) Off-board programming
Data can be written to the flash memory with a dedicated program adapter (FA series) before the RL78/G12 is
mounted on the target system.
Remark FL-PR5 and FA series are products of Naito Densei Machi da Mfg. Co., Ltd.
Table 24-1. Wiring Between RL78/G12 and Dedicated Flash Memory Prog rammer
Pin No.
Pin Configuration of Dedicated Flash Memory Programmer 20-pin 24-pin 30-pin
Signal Name
PG-FP5, FL-PR5 E1 on-chip
debugging emulator
I/O Pin Function
Pin
Name SSOP WQFN
(4 × 4) SSOP
− TOOL0 I/O Transmit/receive signal 4 24 5
SI/RxD − I/O Transmit/receive signal
TOOL0/
P40
SCK − Output − − − − −
CLK − Output − − − − −
− RESET Output
/RESET − Output
Reset signal RESET 5 1 6
FLMD0 − Output Mode signal − − − −
VDD I/O
VDD voltage generation/
power monitoring VDD 10 6 12
VSS 9 5 11 GND − Ground
REGCNote − − 10
EMVDD − Driving power for TOOL pin VDD 10 6 12
Note Connect REGC pin to VDD via a capacitor (0.47 to 1
μ
F).
Remark Pins that are not indicated in the a bove table can be left open when usi ng the flash memory programmer
for flash programming.
About a connection RL78/G12 and a connector, refer to the user’s manual of each programmer. About a connection
with E1, refer to 25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12.
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24.1.1 Programming environment
The environment required for writing a program to the flash memory of the RL78/G12 is illustrated below.
Figure 24-1. Environment for Writing Program to Flash Memory
RS-232C
USB
RL78/G12
VDD
VSS
RESET
TOOL0 (dedicated single-line UART)
Host machine
Dedicated flash
memory programmer
PG-FP5, FL-PR5 E1
A host machine that controls the dedicated flash memory pr ogrammer is necessary.
To interface between the dedicated flash memory programmer and the RL78/G12, the TOOL0 pin is used for
manipulation such as writing and erasing via a dedicated single-line UART.
24.1.2 Communication mode
Communication between the dedicated flash memory programmer and the RL78/G12 is established by serial
communication using the TOOL0 pin via a dedicate d single-line UART of the RL78/G12.
Transfer rate: 1 M, 500k, 250 k, 115.2 kbps
Figure 24-2. Communication with Dedicated Flash Memory Programmer
V
DD
V
SS
/REGC
Note 3
RESET
TOOL0
EMV
DD
V
DD
V
DD
GND
RESET
Note 1
,
/RESET
Note 2
RL78/G12
Dedicated flash
memory programmer
PG-FP5, FL-PR5 E1
TOOL0
Note 1
SI/RxD
Note 2
Notes 1. When using E1 on-chip debugging emulator.
2. When using PG-FP5 or F L-PR5.
3. Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F) (30-pin products).
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The dedicated flash memory programmer generates the following signals for the RL78/G12. See the manual of PG-FP5,
FL-PR5, or E1 on-chip debugging emulator for details.
Table 24-2. Pin Connection
Dedicated Flash Memory Programmer RL78/G12 Connection
Signal Name
PG-FP5,
FL-PR5 E1 on-chip
debugging
emulator
I/O Pin Function Pin Name
FLMD0 − Output Mode signal − ×
VDD I/O VDD voltage generation/power monitoring VDD
GND − Ground VSS, REGCNote
EMVDD − Driving power for TOOL0 pin VDD
CLK − Output Clock output − ×
/RESET − Output
− RESET Output
Reset signal RESET
− TOOL0 I/O Transmit/receive signal TOOL0
SI/RxD − I/O Transmit/receive signal
SCK − Output Transfer clock − ×
Note Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F) (30-pin products).
Remark : Be sure to connect the pin.
×: The pin does not have to be connected.
24.2 Writing to Flash Memory by Using Extern al Device (that Incorporates UART)
On-board data writing to the internal flash memory is possible by using the RL78/G12 and an external device (a
microcontroller or ASIC) connected to a UART.
On the development of flash memory programmer by user, refer to the RL78 Microcontrollers (RL78 Protocol A)
Programmer Edition Application Note (R01AN0815).
24.2.1 Programming environment
The environment required for writing a program to the flash memory of the RL78/G12 is illustrated below.
Figure 24-3. Environment for Writing Program to Flash Memory
RL78/G12External device
(such as microcontroller
and ASIC)
VDD
VSS
RESET
UART (TOOLTxD, TOOLRxD)
TOOL0
Processing to write data to or delete data from the RL78/G12 by using an external device is performed on-board. Off-
board writing is not possib le.
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24.2.2 Communication mode
Communication between the external device and the RL78/G12 is established by serial communication using the
TOOLTxD and TOOLRxD pins via the dedicated UART of the RL78/G12.
Transfer rate: 1 M, 500 k, 250 k, 115.2 kbps
Figure 24-4. Communication with External Device
VDD
VSS/REGCNote
RESET
TOOLTxD
VDD
GND
/RESET
RL78/G12
RxD
TxD
External device
(such as micro controller
and ASIC)
TOOL0PORT
TOOLRxD
Note Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F) (30-pin products).
The external device generates the following signals for the RL78/G12.
Table 24-3. Pin Connection
External Device RL78/G12 Connection
Signal Name I/O Pin Function Pin Name
VDD I/O VDD voltage gene ration/power monitoring VDD,
GND − Ground VSS, REGCNote
CLK Output Clock output − ×
RESETOUT Output Reset signal output RESET
RxD Input Receive signal TOOL0TxD
TxD Output Transmit signal TOOL0RxD
PORT Output Mode signal TOOL0
SCK Output Transfer clock − ×
Note Connect the REGC pin to GND via a capacitor (0.47 to 1
μ
F) (30-pin products).
Remark : Be sure to connect the pin.
×: The pin does not have to be connected.
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24.3 Connection of Pins on Board
To write the flash memory on-board by using the flash memory programmer, connectors that connect the dedicated
flash memory programmer must be provided on the target system. First provide a function that selects the normal
operation mode or flash memory programming mode on the board.
When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the
same status as immediately after reset. Therefore, if the external device does not recognize the state immediately after
reset, the pins must be handled as described below.
Refer to flash programming mode, see 24.5.2 Flash memory programming mode.
24.3.1 P40/TOOL0 pin
In the flash memory programming mode, pull up externally with a 1 kΩ resister, and connect it to the dedicated flash
memory programmer.
When using it as a port pin, use it as described below.
Input: Do not input a low level of 1 ms interval period after the external reset release. Use a resister of 500 kΩ or
more when using for pull-down.
Output: Use a resister of 500 kΩ or more when using for pull-down.
Remark T he SAU and IICA pins are not used for communication between the RL78/G12 and dedicated flash memor y
programmer, because single-line UART (TOOL0 pin) is used.
24.3.2 RESET pin
Signal conflict will occur if the reset signal of the dedicated flash memory programmer and external device are
connected to the RESET pin that is connect ed to the reset signal generator on the board. To prevent this conflict, isolate
the connection with the reset signal generator.
The flash memory will not be correctly programmed if the reset signal is input from the user system while the flash
memory programming mode is set. Do not input any signal other than the reset signal of the dedicated flash memory
programmer and external device.
Figure 24-5. Signal Conflict (RESET Pin)
Input pin
Dedicated flash memory programmer
connection pin
Another device
Signal conflict
Output pin
In the flash memory programming mode, a signal output by another device
will conflict with the signal output by the dedicated flash memory
programmer. Therefore, isolate the signal of another device.
RL78/G12
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24.3.3 Port pins
In the flash memory program ming mode, all the pins not u sed for flash memor y programming enter the same status as
that immediately after reset. If an external device connected to the ports does not recognize the port status immediately
after reset, the port pin must be connected to either to VDD or VSS via a resistor.
24.3.4 REGC pins
Connect the REGC pin to VSS via a capacitor (0.47 to 1
μ
F) as in normal operation (30- pin products). Use a capacitor
with good characteristics because it is used for stabilization of internal voltage.
24.3.5 X1 and X2 pins
Connect X1 and X2 in the same status as in the normal op eratio n mode.
Remark In the flash memory programming mode, the high-speed o n-chip oscillation clock (fIH) is used.
24.3.6 Power supply
To use the supply voltage output of the flash memory programmer, connect the VDD pin to VDD of the flash memory
programmer, and the VSS pin to GND of the flash memory programmer.
To use the on-board suppl y voltage, connect in compliance with the normal operation mode.
However, when writing to the flash memory by using the flash memory programmer and using the on-board supply
voltage, be sure to connect the VDD and VSS pins to VDD and GND of the flash memory programmer to use the power
monitor function with the flash memory programmer.
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24.4 Data Flash
24.4.1 Data flash overview
In addition to 2K to 16KB of code flash memory, the R5F102 products of the RL78/G12 includes 2 KB of data flash
memory for storing data.
00000H
EFFFFH
F0000H
F07FFH
F0800H
FFEDFH
FFEE0H
FFEFFH
FFF00H
FFFFFH
F1FFFH
F2000H
Special function register (SFR)
256 bytes
RAM
2 KB to 256 bytes
General-purpose register
32 bytes
Special function register (2nd SFR)
2 KB
Reserved
Reserved
Reserved
Mirror
Data flash memory
2 KB
F0FFFH
F1000H
F17FFH
F1800H
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An overview of the data flash memory is provided bel ow. For details of a method for rewriting the data flash memory,
refer to RL78 Family Data Flash Library Type04 User’s Manual.
• The data flash memory can be written to by using the flash memory progr ammer or an external device
• Programming is performed in 8-bit units
• Blocks can be deleted in 1 KB units
• The only access by CPU instructions is byte reading (1 clock + wait 3 clock cycles)
• Because the data flash memory is an ar ea exclusively us ed for data, it cannot be used to execute instructions (code
fetching)
• Instructions can be executed from the code flash memory while rewriting the data flash memory (That is, Back
Ground Operation (BGO) is supported)
• Accessing the data flash memory is not possible while rewriting the code flash memory (during self programming)
• Because the data flash memory is stopped after a reset ends, the data flash control register (DFLCTL) must be set
up in order to use the data flash memory
• Manipulating the DFLCTL register is not possible while rewriting the data flash memory
• Transition the HALT, STOP mode is not possible while re writing the data flash memory
Cautions 1. Interrupts are disabled d uring data flash rewrite for only the R5F10266. Execute the data flash
library with the IE flag cleared (0) by the DI instruction.
2. The high-speed on-chip oscillator should be kept operating during data flash rewrite. When it
is stopped, start the oscillator (HIOSTOP = 0) and execute the data flash library after 30 μs.
Refer to flash programming mode, see 24.7 Flash Memory Programming by Self-Programming.
24.4.2 Register controlling data flash memory
(1) Data flash control register (DFLCTL)
This register is used to enable or disab le accessing to the data flash.
The DFLCTL register is set by a 1-bit or 8-bit memory manipulation instruction.
Reset input sets this register to 00H.
Figure 24-6. Format of Data Flash Control Register (DFLCTL)
Address: F0090H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 <0>
DFLCTL 0 0 0 0 0 0 0 DFLEN
DFLEN Data flash access control
0 Disables data flash access
1 Enables data flash access
Caution Manipulating the DFLCTL register is not possible while rewriting the data flash memory.
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24.4.3 Procedure for accessing data flash memory
The data flash memory is initially stopped after a reset ends and cannot be accessed (read or programmed). To
access the memory, perform the following procedure:
<1> Write 1 to bit 0 (DFLEN) of the data flash control register (DFLCTL).
<2> Wait for the setup to finish for software timer ,etc.
The time setup takes differs for each main clock mode.
<Setup time for each main clock mode>
• HS (High-speed main) mode: 5
μ
s
• LS (Low-speed main) mode: 720 ns
<3> After the wait, the data flash memory can be accesse d.
Cautions 1. Accessing the data flash memory is not possible during the setup time.
2. Before e xecuting a STOP instruction during the setup time, temporarily clear DFLEN to 0.
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24.5 Programming Method
24.5.1 Controlling flash memory
The following figure illustrates the procedure to manipulate the flash mem ory.
Figure 24-7. Flash Memory Manipulation Procedure
Start
Manipulate flash memory
End?
Yes
Controlling TOOL0 pin and RESET pin
No
End
Flash memory programming
mode is set
Refer to flash programming mode, see 24.5.2 Flash memory programming mode.
RL78/G12 CHAPTER 24 FLASH MEMORY
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24.5.2 Flash memory programming mode
To rewrite the contents of the flash memory, set the RL78/G12 in the flash memor y programming mode. To enter the
mode, set as follows.
<When programming by using the dedicated flash memory programmer>
Communication from the dedicated flash memory programmer is performed to automatically switch to the flash
memory programming mode.
<When programming by usi ng an external device>
Set the TOOL0 pin to the low level, and then cancel t he reset. Keep the TOOL0 pin at the low level fro m the reset
ends to 1 ms + software processing end, an d then use UART communication to sen d the data “00H” from the external
device. Finish UART communication within 100 ms after the reset ends.
Figure 24-8. Setting of Flash Memory Programming Mode
RESET
TOOL0
<1> <2> <3>
tSUINIT
tHD+
software
processing
time
tSU
<4>
00H reception
(T OOLRxD , T OOLTxD mode)
<1> Low level is input to the TOOL0 pin.
<2> External reset is released (POR and LVD res et must be rele ased in advance).
<3> Low level of the TOOL0 pin is released.
<4> Mode drawing and baud rate setting are complete via UART reception.
Remark tSUINIT: The segment shows that it is necessary to finish specifying the initial communication settings
within 100 ms from when the resets end.
t
SU: How long from when the TOOL0 pin is placed at the low level until an external reset ends
(Min. 10
μ
s)
t
HD: How long to keep the TOOL0 pin at the low level from when the external and internal resets
end. (Min. 1
μ
s : except software processing time)
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RL78/G12 CHAPTER 24 FLASH MEMORY
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Table 24-4. Relationship Between TOOL0 Pin and Operation Mode After Reset Release
TOOL0 Operation Mode
VDD Normal operation mode
0 V Flash memory programming mode
There are two flash memory programming modes for which the voltage range in which to write, erase, or verify data
differs.
Table 24-5. Programming Modes and Voltages at Which Data Can Be Written, Erased, or Verified
Mode Voltages at which data can be written, erased, or verified Writing Clock Frequency
1.8 V to 5.5 V 8 MHz (MAX.)
2.4 V to 5.5 V 16 MHz (MAX.)
Wide voltage mode
2.7 V to 5.5 V 24 MHz (MAX.)
2.4 V to 5.5 V 16 MHz (MAX.)
Full speed mode Note
2.7 V to 5.5 V 24 MHz (MAX.)
Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1.
Specify the mode that corresponds to the voltage range in which to write data. When programming by using the
dedicated flash memor y progr ammer, the mode is automatically selected by the voltage setting on GUI.
Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing,
deletion, or verification.
2. For details a bo ut communication commands, see 24.5.4 Communicatio n commands.
24.5.3 Selecting communication mode
Communication mode of the RL78/G12 as follows.
Table 24-6. Communication Modes
Standard SettingNote 1 Communication
Mode Port Speed
Note 2 Frequency Multiply Rate
Pins Used
1-line mode
(when flash
memory
programmer is
used)
UART 115200 bps,
250000 bps,
500000 bps,
1 Mbps
− − TOOL0
UART0
(when external
device is used)
UART 115200 bps,
250000 bps,
500000 bps,
1 Mbps
− − TOOLTxD,
TOOLRxD
Notes 1. Selection items for standard settings on GUI of the flash memory programmer.
2. Because factors other than the baud rate error, such as the signal waveform slew, also affect UART
communication, thoroughly evaluate the slew as well as the baud rate error.
RL78/G12 CHAPTER 24 FLASH MEMORY
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24.5.4 Communication commands
The RL78/G12 communicates with the dedicated flash memory programmer or external device by using commands.
The signals sent from the flash memory programmer or external device to the RL78/G12 are called commands, and the
signals sent from the RL78/G12 to the dedicat ed flash memory programmer or external device are ca lled response.
Figure 24-9. Communication Commands
Command
Response
RL78/G12
Dedicated flash
memory programmer
PG-FP5, FL-PR5 E1
External device
(such as microcontroller
and ASIC)
The flash memory control commands of the RL78/G12 are listed in the table below. All these commands are issued
from the programmer or external device, and the RL78/G12 perform processing corresponding to the respective
commands.
Table 24-7. Flash Memory Control Commands
Classification Command Name Function
Verify Verify Compares the contents of a specified area of the flash memory with
data transmitted from the programmer.
Erase Block Erase Erases a specified area in the flash memory.
Blank check Block Blank Check Checks if a specified block in the flash memory has been correctly
erased.
Write Programming Writes data to a specified area in the flash memory.
Silicon Signature Gets the RL78/G12 information (such as the part number and flash
memory configuration, firmware version).
Getting information
Checksum Gets the checksum data for a specified area.
Security Set Sets security information.
Security Get Gets security information.
Security
Security Release Releases the write prohibition setting.
Reset Used to detect synchronization status of communication. Others
Baud Rate Set Sets baud rate when UART communication mode is selected.
The RL78/G12 returns a response for the command issued by the dedicated flash memory programmer or external
device. The response names sent from the RL78/G12 are l isted below.
Table 24-8. Response Nam es
Response Name Function
ACK Acknowledges command/data.
NAK Acknowledges illegal command/data.
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24.5.5 Description of signature data
When the “silicon signature” command is performed, the RL78/G12 information (such as the part number, flash
memory configuration, and programmi ng fir mware version) can be obtained.
Table 24-9 and 24-10 sh ow signature data list and example of signature data list.
Table 24-9. Signature Data List
Field name Description Number of transmit
data
Device code The serial number assigned to the device 3 bytes
Device name Device name (ASCII code) 10 bytes
Code flash memory area last address Last address of code flash memory are a
(Sent from lower address.
Example. 00000H to 03FFFH (16 KB) → FFH, 3F H, 00H)
3 bytes
Data flash memory area last address Last address of data flash memory area
(Sent from lower address.
Example. F1000H to F17FFH (2 KB) → FFH, 17H, 0FH)
3 bytes
Firmware version Version information of firmware for programming
(Sent from upper address.
Example. From Ver. 1.23 → 01H, 02H, 03 H)
3 bytes
Table 24-10. Example of Signature Data
Field name Description Number of transmit
data Data (hexadecimal)
Device code RL78 protocol A 3 bytes 10 00 06
Device name R5F102AA 10 bytes 52 = “R”
35 = “5”
46 = “F”
31 = “1”
30 = “0”
32 = “2”
41 = “A”
41 = “A”
20 = “ ”
20 = “ ”
Code flash memory area last address Code flash memory area
00000H to 03FFFH (16 KB)
3 bytes FF FF 00
Data flash memory area last address Data flash memory area
F1000H to F17FFH (2 KB)
3 bytes FF 17 0F
Firmware version Ver.1.23 → 01H, 02H, 03H) 3 bytes 01 02 03
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24.6 Security Settings
The RL78/G12 supports a sec urity function that prohibits rewriting the user program written to the internal flash memory,
so that the program cannot be changed by an unauthorized person.
The operations shown below can be performed by using the Security Set command.
• Disabling block erase
Execution of the block erase command for a specific block in the flash memory is prohibited during on-board/off-
board programming. However, blocks can be erased by means of self programmi ng.
• Disabling write
Execution of the write command for all the blocks in the flash memory is prohibited during on-board/off-board
programming. However, data can be written by means of self programming.
• Disabling rewriting boot cluster 0
Execution of the block erase command and write command on boot cluster 0 (00000H to 00FFFH) in the flash
memory is prohibited by this setting.
After the security settings are specified, relea sing the secu rity settings b y the Secur it y Release comm and is enabled by
a reset.
The block erase, write, and rewriting boot cluster0 commands are enabled by default when the flash memory is shipped.
Security can be set by on-board/off-board programming only. The security settings can be used in comb ination.
Table 24-11 shows the relationship between the erase and write commands when the RL78/G12 security function is
enabled.
Caution The secu rity function of the flash programmer does n ot support self-programming.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function. (see 24.7.1)
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Table 24-11. Relationship Between Enabled Security Function and Commands
(1) During on-board/off-board programming
Executed Command Enabled Security Function
Block Erase Write
Prohibition of block erasure Blocks cannot be erased. Can be performedNote.
Prohibition of writing Blocks can be erased. Cannot be performed.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Caution Confirm that no data has been w ritten to the write area. Because data cannot be erased when block
erasure is prohibited, do not write data if the data has not been erased.
(2) During self programming
Executed Command Enabled Security Function
Block Erase Write
Prohibition of block erasure
Prohibition of writing
Blocks can be erased. Can be performed.
Prohibition of rewriting boot cluster 0 Boot cluster 0 cannot be erased. Boot cluster 0 cannot be written.
Remark To prohibit writing and erasing during self-programming, use the flash shield window function. (see 24.7.1)
Table 24-12. Security Setting in Each Programming Mode
On-board/off-board programming
Security Security Setting How to Disable Security Setting
Prohibition of block erasure Cannot be disabled after setting.
Prohibition of writing Execute security release command
Prohibition of rewriting boot cluster 0
Use the GUI of dedicated flash memory
programmer.
Cannot be disabled after setting.
Caution The security release command can be applied only when the security is not set as the block erase
prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash
memory area being blanks.
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24.7 Flash Memory Programming by Self-Programming
The RL78/G12 supports a self -programming function that can be used to r ewrite the flash memory via a user program.
Because this function allows a user application to rewrite the flash memory by using the RL78/G12 self-programming
library, it can be used to upgrade the pr ogram in the field.
Cautions 1. An interrup t is prohibited during self-programming. Execute the sel f-programming library in the
state where the IE flag is cleared (0) by the DI instruction.
2. When RAM parity error rese t is en abled (RPERDIS = 0), be sure to in itialize “R AM area to be used
+ 10byte” before rewriting.
3. The high-speed on-chip oscillator clock needs to be operating during self-programming. If the
high-speed on-chip oscillator clock is stopped, execute the self-programming library 30 μs after
operation of the high-speed on-chip oscillator clock is started (HIOSTOP = 0).
4. The self-programming function cannot be used in the R5F 10266 and R5F10366.
Remarks 1. For details of the self-programming function and the RL78/G12 self-programming library, refer to RL78
Microcontroller Self Programming Library Type01 User’s Manual (R01AN0350E).
2. For details of the time required to exec ute self programming, see the notes on use that accompany the
flash self programming library tool.
Similar to when writing data by using the flash memory programmer, the re are two flash memory programming m odes
for which the voltage range in which to write, erase, or verify data differs.
Table 24-13. Programming Modes and Voltages at Which Data Can Be Written, Erased , o r Verified
Mode Voltages at which data can be written, erased, or verified Writing Clock Frequency
1.8 V to 5.5 V 8 MHz (MAX.)
2.4 V to 5.5 V 16 MHz (MAX.)
Wide voltage mode
2.7 V to 5.5 V 24 MHz (MAX.)
2.4 V to 5.5 V 16 MHz (MAX.)
Full speed mode Note
2.7 V to 5.5 V 24 MHz (MAX.)
Note This can only be specified if the CMODE1 and CMODE0 bits of the option byte 000C2H are 1.
Specify the mode that corr esp onds to th e volt age ra nge in which to write data. If the argument fsl_flas h_ voltage_u 08 is
other than 00H when the FSL_Init function of the self programming library provided by Renesas Electronics is executed,
wide-voltage mode is specified. If the argument is 00H, full-speed mode is specified.
Remarks 1. Using both the wide voltage mode and full speed mode imposes no restrictions on writing,
deletion, or verification.
2. For details of the self-programming functio n and the RL78/ G12 self-progr amming l ibrar y, refer to
RL78 Microcontroller Self Prog rammin g Library Type01 User’s Manual (R01AN0350E).
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RL78/G12 CHAPTER 24 FLASH MEMORY
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The following figure illustrates a flow of rewriting the flash memory by using a self programming li brary.
Figure 24-10. Flow of Self Programming (Rewriting Flash Memory)
Initialize flash environment
Flash memory control start
Flash shield window setting
Erase
Write
Flash information getting
Close flash environment
End
Flash information setting
Verify
• Inhibit access to flash memory
• Inhibit shifting STOP mode
• Inhibit clock stop
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24. 7.1 Flash shield window function
The flash shield window function is one of the security funct ions in self-programmin g. The flash shield windo w function
is a security function that prohibits writing and erasing outside the specified window range only during self-progr amming.
The window range c an be set by specifying the start an d en d bl ocks. T he window range can be set or changed b y only
on-board/off-board programming.
Writing and erasing are prohibited in areas other than the window range during self-programming. However, writing
and erasing can be done in ranges not specified as the window during on-board/off-board programming.
Figure 24-11. An example of setting a flash shield window
(Target device: R5F1026A, start block: 04H, and end block: 06H)
Flash memory
area
OK: On-board/Off-board programming
NG: Self-programming
OK: On-board/Off-board programming
NG: Self-programming
OK: On-board/Off-board programming
OK: Self-programming
Block
01H
Block
02H
Block
03H
Window area
Flash shield
area
Flash shield
area
Block
05H
Block
06H
(End block)
Block
04H
(Start block)
Block
0FH
Block
0EH
03FFFH
01C00H
01BFFH
01000H
00FFFH
00000H
Available writing method
Block
00H
Caution A flash shie ld window can be set only for code flash (data flash is not supported).
table 24-14. Setting and chan g ing of the flash shield window function and relations with commands
Execution command
Programming
condition Setting/Changing window
range Block erasure Writing
During on-board/off-
board programming Specify the start block and
end block of the window on
the GUI of the dedicated
flash memory programmer.
Block erasure can be
done also outside the
window range.
Writing can be done
also outside the window
range.
Note To prohibit writing and erasing dur ing on-board/off-board progr amming, refer to "24.6 Security
Settings."
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CHAPTER 25 ON-CHIP DEBUG FUNCTION
25.1 Connecting E1 On-chip Debugging Emulator to RL78/G12
The RL78/G12 uses the VDD, RESET, TOOL0, and VSS pins to communicate with the host machine via an E1 on-chip
debugging emulator. Serial communication is performed by using a single-line UA RT that uses the TOOL0 pin.
Caution The RL78/G12 has an on-chip debug function, which is provided for development and evaluation. Do
not use the on-chip debug function in products designated for mass production, because the
guaranteed number of rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
Figure 25-1. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (20, 24-pin products)
V
DD
EMVDD
GND
GND
GND
TOOL0
RESET
RESET
RSTPU
TRESET
V
DD
V
DD
V
DD
V
DD
8
9
2
12
14
5
10
13
4
6
V
DD
GND
TOOL0
RESET
Note
Note
Target connector
Reset circuit
Reset signal
RL78/G12
1 kΩ
1 kΩ
470 to 510 Ω
Note Connecting the dotted line is not necessary during flash programming.
RL78/G12 CHAPTER 25 ON-CHIP DEBUG FUNCTION
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For the target system which uses the multi-use feature of RESET pin in 20, 24-pin products, its connection to an
external circuit should be isolated.
Figure 25-2. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (When using to the
alternative function of RESET pin)
V
DD
EMVDD
GND
GND
GND
TOOL0
RSTPU
V
DD
V
DD
V
DD
V
DD
8
9
2
12
14
5
10
13
4
6
V
DD
GND
TOOL0
Alternate Function
of RESET pin
Output pin
Target connector
RESET
RESET
TRESET
External circuit
RL78/G12
Figure 25-3. Connection Example of E1 On-chip Debugging Emulator and RL78/G12 (30-pin products)
V
DD
TOOL0
V
DD
Target connector
Reset circuit
Reset signal
GND
GND GND
GND
TOOL0
RESETRESET
RESET
TRESET
Note 2
Note 1
V
DD
V
DD
V
DD
V
DD
10 kΩ1 kΩ
1 kΩ
RL78/G12
V
DD
EMV
DD
8
9
2
12
14
5
10
13
6
Notes 1. Connecting the dotted line is not necessary during flash programming.
2. If the reset circuit on the target system does not have a buffer and generates a reset signal only with
resistors and capacitors, this pull-up resistor is not necessary.
Caution This circuit diagram is assumed that the reset signal outputs from an N-ch O.D. buffer (output
resistor: 100 Ω or less)
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25.2 On-Chip Debug Security ID
The RL78/G12 has an on-chi p debug oper ation control b it in the flash memory at 000C3H (see CHAPTER 23 OPTION
BYTE) and an on-chip debug security ID setting area at 000C4H to 000CDH, to prevent third parties from reading m e mor y
content.
Table 25-1. On-Chip Debug Security ID
Address On-Chip Debug Security ID
000C4H to 000CDH Any ID code of 10 bytes
25.3 Securing of User Resources
To perform communication between the RL78/G12 and E1 on-chip debugging emulator, as well as eac h debug function,
the securing of memory space must be done beforehand.
If Renesas Electronics assembler or compiler is used, the items can be set b y using linker options.
(1) Securement of memory space
The shaded portions in Figure 25-4 are the areas reserved for placing the debug monitor program, so user
programs or data cannot be allocated in thes e spaces. When using the on- chip debug fu n ction, these s paces must
be secured so as not to be used by the user program. Moreover, this area must not be rewritten by the user
program.
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Figure 25-4. Memory Spaces Where Debug Monitor Programs Are Allocated
00000H
00002H
000C3H
000C4H
000CEH
000D8H
Code flash memory
Use prohibited
(512/256 KB Note 2)
Note 1
Debug monitor area
(10 bytes)
Security ID area
(10 bytes)
Debug monitor area
(2 bytes)
Note 3
Code flash
area
On-chip debug option byte area
(1 byte)
Internal RAM
SFR area
Stack area for debugging
(4 bytes)
Note 4
Mirror area
Internal RAM
area
: Area used for on-chip debugging
00FFFH
Boot
cluster 0
Notes 1. Address d iffers depending on products as follows.
Products (code flash memory capacity) Address of Note 1
R5F10266, R5F10366 00600H/00700H to 007FFH
R5F10x67, R5F10x77, R5F10xA7 00E00H/00F 00H to 00FFFH
R5F10x68, R5F10x78, R5F10xA8 01E00H/01F 00H to 01FFFH
R5F10x69, R5F10x79, R5F10xA9 02E00H/02F 00H to 02FFFH
R5F10x6A, R5F10x7A, R5F10xAA 03E00H/03F00H to 03FFFH
(x = 2, 3)
2. When real-time RAM monitor (RRM) function and dynamic memory modification (DMM) function are not
used, it is 256 bytes.
3. In debugging, reset vector is rewritten to address allocated to a monitor pro gram.
4. Since this area is allocated immediately before the stack area, the address of this area varies depending on
the stack increase and decrease. That is, 4 extra bytes are consumed for the stack area used. When using
self-programming, 12 extra bytes are consumed for the stack area used.
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CHAPTER 26 BCD CORRECTION CIRCUIT
26.1 BCD Correction Circuit Function
The result of addition/subtraction of the BCD (binary-coded decimal) code and BCD code can be obtained as BCD
code with this circuit.
The decimal correction operation result is obtained by performing addition/subtraction having the A register as the
operand and then addin g/ subtracting the BCD correction result register (BCDADJ).
26.2 Registers Used by BCD Correction Circuit
The BCD correction circuit uses the follo wing registers.
• BCD correction result register (BCDADJ)
(1) BCD correction result register (BCDADJ)
The BCDADJ register stores correction values for obtaining the add/subtract result as BCD code through
add/subtract instructions using the A register as the operand.
The value read from the BCDA DJ register varies d epend ing on the value of the A register when it is rea d and those
of the CY and AC flags.
The BCDADJ register is read by an 8-bit memor y manipulation instruction.
Reset input sets this register to undefined.
Figure 26-1. Format of BCD Correction Result Register (BCDADJ)
Address: F00FEH After reset: undefined R
Symbol 7 6 5 4 3 2 1 0
BCDADJ
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26.3 BCD Correction Circuit Operation
The basic operation of the BCD correction circuit is as follows.
(1) Addition: Calculating the result of adding a BCD code value and another BCD code value by using a
BCD code value
<1> T he BCD code value to which addition is performed is stored in the A register.
<2> By adding the value of the A register and the second operand (value of one more BCD code to be added) as
are in binary, the binary operation result is stored in the A register and the correction value is stored in the
BCD correction result register (BCDADJ).
<3> Decimal correction is perform ed by adding in binary the v alue of the A register (addition result in binary) and
the BCDADJ register (correction value), an d the correction result is stored in the A register and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction <3>
after the instruction <2> instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Examples 1: 99 + 89 = 188
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #99H ; <1> 99H − − −
ADD A, #89H ; <2> 22H 1 1 66H
ADD A, !BCDADJ ; <3> 88H 1 0 −
Examples 2: 85 + 15 = 100
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #85H ; <1> 85H − − −
ADD A, #15H ; <2> 9AH 0 0 66H
ADD A, !BCDADJ ; <3> 00H 1 1 −
Examples 3: 80 + 80 = 160
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #80H ; <1> 80H − − −
ADD A, #80H ; <2> 00H 1 0 60H
ADD A, !BCDADJ ; <3> 60H 1 0 −
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(2) Subtraction: Calculating the result of subtracting a BCD code value from another BCD code value by
using a BCD code value
<1> The BCD code value from which subtraction is performed is stored in the A register.
<2> By subtracting the value of the second operand (value of BCD code to be subtracted) from the A register as is
in binary, the calculation result in binary is stored in the A register, and the correction value is stored in the
BCD correction result register (BCDADJ).
<3> Decimal correction is performed by subtracting the value of the BCDADJ register (correction value) from the A
register (subtraction result in binar y) in binary, and the correction result is stored in the A register and CY flag.
Caution The value read from the BCDADJ register varies depending on the value of the A register
when it is read and those of the CY and AC flags. Therefore, execute the instruction <3>
after the instruction <2> instead of executing any other instructions. To perform BCD
correction in the interrupt enabled state, saving and restoring the A register is required
within the interrupt function. PSW (CY flag and AC flag) is restored by the RETI instruction.
An example is shown below.
Example: 91 − 52 = 39
Instruction A Register CY Flag AC Flag BCDADJ
Register
MOV A, #91H ; <1> 91H − − −
SUB A, #52H ; <2> 3FH 0 1 06H
SUB A, !BCDADJ ; <3> 39H 0 0 −
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CHAPTER 27 INSTRUCTION SET
This chapter lists the instructions in the RL78 microcontroller instruction set. For details of each operation and
operation code, refer to the separate document RL78 Microcontrollers User’s Manual: software (R01US0015E).
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27.1 Conventions Used in Operation List
27.1.1 Operand identifiers and sp ecification methods
Operands are described in th e “Operand” column of each instruction in accordance with the description metho d of the
instruction operand identifier (refer to the assembler specifications for details). When there are two or more description
methods, select one of them. Alphabetic letters in capitals and the symbols, #, !, !!, $, $!, [ ], and ES: are keywords and
are described as they are. Each symbol has the following meaning.
• #: Immediate data specific ation
• !: 16-bit absolute address specification
• !!: 20-bit absol ute address specification
• $: 8-bit relative a ddress specification
• $!: 16-bit relative address specification
• [ ]: Indirect address specification
• ES:: Extension address specification
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe the #, !, !!, $, $!, [ ], and ES: symbols.
For operand register identifiers, r and rp, either function names (X, A, C, etc.) or absolute names (names in
parentheses in Table 27-1 below, R0, R1, R2, etc.) can be used for description.
Table 27-1. Operand Identifiers and Specification Methods
Identifier Description Method
r
rp
sfr
sfrp
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special-function register symbol (SFR symbol) FFF00H to FFFFFH
Special-function register symbols (16-bit manipulatable SFR symbol. Even addresses onlyNote) FFF00H to
FFFFFH
saddr
saddrp FFE20H to FFF1FH Immediate data or labels
FFE20H to FF1FH Immediate data or labels (even addresses onlyNote)
addr20
addr16
addr5
00000H to FFFFFH Immediate data or labels
0000H to FFFFH Immediate data or labels (Automatically adds F to the top. only even addresses for 16-bit
data transfer instructionsNote)
0080H to 00BFH Immediate data or labels (specification to bits 5 to 1, even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
RBn RB0 to RB3
Note Bit 0 = 0 when an odd address is specified.
Remark The special function registers can be described to operand sfr as symbols. See Table 3-6 SFR List for the
symbols of the special function registers. The extended special function registers can be described to
operand !addr16 as symbols. See Table 3-7 Extended SFR (2nd SFR) List for the symbols of the extended
special function registers.
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27.1.2 Description of operation column
The operation when the instruction is executed is shown in the “Operation” column using the following symbols.
Table 27-2. Symbols in “Operation” Column
Symbol Function
A A register; 8-bit accumulator
X X register
B B register
C C register
D D register
E E register
H H register
L L register
ES ES register
CS CS register
AX AX register pair; 16-bit accumulator
BC BC register pair
DE DE register pair
HL HL register pair
PC Program counter
SP Stack pointer
PSW Program status word
CY Carry flag
AC Auxiliary carry flag
Z Zero flag
RBS Register bank select flag
IE Interrupt request enable flag
() Memory contents indicated by address or register contents in parentheses
XH, XL
XS, XH, XL 16-bit registers: XH = higher 8 bits, XL = lower 8 bits
20-bit registers: XS = (bits 19 to 16), XH = (bits 15 to 8), XL = (bits 7 to 0)
∧ Logical product (AND)
∨ Logical sum (OR)
∨ Exclusive logical sum (exclusive OR)
−
Inverted data
addr5
16-bit immediate data (even addresses only in 0080H to 00BFH)
addr16 16-bit immediate data
addr20 20-bit immediate data
jdisp8 Signed 8-bit data (displacement value)
jdisp16 Signed 16-bit data (displacement value)
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27.1.3 Description o f flag operation column
The change of the flag value when the instruction is executed is shown in the “Flag” column using the following symbols.
Table 27-3. Symbols in “F lag ” Column
Symbol Change of Flag Value
(Blank)
0
1
×
R
Unchanged
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
27.1.4 PREFIX instruction
Instructions with “ES:” have a PREFIX o peration c ode as a prefi x to extend the accessi ble data area to the 1 MB s pace
(00000H to FFFFFH), by adding the ES register value to the 64 KB space from F0000H to FFFFFH. When a PREFIX
operation code is attache d as a prefix to the target instruction, only one instruction immediately after th e PREFIX operation
code is executed as the addresses with the ES register value added.
A interrupt and DMA transfer are not acknowledged between a PREFIX instruction code and the instruction
immediately after.
Table 27-4. Use Example of PREFIX Operation Code
Opcode Instruction
1 2 3 4 5
MOV !addr16, #byte CFH !addr16 #byte −
MOV ES:!addr16, #byte 11H CFH !addr16 #byte
MOV A, [HL] 8BH − − − −
MOV A, ES:[HL] 11H 8BH − − −
Caution Set the ES register value w ith MOV ES, A, etc., befo re executing the PREFIX instruction.
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27.2 Operation List Table 27-5. Operation L ist (1/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
r, #byte 2 1 − r ← byte
PSW, #byte 3 3 − PSW ← byte × × ×
CS, #byte 3 1 − CS ← byte
ES, #byte 2 1 − ES ← byte
!addr16, #byte 4 1 − (addr16) ← byte
ES:!addr16, #byte 5 2 − (ES, addr16) ← byte
saddr, #byte 3 1 − (saddr) ← byte
sfr, #byte 3 1 − sfr ← byte
[DE+byte], #byte 3 1 − (DE+byte) ← byte
ES:[DE+byte],#byte 4 2 − ((ES, DE)+byte) ← byte
[HL+byte], #byte 3 1 − (HL+byte) ← byte
ES:[HL+byte],#byte 4 2 − ((ES, HL)+byte) ← byte
[SP+byte], #byte 3 1 − (SP+byte) ← byte
word[B], #byte 4 1 − (B+word) ← byte
ES:word[B], #byte 5 2 − ((ES, B)+word) ← byte
word[C], #byte 4 1 − (C+word) ← byte
ES:word[C], #byte 5 2 − ((ES, C)+word) ← byte
word[BC], #byte 4 1 − (BC+word) ← byte
ES:word[BC], #byte 5 2 − ((ES, BC)+word) ← byte
A, r Note 3 1 1
− A ← r
r, A Note 3 1 1
− r ← A
A, PSW 2 1 − A ← PSW
PSW, A 2 3 − PSW ← A × × ×
A, CS 2 1 − A ← CS
CS, A 2 1 − CS ← A
A, ES 2 1 − A ← ES
ES, A 2 1 − ES ← A
A, !addr16 3 1 4 A ← (addr16)
A, ES:!addr16 4 2 5 A ← (ES, addr16)
!addr16, A 3 1 − (addr16) ← A
ES:!addr16, A 4 2 − (ES, addr16) ← A
A, saddr 2 1 − A ← (saddr)
8-bit data
transfer MOV
saddr, A 2 1 − (saddr) ← A
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Table 27-5. Operation List (2/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, sfr 2 1 − A ← sfr
sfr, A 2 1 − sfr ← A
A, [DE] 1 1 4 A ← (DE)
[DE], A 1 1 − (DE) ← A
A, ES:[DE] 2 2 5 A ← (ES, DE)
ES:[DE], A 2 2 − (ES, DE) ← A
A, [HL] 1 1 4 A ← (HL)
[HL], A 1 1 − (HL) ← A
A, ES:[HL] 2 2 5 A ← (ES, HL)
ES:[HL], A 2 2 − (ES, HL) ← A
A, [DE+byte] 2 1 4 A ← (DE + byte)
[DE+byte], A 2 1 − (DE + byte) ← A
A, ES:[DE+byte] 3 2 5 A ← ((ES, DE) + byte)
ES:[DE+byte], A 3 2 − ((ES, DE) + byte) ← A
A, [HL+byte] 2 1 4 A ← (HL + byte)
[HL+byte], A 2 1 − (HL + byte) ← A
A, ES:[HL+byte] 3 2 5 A ← ((ES, HL) + byte)
ES:[HL+byte], A 3 2 − ((ES, HL) + byte) ← A
A, [SP+byte] 2 1 − A ← (SP + byte)
[SP+byte], A 2 1 − (SP + byte) ← A
A, word[B] 3 1 4 A ← (B + word)
word[B], A 3 1 − (B + word) ← A
A, ES:word[B] 4 2 5 A ← ((ES, B) + word)
ES:word[B], A 4 2 − ((ES, B) + word) ← A
A, word[C] 3 1 4 A ← (C + word)
word[C], A 3 1 − (C + word) ← A
A, ES:word[C] 4 2 5 A ← ((ES, C) + word)
ES:word[C], A 4 2 − ((ES, C) + word) ← A
A, word[BC] 3 1 4 A ← (BC + word)
word[BC], A 3 1 − (BC + word) ← A
A, ES:word[BC] 4 2 5 A ← ((ES, BC) + word)
8-bit data
transfer MOV
ES:word[BC], A 4 2 − ((ES, BC) + word) ← A
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Table 27-5. Operation List (3/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, [HL+B] 2 1 4 A ← (HL + B)
[HL+B], A 2 1 − (HL + B) ← A
A, ES:[HL+B] 3 2 5 A ← ((ES, HL) + B)
ES:[HL+B], A 3 2 − ((ES, HL) + B) ← A
A, [HL+C] 2 1 4 A ← (HL + C)
[HL+C], A 2 1 − (HL + C) ← A
A, ES:[HL+C] 3 2 5 A ← ((ES, HL) + C)
ES:[HL+C], A 3 2 − ((ES, HL) + C) ← A
X, !addr16 3 1 4 X ← (addr16)
X, ES:!addr16 4 2 5 X ← (ES, addr16)
X, saddr 2 1 − X ← (saddr)
B, !addr16 3 1 4 B ← (addr16)
B, ES:!addr16 4 2 5 B ← (ES, addr16)
B, saddr 2 1 − B ← (saddr)
C, !addr16 3 1 4 C ← (addr16)
C, ES:!addr16 4 2 5 C ← (ES, addr16)
C, saddr 2 1 − C ← (saddr)
MOV
ES, saddr 3 1 − ES ← (saddr)
A, r Note 3 1 (r = X)
2 (other
than r = X
)
1 − A ←→ r
A, !addr16 4 2 − A ←→ (addr16)
A, ES:!addr16 5 3 − A ←→ (ES, addr16)
A, saddr 3 2 − A ←→ (saddr)
A, sfr 3 2 − A ←→ sfr
A, [DE] 2 2 − A ←→ (DE)
A, ES:[DE] 3 3 − A ←→ (ES, DE)
A, [HL] 2 2 − A ←→ (HL)
A, ES:[HL] 3 3 − A ←→ (ES, HL)
A, [DE+byte] 3 2 − A ←→ (DE + byte)
A, ES:[DE+byte] 4 3 − A ←→ ((ES, DE) + byte)
A, [HL+byte] 3 2 − A ←→ (HL + byte)
8-bit data
transfer
XCH
A, ES:[HL+byte] 4 3 − A ←→ ((ES, HL) + byte)
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Table 27-5. Operation List (4/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except rp = AX
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, [HL+B] 2 2 − A ←→ (HL+B)
A, ES:[HL+B] 3 3 − A ←→ ((ES, HL)+B)
A, [HL+C] 2 2 − A ←→ (HL+C)
XCH
A, ES:[HL+C] 3 3 − A ←→ ((ES, HL)+C)
A 1 1
− A ← 01H
X 1 1
− X ← 01H
B 1 1
− B ← 01H
C 1 1
− C ← 01H
!addr16 3 1
− (addr16) ← 01H
ES:!addr16 4 2
− (ES, addr16) ← 01H
ONEB
saddr 2 1
− (saddr) ← 01H
A 1 1
− A ← 00H
X 1 1
− X ← 00H
B 1 1
− B ← 00H
C 1 1
− C ← 00H
!addr16 3 1
− (addr16) ← 00H
ES:!addr16 4 2
− (ES,addr16) ← 00H
CLRB
saddr 2 1
− (saddr) ← 00H
[HL+byte], X 3 1 − (HL+byte) ← X × ×
8-bit data
transfer
MOVS
ES:[HL+byte], X 4 2 − (ES, HL+byte) ← X × ×
rp, #word 3 1 − rp ← word
saddrp, #word 4 1 − (saddrp) ← wo r d
sfrp, #word 4 1 − sfrp ← word
AX, rp Note 3 1 1
− AX ← rp
rp, AX Note 3 1 1
− rp ← AX
AX, !addr16 3 1 4 AX ← (addr16)
!addr16, AX 3 1 − (addr16) ← AX
AX, ES:!addr16 4 2 5 AX ← (ES, addr16)
ES:!addr16, AX 4 2 − (ES, addr16) ← AX
AX, saddrp
2 1 − AX ← (saddrp)
saddrp, AX
2 1 − (saddrp) ← AX
AX, sfrp
2 1 − AX ← sfrp
16-bit
data
transfer
MOVW
sfrp, AX
2 1 − sfrp ← AX
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Table 27-5. Operation List (5/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
AX, [DE] 1 1 4 AX ← (DE)
[DE], AX 1 1 − (DE) ← AX
AX, ES:[DE] 2 2 5 AX ← (ES, DE)
ES:[DE], AX 2 2 − (ES, DE) ← AX
AX, [HL] 1 1 4 AX ← (HL)
[HL], AX 1 1 − (HL) ← AX
AX, ES:[HL] 2 2 5 AX ← (ES, HL)
ES:[HL], AX 2 2 − (ES, HL) ← AX
AX, [DE+byte] 2 1 4 AX ← (DE+byte)
[DE+byte], AX 2 1 − (DE+byte) ← AX
AX, ES:[DE+byte] 3 2 5 AX ← ((ES, DE) + byte)
ES:[DE+byte], AX 3 2 − ((ES, DE) + byte) ← AX
AX, [HL+byte] 2 1 4 AX ← (HL + byte)
[HL+byte], AX 2 1 − (HL + byte) ← AX
AX, ES:[HL+byte] 3 2 5 AX ← ((ES, HL) + byte)
ES:[HL+byte], AX 3 2 − ((ES, HL) + byte) ← AX
AX, [SP+byte] 2 1 − AX ← (SP + byte)
[SP+byte], AX 2 1 − (SP + byte) ← AX
AX, word[B] 3 1 4 AX ← (B + word)
word[B], AX 3 1 − (B+ word) ← AX
AX, ES:word[B] 4 2 5 AX ← ((ES, B) + word)
ES:word[B], AX 4 2 − ((ES, B) + word) ← AX
AX, word[C] 3 1 4 AX ← (C + word)
word[C], AX 3 1 − (C + word) ← AX
AX, ES:word[C] 4 2 5 AX ← ((ES, C) + word)
ES:word[C], AX 4 2 − ((ES, C) + word) ← AX
AX, word[BC] 3 1 4 AX ← (BC + word)
word[BC], AX 3 1 − (BC + word) ← AX
AX, ES:word[BC]
4 2 5 AX ← ((ES, BC) + word)
16-bit
data
transfer
MOVW
ES:word[BC], AX
4 2 − ((ES, BC) + word) ← AX
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Table 27-5. Operation List (6/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except rp = AX
4. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
BC, !addr16 3 1 4 BC ← (addr16)
BC, ES:!addr16 4 2 5 BC ← (ES, addr16)
DE, !addr16 3 1 4 DE ← (addr16)
DE, ES:!addr16 4 2 5 DE ← (ES, addr16)
HL, !addr16 3 1 4 HL ← (addr16)
HL, ES:!addr16 4 2 5 HL ← (ES, addr16)
BC, saddrp 2 1 − BC ← (saddrp)
DE, saddrp 2 1 − DE ← (saddrp)
MOVW
HL, saddrp 2 1 − HL ← (saddrp)
XCHW AX, rp
Note 3 1 1
− AX ←→ rp
AX 1 1
− AX ← 0001H ONEW
BC 1 1
− BC ← 0001H
AX 1 1
− AX ← 0000H
16-bit
data
transfer
CLRW
BC 1 1
− BC ← 0000H
A, #byte 2 1 − A, CY ← A + byte × × ×
saddr, #byte 3 2 − (saddr), C Y ← (saddr)+byte × × ×
A, r Note 4 2 1
− A, CY ← A + r × × ×
r, A 2 1 − r, CY ← r + A × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16) × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16) × × ×
A, saddr 2 1 − A, CY ← A + (saddr) × × ×
A, [HL] 1 1 4 A, CY ← A+ (HL) × × ×
A, ES:[HL] 2 2 5 A,CY ← A + (ES, HL) × × ×
A, [HL+byte] 2 1 4 A, CY ← A + (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A + ((ES, HL)+byte) × × ×
A, [HL+B] 2 1 4 A, CY ← A + (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A+((ES, HL)+B) × × ×
A, [HL+C] 2 1 4 A, CY ← A + (HL+C) × × ×
8-bit
operation ADD
A, ES:[HL+C] 3 2 5 A,CY ← A + ((ES, HL) + C) × × ×
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Table 27-5. Operation List (7/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, #byte 2 1 − A, CY ← A+byte+CY × × ×
saddr, #byte 3 2 − (saddr), C Y ← (saddr) +byte+CY × × ×
A, rv Note 3 2 1
− A, CY ← A + r + CY × × ×
r, A 2 1 − r, CY ← r + A + CY × × ×
A, !addr16 3 1 4 A, CY ← A + (addr16)+CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A + (ES, addr16)+CY × × ×
A, saddr 2 1 − A, CY ← A + (saddr)+CY × × ×
A, [HL] 1 1 4 A, CY ← A+ (HL) + CY × × ×
A, ES:[HL] 2 2 5 A,CY ← A+ (ES, HL) + CY × × ×
A, [HL+byte] 2 1 4 A, CY ← A+ (HL+byte) + CY × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A+ ((ES, HL)+byte) + CY × × ×
A, [HL+B] 2 1 4 A, CY ← A+ (HL+B) +CY × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A+((ES, HL)+B)+CY × × ×
A, [HL+C] 2 1 4 A, CY ← A+ (HL+C)+CY × × ×
ADDC
A, ES:[HL+C] 3 2 5 A,CY ← A+ ((ES, HL)+C)+CY × × ×
A, #byte 2 1 − A, CY ← A − byte × × ×
saddr, #byte 3 2 − (saddr), C Y ← (saddr) − byte × × ×
A, r Note 3 2 1
− A, CY ← A − r × × ×
r, A 2 1 − r, CY ← r − A × × ×
A, !addr16 3 1 4 A, CY ← A − (addr16) × × ×
A, ES:!addr16 4 2 5 A, CY ← A – (ES, addr16) × × ×
A, saddr 2 1 − A, CY ← A – (saddr) × × ×
A, [HL] 1 1 4 A, CY ← A – (HL) × × ×
A, ES:[HL] 2 2 5 A,CY ← A – (ES, HL) × × ×
A, [HL+byte] 2 1 4 A, CY ← A – (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A – ((ES, HL)+byte) × × ×
A, [HL+B] 2 1 4 A, CY ← A – (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A – ((ES, HL)+B) × × ×
A, [HL+C] 2 1 4 A, CY ← A – (HL+C) × × ×
8-bit
operation
SUB
A, ES:[HL+C] 3 2 5 A,CY ← A – ((ES, HL)+C) × × ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 762
Sep. 28, 2012
Table 27-5. Operation List (8/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, #byte 2 1 − A, CY ← A – byte – CY × × ×
saddr, #byte 3 2 − (saddr), C Y ← (saddr) – byte – CY × × ×
A, r Note 3 2 1
− A, CY ← A – r – CY × × ×
r, A 2 1 − r, CY ← r – A – CY × × ×
A, !addr16 3 1 4 A, CY ← A – (addr16) – CY × × ×
A, ES:!addr16 4 2 5 A, CY ← A – (ES, addr16) – CY × × ×
A, saddr 2 1 − A, CY ← A – (saddr) – CY × × ×
A, [HL] 1 1 4 A, CY ← A – (HL) – CY × × ×
A, ES:[HL] 2 2 5 A,CY ← A – (ES, HL) – CY × × ×
A, [HL+byte] 2 1 4 A, CY ← A – (HL+byte) – CY × × ×
A, ES:[HL+byte] 3 2 5 A,CY ← A – ((ES, HL)+byte) – CY × × ×
A, [HL+B] 2 1 4 A, CY ← A – (HL+B) – CY × × ×
A, ES:[HL+B] 3 2 5 A,CY ← A – ((ES, HL)+B) – CY × × ×
A, [HL+C] 2 1 4 A, CY ← A – (HL+C) – CY × × ×
SUBC
A, ES:[HL+C] 3 2 5 A, CY ← A – ((ES:HL)+C) – CY × × ×
A, #byte 2 1 − A ← A ∧ byte ×
saddr, #byte 3 2 − (saddr) ← (saddr) ∧ byte ×
A, r Note 3 2 1
− A ← A ∧ r ×
r, A 2 1 − R ← r ∧ A ×
A, !addr16 3 1 4 A ← A ∧ (addr16) ×
A, ES:!addr16 4 2 5 A ← A ∧ (ES:addr16) ×
A, saddr 2 1 − A ← A ∧ (saddr) ×
A, [HL] 1 1 4 A ← A ∧ (HL) ×
A, ES:[HL] 2 2 5 A ← A ∧ (ES:HL) ×
A, [HL+byte] 2 1 4 A ← A ∧ (HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A ∧ ((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A ∧ (HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A ∧ ((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A ∧ (HL+C) ×
8-bit
operation
AND
A, ES:[HL+C] 3 2 5 A ← A ∧ ((ES:HL)+C) ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 763
Sep. 28, 2012
Table 27-5. Operation List (9/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, #byte 2 1 − A ← A∨byte ×
saddr, #byte 3 2 − (saddr) ← (saddr)∨byte ×
A, r Note 3 2 1
− A ← A∨r ×
r, A 2 1 − r ← r∨A ×
A, !addr16 3 1 4 A ← A∨(addr16) ×
A, ES:!addr16 4 2 5 A ← A∨(ES:addr16) ×
A, saddr 2 1 − A ← A∨(saddr) ×
A, [HL] 1 1 4 A ← A∨(H) ×
A, ES:[HL] 2 2 5 A ← A∨(ES:HL) ×
A, [HL+byte] 2 1 4 A ← A∨(HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A∨((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A∨(HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A∨((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A∨(HL+C) ×
OR
A, ES:[HL+C] 3 2 5 A ← A∨((ES:HL)+C) ×
A, #byte 2 1 − A ← A∨byte ×
saddr, #byte 3 2 − (saddr) ← (saddr)∨byte ×
A, r Note 3 2 1
− A ← A∨r ×
r, A 2 1 − r ← r∨A ×
A, !addr16 3 1 4 A ← A∨(addr16) ×
A, ES:!addr16 4 2 5 A ← A∨(ES:addr16) ×
A, saddr 2 1 − A ← A∨(saddr) ×
A, [HL] 1 1 4 A ← A∨(HL) ×
A, ES:[HL] 2 2 5 A ← A∨(ES:HL) ×
A, [HL+byte] 2 1 4 A ← A∨(HL+byte) ×
A, ES:[HL+byte] 3 2 5 A ← A∨((ES:HL)+byte) ×
A, [HL+B] 2 1 4 A ← A∨(HL+B) ×
A, ES:[HL+B] 3 2 5 A ← A∨((ES:HL)+B) ×
A, [HL+C] 2 1 4 A ← A∨(HL+C) ×
8-bit
operation
XOR
A, ES:[HL+C] 3 2 5 A ← A∨((ES:HL)+C) ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 764
Sep. 28, 2012
Table 27-5. Operation List (10/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. Except r = A
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
A, #byte 2 1 − A – byte × × ×
!addr16, #byte 4 1 4 (addr16) – byte × × ×
ES:!addr16, #byte 5 2 5 (ES:addr16) – byte × × ×
saddr, #byte 3 1 − (saddr) – byte × × ×
A, r Note3 2 1
− A – r × × ×
r, A 2 1 − r – A × × ×
A, !addr16 3 1 4 A – (addr16) × × ×
A, ES:!addr16 4 2 5 A – (ES:addr16) × × ×
A, saddr 2 1 − A – (saddr) × × ×
A, [HL] 1 1 4 A – (HL) × × ×
A, ES:[HL] 2 2 5 A – (ES:HL) × × ×
A, [HL+byte] 2 1 4 A – (HL+byte) × × ×
A, ES:[HL+byte] 3 2 5 A – ((ES:HL)+byte) × × ×
A, [HL+B] 2 1 4 A – (HL+B) × × ×
A, ES:[HL+B] 3 2 5 A – ((ES:HL)+B) × × ×
A, [HL+C] 2 1 4 A – (HL+C) × × ×
CMP
A, ES:[HL+C] 3 2 5 A – ((ES:HL)+C) × × ×
A 1 1
− A – 00H × 0 0
X 1 1
− X – 00H × 0 0
B 1 1
− B – 00H × 0 0
C 1 1
− C – 00H × 0 0
!addr16 3 1 4 (addr16) – 00H × 0 0
ES:!addr16 4 2 5 (ES:addr16) – 00H × 0 0
CMP0
saddr 2 1
− (saddr) – 00H × 0 0
X, [HL+byte] 3 1 4 X – (HL+byte) × × ×
8-bit
operation
CMPS
X, ES:[HL+byte] 4 2 5 X – ((ES:HL)+byte) × × ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 765
Sep. 28, 2012
Table 27-5. Operation List (11/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
AX, #word 3 1 − AX, CY ← AX+word × × ×
AX, AX 1 1 − AX, CY ← AX+AX × × ×
AX, BC 1 1 − AX, CY ← AX+BC × × ×
AX, DE 1 1 − AX, CY ← AX+DE × × ×
AX, HL 1 1 − AX, CY ← AX+HL × × ×
AX, !addr16 3 1 4 AX, CY ← AX+(addr16) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX+(ES:addr16) × × ×
AX, saddrp 2 1 − AX, CY ← AX+(saddrp) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX+(HL+byte) × × ×
ADDW
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX+((ES:HL)+byte) × × ×
AX, #word 3 1 − AX, CY ← AX – word × × ×
AX, BC 1 1 − AX, CY ← AX – BC × × ×
AX, DE 1 1 − AX, CY ← AX – DE × × ×
AX, HL 1 1 − AX, CY ← AX – HL × × ×
AX, !addr16 3 1 4 AX, CY ← AX – (addr16) × × ×
AX, ES:!addr16 4 2 5 AX, CY ← AX – (ES:addr16) × × ×
AX, saddrp 2 1 − AX, CY ← AX – (saddrp) × × ×
AX, [HL+byte] 3 1 4 AX, CY ← AX – (HL+byte) × × ×
SUBW
AX, ES: [HL+byte] 4 2 5 AX, CY ← AX – ((ES:HL)+byte) × × ×
AX, #word 3 1 − AX – word × × ×
AX, BC 1 1 − AX – BC × × ×
AX, DE 1 1 − AX – DE × × ×
AX, HL 1 1 − AX – HL × × ×
AX, !addr16 3 1 4 AX – (addr16) × × ×
AX, ES:!addr16 4 2 5 AX – (ES:addr16) × × ×
AX, saddrp 2 1 − AX – (saddrp) × × ×
AX, [HL+byte] 3 1 4 AX – (HL+byte) × × ×
16-bit
operation
CMPW
AX, ES: [HL+byte] 4 2 5 AX – ((ES:HL)+byte) × × ×
Multiply MULU X 1 1 − AX ← A×X
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 766
Sep. 28, 2012
Table 27-5. Operation List (12/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remarks 1. Number of cl ock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
2. cnt indicates the bit shift count.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
r 1 1
− r ← r+1 × ×
!addr16 3 2
− (addr16) ← (addr16)+1 × ×
ES:!addr16 4 3
− (ES, addr16) ← (ES, addr16)+1 × ×
saddr 2 2
− (saddr) ← (saddr)+1 × ×
[HL+byte] 3 2 − (HL+byte) ← (HL+byte)+1 × ×
INC
ES: [HL+byte] 4 3 − ((ES:HL)+byte) ← ((ES:HL)+byte)+1 × ×
r 1 1
− r ← r – 1 × ×
!addr16 3 2
− (addr16) ← (addr16) – 1 × ×
ES:!addr16 4 3
− (ES, addr16) ← (ES, addr16) – 1 × ×
saddr 2 2
− (saddr) ← (saddr) – 1 × ×
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) – 1 × ×
DEC
ES: [HL+byte] 4 3 − ((ES:HL)+byte) ← ((ES:HL)+byte) – 1 × ×
rp 1 1
− rp ← rp+1
!addr16 3 2
− (addr16) ← (addr16)+1
ES:!addr16 4 3
− (ES, addr16) ← (ES, addr16)+1
saddrp 2 2
− (saddrp) ← (saddrp)+1
[HL+byte] 3 2 − (HL+byte) ← (HL+byte)+1
INCW
ES: [HL+byte] 4 3 − ((ES:HL)+byte) ← ((ES:HL)+byte)+1
rp 1 1
− rp ← rp – 1
!addr16 3 2
− (addr16) ← (addr16) – 1
ES:!addr16 4 3
− (ES, addr16) ← (ES, addr16) – 1
saddrp 2 2
− (saddrp) ← (saddrp) – 1
[HL+byte] 3 2 − (HL+byte) ← (HL+byte) – 1
Increment/
decrement
DECW
ES: [HL+byte] 4 3 − ((ES:HL)+byte) ← ((ES:HL)+byte) – 1
SHR A, cnt 2 1 − (CY ← A0, Am-1 ← Am, A7 ← 0) ×cnt ×
SHRW AX, cnt 2 1 − (CY ← AX0, AXm-1 ← AXm, AX15 ← 0) ×cnt ×
A, cnt 2 1 − (CY ← A7, Am ← Am-1, A0 ← 0) ×cnt ×
B, cnt 2 1 − (CY ← B7, Bm ← Bm-1, B0 ← 0) ×cnt ×
SHL
C, cnt 2 1 − (CY ← C7, Cm ← Cm-1, C0 ← 0) ×cnt ×
AX, cnt 2 1 − (CY ← AX15, AXm ← AXm-1, AX0 ← 0) ×cnt ×SHLW
BC, cnt 2 1 − (CY ← BC15, BCm ← BCm-1, BC0 ← 0) ×cnt ×
SAR A, cnt 2 1 − (CY ← A0, Am-1 ← Am, A7 ← A7) ×cnt ×
Shift
SARW AX, cnt 2 1 − (CY ← AX0, AXm-1 ← AX m, AX15← AX15) ×cnt ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 767
Sep. 28, 2012
Table 27-5. Operation List (13/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
ROR A, 1 2 1 − (CY, A7 ← A0, Am-1 ← Am)×1 ×
ROL A, 1 2 1 − (CY, A0 ← A7, Am+1 ← Am)×1 ×
RORC A, 1 2 1 − (CY ← A0, A7 ← CY, Am-1 ← Am)×1 ×
ROLC A, 1 2 1 − (CY ← A7, A0 ← CY, Am+1 ← Am)×1 ×
AX,1 2 1
− (CY ← AX15, AX0 ← CY, AXm+1 ← AXm) ×1 ×
Rotate
ROLWC
BC,1 2 1
− (CY ← BC15, BC0 ← CY, BCm+1 ← BCm) ×1 ×
CY, A.bit 2 1 − CY ← A.bit ×
A.bit, CY 2 1 − A.bit ← CY
CY, PSW.bit 3 1 − CY ← PSW.bit ×
PSW.bit, CY 3 4 − PSW.bit ← CY × ×
CY, saddr.bit 3 1 − CY ← (saddr).bit ×
saddr.bit, CY 3 2 − (saddr).bit ← CY
CY, sfr.bit 3 1 − CY ← sfr.bit ×
sfr.bit, CY 3 2 − sfr.bit ← CY
CY,[HL].bit 2 1 4 CY ← (HL).bit ×
[HL].bit, CY 2 2 − (HL).bit ← CY
CY, ES:[HL].bit 3 2 5 CY ← (ES, HL).bit ×
MOV1
ES:[HL].bit, CY 3 3 − (ES, HL).bit ← CY
CY, A.bit 2 1 − CY ← CY ∧ A.bit ×
CY, PSW.bit 3 1 − CY ← CY ∧ PSW.bit ×
CY, saddr.bit 3 1 − CY ← CY ∧ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∧ sfr.bit ×
CY,[HL].bit 2 1 4 CY ← CY ∧ (HL).bit ×
AND1
CY, ES:[HL].bit 3 2 5 CY ← CY ∧ (ES, HL).bit ×
CY, A.bit 2 1 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1 − CYX ← CY ∨ ∨PSW.bit ×
CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
Bit
manipulate
OR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 768
Sep. 28, 2012
Table 27-5. Operation List (14/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
CY, A.bit 2 1 − CY ← CY ∨ A.bit ×
CY, PSW.bit 3 1 − CY ← CY ∨ PSW.bit ×
CY, saddr.bit 3 1 − CY ← CY ∨ (saddr).bit ×
CY, sfr.bit 3 1 − CY ← CY ∨ sfr.bit ×
CY, [HL].bit 2 1 4 CY ← CY ∨ (HL).bit ×
XOR1
CY, ES:[HL].bit 3 2 5 CY ← CY ∨ (ES, HL).bit ×
A.bit 2 1
− A.bit ← 1
PSW.bit 3 4
− PSW.bit ← 1 × × ×
!addr16.bit 4 2
− (addr16).bit ← 1
ES:!addr16.bit 5 3
− (ES, addr16).bit ← 1
saddr.bit 3 2
− (saddr).bit ← 1
sfr.bit 3 2
− sfr.bit ← 1
[HL].bit 2 2
− (HL).bit ← 1
SET1
ES:[HL].bit 3 3
− (ES, HL).bit ← 1
A.bit 2 1
− A.bit ← 0
PSW.bit 3 4
− PSW.bit ← 0 × × ×
!addr16.bit 4 2
− (addr16).bit ← 0
ES:!addr16.bit 5 3
− (ES, addr16).bit ← 0
saddr.bit 3 2
− (saddr.bit) ← 0
sfr.bit 3 2
− sfr.bit ← 0
[HL].bit 2 2
− (HL).bit ← 0
CLR1
ES:[HL].bit 3 3
− (ES, HL).bit ← 0
SET1 CY 2 1 − CY ← 1 1
CLR1 CY 2 1 − CY ← 0 0
Bit
manipulate
NOT1 CY 2 1 − CY ← CY ×
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 769
Sep. 28, 2012
Table 27-5. Operation List (15/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
rp 2 3
− (SP – 2) ← (PC+2)S, (SP – 3) ← (PC+2)H,
(SP – 4) ← (PC+2)L, PC ← CS, rp,
SP ← SP – 4
$!addr20 3 3
− (SP – 2) ← (PC+3)S, (SP – 3) ← (PC+3)H,
(SP – 4) ← (PC+3)L, PC ← PC+3+jdisp16,
SP ← SP – 4
!addr16 3 3
− (SP – 2) ← (PC+3)S, (SP – 3) ← (PC+3)H,
(SP – 4) ← (PC+3)L, PC ← 0000, addr16,
SP ← SP – 4
CALL
!!addr20 4 3
− (SP – 2) ← (PC+4)S, (SP – 3) ← (PC+4)H,
(SP – 4) ← (PC+4)L, PC ← addr20,
SP ← SP – 4
CALLT [addr5] 2 5
− (SP – 2) ← (PC+2)S , (SP – 3) ← (PC+2)H,
(SP – 4) ← (PC+2)L , PCS ← 0000,
PCH ← (0000, addr5+1),
PCL ← (0000, addr5),
SP ← SP – 4
BRK - 2 5
− (SP – 1) ← PSW, (SP – 2) ← (PC+2)S,
(SP – 3) ← (PC+2)H, (SP – 4) ← (PC+2)L,
PCS ← 0000,
PCH ← (0007FH), PCL ← (0007EH),
SP ← SP – 4, IE ← 0
RET - 1 6
− PCL ← (SP), PCH ← (SP+1),
PCS ← (SP+2), SP ← SP+4
RETI - 2 6
− PCL ← (SP), PCH ← (SP+1),
PCS ← (SP+2), PSW← (SP+3),
SP ← SP+4
R R R
Call/
return
RETB - 2 6
− PCL ← (SP), PCH ← (SP+1),
PCS ← (SP+2), PSW ← (SP+3),
SP ← SP+4
R R R
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 770
Sep. 28, 2012
Table 27-5. Operation List (16/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. This indicates the number of clocks “when condition is not met/when condition is met”.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemon
ic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
PSW 2 1
− (SP − 1) ← PSW, (SP − 2) ← 00H,
SP ← SP−2
PUSH
rp 1 1
− (SP − 1) ← rpH, (SP − 2) ← rpL,
SP ← SP – 2
PSW 2 3
− PSW ← (SP+1), SP ← SP + 2 R R RPOP
rp 1 1
− rpL ←(SP), rpH ← (SP+1), SP ← SP + 2
SP, #word 4 1 − SP ← word
SP, AX 2 1 − SP ← AX
AX, SP 2 1 − AX ← SP
HL, SP 3 1 − HL ← SP
BC, SP 3 1 − BC ← SP
MOVW
DE, SP 3 1 − DE ← SP
ADDW SP, #byte 2 1 − SP ← SP + byte
Stack
manipul ate
SUBW SP, #byte 2 1 − SP ← SP − byte
AX 2 3
− PC ← CS, AX
$addr20 2 3
− PC ← PC + 2 + jdisp8
$!addr20 3 3
− PC ← PC + 3 + jdisp16
!addr16 3 3
− PC ← 0000, addr16
Unconditio
nal branch
BR
!!addr20 4 3
− PC ← addr20
BC $addr20 2 2/4
Note3 − PC ← PC + 2 + jdisp8 if CY = 1
BNC $addr20 2 2/4
Note3 − PC ← PC + 2 + jdisp8 if CY = 0
BZ $addr20 2 2/4
Note3 − PC ← PC + 2 + jdisp8 if Z = 1
BNZ $addr20 2 2/4
Note3 − PC ← PC + 2 + jdisp8 if Z = 0
BH $addr20 3 2/4
Note3 − PC ← PC + 3 + jdisp8 if (Z∨CY)=0
BNH $addr20 3 2/4
Note3 − PC ← PC + 3 + jdisp8 if (Z∨CY)=1
saddr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 1
sfr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if sfr.bit = 1
A.bit, $addr20 3 3/5 Note3 − PC ← PC + 3 + jdisp8 if A.bit = 1
PSW.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if PSW.bit = 1
[HL].bit, $addr20 3 3/5 Note3 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 1
Conditional
branch
BT
ES:[HL].bit,
$addr20 4 4/6
Note3 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
RL78/G12 CHAPTER 27 INSTRUCTION SET
R01UH0200EJ0110 Rev.1.10 771
Sep. 28, 2012
Table 27-5. Operation List (17/17)
Notes 1. Number of CPU clocks (fCLK) when the internal RAM area, SFR area, or extended SFR area is accessed, or
when no data is accessed.
2. Number of CPU clocks (fCLK) when the program memory area is accessed.
3. This indicates the number of clocks “when condition is not met/when condition is met”.
Remark Number of clock is when program exists in the internal ROM (flash memory) area. If fetching the instruction
from the internal RAM area, the number becomes double number plus 3 clocks at a maximum.
Clocks Flag
Instruction
Group Mnemonic Operands Bytes
Note 1 Note 2
Clocks
Z AC CY
saddr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 0
sfr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if sfr.bit = 0
A.bit, $addr20 3 3/5 Note3 − PC ← PC + 3 + jdisp8 if A.bit = 0
PSW.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if PSW.bit = 0
[HL].bit, $addr20 3 3/5 Note3 6/7 PC ← PC + 3 + jdisp8 if (HL).bit = 0
BF
ES:[HL].b it ,
$addr20 4 4/6
Note3 7/8 PC ← PC + 4 + jdisp8 if (ES, HL).bit = 0
saddr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if (saddr).bit = 1
then reset (saddr).bit
sfr.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if sfr.bit = 1
then reset sfr.bit
A.bit, $addr20 3 3/5 Note3 − PC ← PC + 3 + jdisp8 if A.bit = 1
then reset A.bit
PSW.bit, $addr20 4 3/5 Note3 − PC ← PC + 4 + jdisp8 if PSW.bit = 1
then reset PSW.bit
× × ×
[HL].bit, $addr20 3 3/5 Note3 − PC ← PC + 3 + jdisp8 if (HL).bit = 1
then reset (HL).bit
Condition
al branch
BTCLR
ES:[HL].b it ,
$addr20 4 4/6
Note3 − PC ← PC + 4 + jdisp8 if (ES, HL).bit = 1
then reset (ES, HL).bit
SKC − 2 1 − Next instruction skip if CY = 1
SKNC − 2 1 − Next instruction skip if CY = 0
SKZ − 2 1 − Next instruction skip if Z = 1
SKNZ − 2 1 − Next instruction skip if Z = 0
SKH − 2 1 − Next instruction skip if (Z∨CY)=0
Conditional
skip
SKNH − 2 1 − Next instruction skip if (Z∨CY)=1
SEL Note4 RBn 2 1 − RBS[1:0] ← n
NOP − 1 1 − No Operation
EI − 3 4 − IE ← 1 (Enable Interrupt)
DI − 3 4 − IE ← 0 (Disable Interrupt)
HALT − 2 3 − Set HALT Mode
CPU
control
STOP − 2 3 − Set STOP Mode
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 772
Sep. 28, 2012
CHAPTER 28 ELECTRICAL SPECIFICATIONS
Cautions 1. The RL78/G12 has an on-chip debug function, which is provided for development and evaluation.
Do not use the on-chip debug function in products designated for mass production, because the
guaranteed number o f rewritable times of the flash memory may be exceeded when this function is
used, and product reliability therefore cannot be guaranteed. Renesas Electronics is not liable for
problems occurring when the on-chip debug function is used.
2. The pins mounted depend on the product. Refer to 2.1 Port Function to 2.2.1 Functions Mounted
According to Product.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 773
Sep. 28, 2012
28.1 Absolute Maximum Ratings
Absolute Maximum Ratings (TA = 25°C)
Parameter Symbols Conditions Ratings Unit
VDD −0.5 to + 6.5 V Supply Voltage
VSS −0.5 to + 0.3 V
REGC terminal input
voltageNote 1
VIREGC REGC −0.3 to +2.8
and −0.3 to VDD + 0.3Note 2
V
VI1 Other than P60, P61 −0.3 to VDD + 0.3Note 3 V Input Voltage
VI2 P60, P61 (N-ch open drain) −0.3 to 6.5 V
Output Voltage VO −0.3 to VDD + 0.3Note 3 V
Analog input voltage VAI ANI0 to ANI22 −0.3 to VDD + 0.3Note 3
and −0.3 to
AVREF(+)+0.3 Note 3
V
Per pin Other than P20 to P23 −40 mA
All the terminals other than P20 to P23 −170 mA
20-, 24-pin products: P40 to P42
30-pin products: P00, P01, P40, P120
−70 mA
IOH1
Total of
all pins
20-, 24-pin products: P00 to P03Note 4,
P10 to P14
30-pin products: P10 to P17, P30,
P31, P50, P51, P147
−100 mA
Per pin −0.5 mA
Output current, high
IOH2
Total of
all pins
P20 to P23
−2 mA
Per pin Other than P20 to P23 40 mA
All t he t erminals ot h er than P2 0 t o P 23 170 mA
20-, 24-pin products: P40 to P42
30-pin products: P00, P01, P40, P120
70 mA
IOL1
Total of
all pins
20-, 24-pin products: P00 to P03,
P10 to P14, P60, P61
30-pin products: P1 0 t o P 1 7 , P 3 0 ,
P31, P50, P51, P60, P 61, P147
100 mA
Per pin 1 mA
Output current, low
IOL2
Total of
all pins
P20 to P23
5 mA
Operating ambient
temperature TA −40 to +85 °C
Storage temperature Tstg −65 to +150 °C
Notes 1. 30-pin product only.
2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). This value determines the absolute maximum
rating of the REGC pin. Do not use it with voltage applied.
3. Must be 6.5 V or lower.
4. 24-pin product only.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolu te maximu m ratings are not exceeded.
Remarks 1. Unless specifie d other wise, the characteristics of alternate-f unction pi ns are the same as those of the port
pins.
2. AVREF (+) : + side reference voltage of the A/D converter.
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 774
Sep. 28, 2012
28.2 Oscillator Characteristics
28.2.1 X1 clock oscillator characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Resonator Recommended Circuit Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0
X1 clock oscillation
frequency (fX)Note Ceramic resonator
/ crystal oscillator
C1
X2X1
C2
V
SS
Rd
1.8 V ≤ VDD < 2.7 V 1.0 8.0
MHz
Note Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
Cautions 1. When using the X1 oscillator, wire as follows in the area enclosed by the broken lines in the above
figures to avoid an adverse effect from wiring capacitance.
• Keep the wiring length as short as possible.
• Do not cross the wiring with the other signal lines.
• Do not route the wiring near a signal line through which a high fluctuating current flows.
• Always make the ground point of the oscillator capacitor the same potential as VSS.
• Do not ground the capacitor to a ground pattern through which a high current flows.
• Do not fetch signals from the oscillator.
2. Since the CPU is started by the high-speed on-chip oscillator clock after a reset release, check the X1
clock oscillation stabilization time using the oscillation stabilization time counter status register
(OSTC) by the user. Determine the oscillation stabilization time of the OSTC register and the
oscillation stabilization time select register (OSTS) after sufficiently evaluating the oscillation
stabilization time with the resonator to be used.
28.2.2 On-chip oscillator characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Oscillators Parameters Conditions MIN. TYP. MAX. Unit
High-speed on-chip oscillator
oscillation frequency Note 1 fIH 1 24 MHz
TA = -20 to +85 °C -1
+1
% R5F102
TA = -40 to -20 °C -1.5
+1.5 %
High-speed on-chip oscillator
oscillation frequency
accuracy Note 2
R5F103 -5
+5 %
Low-speed on-chip oscillator
oscillation frequency fIL 15 kHz
Low-speed on-chip oscillator
oscillation frequency
accuracy
-15 +15 %
Notes 1. High-speed on-chip oscillator frequency is selected by bits 0 to 3 of option byte (000C2H/010C2H) and bits
0 to 2 of HOCODIV register.
2. This only indicates the oscil la tor characteristics. Refer to AC Characteristics for instruction execution time.
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 775
Sep. 28, 2012
28.3 DC Characteristics
28.3.1 Pin characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V) (1/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Per pin 20-, 24-pin products:
P00 to P03 Note 3,
P10 to P14,
P40 to P42
30-pin products: P00,
P01,
P10 to P17, P30,
P31, P40, P50, P51,
P120, P147
−10.0 mA
4.0 V ≤ VDD ≤ 5.5 V −30.0 mA
2.7 V ≤ VDD < 4.0 V −6.0 mA
20-, 24-pin products:
P40 to P42
30-pin products: P00,
P01, P40, P120 1.8 V ≤ VDD < 2.7 V −4.5 mA
4.0 V ≤ VDD ≤ 5.5 V −80.0 mA
2.7 V ≤ VDD < 4.0 V −18.0 mA
20-, 24-pin products:
P00 to P03 Note 3,
P10 to P14
30-pin products: P10
to P17, P30, P31,
P50, P51, P147
1.8 V ≤ VDD < 2.7 V −10.0 mA
IOH1
Total of all
pinsNote 2
All the terminals
−100 mA
Per pin −0.1 mA
Output current, highNote 1
IOH2
Total of all
pinsNote 2
P20 to P23
−0.4 mA
Notes 1. value of current at which the device operation is guaranteed even if the current flo ws from the VDD pin to an
output pin.
2. Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOH × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOH = −10.0 mA
Total output current of pins = (−10.0 × 0.7)/(50 × 0.01) = −14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolu te maximum rating must not flow into one pin.
3. 24-pin pro ducts only.
Caution P10 to P12, P41 for 20-pin products, P01, P10 to P12, P41 for 24-pin products, and P00, P10 to P15,
P17, P50 for 30-pin products, do not output high level in N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 776
Sep. 28, 2012
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V) (2/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
20-, 24-pin products:
P00 to P03 Note 3,
P10 to P14,
P40 to P42
30-pin products: P00,
P01, P10 to P17,
P30, P31, P40, P50,
P51, P120, P147
20.0 mA Per pin
P60, P61
15.0 mA
4.0 V ≤ VDD ≤ 5.5 V 60.0 mA
2.7 V ≤ VDD < 4.0 V 9.0 mA
20-, 24-pin products:
P40 to P42
30-pin products:
P00, P01, P40, P120 1.8 V ≤ VDD < 2.7 V 1.8 mA
4.0 V ≤ VDD ≤ 5.5 V 80.0 mA
2.7 V ≤ VDD < 4.0 V 27.0 mA
20-, 24-pin products:
P00 to P03 Note 3,
P10 to P14, P60, P61
30-pin products:
P10 to P17, P30,
P31, P50, P51, P60,
P61, P147
1.8 V ≤ VDD < 2.7 V 5.4 mA
IOL1
Total of all
pinsNote 2
All the terminals
140 mA
Per pin 0.4 mA
Output current, lowNote 1
IOL2
Total of all
pinsNote 2
P20 to P23
1.6 mA
Notes 1. Value of current at which the device operation is guaranteed even if the current flo ws from an output pin to
the VSS pin.
2. Specification under conditions where the duty factor is 70%.
The output current value that has changed the duty ratio can be calculated with the following expression
(when changing the duty factor from 70% to n%).
• Total output current of pins = (IOL × 0.7)/(n × 0.01)
<Example> Where n = 50% and IOL = 10.0 mA
Total output current of pins = (10.0 × 0.7)/(50 × 0.01) = 14.0 mA
However, the current that is allowed to flow into one pin does not vary depending on the duty factor. A
current higher than the absolu te maximum rating must not flow into one pin.
3. 24-pin pro ducts only.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 777
Sep. 28, 2012
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V) (3/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VIH1 Normal input buffer
20-, 24 -pin prod u cts: P00 to P03 Note 2, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P5 1, P1 20, P147
0.8VDD VDD V
4.0 V ≤ VDD ≤ 5.5 V 2.2 VDD V
3.3 V ≤ VDD < 4.0 V 2.0 VDD V
VIH2 TTL input buffer
20-, 24-p in products: P1 0, P1 1
30-pin products: P01, P10,
P11, P13 to P17 1.8 V ≤ VDD < 3.3 V 1.50 VDD V
VIH3 P20 to P23 0.7VDD VDD V
VIH4 P60, P61 0.7VDD 6.0 V
Input voltage, high
VIH5 P121, P122, P125, P137, EXCLK, RESET 0.8VDD VDD V
VIL1 Normal input buffer
20-, 24 -pin prod u cts: P00 to P03 Note 2, P10 to P14,
P40 to P42
30-pin products: P00, P01, P10 to P17, P30, P31,
P40, P50, P5 1, P1 20, P147
0 0.2VDD V
4.0 V ≤ VDD ≤ 5.5 V 0 0.8 V
3.3 V ≤ VDD < 4.0 V 0 0.5 V
VIL2 TTL input buffer
20-, 24-p in products: P1 0, P1 1
30-pin products: P01, P10,
P11, P13 t o P1 7 1.8 V ≤ VDD < 3.3 V 0 0.32 V
VIL3 P20 to P23 0 0.3VDD V
VIL4 P60, P61 0 0.3VDD V
Input voltage, low
VIL5 P121, P122, P125Note 1, P137, EXCLK, RESET 0 0.2VDD V
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −10.0 mA VDD−1.5 V
4.0 V ≤ VDD ≤ 5.5 V,
IOH1 = −3.0 mA VDD−0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOH1 = −2.0 mA VDD−0.6 V
VOH1 20-, 24-pin products:
P00 to P03Note 2, P10 to P14,
P40 to P42
30-pin products:
P00, P01, P10 to P17, P30,
P31, P40, P50, P51, P120,
P147 1.8 V ≤ VDD ≤ 5.5 V,
IOH1 = −1.5 mA VDD−0.5 V
Output voltage, high
VOH2 P20 to P23 IOH2 = −100
μ
A VDD−0.5 V
Notes 1. 20, 24-pin pro ducts only.
2. 24-pin products only.
Caution The maximum value of VIH of pins P01, P10 to P12, P41, for 20-, 24-pin products and P00, P10 to P15,
P17, P50 for 30-pin products is VDD even in N-ch open-drain mode.
High level is not output in the N-ch open-drain mode.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 778
Sep. 28, 2012
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V) (4/4)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 20.0 mA 1.3 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL1 = 8.5 mA 0.7 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 3.0 mA 0.6 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL1 = 1.5 mA 0.4 V
VOL1 20-, 24-pin products:
P00 to P03Note, P10 to P14,
P40 to P42
30-pin products: P00, P01,
P10 to P17, P30, P31, P40,
P50, P51, P120, P147
1.8 V ≤ VDD ≤ 5.5 V,
IOL1 = 0.6 mA 0.4 V
VOL2 P20 to P23 IOL2 = 400
μ
A 0.4 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 15.0 mA 2.0 V
4.0 V ≤ VDD ≤ 5.5 V,
IOL3 = 5.0 mA 0.4 V
2.7 V ≤ VDD ≤ 5.5 V,
IOL3 = 3.0 mA 0.4 V
Output voltage, low
VOL3 P60, P61
1.8 V ≤ VDD ≤ 5.5 V,
IOL3 = 2.0 mA 0.4 V
ILIH1 Other than P121,
P122 VI = VDD 1
μ
A
Input port or external
clock input 1
μ
A
Input leakage current,
high
ILIH2 P121, P122
(X1, X2/EXCLK) VI = VDD
When resonator
connected 10
μ
A
ILIL1 Other than P121,
P122 VI = VSS −1
μ
A
Input port or external
clock input −1
μ
A
Input leakage current,
low
ILIL2 P121, P122
(X1, X2/EXCLK) VI = VSS
When resonator
connected −10
μ
A
On-chip pull-up
resistance RU 20-, 24-pin products:
P00 to P03Note, P10 to P14,
P40 to P42, P125, RESET
30-pin products: P00, P01,
P10 to P17, P30, P31, P40,
P50, P51, P120, P147,
RESET
VI = VSS, input port 10 20 100 kΩ
Note 24-pin products onl y.
Remark Unless specified otherwise, the characteristics of alternate-function pins are the same as those of the port
pins.
<R>
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 779
Sep. 28, 2012
28.3.2 Supply current characteristics
(1) 20-, 24-pin products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 1.5
Basic
operation
VDD = 3.0 V 1.5
mA
VDD = 5.0 V 3.3 5.0
f
IH
= 24 MHz
Note 3
VDD = 3.0 V 3.3 5.0
mA
VDD = 5.0 V 2.5 3.7
HS(High-speed
main) mode
Note 2
f
IH
= 16 MHz
Note 3
VDD = 3.0 V 2.5 3.7
mA
VDD = 3.0 V 1.2 1.8
LS(Low-speed
main) mode
Note 2
f
IH
= 8 MHz
Note 3
VDD = 2.0 V 1.2 1.8
mA
Square wave input 2.8 4.4
f
MX
= 20 MHz
Note 4
,
V
DD
= 5.0 V
Resonator connection 3.0 4.6
mA
Square wave input 2.8 4.4
f
MX
= 20 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 3.0 4.6
mA
Square wave input 1.8 2.6
f
MX
= 10 MHz
Note 4
,
V
DD
= 5.0 V
Resonator connection 1.8 2.6
mA
Square wave input 1.8 2.6
HS(High-speed
main) mode
Note 2
f
MX
= 10 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 1.8 2.6
mA
Square wave input 1.1 1.7
f
MX
= 8 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 1.1 1.7
mA
Square wave input 1.1 1.7
Supply
currentNote 1 IDD1 Operating
mode
LS(Low-speed
main) mode
Note 2
f
MX
= 8 MHz
Note 4
,
V
DD
= 2.0 V
Noramal
operation
Resonator connection 1.1 1.7
mA
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral op eration current (exc ept for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
V
DD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
3. When high-speed system clock is stopped
4. When high-speed on-chip osicllator clock is stopped.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
IH: high-speed on-chip oscillat or clock frequency
3. Temperature condition of the TY P. value is TA = 25°C.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 780
Sep. 28, 2012
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 440 1210fIH = 24 MHzNote 4
VDD = 3.0 V 440 1210
μ
A
VDD = 5.0 V 400 950
HS(High-speed
main) mode
Note 3
fIH = 16 MHzNote 4
VDD = 3.0 V 400 950
μ
A
VDD = 3.0 V 270 542
LS(Low-speed
main) mode
Note 3
fIH = 8 MHzNote 4
VDD = 2.0 V 270 542
μ
A
Square wave input 280 1000
fMX = 20 MHzNote 5,
VDD = 5.0 V
Resonator connection 450 1170
μ
A
Square wave input 280 1000
fMX = 20 MHzNote 5,
VDD = 3.0 V Resonator connection 450 1170
μ
A
Square wave input 190 590
fMX = 10 MHzNote 5,
VDD = 5.0 V Resonator connection 260 660
μ
A
Square wave input 190 590
HS(High-speed
main) mode
Note 3
fMX = 10 MHzNote 5,
VDD = 3.0 V
Resonator connection 260 660
μ
A
Square wave input 110 360
fMX = 8 MHzNote 5,
VDD = 3.0 V Resonator connection 150 416
μ
A
Square wave input 110 360
IDD2 HALT
mode Note 2
LS(Low-speed
main) mode
Note 3
fMX = 8 MHzNote 5,
VDD = 2.0 V Resonator connection 150 416
μ
A
TA = −40°C 0.19
TA = +25°C 0.24 0.50
TA = +50°C 0.25 0.80
TA = +70°C 0.28 1.20
Supply
currentNote 1
IDD3 STOP
mode Note 6
TA = +85°C 0.88 2.20
μ
A
Notes 1. Total current flowing into VDD, including the input leakage current flo wing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral op eration current (exc ept for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. During HALT instruction execution by flash memory.
3. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
V
DD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
4. When high-speed system clock is stopped.
5. When high-speed on-chip oscillator clock is stopped.
6. When high-speed on-chip oscillator clock, hi gh-speed system clock, and watchdog timer are stopped.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
IH: high-speed on-chip oscillat or clock frequency
3. Except temperature condition of the TYP. value is TA = 25°C, other than STOP mode
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 781
Sep. 28, 2012
(2) 30-pin products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (1/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 1.5
Basic
operation
VDD = 3.0 V 1.5
mA
VDD = 5.0 V 3.7 5.5
f
IH
= 24 MHz
Note 3
VDD = 3.0 V 3.7 5.5
mA
VDD = 5.0 V 2.7 4.0
HS(High-speed
main) mode
Note 2
f
IH
= 16 MHz
Note 3
VDD = 3.0 V 2.7 4.0
mA
VDD = 3.0 V 1.2 1.8
LS(Low-speed
main) mode
Note2
f
IH
= 8 MHz
Note 3
VDD = 2.0 V 1.2 1.8
mA
Square wave input 3.0 4.6
f
MX
= 20 MHz
Note 4
,
V
DD
= 5.0 V
Resonator connection 3.2 4.8
mA
Square wave input 3.0 4.6
f
MX
= 20 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 3.2 4.8
mA
Square wave input 1.9 2.7
f
MX
= 10 MHz
Note 4
,
V
DD
= 5.0 V
Resonator connection 1.9 2.7
mA
Square wave input 1.9 2.7
HS(High-speed
main) mode
Note 2
f
MX
= 10 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 1.9 2.7
mA
Square wave input 1.1 1.7
f
MX
= 8 MHz
Note 4
,
V
DD
= 3.0 V
Resonator connection 1.1 1.7
mA
Square wave input 1.1 1.7
Supply
currentNote 1 IDD1 Operating
mode
LS(Low-speed
main) mode
Note2
f
MX
= 8 MHz
Note 4
,
V
DD
= 2.0 V
Noramal
operation
Resonator connection 1.1 1.7
mA
Notes 1. Total current flowing into VDD, including the input leakage current flowing when the level of the input pin is
fixed to VDD or VSS. The values below the MAX. column include the peripheral op eration current (exc ept for
background operation (BGO)). However, not including the current flowing into the A/D converter, LVD
circuit, I/O port, and on-chip pull-up/pull-down resistors.
2. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
V
DD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
3. When high-speed system clock is stopped
4. When high-speed on-chip osicllator clock is stopped.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
IH: high-speed on-chip oscillat or clock frequency
3. Temperature condition of the TY P. value is TA = 25°C.
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 782
Sep. 28, 2012
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V) (2/2)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VDD = 5.0 V 440 1280fIH = 24 MHzNote 4
VDD = 3.0 V 440 1280
μ
A
VDD = 5.0 V 400 1000
HS(High-speed
main) mode
Note 3
fIH = 16 MHzNote 4
VDD = 3.0 V 400 1000
μ
A
VDD = 3.0 V 260 530
LS(Low-speed
main) mode
Note 3
fIH = 8 MHzNote 4
VDD = 2.0 V 260 530
μ
A
Square wave input 280 1000
fMX = 20 MHzNote 5,
VDD = 5.0 V
Resonator connection 450 1170
μ
A
Square wave input 280 1000
fMX = 20 MHzNote 5,
VDD = 3.0 V Resonator connection 450 1170
μ
A
Square wave input 190 600
fMX = 10 MHzNote 5,
VDD = 5.0 V Resonator connection 260 670
μ
A
Square wave input 190 600
HS(High-speed
main) mode
Note 3
fMX = 10 MHzNote 5,
VDD = 3.0 V
Resonator connection 260 670
μ
A
Square wave input 95 330
fMX = 8 MHzNote 5,
VDD = 3.0 V Resonator connection 145 380
μ
A
Square wave input 95 330
IDD2 HALT
mode Note 2
LS(Low-speed
main) mode
Note 3
fMX = 8 MHzNote 5,
VDD = 2.0 V Resonator connection 145 380
μ
A
TA = −40°C 0.18
TA = +25°C 0.23 0.50
TA = +50°C 0.26 1.10
TA = +70°C 0.29 1.90
Supply
currentNote 1
IDD3 STOP
mode Note 6
TA = +85°C 0.90 3.30
μ
A
Notes 1. Total current flowing into VDD, including the input leakage current flo wing when the level of the input pin is
fixed to VDD or VSS. The values belo w the MAX. col umn i nclude th e perip heral o perati on current. However,
not including the current flowing into the A/D converter, LVD circuit, I/O port, and on-chip pull-up/pull-down
resistors.
2. During HALT instruction execution by flash memory.
3. Relationship between operation voltage width, operation frequency of CPU and operation mode is as
follows.
HS(High speed main) mode: VDD = 2.7 V to 5.5 V @1 MHz to 24 MHz
V
DD = 2.4 V to 5.5 V @1 MHz to 16 MHz
LS(Low speed main) mode: VDD = 1.8 V to 5.5 V @1 MHz to 8 MHz
4. When high-speed system clock is stopped.
5. When high-speed on-chip oscillator clock is stopped.
6. When hig h-speed on-chip oscillator clock, high-speed s ystem clock, and watchdog timer are stopped. The
values below the MAX. column include the leakage current.
Remarks 1. f
MX: High-speed system clock frequency (X1 clock oscillation frequency or external main system clock
frequency)
2. f
IH: high-speed on-chip oscillat or clock frequency
3. Except STOP mode, temperature condition of the TYP. value is TA = 25°C.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 783
Sep. 28, 2012
(3) Common to RL78/G12 all products
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Parameter Symbol Conditions MIN. TYP. MAX. Unit
12-bit interval
timer operating
current
ITMKA Notes 1, 2 fIL = 15 kHz 0.22
μ
A
Watchdog timer
operating
current
IWDT Notes 1, 3 fIL = 15 kHz 0.22
μ
A
Normal mode, AVREFP = VDD = 5.0 V 1.30 1.70 mA A/D converter
operating
current
IADC Note 4 When
conversion at
maximum
speed
Low voltage mode, AVREFP = VDD = 3.0 V 0.50 0.70 mA
A/D converter
reference
voltage current
IADREF Note 5 75.0
μ
A
Temperature
sensor
operating
current
ITMPS Note 5 75.0
μ
A
LVD operating
current ILVD Note 6 0.08
μ
A
BGO operating
current IBGO Note 7 2.50 12.20
mA
The mode is performed Note 8 0.50 0.60 mA ADC operation
The A/D conversion operations are
performed, Low voltage mode, AVREFP =
VDD = 3.0 V
1.20 1.44 mA
SNOOZE
operating
current
ISNOZ Note 5
CSI/UART operation 0.70 0.84 mA
Notes 1. When high speed on-chip oscillator and high-speed s ystem clock are stopped.
2. Current flowing only to the 12-bit interval timer (including the operating current of the low-speed on-chip
oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
fCLK = fSUB when the watchdog timer operates in STOP mode.
3. Current flowing only to the watchdog timer (including the operating current of the 15 KHz low-speed on-chip
oscillator). The current value of the RL78/G12 microcontrollers is the sum of IDD1, IDD2 or IDD3 and IWDT when
fCLK = fSUB when the watchdog timer operates in STOP mode.
4. Current flowing only to the A/D converter. The current value of the RL78/G12 microcontrollers is the sum of
IDD1 or IDD2 and IADC when the A/D converter operates in an operation mod e or the HALT mode.
5. Current flowing to the VDD.
6. Current flo wing onl y to the LVD circuit. The current value of the RL78/G1 2 microcontrollers is the sum of IDD1,
IDD2 or IDD3 and IVLD when the LVD circuit operates in the Operating, HALT or STOP mode.
7. Current flowing only to the BGO. The current value of the RL78/G12 microcontrollers is the sum of IDD1 or IDD2
and IBGO when the BGO operates in an operation mode.
8. Refer to shift time to the SNOOZE mode, see 17.2.3 SNOOZE mode..
Remarks 1. fIL: Low-speed on- chip oscillator clock frequency
2. f
CLK: CPU/peripheral hardware clock frequency
3. Temperature condition of the TYP. value is TA = 25°C
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 784
Sep. 28, 2012
28.4 AC Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, V SS = 0 V )
Items Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 0.04167 1
μ
s
HS(High-speed main) mode
2.4 V ≤ VDD < 2.7 V 0.0625 1
μ
s
Instruction cycle (minimum
instruction execution time) TCY
LS(Low-speed main) mode 1.8 V ≤ VDD ≤ 5.5 V 0.125 1
μ
s
2.7 V ≤ VDD ≤ 5.5 V 1.0 20.0 MHz
External main system clock
frequency fEX
1.8 V ≤ VDD < 2.7 V 1.0 8.0 MHz
2.7 V ≤ VDD ≤ 5.5 V 24 ns
External main system clock
input high-level width, low-
level width
tEXH, tEXL
1.8 V ≤ VDD < 2.7 V 60 ns
T I 0 0 t o T I 0 7 input high-level
width, low-level width tTIH, tTIL
1/f
MCK
+ 10 n s
4.0 V ≤ VDD ≤ 5.5 V
12 MHz
2.7 V ≤ VDD < 4.0 V
8 MHz
TO00 to TO07 output
frequency fTO
1.8 V ≤ VDD < 2.7 V
4 MHz
4.0 V ≤ VDD ≤ 5.5 V
16 MHz
2.7 V ≤ VDD < 4.0 V
8 MHz
PCLBUZ0, or PCLBUZ1
output frequency fPCL
1.8 V ≤ VDD < 2.7 V
4 MHz
INTP0 to INTP5 input high-
level width, low-level width tINTH, tINTL 1
μ
s
K R 0 t o K R 9 input available
width tKR 250 ns
RESET low-level width tRSL 10
μ
s
Remark fMCK: Timer array unit operation clock freque ncy
(Operation clock to be set by the CKS0n bit of timer mode register 0n (TMR0n). n: Channel number (n = 0
to 7))
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
AC Timing Test Point
V
IH
V
IL
Test points V
IH
V
IL
External main system clock timing
E
XCLK 0.8V
DD
(MIN.
)
0.2V
DD
(MAX
.)
1/f
EX
t
EXL
t
EXH
TI timing
TI00 to TI07
tTIL tTIH
Interrupt Request Input Timing
INTP0 to INTP5
t
INTL
t
INTH
Key Interrupt Input Timing
KR0 to KR9
t
KR
RESET input timing
RESET
t
RSL
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 786
Sep. 28, 2012
28.5 Serial Communication Characteristics
28.5.1 Serial array unit
(1) During communication at same potential (UART mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Normal operation fMCK/6 bps
Theoretical value of the
maximum transfer rate
fCLK = fMCK = 24 MHz
4.0 Mbps
Transfer rate
SNOOZE mode 4800 9600 bps
UART mode connection diagram (during communication at same potential)
RL78/G12
TxDq
RxDq
Rx
Tx
User’s device
UART mode bit w idth (during communication at same p otential) (reference)
TxDq
RxDq
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Caution Select the normal input buffer for the RxDq pin and the normal output mode for the TxDq pin by
using port input mode register g (PIMg) and port output mode register g (POMg)
Remarks 1. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
2. f
MCK: Serial array unit operation clock freque ncy
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11))
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 787
Sep. 28, 2012
(2) During communication at same potential (CSI00 master mode (fMCK/2), SCK00... internal clock output)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
SCK00 cycle time tKCY1 2.7 V ≤ VDD ≤ 5.5 V 83.3 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 7 ns SCK00 high - /low-level width tKH1,
tKL1 2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 10 ns
4.0 V ≤ VDD ≤ 5.5 V 23 ns SI00 setup time (to SCK00↑) Note 2 tSIK1
2.7 V ≤ VDD ≤ 5.5 V 33 ns
SI00 hold time (to SCK00↑) Note2 tKSI1 2.7 V ≤ VDD ≤ 5.5 V 10 ns
Delay time from SCK00↓ to SO00 output Note 4 tKSO1 C = 20 pFNote 5 10 ns
Notes 1. The value must also be 2/fCLK or more.
2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 setup time becomes “to
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
3. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The SI00 hold time becomes “from
SCK00↓” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
4. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1. The delay time to SO00 output becomes
“from SCK00↑” when DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
5. C is the load capacitance of the SCK00 and SO0 output lines.
Caution Select the normal input buffer for the SI00 pin and the normal output mode for the SO00 and SCK00
pins by using port input mode register 1 (PIM1) and port output mode register 1 (POM1).
Remarks 1. This specification is valid only when CSI00’s peripheral I/O redirect function is not used.
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKS00 bit of serial mode register (SMR00).
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 788
Sep. 28, 2012
(3) During communication at same potential (CSI mode) (master mode (fMCK/4), SCKp... internal clock output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Notes 1. The value must also be 4/fCLK or more.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
5. C is the load capacitance of the SCKp and SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0,
POM1).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unito number (m = 0, 1), n: Channel number (n = 0, 1, 3: “1, 3” is
for the R5F102 products.)
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (n = 0, 1, 3; “1, 3” is for the R5F102 products.)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 167 Note 1 ns
2.4 V ≤ VDD ≤ 5.5 V 250 Note 1 ns
SCKp cycle time tKCY1
1.8 V ≤ VDD ≤ 5.5 V 500 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V tKCY1/2 − 12 ns
2.7 V ≤ VDD ≤ 5.5 V tKCY1/2 − 18 ns
2.4 V ≤ VDD ≤ 5.5 V tKCY1/2 − 38 ns
SCKp high-/low-level width tKH1,
tKL1
1.8 V ≤ VDD ≤ 5.5 V tKCY1/2 − 50 ns
4.0 V ≤ VDD ≤ 5.5 V 44 ns
2.7 V ≤ VDD ≤ 5.5 V 44 ns
2.4 V ≤ VDD ≤ 5.5 V 75 ns
SIp setup time (to SCKp↑)Note 2 tSIK1
1.8 V ≤ VDD ≤ 5.5 V 110 ns
SIp hold time (from SCKp↑)Note 3 tKSI1 19 ns
Delay time from SCKp↓ to
SOp outputNote 4 tKSO1 C = 30 pFNote 5 25 ns
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 789
Sep. 28, 2012
(4) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Normal operation
20 MHz < fMCK 8/fMCK ns 4.0 V ≤ VDD ≤ 5.5 V
fMCK ≤ 20 MHz 6/fMCK ns
16 MHz < fMCK 8/fMCK ns 2.7 V ≤ VDD < 4.0 V
fMCK ≤ 16 MHz 6/fMCK ns
16 MHz < fMCK 8/fMCK ns
1.8 V ≤ VDD < 2.7 V
fMCK ≤ 16 MHz 6/fMCK ns
SCKp cycle time tKCY2
SNOOZE mode 1 Mbps
SCKp high-/low-level width tKH2,
tKL2 1.8 V ≤ VDD ≤ 5.5 V tKCY2/2 ns
2.7 V ≤ VDD ≤ 5.5 V 1/fMCK+20 ns SIp setup time (to SCKp↑) Note 1 tSIK2
1.8 V ≤ VDD < 2.7 V 1/fMCK+30 ns
SIp hold time (from SCKp↑) Note 2 tKSI2 1/fMCK+31 ns
2.7 V ≤ VDD ≤ 5.5 V 2/fMCK+44 ns
2.4 V ≤ VDD < 2.7 V 2/fMCK+75 ns
Delay time from SCKp↓ to SOp
output Note 3 tKSO2 C = 30 pFNote 4
1.8 V ≤ VDD < 2.4 V 2/fMCK+110 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
Caution Select the normal input buffer for the SIp pin and the normal output mode for the SOp and SCKp pins
by using port input mode registers 0, 1 (PIM0, PIM1) and port output mode registers 0, 1 (POM0,
POM1).
Remarks 1. p: CSI number (p = 00, 01, 11, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0, 1, 3; “1, 3” is
for the R5F102 products.)
2. f
MCK: Serial array unit operation clock freque ncy
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number, n:
Channel number (n = 0, 1, 3; “1, 3” is for the R5F102 products.)
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 790
Sep. 28, 2012
CSI mode connection diagram (during communication at same potential)
SCKp
SOp
SCK
SI
SIp SO
RL78/G12 User’s device
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
SIp
SOp
t
KCY1, 2
t
KL1, 2
t
KH1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Input data
Output data
CSI mode serial transfer timing (during commun i cation at same potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
SIp
SOp
t
KCY1, 2
t
KH1, 2
t
KL1, 2
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
SCKp
Input data
Output data
Remarks 1. p: CSI number (p = 00, 01, 11, 20)
2. n: Channel number (0, 1, 3)
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 791
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(5) During communication at same potential (simplified I2C mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. Typ. MAX. Unit
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
400 kHz
SCLr clock frequency fSCL
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
300 kHz
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 ns
Hold time when SCLr = “L” tLOW
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 ns
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1150 ns
Hold time when SCLr = “H” tHIGH
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1550 ns
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
1/fMCK + 145 Note ns Data setup time (reception) tSU:DAT
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
1/fMCK + 230 Note ns
1.8 V ≤ VDD ≤ 5.5 V,
Cb = 100 pF, Rb = 3 kΩ
0 355 ns
Data hold time (transmission) tHD:DAT
1.8 V ≤ VDD < 2.7 V,
Cb = 100 pF, Rb = 5 kΩ
0 405 ns
Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the N-ch open drain output (VDD tolerance) mode for SDAr by using port output mode register
h (POMh).
Remarks 1. R
b [Ω]:Communication line (SDAr) pull-up resistance
C
b [F]: Communication line (SCLr, SDAr) load capac itance
2. r: IIC number (r = 00, 01, 11, 20), h: = POM number (h = 0, 1)
3. f
MCK: Serial array unit operation clock freque ncy
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number (m = 0, 1), n: Channel number (0, 1, 3)
4. Simplified I2C mode is supported by the R5F102 products.
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
Simplified I2C mode connection diagram (during communication at same pot en tial)
RL78/G12 User’s device
SDAr
SCLr
SDA
SCL
VDD
Rb
Simplified I2C mode serial transfer timing (during communication at same po t en tial)
SDAr
tLOW tHIGH
tHD : DAT
SCLr
tSU : DAT
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 793
Sep. 28, 2012
(6) Communication at different potential (1.8 V, 2.5 V, 3 V) (UA RT mode) (dedicated baud rate generator output)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Normal operation
fMCK/6 bps
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V Theoretical maximum
transfer rate
fCLK = fMCK = 24 MHz
4.0 Mbps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V Theoretical maximum
transfer rate
fCLK = fMCK = 24 MHz
4.0 Mbps
Reception
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V Theoretical maximum
transfer rate
fCLK = fMCK = 8 MHz
1.3 Mbps
Note 1 bps
4.0 V ≤ VDD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V Theoretical maximum
transfer rate
Cb = 50 pF, Rb = 1.4 kΩ, Vb =
2.7 V
2.8Note 2 Mbps
Note 3 bps
2.7 V ≤ VDD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V Theoretical maximum
transfer rate
Cb = 50 pF, Rb = 2.7 kΩ, Vb =
2.3 V
1.2Note 4 Mbps
Note 5 bps
Transmissio
n
1.8 V ≤ VDD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
Theoretical maximum
transfer rate
Cb = 50 pF, Rb = 5.5 kΩ, Vb =
1.6 V
0.43Note 6 Mbps
Transfer rate
Note 1
SNOOZE mode 4800 9600 bps
Notes 1. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expr ession for calculating the transfer rate when 4.0 V ≤ VDD ≤ 5.5 V and 2.7 V ≤ Vb ≤ 4.0 V
1
Maximum transfer rate = [bps]
{−Cb × Rb × ln (1 − 2.2
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.2
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* This value is the theoretical value of the relative differenc e between the transmission and reception sides.
2. This value as an example is calculated when the conditi ons described in the “Conditions” column are met.
Refer to Note 1 above to calculate the maximum transfer rate under cond itions of the customer.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 794
Sep. 28, 2012
3. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expression for calculating the transfer rate when 2.7 V ≤ VDD < 4.0 V and 2.3 V ≤ Vb ≤ 2.7 V
1
Maximum transfer rate =
{−Cb × Rb × ln (1 − 2.0
Vb)} × 3 [bps]
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 2.0
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of transferred bits
* T his value is the theor etical value of the relative difference between the transmission and reception s ides.
4. This value as an example is calculated when the conditi ons described in the “Conditions” column are met.
Refer to Note 3 above to calculate the maximum transfer rate under cond itions of the customer.
5. The smaller maximum transfer rate derived by using fMCK/6 or the following expression is the valid
maximum transfer rate.
Expr ession for calculating the transfer rate when 1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
1
Maximum transfer rate = [bps]
{−Cb × Rb × ln (1 − 1.5
Vb)} × 3
1
Transfer rate × 2 − {−Cb × Rb × ln (1 − 1.5
Vb)}
Baud rate error (theoretical value) = × 100 [%]
( 1
Transfer rate ) × Number of tr ansferred bits
* This value is the theoretical value of the relative differenc e between the transmission and reception sides.
6. T his value as an example is calculated when the conditions describ ed in the “Conditions” column are met.
Refer to Note 5 above to calculate the maximum transfer rate under cond itions of the customer.
Caution Select the TTL input buffer for the RxDq pin and the N-ch open drain output (VDD tolerance) mode for
the TxDq pin by using port input mode register g (PIMg) and port output mode register g (POMg). (In
20- or 24-pin products, redirect to P6 is not supported.)
Remarks 1. R
b [Ω]:Communication line (TxDq) pull-up re sistance,
Cb [F]: Communication line (TxDq) load capacitance,
Vb [V]: Communication line voltage
2. q: UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
3. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number, n: Channel number (mn = 00 to 03, 10, 11)
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
UART mode connection diagram (during communication at different potential)
RL78/G12 User’s device
TxDq
RxDq
Rx
Tx
V
b
R
b
UART mode bit w idth (during communication at different potential) (reference)
TxDq
RxDq
Baud rate error tolerance
High-/Low-bit width
1/Transfer rate
Baud rate error tolerance
High-bit width
Low-bit width
1/Transfer rate
Remarks 1. R
b [Ω]: Communication line (TxD0) pull-up re sistance, Vb [V]: Communication line voltage
2. q = UART number (q = 0 to 2), g: PIM, POM number (g = 0, 1)
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
(7) Communication at different potential (2.5 V, 3 V) (CSI00 mode) (CSI00 master mode (fMCK/2), SCK00...
internal clock output)
(TA = −40 to +85°C, 2.7 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
200Note 1 ns SCK00 cycle time tKCY1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
300 Note 1 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2 − 50 ns SCK00 high-level width tKH1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKCY1/2 − 120 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
tKCY1/2 − 7 ns SCK00 low-level width tKL1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
tKCY1/2 − 10 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
58 ns
SI00 setup time
(to SCK00↑) Note 2 tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
121 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
SI00 hold time
(from SCK00↑) Note 2 tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
60 ns
Delay time from SCK00↓ to
SO00 output Note 2 tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
130 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
23 ns
SI00 setup time
(to SCK00↓) Note 3 tSIK1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
33 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
SI00 hold time
(from SCK00↓) Note 3 tKSI1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 20 pF, Rb = 1.4 kΩ
10 ns
Delay time from SCK00↑ to
SO00 output Note 3 tKSO1
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 20 pF, Rb = 2.7 kΩ
10 ns
Notes 1. The value must also be 2/fCLK or more.
2. When DAP00 = 0 and CKP00 = 0, or DAP00 = 1 and CKP00 = 1
3. When DAP00 = 0 and CKP00 = 1, or DAP00 = 1 and CKP00 = 0.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Caution Select the TTL input buffer for the SI00 pin and the N-ch open drain output (VDD tolerance) mode for
the SO00 pin and SCK00 pin by using port input mode register 1 (PIM1) and port output mode
register 1 (POM1) (Redirect to P0 is not supported in 24-pin products).
Remarks 1. R
b [Ω]:Communication line (S CK00, SOp) pull-up resistance, Cb [F]: Communication line (SCK00, SO00)
load capacitance, Vb [V]: Communication line voltage
2. fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKS00 bit of serial mode register (SMR00).
CSI mode connection diagram (during communication at different potential)
SCK00
SO00
SCK
SI
SI00 SO
V
b
R
b
RL78/G12 User’s device
<Master> V
b
R
b
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI00 mode) (master mode, SCKp... internal
clock output) (1/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
300Note ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
500 Note ns
SCKp cycle time tKCY1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
1150 Note ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 −75 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 −170 ns
SCKp high-level width tKH1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −458 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
tKCY1/2 −12 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
tKCY1/2 −18 ns
SCKp low-level width tKL1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
tKCY1/2 −50 ns
Note The value must also be 4/fCLK or more.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different pote ntia l is not all owed i n CSI01 , CSI11.
Remarks 1. R
b [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Sep. 28, 2012
(8) Communication at different potential (1.8 V, 2.5 V, 3 V) (fMCK/4) (CSI mode) (master mode, SCKp... internal
clock output) (2/2)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 81 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 177 ns
SIp setup time
(to SCKp↑) Note 1 tSIK1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 479 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 19 ns
SIp hold time
(from SCKp↑) Note 1 tKSI1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 19 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 100 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 195 ns
Delay time from
SCKp↓ to
SOp output Note 1
tKSO1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 483 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 44 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 44 ns
SIp setup time
(to SCKp↓) Note 2 tSIK1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 110 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 19 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 19 ns
SIp hold time
(from SCKp↓) Note 2 tKSI1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 19 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ 25 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ 25 ns
Delay time from
SCKp↑ to
SOp output Note 2
tKSO1
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ 25 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.
2. When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp pin and SCKp pin by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different pote ntia l is not all owed i n CSI01 , CSI11.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 800
Sep. 28, 2012
Remarks 1. Rb [Ω]: Communication line (SCKp, SOp) pull-up resistance, Cb [F]: Communication line (SCKp, SOp)
load capacitance, Vb [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
CSI mode connection diagram (during communication at different potential)
V
b
R
b
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78/G12 User’s device
<Master>
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1)
tKCY2
tKL2 tKH2
tSIK2 tKSI2
tKSO2
SIp
SOp
SCKp
Input data
Output data
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 801
Sep. 28, 2012
CSI mode serial transfer timing (master mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY1
tKL1
tKH1
tSIK1 tKSI1
tKSO1
SIp
SOp
SCKp
Input data
Output data
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 802
Sep. 28, 2012
(9) Communication at different potential (1.8 V, 2.5 V, 3 V) (CSI mode) (slave mode, SCKp... external clock input)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Noromal operation
20 MHz < fMCK ≤ 24 MHz 12/fMCK ns
8 MHz < fMCK ≤ 20 MHz 10/fMCK ns
4 MHz < fMCK ≤ 8 MHz 8/fMCK ns
4.0 V ≤ V DD ≤ 5.5 V,
2.7 V ≤ Vb ≤ 4.0 V
fMCK ≤ 4 MHz 6/fMCK ns
20 MHz < fMCK ≤ 24 MHz 16/fMCK ns
16 MHz < fMCK ≤ 20 MHz 14/fMCK ns
8 MHz < fMCK ≤ 16 MHz 12/fMCK ns
4 MHz < fMCK ≤ 8 MHz 8/fMCK ns
2.7 V ≤ V DD < 4.0 V,
2.3 V ≤ Vb ≤ 2.7 V
fMCK ≤ 4 MHz
6/fMCK ns
20 MHz < fMCK ≤ 24 MHz 36/fMCK ns
16 MHz < fMCK ≤ 20 MHz 32/fMCK ns
8 MHz < fMCK ≤ 16 MHz 26/fMCK ns
4 MHz < fMCK ≤ 8 MHz
16/fMCK ns
1.8 V ≤ V DD < 3.3 V,
1.6 V ≤ Vb ≤ 2.0 V
fMCK ≤ 4 MHz
10/fMCK ns
SCKp cycle time tKCY2
SNOOZE mode 1 Mbps
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V
t
KCY2/2 − 12 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V
t
KCY2/2 − 18 ns
SCKp high-/low-level
width tKH2,
tKL2
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V
t
KCY2/2 − 50 ns
2.7 V ≤ VDD < 5.5 V
1/f
MCK
+ 20
ns
SIp setup time
(to SCKp↑) Note 1 tSIK2
1.8 V ≤ VDD < 3.3 V
1/f
MCK
+ 30
ns
SIp hold time
(from SCKp↑) Note 2 tKSI2
1/f
MCK
+ 31
ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 30 pF, Rb = 1.4 kΩ
2/fMCK + 120 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb ≤ 2.7 V,
Cb = 30 pF, Rb = 2.7 kΩ
2/fMCK + 214 ns
Delay time from
SCKp↓ to SOp output
Note 3
tKSO2
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 30 pF, Rb = 5.5 kΩ
2/fMCK + 573 ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp↓” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp↑” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
Caution Select the TTL input buffer for the SIp pin and the N-ch open drain output (VDD tolerance) mode for
the SOp and SCKp pins by using port input mode register 0, 1 (PIM0, PIM1) and port output mode
register 0, 1 (POM0, POM1) (Redirect to P0 is not supported in 24-pin products.). Communication at
different pote ntia l is not all owed i n CSI01 , CSI11.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
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Remarks 1. Rb [Ω]: Commun ication line (SOp) pu ll -up resistance, Cb [F]: Communication line (SOp) load capacitance,
V
b [V]: Communication line voltage
2. p: CSI number (p = 00, 20), m: Unit number (m = 0, 1), n: Channel number (n = 0)
3. fMCK: Serial array unit operation clock freq uency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn)
CSI mode connection diagram (during communication at different potential)
SCKp
SOp
SCK
SI
SIp SO
V
b
R
b
RL78/G12 User’s device
<Slave>
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1.)
tKCY1
tKL1 tKH1
tSIK1 tKSI1
tKSO1
SIp
SOp
SCKp
Input data
Output data
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 804
Sep. 28, 2012
CSI mode serial transfer timing (slave mode) (during communication at different potential)
(When DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.)
tKCY2
tKL2 tKH2
tSIK2 tKSI2
tKSO2
SIp
SOp
SCKp
Input data
Output data
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 805
Sep. 28, 2012
(10) Commun i cation at different potential (1.8 V, 2.5 V, 3 V) (simplified I2C mode)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. MAX. Unit
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ 400 kHz
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ 400 kHz
SCLr clock frequency fSCL
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
300 kHz
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ 1150 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ 1150 ns
Hold time when SCLr = “L” tLOW
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1550 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ 675 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ 600 ns
Hold time when SCLr = “H” tHIGH
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
610 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ 1/fMCKNote+190 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ 1/fMCKNote+190 ns
Data setup time (reception) tSU:DAT
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
1/fMCKNote+190 ns
4.0 V ≤ VDD ≤ 5.5 V, 2.7 V ≤ Vb ≤ 4.0 V,
Cb = 100 pF, Rb = 2.8 kΩ 0 355 ns
2.7 V ≤ VDD < 4.0 V, 2.3 V ≤ Vb < 2.7 V,
Cb = 100 pF, Rb = 2.7 kΩ 0 355 ns
Data hold time (transmission) tHD:DAT
1.8 V ≤ VDD < 3.3 V, 1.6 V ≤ Vb ≤ 2.0 V,
Cb = 100 pF, Rb = 5.5 kΩ
0 405 ns
Note Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".
Caution Select the TTL input buffer and the N-ch open drain output (VDD tolerance) mode for the SDAr pin
and the N-ch open drain output (VDD tolerance) mode for the SCLr pin by using port input mode
register 0, 1 (PIM0, PIM1) and port output mode register 0, 1 (POM0, POM1). Communication at
different pote ntial is not allowed in IIC01, IIC 11.
Remarks 1. R
b [Ω]: Communication line (SDAr, SCLr) pull-up resistance, Cb [F]: Communication line (SDAr, SCLr)
load capacitance, Vb [V]: Communicati on line voltage
2. r: IIC Number (r = 00, 20)
3. fMCK: Serial arra y unit operati on clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn).
m: Unit number (m = 0,1), n: Channe l number (n = 0))
4. Simplified I2C mode is supported by the R5F102 products.
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 806
Sep. 28, 2012
Simplified I2C mode connection diagram (during communication at different potential)
SDAr
SCLr
SDA
SCL
V
b
R
b
V
b
R
b
RL78/G12 User’s device
Simplified I2C mode serial transfer t iming (durin g communication at different potential)
SDAr
t
LOW
t
HIGH
t
HD : DAT
SCLr
t
SU : DAT
1/f
SCL
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 807
Sep. 28, 2012
28.5.2 Serial interface IICA
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Standard Mode Fast Mode Parameter Symbol Conditions
MIN. MAX. MIN. MAX.
Unit
Fast mode: fCLK ≥ 3.5 MHz 0 400 kHz SCLA0 clock frequency fSCL
Normal mode: fCLK ≥ 1 MHz 0 100 kHz
Setup time of restart conditionNote 1 tSU:STA 4.7 0.6
μ
s
Hold time tHD:STA 4.0 0.6
μ
s
Hold time when SCLA0 = “L” tLOW 4.7 1.3
μ
s
Hold time when SCLA0 = “H” tHIGH 4.0 0.6
μ
s
Data setup time (reception) tSU:DAT 250 100 ns
Data hold time (transmission)Note 2 tHD:DAT 0 3.45 0 0.9
μ
s
Setup time of stop condition tSU:STO 4.0 0.6
μ
s
Bus-free time tBUF 4.7 1.3
μ
s
Notes 1. The first clock pulse is generated after this period when the start/restart condition is detected.
2. The maximum value (MAX.) of tHD:DAT is during normal transfer and a wait state is inserted in the ACK
(acknowledge) timing.
Remark T he maximum value of Cb (co mmunication line capacit ance) and t he v alue of Rb (commu nication line pull-up
resistor) at that time in each mode are as follows.
Normal mode: Cb = 400 pF, Rb = 2.7 kΩ
Fast mode: Cb = 320 pF, Rb = 1.1 kΩ
IICA serial transfer timing
t
LOW
t
R
t
HIGH
t
F
t
BUF
t
HD:DAT
t
SU:DAT
t
HD:STA
t
SU:STA
t
HD:STA
t
SU:STO
SCLA0
SDAA0
Stop
condition
Start
condition
Restart
condition
Stop
condition
28.5.3 On-chip debug (UART)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Transfer rate 115.2 k 1 M bps
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 808
Sep. 28, 2012
28.6 Analog Characteristics
28.6.1 A/D converter characteristics
(1) When AVREF (+) = AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), (target
ANI pin : ANI2, ANI3)
(TA = −40 to +85°C, 1.8 V ≤VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = AVREFP, Reference v oltage (−) = A VREFM = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL 1.2 ±3.5 LSB
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
Conversion time tCONV
1.8 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS ±0.25 %FSR
Full-scale errorNotes 1, 2 EFS ±0.25 %FSR
Integral linearity errorNote 1 ILE ±2.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD
±1.5 LSB
Reference voltage (+) AVREFP 1.8 VDD V
VAIN 0 AVREFP V Analog input voltage
VBGR Internal reference voltage is selected
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
1.38 1.45 1.50 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale va lue.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 809
Sep. 28, 2012
(2) When AVREF (+)= AVREFP/ANI0 (ADREFP1 = 0, ADREFP0 = 1), AVREF (−) = AVREFM/ANI1 (ADREFM = 1), (target
ANI pin : ANI16 to ANI22)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference v oltage (+) = AVREFP, Reference v oltage (−) = AVREFM =0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL 1.2 ±5.0 LSB
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
Conversion time tCONV
1.8 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS ±0.35 %FSR
Full-scale errorNotes 1, 2 EFS ±0.35 %FSR
Integral linearity errorNote 1 ILE ±3.5 LSB
Differential linearity error Note 1 DLE
10-bit resolution
AVREFP = VDD
±2.0 LSB
Reference voltage (+) AVREFP 1.8 VDD V
VAIN 0 AVREFP
and VDD V
Analog input voltage
VBGR Internal reference voltage is selected
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
1.38 1.45 1.5 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale va lue.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 810
Sep. 28, 2012
(3) When AVREF (+) = VDD (ADREFP1 = 0, ADREFP0 = 0), AVREF (−) = VSS (ADREFM = 0), (target ANI pin : ANI0 to
ANI3, ANI16 to ANI22)
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VDD, Reference voltage (−) = VSS)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 10 bit
Overall errorNote 1 AINL 1.2 ±7.0 LSB
3.6 V ≤ VDD ≤ 5.5 V 2.125 39
μ
s
2.7 V ≤ VDD ≤ 5.5 V 3.1875 39
μ
s
Conversion time tCONV
1.8 V ≤ VDD ≤ 5.5 V 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS ±0.60 %FSR
Full-scale errorNotes 1, 2 EFS ±0.60 %FSR
Integral linearity errorNote 1 ILE ±4.0 LSB
Differential linearity error Note 1 DLE
10-bit resolution
±2.0 LSB
VAIN 0 VDD V Analog input voltage
VBGR Internal reference voltage is selected
2.4 V ≤ VDD ≤ 5.5 V
HS (high-speed main) mode
1.38 1.45 1.50 V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale va lue.
(4) When AVREF (+) = Internal referen ce voltage (ADREFP1 = 1, ADREFP0 = 0), AVREF (−) = AVREFM (ADREFM = 1),
(target ANI pin : ANI0, ANI2, ANI3, ANI16 to ANI22)
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, Reference voltage (+) = VBGR, Reference voltage (−) = AVREFM = 0 V,
HS (high-speed main) mode)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Resolution RES 8 bit
Conversion time tCONV 17 39
μ
s
Zero-scale errorNotes 1, 2 EZS ±0.60 %FSR
Integral linearity errorNote 1 ILE ±2.0 LSB
Differential linearity error Note 1 DLE
8-bit resolution
AVREFM = 0 V, 2.4 V ≤ VDD ≤ 5.5 V
±1.0 LSB
Reference voltage (+) VBGR 1.38 1.45 1.5 V
Analog input voltage VAIN 0 VBGR V
Notes 1. Excludes quantization error (±1/2 LSB).
2. This value is indicated as a ratio (%FSR) to the full-scale va lue.
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 811
Sep. 28, 2012
28.6.2 Temperature sensor/in tern al reference voltage characteristics
(TA = −40 to +85°C, 2.4 V ≤ VDD ≤ 5.5 V, VSS = 0 V, HS (high-speed main) mode
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Temperature sensor output voltage VTMPS25 Setting ADS register = 80H,
TA = +25°C 1.05 V
Internal reference voltage VCONST Setting ADS register = 81H 1.38 1.45 1.5 V
Temperature coefficient FVTMPS Temperature sensor that
depends on the temperature −3.6 mV/°C
Operation stabilization wait time tAMP 5
μ
s
28.6.3 POR circuit characteristics
(TA = −40 to +85°C, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VPOR Power supply rise time 1.48 1.51 1.54 V Detection voltage
VPDR Power supply fall time 1.47 1.50 1.53 V
Minimum pulse width TPW 300
μ
s
Detection delay time 350
μ
s
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 812
Sep. 28, 2012
28.6.4 LVD circuit characteristics
LVD Detection Voltage of Reset Mode and In terrupt Mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Power supply rise time 3.98 4.06 4.14 V VLVD0
Power supply fall time 3.90 3.98 4.06 V
Power supply rise time 3.68 3.75 3.82 V VLVD1
Power supply fall time 3.60 3.67 3.74 V
Power supply rise time 3.07 3.13 3.19 V VLVD2
Power supply fall time 3.00 3.06 3.12 V
Power supply rise time 2.96 3.02 3.08 V VLVD3
Power supply fall time 2.90 2.96 3.02 V
Power supply rise time 2.86 2.92 2.97 V VLVD4
Power supply fall time 2.80 2.86 2.91 V
Power supply rise time 2.76 2.81 2.87 V VLVD5
Power supply fall time 2.70 2.75 2.81 V
Power supply rise time 2.66 2.71 2.76 V VLVD6
Power supply fall time 2.60 2.65 2.70 V
Power supply rise time 2.56 2.61 2.66 V VLVD7
Power supply fall time 2.50 2.55 2.60 V
Power supply rise time 2.45 2.50 2.55 V VLVD8
Power supply fall time 2.40 2.45 2.50 V
Power supply rise time 2.05 2.09 2.13 V VLVD9
Power supply fall time 2.00 2.04 2.08 V
Power supply rise time 1.94 1.98 2.02 V VLVD10
Power supply fall time 1.90 1.94 1.98 V
Power supply rise time 1.84 1.88 1.91 V
Detection supply voltage
VLVD11
Power supply fall time 1.80 1.84 1.87 V
Minimum pulse width tLW 300
μ
s
Detection delay time 300
μ
s
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 813
Sep. 28, 2012
LVD detection voltage of interrupt & rese t mode
(TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
VLVD11 VPOC2, VPOC1, VPOC0 = 0, 0, 1, falling reset voltage: 1.8 V 1.80 1.84 1.87 V
Rising reset release voltage 1.94 1.98 2.02 V VLVD10 LVIS1, LVIS0 = 1, 0
(+0.1 V) Falling interrupt voltage 1.90 1.94 1.98 V
Rising reset release voltage 2.05 2.09 2.13 V VLVD9 LVIS1, LVIS0 = 0, 1
(+0.2 V) Falling interrupt voltage 2.00 2.04 2.08 V
Rising reset release voltage 3.07 3.13 3.19 V VLVD2
LVIS1, LVIS0 = 0, 0
(+1.2 V) Falling interrupt voltage 3.00 3.06 3.12 V
VLVD8 VPOC2, VPOC1, VPOC0 = 0, 1, 0, falling reset voltage: 2.4 V 2.40 2.45 2.50 V
Rising reset release voltage 2.56 2.61 2.66 V VLVD7 LVIS1, LVIS0 = 1, 0
(+0.1 V) Falling interrupt voltage 2.50 2.55 2.60 V
Rising reset release voltage 2.66 2.71 2.76 V VLVD6 LVIS1, LVIS0 = 0, 1
(+0.2 V) Falling interrupt voltage 2.60 2.65 2.70 V
Rising reset release voltage 3.68 3.75 3.82 V VLVD1
LVIS1, LVIS0 = 0, 0
(+1.2 V) Falling interrupt voltage 3.60 3.67 3.74 V
VLVD5 VPOC2, VPOC1, VPOC1 = 0, 1, 1, falling reset voltage: 2.7 V 2.70 2.75 2.81 V
Rising reset release voltage 2.86 2.92 2.97 V VLVD4 LVIS1, LVIS0 = 1, 0
(+0.1 V) Falling interrupt voltage 2.80 2.86 2.91 V
Rising reset release voltage 2.96 3.02 3.08 V VLVD3 LVIS1, LVIS0 = 0, 1
(+0.2 V) Falling interrupt voltage 2.90 2.96 3.02 V
Rising reset release voltage 3.98 4.06 4.14 V
LVD detection
voltage
VLVD0
LVIS1, LVIS0 = 0, 0
(+1.2 V) Falling interrupt voltage 3.90 3.98 4.06 V
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 814
Sep. 28, 2012
28.7 Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics
(TA = −40 to +85°C)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
Data retention supply voltage VDDDR 1.47Note 5.5 V
Note The value depends on the POR detection voltage. When the voltage drops, the data is retained before a POR
reset is affected, but data is not retained when a POR reset is affected.
V
DD
V
DDDR
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
Operation mode
28.8 Flash Memory Programming Characteristics
(TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
System clock frequency fCLK 1.8 V ≤ VDD ≤ 5.5 V 1 24 MHz
Code flash memory rewritable times
Notes 1.2.3
Retained for 20 years TA = 85°C Note 3 1,000
Retained for 1 year TA = 25°C Note 3 1,000,000
Retained for 5 years TA = 85°C Note 3 100,000
Data flash memory rewritable times
Notes 1.2.3
Cerwr
Retained for 20 years TA = 85°C Note 3 10,000
Times
Notes 1. 1 erase + 1 write after the erase is regarded as 1 rewrite.
The retaining years are until next rewrite after the rewrite.
2. When using flash memory programmer and Renesas Electronics self progr am library.
3. These are the characteristics of the flash memory and the results obta ined from reliab ilit y testing b y Renesas
Electronics Corporation.
Caution This specifications sh ow target values, which may change after device evaluation.
Remark When updating data multiple times, use the flash memory as one for updating data.
<R>
<R>
<R>
RL78/G12 CHAPTER 28 ELECTRICAL SPECIFICATIONS
R01UH0200EJ0110 Rev.1.10 815
Sep. 28, 2012
28.9 Timing Specs for Flash Memory Programming Switching Modes
Parameter Symbol Conditions MIN. TYP. MAX. Unit
How long from when an external reset ends until
the initial communication settings are specified tSUINIT POR and LVD reset are
released before external
reset release
100 ms
How long from when the TOOL0 pin is placed at
the low level until an external reset ends tsu 10
μ
s
How long the TOOL0 pin must be kept at the low
level after a reset ends
(except soft processing time)
tHD 1 ms
RESET
TOOL0
<1> <2> <3>
tSUINIT
tHD+
software
processing
time
tSU
<4>
00H reception
(T OOLRxD , T OOLTxD mode)
<1> The low level is input to the TOOL0 pin.
<2> The external reset ends (POR and LVD reset must end before the pin reset ends.).
<3> The TOOL0 pin is set to the high level.
<4> Setting of the flash memory programming mode by UART reception and complete the baud
rate setting.
Remark t
SUINIT: The segment shows that it is necessary to finish specifying the initial communication settings within
100 ms from when the resets end.
t
SU: How long from when the TOOL0 pin is place d at the low level until an external reset ends.
tHD: How long to keep the TOOL0 pin at the low level from when the external and internal resets end.
(except soft processing time)
<R>
<R>
<R>
<R>
RL78/G12 CHAPTER 29 PACKAGE DRAWINGS
R01UH0200EJ0110 Rev.1.10 816
Sep. 28, 2012
CHAPTER 29 PACKAGE DRA WINGS
29.1 20-pin products
R5F1026AASP, R5F10269ASP, R5F10268ASP, R5F10267ASP, R5F10266ASP
R5F1036AASP, R5F10369ASP, R5F10368ASP, R5F10367ASP, R5F10366ASP
R5F1026ADSP, R5F10269DSP, R5F10268DSP, R5F10267DSP, R5F10266DSP
R5F1036ADSP, R5F10369DSP, R5F10368DSP, R5F10367DSP, R5F10366DSP
2012 Renesas Electronics Corporation. All rights reserved.
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LSSOP20-4.4x6.5-0.65 PLSP0020JB-A P20MA-65-NAA-1 0.1
20
110
detail of lead end
ITEM DIMENSIONS
D
E
e
A1
A
A2
L
c
y
bp
0.10
0.10
0 to 10
(UNIT:mm)
AA2
A1 e
y
HE
c
6.50
4.40
0.20
0.10
6.40
0.10
0.10
1.45 MAX.
1.15
0.65 0.12
0.10
0.05
0.22
0.05
0.02
0.15
0.50 0.20
11
bp
HE
E
D
L
3
2
1
NOTE
1.Dimensions “ 1” and “ 2”
2.Dimension “ ” does not include tr
RL78/G12 CHAPTER 29 PACKAGE DRAWINGS
R01UH0200EJ0110 Rev.1.10 817
Sep. 28, 2012
29.2 24-pin products
R5F1027AANA, R5F10279ANA, R5F10278ANA, R5F10277ANA
R5F1037AANA, R5F10379ANA, R5F10378ANA, R5F10377ANA
R5F1027ADNA, R5F10279DNA, R5F10278DNA, R5F10277DNA
R5F1037ADNA, R5F10379DNA, R5F10378DNA, R5F10377DNA
2012 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
18
12
13
6
7
1
24
A
S
B
A
D
E
A
e
Lp
x
y
4.00 0.05
0.50
0.05
0.05
4.00 0.05
0.75 0.05
0.40 0.10
S
D2
E2
(UNIT:mm)
ITEM DIMENSIONS
19
DETAIL OF A PART
EXPOSED DIE PAD
ITEM D2 E2
A
MIN NOM MAX
2.45 2.50
EXPOSED
DIE PAD
VARIATIONS 2.55
MIN NOM MAX
2.452.50 2.55
b0.25 0.05
0.07
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-HWQFN24-4x4-0.50 PWQN0024KE-A P24K8-50-CAB-1 0.04
RL78/G12 CHAPTER 29 PACKAGE DRAWINGS
R01UH0200EJ0110 Rev.1.10 818
Sep. 28, 2012
29.3 30-pin products
R5F102AAASP, R5F102A9ASP, R5F102A8ASP, R5F102A7ASP
R5F103AAASP, R5F103A9ASP, R5F103A8ASP, R5F103A7ASP
R5F102AADSP, R5F102A9D SP, R5F 102A8DSP, R5F102A7DSP
R5F103AADSP, R5F103A9D SP, R5F 103A8DSP, R5F103A7DSP
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-LSSOP30-0300-0.65 PLSP0030JB-B S30MC-65-5A4-3 0.18
S
S
H
J
T
I
G
D
E
F
CB
K
PL
U
N
ITEM
B
C
I
L
M
N
A
K
D
E
F
G
H
J
P
30 16
115
A
detail of lead end
M
M
T
MILLIMETERS
0.65 (T.P.)
0.45 MAX.
0.13
0.5
6.1 0.2
0.10
9.85 0.15
0.17 0.03
0.1 0.05
0.24
1.3 0.1
8.1 0.2
1.2
0.08
0.07
1.0 0.2
35
3
0.25
0.6 0.15U
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
2012 Renesas Electronics Corporation. All rights reserved.
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 819
Sep. 28, 2012
APPENDIX A REVISION HISTORY
A.1 Major Revisions in This Edition (1/4)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Page Description Classification
Deletion of overbars for SCK(serial clock signal) (c)
Titles of register description headlined (c)
Though out
Change from products with data flash memory to R5F102 products (c)
CHAPTER 1 OUTLINE
1 Addition of 1.1 Differences between R5F102 and R5F103 (b)
3 Partial modification of description in 1.2 Features (c)
5 Change from 1.3 Ordering Information to 1.3 List of Part Numbers (c)
5 Modification of Figure 1-1. Part Number, Memory size, and Package of RL78/G12 (c)
5 Addition of Fields of Application to 1.3 List of Part Numbers (c)
9 Partial modification of 1.5 Pin Identification (c)
13 Modification of description and Notes 1 to 3 and addition of Caution in 1.7 Outline of Functions (c)
CHAPTER 2 PIN FUNCTIONS
20 Modification of error in 2.2.2 Description of Functions (a)
CHAPTER 3 CPU ARCHITECTURE
25, 26 Modification of Note1 and Caution1 and addition of Cautions 2 and 3 in Figure 3-1. Memory Map (c)
27 to 31 Modification of Caution in Figure 3-2 to 3-6. Memory Maps (c)
33 Partial modification of description in 3.1.1 Internal program memory space (c)
38 Addition and modification of Cautions 1 and 2 in Processor mode control register (PMC) (c)
38, 39 Modification of description and Cautions 1 and 2 a nd addition of Caution 3 in 3.1.3 Internal data
memory space (c)
41 Modification of Note 1 and Caution 1 and addition of Cautions 2 and 3 in Figure 3-8.
Correspondence Between Data Memory and Addressing (c)
42 to 46 Modification of Caution in Figure 3-9 to Figure 3-13. Correspondence Between Data Memory and
Addressing (c)
47, 48 Modification of description and Cautions 2 and 3 a nd addition of Caution 4 in 3.2.1 Control
registers (c)
50 Modification of Cautions 1 and 2 and addition of Caution 3 in 3.2.2 General-purpose registers (c)
51 Modification of description in 3.2.3 ES and CS registers (c)
52 Modification of description in 3.2.4 Special function registers (SFRs) (c)
57 Modification of description in 3.2.5 Extended special function registers (2nd SFRs: 2nd
Special Function Registers) (c)
57 Modification of Caution in 3.2.5 Extended special function regi sters (2nd SFRs: 2nd Special
Function Registers) (c)
59 Modification of error in Table 3-7. Extended SFR (2nd SFR) List (2/5) (a)
59 Addition of Note in Table 3-7. Extended SFR (2nd SFR) List (c)
63 to 76 Modification of description in Figure 3-21 to Figure 3-48 (c)
66 Modification of description of [Operand format] in 3.4.3 Direct addressing (c)
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 820
Sep. 28, 2012
(2/4)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Page Description Classification
68 Modification of description of [Operand format] in 3.4.5 SFR addressing (c)
70 Modification of description of [Function] in 3.4.7 Based addressing (c)
74 Modification of description of [Function] and [Format] in 3.4.9 Stack addressing (c)
CHAPTER 4 PORT FUNCTION
95 Modification of error in Table 4-7. Settings of Registers When Using Port 6 (20-, 24-pin Products) (a)
128 Modification of error in Figure 4-34. Format of Port Registers (a)
CHAPTER 5 CLOCK GENERATOR
151 Modification of Caution 5 and deletion of Cautions 6 and 7 in Figure 5-2. Format of Clock
Operation Mode Control register (CMC) (c)
160 Modification of Cautions 1 to 3 in 5.3.8 High-speed on-chip oscillator frequency selection
register (HOCODIV) (c)
166 Modification of Note 3 in Figure 5-13. Clock Generator Operation When Power Supply Voltage Is
Turned On (When voltage detector (LVD) is used) (b)
167 Modification of [Option byte setting] in 5.6.1 Example of setting high-speed on-chip oscillator (c)
174 Addition of 5.7 Resonator and Oscillator Constants (b)
CHAPTER 6 TIMER ARRAY UNIT
188 Modification of description in (2) Timer data register 0n (TDR0n) (a)
192 Modification of error in Figure 6-8. Format of Timer Clock Select Register 0 (TPS0) (a)
197 Modification of description in Figure 6-9. Format of Timer Mode Register 0n (TMR0n) (4/4) (c)
CHAPTER 10 A/D CONVERTER
303 Modification of Caution 1 in Figure 10-2. Format of Peripheral Enable Register 0 (PER0) (c)
304 Modification of Caution 1 and addition of Caution 2 in 10.3.2 A/D converter mode register 0
(ADM0) (c)
305 Modification of description in Table 10-1. Settings of ADCS and ADCE Bits (c)
308 Addition of Note 3 and modification of Caution 1 in Tables 10-3 A/D Conversion Time Selection
(1/4) (c)
309 Addition of Note 6 and modification of Caution 1 and LV1 in Tables 10-3 A/D Conversion Time
Selection (2/4) (c)
310 Addition of Note 4 and modification of Caution 1 in Tables 10-3 A/D Conversion Time Selection
(3/4) (c)
311 Addition of Note 7 and modification of Caution 1 and LV1 in Tables 10-3 A/D Conversion Time
Selection (4/4) (c)
312 Modification of Caution 1 in 10.3.3 A/D converter mode register 1 (ADM1) (c)
313 Modification of Caution 1 in 10.3.4 A/D converter mode register 2 (ADM2) (c)
318 Modification of Caution 5 in Figure 10-11. Format of Analog Input Channel Specification Register
(ADS) (c)
330 Modification of error in Figure 10-22. Example of Software Trigger Mode (Scan Mode, Sequential
Conversion Mode) Operation Timing (a)
331 Modification of error in Figure 10-23. Example of Software Trigger Mode (Scan Mode, One-Shot
Conversion Mode) Operation Timing (a)
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 821
Sep. 28, 2012
(3/4)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Page Description Classification
334 Modification of error in Figure 10-26. Example of Hardware Trigger No-Wait Mode (Scan Mode,
Sequential Conversion Mode) Operation Timing (a)
335 Modification of error in Figure 10-27. Example of Hardware Trigger No-Wait Mode (Scan Mode,
One-Shot Conversion Mode) Operation Timing (a)
338 Modification of error in Figure 10-30. Example of Hardware Trigger Wait Mode (Scan Mode,
Sequential Conversion Mode) Operation Timing(a)
339 Modification of error in Figure 10-31. Example of Hard ware Trigger Wait Mode (Scan Mode, One-
Shot Conversion Mode) Operation Timing(a)
344 Change title of chapter 10.7.4 to Setup when temperature sensor output/internal reference
voltage output is selected (example for software trigger mode and one-shot conversion
mode)
(c)
344 Change title of Figure 10-35 to Setup when temperature sensor output/internal reference
voltage output is selected. (c)
CHAPTER 11 SERIAL ARRAY UNIT
367 Modification of error in Figure 11-7. Format of Serial Clock Select Register m (SPSm) (a)
CHAPTER 17 STANDBY FUNCTION
660 Modification of Figure 17-4. HALT Mode Release by Reset (c)
660 Modification of Note in Figure 17-4. HALT Mode Release by Reset (b)
661 Modification of caution1 in (1) STOP mode setting and operating statuses (c)
662 Modification of error in Table 17-2. Operating Statuses in STOP Mode (c)
663 Deletion of Caution 1 in Table 17-2. Operating Statuses in STOP Mode (c)
665 Modification of Figure 17-6. STOP Mode Release by Reset (c)
665 Modification of Note in Figure 17-6. STOP Mode Release by Reset (b)
666 Modification of description in (1) SNOOZE mode setting and operating statuses (c)
CHAPTER 18 RESET FUNCTION
668 Modification of Caution 3 in CHAPTER 18 RESET FUNCTION (c)
670 Modification of description in Figure 18-2. Timing of Reset by RESET Input (b)
670 Modification of description in Figure 18-3. Timing of Reset Due to Execution of Illegal Instruction
or Watchdog Timer Overflow (b)
671 Modification of description and deletion of Note in Table 18-1. Operation Statuses During Reset
Period (c)
672 Modification of Note 2 in Table 18-2. Hardware Statuses After Reset Acknowledgment (1/3) (b)
675 Modification of Caution 2 in 18.1.1 Reset Control Flag Register (RESF) (c)
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 822
Sep. 28, 2012
(4/4)
Remark “Classification” in the above table classifies revisions as follows.
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Page Description Classification
CHAPTER 19 POWER-ON-RESET CIRCUIT
679 Modification of Note 3 in Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-
reset Circuit and Voltage Detector (1/3) (c)
680 Modification of Note 4 in Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-
reset Circuit and Voltage Detector (2/3) (c)
681 Addition of Figure 19-2. Timing of Generation of Internal Reset Signal by Power-on-reset Circuit
and Voltage Detector (3/3) (c)
CHAPTER 21 SAFETY FUNCTIONS
701 Modification of 21.1 (2) RAM parity error detection function (a)
705 Modification of Caution in 21.3.2 RAM parity error detection function (c)
CHAPTER 23 OPTION BYTE
716 Modification of description in 23.1 Functions of Option B ytes(c)
718 Modification of Caution in Figure 23-1. Format of User Option Byte (000C0H) (c)
720 Addition of Caution in Figure 23-2. Format of User Option Byte (000C1H)(2/2) (c)
721 Addition of Caution in Figure 23-3. Format of User Option Byte (000C2H) (c)
CHAPTER 24 FLASH MEMORY
729 Modification of description in 24.3.1 P40/TOOL0 pin (c)
732 Modification of description and addition of Cautions 1 and 2 in 24.4.1 Data flash overview (c)
735 Modification of description and Remark in Figure 24-8. Setting of Flash Memory Programming
Mode (c)
739 Modification of explanation of 24.6 Security Settings (c)
740 Deletion of (2) Self programming in T able 24-12. Security Setting in Each Programming Mode (c)
741 Modification of Cautions 1 to 4 in 24.7 Flash Memory Programming by Self-Programming (c)
743 Modification of description in 24.7.1 Flash shield window function (c)
743 Modification of description in Table 24-14. Setting and changing of the flash shield window function
and relations with commands (c)
CHAPTER 28 ELECTRICAL SPECIFICATIONS
773 Addition of Note 4 in 28.1 Absolute Maximum Ratings (c)
775 Addition of Note 3 in 28.3.1 Pin characteristics (1/4) (c)
776 Addition of Note 3 in 28.3.1 Pin characteristics (2/4) (c)
777 Addition of Notes 1 and 2 in 28.3.1 Pin characteristics (3/4) (c)
778 Modification of Note in 28.3.1 Pin characteristics (4/4) (c)
781 Modification of Notes 2 and 4 in (2) 30-pin products (c)
811 Change title of chapter 28.6.2 to Temperature sensor/internal reference voltage (c)
811 Change from reference output voltage to internal reference voltage (c)
814 Modification of description in 28.8 Flash Memory Programming Characteristics (b)
815 Modification of description in 28.9 Timing Specs for Flash Memory Programming Switching
Modes (c)
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 823
Sep. 28, 2012
A.2 Revision History of Preceding E ditions
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/11)
Edition Description Chapter
Addition of products of industrial application
Renamed interval timer (unit) to 12-bit interval timer
Addition of pin name of the peripheral I/O redirection function
Modification of reset processing time
Deletion of LIN communication function
Renamed VLVI, VLVIH, VLVIL to VLVD, VLVDH, VLVDL (LVD detection voltage)
Renamed RAMTOP to RPE, renamed ITIF, ITMK, ITKAPR0, ITKAPR1 to TMKAIF,
TMKAMK, TMKAPR0, TMKAPR1 (interrupt source, flag)
Though out
Addition of description to 1.1 Features
Modification of description in 1.2 Ordering Information
Addition of Figure 1-1. Part Number, Memory Size, and Package of RL78/G12
Addition and Modification of description in 1.6 Outline of Functions
CHAPTER 1 OUTLINE
Modification of description in 2.1 Port Function
Modification of description in 2.2 Functions other than port pins (Deletion of
description of port function)
Modification of description in 2.3 Pin I/O Circuits and Recommended Connection of
Unused Pins
CHAPTER 2 PIN
FUNCTIONS
Addition of remark to Table 3-1. Correspondence Between Address Values and
Block
Numbers in Flash Memory
Addition of product in Table 3-2. Internal ROM Capacity
Addition of INTFL to Table 3-3. Vector Table (20-, 24-pin products)
Modification of description in 3.1.2 Mirror area
Addition of description to Caution in Table 3-5. Internal RAM Capacity
Modification of Figure 3-23. Outline of Table Indirect Addressing
CHAPTER 3 CPU
ARCHITECTURE
Addition of setting of registers when using port xx to Table 4-2 to 4-4, 4-6 to 4-12, 4-14
to 4-20
Modification of block diagrams for Pxxx
Addition of description to (3) Port 2
Addition of description to (4) Port 4
Addition of Note to (6) Port 12
Addition of description to (3) Port 2
Addition of description to (2) Port register (Pxx)
Addition of description to (3) Pull-up resistor option registers (PUxx)
Modification of description in Figure 4-37. Format of Port Output Mode Register
Addition of Caution to Figure 4-38. Format of Port Mode Control Register
Addition of description to (8) Peripheral I/O redirection register (PIOR)
Rev.1.00
Addition of description to 4.4.1 Writing to I/O port, and 4.4.3 Operations on I/O
port
CHAPTER 4 PORT
FUNCTIONS
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 824
Sep. 28, 2012
(2/11)
Edition Description Chapter
Addition of description to 4.4.4 Connecting to external device with different
potential (1.8 V, 2.5 V, 3 V)
Addition of description to 4.5 Settings of Port Mode Register, and Output Latch
When Using Alternate Function
Addition of 4.6.2 Notes on specifying the pin settings
CHAPTER 4 PORT
FUNCTIONS
Addition of description to 5.1 (1) <2> High-speed on-chip oscillator
Addition of Caution to Figure 5-2. Format of Clock Operation Mode Control
Register (CMC)
Modification of Figure 5-1. Block Diagram of Clock Generator
Modification of description in Table 5-2. Condition Before Stopping Clock
Oscillation and Flag Setting
Deletion of Note to Figure 5-7. Format of Peripheral Enable Register 0 (PER0)
(1/2)
Addition of description to (7) Operation speed mode control register ( OSMC)
Modification of Caution 3 to Figure 5-9 Form at of High-Speed On-Chip Oscillator
Frequency Sel ec ti on Re gister (HOCODIV)
Modification of description in Figure 5- 13. Clo ck Gene rato r Ope rati on When Po wer
Supply Vo lta ge Is T u rned On (When v olt age d ete ct or (L V D) i s us ed )
Addition of description to 5.6.2 Example of setting X1 oscillation clock
Addition of description to Figure 5-14. CPU Clock Status Transition Diagram
Addition of description to (2) CPU operating with high-speed system clock (C)
after reset release (A)
Modification and deletion of description in Table 5-4. Changing CPU Clock
Modification of description in Table 5-5. Maximum Number of Clocks Required for
fIH ↔ fMX, and Table 5-6. Conditions Before the Clock Oscillation Is Stopped and
Flag Settings
CHAPTER 5 CLOCK
GENERATOR
Addition of Figure to (7) Delay counter
Addition of description to Figure 6-2. Entire Configuration of Timer Array Unit (30-
pin products)
Addition of Figure 6-3. Internal Block Diagram of Channel of Timer Array Unit
Addition of description to (1) Timer/counter register 0n (TCR0n)
Addition of description to (2) Timer data register 0n (TDR0n)
Modification of description and addition of caution to Figure 6-8. Format of Timer
Clock Select register 0 (TPS0)
Modification of description in Table 6-4. Interval Times Available for Operation
Clock CKS02 or CKS03, and addition of Caution in (3) Timer mode register 0n
(TMR0n)
Modification of Figure 6-9. Format of Ti mer Mode Register 0n (TMR0n)
Addition of description to (5) Timer channel enable status register 0 (TE0)
Modification of Figure 6-12. Format of T imer Channel Start register 0 (TS0)
Addition of description to Figure 6-13. Format of Timer Channel Stop register 0
(TT0)
Addition of description to (8) Timer input select register 0 (TIS0)
Rev.1.00
Modification of description to Figure 6-15. Form at of Timer Output Enable register
0 (TOE0)
CHAPTER 6 TIMER
ARRAY UNIT
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 825
Sep. 28, 2012
(3/11)
Edition Description Chapter
Addition of description to (14) Port mode registers 0, 1, 3, or 4 (PM0, PM1, PM3, or
PM4)
Addition of description to 6.4.1 Basic Rules of Simultaneous Channel Operation
Function
Addition of description to 6.5.1 Count clock (fTCLK)
Modification of description to Table 6-6. Operations from Count Operation
Enabled State to Timer count Register 0n (TCR0n) Count Start
Addition of title to 6.5.3 Operation of counter
Modification of Figure 6-27. Operation Timing (In Capture & One-count Mode:
High-level Width Measurement)
Addition of description to 6.6.2 TO0n Pin Output Setting
Modification of description to Figure 6-39, 43, 51, 55, 59, 64, 69, 74 Example of Set
Contents of Registers
Modification of Figure 6-41, 45, 49, 53, 61
Addition of 6.9 Cautions When Using Timer Array Unit
CHAPTER 6 TIMER
ARRAY UNIT
Addition of description to (2) Operation speed mode control register ( OSMC)
Addition of Caution to Figure 7-4. Format of Interval Timer Control Register
(ITMC)
Modification of Figure 7-5. 12-Bit Interval Timer Operation Timing
CHAPTER 7 12-BIT
INTERVAL TIMER
Modification of Figure 8-1. Block Diagram of Clock Output/Buzzer Output
Controller
Modification of Figure 8-2. Format of Cloc k Output Select Register n (CKSn)
Addition of description to (2) Port mode register 1, 3 (PM1, PM3)
Addition of Caution to 8.4.1 Operation as output pin
CHAPTER 8 CLOCK
OUTPUT/BUZZER
OUTPUT CONTROLLER
Modification of description to 9.1 Functions of Watchdog Timer, 9.4.4 Setting
watchdog timer interval interrup t CHAPTER 9
WATCHDOG TIMER
Modification of Figure 10-1. Block Diagram of A/D Converter
Modification of description to (3) A/D voltage comparator
Addition of Caution to Figure 10-3. Format of A/D Converter Mode Register 0
(ADM0)
Modification of description to Figure 10-4. Timing Chart When A/D Voltage
Comparator Is Used
Addition of description to Table 10-3. A/D Conversion Time Selection
Modification of Caution to Figure 10-6. Format of A/D Converter Mode Register 1
(ADM1)
Addition of description to Figure 10-7. Format o f A/D Converter Mode Register 2
(ADM2)
Addition of description to Figure 10-11. Format o f Analog Input Channel
Specification Register (ADS)
Rev.1.00
Addition of description and Caution to (10) A/D test register (ADTES), (11) A/D port
configuration register (ADPC), (12) Port mode control registers 0, 1, 4, 12, and
14 (PMC0, PMC1, PMC4, PMC12, and PMC14), and (13) Port mode registers 0, 1,
2, 4, 12, and 14 (PM0, PM1, PM2, PM4, PM12 and PM14)
CHAPTER 10
A/D CONVERTER
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 826
Sep. 28, 2012
(4/11)
Edition Description Chapter
Addition of Note to 10.4 A/D Converter Conversion Operations
Modification of Figure 10-32. Setting up Software Trigger Mode to Figure 10-
36. Setting up Test Trigger Mode
Addition of description to 10.8 SNOOZE mode function
Addition and modification of description to 10.10 Cautions for A/D Converter
Change the value to Table 10-6. Resistance and Capacitance Values of
Equivalent Circuit (Reference Values)
CHAPTER 10
A/D CONVERTER
Addition of description to CHAPTER 11 SERIAL ARRAY UNIT
Addition of description to 11.1.2 UART (UART0 to UART2)
Modification of Figure 11-1. to 11-3 Block Diagram of Serial Array Unit 0 (20- or
24-pin products)
Modification of Caution to Figure 11-6. Format of Peripheral Enable Register 0
(PER0)
Modification of frequency to Figure 11-7. Format of Serial Clock Select
Register m (SPSm)
Addition of description for Note to Figure 11-9. Format of Serial
Communication Operation Setting Register mn (SCRmn)
Addition of description to Figure 11-10. Format o f Serial Data Register mn
(SDRmn)
Addition of description to Figure 11-12. Format o f Serial Status Register mn
(SSRmn) (2/2)
Addition and modification of Note and Caution to Figure 11-13. Format of Serial
Channel Start Register m (SSm)
Addition and modification of Note to Figure 11-14. Format of Serial Channel
Stop Register m (STm), Figure 11-15. Format of Serial Channel Enable
Status Register m (SEm)
Addition of description to Figure 11-16. Format o f Serial Output Enable
Register m (SOEm) and Figure 11-17. Format of Serial Output Register m (SOm)
Addition of description to (13) Serial output level register m (SOLm)
Modification of description to Figure 11-19. Format of Serial Standby Control
Register 0 (SSC0)
Addition of description to (18) Port mode re gisters 0, 1, 3 to 6 (PM0, PM1, PM3 to
PM6)
Addition of description to Figure 11-25. Each Register Setting When Stopping
Operation by Channels
Modification of description to 11.5.1 Master transmission, 11.5.2 Master
reception, 11.5.3 Master transmission/reception
Modification of description to Figure 11-26, 34, 42, 50, 58, 64, 77, 85, 99, 103, 106
(Example of Contents of Registers)
Modification of description to Figure 11-28, 29, 31, 33, 36, 37, 39, 41, 44, 45, 47,
49, 52, 53, 55, 57, 60, 61, 63, 66, 69, 71, 73, 75, 79, 80, 82, 84, 86, 87, 88, 90, 93,
95, 100, 102, 105, 108 (flow chart)
Addition of description to 11.5.4 Slave transmission, 11.5.5 Slave reception,
11.5.6 Slave transmission/reception
Rev.1.00
Addition of Caution to 11.5.7 SNOOZE mode function (only CSI00), 11.6.3
SNOOZE mode function (onl y UART0 reception )
CHAPTER 11
SERIAL ARR AY UNIT
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 827
Sep. 28, 2012
(5/11)
Edition Description Chapter
Addition of Caution to 11.6 Operation of U ART (UART0 to UART2)
Communication
Modification of description to 11.7.1 Address field transmissi on, 11.7.2 Data
transmission, 11.7.3 Data reception
Addition of Caution to 11.7.5 Calculating transfer rate
Modification of description for example of setting IIC transfer rate
CHAPTER 11 SERIAL
ARRAY UNIT
Modification of description to Figure 12-6. Format of IICA Control Register 00
(IICCTL00)
Addition of description to Figure 12-7. Format o f IICA Status Register 0 (IICS0)
Modification of Figure 12-28, 29, 30
CHAPTER 12 SERIAL
INTERFACE IICA
Modification of Figure 13-1. Block Diagram of Multiplier and Di vider/Multiply-
Accumulator
Modification of value to Figure 13-6. Timing Diagram of Multiplication (Unsigned)
Operation (2 × 3 = 6)
Addition of description to 13.4.5 Division operation
CHAPTER 13
Addition of description
Addition of description to Table 15-1 and 15-2 Interrupt Source List
Addition of INTFL to Table 15-3 and 15-4 Flags Corresponding to Interrupt
Request Sources
Modification of description to Table 15-5. Time from Generation of Maskable
Interrupt Until Servicing
Modification of Figure 15-12. Interrupt Request Acknowledgment Timing
(Maximum Time)
Modification of Table 15-6. Relationship Between Interrupt Requests Enabled for
Multiple Interrupt Servicing During Interrupt Servicing
CHAPTER 15
INTERRUPT FUNCTION
Addition and modification of description to Though out CHAPTER 16 KEY
INTERRUPT FUNCTION
Modification of Caution to (3) SNOOZE mode
Modification of description to Table 17-1. Operati ng Statuses in HALT Mode
Addition and modification of rerease to standby function, wait time for SNOOZE status
CHAPTER 17
STANDBY FUNCTION
Addition of description to Table 18-1. Operation Statuses During Reset Period
Addition of description to Table 18-2. Hardware Statuses After Reset
Acknowledgment
Addition of Note to Table 18-2. Hardware Statuses After Reset Acknowledgment
CHAPTER 18 RESET
FUNCTION
Addition and modification of 19.1 Fun ct ions of Power-on-reset Circui t, 1 9 .3
Operation of Power- o n - r es et C irc ui t CHAPTER 19 POWER-
ON-RESET CIRCUIT
Modification of Figure 20-1. Block Diagram of Voltage Detector
Modification of description to Figure 20-2. Form at of Voltage Detection Register
(LVIM)
Addition of description to Figure 20-3. Format o f Voltage Detection Level Select
Register (LVIS)
Addition of Caution to Table 20-1. LVD Operation Mode and De tection Voltage
Settings for User Option Byte (000C1H)
Modification of Figure 20-4, 20-5, 20-6
Rev.1.00
Addition of description to Figure 20-7, 20-8
CHAPTER 20
VOLTAGE DETECTOR
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 828
Sep. 28, 2012
(6/11)
Edition Description Chapter
Addition of description to 21.3.1 CRC operation function (general-purpose CRC)
Addition of description to Figure 21-3. CRC Operation Function (General-Purpose
CRC)
Addition of description to Figure 21-5. Format o f Invalid Memory Access Detection
Control Register (IAWCTL)
Modification of Figure 21-7. Invalid access detection area
Addition of description to 21.3.7 A/D test function
CHAPTER 21 SAFETY
FUNCTIONS
Addition of Figure CHAPTER 22
REGULATOR
Addition of description to (2) 000C1H
Addition of description to Figure 23-1. Format o f User Option Byte (000C0H)
Modification and addition of Caution to Figure 23-2. Format of User Option Byte
(000C1H)
CHAPTER 23 OPTION
BYTE
Deletion of description to 24.1.1 Programming environment
Addition of description to 24.2 Writing to Flash Memory by Using External Device (that
Incorporates UART)
Addition of description to Figure 24-8. Setting of Flash Memory Programming Mode
Addition of description to Table 24-5, Table 24-13. Programming Modes and Voltages
at Which Data Can Be Written, Erased, or Verified
Modification of description to Table 24-10. Example of Signature Data
Addition of description to 24.6 Security Settings
CHAPTER 24 FLASH
MEMORY
Addition of Figure 25-3. Connection Example of E1 On-chip Debugging Emulator and
RL78/G12 (30-pin products)
Modification of description to Figure 25-4. Memory Spaces Where Debug Monitor
Programs Are Allocated
CHAPTER 25 ON-CHIP
DEBUG FUNCTION
Modification of flag status CHAPTER 27
INSTRUCTION SET
Rev.1.00
Deletion of target, and public release CHAPTER 28
ELECTRICAL
SPECIFICATIONS
Deletion of temperature trimming registers 0 to 3 (TEMPCAL0 to TEMPCAL3)
Change of value in power supply voltage: Throughout
Addition of description to 1.1 Features
Addition of description to 1.6 Outline of Functions CHAPTER 1 OUTLINE
Change of description for 2.1.4 Pins for each product (pins other than port pins)
Addition of 2.2 Description of Pin Functions CHAPTER 2 PIN
FUNCTIONS
Addition of note in Figures 3-3 to 3-5 Memory Map, Figures 3-10 to 3-12
Correspondence Between Data Memory and Addressing
Addition of description to 3.1.2 Mirror area
Addition of caution 2 to 3.1.3 Internal data memory space
Addition of caution 3 to 3.2.1 (3) Stack pointer (SP)
Addition of caution 2 to 3.2.2 General-purpose registers
Change of description in Table 3-7. Extended SFR (2nd SFR) List (2/5)
Addition of description to 3.4.3 Direct addressing
CHAPTER 3 CPU
ARCHITECTURE
Addition of 4.4 Port Function Operations
Rev.0.03
Change of setting value in Table 4-6. Settings of Port Mode Register and Output
Latch When Using Alternate Function and Table 4-9. Settings of Port Mode
Register and Output Latch When Using Alternate Function (30-pin products)
CHAPTER 4 PORT
FUNCTIONS
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 829
Sep. 28, 2012
(7/11)
Edition Description Chapter
Addition of value to 5.1 (1) <2> High-speed on-chip oscillator (HOCO)
Change of Figure 5-1. Block Diagram of Clock Generator
Addition of description to 5.3 (2) System clock control register (CKC)
Change of value in Figure 5-4. Format of Clock Operation Status Control Register
(CSC)
Change of description in 5.3 (4) Oscillation stabilization time counter status
register (OSTC)
Addition of value to Figure 5-6. Format of Oscillation Stabilizatio n Time Select
Register (OSTS)
Addition of description to 5.3 (6) Peripheral enable register 0 (PER0)
Addition of description to 5.3 (9) High-speed on-chip oscillator trimming re gister
(HIOTRM)
Addition of note 3 to Figure 5-13. Clock Generator Operation When Power Supply
Voltage Is Turned On
Addition of 5.6.1 Example of setting high-speed on-chip oscillator
Addition of description to 5.6.2 Example of setting X1 oscillation clock
Addition of description to 5.6.3 CPU clock status transition diagram
Addition of X1 clock to Table 5-4. Changing CPU Clock
Addition of description to 5.6.5 Time required for switchover of CPU clock and
main system clock
Change of description in Table 5-6. Conditions Before the Clock Oscillation Is
Stopped and Flag Settings
CHAPTER 5 CLOCK
GENERATOR
Addition of 6.1.3 8-bit timer operation function (channels 1 and 3 only)
Addition of description of caution 1 to Figure 6-7. Format of Peripheral Enable
Register 0 (PER0)
Addition of remark to Figure 6-8. Forma t of Timer Clock Select register 0 (TPS0)
Addition of address and change of description of note 2 in Figure 6-9. Format of
Timer Mode Register 0n (TMR0n)
Addition of address to Figure 6-10. Format of Timer Status Register 0n (TSR0n)
Addition of 30-pin products to Figure 6-11. Format of Timer Channel Enable Status
register 0 (TE0) to Figure 6-13. Format of Timer Channel Stop register 0 (TT0),
and Figure 6-15. Format of Timer Output Enable register 0 (TOE0)
Change of description in Figure 6-17. F ormat of Timer Output Level register 0
(TOL0)
Addition of description to 6.4.1 Basic Rules of Simult aneous Channel Operation
Function
Addition of 6.5 Operation Timing of Counter
Change of description in 6.6.1 TO0n pin output circuit configuration and 6.6.2
TO0n Pin Output Setting
Addition of 6.6.3 Cautions on Channel Output Operation
Addition of 6.6.4 Collective mani pulation of TO0n bit
Addition of 6.6.5 Timer Interrupt and TO0n Pin Output at Operation Start
Addition of 6.7 Independent Channel Operation Function of Timer Array Unit
Addition of 6.8 Simultaneous Channel Operation Function of Timer Array Unit
CHAPTER 6 TIMER
ARRAY UNIT
Change of description in 7.1 Functions of Interval Timer
Change of description and addition of caution to Figure 7-2. Format of Peripheral
Enable Register 0 (PER0)
Addition of caution to Figure 7-4. Format of Interval Timer Control Register (ITMC)
CHAPTER 7 INTERVAL
TIMER
Change of Figure 8-1. Block Diagram of Clock Output/Buzzer Output Con troller
Addition of frequency to Figure 8-2. Format of Clock Output Select Register n
(CKSn)
CHAPTER 8 CLOCK
OUTPUT/BUZZER
OUTPUT CONTROLLER
Rev.0.03
Change of remark in Table 9-4. Setting Window Open Period of Watchdog Timer CHAPTER 9
WATCHDOG TIMER
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 830
Sep. 28, 2012
(8/11)
Edition Description Chapter
Change of internal reference voltage
Change of Figure 10-1. Block Diagram of A/D Converter
Addition of caution to Table 10-1. Settings of ADCS and ADCE Bits
Change of description in Table 10-2. Setting and Clearing Conditions for ADCS Bit
Addition of frequency to f Table 10-3. A/D Conversion Time Selection
Change of Figure 10-6. Format of A/D Con verter Mode Register 1 (ADM1)
Change of bit name in Figure 10-7. Format of A/D Converter Mode Register 2
(ADM2)
Change of caution 5 in Figure 10-11. Format of Analog Input Channel
Specification Register (ADS)
Addition of 10.7 A/D Converter Setup Flowchart
Change of description of note 2 in 10.8 SNOOZE mode function
Addition of 10.10 Cautions for A/D Converter
CHAPTER 10 A/D
CONVERTER
Addition of description to CHAPTER 11 SERIAL ARRAY UNIT
Addition of description to 11.1.1 3-wire serial I/O (CSI00, CSI01, CSI11, CSI20)
Addition of description to 11.1.2 UART (UART0 to UART2)
Addition of description to 11.1.3 Simplified I2C (IIC00, IIC01, IIC11, IIC20)
Addition of SSC1 to Figure 11-3. Block Diagram of Serial Array Unit 1 (30-pin
products)
Addition of value to Figure 11-7. Format of Serial Clock Select Register m (SPSm)
Change of address in Figure 11-10. Format of Serial Data Register mn (SDRmn)
Addition of description to 11.3 (14) Serial standby control register m (SSCm)
Addition of description to 11.3 (16) Noise filter e nable register 0 (NFEN0)
Addition of description to 11.5 Operation of 3-Wire Serial I/O (CSI00, CSI01, CSI11,
CSI20) Communication
Change of value in (c) Serial communication operation setting register mn
(SCRmn) of Figure 11-86
Change of value of remark 1 in 11.6.4 (1) Baud rate calculation expression
CHAPTER 11 SERIAL
ARRAY UNIT
Change of description and addition of caution to Figure 12-9. Format of IICA
Control Register 01 (IICCTL01)
Addition of description to 12.3 (6) IICA low-level width setting register 0 (IICWL0)
Change of description in Figure 12-32. Example of Master to Slave
Communication and Figure 12-33. Example of Slave to Master Communication
CHAPTER 12 SERIAL
INTERFACE IICA
Change of value in Figure 13-6. Timing Diagram of Multiplication (Unsigned)
Operation (2 × 3 = 6)
Addition of description to 13.4.3 Multiply-accumulation (unsigned) operation
Addition of description to 13.4.4 Multiply-accumulation (signed) operation
Change of Figure 13-9. Timing Diagram of Multiply-Accumulation (signed)
Operation
CHAPTER 13
MULTIPLIER AND
DIVIDER/MULTIPLY-
ACCUMULATOR
Change of description in 14.2 (2) DMA RAM address register n (DRAn)
Addition of description to Figure 14-4. Format of DMA Mode Control Register n
(DMCn)
Addition of 14.5 Example of Setting of DMA Controller
Addition of 14.6 Cautions on Using DMA Controller
CHAPTER 14 DMA
CONTROLLER
Addition of 30-pin products to Figure 15-8. Format of External Interrupt Rising
Edge Enable Register (EGP0) and External Interrupt Falling Edge Enable
Register (EGN0)
CHAPTER 15
INTERRUPT FUNCTION
Rev.0.03
Addition of value to Figure 17-2. Format of Oscillation Stabilization Time Select
Register (OSTS) CHAPTER 17 STANDBY
FUNCTION
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 831
Sep. 28, 2012
(9/11)
Edition Description Chapter
Addition of description to Table 17-1. Operating Statuses in HALT Mode to Table
17-3. Operating Statuses in SNOOZE Mode
Addition of note in Figure 17-3. HALT Mode Release by Interrupt Request
Generation to Figure 17-6. STOP Mode Release by Reset
CHAPTER 17 STANDBY
FUNCTION
Change of value and hardware name in Table 18-2. Hardware Statuses After Reset
Acknowledgment
Addition of name and value of note 2 to Table 18-2. Hardware Statuses After Reset
Acknowledgment
CHAPTER 18 RESET
FUNCTION
Addition of note to Figure 19-2. Timing of Generation of Internal Reset Signal by
Power-on-reset Circuit and Voltage Detector
Change of value in Figure 19-3. Example of Software Processing After Reset
Release
CHAPTER 19 POWER-
ON-RESET CIRCUIT
Change of description in 20.1 Functions of Voltage Detector
Addition of note to Figure 20-2. Format of Voltage Detection Register (LVIM)
Change of notes to Figure 20-3. Format of Voltage Detection Level Select
Register (LVIS)
Change of Table 20-1. LVD Operation Mode and Detection Voltage Settings for
User Option Byte (000C1H)
Change of description in 20.4.1 When used as reset mode to 20.4.3 When used as
interrupt and reset mode
Change of Figure 20-4. Timing of Voltage Detector Internal Reset Signal
Generation (Option Byte LVIMDS1, LVIMDS0 = 1, 1) to Figure 20-6. Timing of
Voltage Detector Reset Signal and Interrupt Signal Generation (Option Byte
LVIMDS1, LVIMDS0 = 1, 0)
Change of Figure 20-8. D elay from the time LVD reset source is generated until
the time LVD reset has been generated or released
CHAPTER 20 VOLTAGE
DETECTOR
Change of all CHAPTER 21 SAFETY
FUNCTIONS
Change of Table 22-1. Regulator Output Voltage Conditions CHAPTER 22
REGULATOR
Deletion of description of 23.1.1 (2) 000C1H
Change of description in Figure 23-2. Format of User Option Byte (000C1H) and
Figure 23-3. Format of Option Byte (000C2H)
Change of setting value in 23.4 Setting of Option Byte
CHAPTER 23 OPTION
BYTE
Addition of description to 24.1.2 Communication mode
Change of description in Table 24-2. Pin Connection
Change of description in 24.2.2 Communication mode
Addition of description to 24.4.1 Data flash o verview
Change of description in 24.5.2 Flash memory programming mode
Addition of 24.5.5 Description of signature data
Change of description in (2) Self programming of Table 24-12.
Addition of description to 24.7.1 Flash shield window function
Change of description in Figure 24-14. Setting and changing of the flash shield
window function and relations with commands
Change of value in Table 24-13. Programming Modes and Voltages at Which Data
Can Be Written, Erased, or Verified
CHAPTER 24 FLASH
MEMORY
Change of Figure 25-1. C onnection Example of E1 On-chip Debugging Emulator
and RL78/G12
Rev.0.03
Addition of Figure 25-2. Connection Example of E1 On-chip Debugging Emulator
and RL78/G12 (When using to the alternative function of RESET pin)
CHAPTER 25 ON-CHIP
DEBUG FUNCTION
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 832
Sep. 28, 2012
(10/11)
Edition Description Chapter
Change of description in Figure 25-3. Memory Spaces Where Debug Monitor
Programs Are Allocated
CHAPTER 25 ON-CHIP
DEBUG FUNCTION
Addition of description to Table 27-1. Operand Identifiers and Specification
Methods CHAPTER 27
INSTRUCTION SET
Addition of value to 28.3.2 On-chip oscillator characteristics
Change of 28.4.1 Pin characteristics
Addition of value to 28.4.2 Supply current characteristics
Change of value in 28.5.1 Basic operation
Change of value in 28.6.1 Serial array unit
Addition of value to 28.7.1 A/D converter characteristics
Addition of value to 28.7.2 Temperature se nsor characteristics and 28.7.3 POR
circuit characteristics
Deletion of value of LVD detection voltage of interrupt & reset mode
Change of value in 28.8 Data Memory STOP Mode Low Supply Voltage Data
Retention Characteristics
Change of 28.10 Timing Specs for Switching Modes
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(target)
Rev.0.03
Addition of all CHAPTER 29 PACKAGE
DRAWINGS
Addition of the 30-pin product
Modification of the names "internal high-speed oscillator circuit" and "internal low-
speed oscillator circuit" to "high-speed on-chip oscillator (HOCO)" and "low-speed on-
chip oscillator (LOCO)"
Throughout
Addition of cautions in Figures 3-1 through 3-6 Me mory maps and Figure 3-8 through
3-13 Correspondences between data memory and addressing
Modification of reset values of P13 in Table 3-6 SFR list
Addition of high-speed on-chip oscillator frequency selecting register (HOCODIV) to
Table 3-7 Extended SFR (2ndSFR) list
Modification of description method of operand
CHAPTER 3 CPU
ARCHITECTURE
Addition of Cautions 1 through 3 in 4.2.1 20-, 24-pin product (2) Port 1
Addition of Caution 2 in 4.2.1 20-, 24-pin product (4) Port 4
Addition of Caution in 4.2.1 20-, 24-pin product (5) Port 6
CHAPTER 4 PORT
FUNCTIONS
Addition of the high-speed on-chip oscillator frequency selection register (HOCODIV)
in control registers
Deletion of LV (low-voltage main) mode in 5.6.1 Example of setting high-speed on-
chip oscillator
Modification of voltages in Figure 5-14 CPU clock status transition diagram
CHAPTER 5 CLOCK
GENERATOR
Addition of description of alternate ports in 6.2 Timer array unit configuration CHAPTER 6 TIMER
ARRAY UNIT
Modification in Figure 11-10 Format of Serial Data Register mn (SDRmn)
Deletion of values in Caution 2 in Figure 11-10 Format of Serial Data Register mn
(SDRmn) and Caution in 11.6.4 Calculating baud rate
CHAPTER 11 SERIAL
ARRAY UNIT
Addition of description in cautions in 12.4.2 Setting transfer clock by using the IICWL0
and IICWH0 registers CHAPTER 12 SERI AL
INTERFACE IICA
Addition of setting values in Figure 15-6 Format of Priority Specification Flag
Registers (PR00L, PR00H, PR01L, PR10L, PR10H, PR11L) (20-, 24-pin product) CHAPTER 15
INTERRUPT FUNCTIONS
Addition of Cautions 2 and 3 in Figure 18-5 Format of Reset Control Flag Register
(RESF) CHAPTER 18 RESET
FUNCTION
Rev.0.02
Modification of voltage in Figure 19-2 Timing of Generation of Internal Reset Signal by
Power-on-reset Circuit and Voltage Detectior CH APTER 19 POWER-
ON-RESET CIRCUIT
RL78/G12 APPENDIX A REVISION HISTORY
R01UH0200EJ0110 Rev.1.10 833
Sep. 28, 2012
(11/11)
Edition Description Chapter
Deletion of description in 20.1 Function of Voltage Detector
Modification in Figure 20-5 Timing of Interrupt Signal Generation
CHAPTER 20 VOLTAGE
DETECTIOR
Addition of Caution 2 in Figure 21-4 Format of RAM Parity Error Control Register
(RPECTL) CHAPTER 21 SAFETY
FUNCTIONS
Deletion of the description of boot swap CH APTER 23 OPTION
BYTE
Modification of description in Table 24-1 Wiring Between RL78/G12 and Dedicated
Flash Memory Programmer and Table 24-2 Pin Connection
Modification of description in Notes of 24.1.2 Communication Mode
Addition of description in 24.3.1 TOOL0 pin
Modification of description in 24.4.1 Data flash overview
Modification in Figure 24-8 Setting of Flash Memory Programming Mode
Modification in Table 24-7 Flash Memory Control Commands
Addition of Caution 2 in 24.7 Flash Memory Programming by Self-Programming
Addition of 24.7.1 Flash shield window function
CHAPTER 24 FLASH
MEMORY
Modification of values of Absolute Maximum Ratings
Modification of values of On-chip Oscillator Characteristics
Modification of values in 28.4 DC Characteristics
Modification of values in 28.6.1 Serial array unit
Addition of Caution in 28.6.1 Serial array unit
Addition of description in Caution of 28.6.1 Serial array unit
Addition and deletion of values in 28.7 Analog Characteristics, and modification of
the value in the same section
Modification in 28.9 Flash Memory Programming Characteristics
Rev.0.02
Modification in 28.10 Timing Specs for Switching Modes and of tHD unit
CHAPTER 28
ELECTRICAL
SPECIFICATIONS
(TARGET)
RL78/G12 User’s Manual: Hardware
Publication Date: Rev.1.10 Sep. 28, 2012
Published by: Renesas Electronics Corporation
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