DS05-50211-2E
FUJITSU SEMICONDUCTOR
DATA SHEET
Stacked MCP (Multi-Chip Package) FLASH MEMORY & SRAM
CMOS
64M (×8/×16) FLASH MEMORY &
8M (×8/×16) STATIC RAM
MB84VD23280EA-90/MB84VD23280EE-90
■FEATURES
• Power supply voltage of 2.7 V to 3.3 V
• High performance
90 ns maximum access time (Flash)
70 ns maximum access time (SRAM)
• Operating Temperature
–25 °C to +85 °C
• Package 101-ball BGA
(Continued)
■PRODUCT LINEUP
*: Both VCCf and VCCs must be in recommended operation range when wither part is being accessed.
■PACKAGE
Flash Memory SRAM
Ordering Part No. VCCf*, VCCs* = 3.0 V MB84VD23280EA-90/MB84VD23280EE-90
Max. Address Access Time (ns) 90 70
Max. CE Access Time (ns) 90 70
Max. OE Access Time (ns) 35 35
101-pin plastic FBGA
BGA-101P-M01
+0.3V
–0.3 V
MB84VD23280EA-90/MB84VD23280EE-90
2
(Continued)
—FLASH MEMORY
• Simultaneous Read/Write operations (flex bank)
Two virtual Banks are chosen from the combination of four physical banks
Host system can program or erase in one bank, then read immediately and simultaneously read from the other
bank between read and write operations
Read-while-erase
Read-while-program
• Minimum 100,000 write/erase cycles
• Sector erase architecture
Sixteen 4 K words and one hundred twenty-six 32 K word.
Any combination of sectors can be concurrently erased. Also supports full chip erase.
• Embedded EraseTM* Algorithms
Automatically pre-programs and erases the chip or any sector
• Embedded ProgramTM* Algorithms
Automatically writes and verifies data at specified address
•Data Polling and Toggle Bit feature for detection of program or erase cycle completion
• Ready-Busy output (RY/BY)
Hardware method for detection of program or erase cycle completion
• Automatic sleep mode
When addresses remain stable, automatically switch themselves to low power mode.
•Low V
CC write inhibit ≤ 2.5 V
• Hidden ROM (Hi-ROM) region
256 byte of Hi-ROM, accessible through a new “Hi-ROM Enable” command sequence
Factory serialized and protected to provide a secure electronic serial number (ESN)
•WP
/ACC input pin
At VIL, allows protection of 2 of 8 Kbytes on both ends of each boot sector, regardless of sector protection/
unprotection status.
At VIH, allows removal of boot sector protection
At VACC, increases program performance
• Pro gram Suspend/Resume
Suspends the program operation to allow a read in another address
• Erase Suspend/Resume
Suspends the erase operation to allow a read in another sector within the same device
• Please refer to “MBM29DL640E” data sheet in detailed function
—SRAM
• Power dissipation
Operating: 50 mA Max.
Standby : 15 µA Max.
• Power down features using CE1s and CE2s
• Data retention supply voltage: 1.5 V to 3.3 V
•CE1s and CE2s Chip Select
• Byte data control: LBs (DQ7-DQ0), UBs (DQ15-DQ8)
*: Embedded EraseTM and Embedded Prog ramTM are trademarks of Advanced Micro Devices, Inc.
MB84VD23280EA-90/MB84VD23280EE-90
3
■PIN ASSIGNMENT
(BGA-101P-M01)
Marking Side
(TOP View)
DQ
8
DQ
2
DQ
11
DQ
14
N.C.
N.C.N.C.N.C.
N.C.N.C.N.C.
CIOs N.C.CE2s
N.C. N.C.
D9
D8
D7
D6
D5
C7
C6
E9
E8
E7
E6
F9
F8
F7
F6
G9
G8
G5
H9
H8
H5
J9
J8
J7
J6
K9
K8
K7
K6
L9
L8
L7
L6
E5 F5 J5 K5 L5
D4 G4 H4
E4 F4 J4 K4 L4
G3 H3
G2 H2
E3 F3 J3 K3
M7
M6
A
11
LBs
WP/ACC
WE
A
7
D2
A
12
E10 F10 G10 H10 J10 K10
A
15
A
3
UBs
RESET
A
6
A
13
A
20
A
2
A
18
RY/BY
A
21
A
5
A
14
A
1
A
17
N.C.
G11C11B11A11
N.C.
A10 B10 C10
N.C.N.C.N.C.
A12 B12 C12
N.C. N.C.N.C.N.C.
N.C.N.C.N.C.
C2B2A2
A1 B1 C1
N.C.N.C.N.C.
A3 B3 C3
N.C.N.C.N.C.
N.C.N.C.N.C.
P2N2M2
M1 N1 P1
N.C.N.C.N.C.
M3 N3 P3
N.C.N.C.N.C.
N.C.N.C.N.C.
P11N11M11
M10 N10 P10
N.C.N.C.N.C.
M12 N12 P12
N.C.
A
4
SA
A
16
A
0
DQ
1
N.C.
H11
N.C.
Vss
DQ
10
Vccf
Vccs
DQ
7
DQ
15
/A
-1
DQ
5
A
8
A
19
A
9
A
10
DQ
6
DQ
12
DQ
13
Vss
CE1s
DQ
0
CEf
DQ
4
DQ
3
DQ
9
CIOf
OE
MB84VD23280EA-90/MB84VD23280EE-90
4
■
■■
■PIN DESCRIPTION
Pin name Input/
Output Description
A18 to A0I Address Inputs (Common)
A21 to A19, A–1 I Address Inputs (Flash)
SA I Address Input (SRAM)
DQ15 to DQ0I/O Data Inputs/Outputs (Common)
CEf I Chip Enable (Flash)
CE1s I Chip Enable (SRAM)
CE2s I Chip Enable (SRAM)
OE I Output Enable (Common)
WE I Write Enable (Common)
RY/BY O Ready/Busy Output (Flash) Open Drain Output
UBs I Upper Byte Control (SRAM)
LBs I Lower Byte Control (SRAM)
CIOf I I/O Configuration (Flash)
CIOf = VCCf is Word mode (×16), CIOf = VSS is Byte mode (×8)
CIOs I I/O Configuration (SRAM)
CIOs = VCCs is Word mode (×16), CIOs = VSS is Byte mode (×8)
RESET I Hardware Reset Pin/Sector Protection Unlock (Flash)
WP/ACC I Write Protect / Acceleration (Flash)
N.C. — No Internal Connection
VSS Power Device Ground (Common)
VCCf Power Device Power Supply (Flash)
VCCs Power Device Power Supply (SRAM)
MB84VD23280EA-90/MB84VD23280EE-90
5
■BLOCK DIAGRAM
VSS
VCCs
64 M bit
RESET Flash Memory
WE
8 M bit
Static RAM
CEf
A21 to A0
OE
CE1s
VSS
VCCf
A21 to A0
A18 to A0
DQ15/A–1 to DQ0
RY/BY
LBs
UBs
CIOf
WP/ACC
CE2s
DQ15/A–1 to DQ0
DQ15 to DQ0
A–1
SA
CIOs
MB84VD23280EA-90/MB84VD23280EE-90
6
■
■■
■DEVICE BUS OPERATIONS
Table 1. 1 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Word mode; CIOs = VCCs)
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:Protect of 2 of 8 Kbytes on both ends of each boot sector.
*6:SA; Don’t care or Open.
Operation *1, *3CEfCE1sCE2s OE WE SA
*6LBsUBsDQ
7 to DQ0DQ15 to DQ8RESET WP/
ACC
*5
Full Standby H HX
X X X X X High-Z High-Z H X
XL
Output Disable
HLHH H X X X High-Z High-Z
HX
X X X H H High-Z High-Z
LHX
H H X X X High-Z High-Z
XL
Read from Flash *2LHXLHXXX DOUT DOUT HX
XL
Write to Flash L HX
HLXXX D
IN DIN HX
XL
Read from SRAM H L H L H X
LL D
OUT DOUT
HXH L High-Z DOUT
LH DOUT High-Z
Write to SRAM H L H X L X
LL D
IN DIN
HXH L High-Z DIN
LH DIN High-Z
Temporary Sector
Group
Unprotection *4X X X XXXXX X X VID X
Flash Hardware
Reset XHX
X X X X X High-Z High-Z L X
XL
Boot Block Sector
Write Protection X X X XXXXX X X X L
MB84VD23280EA-90/MB84VD23280EE-90
7
Table 1. 2 User Bus Operations (Flash = Word mode; CIOf = VCCf, SRAM = Byte mode; CIOs = VSS)
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:Protect of 2 of 8 Kbytes on both ends of each boot sector.
*6:LBS , UBS; Don’t care or Open.
Operation *1, *3CEfCE1sCE2s OE WE SA LBs
*6UBs
*6DQ7 to DQ0DQ15 to DQ8RESET WP/
ACC
*5
Full Standby H HX
X X X X X High-Z High-Z H X
XL
Output Disable
HLHH H X X X High-Z High-Z
HX
X X X H H High-Z High-Z
LHX
H H X X X High-Z High-Z
XL
Read from Flash *2LHXLHXXX DOUT DOUT HX
XL
Write to Flash L HX
HLXXX D
IN DIN HX
XL
Read from SRAM H L H L H SA X X DOUT High-Z H X
Write to SRAM H L H X L SA X X DIN High-Z H X
Temporary Sector
Group
Unprotection *4X X X XXXXX X X VID X
Flash Hardware
Reset XHX
X X X X X High-Z High-Z L X
XL
Boot Block Sector
Write Protection X X X XXXXX X X X L
MB84VD23280EA-90/MB84VD23280EE-90
8
Table 1. 3 User Bus Operations (Flash = Byte mode; CIOf = VSS, SRAM = Byte mode; CIOs = VSS)
Legend: L = VIL, H = VIH, X = VIL or VIH. See DC Characteristics for voltage levels.
*1:Other operations except for indicated this column are inhibited.
*2:WE can be VIL if OE is VIL, OE at VIH initiates the write operations.
*3:Do not apply CEf = VIL, CE1s = VIL and CE2s = VIH at a time.
*4:It is also used for the extended sector group protections.
*5:Protect of 2 of 8 Kbytes on both ends of each boot sector.
*6:LBS , UBS; Don’t care or Open.
Operation *1, *3CEfCE1sCE2sDQ
15/A–1OE WE SA LBs
*6UBs
*6DQ7 to
DQ0DQ14 to
DQ8RESET WP/
ACC
*5
Full Standby H HX X X X X X X High-Z High-Z H X
XL
Output Disable
HL H X H H X X X High-Z High-Z
HX
X X X X H H High-Z High-Z
LHX A–1 H H X X X High-Z High-Z
XL
Read from Flash *2LHX A–1 LHXX X DOUT XHX
XL
Write to Flash L HX A–1 HLXX X DIN XHX
XL
Read from SRAM H L H X L H SA X X DOUT High-Z H X
Write to SRAM H L H X X L SA X X DIN High-Z H X
Temporary Sector
Group
Unprotection *4X X X X XXXX X X X VID X
Flash Hardware
Reset XHX X X X X X X High-Z High-Z L X
XL
Boot Block Sector
Write Protection X X X X XXXX X X X X L
MB84VD23280EA-90/MB84VD23280EE-90
9
■
■■
■FLEXIBLE SECTOR-ERASE ARCHITECTURE on FLASH MEMORY
• Sixteen 4K words, and one hundred twenty-six 32 K words.
• Individual-sector, multiple-sector, or bulk-erase capability.
MB84VD23280EA/EE Sector Architecture
SA31 : 64KB (32KW)
SA30 : 64KB (32KW)
SA29 : 64KB (32KW)
SA28 : 64KB (32KW)
SA27 : 64KB (32KW)
SA26 : 64KB (32KW)
SA25 : 64KB (32KW)
SA24 : 64KB (32KW)
SA23 : 64KB (32KW)
SA22 : 64KB (32KW)
SA21 : 64KB (32KW)
SA20 : 64KB (32KW)
SA19 : 64KB (32KW)
SA18 : 64KB (32KW)
SA17 : 64KB (32KW)
SA16 : 64KB (32KW)
SA15 : 64KB (32KW)
SA14 : 64KB (32KW)
SA13 : 64KB (32KW)
SA12 : 64KB (32KW)
SA11 : 64KB (32KW)
SA10 : 64KB (32KW)
SA9 : 64KB (32KW)
SA8 : 64KB (32KW)
SA7 : 8KB (4KW)
SA6 : 8KB (4KW)
SA5 : 8KB (4KW)
SA4 : 8KB (4KW)
SA3 : 8KB (4KW)
SA2 : 8KB (4KW)
SA70 : 64KB (32KW)
SA69 : 64KB (32KW)
SA68 : 64KB (32KW)
SA67 : 64KB (32KW)
SA66 : 64KB (32KW)
SA65 : 64KB (32KW)
SA64 : 64KB (32KW)
SA63 : 64KB (32KW)
SA62 : 64KB (32KW)
SA61 : 64KB (32KW)
SA60 : 64KB (32KW)
SA59 : 64KB (32KW)
SA58 : 64KB (32KW)
SA57 : 64KB (32KW)
SA56 : 64KB (32KW)
SA55 : 64KB (32KW)
SA54 : 64KB (32KW)
SA53 : 64KB (32KW)
SA52 : 64KB (32KW)
SA51 : 64KB (32KW)
SA50 : 64KB (32KW)
SA49 : 64KB (32KW)
SA48 : 64KB (32KW)
SA47 : 64KB (32KW)
SA46 : 64KB (32KW)
SA45 : 64KB (32KW)
SA44 : 64KB (32KW)
SA43 : 64KB (32KW)
SA42 : 64KB (32KW)
SA41 : 64KB (32KW)
SA40 : 64KB (32KW)
SA39 : 64KB (32KW)
SA38 : 64KB (32KW)
SA37 : 64KB (32KW)
SA36 : 64KB (32KW)
SA35 : 64KB (32KW)
SA34 : 64KB (32KW)
SA33 : 64KB (32KW)
SA32 : 64KB (32KW)
SA1 : 8KB (4KW)
SA0 : 8KB (4KW)
Bank A
Bank B
070000h
078000h
060000h
068000h
050000h
058000h
040000h
048000h
030000h
038000h
020000h
028000h
010000h
018000h
007000h
008000h
005000h
006000h
003000h
004000h
001000h
002000h
000000h
SA102 : 64KB (32KW)
SA101 : 64KB (32KW)
SA100 : 64KB (32KW)
SA99 : 64KB (32KW)
SA98 : 64KB (32KW)
SA97 : 64KB (32KW)
SA96 : 64KB (32KW)
SA95 : 64KB (32KW)
SA94 : 64KB (32KW)
SA93 : 64KB (32KW)
SA92 : 64KB (32KW)
SA91 : 64KB (32KW)
SA90 : 64KB (32KW)
SA89 : 64KB (32KW)
SA88 : 64KB (32KW)
SA87 : 64KB (32KW)
SA86 : 64KB (32KW)
SA85 : 64KB (32KW)
SA84 : 64KB (32KW)
SA83 : 64KB (32KW)
SA82 : 64KB (32KW)
SA81 : 64KB (32KW)
SA80 : 64KB (32KW)
SA79 : 64KB (32KW)
SA78 : 64KB (32KW)
SA77 : 64KB (32KW)
SA76 : 64KB (32KW)
SA75 : 64KB (32KW)
SA74 : 64KB (32KW)
SA73 : 64KB (32KW)
3FFFFFh
SA141 : 8KB (4KW)
SA140 : 8KB (4KW)
SA139 : 8KB (4KW)
SA138 : 8KB (4KW)
SA137 : 8KB (4KW)
SA136 : 8KB (4KW)
SA135 : 8KB (4KW)
SA134 : 8KB (4KW)
SA133 : 64KB (32KW)
SA132 : 64KB (32KW)
SA131 : 64KB (32KW)
SA130 : 64KB (32KW)
SA129 : 64KB (32KW)
SA128 : 64KB (32KW)
SA127 : 64KB (32KW)
SA126 : 64KB (32KW)
SA125 : 64KB (32KW)
SA124 : 64KB (32KW)
SA123 : 64KB (32KW)
SA122 : 64KB (32KW)
SA121 : 64KB (32KW)
SA120 : 64KB (32KW)
SA119 : 64KB (32KW)
SA118 : 64KB (32KW)
SA117 : 64KB (32KW)
SA116 : 64KB (32KW)
SA115 : 64KB (32KW)
SA114 : 64KB (32KW)
SA113 : 64KB (32KW)
SA112 : 64KB (32KW)
SA111 : 64KB (32KW)
SA110 : 64KB (32KW)
SA109 : 64KB (32KW)
SA108 : 64KB (32KW)
SA107 : 64KB (32KW)
SA106 : 64KB (32KW)
SA105 : 64KB (32KW)
SA104 : 64KB (32KW)
SA103 : 64KB (32KW)
SA72 : 64KB (32KW)
SA71 : 64KB (32KW)
Bank C
Bank D
3FF000h
3FE000h
3FD000h
3FC000h
3FB000h
3FA000h
3F9000h
0F0000h
0F8000h
0E0000h
0E8000h
0D0000h
0D8000h
0C0000h
0C8000h
0B0000h
0B8000h
0A0000h
0A8000h
090000h
098000h
088000h
080000h
170000h
178000h
160000h
168000h
150000h
158000h
140000h
148000h
130000h
138000h
120000h
128000h
110000h
118000h
100000h
108000h
1F0000h
1F8000h
1E0000h
1E8000h
1D0000h
1D8000h
1C0000h
1C8000h
1B0000h
1B8000h
1A0000h
1A8000h
190000h
198000h
188000h
180000h
270000h
278000h
260000h
268000h
250000h
258000h
240000h
248000h
230000h
238000h
220000h
228000h
210000h
218000h
208000h
2F0000h
2F8000h
2E0000h
2E8000h
2D0000h
2D8000h
2C0000h
2C8000h
2B0000h
2B8000h
2A0000h
2A8000h
290000h
298000h
288000h
280000h
370000h
378000h
360000h
368000h
350000h
358000h
340000h
348000h
330000h
338000h
320000h
328000h
310000h
318000h
300000h
308000h
3F0000h
3F8000h
3E0000h
3E8000h
3D0000h
3D8000h
3C0000h
3C8000h
3B0000h
3B8000h
3A0000h
3A8000h
390000h
398000h
388000h
380000h
200000h
1FFFFFh
0E0000h
0F0000h
0C0000h
0D0000h
0A0000h
0B0000h
080000h
090000h
060000h
070000h
040000h
050000h
020000h
030000h
00E000h
010000h
00A000h
00C000h
006000h
008000h
002000h
004000h
000000h
1E0000h
1F0000h
1C0000h
1D0000h
1A0000h
1B0000h
180000h
190000h
160000h
170000h
140000h
158000h
120000h
130000h
110000h
100000h
2E0000h
2F0000h
2C0000h
2D0000h
2A0000h
2B0000h
280000h
290000h
260000h
270000h
240000h
250000h
220000h
230000h
200000h
210000h
3E0000h
3F0000h
3C0000h
3D0000h
3A0000h
3B0000h
380000h
390000h
360000h
370000h
340000h
350000h
320000h
330000h
310000h
300000h
3FFFFFh
Word Mode Byte Mode Word Mode Byte Mode
7FFFFFh
7FE000h
7FC000h
7FA000h
7F8000h
7F6000h
7F4000h
7F2000h
4E0000h
4F0000h
4C0000h
4D0000h
4A0000h
4B0000h
480000h
490000h
460000h
470000h
440000h
450000h
420000h
430000h
410000h
5E0000h
5F0000h
5C0000h
5D0000h
5A0000h
5B0000h
580000h
590000h
560000h
570000h
540000h
550000h
520000h
530000h
510000h
500000h
6E0000h
6F0000h
6C0000h
6D0000h
6A0000h
6B0000h
680000h
690000h
660000h
670000h
640000h
650000h
620000h
630000h
600000h
610000h
7E0000h
7F0000h
7C0000h
7D0000h
7A0000h
7B0000h
780000h
790000h
760000h
770000h
740000h
750000h
720000h
730000h
710000h
700000h
400000h
MB84VD23280EA-90/MB84VD23280EE-90
10
Table 2 Example of Virtual Banks Combination
BankA: Address 000000h to 07FFFFh (Word) , 000000h to 0FFFFFh (Byte)
BankB: Address 080000h to 1FFFFFh (Word) , 100000h to 3FFFFFh (Byte)
BankC: Address 200000h to 37FFFFh (Word) , 400000h to 6FFFFFh (Byte)
BankD: Address 380000h to 3FFFFFh (Word) , 700000h to 7FFFFFh (Byte)
Table 3 Sector Address Tables
(Continued)
Bank
Splits Bank 1 Bank 2
Volume Combination Sector Size Volume Combination Sector Size
1 8M bit Bank A 8 of 8 Kbyte / 4 K word
+
15 of 64 Kbyte / 32 K word 56 Mbit
Bank B
+
Bank C
+
Bank D
8 of 8 Kbyte / 4 K word
+
111 of 64 Kbyte / 32 K word
216 MbitBank A
+
Bank D
16 of 8 Kbyte / 4 K word
+
30 of 64 Kbyte / 32 K word 48 Mbit Bank B
+
Bank C 96 of 64 Kbyte / 32 K word
3 24 Mbit Bank B 48 of 64 Kbyte / 32 K word 40 Mbit
Bank A
+
Bank C
+
Bank D
16 of 8 Kbyte / 4 K word
+
78 of 64 Kbyte / 32 K word
432 MbitBank A
+
Bank B
8 of 8 Kbyte / 4 K word
+
63 of 64 Kbyte / 32 K word 32 Mbit Bank C
+
Bank D
8 of 8 Kbyte / 4 K word
+
63 of 64 Kbyte / 32 K word
Bank Sector Sector Address Address Range
Bank Address Byte Mode Word Mode
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank A
SA0 0 0 0 0 0 0 0 0 0 0 000000h to 001FFFh 000000h to 000FFFh
SA1 0 0 0 0 0 0 0 0 0 1 002000h to 003FFFh 001000h to 001FFFh
SA2 0 0 0 0 0 0 0 0 1 0 004000h to 005FFFh 002000h to 002FFFh
SA3 0 0 0 0 0 0 0 0 1 1 006000h to 007FFFh 003000h to 003FFFh
SA4 0 0 0 0 0 0 0 1 0 0 008000h to 009FFFh 004000h to 004FFFh
SA5 0 0 0 0 0 0 0 1 0 1 00A000h to 00BFFFh 005000h to 005FFFh
SA6 0 0 0 0 0 0 0 1 1 0 00C000h to 00DFFFh 006000h to 006FFFh
SA7 0 0 0 0 0 0 0 1 1 1 00E000h to 00FFFFh 007000h to 007FFFh
SA8 0 0 0 0 0 0 1 X X X 010000h to 01FFFFh 008000h to 00FFFFh
SA9 0 0 0 0 0 1 0 X X X 020000h to 02FFFFh 010000h to 017FFFh
SA10 0 0 0 0 0 1 1 X X X 030000h to 03FFFFh 018000h to 01FFFFh
SA11 0 0 0 0 1 0 0 X X X 040000h to 04FFFFh 020000h to 027FFFh
SA12 0 0 0 0 1 0 1 X X X 050000h to 05FFFFh 028000h to 02FFFFh
SA13 0 0 0 0 1 1 0 X X X 060000h to 06FFFFh 030000h to 037FFFh
SA14 0 0 0 0 1 1 1 X X X 070000h to 07FFFFh 038000h to 03FFFFh
SA15 0 0 0 1 0 0 0 X X X 080000h to 08FFFFh 040000h to 047FFFh
SA16 0 0 0 1 0 0 1 X X X 090000h to 09FFFFh 048000h to 04FFFFh
SA17 0 0 0 1 0 1 0 X X X 0A0000h to 0AFFFFh 050000h to 057FFFh
SA18 0 0 0 1 0 1 1 X X X 0B0000h to 0BFFFFh 058000h to 05FFFFh
SA19 0 0 0 1 1 0 0 X X X 0C0000h to 0CFFFFh 060000h to 067FFFh
SA20 0 0 0 1 1 0 1 X X X 0D0000h to 0DFFFFh 068000h to 06FFFFh
SA21 0 0 0 1 1 1 0 X X X 0E0000h to 0EFFFFh 070000h to 077FFFh
SA22 0 0 0 1 1 1 1 X X X 0F0000h to 0FFFFFh 078000h to 07FFFFh
MB84VD23280EA-90/MB84VD23280EE-90
11
(Continued)
(Continued)
Bank Sector Sector Address Address Range
Bank Address Byte Mode Word Mode
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank B
SA23 0 0 1 0 0 0 0 X X X 100000h to 10FFFFh 080000h to 087FFFh
SA24 0 0 1 0 0 0 1 X X X 110000h to 11FFFFh 088000h to 08FFFFh
SA25 0 0 1 0 0 1 0 X X X 120000h to 12FFFFh 090000h to 097FFFh
SA26 0 0 1 0 0 1 1 X X X 130000h to 13FFFFh 098000h to 09FFFFh
SA27 0 0 1 0 1 0 0 X X X 140000h to 14FFFFh 0A0000h to 0A7FFFh
SA28 0 0 1 0 1 0 1 X X X 150000h to 15FFFFh 0A8000h to 0AFFFFh
SA29 0 0 1 0 1 1 0 X X X 160000h to 16FFFFh 0B0000h to 0B7FFFh
SA30 0 0 1 0 1 1 1 X X X 170000h to 17FFFFh 0B8000h to 0BFFFFh
SA31 0 0 1 1 0 0 0 X X X 180000h to 18FFFFh 0C0000h to 0C7FFFh
SA32 0 0 1 1 0 0 1 X X X 190000h to 19FFFFh 0C8000h to 0CFFFFh
SA33 0 0 1 1 0 1 0 X X X 1A0000h to 1AFFFFh 0D0000h to 0D7FFFh
SA34 0 0 1 1 0 1 1 X X X 1B0000h to 1BFFFFh 0D8000h to 0DFFFFh
SA35 0 0 1 1 1 0 0 X X X 1C0000h to 1CFFFFh 0E0000h to 0E7FFFh
SA36 0 0 1 1 1 0 1 X X X 1D0000h to 1DFFFFh 0E8000h to 0EFFFFh
SA37 0 0 1 1 1 1 0 X X X 1E0000h to 1EFFFFh 0F0000h to 0F7FFFh
SA38 0 0 1 1 1 1 1 X X X 1F0000h to 1FFFFFh 0F8000h to 0FFFFFh
SA39 0 1 0 0 0 0 0 X X X 200000h to 20FFFFh 100000h to 107FFFh
SA40 0 1 0 0 0 0 1 X X X 210000h to 21FFFFh 108000h to 10FFFFh
SA41 0 1 0 0 0 1 0 X X X 220000h to 22FFFFh 110000h to 117FFFh
SA42 0 1 0 0 0 1 1 X X X 230000h to 23FFFFh 118000h to 11FFFFh
SA43 0 1 0 0 1 0 0 X X X 240000h to 24FFFFh 120000h to 127FFFh
SA44 0 1 0 0 1 0 1 X X X 250000h to 25FFFFh 128000h to 12FFFFh
SA45 0 1 0 0 1 1 0 X X X 260000h to 26FFFFh 130000h to 137FFFh
SA46 0 1 0 0 1 1 1 X X X 270000h to 27FFFFh 138000h to 13FFFFh
SA47 0 1 0 1 0 0 0 X X X 280000h to 28FFFFh 140000h to 147FFFh
SA48 0 1 0 1 0 0 1 X X X 290000h to 29FFFFh 148000h to 14FFFFh
SA49 0 1 0 1 0 1 0 X X X 2A0000h to 2AFFFFh 150000h to 157FFFh
SA50 0 1 0 1 0 1 1 X X X 2B0000h to 2BFFFFh 158000h to 15FFFFh
SA51 0 1 0 1 1 0 0 X X X 2C0000h to 2CFFFFh 160000h to 167FFFh
SA52 0 1 0 1 1 0 1 X X X 2D0000h to 2DFFFFh 168000h to 16FFFFh
SA53 0 1 0 1 1 1 0 X X X 2E0000h to 2EFFFFh 170000h to 177FFFh
SA54 0 1 0 1 1 1 1 X X X 2F0000h to 2FFFFFh 178000h to 17FFFFh
SA55 0 1 1 0 0 0 0 X X X 300000h to 30FFFFh 180000h to 187FFFh
SA56 0 1 1 0 0 0 1 X X X 310000h to 31FFFFh 188000h to 18FFFFh
SA57 0 1 1 0 0 1 0 X X X 320000h to 32FFFFh 190000h to 197FFFh
SA58 0 1 1 0 0 1 1 X X X 330000h to 33FFFFh 198000h to 19FFFFh
SA59 0 1 1 0 1 0 0 X X X 340000h to 34FFFFh 1A0000h to 1A7FFFh
SA60 0 1 1 0 1 0 1 X X X 350000h to 35FFFFh 1A8000h to 1AFFFFh
SA61 0 1 1 0 1 1 0 X X X 360000h to 36FFFFh 1B0000h to 1B7FFFh
SA62 0 1 1 0 1 1 1 X X X 370000h to 37FFFFh 1B8000h to 1BFFFFh
SA63 0 1 1 1 0 0 0 X X X 380000h to 38FFFFh 1C0000h to 1C7FFFh
SA64 0 1 1 1 0 0 1 X X X 390000h to 39FFFFh 1C8000h to 1CFFFFh
SA65 0 1 1 1 0 1 0 X X X 3A0000h to 3AFFFFh 1D0000h to 1D7FFFh
SA66 0 1 1 1 0 1 1 X X X 3B0000h to 3BFFFFh 1D8000h to 1DFFFFh
SA67 0 1 1 1 1 0 0 X X X 3C0000h to 3CFFFFh 1E0000h to 1E7FFFh
SA68 0 1 1 1 1 0 1 X X X 3D0000h to 3DFFFFh 1E8000h to 1EFFFFh
SA69 0 1 1 1 1 1 0 X X X 3E0000h to 3EFFFFh 1F0000h to 1F7FFFh
SA70 0 1 1 1 1 1 1 X X X 3F0000h to 3FFFFFh 1F8000h to 1FFFFFh
MB84VD23280EA-90/MB84VD23280EE-90
12
(Continued)
(Continued)
Bank Sector Sector Address Address Range
Bank Address Byte Mode Word Mode
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank C
SA71 1 0 0 0 0 0 0 X X X 400000h to 40FFFFh 200000h to 207FFFh
SA72 1 0 0 0 0 0 1 X X X 410000h to 41FFFFh 208000h to 20FFFFh
SA73 1 0 0 0 0 1 0 X X X 420000h to 42FFFFh 210000h to 217FFFh
SA74 1 0 0 0 0 1 1 X X X 430000h to 43FFFFh 218000h to 21FFFFh
SA75 1 0 0 0 1 0 0 X X X 440000h to 44FFFFh 220000h to 227FFFh
SA76 1 0 0 0 1 0 1 X X X 450000h to 45FFFFh 228000h to 22FFFFh
SA77 1 0 0 0 1 1 0 X X X 460000h to 46FFFFh 230000h to 237FFFh
SA78 1 0 0 0 1 1 1 X X X 470000h to 47FFFFh 238000h to 23FFFFh
SA79 1 0 0 1 0 0 0 X X X 480000h to 48FFFFh 240000h to 247FFFh
SA80 1 0 0 1 0 0 1 X X X 490000h to 49FFFFh 248000h to 24FFFFh
SA81 1 0 0 1 0 1 0 X X X 4A0000h to 4AFFFFh 250000h to 257FFFh
SA82 1 0 0 1 0 1 1 X X X 4B0000h to 4BFFFFh 258000h to 25FFFFh
SA83 1 0 0 1 1 0 0 X X X 4C0000h to 4CFFFFh 260000h to 267FFFh
SA84 1 0 0 1 1 0 1 X X X 4D0000h to 4DFFFFh 268000h to 26FFFFh
SA85 1 0 0 1 1 1 0 X X X 4E0000h to 4EFFFFh 270000h to 277FFFh
SA86 1 0 0 1 1 1 1 X X X 4F0000h to 4FFFFFh 278000h to 27FFFFh
SA87 1 0 1 0 0 0 0 X X X 500000h to 50FFFFh 280000h to 287FFFh
SA88 1 0 1 0 0 0 1 X X X 510000h to 51FFFFh 288000h to 28FFFFh
SA89 1 0 1 0 0 1 0 X X X 520000h to 52FFFFh 290000h to 297FFFh
SA90 1 0 1 0 0 1 1 X X X 530000h to 53FFFFh 298000h to 29FFFFh
SA91 1 0 1 0 1 0 0 X X X 540000h to 54FFFFh 2A0000h to 2A7FFFh
SA92 1 0 1 0 1 0 1 X X X 550000h to 55FFFFh 2A8000h to 2AFFFFh
SA93 1 0 1 0 1 1 0 X X X 560000h to 56FFFFh 2B0000h to 2B7FFFh
SA94 1 0 1 0 1 1 1 X X X 570000h to 57FFFFh 2B8000h to 2BFFFFh
SA95 1 0 1 1 0 0 0 X X X 580000h to 58FFFFh 2C0000h to 2C7FFFh
SA96 1 0 1 1 0 0 1 X X X 590000h to 59FFFFh 2C8000h to 2CFFFFh
SA97 1 0 1 1 0 1 0 X X X 5A0000h to 5AFFFFh 2D0000h to 2D7FFFh
SA98 1 0 1 1 0 1 1 X X X 5B0000h to 5BFFFFh 2D8000h to 2DFFFFh
SA99 1 0 1 1 1 0 0 X X X 5C0000h to 5CFFFFh 2E0000h to 2E7FFFh
SA100 1 0 1 1 1 0 1 X X X 5D0000h to 5DFFFFh 2E8000h to 2EFFFFh
SA101 1 0 1 1 1 1 0 X X X 5E0000h to 5EFFFFh 2F0000h to 2F7FFFh
SA102 1 0 1 1 1 1 1 X X X 5F0000h to 5FFFFFh 2F8000h to 2FFFFFh
SA103 1 1 0 0 0 0 0 X X X 600000h to 60FFFFh 300000h to 307FFFh
SA104 1 1 0 0 0 0 1 X X X 610000h to 61FFFFh 308000h to 30FFFFh
SA105 1 1 0 0 0 1 0 X X X 620000h to 62FFFFh 310000h to 317FFFh
SA106 1 1 0 0 0 1 1 X X X 630000h to 63FFFFh 318000h to 31FFFFh
SA107 1 1 0 0 1 0 0 X X X 640000h to 64FFFFh 320000h to 327FFFh
SA108 1 1 0 0 1 0 1 X X X 650000h to 65FFFFh 328000h to 32FFFFh
SA109 1 1 0 0 1 1 0 X X X 660000h to 66FFFFh 330000h to 337FFFh
SA110 1 1 0 0 1 1 1 X X X 670000h to 67FFFFh 338000h to 33FFFFh
SA111 1 1 0 1 0 0 0 X X X 680000h to 68FFFFh 340000h to 347FFFh
SA112 1 1 0 1 0 0 1 X X X 690000h to 69FFFFh 348000h to 34FFFFh
SA113 1 1 0 1 0 1 0 X X X 6A0000h to 6AFFFFh 350000h to 357FFFh
SA114 1 1 0 1 0 1 1 X X X 6B0000h to 6BFFFFh 358000h to 35FFFFh
SA115 1 1 0 1 1 0 0 X X X 6C0000h to 6CFFFFh 360000h to 367FFFh
SA116 1 1 0 1 1 0 1 X X X 6D0000h to 6DFFFFh 368000h to 36FFFFh
SA117 1 1 0 1 1 1 0 X X X 6E0000h to 6EFFFFh 370000h to 377FFFh
SA118 1 1 0 1 1 1 1 X X X 6F0000h to 6FFFFFh 378000h to 37FFFFh
MB84VD23280EA-90/MB84VD23280EE-90
13
(Continued)
Bank Sector Sector Address Address Range
Bank Address Byte Mode Word Mode
A21 A20 A19 A18 A17 A16 A15 A14 A13 A12
Bank D
SA119 1 1 1 0 0 0 0 X X X 700000h to 70FFFFh 380000h to 387FFFh
SA120 1 1 1 0 0 0 1 X X X 710000h to 71FFFFh 388000h to 38FFFFh
SA121 1 1 1 0 0 1 0 X X X 720000h to 72FFFFh 390000h to 397FFFh
SA122 1 1 1 0 0 1 1 X X X 730000h to 73FFFFh 398000h to 39FFFFh
SA123 1 1 1 0 1 0 0 X X X 740000h to 74FFFFh 3A0000h to 3A7FFFh
SA124 1 1 1 0 1 0 1 X X X 750000h to 75FFFFh 3A8000h to 3AFFFFh
SA125 1 1 1 0 1 1 0 X X X 760000h to 76FFFFh 3B0000h to 3B7FFFh
SA126 1 1 1 0 1 1 1 X X X 770000h to 77FFFFh 3B8000h to 3BFFFFh
SA127 1 1 1 1 0 0 0 X X X 780000h to 78FFFFh 3C0000h to 3C7FFFh
SA128 1 1 1 1 0 0 1 X X X 790000h to 79FFFFh 3C8000h to 3CFFFFh
SA129 1 1 1 1 0 1 0 X X X 7A0000h to 7AFFFFh 3D0000h to 3D7FFFh
SA130 1 1 1 1 0 1 1 X X X 7B0000h to 7BFFFFh 3D8000h to 3DFFFFh
SA131 1 1 1 1 1 0 0 X X X 7C0000h to 7CFFFFh 3E0000h to 3E7FFFh
SA132 1 1 1 1 1 0 1 X X X 7D0000h to 7DFFFFh 3E8000h to 3EFFFFh
SA133 1 1 1 1 1 1 0 X X X 7E0000h to 7EFFFFh 3F0000h to 3F7FFFh
SA134 1 1 1 1 1 1 1 0 0 0 7F0000h to 7F1FFFh 3F8000h to 3F8FFFh
SA135 1 1 1 1 1 1 1 0 0 1 7F2000h to 7F3FFFh 3F9000h to 3F9FFFh
SA136 1 1 1 1 1 1 1 0 1 0 7F4000h to 7F5FFFh 3FA000h to 3FAFFFh
SA137 1 1 1 1 1 1 1 0 1 1 7F6000h to 7F7FFFh 3FB000h to 3FBFFFh
SA138 1 1 1 1 1 1 1 1 0 0 7F8000h to 7F9FFFh 3FC000h to 3FCFFFh
SA139 1 1 1 1 1 1 1 1 0 1 7FA000h to 7FBFFFh 3FD000h to 3FDFFFh
SA140 1 1 1 1 1 1 1 1 1 0 7FC000h to 7FDFFFh 3FE000h to 3FEFFFh
SA141 1 1 1 1 1 1 1 1 1 1 7FE000h to 7FFFFFh 3FF000h to 3FFFFFh
MB84VD23280EA-90/MB84VD23280EE-90
14
Table 4 Sector Group Address (MB84VD23280EA/EE)
Sector Group A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 Sectors
SGA0 0000000000 SA0
SGA1 0000000001 SA1
SGA2 0000000010 SA2
SGA3 0000000011 SA3
SGA4 0000000100 SA4
SGA5 0000000101 SA5
SGA6 0000000110 SA6
SGA7 0000000111 SA7
SGA8 0000000XXX SA8 to SA1001
10
SGA9 00001XXXXXSA11 to SA14
SGA10 00010XXXXXSA15 to SA18
SGA11 00011XXXXXSA19 to SA22
SGA12 00100XXXXXSA23 to SA26
SGA13 00101XXXXXSA27 to SA30
SGA14 00110XXXXXSA31 to SA34
SGA15 00111XXXXXSA35 to SA38
SGA16 01000XXXXXSA39 to SA42
SGA17 01001XXXXXSA43 to SA46
SGA18 01010XXXXXSA47 to SA50
SGA19 01011XXXXXSA51 to SA54
SGA20 01100XXXXXSA55 to SA58
SGA21 01101XXXXXSA59 to SA62
SGA22 01110XXXXXSA63 to SA66
SGA23 01111XXXXXSA67 to SA70
SGA24 10000XXXXXSA71 to SA74
SGA25 10001XXXXXSA75 to SA78
SGA26 10010XXXXXSA79 to SA82
SGA27 10011XXXXXSA83 to SA86
SGA28 10100XXXXXSA87 to SA90
SGA29 10101XXXXXSA91 to SA94
SGA30 10110XXXXXSA95 to SA98
SGA31 10111XXXXX
SA99 to SA102
SGA32 11000XXXXX
SA103 to SA106
SGA33 11001XXXXX
SA107 to SA110
SGA34 11010XXXXX
SA111 to SA114
SGA35 11011XXXXX
SA115 to SA118
SGA36 11100XXXXX
SA119 to SA122
SGA37 11101XXXXX
SA123 to SA126
SGA38 11110XXXXX
SA127 to SA130
SGA39 1111100XXX
SA131 to SA13301
10
SGA40 1111111000 SA134
SGA41 1111111001 SA135
SGA42 1111111010 SA136
SGA43 1111111011 SA137
SGA44 1111111100 SA138
SGA45 1111111101 SA139
SGA46 1111111110 SA140
SGA47 1111111111 SA141
MB84VD23280EA-90/MB84VD23280EE-90
15
Table 5 Flash Memory Autoselect Codes
*1 : A-1 is for Byte mode.
*2 : Outputs 01h at protected sector group addresses and outputs 00h at unprotected sector group addresses.
*3 : When VID is applied, both Bank 1 and Bank 2 become Autoselect mode, which leads to the simultaneous operation
unable to be executed. Consequently, specifying the bank address is not demanded. However, the bank address
needs to be indicated when Autoselect mode is read out at command mode; because then it becomes OK to
activate simultaneous operation.
*4 : At WORD mode, a read cycle at address (BA) 01h (at BYTE mode, (BA) 02h) outputs device code. When 227Eh
(at BYTE mode, 7Eh) was output, this indicates that there will require two additional codes, called Extended
De vice Codes. Theref ore the system ma y continue reading out these Extended De vice Codes at the address of
(BA) 0Eh (at BYTE mode, (BA) 1Ch) , as well as at (BA) 0Fh (at BYTE mode, (BA) 1Eh) .
Type A21 to A12 A6A3A2A1A0A-1*1Code (HEX)
Manufacture’s Code BA*3VIL VIL VIL VIL VIL VIL 04h
Device Code Byte BA*3VIL VIL VIL VIL VIH VIL 7Eh
Word X 227Eh
Extended Device
Code *4
Byte BA*3VIL VIH VIH VIH VIL VIL 02h
Word X 2202h
Byte BA*3VIL VIH VIH VIH VIH VIL 01h
Word X 2201h
Sector Group Protection Sector Group
Addresses VIL VIL VIL VIH VIL VIL 01h*2
MB84VD23280EA-90/MB84VD23280EE-90
16
Table 6 Flash Memory Command Definitions
(Continued)
Command
Sequence
Bus
Write
Cycles
Req’d
First Bus
Write Cycle Second Bus
Write Cycle Third Bus
Write Cycle Fourth Bus
Read/Write
Cycle Fifth Bus
Write Cycle Sixth Bus
Write Cycle
Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data
Read/Reset Word 1 XXXh F0h ——————————
Byte
Read/Reset Word 3555h AAh 2AAh 55h 555h F0hRARD————
Byte AAAh 555h AAAh
Autoselect Word 3555h AAh 2AAh 55h
(BA)
555h 90h——————
Byte AAAh 555h (BA)
AAAh
Program Word 4555h AAh 2AAh 55h 555h A0hPAPD————
Byte AAAh 555h AAAh
Program Suspend 1 BAB0h——————————
Program Resume 1 BA30h——————————
Chip Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h 555h 10h
Byte AAAh 555h AAAh AAAh 555h AAAh
Sector Erase Word 6555h AAh 2AAh 55h 555h 80h 555h AAh 2AAh 55h SA 30h
Byte AAAh 555h AAAh AAAh 555h
Erase Suspend 1 BAB0h——————————
Erase Resume 1 BA30h——————————
Extended
Sector Group
Protection *2
Word 4 XXXh 60h SPA 60h SPA 40h SPA SD ————
Byte
Set to
Fast Mode Word 3555h AAh 2AAh 55h 555h 20h——————
Byte AAAh 555h AAAh
Fast
Program *1Word 2XXXh A0hPAPD————————
Byte XXXh
Reset from
Fast Mode *1Word 2BA 90h XXXh *4
F0h ————————
Byte BA XXXh
Query Word 1
(BA)
55h 98h——————————
Byte (BA)
AAh
Hi-ROM
Entry Word 3555h AAh 2AAh 55h 555h 88h——————
Byte AAAh 555h AAAh
Hi-ROM
Program *3Word 4555h AAh 2AAh 55h 555h A0h (HRA)
PA PD————
Byte AAAh 555h AAAh
Hi-ROM
Exit *3
Word 4555h AAh 2AAh 55h
(HRBA)
555h 90hXXXh00h————
Byte AAAh 555h (HRBA)
AAAh
MB84VD23280EA-90/MB84VD23280EE-90
17
(Continued)
*1:This command is valid while Fast Mode.
*2:This command is valid while RESET = VID.
*3:This command is valid while Hi-ROM mode.
*4:The data “00h” is also acceptable.
Notes: 1. Address bits A21 to A11 = X = “H” or “L” for all address commands except or Program Address (PA),
Sector Address (SA), and Bank Address (BA), and Sector Group Address (SPA).
2. Bus operations are defined in Tables 3 and 4.
3. RA =Address of the memory location to be read
PA = Address of the memory location to be programmed
Addresses are latched on the falling edge of the write pulse.
SA = Address of the sector to be erased. The combination of A21, A20, A19, A18, A17, A16, A15, A14, A13, and
A12 will uniquely select any sector.
BA = Bank Address (A21, A20, A19)
4. RD = Data read from location RA during read operation.
PD = Data to be programmed at location PA. Data is latched on the falling edge of write pulse.
5. SP A =Sector group address to be protected. Set sector group address and (A6, A3, A2, A1, A0) = (0, 0, 0, 1, 0).
SD = Sector group protection verify data. Output 01h at protected sector group addresses and output
00h at unprotected sector group addresses.
6. HRA = Address of the Hi-ROM area Word Mode:000000h to 00007Fh
Byte Mode:000000h to 0000FFh
7. HRBA = Bank Address of the Hi-ROM area (A21 = A20 = A19 = VIL)
8. The system should generate the following address patterns:
Word Mode: 555h or 2AAh to addresses A10 to A0
Byte Mode: AAAh or 555h to addresses A10 to A0, and A-1
9. Both Read/Reset commands are functionally equivalent, resetting the device to the read mode.
MB84VD23280EA-90/MB84VD23280EE-90
18
■
■■
■ABSOLUTE MAXIMUM RATINGS
*1 Minimum DC v oltage on input or I/O pins is –0.3 V. During v oltage transitions, input or I/O pins may undershoot
VSS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCCf + 0.3 V or VCCs + 0.3
V. During voltage transitions , input or I/O pins ma y o v ershoot to VCCf + 2.0 V or VCCs + 2.0 V f or periods of up to
20 ns.
*2: Minimum DC input v oltage on RESET pin is –0.5 V. During voltage tr ansitions, RESET pin ma y undershoot VSS
to –2.0 V for periods of up to 20 ns.
Voltage difference between input and supply voltage (VIN-VCCf or VCCs) does not exceed +9.0 V.
Maximum DC input v oltage on RESET pin is +13.0 V which ma y ov ershoot to +14.0 V f or periods of up to 20 ns.
*3:Minimum DC input voltage on WP/ACC pin is –0.5 V. During voltage transitions, WP/ACC pin may undershoot
Vss to –2.0 V for periods of up to 20 ns. Maximum DC input voltage on WP/ACC pin is +10.5 V which may
overshoot to +12.0 V for periods of up to 20 ns, when VCCf is applied.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
■
■■
■RECOMMENDED OPERATING CONDITIONS
Note: Operating ranges define those limits between which the functionality of the device is guaranteed.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Rating Unit
Min. Max.
Storage Temperature Tstg –55 +125 °C
Ambient Temperature with Power Applied Ta –25 +85 °C
Voltage with Respect to Ground All pins
except RESET and WP/ACC *1VIN, VOUT –0.3 VCCf +0.3 V
VCCs +0.3 V
VCCf/VCCs Supply *1VCCf, VCCs –0.3 +4.0 V
RESET *2VIN –0.5 + 13.0 V
WP/ACC *3VIN –0.5 +10.5 V
Parameter Symbol Value Unit
Min. Max.
Ambient Temperature Ta –25 +85 °C
VCCf/VCCs Supply Voltages VCCf, VCCs +2.7 +3.3 V
MB84VD23280EA-90/MB84VD23280EE-90
19
■
■■
■ELECTRICAL CHARACTERRISTICS
1. DC Characteristics
(Continued)
Parameter Symbol Conditions Value Unit
Min. Typ. Max.
Input Leakage Current ILI VIN = VSS to VCCf, VCCs –1.0 — +1.0 µA
Output Leakage Current ILO VOUT = VSS to VCCf, VCCs –1.0 — +1.0 µA
RESET Inputs Leakage
Current ILIT VCCf = VCCf Max., RESET = 12.5 V — — 35 µA
ACC Input Leakage Current ILIA VCCf = VCCf Max., WP/ACC = VACC Max. — — 20 mA
Flash VCC Active Current
(Read) *1ICC1fCEf = VIL,
OE = VIH
tCYCLE = 5 MHz Byte — — 16 mA
tCYCLE = 5 MHz Word — — 18
tCYCLE = 1 MHz Byte — — 7 mA
tCYCLE = 1 MHz Word — — 7
Flash VCC Active Current
(Program/Erase) *2ICC2fCEf = VIL, OE = VIH ——35mA
Flash VCC Active Current
(Read-While-Program) *5ICC3fCEf = VIL, OE = VIH Byte — — 51 mA
Word — — 53
Flash VCC Active Current
(Read-While-Erase) *5ICC4fCEf = VIL, OE = VIH Byte — — 51 mA
Word — — 53
Flash VCC Active Current
(Erase-Suspend-Program) ICC5fCEf = VIL, OE = VIH ——35mA
SRAM VCC Active Current ICC1sVCCs = VCCs Max.,
CE1s = VIL,
CE2s = VIH tCYCLE =10 MHz — — 50 mA
SRAM VCC Active Current ICC2sCE1s = 0.2 V,
CE2s = VCCs –
0.2 V
tCYCLE = 10 MHz — — 50 mA
tCYCLE = 1 MHz — — 10 mA
Flash VCC Standby Current ISB1fVCCf = VCCf Max., CEf = VCCf ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V ——5µA
Flash VCC Standby Current
(RESET)ISB2fVCCf = VCCf Max., RESET = VSS ± 0.3 V,
WP/ACC = VCCf± 0.3 V ——5µA
Flash VCC Current (Auto-
matic Sleep Mode) *3ISB3f
VCCf = VCCf Max., CEf = VSS ± 0.3 V
RESET = VCCf ± 0.3 V,
WP/ACC = VCCf± 0.3 V,
VIN = VCCf± 0.3 V or VSS ± 0.3 V
——5µA
SRAM VCC Standby
Current ISB1sCE1s > VCCs – 0.2 V, CE2s > VCCs – 0.2 V — — 15 µA
SRAM VCC Standby
Current ISB2sCE2s < 0.2V — — 15 µA
MB84VD23280EA-90/MB84VD23280EE-90
20
(Continued)
*1:The ICC current listed includes both the DC operating current and the frequency dependent component.
*2:ICC activ e while Embedded Algorithm (program or erase) is in progress.
*3:Automatic sleep mode enables the low power mode when address remains stable for 150 ns.
*4:Applicable for only VCCf applying.
*5:Embedded Algorithm (program or erase) is in progress. (@5 MHz)
*6: VCC indicates low e r of VCCf or VCCs.
Parameter Symbol Conditions Value Unit
Min. Typ. Max.
Input Low Level VIL —–0.3—0.5V
Input High Level VIH —2.4—
VCC+0.3 *6V
Voltage for Sector Protection,
and Temporary Sector Unpro-
tection (RESET) *4VID — 11.5 — 12.5 V
Voltage for Program
Acceleration (WP/ACC) *4VACC — 8.5 9.0 9.5 V
Output Low Voltage Level VOL VCCf = VCCf Min., IOL=4.0 mA Flash — — 0.45 V
VCCs = VCCs Min., IOL=1.0 mA SRAM — — 0.4 V
Output High Voltage Level VOH VCCf = VCCf Min., IOH=–0.1 mA Flash VCCf–
0.4 ——V
VCCs = VCCs Min., IOH=–0.5 mA SRAM 2.2 — — V
Flash Low VCCf Lock-Out
Voltage VLKO — 2.3 — 2.5 V
MB84VD23280EA-90/MB84VD23280EE-90
21
2. AC Characteristics
•CE Timing
• Timing Diagram for alternating SRAM to Flash
Parameter Symbol Condition Value Unit
JEDEC Standard Min. Max.
CE Recover Time — tCCR —0—ns
CE Hold Time — tCHOLD —3—ns
CEf
tCCR tCCR
CE1s
CE2s tCCR tCCR
WE
tCHOLD tCHOLD
MB84VD23280EA-90/MB84VD23280EE-90
22
• Read Only Operations Characteristics (Flash)
Note: Test Conditions– Output Load:1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCf
Timing measurement reference level
Input: 0.5×VCCf
Output: 0.5×VCCf
Parameter Symbol Condition Value (Note) Unit
JEDEC Standard Min. Max.
Read Cycle Time tAVAV tRC —90—ns
Address to Output Delay tAVQV tACC CEf = VIL
OE = VIL —90ns
Chip Enable to Output Delay tELQV tCEfOE = VIL —90ns
Output Enable to Output Delay tGLQV tOE ——35ns
Chip Enable to Output High-Z tEHQZ tDF ——30ns
Output Enable to Output High-Z tGHQZ tDF ——30ns
Output Hold Time From Addresses,
CEf or OE, Whichever Occurs First tAXQX tOH —0—ns
RESET Pin Low to Read Mode — tREADY ——20µs
MB84VD23280EA-90/MB84VD23280EE-90
23
• Read Cycle (Flash)
WE
OE
CEf
tCEf
tOE
DQ
Address Stable
High-Z Output Valid High-Z
tOEH
tACC
tRC
RESET
tACC
tOH
DQ
tRC
Address Stable
High-Z Output Valid
tRH
tDF
Address
Address
tRH
tCEf
tRP
CEf
MB84VD23280EA-90/MB84VD23280EE-90
24
• Erase/Program Operations (Flash)
*1:This does not include the preprogramming time.
*2:This timing is for Sector group Protection Operation.
*3:The time between writes must be less than “tTOW” otherwise that command will not be accepted and erasure will
start. A time-out or “tTOW” from the rising edge of last CEf or WE whichever happens first will initiate the execution
of the Sector Erase command(s).
*4:When the Erase Suspend command is written during the Sector Erase operation, the device will take a maximum
of “tSPD” to suspend the erase operation.
Parameter Symbol Value Unit
JEDEC Standard Min. Typ. Max.
Write Cycle Time tAVAV tWC 90 — — ns
Address Setup Time (WE to Addr.) tAVWL tAS 0——ns
Address Setup Time to CEf Low During Toggle Bit Polling —tASO 15 — — ns
Address Hold Time (WE to Addr.) tWLAX tAH 45 — — ns
Address Hold Time from CEf or OE High During Toggle Bit Polling —tAHT 0——ns
Data Setup Time tDVWH tDS 35 — — ns
Data Hold Time tWHDX tDH 0——ns
Output Enable Hold Time Read —t
OEH 0——ns
Toggle and Data Polling 10 — — ns
CEf High During Toggle Bit Polling —t
CEPH 20 — — ns
OE High During Toggle Bit Polling — tOEPH 20 — — ns
Read Recover Time Before Write (OE to CEf) tGHEL tGHEL 0——ns
Read Recover Time Before Write (OE to WE)tGHWL tGHWL 0——ns
WE Setup Time (CEf to WE)tWLEL tWS 0——ns
CEf Setup Time (WE to CEf) tELWL tCS 0——ns
WE Hold Time (CEf to WE)tEHWH tWH 0——ns
CEf Hold Time (WE to CEf) tWHEH tCH 0——ns
Write Pulse Width tWLWH tWP 35 — — ns
CEf Pulse Width tELEH tCP 35 — — ns
Write Pulse Width High tWHWL tWPH 30 — — ns
CEf Pulse Width High tEHEL tCPH 30 — — ns
Word Programming Operation tWHWH1 tWHWH1 —16—µs
Sector Erase Operation *1tWHWH2 tWHWH2 —1—s
VCCf Setup Time — tVCS 50 — — µs
Voltage Transition Time *2—tVLHT 4——µs
Rise Time to VID *2—tVIDR 500 — — ns
Rise Time to VACC —tVACCR 500 — — ns
Recover Time from RY/BY —tRB 0——ns
RESET Pulse Width — tRP 500 — — ns
Delay Time from Embedded Output Enable — tEOE — — 90 ns
RESET High Level Period Before Read — tRH 200 — — ns
Program/Erase Valid to RY/BY Delay — tBUSY — — 90 ns
Erase Time-out Time *3—tTOW 50 — — µs
Erase Suspend Transition Time *4—tSPD — — 20 µs
MB84VD23280EA-90/MB84VD23280EE-90
25
• Write Cycle (WE control) (Flash)
tCH
tWP tWHWH1
tWC tAH
CEf
OE
tRC
DQ
tAS
tOE
tWPH
tGHWL
tDH
DQ7
PD
A0h DOUT
WE
555h PA PA
tOH
Data Polling3rd Bus Cycle
tCS tCEf
tDS
DOUT
Address
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
MB84VD23280EA-90/MB84VD23280EE-90
26
• Write Cycle (CEf control) (Flash)
Notes: 1. PA is address of the memory location to be programmed.
2. PD is data to be programmed at byte address.
3. DQ7 is the output of the complement of the data written to the device.
4. DOUT is the output of the data written to the device.
5. Figure indicates last two bus cycles out of four bus cycle sequence.
6. These waveforms are for the ×16 mode. (The addresses differ from ×8 mode.)
tCP
tDS
tWHWH1
tWC tAH
WE
OE
DQ
tAS
tCPH
tDH
DQ7
A0h DOUT
CEf
555h PA PA
Data Polling3rd Bus Cycle
tWS tWH
tGHEL
PD
Address
MB84VD23280EA-90/MB84VD23280EE-90
27
• AC Waveforms Chip/Sector Erase Operations (Flash)
Address
VCCf
CEf
OE
DQ
WE
555h 2AAh 555h
555h 2AAh SA*
tDS
tCH
tAS tAH
tCS
tWPH
tDH
tGHWL
tVCS
tWC
tWP
AAh 55h 80h AAh 55h 10h/
30h for Sector Erase
30h
*: SA is the sector address for Sector Erase. Address = 555h for Chip Erase.
Note: These waveforms are for the ×
××
×16 mode. (The addresses differ from ×
××
×8
mode.)
MB84VD23280EA-90/MB84VD23280EE-90
28
• AC Waveforms for Data Polling during Embedded Algorithm Operations (Flash)
*: DQ7 = Valid Data (The device has completed the Embedded operation.)
tOEH
tOE
CEf
OE
WE
DQ7
tDF
tCH
tCEf
DQ7 =
Valid Data
DQ7
*
DQ6 to DQ0 = Output Flag
tEOE
DQ6 to DQ0
Valid Data
High-Z
High-Z
DQ6 to DQ0
Data In
Data In
tBUSY
RY/BY
tWHWH1 or tWHWH2
MB84VD23280EA-90/MB84VD23280EE-90
29
• AC Waveforms for Toggle Bit during Embedded Algorithm Operations (Flash)
*: DQ6 stops toggling (The device has completed the Embedded operation).
Address
RY/BY
CEf
WE
DQ6/DQ2
OE
tAS
tBUSY
Toggle
tAHTtAHT tASO
tOEH tOEH
tOE
Data Toggle
Data Toggle
Data Stop
Toggling
Data
tCEf*
Output
Valid
tDH
tCEPH
tOEPH
MB84VD23280EA-90/MB84VD23280EE-90
30
• Back-to-back Read/Write Timing Diagram (Flash)
CEf
DQ
WE
Address BA1 BA1 BA1
BA2
(555h) BA2
(PA) BA2
(PA)
OE
Valid
Output Valid
Output Valid
Output Status
Valid
Intput Valid
Intput
tRC tRC tRC tRCtWC tWC
tAHT tAS
tAS tAH tACC
tCEf
tOE
tOEH
tWP
tGHWL
tDS tDF
tDH
tDF
tCEPH
Read Command CommandRead Read Read
(A0h) (PD)
Note: This is an example of Read f or Bank 1 and Embedded Algorithm (program) f or Bank 2.
BA1: Address of Bank 1.
BA2: Address of Bank 2.
MB84VD23280EA-90/MB84VD23280EE-90
31
•RY/BY
Timing Diagram during Write/Erase Operations (Flash)
• RESET, RY/BY Timing Diagram (Flash)
The rising edge of the last write pulse
CEf
RY/BY
WE
tBUSY
Entire programming
or erase operations
tRP
RESET
tREADY
RY/BY
WE
tRB
MB84VD23280EA-90/MB84VD23280EE-90
32
• Temporary Sector Unprotection (Flash)
• Acceleration Mode Timing Diagram (Flash)
VCCf
VID
RESET
VIH
CEf
WE
RY/BY Program or Erase Command Sequence
tVIDR tVLHT
tVCS
tVLHT tVLHT
Unprotection Period
3V
VCCf
VACC
WP/ACC
VCC
CEf
WE
RY/BY
tVACCR tVLHT
tVCS
tVLHT tVLHT
Acceleration Mode Period
MB84VD23280EA-90/MB84VD23280EE-90
33
• Extended Sector Group Protection (Flash)
SPAX: Sector Group Address to be protected
SPAY : Next Group Sector Address to be protected
TIME-OUT : Time-Out window = 250 µs (Min.)
SPAY
RESET
OE
WE
CEf
Data
A1
VCCf
A6, A3, A2, A0
Address SPAXSPAX
60h
01h
40h
60h
60h
TIME-OUT
tVCS
tVLHT
tVIDR
tOE
tWP
tWC tWC
MB84VD23280EA-90/MB84VD23280EE-90
34
•Read Cycle (SRAM)
Note: Test conditions: Output Load: 1 TTL gate and 30 pF
Input rise and fall times: 5 ns
Input pulse levels: 0.0 V to VCCs
Timing measurement reference level
Input: 0.5 × VCCs
Output: 0.5 × VCCs
Parameter Symbol Value Unit
Min. Max.
Read Cycle Time tRC 70 — ns
Address Access Time tAA —70ns
Chip Enable (CE1s) Access Time tCO1 —70ns
Chip Enable (CE2s) Access Time tCO2 —70ns
Output Enable Access Time tOE —35ns
LBs, UBs to Output Valid tBA —70ns
Chip Enable (CE1s Low and CE2s High) to Output Active tCOE 5—ns
Output Enable Low to Output Active tOEE 0—ns
UBs, LBs Enable Low to Output Active tBE 0—ns
Chip Enable (CE1s High or CE2s Low) to Output High-Z tOD —25ns
Output Enable High to Output High-Z tODO —25ns
UBs, LBs Output Enable to Output High-Z tBD —25ns
Output Data Hold Time tOH 10 — ns
MB84VD23280EA-90/MB84VD23280EE-90
35
•Read Cycle (SRAM)
tRC
tAA tOH
tCO1
tOD
tODO
tOEE
tCOE
Valid Data Out
Address
CE1s
OE
DQ
CE2s
tCOE
tOE
tCO2
tOD
LBs, UBs
tBA tBD
tBE
Note: WE remains “H” for the read cycle.
MB84VD23280EA-90/MB84VD23280EE-90
36
• Write Cycle (SRAM)
Parameter Symbol Value Unit
Min. Max.
Write Cycle Time tWC 70 — ns
Write Pulse Width tWP 55 — ns
Chip Enable to End of Write tCW 60 — ns
Address valid to End of Write tAW 60 — ns
UBs, LBs to End of Write tBW 60 — ns
Address Setup Time tAS 0—ns
Write Recovery Time tWR 0—ns
WE Low to Output High-Z tODW —25ns
WE High to Output Active tOEW 0—ns
Data Setup Time tDS 30 — ns
Data Hold Time tDH 0—ns
MB84VD23280EA-90/MB84VD23280EE-90
37
• Write Cycle (Note 3) (WE control) (SRAM)
tWC
tAS tWP tWR
tCW
tODW tOEW
tDS tDH
Valid Data In
Address
WE
CE1s
DOUT
DIN
CE2s tCW
Notes: 1. If CE1s goes “L” (or CE2s goes “H”) coincident with or after WE goes “L”, the output
will remain at High-Z.
2. If CE1s goes “H” (or CE2s goes “L”) coincident with or before WE goes “H”, the output
will remain at High-Z.
3. If OE is “H” during the write cycle, the outputs will remain at High-Z.
4. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
Note 1
Note 4
Note 2
Note 4
tBW
LBs, UBs
tAW
MB84VD23280EA-90/MB84VD23280EE-90
38
• Write Cycle (Note 1) (CE1s control) (SRAM)
tWC
tAS tWP tWR
tCW
tODW
tCOE
tDS tDH
Valid Data In
Address
WE
CE1s
DOUT
DIN
CE2s tCW
Notes: 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
Note 2
LBs, UBs
tBW
tBE
tAW
MB84VD23280EA-90/MB84VD23280EE-90
39
• Write Cycle (Note 1) (CE2s Control) (SRAM)
tWC
tAS tWP tWR
tCW
tODW
tCOE
tDS tDH
Valid Data In
Address
WE
CE1s
DOUT
DIN
CE2s
Notes: 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
Note 2
tCW
LBs, UBs
tBW
tBE
tAW
MB84VD23280EA-90/MB84VD23280EE-90
40
• Write Cycle (Note 1) (LBs, UBs Control) (SRAM)
tWC
tDS tDH
Address
LBs, UBs
WE
DIN
Notes: 1. If OE is “H” during the write cycle, the outputs will remain at High-Z.
2. Because I/O signals may be in the output state at this Time, input signals of reverse
polarity must not be applied.
tWP
CE2s
tCW
CE1s
tAS
tWR
tBW
tODW
tCOE
DOUT
tBE
Valid Data In
Note 2
tCW
tAW
MB84VD23280EA-90/MB84VD23280EE-90
41
■
■■
■ERASE AND PROGRAMMING PERFORMANCE (Flash)
■DATA RETENTION CHARACTERISTICS (SRAM)
Note tRC: Read cycle time
•CE1
s Controlled Data Retention Mode (Note 1)
Parameter Value Unit Remarks
Min. Typ. Max.
Sector Erase Time — 1 10 s Excludes programming time
prior to erasure
Byte Programming Time — 8 300 µsExcludes system-level
overhead
Word Programming Time — 16 360 µsExcludes system-level
overhead
Chip Progra mming Time — — 200 s Excludes system-level
overhead
Erase/Program Cycle 100,000 — — cycle
Parameter Symbol Value Unit
Min. Typ. Max.
Data Retention Supply Voltage VDH 1.5 — 3.3 V
Standby Current VDH = 3.0 V IDDS2 —1 6µA
Chip Deselect to Data Retention Mode Time tCDR 0——ns
Recovery Time tRtRC ——ns
VCCs
2.7 V
VIH
GND
Data Retention Mode
See Note 2
tCDR
CE1sVCCS – 0.2 V
See Note 2
tR
VDH
MB84VD23280EA-90/MB84VD23280EE-90
42
• CE2s Controlled Data Retention Mode (Note 3)
Notes: 1. In CE1s controlled data retention mode, input level of CE2s should be fixed Vccs to Vccs–0.2 V or Vss
to 0.2 V during data retention mode. Other input and input/output pins can be used between –0.3 V to
Vccs+0.3 V.
2. When CE1s is operating at the VIH Min. level, the standby current is given by ISB1s during the transition
of VCCs from 3.3V to VIH Min. level.
3. In CE2s controlled data retention mode, input and input/output pins can be used between
–0.3 V to Vccs+0.3V.
■
■■
■PIN CAPACITANCE
Note: Test conditions Ta = 25°C, f = 1.0 MHz
■HANDLING OF PACKAGE
Please handle this package carefully since the sides of packages are right angle.
■CAUTION
1) The high voltage (VID) can not apply to address pins and control pins except RESET. Therefore, it can not
use autoselect and sector protect function by applying the high voltage (VID) to specific pins.
2) For the sector protection, since the high voltage (VID) can be applied to the RESET, it can be protected
the sector useing “Extended sector protect” command.
Parameter Symbol Condition Value Unit
Min. Typ. Max.
Input Capacitance CIN VIN = 0 11 14 pF
Output Capacitance COUT VOUT = 0 12 16 pF
Control Pin Capacitance CIN2 VIN = 0 14 16 pF
WP/ACC Pin Capacitance CIN3 VIN = 0 21.5 26 pF
VCCs
2.7 V
GND
Data Retention Mode
VIH
VIL
CE2s
tCDR tR
0.2 V
VDH
MB84VD23280EA-90/MB84VD23280EE-90
43
■
■■
■ORDERING INFORMATION
MB84VD23280 EA -90 -PBS
DEVICE NUMBER/DESCRIPTION
64Mega-bit (8M × 16-bit or 4M × 16-bit) Dual Operation Flash Memory
3.0V-only Read, Program, and Erase
8Mega-bit(1M × 8-bit or 512K × 16-bit) SRAM
PACKAGE TYPE
PBS = 101-ball BGA
SPEED OPTION
See Product Selector Guide
Device Revision
EA or EE
MB84VD23280EA-90/MB84VD23280EE-90
44
■
■■
■PACKAGE DIMENSION
101-pin plastic FBGA
(BGA-101P-M01)
C
2000 FUJITSU LIMITED B101001S-1c-1
12.00±0.10(.472±.004)
11.00±0.10
(.433±.004)
INDEX-MARK AREA
0.10(.004)
0.39±0.10
(.015±.004) (Stand off)
.049 –.004
+.006
±0.10
+0.15
1.25 (Mounting height)
0.80
(.031)
5.60(.220)REF
7.20(.283)
10.40(.409)
0.80
(.031)
5.60(.220)
REF
8.80(.346)
ABCDEFGHJKLMNP
1
2
3
4
5
6
7
8
9
10
11
12
101-Ø.018 –.002
+.004
–0.05
+0.10
101-Ø0.45 M
0.08(.003)
Dimensions in mm (inches).
MB84VD23280EA-90/MB84VD23280EE-90
FUJITSU LIMITED
For further information please contact:
Japan
FUJITSU LIMITED
Corporate Global Business Support Division
Electronic Devices
Shinjuku Dai-Ichi Seimei Bldg. 7-1,
Nishishinjuku 2-chome, Shinjuku-ku,
Tokyo 163-0721, Japan
Tel: +81-3-5322-3347
Fax: +81-3-5322-3386
http://edevice.fujitsu.com/
North and South America
FUJITSU MICROELECTRONICS, INC.
3545 North First Street,
San Jose, CA 95134-1804, U.S.A.
Tel: +1-408-922-9000
Fax: +1-408-922-9179
Customer Response Center
Mon. - Fri.: 7 am - 5 pm (PST)
Tel: +1-800-866-8608
Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe
FUJITSU MICROELECTR ONICS EUR OPE GmbH
Am Siebenstein 6-10,
D-63303 Dreieich-Buchschlag,
Germany
Tel: +49-6103-690-0
Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific
FUJITSU MICROELECTR ONICS ASIA PTE. LTD .
#05-08, 151 Lorong Chuan,
New Tech Park,
Singapore 556741
Tel: +65-281-0770
Fax: +65-281-0220
http://www.fmap.com.sg/
Korea
FUJITSU MICROELECTR ONICS K OREA LTD.
1702 KOSMO TOWER, 1002 Daechi-Dong,
Kangnam-Gu,Seoul 135-280
Korea
Tel: +82-2-3484-7100
Fax: +82-2-3484-7111
F0104
FUJITSU LIMITED Printed in Japan
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information and circuit diagrams in this document are
presented as examples of semiconductor device applications, and
are not intended to be incorporated in devices for actual use. Also,
FUJITSU is unable to assume responsibility for infringement of
any patent rights or other rights of third parties arising from the use
of this information or circuit diagrams.
The products described in this document are designed, and
manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use,
and household use, but are not designed, developed and
manufactured as contemplated (1) for use accompanying fatal risks
or dangers that, unless extremely high safety is secured, could have
a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have inherently a certain rate of failure.
You must protect against injury, damage or loss from such failures
by incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Control Law of Japan, the
prior authorization by Japanese government should be required for
export of those products from Japan.
