REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD8012
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Dual 350 MHz
Low Power Amplifier
FUNCTIONAL BLOCK DIAGRAM
8
7
6
5
1
2
3
4
OUT1
–IN1
+IN1
+VS
OUT2
–IN2
+IN2–VSAD8012
FEATURES
Low Power
1.7 mA/Amplifier Supply Current
Fully Specified for 5 V and +5 V Supplies
High Output Current, 125 mA
High Speed
350 MHz, –3 dB Bandwidth (G = +1)
150 MHz, –3 dB Bandwidth (G = +2)
2,250 V/s Slew Rate
20 ns Settling Time to 0.1%
Low Distortion
–72 dBc Worst Harmonic @ 500 kHz, RL = 100
–66 dBc Worst Harmonic @ 5 MHz, RL = 1 k
Good Video Specifications (RL = 1 k, G = +2)
0.02% Differential Gain Error
0.06 Differential Phase Error
Gain Flatness 0.1 dB to 40 MHz
60 ns Overdrive Recovery
Low Offset Voltage, 1.5 mV
Low Voltage Noise, 2.5 nV/Hz
Available in 8-Lead SOIC and 8-Lead microSOIC
APPLICATIONS
XDSL, HDSL Line Driver
ADC Buffer
Professional Cameras
CCD Imaging System
Ultrasound Equipment
Digital Camera
PRODUCT DESCRIPTION
The AD8012 is a dual low power current feedback amplifier
capable of providing 350 MHz bandwidth while using only
1.7 mA per amplifier. It is intended for use in high frequency,
wide dynamic range systems where low distortion, high speed
are essential and low power is critical.
With only 1.7 mA of supply current, the AD8012 also offers
exceptional ac specs such as 20 ns settling time and 2,250 V/µs
slew rate. The video specifications are 0.02% differential gain
and 0.06 degree differential phase, excellent for such a low power
amplifier. In addition, the AD8012 has a low offset of 1.5 mV.
The AD8012 is well suited for any application that requires high
performance with minimal power.
The product is available in standard 8-lead SOIC or micro-
SOIC packages and operates over the industrial temperature
range –40°C to +85°C.
RLV
–40
–9010 1k100
DISTORTION – dBc
–70
–80
–60
–50
G = +2
VOUT = 2V p-p
RF = 750V
3rd
2nd
Figure 1. Distortion vs. Load Resistance, V
S
=
±
5 V,
Frequency = 500 kHz
AMP 1
VIN VREF
R2
R1
RL = 100V
OR
135V
VOUT
Np:Ns
TRANSFORMER
LINE
POWER
IN dB
+VS
+
–VS
+
Figure 2. Differential Drive Circuit for XDSL Applications
*
*Protected under U.S. Patent Number 5,537,079.
–2 REV. A
AD8012–SPECIFICATIONS
DUAL SUPPLY
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = +1, V
OUT
< 0.4 V p-p, R
L
= 1 k270 350 MHz
G␣ =␣ +2, V
OUT
< 0.4 V p-p, R
L
= 1 k95 150 MHz
G␣ =␣ +2, V
OUT
< 0.4 V p-p, R
L
= 100 90 MHz
0.1 dB Bandwidth V
OUT
< 0.4 V p-p, R
L
= 1 k/100 40/23 MHz
Large Signal Bandwidth V
OUT
= 4 V p-p 75 MHz
Slew Rate V
OUT
= 4 V p-p 2,250 V/µs
Rise and Fall Time V
OUT
= 2 V p-p 3 ns
Settling Time 0.1%, V
OUT
= 2 V p-p 20 ns
0.02%, V
OUT
= 2 V p-p 35 ns
Overdrive Recovery 2× Overdrive 60 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
OUT
= 2 V p-p, G = +2
2nd Harmonic 500 kHz, R
L
= 1 k/100 –89/–73 dBc
5 MHz, R
L
= 1 k/100 –78/–62 dBc
3rd Harmonic 500 kHz, R
L
= 1 k/100 –84/–72 dBc
5 MHz, R
L
= 1 k/100 –66/–52 dBc
Output IP3 500 kHz, f = 10 kHz, R
L
= 1 k/100 30/40 dBm
IMD 500 kHz, f = 10 kHz, R
L
= 1 k/100 –79/–77 dBc
Crosstalk 5 MHz, R
L
= 100 –70 dB
Input Voltage Noise f = 10 kHz 2.5 nV/Hz
Input Current Noise f = 10 kHz,␣ +Input, –Input 15 pA/Hz
Differential Gain f = 3.58 MHz, R
L
= 150 /1 k, G = +2 0.02/0.02 %
Differential Phase f = 3.58 MHz, R
L
= 150 /1 k, G = +2 0.3/0.06 Degrees
DC PERFORMANCE
Input Offset Voltage ±1.5 ±4mV
T
MIN
–T
MAX
±5mV
Open-Loop Transimpedance V
OUT
= ±2 V, R
L
= 100 240 500 k
T
MIN
–T
MAX
200 k
INPUT CHARACTERISTICS
Input Resistance +Input 450 k
Input Capacitance +Input 2.3 pF
Input Bias Current +Input, –Input ±3±12 µA
+Input, –Input, T
MIN
–T
MAX
±15 µA
Common-Mode Rejection Ratio V
CM
= ±2.5 V –56 –60 dB
Input Common-Mode Voltage Range ±3.8 ±4.1 V
OUTPUT CHARACTERISTICS
Output Resistance G = +2 0.1
Output Voltage Swing ±3.85 ±4V
Output Current T
MIN
–T
MAX
70 125 mA
Short Circuit Current 500 mA
POWER SUPPLY
Supply Current/Amp 1.7 1.8 mA
T
MIN
–T
MAX
1.9 mA
Operating Range Dual Supply ±1.5 ±6.0 V
Power Supply Rejection Ratio –58 –60 dB
Specifications subject to change without notice.
(@ TA = +25C, VS = 5 V, G = +2, RL = 100 , RF = RG = 750 , unless otherwise noted)
–3–REV. A
AD8012
(@ TA +25C, VS = +5 V, G = +2, RL = 100 , RF = RG = 750 , unless otherwise noted)
Parameter Conditions Min Typ Max Units
DYNAMIC PERFORMANCE
–3 dB Small Signal Bandwidth G = +1, V
OUT
< 0.4 V p-p, R
L
= 1 k220 300 MHz
G␣ =␣ +2, V
OUT
< 0.4 V p-p, R
L
= 1 k90 140 MHz
G␣ =␣ +2, V
OUT
< 0.4 V p-p, R
L
= 100 85 MHz
0.1 dB Bandwidth V
OUT
< 0.4 V p-p, R
L
= 1 k/100 43/24 MHz
Large Signal Bandwidth V
OUT
= 2 V p-p 60 MHz
Slew Rate V
OUT
= 3 V p-p 1,200 V/µs
Rise and Fall Time V
OUT
= 2 V p-p 2 ns
Settling Time 0.1%, V
OUT
= 2 V p-p 25 ns
0.02%, V
OUT
= 2 V p-p 40 ns
Overdrive Recovery 2× Overdrive 60 ns
NOISE/HARMONIC PERFORMANCE
Distortion V
OUT
= 2 V p-p, G = +2
2nd Harmonic 500 kHz, R
L
= 1 k/100 –87/–71 dBc
5 MHz, R
L
= 1 k/100 –77/–61 dBc
3rd Harmonic 500 kHz, R
L
= 1 k/100 –89/–72 dBc
5 MHz, R
L
= 1 k/100 –78/–52 dBc
Output IP3 500 kHz, R
L
= 1 k/100 30/40 dBm
IMD 500 kHz, R
L
= 1 k/100 –77/–80 dBc
Crosstalk 5 MHz, R
L
= 100 –70 dB
Input Voltage Noise f = 10 kHz 2.5 nV/Hz
Input Current Noise f = 10 kHz,␣ +Input, –Input 15 pA/Hz
Black Level Clamped to +2 V, f = 3.58 MHz
Differential Gain R
L
= 150 /1 k0.03/0.03 %
Differential Phase R
L
= 150 /1 k0.4/0.08 Degrees
DC PERFORMANCE
Input Offset Voltage ±1±3mV
T
MIN
–T
MAX
±4mV
Open-Loop Transimpedance V
OUT
= 2 V p-p, R
L
= 100 200 400 k
T
MIN
–T
MAX
150 k
INPUT CHARACTERISTICS
Input Resistance +Input 450 k
Input Capacitance +Input 2.3 pF
Input Bias Current +Input, –Input ±3±12 µA
+Input, –Input, T
MIN
–T
MAX
±15 µA
Common-Mode Rejection Ratio V
CM
= 1.5 V to 3.5 V –56 –60 dB
Input Common-Mode Voltage Range 1.5 to 3.5 1.2 to 3.8 V
OUTPUT CHARACTERISTICS
Output Resistance G = +2 0.1
Output Voltage Swing 1 to 4 0.9 to 4.2 V
Output Current T
MIN
–T
MAX
50 100 mA
Short Circuit Current 500 mA
POWER SUPPLY
Supply Current/Amp 1.55 1.75 mA
T
MIN
–T
MAX
1.85 mA
Operating Range Single Supply 3 12 V
Power Supply Rejection Ratio –58 –60 dB
Specifications subject to change without notice.
SINGLE SUPPLY
AD8012
–4 REV. A
ABSOLUTE MAXIMUM RATINGS
1
Supply␣ Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6␣ V
Internal␣ Power␣ Dissipation
2
Small␣ Outline␣ Package (R) . . . . . . . . . . . . . . . . . . . . . 0.8␣ W
microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 0.6 W
Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . ±V
S
Differential␣ Input␣ Voltage . . . . . . . . . . . . . . . . . . . . . . ±2.5␣ V
Output Short Circuit Duration
. . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves
Storage Temperature Range RM, R . . . . . . –65°C to +125°C
Operating Temperature Range (A Grade) . . –40°C to +85°C
Lead Temperature Range (Soldering␣ 10␣ sec) . . . . . . . +300°C
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Specification is for device in free air at +25°C
8-Lead SOIC Package: θ
JA
= 155°C/W
8-Lead microSOIC Package: θ
JA
= 200°C/W
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8012
is limited by the associated rise in junction temperature. The maxi-
mum safe junction temperature for plastic encapsulated devices
is determined by the glass transition temperature of the plastic,
approximately +150°C. Temporarily exceeding this limit may
cause a shift in parametric performance due to a change in the
stresses exerted on the die by the package. Exceeding a junction
temperature of +175°C for an extended period can result in de-
vice failure.
The output stage of the AD8012 is designed for maximum load
current capability. As a result, shorting the output to common
can cause the AD8012 to source or sink 500 mA. To ensure
proper operation, it is necessary to observe the maximum power
derating curves. Direct connection of the output to either power
supply rail can destroy the device.
AMBIENT TEMPERATURE – 8C
–50
0
TJ = +1508C
2.0
1.5
1.0
MAXIMUM POWER DISSIPATION – Watts
8-LEAD SOIC
PACKAGE
–40 –30 0 102030405060708090
8-LEAD
microSOIC
0.5
–20 –10
Figure 3. Plot of Maximum Power Dissipation vs.
Temperature for AD8012
␣␣␣␣
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8012 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ORDERING GUIDE
Temperature Package Package Brand
Model Range Description Options Code
AD8012AR –40°C to +85°C 8-Lead SOIC SO-8
AD8012AR-REEL –40°C to +85°C13 Tape and Reel SO-8
AD8012AR-REEL7 –40°C to +85°C7 Tape and Reel SO-8
AD8012ARM –40°C to +85°C 8-Lead microSOIC RM-08 H6A
AD8012ARM-REEL –40°C to +85°C13 Tape and Reel RM-08 H6A
AD8012ARM-REEL7 –40°C to +85°C7 Tape and Reel RM-08 H6A
AD8012
–5–REV. A
0.1mF
0.1mF
10mF
10mF
RL
VIN
VOUT
750V750V
49.9V+VS
–VS
+
+
Figure 4. Test Circuit; Gain = +2
20mV 5ns
Figure 5.* 100 mV Step Response; G = +2, V
S
=
±
2.5 V or
±
5 V, R
L
= 1 k
1V 10ns
Figure 6. 4 V Step Response; G = +2, V
S
=
±
5 V, R
L
= 1 k
*NOTE:␣ V
S
= ±2.5 V operation is identical to V
S
= +5 V single supply operation.
0.1mF
0.1mF
10mF
10mF
RL
VIN VOUT
750V750V
53.6V
+VS
–VS
+
+
Figure 7. Test Circuit; Gain = –1
20mV 5ns
Figure 8.* 100 mV Step Response; G = –1, V
S
=
±
2.5 V or
±
5 V, R
L
= 1 k
1V 10ns
Figure 9. 4 V Step Response; G = –1, V
S
=
±
5 V, R
L
= 1 k
Typical Performance Characteristics–
AD8012
–6 REV. A
20mV 5ns
Figure 10.* 100 mV Step Response; G = +2, V
S
=
±
2.5 V or
±
5 V, R
L
= 100
500mV 10ns
Figure 11. 2 V Step Response; G = +2, V
S
=
±
2.5 V, R
L
= 100
1V 10ns
Figure 12. 4 V Step Response; G = +2, V
S
=
±
5 V, R
L
= 100
*NOTE:␣ V
S
= ±2.5 V operation is identical to V
S
= +5 V single supply operation.
20mV 5ns
Figure 13.* 100 mV Step Response; G = –1, V
S
=
±
2.5 V or
±
5 V, R
L
= 100
500mV 10ns
Figure 14. 2 V Step Response; G = –1, V
S
=
±
2.5 V, R
L
= 100
1V 10ns
Figure 15. 4 V Step Response; G = –1, V
S
=
±
5 V, R
L
= 100
AD8012
–7–REV. A
RLV
–40
–9010 1k100
DISTORTION – dBc
–70
–80
–60
–50
G = +2
VOUT = 2V p-p
RF = 750V
3rd
2nd
Figure 16. Distortion vs. Load Resistance; V
S
=
±
5 V,
Frequency = 500 kHz
3rd
RL = 1kV
FREQUENCY 2 MHz
DISTORTION 2 dBc
110 20
2nd
RL = 1kV
3rd
RL = 100V
2nd
RL = 100V
–40
–60
–80
–100
G = +2
VOUT = 2V p-p
RF = 750V
Figure 17. Distortion vs. Frequency; V
S
=
±
5 V
FREQUENCY 2 MHz
0.1 10 100
G = +2
VO = 0.3V p-p
RF = 750V
RL = 100V
VS = 65V
1
0.3
–0.3
0.2
–0.1
0.1
0
–0.2
–0.4
–0.5
0.4
0.5
NORMALIZED GAIN 2 dB
Figure 18. Gain Flatness; V
S
=
±
5 V
RLV
–40
–9010 1k100
DISTORTION – dBc
–70
–80
–60
–50
G = +2
VOUT = 2V p-p
RF = 750V
2nd
3rd
Figure 19. Distortion vs. Load Resistance; V
S
= +5 V,
Frequency = 500 kHz
–40
–100 10 20
DISTORTION – dBc
–80
–60
G = +2
VOUT = 2V p-p
RF = 750V
FREQUENCY – MHz
1
3rd
RL = 1kV
2nd
RL = 1kV
3rd
RL = 100V
2nd
RL = 100V
Figure 20. Distortion vs. Frequency; V
S
= +5 V
FREQUENCY 2 MHz
0.1 10 100
G = +2
VO = 0.3V p-p
RF = 750V
RL = 100V
VS = +5V
1
0.3
–0.3
0.2
–0.1
0.1
0
–0.2
–0.4
–0.5
0.4
0.5
NORMALIZED GAIN 2 dB
Figure 21. Gain Flatness; V
S
= +5 V
AD8012
–8 REV. A
FREQUENCY 2 MHz
3
–3
100 500
2
–1
VO = 0.3V p-p
RF = 750V
RL = 100V
VS = 65V
1
0
–2
–4
4
5
G = +10
G = +2
G = +1
–5 10
1
NORMALIZED GAIN 2 dB
Figure 22. Frequency Response; V
S
=
±
5 V
FREQUENCY 2 MHz
3
–15
100 500
0
–9
G = +2
RF = 750V
RL = 100V
VS = 65V
–3
–6
–12
–18
6
9
–21 10
1
OUTPUT VOLTAGE 2 dBV
1V RMS
Figure 23. Output Voltage vs. Frequency; V
S
=
±
5 V,
G = +2 V, R
L
= 100
FREQUENCY – MHz
–20
–80
100 500
–30
–60
VIN = 0.2V p-p
VS = 65V, +5V
–40
–50
–70
–90
–10
0
10.03 0.1 10
CMRR 2 dB
–100
Figure 24. CMRR vs. Frequency; V
S
=
±
5 V, +5 V
FREQUENCY – MHz
NORMALIZED GAIN 2 dB
3
–3
100 500
2
–1
VO = 0.3V p-p
RF = 750V
RL = 100V
VS = +5V
1
0
–2
–4
4
5
G = +10
G = +2
G = +1
–5 10
1
Figure 25. Frequency Response; V
S
= +5 V
FREQUENCY 2 MHz
OUTPUT VOLTAGE 2 dBV
–3
–21
100 500
–6
–15
G = +2
RF = 750V
RL = 100V
VS = +5V
–9
–12
–18
–24
0
3
–27 10
1
1VRMS
Figure 26. Output Voltage vs. Frequency; V
S
= +5 V,
G = +2 V, R
L
= 100
0
–10
–20
–30
–40
–60
–70
–80
100k 1M 10M 100M 500M
FREQUENCY – Hz
–50
–90
–100
PSRR – dB
VS = +5V OR 65V
G = +2
RF = 750V
–PSRR
+PSRR
Figure 27. PSRR vs. Frequency; V
S
=
±
5 V, +5 V
AD8012
–9–REV. A
FREQUENCY – MHz
OUTPUT RESISTANCE 2 V
100
0.1
100 500
1
10
1k
0.01 10.03 0.1 10
VS = 65V
VS = +5V
G = +2
RF = 750V
Figure 28. Output Resistance vs. Frequency
1E+03 1E+04 1E+05 1E+06 1E+07 1E+08 1E+09
135
115
95
75
55
15
–5
FREQUENCY 2 Hz
35
TZ 2 dB V
0
PHASE – Degrees
–40
–80
–120
–160
–200
–240
–280
TZ(s)
PHASE
Figure 29. Open-Loop Transimpedance and Phase vs.
Frequency
LOAD – V
10 1k 10k100
7
1
6
3
5
4
2
0
8
9
SWING – V p-p
+5V
65V
Figure 30. Output Swing vs. Load
FREQUENCY – Hz
100 10k1k
3.6
2.4
3.4
2.8
3.2
3.0
2.6
2.2
2.0
3.8
4.0
CURRENT NOISE
+IN/–IN
VOLTAGE NOISE
26
14
24
18
22
20
16
12
10
28
30
INPUT CURRENT NOISE – pA/ Hz
100k
INPUT VOLTAGE NOISE – nV/ Hz
Figure 31. Noise vs. Frequency
9
8
7
6
5
4
3
2
3 4 5 6 7 8 9 10 11
1
0
f = 5MHz
G = 12
RF = 750V
RL = 100V
RL = 1kV
TOTAL SUPPLY VOLTAGE 2 Volts
PEAK-TO-PEAK OUTPUT AT 5MHz (#1% THD) 2 V
Figure 32. Output Swing vs. Supply
0.1% 5ns
G = +2
RF = 750V
RL = 100V
2V STEP
t = 0
OUTPUT VOLTAGE ERROR – 0.1%/Div
Figure 33. Settling Time, V
S
=
±
5 V
AD8012
–10– REV. A
FREQUENCY – MHz
3
–3
100 500
2
–1
VO = 0.3V p-p
RF = 750V
RL = 1kV
1
0
–2
–4
4
5
G = +10
G = +2
G = +1
–5 10
1
NORMALIZED GAIN 2 dB
Figure 34. Frequency Response; V
S
=
±
5 V
0.3
–0.3
0.2
–0.1
VO = 0.3V p-p
G = +2
RF = 750V
RL = 1kV
0.1
0
–0.2
–0.4
0.4
0.5
–0.5
FREQUENCY – MHz
0.1 101 100
NORMALIZED GAIN – dB
Figure 35. Gain Flatness; V
S
=
±
5 V
FREQUENCY – MHz
INPUT REFERRED ERROR – dB
–40
–100
100 500
–50
–80
–60
–70
–90
–110
–30
–20
–120 10.03 0.1 10
SIDE 1
SIDE 2
DRIVER
VO = 2V p-p
RL = 100V
Figure 36. Crosstalk vs. Frequency
FREQUENCY – MHz
3
–3
100 500
2
–1
VO = 0.3V p-p
RF = 750V
RL = 1kV
1
0
–2
–4
4
5
G = +10
G = +2
G = +1
–5 10
1
NORMALIZED GAIN 2 dB
Figure 37. Frequency Response; V
S
= +5 V
NORMALIZED GAIN – dB
0.3
–0.3
0.2
–0.1
VO = 0.3V p-p
RF = 750V
RL = 1kV
0.1
0
–0.2
–0.4
0.4
0.5
–0.5
FREQUENCY – MHz
0.1 101 100
Figure 38. Gain Flatness; V
S
= +5 V
V
OUT
, 2V/DIV 20ns
+3V
0V
0V
VOUT
VOUT
VIN
VIN
0V
0V
–3V
Figure 39. Overdrive Recovery; V
S
=
±
5 V, G = +2,
R
F
= 750
, R
L
= 100
, V
IN
= 3 V p-p (T = 1
µ
s)
AD8012
–11–REV. A
THEORY OF OPERATION
The AD8012 is a dual high speed CF amplifier that attains new
levels of bandwidth (BW), power, distortion and signal swing
capability. Its wide dynamic performance (including noise) is
the result of both a new complementary high speed bipolar
process and a new and unique architectural design. The AD8012
basically uses a two gain stage complementary design approach
versus the traditional “single stage” complementary mirror
structure sometimes referred to as the Nelson amplifier. Though
twin stages have been tried before, they typically consumed
high power since they were of a folded cascade design much like
the AD9617. This design allows for the standing or quiescent
current to add to the high signal or slew current-induced stages.
In the time domain, the large signal output rise/fall time and
slew rate is typically controlled by the small signal BW of the
amplifier and the input signal step amplitude respectively, not
the dc quiescent current of the gain stages (with the exception
of input level shift diodes Q1/Q2). Using two stages vs. one
also allows for a higher overall gain bandwidth product (GBWP)
for the same power, thus lower signal distortion and the ability
to drive heavier external loads. In addition, the second gain
stage also isolates (divides down) A3’s input reflected load drive
and the nonlinearities created resulting in relatively lower dis-
tortion and higher open-loop gain.
Overall, when “high” external load drive and low ac distortion
is a requirement, a twin gain stage integrating amplifier like the
AD8012 will provide excellent results for lower power over the
traditional single stage complementary devices. In addition,
being a CF amplifier, closed-loop BW variations versus exter-
nal gain variations (varying RN) will be much lower compared
to a VF op amp, where the BW varies inversely with gain. An-
other key attribute of this amplifier is its ability to run on a
single 5 V supply due in part to its wide common-mode input
and output voltage range capability. For 5 V supply operation,
the device obviously consumes half the quiescent power (vs.
10 V supply) with little degradation in its ac and dc perfor-
mance characteristics. See data sheet comparisons.
DC GAIN CHARACTERISTICS
Gain stages A1/A1B and A2/A2B combined provide negative
feedforward transresistance gain. See Figure 40. Stage A3 is a
unity gain buffer which provides external load isolation to A2.
Each stage uses a symmetrical complementary design. (A3 is
also complementary though not explicitly shown). This is done
to reduce both second order signal distortion and overall quies-
cent power as discussed above. In the quasi dc to low frequency
region, the closed loop gain relationship can be approximated
as:
G = 1+R
F
/R
N
noninverting operation
G = –R
F
/R
N
inverting operation
These basic relationships above are common to all traditional
operational amplifiers.
VP
Q1
Q2
IPP IPN
INP IPN
VN
A1
A1
ZI
IQ1
Q3
Q4
IE
CP1
CP1
Z2
A2
CL
RN
ICQ – IO
RF
VO
CD
ICQ + IO
VO 9
IQ1
AD8012
A2
CP2
Z1 = R1 || C1
Z1
CD
A3
RL
Z1
–VI
–VI
IR – IFC
IR + IFC
+–
Figure 40. Simplified Block Diagram
AD8012
–12– REV. A
APPLICATIONS
Line Driving for HDSL
High Bitrate Digital Subscriber Line (HDSL) is becoming
popular as a means of providing full duplex data communication
at rates up to 1.544 MBPS or 2.048 MBPS over moderate dis-
tances via conventional telephone twisted pair wires. Traditional
T1 (E1 in Europe) requires repeaters every 3,000 feet to 6,000
feet to boost the signal strength and allow transmission over
distances of up to 12,000 feet. In order to achieve repeaterless
transmission over this distance, an HDSL modem requires
transmitted power level of +13.5 dBm (assuming a line imped-
ance of 135 ).
HDSL uses the Two Binary/One Quaternary line code (2B1Q).
A sample 2B1Q waveform is shown in Figure 41. The digital bit
stream is broken up into groups of two bits. Four analogue
voltages (called quaternary symbols) are used to represent the
four possible combinations of two bits. These symbols are as-
signed arbitrary names +3, +1, –1 and –3. The corresponding
voltage levels are produced by a DAC that is usually part of an
Analog Front End Circuit (AFEC). Before being applied to the
line, the DAC output is low-pass filtered and acquires the sinu-
soidal form shown in Figure 41. Finally, the filtered signal is
applied to the line driver. The line voltages that correspond to
the quaternary symbols +3, +1, –1 and –3 are 2.64 V, 0.88 V,
–0.88 V and –2.64 V. This gives a peak-to-peak line voltage of
5.28 V.
VOLTAGE
+3 2.64V
+1 0.88V
–1 –0.88V
–3 –2.64V
SYMBOL
NAME DAC
OUTPUT
FILTERED
OUTPUT
TO LINE
DRIVER
–1
01 +3
10 +1
11 –3
00 –3
00 +1
11 +3
10 –3
00 –1
01 –1
01 +1
11 –1
01 –3
00
Figure 41. Time Domain Representation of a HDSL Signal
Many of the elements of a classic differential line driver are
shown in the HDSL line driver in Figure 42. A 6 V peak-to-
peak differential signal is applied to the input. The differential
gain of the amplifier (1+2 R
F
/R
G
) is set to +2, so the resulting
differential output signal is 12 V p-p.
As is normal in telephony applications, a transformer galvani-
cally isolates the differential amplifier from the line. In this case
a 1:1 turns ratio is used. In order to correctly terminate the line,
it is necessary to set the output impedance of the amplifier to be
equal to the impedance of the line being driven (135 in this
case). Because the transformer has a turns ratio of 1:1, the im-
pedance reflected from the line is equal to the line impedance
of 135 (R
REFL
= R
LINE
/Turns Ratio
2
). As a result, two 66.5
resistors correctly terminate the line.
6V p-p 12V p-p
1:1
+5V
–5V
RF
750V
RF
750V
RG
1.5kV
1/2
AD8012
1/2
AD8012
0.1mF
0.1mF
66.5V
66.5V
6V p-p
1:1
135V
TO
RECEIVER
CIRCUITRY
TO
RECEIVER
CIRCUITRY
GAIN = +2
UP TO
12,000 FEET
+
Figure 42. Differential for HDSL Applications
The immediate effect of back-termination is that the signal from
the amplifier is halved before being applied to the line. This
doubles the power the amplifier must deliver. However, the
back-termination resistors also play an important second role.
Full-duplex data transmission systems like HDSL simulta-
neously transmit data in both directions. As a result, the signal
on the line and across the back termination resistors is the com-
posite of the transmitted and received signal. The termination
resistors are used to tap off this signal and feed it to the receive
circuitry. Because the receive circuitry “knows” what is being
transmitted, the transmitted data can be subtracted from the
digitized composite signal to reveal the received data.
Driving a line with a differential signal offers a number of ad-
vantages compared to a single-ended drive. Because the two
outputs are always 180 degrees out of phase relative to one
another, the differential signal output is double the output am-
plitude of either of the op amps. As a result, the differential
amplifier can have a peak-to-peak swing of 16 V (each op amp
can swing to ±4 V), even though the power supply is ±5 V.
In addition to this, even-order harmonics (2nd, 4th, 6th, etc.) of
the two single-ended outputs tend to cancel out one another, so
the Total Harmonic Distortion (quadratic sum of all harmonics)
decreases compared to the single-ended case, even as the signal
amplitude is doubled. This is particularly advantageous for the
case of the second harmonic. As it is very close to the funda-
mental, filtering becomes difficult. In this application, the THD
is dominated by the third harmonic which is 65 dB below the
carrier (i.e., Spurious Free Dynamic Range = –65 dBc).
Differential line driving also helps to preserve the integrity of
the transmitted signal in the presence of Electro-Magnetic In-
terference (EMI). EMI tends to induce itself equally on to both
the positive and negative signal line. As a result, a receiver with
good common-mode rejection, will amplify the original signal
while rejecting induced (common-mode) EMI.
AD8012
–13–REV. A
Choosing the Appropriate Turns Ratio for the Transformer
Increasing the peak-to-peak output signal from the amplifier in
the previous example, combined with a variation in the turns
ratio of the transformer, can yield further enhancements to the
circuit. The output signal swing of the AD8012 can be increased
to about ±3.9 V before clipping occurs. This increases the peak-
to-peak output of the differential amplifier to 15.6 V. Because
the signal applied to the primary winding is now bigger, the
transformer turns ratio of 1:1 can be replaced with a (step-
down) turns ratio of about 1.3:1 (from amplifier to line). This
steps the 7.8 V peak-to-peak primary voltage down to 6 V. This
is the same secondary voltage as before so the resulting power
delivered to the line is the same.
The received signal, which is small relative to the transmitted
signal, will, however be stepped up by a factor of 1.3. Amplifying
the received signal in this manner enhances its signal-to-noise
ratio and is useful when the received signal is small compared to
the to-be-transmitted signal.
The impedance reflected from the 135 line now becomes
228 (1.3
2
times 135 ). With a correctly terminated line, the
amplifier must now drive a total load of 456 (114 + 114
+ 228 ), considerably less than the original 270 load. This
reduces the drive current from the op amps by about 40%.
More significant however is the reduction in dynamic power
consumption; that is, the power the amplifier must consume in
order to deliver the load power. Increasing the output signal so
that it is as close as possible to the power rails, minimizes the
power consumed in the amplifier.
There is, however, a price to pay in terms of increased signal
distortion. Increasing the output signal of each op amp from the
original ±3 V to ±3.9 V reduces the Spurious Free Dynamic
Range (SFDR) from –65 dB to –50 dB (measured at 500 kHz),
even though the overall load impedance has increased from
270 to 456 .
LAYOUT CONSIDERATIONS
The specified high speed performance of the AD8012 requires
careful attention to board layout and component selection.
Table I shows recommended component values for the AD8012
and Figures 44–49 show recommended layouts for the 8-lead
SOIC and microSOIC packages for a positive gain. Proper RF
design techniques and low parasitic component selections are
mandatory.
Table I. Typical Bandwidth vs. Gain Setting Resistors
Small Signal –3 dB BW (MHz),
Gain R
F
R
G
R
T
V
S
= 5 V, R
L
= 1 k
–1 750 750 53.6 110
+1 750 49.9 350
+2 750 750 49.9 150
+10 750 82.5 49.9 40
R
T
chosen for 50 characteristic input impedance.
The PCB should have a ground plane covering all unused por-
tions of the component side of the board to provide a low im-
pedance ground path. The ground plane should be removed
from the area near the input pins to reduce stray capacitance.
Chip capacitors should be used for supply bypassing (see Fig-
ure 43). One end should be connected to the ground plane
and the other within 1/8 in. of each power pin. An additional
(4.7 µF–10 µF) tantalum electrolytic capacitor should be con-
nected in parallel.
The feedback resistor should be located close to the inverting
input pin in order to keep the stray capacitance at this node to a
minimum. Capacitance greater than 1.5 pF at the inverting
input will significantly affect high speed performance when
operating at low noninverting gains.
Stripline design techniques should be used for long signal traces
(greater than about 1 in.). These should be designed with the
proper system characteristic impedance and be properly termi-
nated at each end.
Figure 43. Inverting and Noninverting Configurations
AD8012
–14– REV. A
Figure 44. Universal SOIC Noninverter Top Silkscreen
Figure 45. Universal SOIC Noninverter Top
Figure 46. Universal SOIC Noninverter Bottom
Figure 47. Universal microSOIC Noninverter Top Silkscreen
Figure 48. Universal microSOIC Noninverter Top
Figure 49. Universal microSOIC Noninverter Bottom
AD8012
–15–REV. A
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
85
41 0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
0.0500
(1.27)
BSC 0.0098 (0.25)
0.0075 (0.19) 0.0500 (1.27)
0.0160 (0.41)
8°
0°
0.0196 (0.50)
0.0099 (0.25) x 45°
8-Lead microSOIC
(RM-08)
85
4
1
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
PIN 1
0.0256 (0.65) BSC
0.122 (3.10)
0.114 (2.90)
SEATING
PLANE
0.006 (0.15)
0.002 (0.05) 0.018 (0.46)
0.008 (0.20)
0.043 (1.09)
0.037 (0.94)
0.120 (3.05)
0.112 (2.84)
0.011 (0.28)
0.003 (0.08) 0.028 (0.71)
0.016 (0.41)
33°
27°
0.120 (3.05)
0.112 (2.84)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3207a–0–12/99
PRINTED IN U.S.A.