W49F002U Data Sheet 256K x 8 CMOS FLASH MEMORY Table of Content1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS............................................................................................................. 4 BLOCK DIAGRAM ...................................................................................................................... 4 PIN DESCRIPTION..................................................................................................................... 4 FUNCTIONAL DESCRIPTION.................................................................................................... 5 6.1 Device Operation ............................................................................................................ 5 6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.2 Data Protection ............................................................................................................... 6 6.2.1 6.2.2 6.2.3 6.2.4 6.3 8. Read Command ...............................................................................................................7 Auto-select Command ......................................................................................................7 Byte Program Command ..................................................................................................7 Chip Erase Command ......................................................................................................8 Sector Erase Command ...................................................................................................8 Write Operation Status ................................................................................................... 8 6.4.1 6.4.2 7. Low VDD Inhibit................................................................................................................6 Write Pulse "Glitch" Protection .........................................................................................6 Logical Inhibit ...................................................................................................................6 Power-up Write and Read Inhibit......................................................................................6 Command Definitions ..................................................................................................... 7 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.4 Read Mode.......................................................................................................................5 Write Mode .......................................................................................................................5 Standby Mode ..................................................................................................................5 Output Disable Mode........................................................................................................5 Auto-select Mode..............................................................................................................5 Reset Mode: Hardware Reset ..........................................................................................6 DQ7: Data Polling.............................................................................................................8 DQ6: Toggle Bit ................................................................................................................9 TABLE OF OPERATING MODES .............................................................................................. 9 7.1 Device Bus Operations ................................................................................................... 9 7.2 Auto-select Codes (High Voltage Method) ................................................................... 10 7.3 Embedded Programming Algorithm.............................................................................. 11 7.4 Embedded Erase Algorithm.......................................................................................... 12 7.5 Embedded #Data Polling Algorithm.............................................................................. 13 7.6 Embedded Toggle Bit Algorithm ................................................................................... 13 7.7 Software Product Identification and Boot Block Lockout Detection Acquisition Flow .. 14 7.8 Boot Block Lockout Enable Acquisition Flow................................................................ 15 DC CHARACTERISTICS .......................................................................................................... 16 8.1 Absolute Maximum Ratings .......................................................................................... 16 8.2 DC Operating Characteristics ....................................................................................... 16 8.3 Power-up Timing........................................................................................................... 17 -1- Publication Release Date: April 19, 2005 Revision A7 W49F002U 9. 10. 11. 12. 13. 14. 15. CAPACITANCE......................................................................................................................... 17 AC CHARACTERISTICS .......................................................................................................... 17 10.1 AC Test Conditions....................................................................................................... 17 10.2 AC Test Load and Waveform ....................................................................................... 17 10.3 Read Cycle Timing Parameters.................................................................................... 18 10.4 Write Cycle Timing Parameters .................................................................................... 18 10.5 Datah Polling and Toggle Bit Timing Parameters......................................................... 19 10.6 Reset Timing Parameters ............................................................................................. 19 TIMING WAVEFORMS ............................................................................................................. 20 11.1 Read Cycle Timing Diagram......................................................................................... 20 11.2 #WE Controlled Command Write Cycle Timing Diagram ............................................. 20 11.3 #CE Controlled Command Write Cycle Timing Diagram.............................................. 21 11.4 Program Cycle Timing Diagram.................................................................................... 21 11.5 #DATA Polling Timing Diagram .................................................................................... 22 11.6 Toggle Bit Timing Diagram ........................................................................................... 22 11.7 Boot Block Lockout Enable Timing Diagram ................................................................ 23 11.8 Chip Erase Timing Diagram.......................................................................................... 23 11.9 Sector Erase Timing Diagram....................................................................................... 24 11.10 Reset Timing Diagram................................................................................................. 24 ORDERING INFORMATION..................................................................................................... 25 HOW TO READ THE TOP MARKING...................................................................................... 26 PACKAGE DIMENSIONS ......................................................................................................... 27 14.1 32-pin P-DIP ................................................................................................................. 27 14.2 32-pin PLCC ................................................................................................................. 27 14.3 32-pin STSOP (8 x 14 mm) .......................................................................................... 28 14.4 32-pin TSOP (8 x 20 mm)............................................................................................. 28 VERSION HISTORY ................................................................................................................. 29 -2- W49F002U 1. GENERAL DESCRIPTION The W49F002U is a 2-megabit, 5-volt only CMOS flash memory organized as 256K x 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W49F002U results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers. 2. FEATURES * * * * * * * * * * * Single 5-volt operations: - 5-volt Read - 5-volt Erase - 5-volt Program Fast Program operation: - Byte-by-Byte programming: 35 S (typ.) Fast Erase operation: 100 mS (typ.) Fast Read access time: 70/90/120 nS Endurance: 10K cycles (typ.) Ten-year data retention Hardware data protection One 16K byte Boot Block with Lockout protection Two 8K byte Parameter Blocks Two Main Memory Blocks (96K, 128K) Bytes Low power consumption - - * * - * * * * -3- Active current: 25 mA (typ.) Standby current: 20 A (typ.) Automatic program and erase timing with internal VPP generation End of program or erase detection - Toggle bit Data polling Latched address and data TTL compatible I/O JEDEC standard byte-wide pinouts Available packages: 32-pin DIP, 32-pin STSOP (8 mm x 14 mm), 32-pin TSOP (8 mm x 20 mm) , 32-pin-PLCC and 32-pin-PLCC Lead free Publication Release Date: 8/10/2000 Revision A2.1 W49F002U 3. PIN CONFIGURATIONS 4. BLOCK DIAGRAM VDD #RESET 32 1 A16 2 31 A15 3 30 A12 4 A7 5 A6 6 A5 7 A4 8 32-pin DIP VDD VSS #WE 29 A17 A14 #CE 28 A13 27 #OE A8 26 A9 25 A11 A3 9 24 #OE A2 10 23 A10 A1 11 22 #CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 #WE BOOT BLOCK 16K BYTES A0 . DECODER A 1 2 A 1 5 A 1 6 4 3 2 1 32 31 30 V # D W D E A 1 7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 A3 9 A2 32-pin PLCC PARAMETER BLOCK1 8K BYTES 3FFFF 3C000 3BFFF PARAMETER BLOCK2 8K BYTES A17 A7 DQ7 #RESET . # R E S E T OUTPUT BUFFER CONTROL DQ0 . . 38000 MAIN MEMORY 37FFF BLOCK1 96K BYTES 20000 MAIN MEMORY 1FFFF BLOCK2 128K BYTES 26 A9 25 A11 10 24 #OE A1 11 23 A10 A0 12 22 #CE DQ0 13 21 DQ7 3A000 39FFF 00000 14 15 16 17 18 19 20 D Q 1 D Q 2 V s s D Q 3 D Q 4 D Q 5 D Q 6 5. PIN DESCRIPTION A11 A9 A8 A13 A14 A17 1 2 31 3 30 4 5 29 #WE VDD 7 #RESET A16 A15 A12 A7 A6 A5 A4 32 28 6 8 9 10 27 32-pin TSOP 26 25 24 23 11 12 22 13 20 19 14 15 16 21 18 17 #OE A10 SYMBOL #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 #RESET Reset A0 - A17 Address Inputs DQ0 - DQ7 -4- PIN NAME Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable VDD Power Supply VSS Ground W49F002U 6. FUNCTIONAL DESCRIPTION 6.1 Device Operation 6.1.1 Read Mode The read operation of the W49F002U is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for details. 6.1.2 Write Mode Device erase and program are accomplished via the command register. The content of the register serves as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state when #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. 6.1.3 Standby Mode There are two ways to implement the standby mode on the W49F002U device, both using the #CE pin. A CMOS standby mode is achieved with the #CE input held at VDD -0.3V. Under this condition the current is typically reduced to less than 100 A. A TTL standby mode is achieved with the #CE pin held at VIH. Under this condition the current is typically reduced to less than 3 mA. In the standby mode the outputs are in the high impedance state, independent of the #OE input. 6.1.4 Output Disable Mode With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. 6.1.5 Auto-select Mode The auto-select mode allows the reading of a binary code from the device and will identify its manufacturer and type. This mode is intended to be used by programming equipment for the purpose of automatically matching the device to be programmed with its corresponding programming algorithm. This mode is functional over the entire temperature range of the device. To activate this mode, the programming equipment must force VID (11.5V to 12.5V) on address pin A9. Two identifier bytes may then be sequenced from the device outputs by toggling address A0 from VIL to VIH. All addresses are dont cares except A0 and A1 (see "Auto-select Codes"). Note: The hardware SID read function is not included in all parts; please refer to Ordering Information for details. The manufacturer and device codes may also be read via the command register; i.e., the W49F002U is erased or programmed in a system without access to high voltage on the A9 pin. The command sequence is illustrated in "Auto-select Codes". -5- Publication Release Date: April 19, 2005 Revision A7 W49F002U Byte 0 (A0 = VIL) represents the manufacturers code (Winbond = DAh) and byte 1 (A0 = VIH) the device identifier code (W49F002U = 0Bh,). All identifiers for manufacturer and device will exhibit odd parity with DQ7 defined as the parity bit. In order to read the proper device codes when executing the Auto-select, A1 must be VIL. 6.1.6 Reset Mode: Hardware Reset The #RESET pin provides a hardware method of resetting the device to reading array data. When the system drives the #RESET pin low for at least a period of tRP, the device immediately terminates any operation in progress, tri-states all data output pins, and ignores all read/write attempts for the duration of the #RESET pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the #RESET pulse. When #RESET is held at VIL, the device enters the TTL standby mode; if #RESET is held at Vss, the device enters the CMOS standby mode. The #RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. 6.2 Data Protection The W49F002U is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise. 6.2.1 Low VDD Inhibit To avoid initiation of a write cycle during VDD power-up and power-down, the W49F002U locks out when VDD < 2.5V. The write and read operations are inhibited when VDD is less than 2.5V typical. The W49F002U ignores all write and read operations until VDD > 2.5V. The user must ensure that the control pins are in the correct logic state when VDD > 2.5V to prevent unintentional writes. 6.2.2 Write Pulse "Glitch" Protection Noise pulses of less than 10 nS (typical) on #OE, #OE, or #WE will not initiate a write cycle. 6.2.3 Logical Inhibit Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one. 6.2.4 Power-up Write and Read Inhibit Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE. The internal state machine is automatically reset to the read mode on power-up. -6- W49F002U 6.3 Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences. Moreover, both Reset/Read commands are functionally equivalent, resetting the device to the read mode. 6.3.1 Read Command The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. 6.3.2 Auto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. PROM programmers typically access the signature codes by raising A9 to a high voltage. However, multiplexing high voltage onto the address lines is not generally a desirable system design practice. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAh. A read cycle from address XX01H returns the device code (W49F002U = 0Bh). 6.3.3 Byte Program Command The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. -7- Publication Release Date: April 19, 2005 Revision A7 W49F002U Programming is allowed in any sequence and across sector boundaries. Beware that a data "0" cannot be programmed back to a "1". Only erase operations can convert "0"s to "1"s. Refer to the Embedded Programming Algorithm using typical command strings and bus operations. 6.3.4 Chip Erase Command Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each sector at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Embedded Erase Algorithm using typical command strings and bus operations. 6.3.5 Sector Erase Command Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "set-up" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of #WE, while the command (30H) is latched on the rising edge of #WE. Sector erase does not require the user to program the device prior to erase. When erasing a sector or sectors the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations. The automatic sector erase begins after the rising edge of the #WE pulse for the last sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1." Refer to the Embedded Erase Algorithm using typical command strings and bus operations. 6.4 Write Operation Status 6.4.1 DQ7: Data Polling The W49F002U device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. The flowchart for Data Polling (DQ7) is shown in "Data Polling Algorithm". For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase #WE pulse. Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that bytes valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has -8- W49F002U completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0 - DQ6 may be still invalid. The valid data on DQ0 - DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or sector erase time-out (see "Command Definitions"). See " #DATA Polling During Embedded Algorithm Timing Diagrams". 6.4.2 DQ6: Toggle Bit The W49F002U also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase #WE pulse. The Toggle Bit is active during the sector erase time-out. 7. TABLE OF OPERATING MODES 7.1 Device Bus Operations MODE PIN #CE #OE #WE #RESET A0 - A17 DQ0 - DQ7 Read VIL VIL VIH VIH Ain Dout Write VIL VIH VIL VIH Ain Din VIH X VIL X X High Z/DOUT VIH X X VIH X High Z/DOUT Standby VIH X X VIH X High Z Output Disable VIL VIH VIH VIH X High Z X X X VIL X High Z Write Inhibit Reset -9- Publication Release Date: April 19, 2005 Revision A7 W49F002U 7.2 Auto-select Codes (High Voltage Method) #CE #OE #WE OTHER ADD A9 A1 A0 DQ7 TO DQ0 Manufacturer ID: Winbond VIL VIL VIH X VID VIL VIL DAh Device ID: W49F002U (Top Boot Block) VIL VIL VIH X VID VIL VIH 0Bh DESCRIPTION Notes: 1. SA = Sector Address, X = Dont Care. Sector Protection Verification: 01h (protected); 00h (unprotected). 2. The hardware SID read function is not included in all parts; please refer to Ordering Information for details. Hardware Sequence Flags OPERATION Standard Mode Embedded Program Algorithm DQ7 (NOTE) DQ6 #DQ7 Toggle 0 Toggle Embedded Erase Algorithm Note: DQ7 require a valid address when reading status information. Refer to the appropriate subsection for further details. Command Definition(1) COMMAND DESCRIPTION NO. OF CYCLES 1TH CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE ADDR. DATA ADDR. DATA ADDR. DATA ADDR. DATA ADDR. DATA ADDR. DATA Read 1 Chip Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 Sector Erase 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 SA (3) 30 Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN DIN Boot Block Lockout 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 40 Product ID Entry AIN DOUT 3 5555 AA 2AAA 55 5555 90 Product ID Exit (2) 3 5555 AA 2AAA 55 5555 F0 Product ID Exit (2) 1 XXXX F0 Notes: 1. Address Format: A14 - A0 (Hex); Data Format: DQ7 - DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. SA means: Sector Address If SA is within 3C000 to 3FFFF (Boot Block address range), and the Boot Block programming lockout feature is activated, nothing will happen and the device will go back to read mode after 100nS. If the Boot Block programming lockout feature is not activated, this command will erase Boot Block. If SA is within 3A000 to 3BFFF (Parameter Block1 address range), this command will erase PB1. If SA is within 38000 to 39FFF (Parameter Block2 address range), this command will erase PB2. If SA is within 20000 to 37FFF (Main Memory Block1 address range), this command will erase MMB1. If SA is within 00000 to 1FFFF (Main Memory Block2 address range), this command will erase MMB2. - 10 - W49F002U 7.3 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit Pause TBP No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 11 - Publication Release Date: April 19, 2005 Revision A7 W49F002U 7.4 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause T EC /T SEC Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H - 12 - W49F002U 7.5 Embedded #Data Polling Algorithm Start Read Byte (DQ0 - DQ7) Address = VA No VA = Byte address for programming = Any of the sector addresses within the sector being erased during sector erase operation = Valid address equals any sector group address during chip erase DQ7 = Data ? Yes Pass 7.6 Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 13 - Publication Release Date: April 19, 2005 Revision A7 W49F002U 7.7 Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Load data 55 to address 2AAA Read address = 0000 data = 00DA Load data 90 to address 5555 Read address = 0001 data = 00AE Pause 10 S Read address = 0002 data in DQ0 =1/0 Product Identification Exit(6) Load data AA to address 5555 (2) (2) (4) Load data 55 to address 2AAA Load data F0 to address 5555 Pause 10 S (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ15 - DQ8 (Don't Care), DQ7 - DQ0 (Hex); Address Format: A14 - A0 (Hex) (2) A1 - A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 = 1, the boot block programming lockout feature is activated; if the output data in DQ0 = 0, the lockout feature is inactivated and the block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-write cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 14 - W49F002U 7.8 Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to address 2AAA Load data 40 to address 5555 Pause 200 mS Exit - 15 - Publication Release Date: April 19, 2005 Revision A7 W49F002U 8. DC CHARACTERISTICS 8.1 Absolute Maximum Ratings PARAMETER RATING UNIT -0.5 to +7.0 V 0 to +70 C -65 to +150 C D.C. Voltage on Any Pin to Ground Potential Except A9 -0.5 to VDD +1.0 V Transient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to VDD +1.0 V -0.5 to 12.5 V Power Supply Voltage to Vss Potential Operating Temperature Storage Temperature Voltage on A9 Pin to Ground Potential Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 8.2 DC Operating Characteristics (VDD = 5.0V 10%, VSS = 0V, TA = 0 to 70 C) PARAMETER Power Supply Current Standby VDD Current (TTL input) LIMITS SYM. TEST CONDITIONS ICC #CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz - 25 50 #CE = VIH, all DQs open Other inputs = VIL/VIH - 2 3 ISB1 MIN. TYP. MAX. UNIT mA mA A Standby VDD Current (CMOS input) ISB2 #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ Vss - 20 100 Input Leakage Current ILI VIN = Vss to VDD - - 10 A Output Leakage Current ILO VOUT = Vss to VDD - - 10 A Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V - 16 - W49F002U 8.3 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 S Power-up to Write Operation TPU. WRITE 5 mS CONDITIONS MAX. UNIT 9. CAPACITANCE (VDD = 5.0V, TA = 25 C, f = 1 MHz) PARAMETER SYMBOL I/O Pin Capacitance CI/O VI/O = 0V 12 pF Input Capacitance CIN VIN = 0V 6 pF 10. AC CHARACTERISTICS 10.1 AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise/Fall Time <5 nS Input/Output Timing Level 1.5V / 1.5V Output Load 1 TTL Gate and CL = 30pF (for 70 nS/ 90 nS), 100 pF (for 120 nS) 10.2 AC Test Load and Waveform +5V 1.8K DOUT 30 pF for 70nS / 90nS 100 pF for 120nS (Including Jig and Scope) 1.3K Input Output 3V 1.5V 1.5V 0V Test Point - 17 - Test Point Publication Release Date: April 19, 2005 Revision A7 W49F002U AC Characteristics, continued 10.3 Read Cycle Timing Parameters (VDD = 5.0V 10%, VDD = 0V, TA = 0 to 70 C) PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 MIN. MAX. MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - 120 - nS Chip Enable Access Time TCE - 70 - 90 - 120 nS Address Access Time TAA - 70 - 90 - 120 nS Output Enable Access Time TOE - 35 - 40 - 50 nS #CE Low to Active Output TCLZ 0 - 0 - 0 - nS #OE Low to Active Output TOLZ 0 - 0 - 0 - nS #CE High to High-Z Output TCHZ - 25 - 25 - 30 nS #OE High to High-Z Output TOHZ - 25 - 25 - 30 nS Output Hold from Address Change TOH 0 - 0 - 0 - nS 10.4 Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time TAS 0 - - nS Address Hold Time TAH 50 - - nS #WE and #CE Setup Time TCS 0 - - nS #WE and #CE Hold Time TCH 0 - - nS #OE High Setup Time TOES 0 - - nS #OE High Hold Time TOEH 0 - - nS #CE Pulse Width TCP 100 - - nS #WE Pulse Width TWP 100 - - nS #WE High Width TWPH 100 - - nS Data Setup Time TDS 50 - - nS Data Hold Time TDH 10 - - nS Byte Programming Time TBP - 35 50 S Erase Cycle Time TEC - 0.1 0.2 S Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 18 - W49F002U AC Characteristics, continued 10.5 Datah Polling and Toggle Bit Timing Parameters PARAMETER SYM. W49F002U-70 W49F002U-90 W49F002U-120 MIN. MAX. MIN. MAX. MIN. MAX. UNIT #OE to Data Polling Output Delay TOEP - 35 - 40 - 50 nS #CE to Data Polling Output Delay TCEP - 70 - 90 - 120 nS #OE to Toggle Bit Output Delay TOET - 35 - 40 - 50 nS #CE to Toggle Bit Output Delay TCET - 70 - 90 - 120 nS 10.6 Reset Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT VDD stable to Reset Active TPRST 1 - - mS Reset Pulse Width TRSTP 500 - - nS Reset Active to Output Float TRSTF - - 50 nS Reset Inactive to Input Active TRST 1 - - S - 19 - Publication Release Date: April 19, 2005 Revision A7 W49F002U 11. TIMING WAVEFORMS 11.1 Read Cycle Timing Diagram TRC Address A17-0 TCE #CE TOE #OE #WE TOHZ TOLZ VIH TCLZ DQ7-0 TOH TCHZ High-Z High-Z Data Valid Data Valid TAA 11.2 #WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 #CE TCS TCH TOES TOEH #OE TWP #WE TWPH TDS DQ7-0 Data Valid TDH - 20 - W49F002U Timing Waveforms, continued 11.3 #CE Controlled Command Write Cycle Timing Diagram TAS TAH Address A17-0 TCPH TCP #CE TOES TOEH #OE #WE TDS DQ7-0 High Z Data Valid TDH 11.4 Program Cycle Timing Diagram Byte Program Cycle Address A17-0 2AAA 5555 AA DQ7-0 Address 5555 55 A0 Data-In #CE #OE #WE TWP Byte 0 T WPH TBP Byte 1 Byte 2 - 21 - Byte 3 Internal Write Start Publication Release Date: April 19, 2005 Revision A7 W49F002U Timing Waveforms, continued 11.5 #DATA Polling Timing Diagram Address A17-0 An An An An #WE TCEP #CE TOEH TOES #OE TOEP DQ7 X X X X TBP or TEC 11.6 Toggle Bit Timing Diagram Address A17-0 #WE #CE TOES TOEH #OE DQ6 TBP orTEC - 22 - W49F002U Timing Waveforms, continued 11.7 Boot Block Lockout Enable Timing Diagram Six byte code for Boot Block Lockout Feature Enable Address A17-0 DQ7-0 5555 2AAA 5555 AA 55 80 5555 AA 2AAA 5555 40 55 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 11.8 Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A17-0 DQ7-0 5555 2AAA 55 AA 5555 80 5555 AA 2AAA 55 5555 10 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 - 23 - SB4 SB5 Internal Erase starts Publication Release Date: April 19, 2005 Revision A7 W49F002U Timing Waveforms, continued 11.9 Sector Erase Timing Diagram Six-byte code for 5V-only software Main Memory Erase Address A17-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 55 SA 30 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 SB4 SB5 Internal Erase starts SA = Sector Address 11.10 Reset Timing Diagram VDD TPRST TRSTP #RESET TRSTF Address A17-0 DQ7-0 - 24 - TRST W49F002U 12. ORDERING INFORMATION STANDBY VDD CURRENT MAX. (A) (nS) POWER SUPPLY CURRENT MAX. (mA) W49F002U-70B 70 50 100 (CMOS) 32-pin DIP 10K Y W49F002U-90B 90 50 100 (CMOS) 32-pin DIP 10K Y W49F002U-12B 120 50 100 (CMOS) 32-pin DIP 10K Y W49F002UT70B 70 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K Y W49F002UT90B 90 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K Y W49F002UT12B 120 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K Y W49F002UP70B 70 50 100 (CMOS) 32-pin PLCC 10K Y W49F002UP90B 90 50 100 (CMOS) 32-pin PLCC 10K Y W49F002UP12B 120 50 100 (CMOS) 32-pin PLCC 10K Y W49F002UQ70B 70 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K Y W49F002UQ90B 90 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K Y W49F002UQ12B 120 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K Y W49F002U70BN 70 50 100 (CMOS) 32-pin DIP 10K N W49F002U90BN 90 50 100 (CMOS) 32-pin DIP 10K N W49F002U12BN 120 50 100 (CMOS) 32-pin DIP 10K N W49F002UT70N 70 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K N W49F002UT90N 90 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K N W49F002UT12N 120 50 100 (CMOS) 32-pin TSOP (8 mm x 20 mm) 10K N W49F002UP70N 70 50 100 (CMOS) 32-pin PLCC 10K N W49F002UP90N 90 50 100 (CMOS) 32-pin PLCC 10K N W49F002UP12N 120 50 100 (CMOS) 32-pin PLCC 10K N W49F002UQ70N 70 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K N W49F002UQ90N 90 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K N W49F002UQ12N 120 50 100 (CMOS) 32-pin STSOP (8 mm x 14 mm) 10K N W49F002UP12Z 120 50 100 (CMOS) 32-pin PLCC Lead free 10K Y PART NO. ACCES S TIME PACKAGE CYCLE HARDWARE SID READ FUNCTION Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. 3. Winbond offers Top Boot Block device, if any of Bottom Boot Block devices is required, please contact Winbond FAEs. 4. In Hardware SID read function column: Y = with SID read function; N = without SID read function. - 25 - Publication Release Date: April 19, 2005 Revision A7 W49F002U 13. HOW TO READ THE TOP MARKING Example: The top marking of 48-pin TSOP W49F002UT70B W49F002UT70B 2138977A-A12 149OBSA 1st line: winbond logo 2nd line: the part number: W49F002UT70B 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code - 26 - W49F002U 14. PACKAGE DIMENSIONS 14.1 32-pin P-DIP Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 E A1 L Base Plane Seating Plane B e1 a B1 0.25 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 0.150 1.650 1.660 41.91 42.16 0.600 0.610 14.99 15.24 15.49 0.590 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 15 0 15 0.630 0.650 0.670 16.00 16.51 17.02 0 0.085 2.16 1.Dimensions D Max. & S include mold flash or tie bar burrs. 2.Dimension E1 does not include interlead flash. 3.Dimensions D & E1. include mold mismatch and are determined at the mold parting line. 4.Dimension B1 does not include dambar protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be based on final visual inspection spec. c A A2 5.33 0.210 eA S Notes: 16 S Dimension in mm Min. Nom. Max. Min. Nom. Max. 0.010 a 1 Dimension in inches eA 14.2 32-pin PLCC Symbol HE E 4 1 32 30 5 29 GD D HD A A1 A2 b1 b c D E e GD GE HD HE L y Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. 0.140 0.020 Max. 3.56 0.50 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.46 0.018 0.022 0.41 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.51 0.530 12.45 13.46 0.390 0.410 9.91 12.9 5 10.41 0.585 0.590 0.595 14.86 14.99 15.11 0.49 0 0.090 0.495 12.32 12.45 12.57 0.095 1.91 2.29 2.41 0.485 0.075 0.430 10 10.92 0.10 0.004 0 0.56 0 10 21 13 Notes: 14 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. c 20 L A2 e b b1 Seating Plane GE A A1 y - 27 - Publication Release Date: April 19, 2005 Revision A7 W49F002U Package Dimensions, continued 14.3 32-pin STSOP (8 x 14 mm) HD D Dimension in Inches Dimension in mm c Symbol Min. Nom. Max. e A A1 A2 b c D E HD e L L1 Y E b A1 A2 A L L1 Y Min. Nom. Max. 0.047 0.002 1.20 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 1.05 0.007 0.009 0.010 0.17 0.22 0.27 0.004 ----- 0.008 0.10 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.020 0.024 0.50 0.028 0.50 0.000 0 3 0.70 0.60 0.80 0.031 0.004 0.00 5 0 0.10 3 5 14.4 32-pin TSOP (8 x 20 mm) HD Dimension in Inches Dimension in mm Symbol D A c A1 M e E 0.10(0.004) b A2 A1 L1 __ 0.002 __ 0.047 Nom. __ __ 0.006 0.05 __ Max. 1.20 0.15 0.037 0.039 0.041 0.95 1.00 1.05 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 7.90 8.00 8.10 HD 0.780 0.787 0.795 19.80 20.00 20.20 __ __ 0.024 0.40 __ __ __ 0.016 __ 1 Y 0.000 1 0.020 0.020 0.031 __ 3 0.004 0.00 5 1 Y Note: Controlling dimension: Millimeters - 28 - Min. 0.007 L L __ Max. b L Nom. A2 e A Min. 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 W49F002U 15. VERSION HISTORY VERSION DATE PAGE A1 Nov. 1999 - A2 Apr. 2000 1, 13 - 15, 20 A3 Dec. 2000 Renamed from W49F002/B/U/N Change Tbp(typ.) from 10 S to 35 S Change Tec (max.) from 1 Sec to 0.2 Sec All Modify some function description 3, 9, 25 Add in Hardware SID read note 1, 25, 27 Add in 32-pin TSOP (8 mm x 14 mm) package Jan. 2001 All A5 Aug. 13, 2001 16,22 A6 Feb. 21, 2002 1, 25, 28 April 19, 2005 Add the 120 nS bin 14 A4 A7 DESCRIPTION Typo correction Add Reset Timing Parameters and Diagram Rename STOP (8 x 14 mm) as STSOP (8 x 14 mm) 4 Modify Low VDD Write Inhibit description 13 Add in Software Product Identification and Boot Block Lockout Detection Acquisition Flow 14 Add in Boot Block Lockout Enable Acquisition Flow 24 Add HOW TO READ THE TOP MARKING 1, 24 Addition 32 PLCC Lead free package Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 29 - Publication Release Date: April 19, 2005 Revision A7 W49F002U Headquarters Winbond Electronics Corporation America Winbond Electronics (Shanghai) Ltd. No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/ 2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Taipei Office Winbond Electronics Corporation Japan Winbond Electronics (H.K.) Ltd. 9F, No.480, Rueiguang Rd., Neihu Chiu, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579 7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800 Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners. - 30 -