MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
________________________________________________________________
Maxim Integrated Products
1
Ordering Information
19-0628; Rev 2; 1/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
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General Description
The MAX8791/MAX8791B are single-phase, synchro-
nous, noninverting MOSFET drivers. The MAX8791/
MAX8791B are intended to work with controller ICs like
the MAX8736 or MAX8786, in multiphase notebook
CPU core regulators.
The regulators can either step down directly from the
battery voltage to create the core voltage, or step down
from the main system supply. The single-stage conver-
sion method allows the highest possible efficiency, while
the 2-stage conversion at higher switching frequency
provides the minimum possible physical size.
The low-side drivers are optimized to drive 3nF capaci-
tive loads with 4ns/8ns typical fall/rise times, and the
high-side driver with 8ns/10ns typical fall/rise times.
Adaptive dead-time control prevents shoot-through cur-
rents and maximizes converter efficiency.
The MAX8791/MAX8791B are available in a small, lead-
free, 8-pin, 3mm x 3mm TQFN package.
Features
Applications
+
Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX8791GTA+ -40oC to +105oC 8 TQFN-EP*
MAX8791BGTA+ -40oC to +105oC 8 TQFN-EP*
Single-Phase, Synchronous MOSFET Drivers
0.5ΩLow-Side On-Resistance
0.7ΩHigh-Side On-Resistance
8ns Propagation Delay
15ns Minimum Guaranteed Dead Time
Integrated Boost “Diode”
2V to 24V Input Voltage Range
Selectable Pulse-Skipping Mode
Low-Profile TQFN Package
Notebooks/Desktops/Servers
CPU Core Power Supplies
Multiphase Step-Down Converters
V
DD
SKIP
12
3
65
4
8
7
PWM
BST
DH
LX
GND
DL
TQFN
3mm × 3mm
+
MAX8791
MAX8791B
TOP VIEW
Pin Configuration
MAX8791
MAX8791B
PWM DH
BST
LX
DL
GND
PAD
PWM
+5V BIAS
SUPPLY
SKIP SKIP
VDD
INPUT (VIN)*
5V TO 24V
VOUT (1.45V
AT 20A)
Typical Operating Circuit
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, VDD = VSKIP = 5V, TA= -40°C to +105°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND...............…………………….………….. -0.3V to +6V
SKIP to GND..................………………………………-0.3V to +6V
PWM to GND ................……………………………….-0.3V to +6V
DL to GND..................................................-0.3V to (VDD + 0.3V)
BST to GND ............................................................-0.3V to +36V
DH to LX....................................................-0.3V to (VBST + 0.3V)
BST to VDD .............................................................-0.3V to +30V
BST to LX ................…………………………………...-0.3V to +6V
Continuous Power Dissipation (TA= +70°C)
8-Pin 3mm x 3mm TQFN
(derate 23.8mW/°C above +70°C).............................1904mW
Operating Temperature Range .........................-40°C to +105°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Voltage Range VDD 4.20 5.50 V
Rising edge, PWM disabled below this level 3.7
VDD Undervoltage
Lockout Threshold VUVLO
(
VDD
)
Falling edge, PWM disabled below this level 3.0 3.5 4.0 V
PWM = open; after the shutdown hold time has expired 0.08 0.2
SKIP = GND, PWM = GND,
LX = GND (after zero crossing) 0.25 0.5
Quiescent Supply
Current (VDD)IDD
SKIP = GND or VDD, PWM = VDD, VBST = 5V 0.6 1.5
mA
DRIVERS
tON(MIN) Minimum on-time 50
PWM Pulse Width tOFF
(
MIN
)
Minimum off-time 300 ns
DL Propagation Delay tPWM-DL PWM high to DL low 10 ns
DH Propagation Delay tPWM-DH PWM low to DH low 14 ns
TA = 0°C to +85°C 15 30
DL-to-DH Dead Time tDL-DH DL falling to DH rising TA = -40°C to +105°C 15 ns
TA = 0°C to +85°C 15 30
DH-to-DL Dead Time tDH-DL DH falling to DL rising TA = -40°C to +105°C 15 ns
tF_DL Falling, 3.0nF load 12
DL Transition Time tR_DL Rising, 3.0nF load 14 ns
tF_DH Falling, 3.0nF load 8
DH Transition Time tR_DH Rising, 3.0nF load 10 ns
DH, high state (pullup) 0.9 2.5
DH Driver On-Resistance RON(DH) BST-LX forced to 5V DH, low state (pulldown) 0.7 2.3
Ω
DL, high state (pullup) 0.7 1.8
DL Driver On-Resistance RON(DL) DL, low state (pulldown) 0.5 1.2
Ω
D H D r i ver S our ce C ur r ent IDH_SOURCE DH forced to 2.5V, BST - LX forced to 5V 2.2 A
DH Driver Sink Current IDH_SINK DH forced to 2.5V, BST - LX forced to 5V 2.7 A
DL Driver Source Current IDL_SOURCE DL forced to 2.5V 2.7 A
DL Driver Sink Current IDL_SINK DL forced to 2.5V 8 A
Zero-Crossing Threshold VZX GND - LX, SKIP = GND 3 mV
Boost On-Resistance RON
(
BST
)
V
D D
= 5V , D H = LX = G N D ( p ul l d ow n state) , IBS T = 10m A512Ω
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, VDD = VSKIP = 5V, TA= -40°C to +105°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
High (DH = high; DL = low) VDD -
0.4
Midlevel V
D D
/2
- 0.4
V
D D
/2
+ 0.4
PWM Input Levels
Low (DH = low; DL = high) 0.4
V
Sink; PWM forced to VDD -400 -200 -80
PWM Input Current IPWM Source; PWM forced to GND 80 +200 400 µA
Midlevel Shutdown Hold
Time tMID 120 300 600 ns
Rising edge 1.7 2.4
SKIP Input Threshold Falling edge 0.8 1.5 V
SKIP Input Current ISKIP Sink; SKIP forced to 0.8V to VDD, TA = +25°C -4 -2 -0.5 µA
Thermal-Shutdown
Threshold TSHDN Hysteresis = 20°C +160 °C
Note 1: Limits are 100% production tested at TA= +25°C. Maximum and minimum limits over temperature are guaranteed through
correlation using statistical-quality-control (SQC) methods.
Typical Operating Characteristics
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
PWM FREQUENCY (kHz)
PD (mW)
MAX8791 toc01
0 200 400 600 800 1000 1200
0
50
100
150
200
B
A
250
300
A: CDH = 3.3nF; CDL = 3.3nF
B: CDH = 1.5nF; CDL = 6.8nF
PACKAGE-POWER DISSIPATION
vs. CAPACITIVE LOAD ON DH AND DL
CAPACITANCE (pF)
PD (mW)
MAX8791 toc02
1000 2500 4000 5500 7000 8500 10,000
0
50
100
150
200
250
300
350
400
450
500
C
B
A
A: 300kHz
B: 600kHz
C: 1MHz
DL RISE AND FALL TIMES
vs. CAPACITIVE LOAD
CAPACITANCE (pF)
RISE AND FALL TIME (ns)
MAX8791 toc03
1000 2500 4000 5500 7000 8500 10,000
0
5
10
15
20
25
30
RISE TIME
FALL TIME
CDL = CDH
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
4 _______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
DH RISE AND FALL TIMES
vs. CAPACITIVE LOAD
CAPACITANCE (pF)
RISE AND FALL TIME (ns)
MAX8791 toc04
1000 2500 4000 5500 7000 8500 10,000
0
5
10
15
20
25
30
35
40
RISE TIME
FALL TIME
CDL = CDH
DH AND DL RISE AND FALL TIMES
vs. TEMPERATURE
TEMPERATURE (°C)
RISE AND FALL TIME (ns)
MAX8791 toc05
-40 -15 10 35 60 85 110
10
15
20
25
30
35
40
DL RISE
DH RISE
DH FALL
DL FALL
DL FALL
DL IS DRIVING 2 SI7336ADP
DH IS DRIVING 1 SI7892ADP
PACKAGE-POWER DISSIPATION
vs. PWM FREQUENCY
PWM FREQUENCY (kHz)
IDD (mW)
MAX8791 toc06
0 200 400 600 800 1000 1200
0
10
20
30
40
50
60
A
B
A: CDH = 3.3nF; CDL = 3.3nF
B: CDH = 1.5nF; CDL = 6.8nF
PROPAGATION DELAY TIME
vs. TEMPERATURE
TEMPERATURE (°C)
PROPOGATION DELAY TIME (ns)
MAX8791 toc07
-40 -15 10 35 60 85 110
8
9
10
11
12
13
14
15
16
PWM FALL TO DH FALL
PWM RISE TO DL FALL
DH FALL AND DL RISE WAVEFORMS
MAX8791 toc09
VPWM
VDL
10V/div
10V/div
5V/div
5V/div
20ns/div
VLX
VDH
DH RISE AND DL FALL WAVEFORMS
MAX8791 toc10
VPWM
VDL
10V/div
10V/div
5V/div
5V/div
20ns/div
VLX
VDH
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
_______________________________________________________________________________________
5
Pin Description
PIN NAME FUNCTION
1 BST Boost Flying-Capacitor Connection. Gate-drive power supply for DH high-side gate driver. Connect a 0.1µF or
0.22µF capacitor between BST and LX.
2 PWM
PWM Input Pin. Noninverting DH control input from the controller IC:
Logic high: DH = high (BST), DL = low (PGND).
Midlevel: After the midlevel hold time expires, the controller enters standby mode. DH and DL pulled low.
Logic low: DH = low (LX), DL = high (VDD) when SKIP = high.
Internal pullup and pulldown resistors create the midlevel and prevent the controller from triggering an on-time if
this input is left unconnected (not soldered properly) or driven by a high impedance.
3 GND Power Ground for the DL Gate Drivers and Analog Ground. Connect exposed pad to GND.
4 DL PWM Low-Side Gate-Driver Output. Swings between GND and VDD. DL forced high in shutdown.
5 VDD
Supply Voltage Input for the DL Gate Drivers. Connect to 4.2V to 5.5V supply and bypass to GND with a 1µF
ceramic capacitor.
6 SKIP
Pulse-Skipping Mode Pin. Enable pulse-skipping mode (zero-crossing comparator enabled) when the driver is
operating in SKIP mode:
SKIP = VDD PWM mode
SKIP = GND SKIP mode
An internal pulldown current pulls the controller into the low-power pulse-skipping state if this input is left
unconnected (not soldered properly) or driven by a high impedance.
7 LX Switching Node and Inductor Connection. Low-power supply for the DH high-side gate driver. LX connects to
the skip-mode zero-crossing comparator.
8 DH External High-Side nMOSFET Gate-Driver Output. Swings between LX and BST.
— EP Exposed Pad. Connect to ground through multiple vias to reduce the thermal impedance.
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDD = 5V, CDH = 3nF, CDL = 3nF, TA = +25°C, unless otherwise noted.)
SWITCHING WAVEFORMS
(PWM = MID TO LOW TO MID)
MAX8791 toc11
VPWM
VDL
VDH
VLX
0
0
0
5V
5V/div
5V/div
10V/div
0
10V/div
5V
SWITCHING WAVEFORMS
(PWM = HIGH TO MID TO HIGH)
MAX8791 toc12
VPWM
VDL
VDH
VLX
0
0
10V
0
0
5V
5V/div
5V/div
10V/div
15V
10V/div
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
6 _______________________________________________________________________________________
PWM
tPWM-DL
DL
tPWM-DH
tF_DL
tR_DH
tR_DH tR_DH
DH
tDL-DH tDH-DL
tMID
tMID
tPWM-DH
tPWM-DL
tF_DL
tR_DL tR_DL
tR_DH
Figure 2. Timing Diagram
MAX8791
MAX8791B
PWM DH
BST
LX
GND
PAD
PWM
+5V BIAS
SUPPLY
SKIP SKIP
VDD
CBST
0.1µF
C1
1.0µF
CDH
3nF
DL CDL
3nF
Figure 1. Test Circuit
Detail Description
The MAX8791/MAX8791B single-phase gate drivers,
along with the MAX8736 or MAX8786 multiphase con-
trollers, provide flexible multiphase CPU core-voltage
supplies. The low driver resistance allows up to 7A out-
put peak current. Each MOSFET driver in the
MAX8791/MAX8791B is capable of driving 3nF capaci-
tive loads with only 9ns propagation delay and 4ns/8ns
(typ) fall/rise times, allowing operation up to 3MHz per
phase. Larger capacitive loads are allowable but result
in longer propagation and transition times. Adaptive
dead-time control prevents shoot-through currents and
maximizes converter efficiency while allowing operation
with a variety of MOSFETs and PWM controllers. An
input undervoltage lockout (UVLO) circuit allows proper
power-on sequencing.
PWM Input
The drivers for the MAX8791/MAX8791B are disabled—
DH and DL pulled low—if the PWM input remains in the
midlevel window for at least 300ns (typ). Once the
PWM signal is driven high or low, the MAX8791/
MAX8791B immediately exit the low-current shutdown
state and resume active operation. Outside the shut-
down state, the drivers are enabled based on the rising
and falling thresholds specified in the
Electrical
Characteristics
.
MOSFET Gate Drivers (DH, DL)
The high-side driver (DH) has a 0.9Ωsourcing resis-
tance and 0.7Ωsinking resistance, resulting in 2.2A
peak sourcing current and 2.7A peak sinking current
with a 5V supply voltage. The low-side driver (DL) has a
typical 0.7Ωsourcing resistance and 0.3Ωsinking
resistance, yielding 2.7A peak sourcing current and 8A
peak sinking current. This reduces switching losses,
making the MAX8791/MAX8791B ideal for both high-
frequency and high output-current applications.
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
_______________________________________________________________________________________ 7
OUTPUT (VOUT)
L1
0.36µH
MAX8791
MAX8791B
PWM DH
BST
LX
DL
GND
PAD
PWM
+5V BIAS
SUPPLY
SKIP SKIP
VDD
CBST
0.22µF
COUT
2x 330µF
6mΩ
CIN
2x 10µF
INPUT (VIN)
CVDD
1.0µFNLDL
NH
Figure 3. Typical MOSFET-Driver Application Circuit
Table 1. Typical Components
DESIGNATION QTY COMPONENT SUPPLIERS
NH 1 per phase Siliconix Si4860DY
NL 1–2 per phase Siliconix Si4336DY
BST Capacitor (CBST) 1 per phase 0.1µF or 0.22µF ceramic capacitor
Schottky Diode Optional 3A, 40V Schottky diode
Inductor (L1) 1 per phase 0.36µH, 26A, 0.9mΩ power inductor
Output Capacitors (COUT) 1–2 per phase 330µF, 6mΩ per phase
Input Capacitors (CIN) 1–2 per phase 10µF, 25V X5R ceramic capacitors
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
8 _______________________________________________________________________________________
Adaptive Shoot-Through Protection
The DH and DL drivers are optimized for driving mod-
erately sized high-side and larger low-side power
MOSFETs. This is consistent with the low duty factor
seen in the notebook CPU environment, where a large
VIN - VOUT differential exists. Two adaptive dead-time
circuits monitor the DH and DL outputs and prevent the
opposite-side FET from turning on until the other is fully
off. The MAX8791/MAX8791B constantly monitor the
low-side driver output (DL) voltage, and only allow the
high-side driver to turn on when DL drops below the
adaptive threshold. Similarly, the controller monitors the
high-side driver output (DH), and prevents the low side
from turning on until DH falls below the adaptive thresh-
old before allowing DL to turn on.
The adaptive driver dead time allows operation without
shoot-through with a wide range of MOSFETs, minimiz-
ing delays and maintaining efficiency. There must be a
low-resistance, low-inductance path from the DL and
DH drivers to the MOSFET gates for the adaptive dead-
time circuits to work properly; otherwise, the sense cir-
cuitry in the MAX8791/MAX8791B interprets the
MOSFET gates as off while charge actually remains.
Use very short, wide traces (50 mils to 100 mils wide if
the MOSFET is 1in from the driver).
Internal Boost Switch
The MAX8791/MAX8791B use a bootstrap circuit to
generate the necessary drive voltage to fully enhance
the high-side n-channel MOSFET. The internal p-chan-
nel MOSFET creates an ideal diode, providing a low
voltage drop between VDD and BST.
The selected high-side MOSFET determines appropriate
boost capacitance values (CBST in Figure 1), according
to the following equation:
where QGATE is the total gate charge of the high-side
MOSFET and ∆VBST is the voltage variation allowed on
the high-side MOSFET driver. Choose ∆VBST = 0.1V to
0.2V when determining CBST. The boost flying capacitor
should be a low equivalent-series resistance (ESR)
ceramic capacitor.
CQ V
BST GATE BST
=∆
BST
DH
LX
VDD
DL
GND
UVLO
LX
ZX DETECTION
DRIVER LOGIC
AND
DEAD-TIME
CONTROL
PWM
VDD
SKIP
DRV
DRV#
THERMAL SHUTDOWN
PAD
Figure 4. Overview Block Diagram
5V Bias Supply (VDD)
VDD provides the supply voltage for the internal logic cir-
cuits. Bypass VDD with a 1µF or larger ceramic capaci-
tor to GND to limit noise to the internal circuitry. Connect
these bypass capacitors as close as possible to the IC.
Input Undervoltage Lockout
When VDD is below the UVLO threshold, DH and DL
are held low. Once VDD is above the UVLO threshold
and while PWM is low, DL is driven high and DH is
driven low. This prevents the output of the converter
from rising before a valid PWM signal is applied.
Low-Power Pulse Skipping
The MAX8791/MAX8791B enter into low-power pulse-
skipping mode when SKIP is pulled low. In skip mode,
an inherent automatic switchover to pulse-frequency
modulation (PFM) takes place at light loads. A zero-
crossing comparator truncates the low-side switch on-
time at the inductor current’s zero crossing. The
comparator senses the voltage across LX and GND.
Once VLX - VGND drops below the zero-crossing com-
parator threshold (see the
Electrical Characteristics
),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-cur-
rent operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peak-
to-peak ripple current, which is a function of the induc-
tor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal oper-
ating condition that results in high light-load efficiency.
Applications Information
Power-MOSFET Selection
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability
when using high-voltage (> 20V) AC adapters. Low-
current applications usually require less attention. The
high-side MOSFET (NH) must be able to dissipate the
resistive losses plus the switching losses at both
VIN(MIN) and VIN(MAX). Calculate both these sums.
Ideally, the losses at VIN(MIN) should be roughly equal
to losses at VIN(MAX), with lower losses in between. If
the losses at VIN(MIN) are significantly higher than the
losses at VIN(MAX), consider increasing the size of NH
(reducing RDS(ON) but increasing CGATE). Conversely,
if the losses at VIN(MAX) are significantly higher than the
losses at VIN(MIN), consider reducing the size of NH
(increasing RDS(ON) but reducing CGATE). If VIN does
not vary over a wide range, the minimum power dissi-
pation occurs where the resistive losses equal the
switching losses. Choose a low-side MOSFET that has
the lowest possible on-resistance (RDS(ON)), comes in
a moderate-sized package (i.e., one or two 8-pin SOs,
DPAK, or D2PAK), and is reasonably priced. Ensure
that the DL gate driver can supply sufficient current to
support the gate charge and the current injected into
the parasitic gate-to-drain capacitor caused by the
high-side MOSFET turning on; otherwise, cross-con-
duction problems can occur.
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (NH), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
where ηTOTAL is the total number of phases. Generally,
a small high-side MOSFET is desired to reduce switch-
ing losses at high input voltages. However, the RDS(ON)
required to stay within package-power dissipation often
limits how small the MOSFETs can be. Again, the opti-
mum occurs when the switching losses equal the con-
duction (RDS(ON)) losses. High-side switching losses
do not usually become an issue until the input is
greater than approximately 15V.
Calculating the power dissipation in high-side
MOSFETs (NH) due to switching losses is difficult since
it must allow for difficult quantifying factors that influ-
ence the turn-on and turn-off times. These factors
include the internal gate resistance, gate charge,
threshold voltage, source inductance, and PCB layout
characteristics.
The following switching-loss calculation provides only a
very rough estimate and is no substitute for prototype
evaluation, preferably including verification using a
thermocouple mounted on NH:
where COSS is the NHMOSFET’s output capacitance,
QG(SW) is the charge needed to turn on the high-side
MOSFET, and IGATE is the peak gate-drive source/sink
current (5A typ).
PD N SWITCHING VIf
n
Q
I
CVf
HIN MAX LOAD SW
TOTAL
GSW
GATE
OSS IN SW
( )
() ()
=⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟+
2
2
PD N RESISTIVE V
V
IR
HOUT
IN
LOAD
TOTAL DS ON
( ) ()
=⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
η
2
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
_______________________________________________________________________________________ 9
MAX8791/MAX8791B
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied due to the squared term in the
switching-loss equation above. If the high-side MOSFET
chosen for adequate RDS(ON) at low battery voltages
becomes extraordinarily hot when biased from VIN(MAX),
consider choosing another MOSFET with lower parasitic
capacitance.
For the low-side MOSFET (NL), the worst-case power
dissipation always occurs at the maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy load conditions that are greater than
ILOAD(MAX), but are not quite high enough to exceed the
current limit and cause the fault latch to trip. The
MOSFETs must have a good-sized heatsink to handle the
overload power dissipation. The heat sink can be a large
copper field on the PCB or an externally mounted device.
An optional Schottky diode only conducts during the
dead time when both the high-side and low-side
MOSFETs are off. Choose a Schottky diode with a
forward voltage low enough to prevent the low-side
MOSFET body diode from turning on during the dead
time, and a peak current rating higher than the peak
inductor current. The Schottky diode must be rated to
handle the average power dissipation per switching
cycle. This diode is optional and can be removed if effi-
ciency is not critical.
IC Power Dissipation and
Thermal Considerations
Power dissipation in the IC package comes mainly from
driving the MOSFETs. Therefore, it is a function of both
switching frequency and the total gate charge of the
selected MOSFETs. The total power dissipation when
both drivers are switching is given by:
where IBIAS is the bias current of the 5V supply calcu-
lated in the
5V Bias Supply (V
DD
)
section. The rise in
die temperature due to self-heating is given by the
following formula:
where PD(IC) is the power dissipated by the device,
and ΘJA is the package’s thermal resistance. The typi-
cal thermal resistance is 42°C/W for the 3mm x 3mm
TQFN package.
Avoiding dV/dt Turning on the
Low-Side MOSFET
At high input voltages, fast turn-on of the high-side
MOSFET can momentarily turn on the low-side MOSFET
due to the high dV/dt appearing at the drain of the low-
side MOSFET. The high dV/dt causes a current flow
through the Miller capacitance (CRSS) and the input
capacitance (CISS) of the low-side MOSFET. Improper
selection of the low-side MOSFET that results in a high
ratio of CRSS/CISS makes the problem more severe. To
avoid this problem, minimize the ratio of CRSS/CISS
when selecting the low-side MOSFET. Adding a 1Ωto
4.7Ωresistor between BST and CBST can slow the
high-side MOSFET turn-on. Similarly, adding a small
capacitor from the gate to the source of the high-side
MOSFET has the same effect. However, both methods
work at the expense of increased switching losses.
Layout Guidelines
The MAX8791/MAX8791B MOSFET driver sources and
sinks large currents to drive MOSFETs at high switch-
ing speeds. The high di/dt can cause unacceptable
ringing if the trace lengths and impedances are not well
controlled. The following PCB layout guidelines are rec-
ommended when designing with the MAX8791/
MAX8791B:
1) Place all decoupling capacitors as close as possi-
ble to their respective IC pins.
2) Minimize the length of the high-current loop from
the input capacitor, the upper switching MOSFET,
and the low-side MOSFET back to the input-capacitor
negative terminal.
3) Provide enough copper area at and around the
switching MOSFETs and inductors to aid in thermal
dissipation.
4) Connect GND of the MAX8791/MAX8791B as close
as possible to the source of the low-side MOSFETs.
A sample layout is available in the MAX8786 evaluation kit.
∆ΘTPDIC
JJA
=×()
PD IC I V
BIAS
()=×5
PD N RESISTIVE V
V
IR
LOUT
IN MAX
LOAD
TOTAL DS ON
( )
() ()
=−
⎛
⎝
⎜⎞
⎠
⎟
⎡
⎣
⎢
⎢
⎤
⎦
⎥
⎥
⎛
⎝
⎜⎞
⎠
⎟
1
2
η
Single-Phase, Synchronous MOSFET Drivers
10 ______________________________________________________________________________________
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
______________________________________________________________________________________ 11
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
8 TDFN-EP TQ833+1 21-0136
MAX8791/MAX8791B
Single-Phase, Synchronous MOSFET Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 8/06 Initial release —
1 11/06 Updated Electrical Characteristics and PWM Input section. 3, 7
2 1/10 Added the MAX8791B to entire data sheet. 1–12