CY7C164 CY7C166 16K x 4 Static RAM three-state drivers. The CY7C166 has an active low output enable (OE) feature. Both devices have an automatic power-down feature, reducing the power consumption by 65% when deselected. Features * High speed -- 15 ns Output enable (OE) feature (7C166) * CMOS for optimum speed/power * Low active power * -- 633 mW * Low standby power -- 220 mW TTL-compatible inputs and outputs * Automatic power-down when deselected * Writing to the device is accomplished when the chip enable (CE) and write enable (WE) inputs are both LOW (and the output enable (OE) is LOW for the 7C166). Data on the four input/output pins (I/O0 through I/O3) is written into the memory location specified on the address pins (A0 through A13). Reading the device is accomplished by taking chip enable (CE) LOW (and OE LOW for 7C166), while write enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the four data I/O pins. Functional Description The CY7C164 and CY7C166 are high-performance CMOS static RAMs organized as 16,384 by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and Logic Block Diagram The I/O pins stay in a high-impedance state when chip enable (CE) is HIGH (or output enable (OE) is HIGH for 7C166). A die coat is used to insure alpha immunity. Pin Configurations SOJ Top View DIP Top View A5 A6 A7 A8 A9 A10 A11 A12 A13 CE GND INPUT BUFFER 1 2 3 4 5 6 7C164 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 VCC A4 A3 A2 A1 A0 I/O3 I/O2 I/O1 I/O0 WE A5 A6 A7 A8 A9 A10 A11 A12 A13 CE NC GND VCC A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE 24 23 22 21 20 19 18 17 16 15 14 13 C164-2 256 x 64 x 4 ARRAY DIP/SOJ Top View I/O2 A5 A6 A7 A8 A9 A10 A11 A12 A13 CE OE GND I/O1 I/O0 POWER DOWN CE WE (OE) (7C166 ONLY) A13 COLUMN DECODER A0 A9 A10 A11 A12 I/O3 SENSE AMPS A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER C164-3 1 2 3 4 5 6 7C164 7 8 9 10 11 12 24 1 2 23 3 22 4 21 5 20 7C166 6 19 7 18 17 8 9 16 10 15 11 14 13 12 VCC A4 A3 A2 A1 A0 NC I/O3 I/O2 I/O1 I/O0 WE C164-1 C164-4 ] Selection Guide[1] 7C164-12 7C166-12 7C164-15 7C166-15 7C164-20 7C166-20 7C164-25 7C166-25 7C164-35 7C166-35 Maximum Access Time (ns) 12 15 20 25 35 Maximum Operating Current (mA) 160 115 80 70 70 40/20 40/20 40/20 20/20 20/20 Maximum Standby Current (mA) Shaded area contains advanced information. Note: 1. For military specifications, see the CY6C164A/CY7C166A datasheet Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 January 1988 - Revised December 1994 CY7C164 CY7C166 Maximum Ratings Output Current into Outputs (LOW)............................. 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Static Discharge Voltage .......................................... >2001V (per MIL-STD-883, Method 3015) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied ............................................. -55C to +125C Latch-Up Current.................................................... >200 mA Supply Voltage to Ground Potential ............... -0.5V to +7.0V Operating Range DC Voltage Applied to Outputs in High Z State[2] ............................................ -0.5V to +7.0V [2] DC Input Voltage ......................................... -0.5V to +7.0V Range Ambient Temperature VCC Commercial 0C to +70C 5V 10% Electrical Characteristics Over the Operating Range 7C164-12 7C166-12 Parameter Description Test Conditions Min. Max. 2.4 7C164-15 7C166-15 Min. Max. 2.4 7C164-20 7C166-20 Min. Max. VOH Output HIGH Voltage VCC = Min., IOH = -4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage 2.2 VCC 2.2 VCC 2.2 VCC VIL Input LOW Voltage[2] -0.5 0.8 -0.5 0.8 -0.5 0.8 IIX Input Load Current -5 +5 -5 +5 -5 +5 IOZ Output Leakage Current GND < VI < VCC GND < VO < VCC, Output Disabled -5 +5 -5 +5 -5 +5 IOS Output Short Circuit Current[3] VCC = Max., VOUT = GND -350 -350 ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA 160 ISB1 Automatic CE Max. VCC, CE > VIH, Power-Down Current[4] Min. Duty Cycle = 100% ISB2 Automatic CE Power-Down Current[4] 0.4 Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V 2.4 0.4 7C164-25, 35 7C166-25, 35 Min. Max. 2.4 0.4 V 0.4 V 2.2 VCC V -0.5 0.8 V -5 +5 A -5 +5 A -350 -350 mA 115 80 70 mA 40 40 40 20 mA 20 20 20 20 mA Shaded area contains advanced information. ] Capacitance[5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 5.0V Max. Unit 10 pF 10 pF Notes: 2. Minimum voltage is equal to -3.0V for pulse durations less than 30 ns. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. A pull-up resistor to VCC on the CE input is required to keep the device deselected during VCC power-up, otherwise ISB will exceed values given. 5. Tested initially and after any design or process changes that may affect these parameters. 2 Unit CY7C164 CY7C166 AC Test Loads and Waveforms R1 481 5V R1 481 5V OUTPUT ALL INPUT PULSES OUTPUT R2 255 30 pF 3.0V R2 255 5 pF INCLUDING JIG AND SCOPE (b) INCLUDING JIG AND SCOPE (a) GND 90% 10% 90% 10% < 5 ns < 5 ns C164-6 C164-5 Equivalent to: THEVENIN EQUIVALENT 167 OUTPUT 1.73V Switching Characteristics Over the Operating Range[6] 7C164-12 7C166-12 Parameter Description Min. Max. 7C164-15 7C166-15 Min. Max. 7C164-20 7C166-20 Min. Max. 7C164-25 7C166-25 Min. Max. 7C164-35 7C166-35 Min. Max. Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Output Hold from Address Change tACE CE LOW to Data Valid tDOE OE LOW to Data Valid 7C166 tLZOE OE LOW to Low Z 7C166 tHZOE OE HIGH to High Z 7C166 tLZCE CE LOW to Low Z 12 CE HIGH to High Z CE LOW to Power-Up tPD CE HIGH to Power-Down 20 15 3 25 20 5 35 25 5 ns 35 5 ns ns 12 15 20 25 35 ns 6 10 10 12 15 ns 0 3 7 3 8 3 [7, 8] tPU WRITE CYCLE 12 3 [7] tHZCE 15 3 7 5 8 0 0 12 3 8 5 8 0 15 3 10 5 10 0 20 ns 12 ns 15 0 20 ns ns ns 20 ns [9] tWC Write Cycle Time 12 15 20 20 25 ns tSCE CE LOW to Write End 8 12 15 20 25 ns tAW Address Set-Up to Write End 9 12 15 20 25 ns tHA Address Hold from Write End 0 0 0 0 0 ns tSA Address Set-Up to Write Start 0 0 0 0 0 ns tPWE WE Pulse Width 8 12 15 15 20 ns tSD Data Set-Up to Write End 6 10 10 10 15 ns tHD Data Hold from Write End 0 0 0 0 0 ns tLZWE WE HIGH to Low Z[7] 3 5 5 5 5 ns tHZWE WE LOW to High Z [7,8] 6 7 7 7 10 ns Shaded area contains advanced information. Notes: 6. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 7. At any given temperature and voltage condition, t HZCE is less than tLZCE for any given device. These parameters are guaranteed by design and not 100% tested. 8. tHZCE and tHZWE are specified with CL = 5 pF as in part (b) in AC Test Loads. Transition is measured 500 mV from steady-state voltage. 9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write. 3 CY7C164 CY7C166 Switching Waveforms Read Cycle No.1 [10,11] tRC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID C164-7 Read Cycle No.2 [10,12] tRC CE tACE OE 7C166 tHZOE tHZCE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE V CC SUPPLY CURRENT tPD tPU ICC 50% 50% ISB C164-8 Write Cycle No.1 (WE Controlled) [9,13] tWC ADDRESS tSCE CE tSA tAW tHA tPWE WE tSD DATAINVALID DATA IN tHZWE DATA I/O tHD tLZWE HIGH IMPEDANCE DATA UNDEFINED C164-9 Notes: 10. WE is HIGH for read cycle. 11. Device is continuously selected, CE = VIL. (7C166: OE = VIL also). 12. Address valid prior to or coincident with CE transition LOW. 13. 7C166 only: Data I/O will be high impedance if OE = VIH. 4 CY7C164 CY7C166 Switching Waveforms (continued) Write Cycle No. .2 (CE Controlled) [9,13,14] tWC ADDRESS tSA tSCE CE tHA tAW tPWE WE tHD tSD DATA IN DATAIN VALID HIGH IMPEDANCE DATA I/O C164-10 Note: 14. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. NORMALIZED SUPPLY CURRENT vs.AMBIENT TEMPERATURE NORMALIZED SUPPLY CURRENT vs.SUPPLY VOLTAGE 1.2 NORMALIZED ICC, I SB 1.2 I CC 1.0 0.8 0.6 0.4 0.0 4.0 4.5 5.0 I CC 0.8 0.6 0.4 V CC =5.0V V IN =5.0V 0.2 I SB 0.2 1.0 5.5 6.0 I SB 0.0 -55 25 NORMALIZED ACCESS TIME vs.AMBIENT TEMPERATURE 1.4 1.6 1.3 1.4 NORMALIZED t AA NORMALIZED t AA NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.2 1.1 TA =25C 1.0 1.2 1.0 VCC =5.0V 0.8 0.9 4.5 5.0 5.5 SUPPLY VOLTAGE (V) 120 100 80 V CC =5.0V TA =25C 60 40 20 0 0.0 1.0 AMBIENT TEMPERATURE (C) SUPPLY VOLTAGE (V) 0.8 4.0 125 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 6.0 0.6 -55 25 125 AMBIENT TEMPERATURE (C) 5 2.0 3.0 4.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT (mA) NORMALIZED I CC, I SB 1.4 OUTPUT SOURCE CURRENT (mA) Typical DC and AC Characteristics OUTPUT SINK CURRENT vs.OUTPUT VOLTAGE 140 120 100 VCC =5.0V TA =25C 80 60 40 20 0 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) 4.0 CY7C164 CY7C166 Typical DC and AC Characteristics (continued) TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 30.0 2.5 25.0 2.0 1.5 1.0 0.0 0.0 20.0 15.0 10.0 VCC =4.5V TA =25C 5.0 0.5 1.0 2.0 3.0 4.0 5.0 0.0 0 SUPPLY VOLTAGE (V) 200 400 WE 600 800 1000 VCC =5.0V TA =25C VIN =0.5V 1.00 0.75 0.50 10 CAPACITANCE (pF) CY7C164 Truth Table CE NORMALIZED I CC vs.CYCLE TIME 1.25 NORMALIZED I CC 3.0 DELTA tAA (ns) NORMALIZED I PO TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 20 30 40 CYCLE FREQUENCY (MHz) CY7C166 Truth Table Input/Output Mode CE WE OE Input/Output Mode H X High Z Deselect/Power-Down H X X High Z Deselect/Power-Down L H Data Out Read L H L Data Out Read L L Data In Write L L H Data In Write L H H High Z Write Address Designators Address Name Address Function CY 7C164 Pin CY7C166 Pin Number Number A5 X3 1 1 A6 X4 2 2 A7 X5 3 3 A8 X6 4 4 A9 X7 5 5 A10 Y5 6 6 A11 Y4 7 7 A12 Y0 8 8 A13 Y1 9 9 A0 Y2 17 19 A1 Y3 18 20 A2 X0 19 21 A3 X1 20 22 A4 X2 21 23 6 CY7C164 CY7C166 Ordering Information Speed (ns) 12 15 20 25 35 Speed (ns) 12 15 20 25 35 Package Name Package Type CY7C164-12PC P9 22-Lead (300-Mil) Molded DIP CY7C164-12VC V13 24-Lead Molded SOJ CY7C164-15PC P9 22-Lead (300-Mil) Molded DIP CY7C164-15VC V13 24-Lead Molded SOJ CY7C164-20PC P9 22-Lead (300-Mil) Molded DIP CY7C164-20VC V13 24-Lead Molded SOJ CY7C164-25PC P9 22-Lead (300-Mil) Molded DIP CY7C164-25VC V13 24-Lead Molded SOJ CY7C164-35PC P9 22-Lead (300-Mil) Molded DIP CY7C164-35VC V13 24-Lead Molded SOJ Ordering Code Ordering Code Package Name Package Type CY7C166-12PC P13 24-Lead (300-Mil) Molded DIP CY7C166-12VC V13 24-Lead Molded SOJ CY7C166-15PC P13 24-Lead (300-Mil) Molded DIP CY7C166-15VC V13 24-Lead Molded SOJ CY7C166-20PC P13 24-Lead (300-Mil) Molded DIP CY7C166-20VC V13 24-Lead Molded SOJ CY7C166-25PC P13 24-Lead (300-Mil) Molded DIP CY7C166-25VC V13 24-Lead Molded SOJ CY7C166-35PC P13 24-Lead (300-Mil) Molded DIP CY7C166-35VC V13 24-Lead Molded SOJ Shaded areas contain advanced information. Document #: 38-00032-I 7 Operating Range Commercial Commercial Commercial Commercial Commercial Operating Range Commercial Commercial Commercial Commercial Commercial CY7C164 CY7C166 Package Diagrams 22-Lead (300-Mil) MoldedDIP P9 24-Lead (300-Mil) Molded DIP P13/P13A 24-Lead Molded SOJ V13 (c) Cypress Semiconductor Corporation, 1994. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.