2N6796 Data Sheet November 1998 8A, 100V, 0.180 Ohm, N-Channel Power MOSFET Features The 2N6796 is an N-Channel enhancement mode silicon gate power field effect transistor designed for applications such as switching regulators, switching converters, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. This type can be operated directly from integrated circuits. * rDS(ON) = 0.180 Ordering Information * Majority Carrier Device PART NUMBER 2N6796 PACKAGE TO-205AF File Number 1594.2 * 8A, 100V * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" BRAND 2N6796 NOTE: When ordering, use the entire part number. Symbol D G S Packaging JEDEC TO-205AF DRAIN (CASE) SOURCE GATE (c)2001 Fairchild Semiconductor Corporation 2N6796 Rev. A 2N6796 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Continuous Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID Pulsed Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IS Pulse Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ISM Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg 2N6796 100 100 8 5 32 20 8 32 25 0.20 -55 to 150 UNITS V V A A A V A A W W/oC oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS ID = 0.25mA, VGS = 0V 100 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 0.5mA 2 - 4 V IDSS VDS = 100V, VGS = 0V - - 250 A Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) SYMBOL VDS(ON) IGSS rDS(ON) TEST CONDITIONS VDS = 80V, VGS = 0V, TC = 125oC - - 1000 A ID = 8A, VGS = 10V - - 1.56 V VGS = 20V - - 100 nA ID = 5A, VGS = 10V - 0.14 0.180 ID = 5A, VGS = 10V, TC = 125oC - - 0.350 Diode Forward Voltage (Note 2) VSD TC = 25oC, IS = 8A, VGS = 0V 0.75 - 1.5 V Forward Transconductance (Note 2) gfs VDS = 5V, ID = 5A 3 5.5 9 S VDD 30V, ID = 5A, RG = 50 (Figure 17) MOSFET Switching Times are Essentially Independent of Operating Temperature - - 30 ns - - 75 ns - - 40 ns - - 45 ns Turn-On Delay Time td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time tf Input Capacitance CISS 350 600 900 pF Output Capacitance COSS VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) 150 300 500 pF Reverse Transfer Capacitance CRSS 50 100 150 pF - - 5 oC/W - - 175 oC/W VDS = 80V, ID = 310mA 25 - - W VDS = 3.12V, ID = 8A 25 - - W Thermal Resistance Junction to Case RJC Thermal Resistance Junction to Ambient RJA Free Air Operation Safe Operating Area SOA Source to Drain Diode Specifications PARAMETER Reverse Recovery Time Reverse Recovered Charge SYMBOL MIN TYP MAX trr TJ = 150oC, ISD = 8A, dISD/dt = 100A/s TEST CONDITIONS - 300 - UNITS ns QRR TJ = 150oC, ISD = 8A, dISD/dt = 100A/s - 1.5 - C NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). (c)2001 Fairchild Semiconductor Corporation 2N6796 Rev. A 2N6796 Typical Performance Curves Unless Otherwise Specified 10 POWER DISSIPATION MULTIPLIER 1.2 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 8 6 4 2 0 0 0 25 125 50 75 100 TC , CASE TEMPERATURE (oC) 25 150 50 75 100 125 150 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE ZJC, NORMALIZED THERMAL IMPEDANCE 1.0 0.5 0.2 PDM 0.1 0.1 0.05 t1 t2 0.02 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC 0.01 SINGLE PULSE 0.01 10-5 10-4 10-3 10-2 10-1 10 1 t, RECTANGULAR PULSE DURATION (s) FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE 100 35 10V 10s 100s 10 1ms 10ms 1 100ms -0.1 -1 TC = 25oC TJ = MAX RATED SINGLE PULSE DC 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA (c)2001 Fairchild Semiconductor Corporation PULSE DURATION = 80s 30 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 9V 25 8V 20 7V 15 10 6V 5 5V 4V 0 1000 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 5. OUTPUT CHARACTERISTICS 2N6796 Rev. A 2N6796 Typical Performance Curves 80s PULSE TEST VGS = 10V 30 ID, DRAIN CURRENT (A) 35 PULSE DURATION = 80s 30 ID, DRAIN CURRENT (A) 35 Unless Otherwise Specified (Continued) 25 9V 20 8V 15 7V 10 6V 4V 0 0 1 20 TJ = 125oC 15 TJ = 25oC TJ = -55oC 10 5 5V 5 25 2 3 5 4 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 6 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) 0 FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 2.00 NORMALIZED ON-RESISTANCE rDS(ON), ON-STATE RESISTANCE () 0.6 0.5 0.4 VGS = 10V 0.3 0.2 VGS = 20V 0.1 0 10 0 10 20 30 40 ID, DRAIN CURRENT (A) 50 VGS = 10V ID = 4A 1.75 1.50 1.25 1.00 0.75 0.50 0.25 -80 60 -40 0 40 120 80 TJ , JUNCTION TEMPERATURE (oC) 160 NOTE: Heating effect of 2s pulse is minimal. FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 2000 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 1.10 1600 C, CAPACITANCE (pF) NORMALIZED ON-RESISTANCE 1.15 1.05 1.00 0.95 0.90 1200 800 CISS 400 COSS 0.85 0.80 -80 CRSS 0 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) 160 FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE (c)2001 Fairchild Semiconductor Corporation 0 10 20 30 40 50 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 2N6796 Rev. A 2N6796 Typical Performance Curves 80s PULSE TEST 8 ISD, SOURCE TO DRAIN CURRENT (A) gfs, TRANSCONDUCTANCE (S) 10 Unless Otherwise Specified (Continued) TJ = -55oC TJ = 25oC 6 TJ = 125oC 4 2 5 2 10 5 TJ = 25oC TJ = 150oC 2 1 0 0 5 10 15 20 25 ID, DRAIN CURRENT (A) 30 35 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 0 0.5 1.0 1.5 2.0 2.5 VSD, SOURCE TO DRAIN VOLTAGE (V) 3.0 FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE 20 VGS, GATE TO SOURCE (V) ID = 18A VDS = 20V VDS = 50V VDS = 80V 15 10 5 0 0 8 16 24 Qg , TOTAL GATE CHARGE (nC) 32 FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE (c)2001 Fairchild Semiconductor Corporation 2N6796 Rev. A 2N6796 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN IAS + RG REQUIRED PEAK IAS VDS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr VDS RL 90% 90% + RG - VDD 10% 10% 0 90% DUT VGS VGS 0 VDS (ISOLATED SUPPLY) CURRENT REGULATOR 0.2F 50% PULSE WIDTH FIGURE 18. RESISTIVE SWITCHING WAVEFORMS FIGURE 17. SWITCHING TIME TEST CIRCUIT 12V BATTERY 50% 10% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G IG(REF) 0 S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT (c)2001 Fairchild Semiconductor Corporation IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS 2N6796 Rev. A 2N6796 TO-205AF 3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE INCHES OD OD1 P A SEATING PLANE h L Ob e e1 2 e2 1 90o 3 45o j k MILLIMETERS SYMBOL MIN MAX MIN MAX A 0.160 0.180 4.07 4.57 NOTES - Ob 0.016 0.021 0.41 0.53 2, 3 - OD 0.350 0.370 8.89 9.39 OD1 0.315 0.335 8.01 8.50 - e 0.095 0.105 2.42 2.66 4 e1 0.190 0.210 4.83 5.33 4 e2 0.095 0.105 2.42 2.66 4 h 0.010 0.020 0.26 0.50 - j 0.028 0.034 0.72 0.86 - k 0.029 0.045 0.74 1.14 - L 0.500 0.560 12.70 14.22 3 P 0.075 - 1.91 - 5 NOTES: 1. These dimensions are within allowable dimensions of Rev. E of JEDEC TO-205AF outline dated 11-82. 2. Lead dimension (without solder). 3. Solder coating may vary along lead length, add typically 0.002 inches (0.05mm) for solder coating. 4. Position of lead to be measured 0.100 inches (2.54mm) from bottom of seating plane. 5. This zone controlled for automatic handling. The variation in actual diameter within this zone shall not exceed 0.010 inches (0.254mm). 6. Lead no. 3 butt welded to stem base. 7. Controlling dimension: Inch. 8. Revision 3 dated 6-94. (c)2001 Fairchild Semiconductor Corporation 2N6796 Rev. A TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACExTM BottomlessTM CoolFETTM CROSSVOLTTM DenseTrenchTM DOMETM EcoSPARKTM E2CMOSTM EnSignaTM FACTTM FACT Quiet SeriesTM FAST FASTrTM GlobalOptoisolatorTM GTOTM HiSeCTM ISOPLANARTM LittleFETTM MicroFETTM MICROWIRETM OPTOLOGICTM OPTOPLANARTM PACMANTM POPTM PowerTrench QFETTM QSTM QT OptoelectronicsTM Quiet SeriesTM SILENT SWITCHER SMART STARTTM Star* PowerTM StealthTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM TinyLogicTM UHCTM UltraFET VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. H1