©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
2N6796
8A, 100V, 0.180 Ohm, N-Channel Power
MOSFET
The 2N6796 is an N-Channel enhancement mode silicon
gate power field effect transistor designed for applications
such as switching regulators, switching converters, motor
drivers, relay drivers, and drivers for high power bipolar
switching transistors requiring high speed and low gate drive
power. This type can be operated directly from integrated
circuits.
Features
• 8A, 100V
•r
DS(ON)
= 0.180
Ω
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-205AF
Ordering Information
PART NUMBER PACKAGE BRAND
2N6796 TO-205AF 2N6796
NOTE: When ordering, use the entire part number.
G
D
S
SOURCE
DRAIN
(CASE)
GATE
Data Sheet November 1998 File Number
1594.2
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
2N6796 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
100 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
100 V
Continuous Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
T
C
= 100
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
D
8
5
A
A
Pulsed Drain Current (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
DM
32 A
Gate to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V
GS
±
20 V
Continuous Source Current (Body Diode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
S
8A
Pulse Source Current (Body Diode). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
SM
32 A
Maximum Power Dissipation (Figure 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
25 W
Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.20 W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
J,
T
STG
-55 to 150
o
C
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 0.25mA, V
GS
= 0V 100 - - V
Gate Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 0.5mA 2 - 4 V
Zero Gate Voltage Drain Current I
DSS
V
DS
= 100V, V
GS
= 0V - - 250
µ
A
V
DS
= 80V, V
GS
= 0V, T
C
= 125
o
C - - 1000
µ
A
On-State Drain Current (Note 2) V
DS(ON)
I
D
= 8A, V
GS
= 10V - - 1.56 V
Gate to Source Leakage Current I
GSS
V
GS
=
±
20V - -
±
100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 5A, V
GS
= 10V - 0.14 0.180
Ω
I
D
= 5A, V
GS
= 10V, T
C
= 125
o
C - - 0.350
Ω
Diode Forward Voltage (Note 2) V
SD
T
C
= 25
o
C, I
S
= 8A, V
GS
= 0V 0.75 - 1.5 V
Forward Transconductance (Note 2) gfs V
DS
= 5V, I
D
= 5A 3 5.5 9 S
Turn-On Delay Time t
d(ON)
V
DD
≅
30V, I
D
= 5A, R
G
= 50
Ω
(Figure 17) MOSFET Switching Times are
Essentially Independent of Operating
Temperature
- - 30 ns
Rise Time t
r
- - 75 ns
Turn-Off Delay Time t
d(OFF)
- - 40 ns
Fall Time t
f
- - 45 ns
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz, (Figure 11) 350 600 900 pF
Output Capacitance C
OSS
150 300 500 pF
Reverse Transfer Capacitance C
RSS
50 100 150 pF
Thermal Resistance Junction to Case R
θ
JC
--5
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
Free Air Operation - - 175
o
C/W
Safe Operating Area SOA V
DS
= 80V, I
D
= 310mA 25 - - W
V
DS
= 3.12V, I
D
= 8A 25 - - W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Reverse Recovery Time t
rr
T
J
= 150
o
C, I
SD
= 8A, dI
SD
/dt = 100A/
µ
s - 300 - ns
Reverse Recovered Charge Q
RR
T
J
= 150
o
C, I
SD
= 8A, dI
SD
/dt = 100A/
µ
s - 1.5 -
µ
C
NOTES:
2. Pulse test: pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
2N6796
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
0
50 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
150
25 75 125
10
8
6
4
2
t, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED
THERMAL IMPEDANCE
10-3 10-2
1.0
10-5 10-4
0.01
0.1
10
10-1 1
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
t1
t2
SINGLE PULSE
0.1
0.02
0.2
0.5
0.01
0.05
VDS, DRAIN TO SOURCE VOLTAGE (V)
10
ID, DRAIN CURRENT (A)
100
100
1
10-1
-0.1 1000
10µs
100µs
1ms
10ms
100ms
DC
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
OPERATION IN THIS AREA IS
LIMITED BY rDS(ON)
ID, DRAIN CURRENT (A)
010203040
5
10
15
20
25
50
10V
VDS, DRAIN TO SOURCE VOLTAGE (V)
PULSE DURATION = 80µs
0
8V
7V
6V
5V
4V
30
35
9V
2N6796
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
NOTE: Heating effect of 2µs pulse is minimal.
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
Typical Performance Curves Unless Otherwise Specified (Continued)
0
5
0123 5
10
15
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
20
4
25
PULSE DURATION = 80µs
30
35
7V
4V
5V
6V
8V
9V
VGS = 10V
6
15
10
5
024
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
0
25
20
6810
TJ = 125oC
TJ = 25oC
TJ = -55oC
30
80µs PULSE TEST
35
ID, DRAIN CURRENT (A)
rDS(ON), ON-STATE RESISTANCE (Ω)
0.4
0.3
0.2
0.1
0010203040
VGS = 20V
VGS = 10V
50 60
0.5
0.6
1.75
1.00
0.75
0.50
0.25
-80 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
80 120 160
1.25
1.50
NORMALIZED ON-RESISTANCE
2.00 VGS = 10V
ID = 4A
1.10
0.95
0.90
0.85
0.80
-80 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
80 120 160
1.00
1.05
NORMALIZED ON-RESISTANCE
1.15 2000
400
0020 50
C, CAPACITANCE (pF)
1200
VDS, DRAIN TO SOURCE VOLTAGE (V)
1600
800 CISS
COSS
CRSS
10 30 40
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGD
VGS = 0V, f = 1MHz
2N6796
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves Unless Otherwise Specified (Continued)
6
4
2
0
510
ID, DRAIN CURRENT (A)
0
10
8
15 20 25
gfs, TRANSCONDUCTANCE (S)
80µs PULSE TEST
TJ = 125oC
TJ = -55oC
TJ = 25oC
30 35 0
2
10
5
2
1
VSD, SOURCE TO DRAIN VOLTAGE (V)
ISD, SOURCE TO DRAIN CURRENT (A)
TJ = 150oCTJ = 25oC
5
0.5 1.0 1.5 2.0 2.5 3.0
15
10
5
0 8 16 24 32
VDS = 20V
VDS = 50V
VDS = 80V
Qg, TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
20
0
ID = 18A
2N6796
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-
VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
IG(REF)
0
2N6796
©2001 Fairchild Semiconductor Corporation 2N6796 Rev. A
2N6796
TO-205AF
3 LEAD JEDEC TO-205AF HERMETIC METAL CAN PACKAGE
L
A
Øb
ØD1
ØD
h
1
2
3
e
e1
SEATING
PLANE
90o
e2
jk
P
45o
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.160 0.180 4.07 4.57 -
Øb 0.016 0.021 0.41 0.53 2, 3
ØD 0.350 0.370 8.89 9.39 -
ØD10.315 0.335 8.01 8.50 -
e 0.095 0.105 2.42 2.66 4
e10.190 0.210 4.83 5.33 4
e20.095 0.105 2.42 2.66 4
h 0.010 0.020 0.26 0.50 -
j 0.028 0.034 0.72 0.86 -
k 0.029 0.045 0.74 1.14 -
L 0.500 0.560 12.70 14.22 3
P 0.075 - 1.91 - 5
NOTES:
1. These dimensions are within allowable dimensions of Rev. E of
JEDEC TO-205AF outline dated 11-82.
2. Lead dimension (without solder).
3. Solder coating may vary along lead length, add typically 0.002
inches (0.05mm) for solder coating.
4. Position of lead to be measured 0.100 inches (2.54mm) from bottom
of seating plane.
5. This zone controlled for automatic handling. The variation in
actual diameter within this zone shall not exceed 0.010 inches
(0.254mm).
6. Lead no. 3 butt welded to stem base.
7. Controlling dimension: Inch.
8. Revision 3 dated 6-94.
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failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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