High Power, 44 W Peak, Silicon SPDT,
Reflective Switch, 0.7 GHz to 3.8 GHz
Data Sheet
ADRF5130
Rev. C Document Feedback
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FEATURES
Reflective, 50 Ω design
Low insertion loss
0.6 dB typical to 2.0 GHz
0.7 dB typical to 3.5 GHz
High isolation
50 dB typical to 2.0 GHz
46 dB typical to 3.5 GHz
High power handling
RF input power, continuous wave (CW) at TCASE = 85°C
43 dBm maximum operating
46.5 dBm absolute maximum rating
High linearity
0.1 dB compression (P0.1dB): 46 dBm typical
Input third-order intercept (IP3)
68 dBm typical to 2 GHz
65 dBm typical to 3.5 GHz
ESD ratings
Human body model (HBM): 2 kV, Class 2
Charged device model (CDM): 1.25 kV
Single positive supply: VDD = 5 V
Positive control, TTL-compatible: VCTL = 0 V or VDD
24-lead, 4 mm × 4 mm LFCSP package (16 mm2)
APPLICATIONS
Cellular/4G infrastructure
Wireless infrastructure
Military and high reliability applications
Test equipment
Pin diode replacement
FUNCTIONAL BLOCK DIAGRAM
RF1 RF2
RFC
VCTL
14081-001
ADRF5130
Figure 1.
GENERAL DESCRIPTION
The ADRF5130 is a high power, reflective, 0.7 GHz to 3.8 GHz,
silicon, single-pole, double-throw (SPDT) switch in a leadless,
surface-mount package. The switch is ideal for high power and
cellular infrastructure applications, like long-term evolution (LTE)
base stations.
The ADRF5130 has high power handling of 43 dBm (maximum)
and 0.1 dB compression (P0.1dB) of 46 dBm, with a low
insertion loss of 0.6 dB at 2 GHz and 0.7 dB at 3.5 GHz. On-chip
circuitry operates at a single, positive supply voltage of 5 V and
typical supply current of 1.06 mA, making the ADRF5130 an
ideal alternative to pin diode-based switches.
The device comes in a RoHS compliant, compact, 24-lead, 4 mm ×
4 mm LFCSP package.
ADRF5130 Data Sheet
Rev. C | Page 2 of 10
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Absolute Maximum Ratings ........................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions ............................ 5
Interface Schematics .....................................................................5
Typical Performance Characteristics .............................................6
Insertion Loss, Isolation, Return Loss, and IP3 ........................6
Theory of Operation .........................................................................7
Applications Information ................................................................8
Evaluation Board ...........................................................................8
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
6/2020—Rev. B to Rev. C
Changed Operating Frequency from 0.7 GHz to 3.5 GHz to
0.7 GHz to 3.8 GHz ....................................................... Throughout
Changes to Data Sheet Title, Features Section, and General
Description Section .......................................................................... 1
Changes to Table 1 ........................................................................... 3
5/2018—Rev. A to Rev. B
Change to RFC to RF2 Column, Table 5 ....................................... 7
Updated Outline Dimensions ...................................................... 10
1/2017—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 10
7/2016—Revision 0: Initial Version
Data Sheet ADRF5130
Rev. C | Page 3 of 10
SPECIFICATIONS
VDD = 5 V, VCTL = 0 V or VDD, TA = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 0.7 3.8 GHz
INSERTION LOSS 0.7 GHz to 2.0 GHz 0.6 dB
2.0 GHz to 3.5 GHz 0.7 dB
3.5 GHz to 3.8 GHz 0.75 dB
ISOLATION
RFC to RF1 or RF2 (Worst Case) 0.7 GHz to 2.0 GHz 50 dB
2.0 GHz to 3.8 GHz 46 dB
RF1 to RF2 (Worst Case) 0.7 GHz to 2.0 GHz 51 dB
2.0 GHz to 3.8 GHz 40 dB
RETURN LOSS
RFC 0.7 GHz to 2.0 GHz 23 dB
2.0 GHz to 3.5GHz 17 dB
3.5 GHz to 3.8 GHz 15 dB
RFC to RF1 or RF2 0.7 GHz to 2.0 GHz 21 dB
2.0 GHz to 3.5 GHz 17 dB
3.5 GHz to 3.8 GHz 16 dB
SWITCHING SPEED
Time
Rise and Fall tRISE, tFALL 90% to 10% of RF output 155 ns
On and Off tON, tOFF 50% VCTL to 10% to 90% of RF output 750 ns
RADIO FREQUENCY (RF) SETTLING TIME 50% VCTL to 0.1 dB margin of final RF output 1.8 µs
INPUT POWER
0.1 dB Compression P0.1dB 46 dBm
INPUT THIRD-ORDER INTERCEPT IP3 Two-tone input power = 25 dBm/tone
0.7 GHz to 2 GHz 68 dBm
2 GHz to 3.8 GHz 65 dBm
RECOMMENDED OPERATING
CONDITIONS
Voltage Range
Bias VDD 4.5 5.4 V
Control VCTL 0 VDD V
Maximum RF Input Power
TCASE = 105°C Continuous wave 41 dBm
TCASE = 85°C Continuous wave 43 dBm
8 dB peak to average ratio (PAR) LTE, average 38 dBm
8 dB PAR LTE, single event (<10 sec), average 44 dBm
TCASE = 25°C Continuous wave 44.5 dBm
Case Temperature Range TCASE −40 +105 °C
DIGITAL INPUT CONTROL VOLTAGE VDD = 4.5 V to 5.4 V, TCASE = −40°C to +105°C at <1 µA
typical
Low Range VIL 0 0.8 V
High Range VIH 1.3 5.0 V
SUPPLY CURRENT IDD VDD = 5 V 1.06 mA
ADRF5130 Data Sheet
Rev. C | Page 4 of 10
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Rating
Bias Voltage Range (VDD) −0.3 V to +5.5 V
Control Voltage Range (VCTL) −0.3 V to +5.5 V
RF Input Power,1 Continuous Wave 46.5 dBm
Channel Temperature 135°C
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +105°C
Peak Reflow Temperature (MSL3)2 260°C
Thermal Resistance (Channel to Package
Bottom)
17°C/W
Electrostatic Discharge (ESD) Sensitivity
HBM 2 kV (Class 2)
CDM 1.25 kV
1 For the recommended operating conditions, see Table 1.
2 See the Ordering Guide section.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
Data Sheet ADRF5130
Rev. C | Page 5 of 10
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
13
1
3
4
2
7
GND
GND
RF1
GND 5
6
GND
GND GND
14 GND
15 GND
16 RF2
17 GND
18 GND
GND
8
GND
9
GND
10
RFC
11
GND
12 19
GND GND
20
GND
21
V
CTL
22
V
DD
23
GND
24
GND
ADRF5130
TOP VIEW
(No t t o Scal e)
NOTES
1. EXPOSED PAD. EXPOSED PAD MUST BE
CONNECTED TO RF/ DC GROUND.
14081-002
PACKAGE
BASE
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4 to 9, 11 to 15, 17 to 20, 23, 24 GND Ground. The package bottom has an exposed metal pad that must connect to the
printed circuit board (PCB) RF/dc ground. See Figure 3 for the GND interface schematic.
3 RF1 RF Output Port 1. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor
is required on this pin.
10 RFC RF Input Common Port. This pin is dc-coupled and matched to 50 Ω. A dc blocking
capacitor is required on this pin.
16 RF2 RF Output Port 2. This pin is dc-coupled and matched to 50 Ω. A dc blocking capacitor
is required on this pin.
21 VCTL Control Input. See Figure 4 for the VCTL interface schematic. Refer to Table 4 and the
recommended digital input control voltage range in Table 1.
22 VDD Supply Voltage. See Figure 4 for the VDD interface schematic.
EPAD Exposed Pad. Exposed pad must be connected to RF/dc ground.
Table 4. Truth Table
Signal Path State
Control Input (VCTL) State RFC to RF1 RFC to RF2
Low Off On
High On Off
INTERFACE SCHEMATICS
GND
14081-003
Figure 3. GND Interface Schematic
VDD
VCTL
14081-004
Figure 4. Control Interface Schematic
ADRF5130 Data Sheet
Rev. C | Page 6 of 10
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, ISOLATION, RETURN LOSS, AND IP3
0
–2.5
–2.0
–1.5
–1.0
–0.5
012345
INSERTION LOSS (dB)
FREQUENCY ( GHz)
14081-005
RF1
RF2
Figure 5. Insertion Loss of RF1 and RF2 vs. Frequency at VDD = 5 V
0
–90
–70
–50
–30
–10
–80
–60
–40
–20
ISOLATION (dB)
0123 4 5
FREQUENCY ( GHz)
14081-006
RF1
RF2
Figure 6. Isolation Between RFC to RF1 or RF2 vs. Frequency at VDD = 5 V
–45
0
–35
–25
–15
–5
–40
–30
–20
–10
RET URN LOS S ( dB)
012345
FREQUENCY ( GHz)
RFC
RF1
RF2
14081-007
Figure 7. Return Loss vs. Frequency at VDD = 5 V (RFC, RF1, and RF2)
0
–2.5
–2.0
–1.5
–1.0
–0.5
012345
INSERTION LOSS (dB)
FREQUENCY ( GHz)
+105°C
+85°C
+25°C
–40°C
14081-008
Figure 8. Insertion Loss vs. Frequency over Temperature at VDD = 5 V
0
–80
–60
–70
–50
–30
–10
–40
–20
ISOLATION (dB)
012 3 4 5
FREQUENCY ( GHz)
14081-009
RF1 O N
RF2 O N
Figure 9. Isolation Between RF1 and RF2 vs. Frequency at VDD = 5 V,
Switch Mode On
74
620.5 4.0
IP3 (dBm)
FREQUENCY ( GHz)
+105°C
+85°C
+25°C
–40°C
64
66
68
70
72
1.0 1.5 2.0 2.5 3.0 3.5
14081-010
Figure 10. IP3 vs. Frequency over Temperature, VDD = 5 V
Data Sheet ADRF5130
Rev. C | Page 7 of 10
THEORY OF OPERATION
The ADRF5130 requires a single-supply voltage applied to the
VDD pin. Bypass capacitors are recommended on the supply line
to minimize RF coupling.
A digital control voltage applied to the VCTL pin controls the
ADRF5130. A small bypassing capacitor is recommended on
these digital signal lines to improve the RF signal isolation.
The ADRF5130 is internally matched to 50 Ω at the RF input
port (RFC) and the RF output ports (RF1 and RF2); therefore,
no external matching components are required. The RFx pins
are dc-coupled, and dc blocking capacitors are required on the
RF lines. The design is bidirectional; the input and outputs are
interchangeable.
The ideal power-up sequence of the ADRF5130 is as follows:
1. Connect to GND.
2. Power up VDD.
3. Power up the digital control input. Powering the digital
control input before the VDD supply can inadvertently
forward-bias and damage the ESD protection structures.
4. Power up the RF input. Depending on the logic level
applied to the VCTL pin, one RF output port (for example,
RF1) is set to on mode, by which an insertion loss path is
provided from the input to the output, while the other RF
output port (for example, RF2) is set to off mode, by which
the output is isolated from the input.
Table 5. Switch Operation Mode
Digital Control Input (VCTL)
Switch Mode
RFC to RF1 RFC to RF2
0 Off mode: the RF1 port is isolated from the RFC
port and is internally terminated to a 50 Ω load to
absorb the applied RF signals.
On mode: a low insertion loss path from the RFC port
to the RF2 port.
1 On mode: a low insertion loss path from the RFC
port to the RF1 port.
Off mode: the RF2 port is isolated from the RFC port
and becomes open reflective.
ADRF5130 Data Sheet
Rev. C | Page 8 of 10
APPLICATIONS INFORMATION
Generate the evaluation PCB used in the application circuit
shown in Figure 11 with proper RF circuit design techniques.
Signal lines at the RF port must have a 50 Ω impedance, and the
package ground leads and backside ground slug must connect
directly to the ground plane, as shown in Figure 14.
14081-011
13
GND
GND
RF1
GND
GND
GND GND
14
GND
15
GND
16
RF2
17
GND
18
GND
GND
GND
GND
RFC
GND
19
GND GND
20
GND
21
V
CTL
22
V
DD
23
GND
24
GND
7
8
9
10
11
12
C4 C7
C5
C8 TO C11 C12 TO C15
C6
V
DD
R1 V
CTL
C1 C3
RF1 RF2
RFC
C2
C18 TO C21
1
3
4
2
5
6
Figure 11. Application Circuit
EVALUATION BOARD
The ADRF5130 evaluation board has eight metal layers and
dielectrics between each layer (see Figure 12). The top and the
bottom metal layers have copper thickness of 2 oz (2.7 mil),
whereas the metal layers in between them have 1 oz copper
(1.3 mil) thickness. The top dielectric material is 10 mil Rogers
RO4350, which exhibits a very low thermal coefficient, offering
control over thermal rise of the board. The dielectrics between
other metal layers are FR-4. The overall board thickness
achieved is 62 mil.
Figure 13 shows the top view of the ADRF5130 evaluation
board.
The top copper layer has all RF and dc traces, whereas the other
seven layers provide good ground and help to handle the thermal
rise on the evaluation board caused by the high power of the
ADRF5130. In addition, for proper thermal grounding, many
via holes are provided around the transmission lines and under
the exposed pad of the package. RF transmission lines on the
ADRF5130 evaluation board are coplanar wave guide design with
an 18 mil width and a ground spacing of 13 mil. For controlling
the thermal rise of the ADRF5130 evaluation board at high
temperatures and power levels, it is recommended to use a
heat sink and a mini dc fan.
W = 18mi l G = 13mil
T = 2.7mi l
TOTAL THICKNES S = 62mil
H = 10mil
2oz Cu (2. 7mil)
RO4350 = 10mil
FR4
FR4
FR4
FR4
FR4
FR4
1oz Cu (1. 3mil)
1oz Cu (1. 3mil)
1oz Cu (1. 3mil)
1oz Cu (1. 3mil)
1oz Cu (1. 3mil)
1oz Cu (1. 3mil)
2oz Cu (2. 7mil)
2oz Cu (2. 7mil) 2o z Cu (2. 7mil )
14081-013
Figure 12. Evaluation Board Cross-Sectional View
1.500
1.500
0.050
0.050
14081-014
Figure 13. Evaluation Board Top View
Data Sheet ADRF5130
Rev. C | Page 9 of 10
Figure 14 shows the ADRF5130 evaluation board with all
components populated. The VDD supply port connects to TP1.
The VDD supply trace has three bypass capacitors 100 pF, 1 µF,
and 1 nF. The TP2 test point connects to the control voltage
port (VCTL). The control trace has a 100 pF bypass capacitor
and 0 Ω resistor. The ground reference connects to GND. A
100 pF dc blocking capacitor is used on all RF traces that connect
the RF1, RF2, and RFC ports to the J1, J2, and J3 connectors,
respectively. The connectors used are 2.9 mm end launch SMA
connectors. Unpopulated capacitor positions are available on
all RF traces to provide extra matching. A through transmission
line (THRU CAL) is available on the ADRF5130 evaluation board
that can measure board loss on the printed circuit board (PCB).
Table 6 shows the bill of materials for the ADRF5130
evaluation board. The evaluation board shown in Figure 14 is
available from Analog Devices, Inc., upon request.
C4
C6
J3
J2
J1
U1
C5
C7
R1
TP1
TP2
TP3
C1
C2
C3
600-01532-00-2
RF1
RFC
RF2
VDD
GND
VCTL
THRU CAL
12
34
432143
21
14081-012
Figure 14. ADRF5130-EVALZ Evaluation Board
Table 6. Bill of Materials for the ADRF5130-EVALZ Evaluation Board
Reference Designator Description
J1 to J3 PCB mount SMA connectors
C1 to C4, C7 100 pF capacitors, 0402 package
C5 1 nF capacitor, 0402 package
C6 1 µF capacitor, 0402 package
C8 to C15, C18 to C21 Do not insert (DNI)
R1 0 Ω resistor, 0402 package
TP1, TP2, TP3 Surface-mount test points
U1 ADRF5130 SPDT switch
PCB 600-01532-00-21 evaluation PCB; circuit board material: Rogers RO4350 or Arlon 25FR
1 Reference this evaluation board number when ordering the complete evaluation board.
ADRF5130 Data Sheet
Rev. C | Page 10 of 10
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
COMPLIANT
TO
JEDEC STANDARDS M O-220-V GG D- 8
BOTTOM VI EW
TOP VIEW
SIDE VIEW
4.10
4.00 SQ
3.90
0.90
0.85
0.80 0. 05 MAX
0.02 NO M
0.20 REF
COPLANARITY
0.08
1
24
7
12
13
18
19
6
FOR PRO P E R CONNECT ION OF
THE EXPOSED PAD, REFER TO
THE PIN CO NFIGURAT ION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
09-10-2018-C
0.30
0.25
0.18
0.20 M IN
2.80
2.70 SQ
2.60
EXPOSED
PAD
PKG-004926/004942
SEATING
PLANE
PIN 1
IN DICATO R AR EA OP TION S
(SEE DETAIL A)
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
AREA
Figure 15. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.85 mm Package Height
(CP-24-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range MSL Rating2 Package Description Package Option
ADRF5130BCPZ −40°C to +105°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
ADRF5130BCPZ-R7 −40°C to +105°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16
ADRF5130-EVALZ −40°C to +105°C Evaluation Board
1 Z = RoHS Compliant Part.
2 See the Absolute Maximum Ratings section.
©2016–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14081-6/20(C)
