ispLSI® 2064/A
In-System Programmable High Density PLD
2064_10 1
USE ispLSI 2064E FOR NEW DESIGNS
Lead-
Free
Package
Options
Available!
Features
• ENHANCEMENTS
— ispLSI 2064A is Fully Form and Function Compatible
to the ispLSI 2064, with Identical Timing
Specifcations and Packaging
— ispLSI 2064A is Built on an Advanced 0.35 Micron
E2CMOS® Technology
• HIGH DENSITY PROGRAMMABLE LOGIC
— 2000 PLD Gates
— 64 I/O Pins, Four Dedicated Inputs
— 64 Registers
— High Speed Global Interconnect
— Wide Input Gating for Fast Counters, State
Machines, Address Decoders, etc.
— Small Logic Block Size for Random Logic
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
— fmax = 125 MHz Maximum Operating Frequency
— tpd = 7.5 ns Propagation Delay
— TTL Compatible Inputs and Outputs
— Electrically Erasable and Reprogrammable
— Non-Volatile
— 100% Tested at Time of Manufacture
— Unused Product Term Shutdown Saves Power
• IN-SYSTEM PROGRAMMABLE
— In-System Programmable (ISP™) 5V Only
— Increased Manufacturing Yields, Reduced Time-to-
Market and Improved Product Quality
— Reprogram Soldered Devices for Faster Prototyping
• OFFERS THE EASE OF USE AND FAST SYSTEM
SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY
OF FIELD PROGRAMMABLE GATE ARRAYS
— Complete Programmable Device Can Combine Glue
Logic and Structured Designs
— Enhanced Pin Locking Capability
— Three Dedicated Clock Input Pins
— Synchronous and Asynchronous Clocks
— Programmable Output Slew Rate Control to
Minimize Switching Noise
— Flexible Pin Placement
— Optimized Global Routing Pool Provides Global
Interconnectivity
— Lead-Free Package Options
Fu
Description
The ispLSI 2064 and 2064A are High Density Program-
mable Logic Devices. The devices contain 64 Registers,
64 Universal I/O pins, four Dedicated Input pins, three
Dedicated Clock Input pins, two dedicated Global OE
input pins and a Global Routing Pool (GRP). The GRP
provides complete interconnectivity between all of these
elements. The 2064 and 2064A feature 5V in-system
programmability and in-system diagnostic capabilities.
The ispLSI 2064 and 2064A offer non-volatile
reprogrammability of the logic, as well as the intercon-
nect, to provide truly reconfigurable systems.
The basic unit of logic on these devices is the Generic
Logic Block (GLB). The GLBs are labeled A0, A1…B7
(Figure 1). There are a total of 16 GLBs in the ispLSI 2064
and 2064A devices. Each GLB is made up of four
macrocells. Each GLB has 18 inputs, a programmable
AND/OR/Exclusive OR array, and four outputs which can
be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and dedicated
inputs. All of the GLB outputs are brought back into the
GRP so that they can be connected to the inputs of any
GLB on the device.
Functional Block Diagram
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
B3
B2
B1
B0
Input Bus
Output Routing Pool (ORP)
A2 GLB
Logic
Array
DQ
DQ
DQ
DQ
A4 A5 A6 A7
Input Bus
Output Routing Pool (ORP)
B7 B6 B5 B4
Input Bus
Output Routing Pool (ORP)
0139Bisp/2064
Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject
to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.
Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com August 2006
Select devices have been discontinued.
See Ordering Information section for product status.
2
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Functional Block Diagram
Figure 1. ispLSI 2064/A Functional Block Diagram
SDO/IN 2
Global Routing Pool
(GRP)
A0
A1
A3
Input Bus
Output Routing Pool (ORP)
B3
B2
B1
B0
Input Bus
Output Routing Pool (ORP)
A2
CLK 0
CLK 1
CLK 2
GOE 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 6
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
SDI/IN 0
MODE/IN 1
I/O 4
I/O 5
ispEN
RESET
0139B(1)isp/2064
I/O 63
I/O 62
I/O 61
I/O 60
I/O 59
I/O 58
I/O 57
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
Input Bus
Output Routing Pool (ORP)
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
I/O 25
I/O 26
I/O 27
I/O 28
I/O 29
I/O 30
Y0
Y1
Y2
I/O 31
Output Routing Pool (ORP)
Megablock
Input Bus
A4 A5 A6 A7
B7 B6 B5 B4
GOE 1
SCLK/IN 3
Generic Logic
Blocks (GLBs)
The devices also have 64 I/O cells, each of which is
directly connected to an I/O pin. Each I/O cell can be
individually programmed to be a combinatorial input,
output or bi-directional I/O pin with 3-state control. The
signal levels are TTL compatible voltages and the output
drivers can source 4 mA or sink 8 mA. Each output can
be programmed independently for fast or slow output
slew rate to minimize overall output switching noise.
Eight GLBs, 32 I/O cells, two dedicated inputs and two
ORPs are connected together to make a Megablock
(Figure 1). The outputs of the eight GLBs are connected
to a set of 32 universal I/O cells by two ORPs. Each ispLSI
2064 and 2064A device contains two Megablocks.
The GRP has as its inputs, the outputs from all of the
GLBs and all of the inputs from the bi-directional I/O cells.
All of these signals are made available to the inputs of the
GLBs. Delays through the GRP have been equalized to
minimize timing skew.
Clocks in the ispLSI 2064 and 2064A devices are se-
lected using the dedicated clock pins. Three dedicated
clock pins (Y0, Y1, Y2) or an asynchronous clock can be
selected on a GLB basis. The asynchronous or Product
Term clock can be generated in any GLB for its own clock.
Select devices have been discontinued.
See Ordering Information section for product status.
3
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Absolute Maximum Ratings 1
Supply Voltage Vcc ................................................... -0.5 to +7.0V
Input Voltage Applied..............................-2.5 to VCC +1.0V
Off-State Output Voltage Applied ...........-2.5 to VCC +1.0V
Storage Temperature ..................................... -65 to 150°C
Case Temp. with Power Applied .................... -55 to 125°C
Max. Junction Temp. (TJ) with Power Applied ............ 150°C
1. Stresses above those listed under the “Absolute Maximum Ratings” may cause permanent damage to the device. Functional
operation of the device at these or at any other conditions above those indicated in the operational sections of this specification
is not implied (while programming, follow the programming specifications).
DC Recommended Operating Condition
TA = 0°C to + 70°C
TA = -40°C to + 85°C
SYMBOL
Table 2 - 0005/2064
VCC
VIH
VIL
PARAMETER
Supply Voltage
Input High Voltage
Input Low Voltage
MIN. MAX. UNITS
4.75
4.5
2.0
0
5.25
5.5
Vcc+1
0.8
V
V
V
V
Commercial
Industrial
Table 2-0008/2064
PARAMETER
Data Retention
MINIMUM MAXIMUM UNITS
Erase/Reprogram Cycles
20
10000
–
–
Years
Cycles
Data Retention Specifications
Capacitance (TA=25°C, f=1.0 MHz)
C
SYMBOL
Table 2-0006/2064
C
PARAMETER
I/O Capacitance 9
UNITSTYPICAL TEST CONDITIONS
1
2
8Dedicated Input Capacitance
pf
pf
V = 5.0V, V = 2.0V
V = 5.0V, V = 2.0V
CC
CC I/O
IN
C
Clock Capacitance 15
3
pf V = 5.0V, V = 2.0V
CC Y
Select devices have been discontinued.
See Ordering Information section for product status.
4
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Output Load Conditions (see Figure 2)
Figure 2. Test Load
+ 5V
R1
R2CL*
Device
Output
Test
Point
*CL includes Test Fixture and Probe Capacitance.
DC Electrical Characteristics
Over Recommended Operating Conditions
Input Pulse Levels
Table 2-0003/2064
Input Rise and Fall Time
10% to 90%
Input Timing Reference Levels
Output Timing Reference Levels
Output Load
GND to 3.0V
1.5V
1.5V
See Figure 2
3-state levels are measured 0.5V from
steady-state active level.
-125
Others
≤ 2 ns
≤ 3 ns
TEST CONDITION R1 R2 CL
A 470Ω390Ω35pF
B∞390Ω35pF
470Ω390Ω35pF
Active High
Active Low
C
470Ω390Ω5pF
∞390Ω5pF
Active Low to Z
at V +0.5V
OL
Active High to Z
at V -0.5V
OH
Table 2-0004/2064
Switching Test Conditions
VOL
SYMBOL
1. One output at a time for a maximum duration of one second. V = 0.5V was selected to avoid test problems
by tester ground degradation. Characterized but not 100% tested.
2. Measured using four 16-bit counters.
3. Typical values are at V = 5V and T = 25°C.
4. Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption
section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to
estimate maximum I .
Table 2-0007/2064
1
VOH
IIH
IIL
IIL-isp
PARAMETER
IIL-PU
IOS
2, 4
ICC
Output Low Voltage
Output High Voltage
Input or I/O High Leakage Current
Input or I/O Low Leakage Current
ispEN Input Low Leakage Current
I/O Active Pull-Up Current
Output Short Circuit Current
Operating Power Supply Current
I = 8 mA
I = -4 mA
3.5V ≤ V ≤ V
0V ≤ V ≤ V (Max.)
0V ≤ V ≤ V
0V ≤ V ≤ V
V = 5V, V = 0.5V
V = 0.0V, V = 3.0V
f = 1 MHz
OL
OH
IN IL
IN CC
IN IL
IN IL
CC OUT
CLOCK
IL IH
CONDITION MIN. TYP. MAX. UNITS
3
–
2.4
–
–
–
–
–
–
–
–
–
–
–
–
–
–
95
95
0.4
–
10
-10
-150
-150
-200
175
–
V
V
μA
μA
μA
μA
mA
mA
mA
CC A
OUT
CC
CC
Commercial
Industrial
Select devices have been discontinued.
See Ordering Information section for product status.
5
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
External Timing Parameters
Over Recommended Operating Conditions
tpd1
UNITS
-100
MIN.
TEST
COND.
1. Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock.
2. Refer to Timing Model in this data sheet for further details.
3. Standard 16-bit counter using GRP feedback.
4. Reference Switching Test Conditions section.
Table 2 - 0030B/2064-130
1
4
3
1
tsu2 + tco1
( )
-80
MIN.MAX. MAX.
DESCRIPTION#2
PARAMETER
A 1 Data Propagation Delay, 4PT Bypass, ORP Bypass – 10.0 – 15.0 ns
tpd2 A 2 Data Propagation Delay – – ns
fmax A 3 Clock Frequency with Internal Feedback 100 – 81.0 – MHz
fmax (Ext.) – 4 Clock Frequency with External Feedback – – MHz
fmax (Tog.) – 5 Clock Frequency, Max. Toggle – – MHz
tsu1 – 6 GLB Reg. Setup Time before Clock, 4 PT Bypass – – ns
tco1 A 7 GLB Reg. Clock to Output Delay, ORP Bypass – – ns
th1 – 8 GLB Reg. Hold Time after Clock, 4 PT Bypass 0.0 – ns
tsu2 – 9 GLB Reg. Setup Time before Clock 8.0 – ns
tco2 – 10 GLB Reg. Clock to Output Delay – – ns
th2 – 11 GLB Reg. Hold Time after Clock 0.0 – ns
tr1 A 12 Ext. Reset Pin to Output Delay – – ns
trw1 – 13 Ext. Reset Pulse Duration 6.5 – ns
tptoeen B 14 Product Term OE, Enable – – ns
tptoedis C 15 Product Term OE, Disable – – ns
tgoeen B 16 Global OE, Enable – – ns
tgoedis C 17 Global OE, Disable – – ns
twh – 18 External Synchronous Clock Pulse Duration, High 4.5 – – ns
twl – 19 External Synchronous Clock Pulse Duration, Low 4.5 – – ns
77.0
111
6.5
5.0
–
–
6.0
–
13.5
–
15.0
15.0
9.0
9.0
13.0
57.0
100
9.0
0.0
11.0
0.0
10.0
5.0
5.0
18.5
6.5
8.0
17.0
18.0
18.0
12.0
12.0
-125
MIN.
– 7.5
–
125 –
–
–
–
–
0.0
6.0
–
0.0
–
5.0
–
–
–
–
4.0 –
4.0 –
100
125
5.0
4.0
–
–
4.5
–
10.0
–
12.0
12.0
7.0
7.0
10.0
MAX.
Select devices have been discontinued.
See Ordering Information section for product status.
6
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Internal Timing Parameters1
Over Recommended Operating Conditions
–
–
–
–
–
–
–
–
–
1.2
4.0
–
–
–
–
4.1
–
–
–
–
–
–
–
2.7
2.7
–
0.2
1.5
1.3
4.5
5.0
5.7
6.0
6.5
0.5
–
–
0.2
1.1
4.8
7.3
5.6
0.8
0.3
1.2
10.0
3.2
3.2
3.8
2.3
2.3
6.9
-125 -80
MAX.MIN. MAX. MIN. MAX.MIN.
–
–
–
–
–
–
–
–
–
0.8
3.0
–
–
–
–
3.3
–
–
–
–
–
–
–
2.3
2.3
–
–
–
–
–
–
–
–
–
–
1.4
6.0
–
–
–
–
5.6
–
–
–
–
–
–
–
3.6
3.6
–
-100
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Input Buffer Delay
Dedicated Input Delay
GRP Delay
4 Product Term Bypass Comb. Path Delay
4 Product Term Bypass Reg. Path Delay
1 Product Term/XOR Path Delay
20 Product Term/XOR Path Delay
XOR Adjacent Path Delay3
GLB Register Bypass Delay
GLB Register Setup Time before Clock
GLB Register Hold Time after Clock
GLB Register Clock to Output Delay
GLB Register Reset to Output Delay
GLB Product Term Reset to Register Delay
GLB Product Term Output Enable to I/O Cell Delay
GLB Product Term Clock Delay
ORP Delay
ORP Bypass Delay
Output Buffer Delay
Output Slew Limited Delay Adder
I/O Cell OE to Output Enabled
I/O Cell OE to Output Disabled
Global Output Enable
Clock Delay, Y0 to Global GLB Clock Line (Ref. clock)
Clock Delay, Y1 or Y2 to Global GLB Clock Line
Global Reset to GLB
1.8
4.4
2.6
8.1
6.8
8.0
8.8
9.8
1.3
–
–
0.4
1.6
8.6
9.0
10.2
2.0
0.5
2.0
10.0
4.6
4.6
7.4
3.6
3.6
11.4
tio
tdin
tgrp
t4ptbp
t4ptbp
t1ptxor
t20ptxor
txoradj
tgbp
tgsu
tgh
tgco
tgro
tptre
tptoe
tptck
torp
torpbp
tob
tsl
toen
todis
tgoe
tgy0
tgy1/2
tgr
UNITS
#2
Inputs
GRP
DESCRIPTION
GLB
PARAMETER
ORP
Outputs
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 2- 0036C/2064-130
0.5
2.2
1.7
5.8
5.8
6.8
7.3
8.0
0.5
–
–
0.3
1.3
6.1
8.6
7.1
1.4
0.4
1.6
10.0
4.2
4.2
4.8
2.7
2.7
9.2
Clocks
Global Reset
Select devices have been discontinued.
See Ordering Information section for product status.
7
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
ispLSI 2064/A Timing Model
GLB Reg
Delay
I/O Pin
(Output)
ORP
Delay
Feedback
Reg 4 PT Bypass
20 PT
XOR Delays
Control
PTs
I/O Pin
(Input)
Y0,1,2
GRP GLB Reg Bypass ORP Bypass
DQ
RST
RE
OE
CK
I/O Delay
I/O CellORPGLBGRPI/O Cell
#24
#25, 26, 27
#33, 34,
35
#43, 44
#36
Reset
Ded. In #21
#20 #28
#29, 30,
31, 32
#38,
39
GOE 0,1 #42
#40, 41
0491/2064
#22
Comb 4 PT Bypass #23
#37
#45
Derivations of
t
su,
t
h and
t
co from the Product Term Clock1
=
=
=
=
t
su Logic + Reg su - Clock (min)
(
t
io +
t
grp +
t
20ptxor) + (
t
gsu) - (
t
io +
t
grp +
t
ptck(min))
(#20 + #22 + #26) + (#29) - (#20 + #22 + #35)
(0.2 + 1.3 + 6.0) + (0.8) - (0.2 + 1.3 + 3.3)3.5 ns
=
=
=
=
t
h Clock (max) + Reg h - Logic
(
t
io +
t
grp +
t
ptck(max)) + (
t
gh) - (
t
io +
t
grp +
t
20ptxor)
(#20 + #22 + #35) + (#30) - (#20 + #22 + #26)
(0.2 + 1.3 + 5.6) + (3.0) - (0.2 + 1.3 + 6.0)2.6 ns
=
=
=
=
t
co Clock (max) + Reg co + Output
(
t
io +
t
grp +
t
ptck(max)) + (
t
gco) + (
t
orp +
t
ob)
(#20 + #22 + #35) + (#31) + (#36 + #38)
(0.2 + 1.3 + 5.6) + (0.2) + (0.8 + 1.2)9.4 ns
Table 2- 0042A-2064
Note: Calculations are based upon timing specifications for the ispLSI 2064/A-125L.
Select devices have been discontinued.
See Ordering Information section for product status.
8
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Power Consumption
Power consumption in the ispLSI 2064 and 2064A de-
vices depends on two primary factors: the speed at which
the device is operating and the number of Product Terms
used. Figure 4 shows the relationship between power
and operating speed.
Figure 4. Typical Device Power Consumption vs fmax
80
100
120
1 20 40 60 80 100 120 140
f
max (MHz)
I
CC (mA)
Notes: Configuration of Four 16-bit Counters
Typical Current at 5V, 25° C
ispLSI 2064/A
110
90
0127A/2064A
ICC can be estimated for the ispLSI 2064/A using the following equation:
ICC(mA) = 38 + (# of PTs * 0.33) + (# of nets * Max freq * 0.007)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of two GLB loads
on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions
and the program in the device, the actual ICC should be verified.
70
130
140
150
160
Select devices have been discontinued.
See Ordering Information section for product status.
9
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Pin Description
I/O 0 - I/O 3
I/O 4 - I/O 7
I/O 8 - I/O 11
I/O 12 - I/O 15
I/O 16 - I/O 19
I/O 20 - I/O 23
I/O 24 - I/O 27
I/O 28 - I/O 31
I/O 32 - I/O 35
I/O 36 - I/O 39
I/O 40 - I/O 43
I/O 44 - I/O 47
I/O 48 - I/O 51
I/O 52 - I/O 55
I/O 56 - I/O 59
I/O 60 - I/O 63
NAME DESCRIPTION
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
Table 2-0002A-08isp/2064
PLCC PIN NUMBERS
Input — Dedicated in-system programming enable pin. This pin is brought low to
enable the programming mode. When low, the MODE, SDI, SDO and SCLK
controls become active.
Input — This pin performs two functions. When ispEN is logic low, it functions
as an input pin to load programming data into the device. SDI/IN 0 also is used
as one of the two control pins for the ISP state machine. When ispEN is high, it
functions as a dedicated pin input.
Input — This pin performs two functions. When ispEN is logic low, it functions
as a pin to control the operation of the ISP state machine. When ispEN is high,
it functions as a dedicated input pin.
Output/Input — This pin performs two functions. When ispEN is logic low, it
functions as an output pin to read serial shift register data. When ispEN is high,
it functions as a dedicated input pin.
Input — This pin performs two functions. When ispEN is logic low, it functions
as a clock pin for the Serial Shift Register. When ispEN is high, it functions as
a dedicated input pin.
No ConnectNC1
VCC 21, 65
GND 1,
SDO/IN 2244
MODE/ IN 1242
SDI/ IN 0225
ispEN 23
RESET 24
SCLK/IN 3261
22, 43, 64
Y0, Y1, Y2 20, 66,
GOE 0, GOE 1 67, 84
63
Input/Output Pins — These are the general purpose I/O pins used by the logic
array.
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the clock inputs of
all the GLBs in the device.
Active Low (0) Reset pin which resets all registers in the device.
Ground (GND)
Vcc
26, 27, 28, 29,
30, 31, 32, 33,
34, 35, 36, 37,
38, 39, 40, 41,
2, 19, 62
45, 46, 47, 48,
49, 50, 51, 52,
53, 54, 55, 56,
57, 58, 59, 60,
68, 69, 70, 71,
72, 73, 74, 75,
76, 77, 78, 79,
80, 81, 82, 83,
3, 4, 5, 6,
7, 8, 9, 10,
11, 12, 13, 14,
15, 16, 17, 18
Select devices have been discontinued.
See Ordering Information section for product status.
10
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
GND 13, 38, 63, 88
VCC 12, 64
Ground (GND)
VCC
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK controls become active.
Input – This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the ISP state machine.
When ispEN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
No Connect.
ispEN 14
SDI/IN 02 16
MODE/IN 12 37
SDO/IN 22 39
SCLK/IN 32 60
NC11, 2, 10, 24,
25, 26, 27, 49,
50, 51, 52, 61,
74, 75, 76, 77,
89, 99, 100
DESCRIPTION
TQFP PIN NUMBERS
NAME
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 3 17, 18, 19, 20,
I/O 4 - I/O 7 21, 22, 23, 28,
I/O 8 - I/O 11 29, 30, 31, 32,
I/O 12 - I/O 15 33, 34, 35, 36,
I/O 16 - I/O 19 40, 41, 42, 43,
I/O 20 - I/O 23 44, 45, 46, 47,
I/O 24 - I/O 27 48, 53, 54, 55,
I/O 28 - I/O 31 56, 57, 58, 59,
I/O 32 - I/O 35 67, 68, 69, 70,
I/O 36 - I/O 39 71, 72, 73, 78,
I/O 40 - I/O 43 79, 80, 81, 82,
I/O 44 - I/O 47 83, 84, 85, 86,
I/O 48 - I/O 51 90, 91, 92, 93,
I/O 52 - I/O 55 94, 95, 96, 97,
I/O 56 - I/O 59 98, 3, 4, 5,
I/O 60 - I/O 63 6, 7, 8, 9
GOE 0, GOE 1 66, 87
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
Y0, Y1, Y2 11, 65, 62
RESET 15
Table 2-0002-2064b.eps
Select devices have been discontinued.
See Ordering Information section for product status.
11
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Pin Configuration
ispLSI 2064/A 84-Pin PLCC Pinout Diagram
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0
Y1
VCC
GND
Y2
NC1
SCLK/IN 32
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
1NC
Y0
VCC
GND
ispEN
RESET
2SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
NC1
GND
GOE 1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
2MODE/IN 1
GND
2SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
11 10
9 8 7 6 5 4 3 2 1
84 83 82 81 80 79 78 77 76 75
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
ispLSI 2064/A
Top View
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
0123A/2064
Select devices have been discontinued.
See Ordering Information section for product status.
12
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Pin Configuration
ispLSI 2064/A 100-Pin TQFP Pinout Diagram
1
NC
1
NC
I/O 57
I/O 58
I/O 59
I/O 60
I/O 61
I/O 62
I/O 63
1
NC
Y0
VCC
GND
ispEN
RESET
2
SDI/IN 0
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
1
NC
1
NC
NC
1
NC
1
I/O 38
I/O 37
I/O 36
I/O 35
I/O 34
I/O 33
I/O 32
GOE 0
Y1
VCC
GND
Y2
NC
1
SCLK/IN 3
2
I/O 31
I/O 30
I/O 29
I/O 28
I/O 27
I/O 26
I/O 25
NC
1
NC
1
NC
1
NC
1
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
NC
1
GND
GOE 1
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
NC
1
NC
1
1
NC
1
NC
I/O 7
I/O 8
I/O 9
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
2
MODE/IN 1
GND
2
SDO/IN 2
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
I/O 24
1
NC
1
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
57
56
55
54
53
52
51
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
58
ispLSI 2064/A
Top View
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function ca
p
abilit
y
.
0766A-2064-isp
Select devices have been discontinued.
See Ordering Information section for product status.
13
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Part Number Description
ispLSI 2064/A Ordering Information
Conventional Packaging
Device Number
ispLSI XXXXX XXX X X
Grade
Blank = Commercial
I = Industrial
X
Speed
125 = 125 MHz
f
max
100 = 100 MHz
f
max
80 = 81 MHz
f
max Power
L = Low
Package
J = PLCC
T = TQFP
JN = Lead-Free PLCC
TN = Lead-Free TQFP
–
Device Family
2064
1
2064A
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
81
81
84-Pin PLCC15
15
ispLSI 2064A-80LJ84
100-Pin TQFPispLSI 2064A-80LT100
FAMILY fmax (MHz)
125
125
100
ORDERING NUMBER PACKAGE
84-Pin PLCC
100-Pin TQFP
tpd (ns)
7.5
7.5
10
ispLSI
ispLSI 2064A-125LJ84
ispLSI 2064A-125LT100
84-Pin PLCCispLSI 2064A-100LJ84
100 100-Pin TQFP10 ispLSI 2064A-100LT100
COMMERCIAL
81
81
84-Pin PLCC15
15
ispLSI 2064-80LJ
1
100-Pin TQFPispLSI 2064-80LT
1
125
125
100
84-Pin PLCC
100-Pin TQFP
7.5
7.5
10
ispLSI 2064-125LJ
1
ispLSI 2064-125LT
1
84-Pin PLCCispLSI 2064-100LJ
1
100 100-Pin TQFP10 ispLSI 2064-100LT
1
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
FAMILY fmax (MHz)
81
81
ORDERING NUMBER PACKAGE
84-Pin PLCC
100-Pin TQFP
tpd (ns)
15
15
ispLSI
ispLSI 2064A-80LJ84I
ispLSI 2064A-80LT100I
INDUSTRIAL
81
81
84-Pin PLCC
100-Pin TQFP
15
15
ispLSI 2064-80LJI1
ispLSI 2064-80LTI1
1. Discontinued per PCN #02-06. Contact Rochester Electronics for available inventory.
Select devices have been discontinued.
See Ordering Information section for product status.
14
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Lead-Free Packaging
ispLSI 2064/A Ordering Information (Cont.)
Revision History
81
81
Lead-Free 84-Pin PLCC15
15
ispLSI 2064A-80LJN841
Lead-Free 100-Pin TQFPispLSI 2064A-80LTN100
FAMILY fmax (MHz)
125
1. 84-PLCC lead-free package is MSL4. Refer to “Handling Moisture Sensitive Packages” document on www.latticesemi.com.
125
100
ORDERING NUMBER PACKAGE
Lead-Free 84-Pin PLCC
Lead-Free 100-Pin TQFP
tpd (ns)
7.5
7.5
10
ispLSI
ispLSI 2064A-125LJN841
ispLSI 2064A-125LTN100
Lead-Free 84-Pin PLCCispLSI 2064A-100LJN841
100 Lead-Free 100-Pin TQFP10 ispLSI 2064A-100LTN100
COMMERCIAL
FAMILY fmax (MHz)
81
81
ORDERING NUMBER PACKAGE
Lead-Free 84-Pin PLCC
Lead-Free 100-Pin TQFP
tpd (ns)
15
15
ispLSI ispLSI 2064A-80LJN84I1
ispLSI 2064A-80LTN100I
INDUSTRIAL
1. 84-PLCC lead-free package is MSL4. Refer to “Handling Moisture Sensitive Packages” document on www.latticesemi.com.
Date Version
10
09
August 2006
—
Change Summary
Updated for lead-free package options.
Previous Lattice release.
Select devices have been discontinued.
See Ordering Information section for product status.
