10
Specifications ispLSI 2064/A
USE ispLSI 2064E FOR NEW DESIGNS
Pin Description
1. NC pins are not to be connected to any active signals, VCC or GND.
2. Pins have dual function capability.
GND 13, 38, 63, 88
VCC 12, 64
Ground (GND)
VCC
Input – Dedicated in-system programming enable input pin. This pin
is brought low to enable the programming mode. The MODE, SDI,
SDO and SCLK controls become active.
Input – This pin performs two functions. When ispEN is logic low, it
functions as an input pin to load programming data into the device.
SDI/IN 0 also is used as one of the two control pins for the ISP state
machine. When ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a pin to control the operation of the ISP state machine.
When ispEN is high, it functions as a dedicated input pin.
Output/Input – This pin performs two functions. When ispEN is logic
low, it functions as an output pin to read serial shift register data. When
ispEN is high, it functions as a dedicated input pin.
Input – This pin performs two functions. When ispEN is logic low, it
functions as a clock pin for the Serial Shift Register. When ispEN is
high, it functions as a dedicated input pin.
No Connect.
ispEN 14
SDI/IN 02 16
MODE/IN 12 37
SDO/IN 22 39
SCLK/IN 32 60
NC11, 2, 10, 24,
25, 26, 27, 49,
50, 51, 52, 61,
74, 75, 76, 77,
89, 99, 100
DESCRIPTION
TQFP PIN NUMBERS
NAME
Input/Output Pins - These are the general purpose I/O pins used by the
logic array.
I/O 0 - I/O 3 17, 18, 19, 20,
I/O 4 - I/O 7 21, 22, 23, 28,
I/O 8 - I/O 11 29, 30, 31, 32,
I/O 12 - I/O 15 33, 34, 35, 36,
I/O 16 - I/O 19 40, 41, 42, 43,
I/O 20 - I/O 23 44, 45, 46, 47,
I/O 24 - I/O 27 48, 53, 54, 55,
I/O 28 - I/O 31 56, 57, 58, 59,
I/O 32 - I/O 35 67, 68, 69, 70,
I/O 36 - I/O 39 71, 72, 73, 78,
I/O 40 - I/O 43 79, 80, 81, 82,
I/O 44 - I/O 47 83, 84, 85, 86,
I/O 48 - I/O 51 90, 91, 92, 93,
I/O 52 - I/O 55 94, 95, 96, 97,
I/O 56 - I/O 59 98, 3, 4, 5,
I/O 60 - I/O 63 6, 7, 8, 9
GOE 0, GOE 1 66, 87
Global Output Enable input pins.
Dedicated Clock input. This clock input is connected to one of the
clock inputs of all of the GLBs on the device.
Active Low (0) Reset pin which resets all of the registers in the device.
Y0, Y1, Y2 11, 65, 62
RESET 15
Table 2-0002-2064b.eps
Select devices have been discontinued.
See Ordering Information section for product status.