NJIUG355 Series SERIAL 1/0 REAL TIME CLOCK WH GENERAL DESCRIPTION The NJU6355 series is a serial 1/0 Real Time Clock suitable for 4 bits microprocessor. It contains quartz crystal osci!lator, counter, shift register, voltage regulator, voltage detector and in- terface contral ler. The NJUG355 required only 4-port of microprocessor for data transfer, and the microprocessor can receive the data at any time when the microprocessor requires. The operating voltage is as wide as 2.0V to 5.5V, consequently, the NJU6355 can count accurate time data even if the back up period. Furthermore, the long time back up is available as the current consumption during the back up period is MB PACKAGE OUTLINE WJUG3550 WJU6955XM M@ PIN CONFIGURATION Jess than 344A. oO a Voo XT Ol2 700 DATA @@ FEATURES XT C3 6h CLK @ Operating Voltage 72.0 ~ 5.5V Vss C4 sCE @ low operating current :3 A (Typ.) at 3.0V 30 wA (Max.) at 5.0V @ BCD Counts of Seconds, Minutes, Hours, Date, Days of Week, Month and Year @ Required only 4-port (DATA,CLK, CE and 1/0) @ Low Battery Detector(Low voltage alarm signal output) @ Automatic Leap Year Compensation @ Package Outline -- DIP 8/DMP 8 @ C-W0S Technology LINE UP VERSION OUTPUT DATA OSC. CAPACITOR F Seconds, Minutes, Hours, Days of Week H | Seconds, Minutes, Hours, Days of Heek 6355 E | Seconds, Minutes, Hours, Days of Week, Date, Month, Year | C,/C. on chip G | Seconds, Minutes, Hours, Days of Week, Date, Month, Year Ca on chip C./Ca on chip Ca on chip New Japan Radio Co,Ltd. __9.25NJIUG35 5 Series @ BLOCK 0) AGRAN XT >] geil lator/ Timer Counter xT +j Divider Sec. | Nin. | Hr. | bate| Day |Nonthy Year Vy O a Ct Ct DUU0d0 Sec.| Win.| Hr. [Date | Day [Month] Year f Shift Register p DATA Control ler/ Low Voltage Glock Counter Detector CE CLK Mi TERMINAL DESCRIPTION NO. | SYMBOL FU N JT ] O NW _ input/Gutput Select Terminal for DATA Terminal 1 1/0 "H": Input, "L": Output During the CE terminal is "L, the Data terminal is high impedance. 2] XI Quartz Crystal Connecting Terminal (#=32.768kHz) 3 XT Refer to the Line-Up Table for internal Cg, Cd value. Chip Enable Input Terminal (with pull-down resistance) 5 CE "H : Data Input/Output is available "L : Data terminal is high impedance 6 CLK Clock Input Terminal The Data Input/Output is synchronized by this clock. | When the CE terminal is "L the data terminal is high impedance. Serial Timer Data - Input/Output 1/0) Cf DATA Terminal H H Input 7 DATA L H Output H L High-|mpedance L L High-|mpedance 8 Yoo Power Supply (+5V) 4 Ves GND 9-26 New Japan Radio Co, Lid.NJUOUGS35 5 Series MB FUNCTIONAL DESCRIPTION 1. Timer Data structure The NJU6355 using BCD code which consisting of 4 bits per 1 digit. The calendar function including the last date of each month and the leap year calculation is executed automatical ly. The Unsed bit for the timer data is 70. < Timer Data Bit Hap > NSB LSBs Range Second 0} S | Sh | S47] S33 | S2 | SI | 80 0 - 59 Minute 0 | m | mo | m4 | mB {| m2 | mi | m 0 - 59 Hour 0 0 {| HS | H4 | HB | H2 | Ht | HO 0 - 23 Days of Week oO} W2 | Wt} WO 1-7 Date 0 0; DS | D4 7 D8 | D2 } OT | DO 1 - 31 Month 0 0 0 | M4 M3 | M2 | MT YY MO 1 - 12 Year v7 | Y | 5 | Y4 3 | 2 | Y1 | YO 0 - 99 2. Timer Data Reading When the 1/0 terminal is "L and the CE terminal is "H", timer data can read out. The output is LSB first and the output data strings (depending on the version) is shown below. The timer data is transfered from timer counter to shift register at rising edge of the chip enable on the CE terminal, and output the LSB of the timer data from the Data terminal . Afterward the timer data in the shift register shift by syhnchronized at the falling edge of clock signal on CLK terminal and output from the DATA terminal. [f the timer data is updated in the data output, there are one second difference between timer data and output data. , < E & G Version > i Year | Month} Date | Day | Hour | Minute | Second | The data is read out from LSB of Year, and first 52-bit is effective. < F & H Version > } Day | Hour {Minute | Second | The data is read out from LSB of Days of Week, and first 28-bit is effective. if the low voltage detector detect the low battery, (EE)s is written into each dighit of timer data and read out. The code of (EE}x is a warning for the data broken. New Japan Radio Co Lk 9.97NIU 6G635 5 Series < Read-Out Timing > FUUU UU Ue cE 4 ~~ , wi - [ CON X eX KKK K KEK EXE Year or Day ve Second +] REGISTER XX KX XX XK Xe Xe KX eK) The timer data is transfered to the shift register at rising @ @ edge of the CE(@) and LSB of the timer data is output to the Data termina). Afterward the timer data in the shift register shift by synchronized at falling edge of the CLK(@) then output to the Data terminal time-to-time. Data Output 3. Timer Data Writing When both of 1/0 terminal and CE terminal are "H", update is stopped, Oscillator divider is cleared, and the timer data can be written to the NJU6355. The timer data is written into the shift register from the Data terminal by synchronized with rising edge of the clock signal input from the CLK terminal, and the data is transfered from the shift register to the timer counter by synchronized with falling edge of the CE signal. in this time the second-counter is cleared to "}, and the oscillator divider start the operation. The input data strings are LSB first of each digit as shown below (the data format is depend on the version): < E & G Version > | Year | Month} Date | Day {| Hour | Minute | The data is written from LSB of Year and last 44-bit is effective. < F & H Version > | Day | Hour | Minute | The data is written from LSB of Days of Week and last 20-bit is effective. 9-28_________~ New japan Radio Co, Ltd.(orc) NJIOUG35S5 Series < Write-Down Timing > ao JU UU cE , _ a Data Input j SHIFT REGISTER L_ ( K The data is input into The data in the shift register the shift register at is transferred to the timer rising edge of the CLK. counter at this falling edge of the CE, then the oscil lator divider start the operation. 4. Low Voltage Detector The NJU6355 series incorporate the low battery detector. If the supply voltage reduse to the detection level, (FE)x is written into each digit of the shift register as warning code for the CPU. 5. Data Access The NJU6355 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of 5VE10%. It may be broken the data unless 5V10%. Thus, when the data access, CE terminal should be "H after the power supply rise to 5V+10%, then start the operation. Wi ABSOLUTE NAXIMUN RATINGS ( Ta=25C ) PARAMETER SYHBOL RATINGS UNIT _[ Supply Vol tage Vop - 0.3 ~ + 6.0 V Input Voltage Vin Vss-0.3 ~ Vpnt0.3 V Power Dissipation Po op MP nl Operating Temperature Tope - 30 ~ + 80 c Storage Temperature Tstg -~ 55 ~ +150 c New Japan Radio Co, Ltd. 9-29NJIJUG3SS5S5S Series MM ELECTRICAL CHARACTERISTICS OC Characteristics ( Vov=2.0V, Ta=25T ) PARAMETER SYMBOL CONDITIONS WIN TYP MAX UNIT Operating Currant Joo XT=32.768kHz, CE=OV 4.0 A Low Battery Detect Vit] Voer 1.1 1.7 V OC Characteristics ( Voo=5.0V10K, Ta=25C ) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNIT Operating Voltage Voo 4.5 5.5 V Operating Current lbp XT=32. 768kHz,CE=0V 15 BA 3-st Leakage Current Irs | DATA Terminal (CE=0V) -2.0 2.0 uA Input Leakage Current bin 1/0, CLK Terminals ~1.0 1.0 uA Input Current lex CE Terminal (CE=Voo) 20 MA Input Yottaze Vis | 1/0,CE,CLK,DATA Terminals | Voox0.8 Vop ae Vi. |1/0,CE.CLK,DATA Terminais | Vos Voox0.2 Vou DATA Terminal (1 on=~0. 4mA) 4.1 Output Voltage Vou. | DATA Terminal (lou=1-OmA) a4 | AC CHARACTERISTICS ( Von=5.0VE10%, Ta=25T, Ciz50pF ) PARAMETER | sYwOL | CONDITIONS win [tye | wax [UNIT CLK Pulse "H Period tews 0.47 5000 us CLK Pulse "L Period town 0.47 5000 [us CE Set-up Time Before CLK Rising tes 470 ns CE Hold Time After CLK Falling ten 20 ns 1/0 Set-up Time Before CLK Rising | ** 60 ns 1/0 Hold Time After CLK Falling tos 2 ne Write-Down Data Set-Up Tine twos "00 ns Write-Down Data Hold Time twpu 20 ns Data Delay Time After CLK Falling trop 200) (fs Rise/Fall Time ter 50 ns 9-30 New Japan Radio Co,Ltd.CE tes tra] J CE f+tes tea>4J Lo tos ~~ ton 0 L. , 4 - (in) _-- tout) Lie nee eee _ tf CLK Vex CLK 507% 50% toa ; Input Data MX ne XX 80% 807% 40 Vos ,AN | Qutput Data 20% HH APPLICATION CIRCUIT Main Power Vo Supply NJU6355 TF Voo DATA vo 8 CPU CLK CE | : NJUG35 5 Series New Japan Radio Co, Lhd. ta 9-31