ALT29538A - 2-Power - Datasheet.Live

FEATURES

• 2.5V to 20V Step Down Achieved Using Dual Input

• Output Voltage down to 0.8V

• 3A Output Capability (Up to 5A with Air Flow)

• Built in Low RDSON Power FETs (40 mΩ typ)

• Highly Integrated Design, Minimal Components

• 900 kHz Fixed Frequency Operation

• UVLO Detects Both VCC and VIN

• Over Temperature Protection

• Short Circuit Protection with Auto-Restart

• Wide BW Amp Allows Type II or III Compensation

• Programmable Soft Start

• Fast Transient Response

• High Efciency: Greater than 92% Possible

• Asynchronous Start-Up into a Pre-Charged Output

• Small 7mm x 4mm DFN Package

• U.S. Patent #6,922,041

The SP7651 is a high voltage synchronous step-down switching regulator optimized for high efciency. The part

is designed to be especially attractive for dual supply, 12V step down with 5V used to power the controller. This

lower VCC voltage minimizes power dissipation in the part. The SP7651 is designed to provide a fully integrated

buck regulator solution using a xed 900kHz frequency, PWM voltage mode architecture. Protection features

include UVLO, thermal shutdown and output short circuit protection. The SP7651 is available in the space saving

7mm X 4mm DFN package.TYPICAL APPLICATION CIRCUIT

DESCRIPTION

CBST

6800pF

4.7uH, Irate=3.87A

22uF

CVCC

2.2uF

SP7651

PGND

GND

VFB

COMP

UVIN

GND

VIN

13 LX 14

LX 15

LX 16

NC 17

BST 18

GND19

GND20

GND21

VCC 22

LX 23

LX 24

LX 25

LX 26

DBST

CSS

15nF

CP1

22pF

3.3V

0-3A

RSET

21.5kΩ,1%

GND

22uF

Notes:

12V

VIN

1. U1 Bottom-Side Layout should

have three contacts isolated from

one another: Vin, SWNODE, and GND.

SD101AWS

VOUT

RZ3

7.15kΩ,

CZ3

150pF

CZ2

1,000pF R1

68.1kΩ,1%

RZ2

15k,1%

CF1

100pF

fs=900Khz

+5V

VCC

ENABLE

2. RSET=54.48/(Vout-0.8V) (KOhm)

6.3V

(note 2)

16V

Solved by

SP7651

Wide Input Voltage Range 3Amp

900kHz Buck Regulator

SP7651

DFN PACKAGE

7mm x 4mm

BOTTOM VIEW

Heatsink Pad 1

Connect to Lx

Heatsink Pad 2

Connect to GND

Heatsink Pad 3

Connect to V

GND

COMP

UVIN

GND

BST

Pin 27

Pin 28

Pin 29

Solved by

Unless otherwise specied: -40°C < TAMB < 85°C, -40°C< Tj <125°C, 4.5V < VCC < 5.5V, 3V< Vin < 20V, BST=LX + 5V,

= GND = 0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.

The • denotes the specications which apply over the full temperature range, unless otherwise specied.

VCC .................................................................................................. 7V

VIN .................................................................................................. 22V

ILX .................................................................................................... 5A

BST ................................................................................................ 35V

LX-BST ...............................................................................-0.3V to 7V

LX ........................................................................................-1V to 20V

All other pins ............................................................-0.3V to VCC+0.3V

Storage Temperature ................................................... -65°C to 150°C

Power Dissipation ..................................................... Internally Limited

ESD Rating ........................................................................... 2kV HBM

Thermal Resistance ΟJC ........................................................... 5°C/W

ABSOLUTE MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

These are stress ratings only and functional operation of the device at these ratings or any other above those indicated in the operation sections

of the specications below is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

QUIESCENT CURRENT

Vcc Supply Current (No switching) 1.5 3 mA Vfb =0.9V

Vcc Supply Current (switching) 8 12 mA •

BST Supply Current (No switching) 0.2 0.4 mA Vfb =0.9V

BST Supply Current (switching) 4 6 mA •

PROTECTION: UVLO

Vcc UVLO Start Threshold 4.00 4.25 4.5 V

Vcc UVLO Hysteresis 100 200 300 mV

UVIN Start Threshold 2.3 2.5 2.65 V •

UVIN Hysteresis 200 300 400 mV

UVIN Input Current 1 µA UVIN= 3.0V

ERROR AMPLIFIER REFERENCE

Error Amplier Reference 0.792 0.800 0.808 V 2X Gain Cong., Measure

Vfb; Vcc =5 V, T=25°C

Error Amplier Reference

Over Line and Temperature 0.788 0.800 0.812 V •

Error Amplier Transconductance 6 mA/V

Error Amplier Gain 60 dB No Load

COMP Sink Current 150 µA Vfb =0.9V, COMP= 0.9V

COMP Source Current 150 µA Vfb =0.7V, COMP= 2.2V

Vfb Input Bias Current 50 200 nA Vfb = 0.8V

Internal Pole 4 MHz

COMP Clamp 2.5 V Vfb =0.7V, TA=25¼C

COMP Clamp Temp. Coefcient -2 mV/°C

ELECTRICAL CHARACTERISTICS

Unless otherwise specied: -40°C < TAMB < 85°C, -40°C<Tj<125°C, 4.5V < VCC < 5.5V, 3V<Vin<20V, BST=LX + 5V, LX = GND =

0.0V, UVIN = 3.0V, CVCC = 1µF, CCOMP = 0.1µF, CSS = 50nF, Typical measured at VCC = 5V.

The • denotes the specications which apply over the full temperature range, unless otherwise specied.

PARAMETER MIN. TYP. MAX. UNITS CONDITIONS

CONTROL LOOP: PWM COMPARATOR, RAMP & LOOP DELAY PATH

Ramp Amplitude 0.92 1.1 1.28 V

RAMP Offset 1.1 V TA = 25°C, RAMP COMP

until GH starts Switching

RAMP Offset Temp. Coefcient -2 mV/°C

GH Minimum Pulse Width 90 180 ns •

Maximum Controllable Duty Ratio 92 97 %Maximum Duty Ratio Measured

just before pulsing begins

Maximum Duty Ratio 100 %Valid for 20 cycles

Internal Oscillator Ratio 810 900 990 kHz •

TIMERS: SOFTSTART

SS Charge Current: 10 µA

SS Discharge Current: 1 mA • Fault Present, SS = 0.2V

PROTECTION: Short Circuit & Thermal

Short Circuit Threshold Voltage 0.2 0.25 0.3 V • Measured Vref (0.8V) - VFB

Hiccup Timeout 200 ms Vfb = 0.5V

Number of Allowable Clock Cycles at

100% Duty Cycle 20 Cycles

Minimum GL Pulse After 20 Cycles 0.5 Cycles Vfb = 0.7V

Thermal Shutdown Temperature 145 °C Vfb = 0.7V

Thermal Recovery Temperature 135 °C

Thermal Hysteresis 10 °C

OUTPUT: POWER STAGE

High Side Rdson 40 mΩVcc = 5V ; Iout = 3A

Tamb = 25°C

Synchronous FET Rdson 40 mΩVcc = 5V ; Iout = 3A

Tamb = 25°C

Maximum Output Current 3 A

General Overview

The SP7651 is a xed frequency, voltage

mode, synchronous PWM regulator opti-

mized for high efciency. The part has been

designed to be especially attractive for split

plane applications utilizing 5V to power the

controller and 2.5V to 20V for step down

conversion.

The heart of the SP7651 is a wide bandwidth

transconductance amplier designed to ac-

commodate Type II and Type III compensa-

tion schemes. A precision 0.8V reference,

present on the positive terminal of the error

amplier, permits the programming of the

output voltage down to 0.8V via the VFB pin.

The output of the error amplier, COMP,

which is compared to a 1.1V peak-to-peak

ramp, is responsible for trailing edge PWM

control. This voltage ramp, and PWM control

logic are governed by the internal oscillator

THEORY OF OPERATION

that accurately sets the PWM frequency to

900kHz.

The SP7651 contains two unique control

features that are very powerful in distributed

applications. First, asynchronous driver con-

trol is enabled during startup, to prohibit the

low side NFET from pulling down the output

until the high side NFET has attempted to

turn on. Second, a 100% duty cycle timeout

ensures that the low side NFET is periodically

enhanced during extended periods at 100%

duty cycle. This guarantees the synchronized

refreshing of the BST capacitor during very

large duty ratios.

The SP7651 also contains a number of

valuable protection features. Programmable

UVLO allows the user to set the exact VIN

value at which the conversion voltage can

PIN DESCRIPTION

Pin # Pin Name Description

1-3 Pgnd Ground connection for the synchronous rectier

4,8,19-21 GND Ground Pin. The control circuitry of the IC and lower power driver are refer-

enced to this pin. Return separately from other ground traces to the (-) terminal

of Cout.

5 Vfb Feedback Voltage and Short Circuit Detection pin. It is the inverting input of the

Error Amplier and serves as the output voltage feedback point for the Buck

Converter. The output voltage is sensed and can be adjusted through an exter-

nal resistor divider. Whenever Vfb drops 0.25V below the positive reference, a

short circuit fault is detected and the IC enters hiccup mode.

6 COMP Output of the Error Amplier. It is internally connected to the inverting input of

the PWM comparator. An optimal lter combination is chosen and connected

to this pin and either ground or Vfb to stabilize the voltage mode loop.

7 UVIN UVLO input for Vin voltage. Connect a resistor divider between Vin and UVin to

set minimum operating voltage.

9 SS Soft Start. Connect an external capacitor between SS and GND to set the soft

start rate based on the 10µA source current. The SS pin is held low via a 1mA

(min) current during all fault conditions.

10-13 Vin Input connection to the high side N-channel MOSFET. Place a decoupling

capacitor between this pin and Pgnd.

14-16,23-26 LX Connect an inductor between this pinand Vout

17 NC No Connect

18 BST High side driver supply pin. Connect BST to the external boost diode and ca-

pacitor as shown in the Typical Application Circuit on page 1. High side driver

is connected between BST pin and SWN pin.

22 Vcc Input for external 5V bias supply

safely begin down conversion, and an inter-

nal VCC UVLO ensures that the controller

itself has enough voltage to properly operate.

Other protection features include thermal

shutdown and short-circuit detection. In the

event that either a thermal, short-circuit, or

UVLO fault is detected, the SP7651 is forced

into an idle state where the output drivers are

held off for a nite period before a re-start

is attempted.

Soft Start

“Soft Start” is achieved when a power con-

verter ramps up the output voltage while

controlling the magnitude of the input sup-

ply source current. In a modern step down

converter, ramping up the positive terminal

of the error amplier controls soft start. As a

result, excess source current can be dened

as the current required to charge the output

capacitor.

IVIN = COUT * (∆VOUT / ∆TSOFT-START)

The SP7651 provides the user with the op-

tion to program the soft start rate by tying

a capacitor from the SS pin to GND. The

selection of this capacitor is based on the

10µA pullup current present at the SS pin

and the 0.8V reference voltage. Therefore,

the excess source can be redened as:

IVIN = COUT * (∆VOUT *10µA / (CSS * 0.8V)

Under Voltage Lock Out (UVLO)

The SP7651 contains two separate UVLO

comparators to monitor the internal bias (VCC)

and conversion (VIN) voltages independently.

The VCC UVLO threshold is internally set

to 4.25V, whereas the VIN UVLO threshold

is programmable through the UVIN pin.

When the UVIN pin is greater than 2.5V,

the SP7651 is permitted to start up pend-

ing the removal of all other faults. Both the

VCC and VIN UVLO comparators have been

designed with hysteresis to prevent noise

from resetting a fault.

Thermal and Short-Circuit

Protection

Because the SP7651 is designed to drive

large output current, there is a chance that the

power converter will become too hot. There-

fore, an internal thermal shutdown (145°C)

has been included to prevent the IC from

malfunctioning at extreme temperatures.

A short-circuit detection comparator has

also been included in the SP7651 to protect

against an accidental short at the output

of the power converter. This comparator

constantly monitors the positive and nega-

tive terminals of the error amplier, and if

the VFB pin falls more than 250mV (typical)

below the positive reference, a short-circuit

fault is set. Because the SS pin overrides the

internal 0.8V reference during soft start, the

SP7651 is capable of detecting short-circuit

faults throughout the duration of soft start as

well as in regular operation.

Handling of Faults:

Upon the detection of power (UVLO), ther-

mal, or short-circuit faults, the SP7651 is

forced into an idle state where the SS and

COMP pins are pulled low and the NFETS

are held off. In the event of UVLO fault, the

SP7651 remains in this idle state until the

UVLO fault is removed. Upon the detection

of a thermal or short-circuit fault, an internal

200ms timer is activated. In the event of a

short-circuit fault, a re-start is attempted im-

mediately after the 200ms timeout expires.

Whereas, when a thermal fault is detected

the 200ms delay continuously recycles and a

re-start cannot be attempted until the thermal

fault is removed and the timer expires.

Error Amplier and Voltage Loop

Since the heart of the SP7651 voltage error

loop is a high performance, wide bandwidth

transconductance amplifier, great care

should be taken to select the optimal compen-

sation network. Because of the amplier’s

THEORY OF OPERATION

current- limited (+/-150µA) transconduc-

tance, there are many ways to compensate

the voltage loop or to control the COMP pin

externally. If a simple, single pole, single zero

response is desired, then compensation can

be as simple as an RC circuit to Ground. If

a more complex compensation is required,

then the amplier has enough bandwidth

(45° at 4 MHz) and enough gain (60dB) to

run Type III compensation schemes with ad-

equate gain and phase margins at crossover

frequencies greater than 50kHz.

The common mode output of the error am-

plier is 0.9V to 2.2V. Therefore, the PWM

voltage ramp has been set between 1.1V and

2.2V to ensure proper 0% to 100% duty cycle

capability. The voltage loop also includes

two other very important features. One is

asynchronous startup mode. Basically, the

synchronous rectier cannot turn on unless

the high side NFET has attempted to turn

on or the SS pin has exceeded 1.7V. This

feature prevents the controller from “dragging

down” the output voltage during startup or in

fault modes. The second feature is a 100%

duty cycle timeout that ensures synchronized

refreshing of the BST capacitor at very high

duty ratios. In the event that the high side

NFET is on for 20 continuous clock cycles,

a reset is given to the PWM ip-op half

way through the 21st cycle. This forces GL

to rise for the cycle, in turn refreshing the

BST capacitor.

Power MOSFETs

The SP7651 contains a pair of integrated low

resistance N MOSFETs designed to drive

up to 3A of output current. Maximum output

current could be limited by thermal limitations

of a particular application. The SP7651

incorporates a built-in over-temperature

protection to prevent internal overheating.

Voltage

V(V IN)

-0V

-V(Diode) V

V(V IN)+V(V CC )

BST

Voltage

V(V CC )

TIME

SWN

Voltage

VBST

VSWN

V(V CC)

The SP7651 can be set to different output

voltages. The relationship in the following

formula is based on a voltage divider from

the output to the feedback pin VFB, which is

set to an internal reference voltage of 0.80V.

Standard 1% metal lm resistors of surface

mount size 0603 are recommended.

Vout = 0.80V ( R1 / R2 + 1 ) =>

Where R1 = 68.1KΩ and for Vout = 0.80V

setting, simply remove R2 from the board.

Furthermore, one could select the value

of the R1 and R2 combination to meet the

exact output voltage setting by restricting

R1 resistance range such that 50KΩ < R1 <

100KΩ for overall system loop stability.

Setting Output Voltages

[(Vout /0.80V) -1]

R2=

APPLICATIONS INFORMATION

Inductor Selection

There are many factors to consider in se-

lecting the inductor, including: core material,

inductance vs. frequency, current handling

capability, efciency, size and EMI. In a typi-

cal SP7651 circuit, the inductor is chosen

primarily by operating frequency, saturation

current and DC resistance. Increasing the

inductor value will decrease output voltage

ripple, but degrade transient response. Low

inductor values provide the smallest size, but

cause large ripple currents, poor efciency

and require more output capacitance to

smooth out the larger ripple current. The

inductor must be able to handle the peak

current at the switching frequency without

saturating, and the copper resistance in the

winding should be kept as low as possible to

minimize resistive power loss. A good com-

promise between size, loss and cost is to set

the inductor ripple current to be within 20%

to 40% of the maximum output current.

The switching frequency and the inductor

operating point determine the inductor value

as follows:

where:

Fs = switching frequency

Kr = ratio of the AC inductor ripple current

to the maximum output current

The peak-to-peak inductor ripple current

is:

Once the required inductor value is se-

lected, the proper selection of core mate-

rial is based on peak inductor current and

efciency requirements. The core must be

large enough not to saturate at the peak

inductor current...

...and provide low core loss at the high switch-

ing frequency. Low cost powdered-iron cores

are inappropriate for 900kHz operation

Gapped ferrite inductors are widely available

for consideration. Select devices that have

operating data shown up to 1MHz. Ferrite

materials, on the other hand, are more

expensive and have an abrupt saturation

characteristic with the inductance dropping

sharply when the peak design current is

exceeded. Nevertheless, they are preferred

at high switching frequencies because they

present very low core loss and the design

only needs to prevent saturation. In general,

ferrite or molypermalloy materials will be

used with the SP7651.

Optimizing Efciency

The power dissipated in the inductor is equal

to the sum of the core and copper losses. To

minimize copper losses, the winding resis-

tance needs to be minimized, but this usu-

ally comes at the expense of using a larger

inductor. Core losses have a more signicant

contribution at low output current where the

copper losses are at a minimum, and can

typically be neglected at higher output cur-

rents where the copper losses dominate.

Core loss information is usually available

from the magnetics vendor. Proper inductor

selection can affect the resulting power sup-

ply efciency by more than 15-20%!

The copper loss in the inductor can be cal-

culated using the following equation:

where IL(RMS) is the RMS inductor current

that can be calculated as follows:

Vout (Vin(max) - Vout)

Vin(max) fs Kr Iout(max)

Ipp=Vout(Vin(max) - Vout)

Vin(max) fs L

Ipeak= iout(max) + Ipp

PL(cu)=i2L(rms) rwinding

IL(rms)=iout(max) 1 + ( )2

Ipp

Iout(max)

Output Capacitor Selection

The required ESR (Equivalent Series Re-

sistance) and capacitance drive the selec-

tion of the type and quantity of the output

capacitors. The ESR must be small enough

that both the resistive voltage deviation due

to a step change in the load current and

the output ripple voltage do not exceed

the tolerance limits expected on the output

voltage. During an output load transient,

the output capacitor must supply all the ad-

ditional current demanded by the load until

the SP7651 adjusts the inductor current to

the new value.

In order to maintain VOUT, the capacitance

must be large enough so that the output

voltage is held up while the inductor current

ramps up or down to the value correspond-

ing to the new load current. Additionally, the

ESR in the output capacitor causes a step

in the output voltage equal to the current.

Because of the fast transient response and

inherent 100% to 0% duty cycle capability

provided by the SP7651 when exposed to

an output load transient, the output capacitor

is typically chosen for ESR, not for capaci-

tance value.

The ESR of the output capacitor, combined

with the inductor ripple current, is typically

the main contributor to output voltage ripple.

The maxi

mum allowable ESR required to

maintain a specied output voltage ripple

can be calculated by:

where:

∆VOUT = Peak-to-Peak Output Voltage

Ripple

IPK-PK = Peak-to-Peak Inductor Ripple Cur-

rent

The total output ripple is a combination of

the ESR and the output capacitance value

and can be calculated as follows:

∆VOUT =

(

IPP (1 – D)

)

+ (IPPRESR)2

COUTFS

FS = Switching Frequency

D = Duty Cycle

COUT = Output Capacitance Value

Input Capacitor Selection

The input capacitor should be selected for

ripple current rating, capacitance and volt-

age rating. The input capacitor must meet

the ripple current requirement imposed

by the switching current. In continuous

conduction mode, the source current of

the high-side MOSFET is approximately

a square wave of duty cycle VOUT/VIN.

Most of this current is supplied by the

input bypass capacitors. The RMS value

of input capacitor current is determined at

the maximum output

current and under the

assumption that the peak-

to-peak inductor ripple current is low; it is given

by:

ICIN(rms) = IOUT(max)

√

D(1 - D)

The worse case occurs when the duty cycle

D is 50% and gives an RMS current value

equal to IOUT/2. Select input capacitors with

adequate ripple current rating to ensure reli-

able operation.

The power dissipated in the input capaci-

tor is:

This can become a signicant part of power

losses in a converter and hurt the overall

energy transfer efciency. The input volt-

age ripple primarily depends on the input

capacitor ESR and capacitance. Ignoring

the inductor ripple current, the input voltage

ripple can be determined by:

The capacitor type suitable for the output

capacitors can also be used for the input ca-

pacitors. However, exercise extra caution

APPLICATIONS INFORMATION

∆Vout

Ipk-pk

Pon= i2on(rms) resr(cin)

∆Vin=iout(max) resr(cin) +

Iout(max) Vout (Vin-Vout)

FscinVin2

Resr ≤

APPLICATIONS INFORMATION

when tantalum capacitors are used. Tantalum

capacitors are known for catastrophic failure

when exposed to surge current, and input

capacitors are prone to such surge current

when power supplies are connected “live”

to low impedance power sources.

Loop Compensation Design

The open loop gain of the whole system

can be divided into the gain of the error

amplier, PWM modulator, buck converter

output stage, and feedback resistor divider.

In order to cross over at the selected fre-

quency FCO, the gain of the error amplier

compensates for the attenuation caused by

the rest of the loop at this frequency. The

goal of loop compensation is to manipulate

loop frequency response such that its gain

crosses over 0db at a slope of -20db/dec.

The rst step of compensation design is to

pick the loop crossover frequency.

High crossover frequency is desirable for

fast transient response, but often jeopardizes

the higher than the ESR zero but less than

1/5 of the switching frequency. The ESR

zero is contributed by the ESR associated

with the output capacitors and can be de-

termined by:

SP7651 Voltage Mode Control Loop with Loop Dynamic

(SRz2Cz2+1)(SR1Cz3+1) (SR

ESR

OUT

+ 1)

[S^2LC

OUT

+S(R

ESR

) C

OUT

+1]

SR1Cz2(SRz3Cz3+1)(SRz2Cp1+1) V

RAMP_PP

OUT

(Volts)

REF

(Volts)

Notes: R

ESR

= Output Capacitor Equivalent Series Resistance.

= Output Inductor DC Resistance.

RAMP_PP

= SP6132 Internal RA MP Amplitude Peak to Peak V oltage.

Condition: Cz2 >> Cp1 & R1 >> Rz3

Output Load Resistance >> R

ESR

& R

REF

+ R

)

or V

OUT

FBK

(Volts)

Type III V oltage Loop

Compensation

AMP

(s) Gain Block

PWM Stage

PWM

Gain

Block

Output Stage

OUT

(s) Gain

Block

Voltage Feedback

FBK

Gain Block

Denitions:

RESR = Output Capacitor Equivalent Series Resistance

RDC = Output Inductor DC Resistance

RRAMP_PP = SP7651 internal RAMP Amplitude Peak-to-Peak Voltage

system stability. Crossover frequency should

be higher than the ESR zero but less than

1/5 of the switching frequency. The ESR

zero is contributed by the ESR associated

with the output capacitors and can be de-

termined by:

ƒZ(ESR) = 1 .

2π COUT RESR

The next step is to calculate the complex

conjugate poles contributed by the LC

output lter,

ƒP(LC) = 1 .

2π

√

L COUT

When the output capacitors are Ceramic

type, the SP7651 Evaluation Board requires

a Type III compensation circuit to give a phase

boost of 180° in order to counteract the effects

of an underdamped resonance of the output

lter at the double pole frequency.

Bode Plot of Type III Error Amplier Compensation.

CP1

RZ2

CZ2

VFB COMP

-0.8V

CF1

VOUT

68.1k, 1% RSET

CZ3

RZ3

RSET =54.48/ (V OUT -0.8) (kΩ)

Type III Error Amplier Compensation Circuit

APPLICATIONS INFORMATION

Frequency

(Hz)

Error Amplifier Gain

Bandwidth Product

Condition:

C22 >> CP1, R1 >> RZ3

20 Log (RZ2/R1)

Gain

(dB)

1/6.28(R22) (CZ2)

1/6.28(R1) (CZ3)

1/6.28(R1) (CZ2)

1/6.28(RZ2) (CP1)

1/6.28(RZ3) (CZ3)

SP765X Thermal Resistance

The SP765X family has been tested with a

variety of footprint layouts along with differ-

ent copper area and thermal resistance has

been measured. The layouts were done on

4 layer FR4 PCB with the top and bottom

layers using 3oz copper and the power and

ground layers using 1oz copper.

For the Minimum footprint, only about 0.1

square inch of 3 ounces of copper was

used on the top or footprint layer, and this

layer had no vias to connect to the 3 other

layers. For the Medium footprint, about 0.7

square inches of 3 ounces of copper was

used on the top layer, but vias were used

to connect to the other 3 layers. For the

Maximum footprint, about 1.0 square inch

of 3 ounces of copper was used on the top

layer and many vias were used to connect

to the 3 other layers.

The results show that only about 0.7 square

inches of 3 ounces of copper on the top

layer and vias connecting to the 3 other

layers are needed to get the best thermal

resistance of 36°C/W. Adding area on the

top beyond the 0.7 square inches did not

reduce thermal resistance.

Using a minimum of 0.1 square inches of

(3 ounces of) Copper on the top layer with

no vias connecting to the 3 other layers

produced a thermal resistance of 44°C/W.

This thermal impedance is only 22% higher

than the medium and large footprint layouts,

indicating that space constrained designs

can still benet thermally from the Powerblox

family of ICs. This indicates that a minimum

footprint of 0.1 square inch, if used on a

4 layer board, can produce 44°C/W ther-

mal resistance. This approach is still very

worthwhile if used in a space constrained

design.

The following page shows the footprint

layouts from an ORCAD le. The thermal

SP765X Thermal Resistance

4 Layer Board:

Top Layer 3ounces Copper

GND Layer 1ounce Copper

Power Layer 1ounce Copper

Bottom Layer 3ounces Copper

Minimum Footprint: 44°C/W

Top Layer: 0.1 square inch

No Vias to other 3 Layers

Medium Footprint: 36°C/W

Top Layer: 0.7 square inch

Vias to other 3 Layers

Maximum Footprint: 36°C/W

Top Layer: 1.0 square inch

Vias to other 3 Layers

APPLICATIONS INFORMATION

data was taken for still air, not with

forced air. If forced air is used, some

improvement in thermal resistance

would be seen.

TYPICAL PERFORMANCE CHARACTERISITICS

PACKAGE: 26 PIN DFN

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the applica-

tion or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

ORDERING INFORMATION

Sipex Corporation

Headquarters and

Sales Ofce

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Part Number Package Code RoHS MIN. Temp. (°C) MAX. Temp.(°C) Status Pack Quantity

SP7651ER DFN26 -40 85 Active Bulk

SP7651ER/TR DFN26 -40 85 Active 500 Tape & Reel

SP7651ER-L DFN26 ▪-40 85 Active Bulk

SP7651ER-L/TR DFN26 ▪-40 85 Active 500 Tape & Reel