APU3073O - Advanced Power Electronics Corp. USA

APU3073

200815061-1/17

Data and specifications subject to change without notice.

DESCRIPTION

The APU3073 controller IC is designed to provide a low

cost synchronous Buck regulator for on-board DC to DC

converter for multiple output applications.

The outputs can be programmed as low as 0.8V for low

voltage applications.

Selectable over-current protection is provided by using

external MOSFET's on-resistance for optimum cost and

performance.

This device features a programmable frequency set from

200KHz to 400KHz, under-voltage lockout for all input

supplies, an external programmable soft-start function

as well as output under-voltage detection that latches

off the device when an output short is detected.

Synchronous Controller plus one LDO controller

Current Limit using MOSFET Sensing

Single 5V/12V Supply Operation

Programmable Switching Frequency up to

400KHz

Soft-Start Function

Fixed Frequency Voltage Mode

Precision Reference Voltage Available

Uncommitted Error Amplifier available for DDR

voltage tracking application

PACKAGE ORDER INFORMATION

FEATURES

SYNCHRONOUS PWM CONTROLLER WITH

OVER-CURRENT PROTECTION / LDO CONTROLLER

APPLICATIONS

DDR memory source sink VTT application

Low cost on-board DC to DC such as

12V/5V to output voltages as low as 0.8V

Graphic Card

Hard Disk Drive

Multi-Output Applications

RoHS Compliant

TA (°C) DEVICE PACKAGE

0 To 70 APU3073O 16-Pin TSSOP

Technology Licensed from International Rectifier

Figure 1 - Typical application of APU3073.

TYPICAL APPLICATION

APU3073

Vcc

VcL

HDrv

LDrv

Fb1

Gnd

Comp

SS/SD

OUT1

+5V

OCSet

PGnd

Drv2

Fb2

3.3V

OUT2

C11

C6 C7

C10

R10

R11

VcH

REF

12V

0.1uF C4 D1

2/17

APU3073

ABSOLUTE MAXIMUM RATINGS

Vcc Supply Voltage ................................................... -0.5 - 25V

VcL, VcH Supply Voltage .......................................... -0.5 - 25V

Storage Temperature Range ...................................... -65°C To 150°C

Operating Junction Temperature Range ..................... 0°C To 125°C

CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device.

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

Feedback Voltage

Fb Voltage

Fb Voltage Line Regulation

Reference Voltage

Ref Voltage Initial Accuracy

Drive Current

UVLO

UVLO Threshold - Vcc

UVLO Hysteresis - Vcc

UVLO Threshold - VcH

UVLO Hysteresis - VcH

UVLO Threshold - Fb1

UVLO Hysteresis - Fb1

Supply Current

Vcc Dynamic Supply Current

Vc Dynamic Supply Current

Vcc Static Supply Current

Vc Static Supply Current

Soft-Start Section

Charge Current

5<Vcc<12

Note 1

Supply Ramping Up

Fb Ramping Down

Freq=200KHz, CL=1500pF

SS=0V

0.784

3.9

3.3

0.3

0.8

0.2

0.8

4.4

0.25

3.5

0.2

0.4

0.1

3.5

0.816

0.625

0.816

4.8

3.7

0.5

uJA=908C/W

Fb2

Drv2

SS/SD

Comp

Fb1

REF

OCSet

VcH

HDrv

Gnd

PGnd

LDrv

VcL

Vcc

PACKAGE INFORMATION

16-Pin TSSOP (O)

VFB

LREG

VREF

IREF

UVLO VCC

UVLO VCH

UVLO Fb1

Dyn ICC

Dyn IC

ICCQ

ICQ

SS IB

ELECTRICAL SPECIFICATIONS

Unless otherwise specified, these specifications apply over Vcc=5V, VcL=VcH=12V and TA=0°C to 70°C. Low duty

cycle pulse testing is used which keeps junction and case temperatures equal to the ambient temperature.

APU3073

3/17

PARAMETER SYM TEST CONDITION MIN TYP MAX UNITS

Error Amp

Fb Voltage Input Bias Current

VP Voltage Range

Transconductance

Oscillator

Frequency

Ramp Amplitude

Output Drivers

Rise Time

Fall Time

Dead Band Time

Max Duty Cycle

Min Duty Cycle

LDO Controller Section

Drive Current

Fb Voltage

Input Bias Current

Thermal Shutdown

Current Limit

OC Threshold Set Current

OC Comp Off-Set Voltage

SS=3V

SS=0V

Note 1

Rt=100K

Rt=50K

Note 1

CLOAD=1500pF

Fb=0.7V, Freq=200KHz

Fb=0.9V

Note 1

-5

0.8

180

340

0.784

-1

-5

-0.1

700

210

400

1.25

100

0.8

-0.1

150

mmho

KHz

VPP

1.5

240

460

100

0.816

PIN DESCRIPTIONS

Note 1: Guaranteed by design but not tested in production.

IFB1

IFB2

Freq

VRAMP

TDB

DMAX

DMIN

Drv1

IOCSET

VOC(OFFSET)

These pins provide feedback for the linear regulator controllers.

Outputs of the linear regulator controllers.

A resistor should be connected from this pin to ground for setting the switching frequency.

This pin provides soft-start for the switching regulator. An internal current source charges

an external capacitor that is connected from this pin to ground which ramps up the output

of the switching regulator, preventing it from overshooting as well as limiting the input

current. The converter can be shutdown by pulling this pin down below 0.4V.

Compensation pin of the error amplifier. An external resistor and capacitor network is

typically connected from this pin to ground to provide loop compensation.

This pin is connected directly to the output of the switching regulator via resistor divider to

provide feedback to the Error amplifier.

Non-inverting input of error amplifier.

Reference voltage.

This pin provides biasing for the internal blocks of the IC as well as powers the LDO

controller. A minimum of 1mF, high frequency capacitor must be connected from this pin

to ground to provide peak drive current capability.

This pin powers the low side output driver and can be connected either to Vcc or separate

supply. A minimum of 1mF, high frequency capacitor must be connected from this pin to

ground to provide peak drive current capability.

Output driver for the synchronous power MOSFET.

PIN# PIN SYMBOL PIN DESCRIPTION

Fb2

Drv2

SS / SD

Comp

Fb1

VP1

VREF

Vcc

VcL

LDrv

4/17

APU3073

Figure 2 - Simplified block diagram of the APU3073.

This pin serves as the separate ground for MOSFET's driver and should be connected to

system's ground plane.

This pin serves as analog ground for internal reference and control circuitry. A high fre-

quency capacitor must be connected from Vcc pin to this pin for noise free operation.

Output driver for the high side power MOSFET. This pin should not go negative (below

ground), this may cause problem for the gate drive circuit. It can happen when the inductor

current goes negative (Source/Sink), soft-start at no load and for the fast load transient

from full load to no load. To prevent negative voltage at gate drive, a low forward voltage

drop diode might be connected between this pin and ground.

This pin is connected to a voltage that must be at least 4V higher than the bus voltage of

the switcher (assuming 5V threshold MOSFET) and powers the high side output driver. A

minimum of 1mF, high frequency capacitor must be connected from this pin to ground to

provide peak drive current capability.

This pin is connected to the Drain of the lower MOSFET via an external resister and it

provides the positive sensing for the internal current sensing circuitry. The external resis-

tor programs the current limit threshold depending on the RDS(ON) of the power MOSFET.

An external capacitor can be placed in parallel with the programming resistor to provide

high frequency noise filtering.

PIN# PIN SYMBOL PIN DESCRIPTION

PGnd

Gnd

HDrv

VcH

OCSet

BLOCK DIAGRAM

13 Gnd

20uA

64uA

Max

POR Oscillator

Error Amp

Error Comp

Reset Dom

POR

0.4V

FbLo Comp

VcH

HDrv

VcL

LDrv

PGnd

SS/SD

Fb1

Comp

25K

25K R

CS Comp

OCSet

3V 20uA

REF

Drv2

0.8V

Fb2

Bias

Generator

1.25V

POR

VcH

UVLO

3.5V / 3.3V

Vcc

4.2V / 4.0V

0.8V 8

9Vcc

Vcc

1.25V

TSD

APU3073

5/17

THEORY OF OPERATION

Introduction

The APU3073 is designed for a two output application

and it includes one synchronous buck controller and a

linear regulator controller. The PWM section is a fixed

frequency, voltage mode and consists of a precision ref-

erence voltage, an uncommitted error amplifier, an inter-

nal oscillator, a PWM comparator, an internal regulator,

a comparator for current limit, gate drivers, soft-start and

shutdown circuits (see Block Diagram).

The output voltage of the synchronous converter is set

and controlled by the output of the error amplifier; this is

the amplified error signal from the sensed output voltage

and the voltage on non-inverting input of error amplifier(VP).

This voltage is compared to a fixed frequency linear

sawtooth ramp and generates fixed frequency pulses of

variable duty-cycle, which drives the two N-channel ex-

ternal MOSFETs.

The timing of the IC is provided through an internal oscil-

lator circuit which uses on-chip capacitor. The oscilla-

tion frequency is programmable between 200KHz to

400KHz by using an external resistor. Figure 14 shows

switching frequency vs. external resistor (Rt).

Soft-Start

The APU3073 has a programmable soft-start to control

the output voltage rise and limit the current surge at the

start-up. To ensure correct start-up, the soft-start se-

quence initiates when the input supplies rise above their

threshold and generates the Power On Reset (POR) sig-

nal. Soft-start function operates by sourcing an internal

current to charge an external capacitor to about 3V. Ini-

tially, the soft-start function clamps the E/A’s output of

the PWM converter and disables the short circuit pro-

tection. During the power up of the buck converter, the

output starts at zero and voltage at Fb1 is below 0.4V.

The feedback UVLO is disabled during this time by in-

jecting a current (64mA) into the Fb1. This generates a

voltage about 1.6V (64mA325K) across the negative

input of E/A and positive input of the feedback UVLO

comparator (see Fig3).

Figure 3 - APU3073 soft-start diagram.

The magnitude of this current is inversely proportional to

the voltage at soft-start pin.

The 20mA current source starts to charge up the exter-

nal capacitor. In the mean time, the soft-start voltage

ramps up, the current flowing into Fb1 pin starts to de-

crease linearly and so does the voltage at the positive

pin of feedback UVLO comparator and the voltage nega-

tive input of E/A.

When the soft-start capacitor is around 1V, the current

flowing into the Fb1 pin is approximately 32mA. The volt-

age at the positive input of the E/A is approximately:

The E/A will start to operate and the output voltage starts

to increase. As the soft-start capacitor voltage contin-

ues to go up, the current flowing into the Fb1 pin will

keep decreasing. Because the voltage at pin of E/A is

regulated to reference voltage 0.8V, the voltage at the

Fb1 is:

32mA325K = 0.8V

VFB1 = 0.8-25K3(Injected Current)

20uA

64uA

Max

POR

Error Amp

64uA

25K=1.6V

When SS=0 POR

0.4V

Feeback

UVLO Comp

SS/SD

Fb1

Comp

25K

0.8V

25K

HDrv

LDrv

6/17

APU3073

LDO Controller

The LDO section is powered directly from Vcc. The out-

put of LDO can be set as low as 0.8V and can be pro-

grammed to higher voltages by using two external resis-

tors.

Supply Voltage Under-Voltage Lockout

The under-voltage lockout circuit assures that the

MOSFET driver outputs, remain in the off state when-

ever the supply voltage drops below set parameters. Lock-

out occurs if Vcc or VcH fall below 4.0V and 3.3V re-

spectively. Normal operation resumes once these volt-

ages rise above the set values.

Shutdown

The PWM section can be shutdown by pulling the soft-

start pin below 0.4V. The control MOSFET turns off and

the synchronous MOSFET turns on during shutdown.

Over-Current Protection

Over-current protection is achieved with a cycle by cycle

scheme and it is performed by sensing current through

the RDS(ON) of low side MOSFET. As shown in Figure 5,

an external resistor (RSET) is connected between OCSet

pin and the drain of low side MOSFET (Q2) and sets the

current limit set point. The internal current source devel-

ops a voltage across RSET. When the low side switch is

turned on, the inductor current flows through the Q2 and

results a voltage which is given by:

Figure 5 - Diagram of the over current sensing.

When voltage VOCSET is below zero, the current sensing

comparator flips and disables the oscillator. The high

side MOSFET is turned off and the low side MOSFET is

turned on until the inductor current reduces to below

current set value. The critical inductor current can be

calculated by setting:

CSS = 20mA3TSTART/1V

20mA3TSTART/CSS = 2V-1V

Soft-Start

Voltage

Voltage at negative input

of Error Amp and Feedback

UVLO comparator

Voltage at Fb1 pin

Current flowing

into Fb1 pin

64uA

0uA

0.8V

≅

1.6V 0.8V

≅

Output of UVLO

POR

The feedback voltage increases linearly as the injecting

current goes down. The injecting current drops to zero

when soft-start voltage is around 2V and the output volt-

age goes into steady state.

As shown in Figure 4, the positive pin of feedback UVLO

comparator is always higher than 0.4V, therefore, feed-

back UVLO is not functional during soft-start.

Figure 4 - Theoretical operation waveforms

during Soft-Start.

From this analysis, the output start-up time is defined

as when soft-start capacitor voltage increases from 1V

to 2V. The start-up time will be dependent on the size of

the external soft-start capacitor and can be estimated

by:

For a given start up time, the soft-start capacitor can be

calculated as:

MOSFET Drivers

The driver capabilities of both high and low side drivers

are optimized to maintain fast switching transitions. They

are sized to drive a MOSFET that can deliver up to 20A

output current.

The low side MOSFET diver is supplied directly by VCC

while the high side driver is supplied by VC.

An internal dead time control is implemented to prevent

cross-conduction and allows the use of several kinds of

MOSFETs.

VOCSET = IOCSET3RSET-RDS(ON)3iL ---(1)

SET

APU3073

OCSet

OCSET

OUT

Osc

ISET = IL(CRITICAL) = ---(2)

RSET3IOCSET

RDS(ON)

VOCSET = IOCSET3RSET - RDS(ON)3IL = 0

APU3073

7/17

If the over-current condition is temporary and goes away

quickly, the APU3073 will resume its normal operation.

If output is shorted or over-current condition persists,

the output voltage will keep going down until it is below

0.4V. Then the output under-voltage lock out comparator

goes high and turns off both MOSFETs. The operation

waveforms are shown in Figure 6.

Figure 6 - Diagram of over-current operation.

Feedback

voltage

Switching

frequency

High Side MOSFET

turn on time (t

)

Average Inductor

Current

OUT

MAX

S(NOM)

0.4V

REF

>=I

OUT

Normal

operation

Over Current

Limit Mode

Shutdown

by UVLO

O(LIM)

O(MAX)

OUT

S(NOM)

Operation in current limit is shown in Figure 7, the high

side MOSFET is turned off and inductor current starts to

decrease. Because the output inductor current is higher

than the current limit setpoint (ISET), the over-current com-

parator keeps high until the inductor current decreases

to be below ISET. Then another cycle starts.

During over-current mode, the valley inductor current is:

The peak inductor current is given as:

To avoid undesirable trigger of over-current protection,

this relationship must be satisfied:

iL(VALLEY) = ISET

IL(PEAK) = ISET+(VIN-VOUT)3tON/L ---(3)

SET

L(VALLEY)

L(PEAK)

OFF

L(AVG)

Current Limit

Comparator Output

Inductor

Current

HDrv

ISET / IO(NOM) -DIPK-PK(NOM)

ISET = IO(LIM) - ---(5)

(VIN-VOUT)3VOUT

23fS3L3VIN

( )

(VIN - VOUT)3VOUT

VIN3L3fS

DIPK-PK(LIM) =

IO(LIM) = ISET + ---(4)

DIPK-PK(LIM)

RSET = 3 IO(LIM) - ---(6)

RDS(ON)

IOCSET [ ( )]

(VIN-VOUT)3VOUT

23fS3L3VIN

Figure 7 - Operation waveforms during current limit.

From Figure 7, the average inductor current during the

current limit mode is:

The inductor's ripple current can be expressed as:

Combination of above equation and (4) results in:

Combination of equations (5) and (2) results in the rela-

tionship between RSET and output current limit:

From the above analysis, the current limit is not only

dependent on the current setting resistor RSET and RDS(ON)

of low side MOSFET but it is also dependent on the

input voltage, output voltage, inductance and switching

frequency as well.

The cycle-by-cycle over-current limit will hold for a cer-

tain amount of time, until the output voltage drops below

0.4V, the under-voltage lock out activates and latches

off the output driver. The operation waveform is shown in

Figure 4. Normal operation will resume after APU3073 is

powered up again.

Where:

IO(LIM) = The Output Current Limit -typical is 50%

higher than nominal output current.

VIN = Maximum Input Voltage

VOUT = Output Voltage

fS = Switching Frequency

L = Output Inductor

RDS(ON) = RDS(ON) of Low Side MOSFET

IOCSET = OC Threshold Set Current

8/17

APU3073

VIN - VOUT = L3 ; Dt = D3 ; D =

VOUT

VIN

L = (VIN - VOUT)3 ---(11)

VOUT

VIN3Di3fS

Where:

VIN = Maximum Input Voltage

VOUT = Output Voltage

∆i = Inductor Ripple Current

fS = Switching Frequency

∆t = Turn On Time

D = Duty Cycle

APPLICATION INFORMATION

Design Example:

The following example is a typical application for APU3073,

the schematic is Figure 17 on page 16.

Output Voltage Programming

Output voltage is programmed by reference voltage and

external voltage divider. The Fb pin is the inverting input

of the error amplifier, which is referenced to the voltage

on non-inverting pin of error amplifier. For this applica-

tion, this pin (VP) is connected to reference voltage (VREF).

The output voltage is defined by using the following equa-

tion:

When an external resistor divider is connected to the

output as shown in Figure 8.

Figure 8 - Typical application of the APU3039 for

programming the output voltage.

Equation (7) can be rewritten as:

If the high value feedback resistors are used, the input

bias current of the Fb pin could cause a slight increase

in output voltage. The output voltage set point can be

more accurate by using precision resistor.

Soft-Start Programming

The soft-start timing can be programmed by selecting

the soft-start capacitance value. The start-up time of the

converter can be calculated by using:

For a start-up time of 5ms, the soft-start capacitor will

be 0.1mF. Choose a ceramic capacitor at 0.1mF.

Supply VcL and VcH

To drive the high side switch, it is necessary to supply a

gate voltage at least 4V greater than the Bus voltage.

For this application, VcL and VcH are biased with a sepa-

rate 12V supply.

Input Capacitor Selection

The input filter capacitor should be based on how much

ripple the supply can tolerate on the DC input line. The

ripple current generated during the on time of upper

MOSFET should be provided by input capacitor. The RMS

value of this ripple is expressed by:

For higher efficiency, a low ESR capacitor is recom-

mended. Choose two Poscap from Sanyo 6TPB47M

(16V, 47mF) with a max allowable ripple current of 5.2A.

Inductor Selection

The inductor is selected based on operating frequency,

transient performance and allowable output voltage ripple.

Low inductor value results to faster response to step

load (high di/dt) and smaller size but will cause larger

output ripple due to increase of inductor ripple current.

As a rule of thumb, select an inductor that produces a

ripple current of 10-40% of full load DC.

For the buck converter, the inductor value for desired

operating ripple current can be determined using the fol-

lowing relation:

VOUT = VP 3 1 + ---(7)

VP = VREF = 0.8V

( )

APU3073

OUT

REF

Css ≅ 203tSTART (mF) ---(8)

Where tSTART is the desirable start-up time (s)

For VIN=5V, IOUT=8A and D=0.5, the IRMS=4A

IRMS = IOUT D3(1-D) ---(9)

Where:

D is the Duty Cycle, D=VOUT/VIN.

IRMS is the RMS value of the input capacitor current.

IOUT is the output current for each channel.

R6 = R5 3 - 1

VOUT

( )

Choose R5 = 1K. This will result to R6 = 2.15K

Switcher

VIN = 5V

VOUT = 2.5V

IOUT = 8A

DVOUT = 50mV

fS = 200KHz

Linear Regulator

VIN = 2.5V

VOUT = 1.6V

IOUT = 2A

Supply Voltage

VCC=VCL=VCH=12V

APU3073

9/17

If Di = 25%(IO), then the output inductor will be:

The Coilcraft DO5022HC series provides a range of in-

ductors in different values, low profile suitable for large

currents. 3.3mH is a good choice for this application.

This will result to a ripple approximately 23% of output

current.

Output Capacitor Selection

The criteria to select the output capacitor is normally

based on the value of the Effective Series Resistance

(ESR). In general, the output capacitor must have low

enough ESR to meet output ripple and load transient

requirements, yet have high enough ESR to satisfy sta-

bility requirements. The ESR of the output capacitor is

calculated by the following relationship:

The Sanyo TPC series, Poscap capacitor is a good choice.

The 6TPC330M, 330mF, 6.3V has an ESR 40mV. Se-

lecting two of these capacitors in parallel, results to an

ESR of ≅ 20mV which achieves our low ESR goal.

The capacitor value must be high enough to absorb the

inductor's ripple current. The larger the value of capaci-

tor, the lower will be the output ripple voltage.

Power MOSFET Selection

The APU3073 uses two N-Channel MOSFETs. The se-

lections criteria to meet power transfer requirements is

based on maximum drain-source voltage (VDSS), gate-

source drive voltage (VGS), maximum output current, On-

resistance RDS(ON) and thermal management.

The MOSFET must have a maximum operating voltage

(VDSS) exceeding the maximum input voltage (VIN).

The gate drive requirement is almost the same for both

MOSFETs. Logic-level transistor can be used and cau-

tion should be taken with devices at very low VGS to pre-

vent undesired turn-on of the complementary MOSFET,

which results a shoot-through current.

The total power dissipation for MOSFETs includes con-

duction and switching losses. For the Buck converter,

the average inductor current is equal to the DC load cur-

rent. The conduction loss is defined as:

The RDS(ON) temperature dependency should be consid-

ered for the worst case operation. This is typically given

in the MOSFET data sheet. Ensure that the conduction

losses and switching losses do not exceed the package

ratings or violate the overall thermal budget.

Choose IRF7832 for both control MOSFET and synchro-

nous MOSFET. This device provides low on-resistance

in a compact SOIC 8-Pin package.

The MOSFETs have the following data:

The total conduction losses will be:

The switching loss is more difficult to calculate, even

though the switching transition is well understood. The

reason is the effect of the parasitic components and

switching times during the switching procedures such

as turn-on / turnoff delays and rise and fall times. The

control MOSFET contributes to the majority of the switch-

ing losses in synchronous Buck converter. The synchro-

nous MOSFET turns on under zero voltage conditions,

therefore, the turn on losses for synchronous MOSFET

can be neglected. With a linear approximation, the total

switching loss can be expressed as:

The switching time waveform is shown in Figure 9.

PCOND(Upper Switch) = ILOAD3RDS(ON)3D3q

PCOND(Lower Switch) = ILOAD3RDS(ON)3(1 - D)3q

q = RDS(ON) Temperature Dependency

L = 3.125mH

Where:

DVO = Output Voltage Ripple

Di = Inductor Ripple Current

DVO = 50mV and DI ≅ 23% of 8A = 1.89A

This results to: ESR=26.5mV

ESR [ ---(10)

DVO

DIO

PCON(TOTAL) = PCON(UPPER) + PCON(LOWER)

PCON(TOTAL) = 0.38W

Where:

VDS(OFF) = Drain to Source Voltage at off time

tr = Rise Time

tf = Fall Time

T = Switching Period

ILOAD = Load Current

PSW = ILOAD ---(12)3

VDS(OFF)

2tr + tf

IRF7832

VDSS = 30V

ID = 16A @ 708C

RDS(ON) = 4mV

10/17

APU3073

FESR = ---(14)

2p3ESR3Co

PSW(TOTAL) = 133mW

FLC = ---(13)

2p3 LO3CO

RDS(ON) = 4mV31.5 = 6mV

ISET ≅ IO(LIM) = 8A31.5 = 12A

(50% over nominal output current)

This results to: RSET ≅ 4.8KV

Select: RSET = 5KV

10%

90%

(ON)

(OFF)

Figure 9 - Switching time waveforms.

From IRF7832 data sheet we obtain:

These values are taken under a certain condition test.

For more details please refer to the IRF7832 datasheet.

By using equation (12), we can calculate the total switch-

ing losses.

Programming the Over-Current Limit

The over-current threshold can be set by connecting a

resistor (RSET) from drain of low side MOSFET to the

OCSet pin. The resistor can be calculated by using equa-

tion (2).

The RDS(ON) has a positive temperature coefficient and it

should be considered for the worse case operation.

Feedback Compensation

The APU3073 is a voltage mode controller; the control

loop is a single voltage feedback path including error

amplifier and error comparator. To achieve fast transient

response and accurate output regulation, a compensa-

tion circuit is necessary. The goal of the compensation

network is to provide a closed loop transfer function with

the highest 0dB crossing frequency and adequate phase

margin (greater than 458).

Gain

0dB

Phase

-180

Frequency Frequency

-40dB/decade

The output LC filter introduces a double pole, –40dB/

decade gain slope above its corner resonant frequency,

and a total phase lag of 1808 (see Figure 10). The Reso-

nant frequency of the LC filter is expressed as follows:

Figure 10 shows gain and phase of the LC filter. Since

we already have 1808 phase shift just from the output

filter, the system risks being unstable.

Figure 10 - Gain and phase of LC filter.

The APU3073’s error amplifier is a differential-input

transconductance amplifier. The output is available for

DC gain control or AC phase compensation.

The E/A can be compensated with or without the use of

local feedback. When operated without local feedback,

the transconductance properties of the E/A become evi-

dent and can be used to cancel one of the output filter

poles. This will be accomplished with a series RC circuit

from Comp pin to ground as shown in Figure 11.

Note that this method requires that the output capacitor

should have enough ESR to satisfy stability requirements.

In general, the output capacitor’s ESR generates a zero

typically at 5KHz to 50KHz which is essential for an

acceptable phase margin.

The ESR zero of the output capacitor expressed as fol-

lows:

IRF7832

tr = 12.3ns

tf = 21ns

APU3073

11/17

First select the desired zero-crossover frequency (Fo):

Use the following equation to calculate R4:

Where:

VIN = Maximum Input Voltage

VOSC = Oscillator Ramp Voltage

Fo = Crossover Frequency

FESR = Zero Frequency of the Output Capacitor

FLC = Resonant Frequency of the Output Filter

R5 and R6 = Resistor Dividers for Output Voltage

Programming

gm = Error Amplifier Transconductance

H(s) = gm3 3 ---(15)

( )

R6 + R5

1 + sR4C9

sC9

FLC = 3.41KHz

R5 = 1K

R6 = 2.15K

gm = 700mmho

For:

VIN = 5V

VOSC = 1.25V

Fo = 20KHz

FESR = 12KHz

R4 = 3 3 3 ---(18)

Fo3FESR

FLC2

VOSC

VIN

R5 + R6

Fo > FESR and FO [ (1/5 ~ 1/10)3fS

For:

Lo = 3.3mH

Co = 660mF

FZ ≅ 75%FLC

FZ ≅ 0.7531

2p LO 3 CO---(19)

FZ = 2.5KHz

R4 = 24K

FZ = ---(17)

2p3R43C9

|H(s=j32p3FO)| = gm3 3R4 ---(16)

R63R5

OUT

Vp=V

REF

E/A

H(s) dB

Frequency

Gain(dB)

Fb Comp

POLE

Figure 11 - Compensation network without local

feedback and its asymptotic gain plot.

The transfer function (Ve / VOUT) is given by:

The (s) indicates that the transfer function varies as a

function of frequency. This configuration introduces a gain

and zero, expressed by:

|H(s)| is the gain at zero cross frequency.

C9 ≅ 2590pF; Choose C9 =2200pF

FP = 2p3R43

1C93CPOLE

C9 + CPOLE

CPOLE = ≅

for FP << fS

p3R43fS

p3R43fS -

This results to R4=23.14K

Choose R4=24K

To cancel one of the LC filter poles, place the zero be-

fore the LC filter resonant frequency pole:

Using equations (17) and (19) to calculate C9, we get:

One more capacitor is sometimes added in parallel with

C9 and R4. This introduces one more pole which is mainly

used to suppress the switching noise. The additional

pole is given by:

The pole sets to one half of switching frequency which

results in the capacitor CPOLE:

For a general solution for unconditionally stability for

ceramic capacitor with very low ESR and any type of

output capacitors, in a wide range of ESR values we

should implement local feedback with a compensation

network. The typically used compensation network for

voltage-mode controller is shown in Figure 12.

12/17

APU3073

Cross Over Frequency:

The stability requirement will be satisfied by placing the

poles and zeros of the compensation network according

to following design rules. The consideration has been

taken to satisfy condition (20) regarding transconduc-

tance error amplifier.

These design rules will give a crossover frequency ap-

proximately one-tenth of the switching frequency. The

higher the band width, the potentially faster the load tran-

sient speed. The gain margin will be large enough to

provide high DC-regulation accuracy (typically -5dB to -

12dB). The phase margin should be greater than 458 for

overall stability.

Based on the frequency of the zero generated by ESR

versus crossover frequency, the compensation type can

be different. The table below shows the compensation

type and location of crossover frequency.

Table - The compensation type and location of zero

crossover frequency.

Detail information is dicussed in application Note AN-

1043 which can be downloaded from the IR Web-Site.

Where:

VIN = Maximum Input Voltage

VOSC = Oscillator Ramp Voltage

Lo = Output Inductor

Co = Total Output Capacitors

FO = R73C103 3

VIN

VOSC

2p3Lo3Co ---(21)

Figure 12 - Compensation network with local

feedback and its asymptotic gain plot.

In such configuration, the transfer function is given by:

The error amplifier gain is independent of the transcon-

ductance under the following condition:

By replacing ZIN and Zf according to Figure 7, the trans-

former function can be expressed as:

As known, transconductance amplifier has high imped-

ance (current source) output, therefore, consider should

be taken when loading the E/A output. It may exceed its

source/sink output current capability, so that the ampli-

fier will not be able to swing its output voltage over the

necessary range.

The compensation network has three poles and two ze-

ros and they are expressed as follows:

OUT

Vp=V

REF

E/A

Frequency

Gain(dB)

H(s) dB

Fb Comp

H(s) = 1+sR7 3(1+sR8C10)

(1+sR7C11)3[1+sC10(R6+R8)]

3[ ( )]

sR6(C12+C11)C12C11

C12+C11

gmZf >> 1 and gmZIN >>1 ---(20)

1 - gmZf

1 + gmZIN

VOUT =

2p3C103(R6 + R8)

FZ2 = ≅1

2p3C103R6

FZ1 = 1

2p3R73C11

FP1 = 0

FP3 = ≅

2p3R73

2p3R73C12

FP2 = 1

2p3R83C10

( )

C123C11

C12+C11

Compensator

Type

Type II (PI)

Type III (PID)

Method A

Type III (PID)

Method B

Location of Zero

Crossover Frequency

(FO)

FPO < FZO < FO < fS/2

FPO < FO < FZO < fS/2

FPO < FO < fS/2 < FZO

Typical

Output

Capacitor

Electrolytic,

Tantalum

Tantalum,

Ceramic

APU3073

13/17

LDO Section

Output Voltage Programming

Output voltage for LDO is programmed by reference volt-

age and external voltage divider. The Fb2 pin is the in-

verting input of the error amplifier, which is internally ref-

erenced to 0.8V. The divider is ratioed to provide 0.8V at

the Fb2 pin when the output is at its desired value. The

output voltage is defined by using the following equation

Results to R7=1KV

Figure 13 - Programming the output voltage for LDO.

LDO Power MOSFET Selection

The first step in selecting the power MOSFET for the

linear regulator is to select the maximum RDS(ON) based

on the input to the dropout voltage and the maximum

load current.

Results to: RDS(ON)(MAX) = 0.45V

Note that since the MOSFET RDS(ON) increases with tem-

perature, this number must be divided by ~1.5 in order

to find the RDS(ON)(MAX) at room temperature. The IRLR2703

has a maximum of 0.065V RDS(ON) at room temperature,

which meets our requirements.

R10

VOUT2 = VREF3 1+

( )

For:

VOUT2 = 1.6V

VREF = 0.8V

R10 = 1KV

Layout Consideration

The layout is very important when designing high fre-

quency switching converters. Layout will affect noise

pickup and can cause a good design to perform with

less than expected results.

Start to place the power components. Make all the con-

nections in the top layer with wide, copper filled areas.

The inductor, output capacitor and the MOSFET should

be close to each other as possible. This helps to reduce

the EMI radiated by the power traces due to the high

switching currents through them. Place input capacitor

directly to the drain of the high-side MOSFET. To reduce

the ESR, replace the single input capacitor with two par-

allel units. The feedback part of the system should be

kept away from the inductor and other noise sources

and be placed close to the IC. In multilayer PCB, use

one layer as power ground plane and have a separate

control circuit ground (analog ground), to which all sig-

nals are referenced. The goal is to localize the high cur-

rent path to a separate loop that does not interfere with

the more sensitive analog control function. These two

grounds must be connected together on the PC board

layout at a single point.

Figure 14 - Switching Frequency vs. Rt.

100

150

200

250

300

350

400

450

500

0 50 100 150 200 250 300 350 400 450 500 550

Rt (KV)

Frequency (KHz)

Fb2

APU3073

OUT2

RDS(ON) = VIN(LDO) - VOUT2

IOUT2

For:

VIN(LDO) = 2.5V

VOUT2 = 1.6V

IOUT2 = 2A

14/17

APU3073

Figure 15 - Typical application of APU3073 for single 5V.

TYPICAL APPLICATION

APU3073

Vcc

VcL

HDrv

LDrv

Fb1

Gnd

Comp

SS/SD

2.5V

@ 8A

+5V

OCSet

PGnd

Drv2

Fb2

2.5V

1.6V

@ 2A

IRLR2703

C14

150uF

0.1uF

C11

1uF

47uF

IRF7832

R14

R7 R4

R10

VcH

REF

C10

0.1uF C2

BAT54

C16

1uF

C19

1uF

C9B

330uF C9C

330uF C12

1uF

33pF

24K 2200pF 5.1K Q2

IRF7832

3.3uH

2.15K

1uH

C2A,B,C=47uF

BAT54

0.1uF

C13

150uF

APU3073

15/17

Figure 16 - Typical application of APU3073.

TYPICAL APPLICATION

APU3073

VcH

VcL

HDrv

LDrv

Fb1

Gnd

Comp

SS/SD

2.5V

@ 8A

+5V

OCSet

PGnd

Drv2

Fb2

3.3V

1.6V

@ 1A

IRLR2703

C14

150uF

0.1uF

C11

1uF

47uF

IRF7832

R14

R7 R4

R10

Vcc

REF

12V

C10

0.1uF C2

BAT54

C16

1uF

C19

1uF

C9B

330uF C9C

330uF C12

1uF

33pF

24K 2200pF 5.1K Q2

IRF7832

3.3uH

2.15K

1uH

C2A,B,C=47uF

C13

150uF

16/17

APU3073

Figure 18 - Normal condition at no load.

Ch1: HDrv

Ch2: LDrv

Ch4: Inductor Current

Figure 19 - Gate signals when SS pin pulls low.

Ch1: HDrv

Ch2: LDrv

Figure 20 - Soft-Start.

Ch1: VIN (5V)

Ch2: Bias Voltage (12V)

Ch3: VOUT1 (PWM)

Ch4: VOUT2 (LDO)

APPLICATION EXPERIMENTAL WAVEFORMS

APU3073

17/17

Figure 22 - Load Transient Response (PWM Section).

Ch1: VOUT1

Ch4: IOUT1 (0-8A)

Figure 21 - Output Shorted at start-up.

Ch1: VOUT

Ch4: IOUT

APPLICATION EXPERIMENTAL WAVEFORMS

Figure 23 - Load Transient Response (LDO Section).

Ch2: VOUT2

Ch4: IOUT2 (0-2A)