MM54HC373/MM74HC373 General Description These high speed octal D-type latches utilize advanced sili- con-gate CMOS technology. They possess the high noise immunity and low power consumption of standard CMOS integrated circuits, as well as the ability to drive 15 LS-TTL loads. Due to the large output drive capability and the TRI- STATE feature, these devices are ideally suited for interfac- ing with bus lines in a bus organized system. When the LATCH ENABLE input is high, the Q outputs will follow the D inputs. When the LATCH ENABLE goes low, data at the D inputs will be retained at the outputs uniil LATCH ENABLE returns high again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are pres- (AV vational Semiconductor TRI-STATE Octal D-Type Latch January 1988 ent at the other inputs and the state of the storage ele- ments. The 54HG/74HC logic family is speed, function, and pin-out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to Voc and ground. Features @ Typical propagation delay: 18 ns m Wide operating voltage range: 2 to 6 volts @ Low input current: 1 wA maximum mw Low quiescent current: 80 ~A maximum (74 Series) @ Output drive capability: 15 LS-TTL loads Connection Diagram Dual-In-Line Package LATCH ENABLE Vec 8a 8D 7D 7a 6a 6D 5D 5a 6 | 20 19 18 17 16 15 14 13 12 11 Ld ba Lb) G4 G P-eaG GP-e-O1G OE OE OE OE t I I /\ Q DEqimjD a Q DEVIir io @ GP OG G fo OG OE & G OE OE G OE I I I J Le aad Lo d 1 2 3 4 5 6 7 8 9 10 OUTPUT 10 1D 2D 2Q 30 3D 4D 4Q GND CONTROL TL/F/5335-1 Top View Order Number MM54HC373 or MM74HC373 Truth Table Output | Latch | 1, | 373 H = high level, L = low level Control Enable Output Qo = level of output before steady-state input L H H H conditions were established. L H L L Z = high impedance L L xX Qo H xX xX Z TRI-STATE js a registered trademark of National Semiconductor Corporation, 1995 National Semiconductor Corporation TL/F/5335 RRD-B30M105/Printed in U.S. A. yo}e7 adAL-q 18190 FLVLS-INL ELEOHPLINW/EZEOHPSINNAbsolute Maximum Ratings (notes 1 2 2) Operating Conditions If Military/Aerospace specified devices are required, Min Max Units please contact the National Semiconductor Sales Supply Voltage (Vcc) 2 6 v Office/Distributors for availability and specifications. DG Input or Output Voltage 0 Voc Vv Supply Voltage (Vcc) 0.5 to +7.0V (Vin. Vout) DC Input Voltage (Vin) 1.5 to Voot 1.5V Operating Temp. Range (Ta) DC Output Voltage (Voy) 0.5 to Veo + 0.5V MM74HC 40 +85 C Clamp Diode Current (lik, lox) +20 mA MMB54HC ; 55 +125 C DC Output Current, per pin (lout) +35 mA me a een2ov 4000 ns DC Voc or GND Currert, per pin (loc) +70 mA Voo=4.5V 500 ns Storage Temperature Range (Tstq) 65C to + 150C Voc =6.0V 400 ns Power Dissipation (Pp) (Note 3) 600 mw S.O. Package only 500 mw Lead Temp. (T,) (Soldering 10 seconds) 260C DC Electrical Characteristics T,=25C 74HC 54HC Symbol Parameter Conditions Vee A Ta= 40 to 85C | Ta= 55 to 125C | Units Typ Guaranteed Limits Vin Minimum High Level 2.0V 1.5 1.5 1.5 v Input Voltage 4.5V 3.15 3.15 3.15 Vv 6.0V 4.2 4.2 4.2 Vv VIL Maximum Low Level 2.0V 0.5 0.5 0.5 v Input Voltage** 4.5V 1.35 1.35 1.35 Vv 6.0V 1.8 1.8 1.8 Vv Vou Minimum High Level VIN =Vin or Vit Output Voltage llout| <20 pA 2.0V} 2.0] 1.9 1.9 1.9 Vv 4.5V | 4.5 44 4.4 4.4 Vv 6.0V| 6.0] 59 5.9 5.9 Vv VIN= Vin OF Vit llour| <6.0 mA 4.5V] 4.2 | 3.98 3.84 3.7 Vv llout| <7.8 mA 6.0V | 5.7 | 5.48 5.34 5.2 v VoL Maximum Low Level | Vin=Vin Or ViL Output Voltage llour|<20 pA 20V) 0 | 01 0.1 0.1 Vv 45V] 0 0.1 0.1 0.1 Vv 6.0V| 0 0.1 0.1 0.1 Vv VIN= Vin OF Vit llout| <6.0 mA 4.5V | 0.2 | 0.26 0.33 0.4 Vv llout| <7.8 mA 6.0V} 0.2 | 0.26 0.33 0.4 v lin Maximum Input Vin=Vcoc or GND 6.0V +04 +1.0 +1.0 pA Current loz Maximum TRI-STATE | Vin=Vin or ViL, OC=Viy | 6.0V +0.5 +5 +10 pA Output Leakage Vout = Vcc or GND Current loc Maximum Quiescent | Vin=Vcc or GND 6.0V 8.0 80 160 pA Supply Current louT=0 pA Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mW/C from 65C to 85C; ceramic J package: 12 mW/C from 100C to 125C, Note 4: For a power supply of 5V +10% the worst case output voltages (Voy, and Vo.) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case Vi} and Vi, occur at Voc = 5.5V and 4.5V respectively. (The V4 value at 5.5V is 3.85V.) The worst case leakage current (lin, loc, and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. **Viz limits are currently tested at 20% of Voc. The above Vi_ specification (30% of Voc) will be implemented no later than Q1, CY89.AC Electrical Characteristics v.g=sv, 1,=25C, ,==6ns Symbol Parameter Conditions Typ Guaranteed Limit Units teHL tPLH Maximum Propagation Delay, Data to Q C_ =45 pF 18 25 ns teHL tPLH Maximum Propagation Delay, LE to Q C_ =45 pF 21 30 ns tpzH: tpz Maximum Output Enable Time Ri =1ko 20 28 ns C_=45 pF tpuz. tpLz Maximum Output Disable Time RL=1ko 18 25 ns CL =5 pF ts Minimum Set Up Time 5 ns tH Minimum Hold Time 10 ns tw Minimum Pulse Width 9 16 ns AC Electrical Characteristics v.c=2.0-60Vv, , =50 pF, t,=1;=6 ns (unless otherwise specified) TT, =25C 74HC 54HC Symbol Parameter Conditions | Vec |_* Ta= 40 to 85C | Ta= 55 to 125C | Units Typ Guaranteed Limits tpHL: tpLH | Maximum Propagation CL=50pF | 2.0V]} 50 | 150 188 225 ns Delay, Data to Q CL=150pF | 2.0V | 80 | 200 250 300 ns CL=50pF | 45V |] 22 | 30 37 45 ns C_=150pF | 45V | 30 | 40 50 60 ns CL=50pF | 6.0V]| 19 26 31 39 ns CL=150pF | 6.0V | 26 | 35 44 53 ns tpi tpLH | Maximum Propagation C_=50pF |} 20V] 63 | 175 220 263 ns Delay, LE toQ C_=150 pF } 2.0V | 110 | 225 280 338 ns CL=50pF | 45V] 25 | 35 44 52 ns C_=150 pF} 45V | 35 | 45 56 68 ns CL=50pF | 60V] 21 30 37 45 ns C_=150pF | 6.0V | 28 | 39 49 59 ns tpzH, tpz_ | Maximum Output Enable RL=1ko Time C_=50pF | 20v] 50 | 150 188 225 ns C_=150 pF } 2.0V | 80 | 200 250 300 ns CL=50pF |} 45V] 21 30 37 45 ns C_=150pF | 45V | 30 | 40 50 60 ns C_=50pF | 6.0V| 19 26 31 39 ns CL=150pF | 6.0V | 26 | 35 44 53 ns tpHz. tp_z | Maximum Output Disable RL=1 ko 2.0V | 50 | 150 188 225 ns Time CL =50pF |} 45V] 21 30 37 45 ns 6.0V | 19 26 31 39 ns ts Minimum Set Up Time 2.0V 50 60 75 ns 4.5V 9 13 15 ns 6.0V 9 11 13 ns tH Minimum Hold Time 2.0V 5 5 5 ns 4.5V 5 5 5 ns 6.0V 5 5 5 ns tw Minimum Pulse Width 2.0V | 30 | 80 100 120 ns 45V 1 10 16 20 24 ns 6.0V| 9 14 18 20 ns ttHL tTLH | Maximum Output Rise CL=50pF | 2.0V] 25 60 75 90 ns and Fall Time 4.5V 7 12 15 18 ns 6.0V | 6 10 13 15 ns Cpp Power Dissipation (per latch) Capacitance (Note 5) OC=Vcc 30 pF OG=GND 50 pF Cin Maximum Input Capacitance 5 10 10 10 pF Cout Maximum Output Capacitance 15 | 20 20 20 pF Note 5: Cpp determines the no load dynamic power consumption, Pp = Cpp Voc? f+ loc Voc, and the no load dynamic current consumption, Is =Cpp Vcc f+ loc.MM54HC373/MM74HC373 TRI-STATE Octal D-Type Latch Physical Dimensions inches (milimeters) oose 0.025 (25.019) MAX ines) fap Fal [v9] Gro] fer] Fre} fs) Fie) [oe] fre] fd z 0.220-0.310 \ (5.5087.874) soos ouza AW EAI PL eee RAD TYP fr 0,037 + 0.005 (0.9800.127) 0.005 0.055 +0.005 : iso 0.290~ 0.220 rr aa (1.397 0.127) ~ 9.020-0.060 ar?) [7 662.128) GLASS SEALANT MIN {0.508 1.524) I L = 0.200 i \ (5.080) A MAX 955 ae 0.080.012 aaa oan my (0 2030.305) 0.310-0.410 0.080 0.018 0.003 [_ssio-a.0 74-1041) | ag (0.457 0,076) MAX BOTH ENDS (0.1004 0.010 (2.5404 0.254) 20H (REY Ta Ceramic Dual-In-Line Package (J) Order Number MM54HC373J or MM74HC373J NS Package Number J20A 4.013-1.040 4.092 x 0.030 (25.73-26.42) (2.337 x 0.762) 0.032 0,005 MAX DP \ feo} Cs] fre) 7) fie) [re bel (aor \ I RAD PIN NO. 1 IDENT. 0.260 +0.005 plW NO.1 WENT 6.604 -0.127 . ~ 0780 OPTION 1 Py \ 7 ane TRIG GGG tt 0.090 9.300-0,320 _.I aa) OPTION 2 (7620-8128) 0 gas BB Pang] ft a aw , ; [3.302 0.427) i667) TYP TyP | ! 71 0,145-0.200 | ee 95% 5 0,009 oors! 90: 0.004 { t (229-0361 229-0391) ee 0.020 6.10020.010 | | 0.125-0.140 (0.508) 0.060 +0.005 (2.540 0.254) 0.018+0.003 || n75-3.558) MIN 0.040 (1,524%0.127) (0.457 0.76) 0.326 0.015 (a28s 4 (azss 71918) Molded Dual-In-Line Package (N) Neoa REY &) Order Number MM74HC373N NS Package Number N20A LIFE SUPPORT POLICY NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd. 1111 West Bardin Road Fax: (+49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge@tevm2.nsc.com Ocean Centre, 5 Canton Rd. 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