©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
BUZ71A
13A, 50V, 0.120 Ohm, N-Channel Power
MOSFET
This is an N-Channel enhancement mode silicon gate power
field effect transistor designed for applications such as
switching regulators, switching converters, motor drivers,
relay drivers, and drivers for high power bipolar switching
transistors requiring high speed and low gate drive power.
This type can be operated directly from integrated circuits.
Formerly developmental type TA9770.
Features
• 13A, 50V
•r
DS(ON)
= 0.120
Ω
• SOA is Power Dissipation Limited
• Nanosecond Switching Speeds
• Linear Transfer Characteristics
• High Input Impedance
• Majority Carrier Device
• Related Literature
- TB334 “Guidelines for Soldering Surface Mount
Components to PC Boards”
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
BUZ71A TO-220AB BUZ71A
NOTE: When ordering, use the entire part number.
G
D
S
GATE
DRAIN (FLANGE)
SOURCE
DRAIN
Data Sheet December 2001
©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
Absolute Maximum Ratings
T
C
= 25
o
C, Unless Otherwise Specified
BUZ71A UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DS
50 V
Drain to Gate Voltage (R
GS
= 20k
Ω)
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
DGR
50 V
Continuous Drain Current, T
C
= 55
o
C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I
D
13 A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .I
DM
48 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V
GS
±
20 V
Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P
D
40 W
Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E
AS
100 mJ
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32 W/
o
C
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
STG
, T
J
-55 to 150
o
C
DIN Humidity Category - DIN 40040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .E
IEC Climatic Category - DIN IEC 68-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55/150/56
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
L
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . T
pkg
300
260
o
C
o
C
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. T
J
= 25
o
C to 125
o
C.
Electrical Specifications
T
C
= 25
o
C, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BV
DSS
I
D
= 250
µ
A, V
GS
= 0V 50 - - V
Gate to Threshold Voltage V
GS(TH)
V
GS
= V
DS
, I
D
= 1mA (Figure 9) 2.1 3 4 V
Zero Gate Voltage Drain Current I
DSS
T
J
= 25
o
C, V
DS
= 50V, V
GS
= 0V - 20 250
µ
A
T
J
= 125
o
C, V
DS
= 50V, V
GS
= 0V - 100 1000
µ
A
Gate to Source Leakage Current I
GSS
V
GS
= 20V, V
DS
= 0V - 10 100 nA
Drain to Source On Resistance (Note 2) r
DS(ON)
I
D
= 9A, V
GS
= 10V (Figure 8) - 0.11 0.12
Ω
Forward Transconductance (Note 2) gfs V
DS
= 25V, I
D
= 9A (Figure 11) 3.0 5.2 - S
Turn-On Delay Time t
d(ON)
V
CC
= 30V, I
D
≈
3A, V
GS
= 10V, R
GS
= 50
Ω,
R
L
= 10
Ω
-2030 ns
Rise Time t
r
-5585 ns
Turn-Off Delay Time t
d(OFF)
-7090 ns
Fall Time t
f
- 80 110 ns
Input Capacitance C
ISS
V
DS
= 25V, V
GS
= 0V, f = 1MHz (Figure 10) - 480 650 pF
Output Capacitance C
OSS
- 280 450 pF
Reverse Transfer Capacitance C
RSS
- 160 280 pF
Thermal Resistance Junction to Case R
θ
JC
≤
3.1
o
C/W
Thermal Resistance Junction to Ambient R
θ
JA
≤
75
o
C/W
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current I
SD
T
C
= 25
o
C--13A
Pulsed Source to Drain Current I
SDM
T
C
= 25
o
C--52A
Source to Drain Diode Voltage V
SD
T
J
= 25
o
C, I
SD
= 26A, V
GS
= 0V, (Figure 12) - 1.6 2.2 V
Reverse Recovery Time t
rr
T
J
= 25
o
C, I
SD
= 13, dI
SD
/dt = 100A/
µ
s,
V
R
= 30V
- 120 - ns
Reverse Recovery Charge Q
RR
- 0.15 -
µ
C
NOTES:
2. Pulse Test: Pulse width
≤
300
µ
s, duty cycle
≤
2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. V
DD
= 10V, T
J
= 25
o
C, L = 820
µ
H, I
PEAK
= 14A. (See Figures 14 and 15).
BUZ71A
©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
TC, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0
0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125
5
0
0 50 100 150
TC, CASE TEMPERATURE (oC)
ID, DRAIN CURRENT (A)
10
VGS ≥ 10V
15
10-5 10-4 10-3 10-2 10-1 100101
t, RECTANGULAR PULSE DURATION (s)
0.5
0.2
0.1
0.05
0.02
0.01
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC + TC
t1
t2
ZθJC, TRANSIENT THERMAL IMPEDANCE
1
0.1
0.01
SINGLE PULSE
VDS, DRAIN TO SOURCE VOLTAGE (V)
101
ID, DRAIN CURRENT (A)
102
102
100
101
100
10-1
103
10µs
5µs
1ms
10ms
100µs
DC
100ms
TJ = MAX RATED
OPERATION IN THIS
AREA MAY BE LIMITED
BY rDS(ON)
TC = 25oC
SINGLE PULSE
30
20
10
002 8
VDS, DRAIN TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
VGS = 20V
10V
PD = 40W
46
VGS = 6.0V
VGS = 5.5V
VGS = 5.0V
VGS = 4.5V
VGS = 4.0V
VGS = 6.5V
VGS = 7.0V
VGS = 7.5V
VGS = 8.0V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
BUZ71A
©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
FIGURE 6. TRANSFER CHARACTERISTICS FIGURE 7. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs
JUNCTION TEMPERATURE
FIGURE 9. GATE THRESHOLD VOLTAGE vs JUNCTION
TEMPERATURE
FIGURE 10. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE FIGURE 11. TRANSCONDUCTANCE vs DRAIN CURRENT
Typical Performance Curves Unless Otherwise Specified (Continued)
0510
VGS, GATE TO SOURCE VOLTAGE (V)
15
10
5
0
IDS(ON), DRAIN TO SOURCE CURRENT (A)
PULSE DURATION = 80µs
VDS = 25V
TJ = 25oC
DUTY CYCLE = 0.5% MAX
010 2015
0.3
0.2
0.1
0
ID, DRAIN CURRENT (A)
NORMALIZED ON RESISTANCE
0.4
5
VGS = 5V 5.5V 6V 6.5V 7V 7.5V 8V
10V
20V
9V
25 30
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
rDS(ON), DRAIN TO SOURCE
0.20
0.10
0-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120
0.30
80
VGS = 10V, ID = 9A
160
ON RESISTANCE (Ω)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
-50 0 50 100 150
VGS(TH), GATE THRESHOLD VOLTAGE (V)
4
3
2
1
0
TJ, JUNCTION TEMPERATURE (oC)
ID = 1mA
VDS = VGS
0 10203040
VDS, DRAIN TO SOURCE VOLTAGE (V)
101
100
10-1
10-2
C, CAPACITANCE (nF)
CISS
COSS
CRSS
VGS = 0, f = 1MHz
CISS = CGS +CGD
CRSS = CGD
COSS ≈ CDS + CGS
6
3
4
2
1
00 5 10 15
ID, DRAIN CURRENT (A)
gfs, TRANSCONDUCTANCE (S)
PULSE DURATION = 80µs
VDS = 25V, TJ = 25oC
5
DUTY CYCLE = 0.5% MAX
BUZ71A
©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
FIGURE 12. SOURCE TO DRAIN DIODE VOLTAGE FIGURE 13. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
Typical Performance Curves Unless Otherwise Specified (Continued)
0 0.5 1.0 1.5 2.0
VSD, SOURCE TO DRAIN VOLTAGE (V)
102
101
100
10-1
ISD, SOURCE TO DRAIN CURRENT (A)
PULSE DURATION = 80µs
TJ = 150oCTJ = 25oC
2.5 3.0
DUTY CYCLE = 0.5% MAX
15
10
5
00510
Qg, GATE CHARGE (nC)
VGS, GATE TO SOURCE VOLTAGE (V)
ID = 18A
VDS = 40V
15 20 25
VDS = 10V
tP
VGS
0.01Ω
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-
VDD
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
BUZ71A
©2001 Fairchild Semiconductor Corporation BUZ71A Rev. B
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
Test Circuits and Waveforms (Continued)
0.3µF
12V
BATTERY 50kΩ
VDS
S
DUT
D
G
Ig(REF)
0
(ISOLATED
VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
SAME TYPE
AS DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
Ig(REF)
0
BUZ71A
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER
NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification Product Status Definition
Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
First Production
Full Production
Not In Production
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