M058/M0516 Data Sheet
ARM Cortex™-M0
32-BIT MICROCONTROLLER
Publication Release Date: Mar 15, 2011
- 1 - Revision V1.0
NuMicro M051™ Series
M058/M0516 Data Sheet
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 2 - Revision V1.0
TABLE OF CONTENTS
1 GENERAL DESCRIPTION∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙6
2 FEATURES∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙7
3 BLOCK DIAGRAM∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙11
4 SELECTION TABLE∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙12
5 PIN CONFIGURATION∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙13
5.1 QFN 33 pin ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙13
5.2 LQFP 48 pin ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙14
5.3 Pin Description∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙15
6 FUNCTIONAL DESCRIPTION ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙18
6.1 ARM® Cortex™-M0 Core ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙18
6.2 System Manager ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙20
6.2.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙20
6.2.2 System Reset∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙20
6.2.3 System Power Architecture ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙20
6.2.4 System Timer (SysTick) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙21
6.2.5 Nested Vectored Interrupt Controller (NVIC) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙22
6.3 Clock Controller ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙26
6.3.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙26
6.3.2 Clock Generator Block Diagram ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙26
6.3.3 System Clock & SysTick Clock ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙27
6.3.4 AHB Clock Source Select ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙28
6.3.5 Peripherals Clock Source Select ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙28
6.3.6 Power Down Mode (Deep Sleep Mode) Clock ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙29
6.3.7 Frequency Divider Output∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙30
6.4 General Purpose I/O ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙32
6.4.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙32
6.5 I2C Serial Interface Controller (Master/Slave) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙34
6.5.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙34
6.5.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙34
6.6 PWM Generator and Capture Timer∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙36
6.6.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙36
6.6.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙37
6.7 Serial Peripheral Interface (SPI) Controller ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙38
6.7.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙38
6.7.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙38
6.8 Timer Controller∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙39
6.8.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙39
6.8.2 Features: ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙39
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 3 - Revision V1.0
6.9 Watchdog Timer (WDT)∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙40
6.9.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙40
6.9.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙41
6.10 UART Interface Controller∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙41
6.10.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙42
6.10.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙44
6.11 Analog-to-Digital Converter (ADC) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙45
6.11.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙45
6.11.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙45
6.12 External Bus Interface (EBI) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙47
6.12.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙47
6.12.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙47
6.13 Flash Memory Controller (FMC) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙48
6.13.1 Overview∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙48
6.13.2 Features∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙48
7 TYPICAL APPLICATION CIRCUIT∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙49
8 ELECTRICAL CHARACTERISTICS∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙50
8.1 Absolute Maximum Ratings ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙50
8.2 DC Electrical Characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙51
8.3 AC Electrical Characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙54
8.3.1 External Crystal ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙54
8.3.2 External Oscillator ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙54
8.3.3 Typical Crystal Application Circuits ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙54
8.3.4 Internal 22.1184 MHz RC Oscillator∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙55
8.3.5 Internal 10kHz RC Oscillator ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙55
8.4 Analog Characteristics∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙56
8.4.1 Specification of 600kHz sps 12-bit SARADC∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙56
8.4.2 Specification of LDO & Power management∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙56
8.4.3 Specification of Low Voltage Reset∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙57
8.4.4 Specification of Brownout Detector ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙57
8.4.5 Specification of Power-On Reset (5V) ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙58
8.5 SPI Dynamic characteristics ∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙59
9 PACKAGE DIMENSIONS∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙61
9.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙61
9.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm)∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙62
10 REVISION HISTORY∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙∙63
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 4 - Revision V1.0
LIST OF FIGURES
Figure 3–1 NuMicro™ M051 Series Block Diagram ....................................................................... 11
Figure 4–1 NuMicro M051™ Naming Rule..................................................................................... 12
Figure 5–1 NuMicro™ M051 Series QFN33 Pin Diagram.............................................................. 13
Figure 5–2 NuMicro™ M051 Series LQFP-48 Pin Diagram.......................................................... 14
Figure 6–1 Functional Block Diagram............................................................................................ 18
Figure 6–2 NuMicro M051™ Series Power Architecture Diagram.................................................. 21
Figure 6–3 Clock generator block diagram .................................................................................... 26
Figure 6–4 System Clock Block Diagram ...................................................................................... 27
Figure 6–5 SysTick clock Control Block Diagram .......................................................................... 27
Figure 6–6 AHB Clock Source for HCLK ....................................................................................... 28
Figure 6–7 Peripherals Clock Source Select for PCLK.................................................................. 29
Figure 6–8 Clock Source of Frequency Divider ............................................................................. 30
Figure 6–9 Block Diagram of Frequency Divider ........................................................................... 31
Figure 6–10 Push-Pull Output........................................................................................................ 32
Figure 6–11 Open-Drain Output..................................................................................................... 33
Figure 6–12 Quasi-bidirectional I/O Mode ..................................................................................... 33
Figure 6–13 I2C Bus Timing .......................................................................................................... 34
Figure 6–14 Timing of Interrupt and Reset Signal ......................................................................... 41
Figure 8–1 Typical Crystal Application Circuit ............................................................................... 55
Figure 8–2 SPI Master timing......................................................................................................... 60
Figure 8–3 SPI Slave timing........................................................................................................... 60
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 5 - Revision V1.0
LIST OF TABLES
Table 4–1 NuMicro™ M051 Series Product Selection Guide......................................................... 12
Table 5–1 NuMicro™ M051 Series Pin Description ....................................................................... 17
Table 6–1 Exception Model............................................................................................................ 24
Table 6–2 System Interrupt Map.................................................................................................... 24
Table 6–3 Vector Table Format ..................................................................................................... 25
Table 6–4 Watchdog Timeout Interval Selection ........................................................................... 40
Table 6–5 UART Baud Rate Equation ........................................................................................... 42
Table 6–6 UART Baud Rate Setting Table .................................................................................... 43
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 6 - Revision V1.0
1 GENERAL DESCRIPTION
The NuMicro M051™ series is a 32-bit microcontroller with embedded ARM® Cortex™-M0 core for
industrial control and applications which need rich communication interfaces. The Cortex™-M0 is
the newest ARM embedded processor with 32-bit performance and at a cost equivalent to
traditional 8-bit microcontroller. The NuMicro M051™ series includes M052, M054, M058 and
M0516 families.
The M058/M0516 can run up to 50 MHz. Thus it can afford to support a variety of industrial
control and applications which need high CPU performance. The M058/M0516 has 32K/64K-byte
embedded flash, 4K-byte data flash, 4K-byte flash for the ISP, and 4K-byte embedded SRAM.
Many system level peripheral functions, such as I/O Port, EBI (External Bus Interface), Timer,
UART, SPI, I2C, PWM, ADC, Watchdog Timer and Brownout Detector, have been incorporated
into the M058/M0516 in order to reduce component count, board space and system cost. These
useful functions make the M058/M0516 powerful for a wide range of applications.
Additionally, the M058/M0516 is equipped with ISP (In-System Programming) and ICP (In-Circuit
Programming) functions, which allow the user to update the program memory without removing
the chip from the actual end product.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 7 - Revision V1.0
2 FEATURES
z Core
ARM® Cortex™-M0 core runs up to 50 MHz.
One 24-bit system timer.
Supports low power sleep-mode.
A single-cycle 32-bit hardware multiplier.
NVIC for the 32 interrupt inputs, each with 4-levels of priority.
Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints.
z Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
z Memory
32KB/64KB Flash memory for program memory (APROM)
4KB Flash memory for data memory (DataFlash)
4KB Flash memory for loader (LDROM)
4KB SRAM for internal scratch-pad RAM (SRAM)
z Clock Control
Programmable system clock source
4~24 MHz external crystal input
22.1184 MHz internal oscillator (trimmed to 1% accuracy)
10 kHz low-power oscillator for Watchdog Timer and wake-up in sleep mode
PLL allows CPU operation up to the maximum 50MHz
z I/O Port
Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi bi-direction
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 8 - Revision V1.0
Push-Pull output
Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink IO mode
z Timer
Provides four channel 32-bit timers, one 8-bit pre-scale counter with 24-bit up-timer for
each timer.
Independent clock source for each timer.
24-bit timer value is readable through TDR (Timer Data Register)
Provides one-shot, periodic and toggle operation modes.
z Watchdog Timer
Multiple clock sources
Supports wake up from power down or sleep mode
Interrupt or reset selectable on watchdog time-out
z PWM
Built-in up to four 16-bit PWM generators; providing eight PWM outputs or four
complementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for each
PWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs
Supports capture interrupt
z UART
Up to two sets of UART device
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 9 - Revision V1.0
Programmable baud-rate generator
Buffered receiver and transmitter, each with 15 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
z SPI
Up to two sets of SPI device.
Supports master/slave mode
Master mode clock rate up to 20 MHz, and slave mode clock rate up to 10 MHz
Full duplex synchronous serial data transfer
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte suspend mode in 32-bit transmission
z I2C
Supports master/slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
Programmable clocks allow versatile rate control.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 10 - Revision V1.0
Supports multiple address recognition (four slave address with mask option)
z ADC
12-bit SAR ADC with 600k SPS
Up to 8-ch single-ended input or 4-ch differential input
Supports single mode/burst mode/single-cycle scan mode/continuous scan mode
Each channel with an individual result register
Supports conversion value monitoring (or comparison) for threshold voltage detection
Conversion can be started either by software trigger or external pin trigger
z EBI (External Bus Interface) for external memory-mapped device access
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Supports 8-bit/16-bit data width
z In-System Programming (ISP) and In-Circuit Programming (ICP)
z Brownout Detector
With 4 levels: 4.5V/3.8V/2.7V/2.2V
Supports brownout interrupt and reset option
z LVR (Low Voltage Reset)
Threshold voltage levels: 2.0V
z Operating Temperature: -40 ~85℃℃
z Packages:
Green package (RoHS)
48-pin LQFP, 33-pin QFN
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 11 - Revision V1.0
3 BLOCK DIAGRAM
Figure 3–1 NuMicro™ M051 Series Block Diagram
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 12 - Revision V1.0
4 SELECTION TABLE
NuMicro M051™ Series Selection Guide
Connectivity
Part No. APROM RAM Data
Flash LDROM I/O Timer UART SPI I2C PWM ADC EBI ISP
ICP Package
M058LAN 32KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 8 8x12-bit v v LQFP48
M058ZAN 32KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 5 5x12-bit v QFN 33
M0516LAN 64KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 8 8x12-bit v v LQFP48
M0516ZAN 64KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 5 5x12-bit v QFN 33
Table 4–1 NuMicro™ M051 Series Product Selection Guide
M05X -XX X
ARM Cortex-M0
L : LQFP 48
Z : QFN 33
52 : 8K Flash ROM
54 : 16K Flash ROM
-
CPU core
Reserved
Part Number Temperature
Package
-40℃ ~ +105℃
E:
-40℃ ~ +85 ℃
N:
-40℃ ~ +105℃
C:
Figure 4–1 NuMicro M051™ Naming Rule
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 13 - Revision V1.0
5 PIN CONFIGURATION
5.1 QFN 33 pin
Figure 5–1 NuMicro™ M051 Series QFN33 Pin Diagram
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 14 - Revision V1.0
5.2 LQFP 48 pin
Figure 5–2 NuMicro™ M051 Series LQFP-48 Pin Diagram
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 15 - Revision V1.0
5.3 Pin Description
Pin number Alternate Function
QFN33 LQFP48
Symbol
1 2
Type[1] Description
11 16 XTAL1
I
(ST)
CRYSTAL1: This is the input pin to the internal inverting
amplifier. The system clock is from external crystal or
resonator when FOSC[1:0] (CONFIG3[1:0]) are both logic
1 by default.
10 15 XTAL2
O CRYSTAL2: This is the output pin from the internal
inverting amplifier. It emits the inverted signal of XTAL1.
27 41 VDD
P POWER SUPPLY: Supply voltage Digital V
DD for
operation.
12
33
17 VSS
P GROUND: Digital Ground potential.
28 42 AVDD
P POWER SUPPLY: Supply voltage Analog AVDD for
operation.
4 6 AVSS
P GROUND: Analog Ground potential.
13 18
LDO_C
AP
P LDO: LDO output pin
Note: It needs to be connected with a 10uF capacitor.
2 4 /RST I
(ST)
RESET: /RST pin is a Schmitt trigger input pin for
hardware device reset. A “Low” on this pin for 768 clock
counter of Internal RC 22.1184 MHz while the system clock
is running will reset the device. /RST pin has an internal
pull-up resistor allowing power-on reset by simply
connecting an external capacitor to GND.
26 40 P0.0 CTS1 AD0 D, I/O
25 39 P0.1 RTS1 AD1 D, I/O
NC 38 P0.2 CTS0 AD2 D, I/O
NC 37 P0.3 RTS0 AD3 D, I/O
24 35 P0.4 SPISS1 AD4 D, I/O
PORT0: Port 0 is an 8-bit four mode output pin and two
mode input. Its multifunction pins are for CTS1, RTS1,
CTS0, RTS0, SPISS1, MOSI_1, MISO_1, and SPICLK1.
P0 has an alternative function as AD[7:0] while external
memory interface (EBI) is enabled.
These pins which are SPISS1, MOSI_1, MISO_1, and
SPICLK1 for the SPI function used.
CTS0/1: Clear to Send input pin for UART0/1
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 16 - Revision V1.0
Pin number Alternate Function
QFN33 LQFP48
Symbol
1 2
Type[1] Description
23 34 P0.5 MOSI_1 AD5 D, I/O
22 33 P0.6 MISO_1 AD6 D, I/O
21 32 P0.7 SPICLK1 AD7 D, I/O
RTS0/1: Request to Send output pin for UART0/1
29 43 P1.0 T2 AIN0 I/O
NC 44 P1.1 T3 AIN1 I/O
30 45 P1.2 RXD1 AIN2 I/O
31 46 P1.3 TXD1 AIN3 I/O
32 47 P1.4 SPISS0 AIN4 I/O
1 1 P1.5 MOSI_0 AIN5 I/O
NC 2 P1.6 MISO_0 AIN6 I/O
NC 3 P1.7 SPICLK0 AIN7 I/O
PORT1: Port 1 is an 8-bit four mode output pin and two
mode input. Its multifunction pins are for T2, T3, RXD1,
TXD1, SPISS0, MOSI_0, MISO_0, and SPICLK0.
T2: Timer2 external input
T3: Timer3 external input
These pins which are SPISS0, MOSI_0, MISO_0, and
SPICLK0 for the SPI function used.
These pins which are AIN0~AIN7 for the 12 bits ADC
function used.
The RXD1/TXD1 pins are for UART1 function used.
NC 19 P2.0 PWM0 AD8 D, I/O
NC 20 P2.1 PWM1 AD9 D, I/O
14 21 P2.2 PWM2 AD10 D, I/O
15 22 P2.3 PWM3 AD11 D, I/O
16 23 P2.4 PWM4 AD12 D, I/O
17 25 P2.5 PWM5 AD13 D, I/O
18 26 P2.6 PWM6 AD14 D, I/O
NC 27 P2.7 PWM7 AD15 D, I/O
PORT2: Port 2 is an 8-bit four mode output pin and two
mode input. It has an alternative function
P2 has an alternative function as AD[15:8] while external
memory interface (EBI) is enabled.
These pins which are PWM0~PWM7 for the PWM function.
3 5 P3.0 RXD I/O
5 7 P3.1 TXD I/O
PORT3: Port 3 is an 8-bit four mode output pin and two
mode input. Its multifunction pins are for RXD, TXD, 0INT ,
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 17 - Revision V1.0
Pin number Alternate Function
QFN33 LQFP48
Symbol
1 2
Type[1] Description
6 8 P3.2 0INT STADC I/O
NC 9 P3.3 1INT MCLK I/O
7 10 P3.4 T0 SDA I/O
8 11 P3.5 T1 SCL I/O
9 13 P3.6
WR CKO I/O
NC 14 P3.7
RD I/O
1INT , T0, T1, WR , and RD .
T0: Timer0 external input
T1: Timer1 external input
The RXD/TXD pins are for UART0 function used.
The SDA/SCL pins are for I2C function used.
MCLK: EBI clock output pin.
CKO: HCLK clock output
The STADC pin is for ADC external trigger input.
NC 24 P4.0 PWM0 I/O
NC 36 P4.1 PWM1 I/O
NC 48 P4.2 PWM2 I/O
NC 12 P4.3 PWM3 I/O
NC 28 P4.4 /CS I/O
NC 29 P4.5 ALE I/O
19 30 P4.6 ICE_CLK I/O
20 31 P4.7 ICE_DAT I/O
PORT4: Port 4 is an 8-bit four mode output pin and two
mode input. Its multifunction pins are for /CS, ALE,
ICE_CLK and ICE_DAT.
/CS for EBI (External Bus Interface) used.
ALE (Address Latch Enable) is used to enable the address
latch that separates the address from the data on Port 0
and Port 2.
The ICE_CLK/ICE_DAT pins are for JTAG-ICE function
used.
PWM0-3 can be used from P4.0-P4.3 when EBI is active.
Table 5–1 NuMicro™ M051 Series Pin Description
[1] I/O type description. I: input, O: output, I/O: quasi bi-direction, D: open-drain, P: power pins,
ST: Schmitt trigger.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 18 - Revision V1.0
6 FUNCTIONAL DESCRIPTION
6.1 ARM® Cortex™-M0 Core
The Cortex™-M0 processor is a configurable, multistage, 32-bit RISC processor. It has an AMBA AHB-
Lite interface and includes an NVIC component. It also has optional hardware debug functionality. The
processor can execute Thumb code and is compatible with other Cortex-M profile processor. The
profile supports two modes -Thread and Handler modes. Handler mode is entered as a result of an
exception. An exception return can only be issued in Handler mode. Thread mode is entered on Reset,
and can be entered as a result of an exception return.
Figure 6–1 Functional Block Diagram
The implemented device provides:
A low gate count processor the features:
The ARMv6-M Thumb® instruction set.
Thumb-2 technology.
ARMv6-M compliant 24-bit SysTick timer.
A 32-bit hardware multiplier.
The system interface supports little-endian data accesses.
The ability to have deterministic, fixed-latency, interrupt handling.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 19 - Revision V1.0
Load/store-multiples and multicycle-multiplies that can be abandoned and restarted to
facilitate rapid interrupt handling.
C Application Binary Interface compliant exception model.
This is the ARMv6-M, C Application Binary Interface(C-ABI) compliant exception model that
enables the use of pure C functions as interrupt handlers.
Low power sleep-mode entry using Wait For Interrupt (WFI), Wait For Event(WFE)
instructions, or the return from interrupt sleep-on-exit feature.
NVIC features:
32 external interrupt inputs, each with four levels of priority.
Dedicated non-Maskable Interrupt (NMI) input.
Support for both level-sensitive and pulse-sensitive interrupt lines
Wake-up Interrupt Controller (WIC), supports ultra-low power sleep mode.
Debug support:
Four hardware breakpoints.
Two watchpoints.
Program Counter Sampling Register (PCSR) for non-intrusive code profiling.
Single step and vector catch capabilities.
Bus interfaces:
Single 32-bit AMBA-3 AHB-Lite system interface that provides simple integration to all
system peripherals and memory.
Single 32-bit slave port that supports the DAP (Debug Access Port).
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 20 - Revision V1.0
6.2 System Manager
6.2.1 Overview
The following functions are included in system manager section
System Resets
System Memory Map
System management registers for Part Number ID, chip reset and on-chip module reset ,
multi-functional pin control
System Timer (SysTick)
Nested Vectored Interrupt Controller (NVIC)
System Control registers
6.2.2 System Reset
The system reset includes one of the list below event occurs. For these reset event flags can be
read by RSTRC register.
The Power-On Reset (POR)
The low level on the /RESET pin
Watchdog Time Out Reset (WDT)
Low Voltage Reset (LVR)
Brownout Detected Reset (BOD)
CPU Reset
System Reset
6.2.3 System Power Architecture
In this device, the power architecture is divided into two segments.
Analog power from AVDD and AVSS provides the power for analog module operation.
Digital power from VDD and VSS supplies the power to the internal regulator which
provides a fixed 2.5V power for digital operation and I/O pins.
The outputs of internal voltage regulator, which is LDO, require an external capacitor which
should be located close to the corresponding pin. The Figure 6–2 shows the power architecture of
this device.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 21 - Revision V1.0
5V to 2.5V
LDO
PLL
12-bit
SAR-ADC Brown Out Detector
POR50
POR25
Low Voltage
Reset
FLASH Digital Logic
(Timer/UART/I2C/SPI…)
2.5V
IRC
22.1184MHz
& 10KHz Osc.
AVDD
AVSS
VDD
VSS
LDO_CAP
10uF
IO cell P0~P4
VSS
NuMicro-M051 Power Architecture
Figure 6–2 NuMicro M051™ Series Power Architecture Diagram
6.2.4 System Timer (SysTick)
The Cortex-M0 includes an integrated system timer, SysTick. SysTick provides a simple, 24-bit
clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. The
counter can be used as a Real Time Operating System (RTOS) tick timer or as a simple counter.
When system timer is enabled, it will count down from the value in the SysTick Current Value
Register (SYST_CVR) to zero, and reload (wrap) to the value in the SysTick Reload Value
Register (SYST_RVR) on the next clock edge, then decrement on subsequent clocks. When the
counter transitions to zero, the COUNTFLAG status bit is set. The COUNTFLAG bit clears on
reads.
The SYST_CVR value is UNKNOWN on reset. Software should write to the register to clear it to
zero before enabling the feature. This ensures the timer will count from the SYST_RVR value
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 22 - Revision V1.0
rather than an arbitrary value when it is enabled.
If the SYST_RVR is zero, the timer will be maintained with a current value of zero after it is
reloaded with this value. This mechanism can be used to disable the feature independently from
the timer enable bit.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”.
6.2.5 Nested Vectored Interrupt Controller (NVIC)
Cortex-M0 provides an interrupt controller as an integral part of the exception mode, named as
“Nested Vectored Interrupt Controller (NVIC)”. It is closely coupled to the processor kernel and
provides following features:
z Nested and Vectored interrupt support
z Automatic processor state saving and restoration
z Dynamic priority changing
z Reduced and deterministic interrupt latency
The NVIC prioritizes and handles all supported exceptions. All exceptions are handled in “Handler
Mode”. This NVIC architecture supports 32 (IRQ[31:0]) discrete interrupts with 4 levels of priority.
All of the interrupts and most of the system exceptions can be configured to different priority
levels. When an interrupt occurs, the NVIC will compare the priority of the new interrupt to the
current running one’s priority. If the priority of the new interrupt is higher than the current one, the
new interrupt handler will override the current handler.
When any interrupts is accepted, the starting address of the interrupt service routine (ISR) is
fetched from a vector table in memory. There is no need to determine which interrupt is accepted
and branch to the starting address of the correlated ISR by software. While the starting address is
fetched, NVIC will also automatically save processor state including the registers “PC, PSR, LR,
R0~R3, R12” to the stack. At the end of the ISR, the NVIC will restore the mentioned registers
from stack and resume the normal execution. Thus it will take less and deterministic time to
process the interrupt request.
The NVIC supports “Tail Chaining” which handles back-to-back interrupts efficiently without the
overhead of states saving and restoration and therefore reduces delay time in switching to
pending ISR at the end of current ISR. The NVIC also supports “Late Arrival” which improves the
efficiency of concurrent ISRs. When a higher priority interrupt request occurs before the current
ISR starts to execute (at the stage of state saving and starting address fetching), the NVIC will
give priority to the higher one without delay penalty. Thus it advances the real-time capability.
For more detailed information, please refer to the documents “ARM® Cortex™-M0 Technical
Reference Manual” and “ARM® v6-M Architecture Reference Manual”.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 23 - Revision V1.0
6.2.5.1 Exception Model and System Interrupt Map
The Table 6–1 lists the exception model supported by NuMicro M051™ series. Software can set
four levels of priority on some of these exceptions as well as on all interrupts. The highest user-
configurable priority is denoted as “0” and the lowest priority is denoted as “3”. The default priority
of all the user-configurable interrupts is “0”. Note that priority “0” is treated as the fourth priority on
the system, after three system exceptions “Reset”, “NMI” and “Hard Fault”.
Exception
Number Vector
Address
Interrupt
Number
(Bit in
Interrupt
Registers)
Interrupt
Name Source IP Interrupt description Power
Down
Wakeup
1-15 0x00-0x3C - - - System exceptions
16 0x40 0 BOD_OUT Brownout Brownout low voltage detected
interrupt Yes
17 0x44 1 WDT_INT WDT Watch Dog Timer interrupt Yes
18 0x48 2 EINT0 GPIO External signal interrupt from P3.2
pin Yes
19 0x4C 3 EINT1 GPIO External signal interrupt from P3.3
pin Yes
20 0x50 4 GP01_INT GPIO External signal interrupt from
P0[7:0] / P1[7:0] Yes
21 0x54 5 GP234_INT GPIO
External interrupt from
P2[7:0]/P3[7:0]/P4[7:0], except P32
and P33
Yes
22 0x58 6 PWMA_INT PWM0~3 PWM0, PWM1, PWM2 and PWM3
interrupt No
23 0x5C 7 PWMB_INT PWM4~7 PWM4, PWM5, PWM6 and PWM7
interrupt No
24 0x60 8 TMR0_INT TMR0 Timer 0 interrupt No
25 0x64 9 TMR1_INT TMR1 Timer 1 interrupt No
26 0x68 10 TMR2_INT TMR2 Timer 2 interrupt No
27 0x6C 11 TMR3_INT TMR3 Timer 3 interrupt No
28 0x70 12 UART0_INT UART0 UART0 interrupt Yes
29 0x74 13 UART1_INT UART1 UART1 interrupt Yes
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 24 - Revision V1.0
30 0x78 14 SPI0_INT SPI0 SPI0 interrupt No
31 0x7C 15 SPI1_INT SPI1 SPI1 interrupt No
32-33 0x80-0x84 16-17 - - - -
34 0x88 18 I2C_INT I2C I2C interrupt No
35-43 0x8C-
0xAC 19-27 - - - -
44 0xB0 28 PWRWU_INT CLKC Clock controller interrupt for chip
wake up from power-down state Yes
45 0xB4 29 ADC_INT ADC ADC interrupt No
46-47 0xB8-
0xBC 30-31 - - -
Table 6–1 Exception Model
E
Ex
xc
ce
ep
pt
ti
io
on
n
N
Na
am
me
e
V
Ve
ec
ct
to
or
r
N
Nu
um
mb
be
er
r
P
Pr
ri
io
or
ri
it
ty
y
Reset 1 -3
NMI 2 -2
Hard Fault 3 -1
Reserved 4 ~ 10 Reserved
SVCall 11 Configurable
Reserved 12 ~ 13 Reserved
PendSV 14 Configurable
SysTick 15 Configurable
Interrupt (IRQ0 ~ IRQ31) 16 ~ 47 Configurable
Table 6–2 System Interrupt Map
6.2.5.2 Vector Table
When any interrupts is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 25 - Revision V1.0
entry as illustrated in previous section.
Vector Table Word Offset Description
0 SP_main – The Main stack pointer
Vector Number Exception Entry Pointer using that Vector Number
Table 6–3 Vector Table Format
6.2.5.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not activate. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 26 - Revision V1.0
6.3 Clock Controller
6.3.1 Overview
The clock controller generates the clocks for the whole chip, including system clocks and all
peripheral clocks. The clock controller also implements the power control function with the
individually clock ON/OFF control, clock source selection and a 4-bit clock divider. The chip will
not enter power-down mode until CPU sets the power down enable bit (PWR_DOWN_EN) and
Cortex-M0 core executes the WFI instruction. After that, chip enter power-down mode and wait for
wake-up interrupt source triggered to leave power-down mode. In the power down mode, the
clock controller turns off the external crystal and internal 22.1184 MHz oscillator to reduce the
overall system power consumption.
6.3.2 Clock Generator Block Diagram
The clock generator consists of 4 sources which list below:
z One external 4~24 MHz crystal
z One internal 22.1184 MHz RC oscillator
z One programmable PLL FOUT(PLL source consists of external 4~24 MHz crystal and
internal 22.1184M)
z One internal 10 kHz oscillator
XT_OUT
External
Crystal
4~24M
XTL12M_EN(PWRCON[0])
XT_IN
Inte r n a l
OSC22M
22.1184M
OSC22M_EN(PWRCON[2])
0
1PLL
PLL_SRC(PLLCON[19])
PLL FOUT
OSC10K 10K
OSC10K_EN(PWRCON[3])
4~24M
22.1184M
10K
Figure 6–3 Clock generator block diagram
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 27 - Revision V1.0
6.3.3 System Clock & SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S(CLKSEL0[2:0]). The block diagram is
shown in the Figure 6–4.
Figure 6–4 System Clock Block Diagram
The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]. The block
diagram is shown in the Figure 6–5.
Figure 6–5 SysTick clock Control Block Diagram
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 28 - Revision V1.0
6.3.4 AHB Clock Source Select
ISP_EN (AHBCLK[2])
HCLK
ISP (In System Programmer)
EBI_EN (AHBCLK[3])
HCLK
EBI (External Bus Interface)
Figure 6–6 AHB Clock Source for HCLK
6.3.5 Peripherals Clock Source Select
The peripherals clock had different clock source switch setting which depends on the different
peripheral. Please refer the CLKSEL1 & APBCLK register description in chapter 6.3.9.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 29 - Revision V1.0
W DT_EN (APBCLK1[0])
PCLK W atch Dog Timer
Timer1
Timer0
TMR0_EN (APBCLK1[2])
TMR1_EN (APBCLK1[3])
Timer2
TMR2_EN (APBCLK1[4])
Timer3
TMR3_EN (APBCLK1[5])
Frequency Divider
FDIV_EN (APBCLK1[6])
I2C
I2C0_EN (APBCLK1[8])
SPI0
SPI0_EN (APBCLK1[12])
SPI1
SPI1_EN (APBCLK1[13])
UART0
UART0_EN (APBCLK1[16])
UART1
UART1_EN (APBCLK1[17])
PWM01
PWM 01_EN (A P BC LK 1[20])
PWM23
PW M23_EN (APBCLK1[21])
PWM45
PW M45_EN (APBCLK1[22])
PWM67
PW M67_EN (APBCLK1[23])
Figure 6–7 Peripherals Clock Source Select for PCLK
6.3.6 Power Down Mode (Deep Sleep Mode) Clock
When chip enter into power down mode, most of clock sources, peripheral clocks and system
clock will be disabled. Some of clock sources and peripherals clock are still active in power down
mode.
For theses clocks which still keep active list below:
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 30 - Revision V1.0
Clock Generator
Internal 10 kHz oscillator clock
Peripherals Clock (When these IP adopt 10 kHz as clock source)
Watch Dog Clock
Timer 0/1/2/3 Clock
PWM Clock
6.3.7 Frequency Divider Output
This device is equipped a power-of-2 frequency divider which is composed by16 chained divide-
by-2 shift registers. One of the 16 shift register outputs selected by a sixteen to one multiplexer is
reflected to P3.6. Therefore there are 16 options of power-of-2 divided clocks with the frequency
from Fin/21 to Fin/217 where Fin is input clock frequency to the clock divider.
The output formula is Fout = Fin/2(N+1), where Fin is the input clock frequency, Fout is the clock
divider output frequency and N is the 4-bit value in FREQDIV.FSEL[3:0].
When write 1 to DIVIDER_EN (FRQDIV[4]), the chained counter starts to count. When write 0 to
DIVIDER_EN (FRQDIV[4]), the chained counter continuously runs till divided clock reaches low
state and stay in low state.
11
10
00
HCLK
Ext. Crystal
22.1184M
CLKSEL2.FRQDIV_S[3:2]
APBCLK.FRQDIV_EN[6]
FRQDIV_CLK
Figure 6–8 Clock Source of Frequency Divider
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 31 - Revision V1.0
16 chained
divide-by-2 counter
1/2 …...1/221/231/21
5
1/21
6
000
001
110
111
FREQDIV.FSEL[3:0]
:
:16 to 1
MUX
FREQDIV.FDIV_EN[4]
0 to 1
Reset Clock
Divider
10
00
P3_ALT[6]
P3_MFP[6]
P3.6/CLKO
P3_DOUT[6]
FRQDIV_CLK
Figure 6–9 Block Diagram of Frequency Divider
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 32 - Revision V1.0
6.4 General Purpose I/O
6.4.1 Overview
There are 40 General Purpose I/O pins shared with special feature functions in this MCU. The 40
pins are arranged in 5 ports named with P0, P1, P2, P3 and P4. Each port equips maximum 8
pins. Each one of the 40 pins is independent and has the corresponding register bits to control the
pin mode function and data
The I/O type of each of I/O pins can be software configured individually as input, output, open-
drain or quasi-bidirectional mode. The all pins of I/O type stay in quasi-bidirectional mode and port
data register Px_DOUT[7:0] resets to 0x000_00FF. Each I/O pin equips a very weakly individual
pull-up resistor which is about 110KΩ~300KΩ for VDD is from 5.0V to 2.5V.
6.4.1.1 Input Mode Explanation
Set Px_PMD(PMDn[1:0]) to 00b the Px[n] pin is in Input mode and the I/O pin is in tri-state(high
impedance) without output drive capability. The Px_PIN value reflects the status of the corresponding
port pins.
6.4.1.2 Output Mode Explanation
Set Px_PMD(PMDn[1:0]) to 2’b01 the Px[n] pin is in Output mode and the I/O pin supports digital
output function with source/sink current capability. The bit value in the corresponding bit [n] of
Px_DOUT is driven on the pin.
Port Pin
Input Data
Port Latch
Data
P
N
VDD
Figure 6–10 Push-Pull Output
6.4.1.3 Open-Drain Mode Explanation
Set Px_PMD(PMDn[1:0]) to 2’b10 the Px[n] pin is in Open-Drain mode and the I/O pin supports
digital output function but only with sink current capability, an additional pull-up resister is needed
for driving high state. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, the pin drive a
“low” output on the pin. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin
output drives high that is controlled by the internal pull-up resistor or the external pull high
resistor.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 33 - Revision V1.0
Port Pin
Port Latch
Data
N
Input Data
Figure 6–11 Open-Drain Output
6.4.1.4 Quasi-bidirectional Mode Explanation
Set Px_PMD(PMDn[1:0]) to 2’b11 the Px[n] pin is in Quasi-bidirectional mode and the I/O pin
supports digital output and input function at the same time but the source current is only up to
hundreds uA. Before the digital input function is performed the corresponding bit in Px_DOUT
must be set to 1. The quasi-bidirectional output is common on the 80C51 and most of its
derivatives. If the bit value in the corresponding bit [n] of Px_DOUT is “0”, the pin drive a “low”
output on the pin. If the bit value in the corresponding bit [n] of Px_DOUT is “1”, the pin will check
the pin value. If pin value is high, no action takes. If pin state is low, then pin will drive strong high
with 2 clock cycles on the pin and then disable the strong output drive and then the pin status is
control by internal pull-up resistor. Note that the source current capability in quasi-bidirectional
mode is only about 200uA to 30uA for VDD is form 5.0V to 2.5V
Port Pin
2 CPU
Clock Delay
Input Data
Port Latch
Data
PP P
N
VDD
Strong Very
Weak Weak
Figure 6–12 Quasi-bidirectional I/O Mode
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 34 - Revision V1.0
6.5 I2C Serial Interface Controller (Master/Slave)
6.5.1 Overview
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data
exchange between devices. The I2C standard is a true multi-master bus including collision
detection and arbitration that prevents data corruption if two or more masters attempt to control
the bus simultaneously.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a
byte-by-byte basis. Each data byte is 8 bits long. There is one SCL clock pulse for each data bit
with the MSB being transmitted first. An acknowledge bit follows each transferred byte. Each bit is
sampled during the high period of SCL; therefore, the SDA line may be changed only during the
low period of SCL and must be held stable during the high period of SCL. A transition on the SDA
line while SCL is high is interpreted as a command (START or STOP). Please refer to the Figure
6–13 for more detail I2C BUS Timing.
tBUF
STOP
SDA
SCL
START
tHD;STA
tLOW
tHD;DAT
tHIGH
tf
tSU;DAT
Repeated
START
tSU;STA tSU;STO
STOP
tr
Figure 6–13 I2C Bus Timing
The device’s on-chip I2C provides the serial interface that meets the I2C bus standard mode
specification. The I2C port handles byte transfers autonomously. To enable this port, the bit ENS1
in I2CON should be set to '1'. The I2C H/W interfaces to the I2C bus via two pins: SDA (Px.y,
serial data line) and SCL (Px.y, serial clock line). Pull up resistor is needed for Pin Px.y and Px.y
for I2C operation as these are open drain pins. When the I/O pins are used as I2C port, user must
set the pins function to I2C in advance.
6.5.2 Features
The I2C bus uses two wires (SDA and SCL) to transfer information between devices connected to
the bus. The main features of the bus are:
Support Master and Slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master)
Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 35 - Revision V1.0
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer
Built-in a 14-bit time-out counter will request the I2C interrupt if the I2C bus hangs up
and timer-out counter overflows.
External pull-up are needed for high output
Programmable clocks allow versatile rate control
Supports 7-bit addressing mode
I2C-bus controllers support multiple address recognition ( Four slave address with mask
option)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 36 - Revision V1.0
6.6 PWM Generator and Capture Timer
6.6.1 Overview
NuMicro M051™ series has 2 sets of PWM group supports 4 sets of PWM Generators which can
be configured as 8 independent PWM outputs, PWM0~PWM7, or as 4 complementary PWM
pairs, (PWM0, PWM1), (PWM2, PWM3), (PWM4, PWM5) and (PWM6, PWM7) with 4
programmable dead-zone generators.
Each PWM Generator has one 8-bit prescaler, one clock divider with 5 divided frequencies (1,
1/2, 1/4, 1/8, 1/16), two PWM Timers including two clock selectors, two 16-bit PWM down-
counters for PWM period control, two 16-bit comparators for PWM duty control and one dead-
zone generator. The 4 sets of PWM Generators provide eight independent PWM interrupt flags
which are set by hardware when the corresponding PWM period down counter reaches zero.
Each PWM interrupt source with its corresponding enable bit can cause CPU to request PWM
interrupt. The PWM generators can be configured as one-shot mode to produce only one PWM
cycle signal or auto-reload mode to output PWM waveform continuously.
When PCR.DZEN01 is set, PWM0 and PWM1 perform complementary PWM paired function; the
paired PWM timing, period, duty and dead-time are determined by PWM0 timer and Dead-zone
generator 0. Similarly, the complementary PWM pairs of (PWM2, PWM3), (PWM4, PWM5) and
(PWM6, PWM7) are controlled by PWM2, PWM4 and PWM6 timers and Dead-zone generator 2,
4 and 6, respectively. Refer to figures bellowed for the architecture of PWM Timers.
To prevent PWM driving output pin with unsteady waveform, the 16-bit period down counter and
16-bit comparator are implemented with double buffer. When user writes data to
counter/comparator buffer registers the updated value will be load into the 16-bit down counter/
comparator at the time down counter reaching zero. The double buffering feature avoids glitch at
PWM outputs.
When the 16-bit period down counter reaches zero, the interrupt request is generated. If PWM-
timer is set as auto-reload mode, when the down counter reaches zero, it is reloaded with PWM
Counter Register (CNRx) automatically then start decreasing, repeatedly. If the PWM-timer is set
as one-shot mode, the down counter will stop and generate one interrupt request when it reaches
zero.
The value of PWM counter comparator is used for pulse high width modulation. The counter
control logic changes the output to high level when down-counter value matches the value of
compare register.
The alternate feature of the PWM-timer is digital input Capture function. If Capture function is
enabled the PWM output pin is switched as capture input mode. The Capture0 and PWM0 share
one timer which is included in PWM 0; and the Capture1 and PWM1 share PWM1 timer, and etc.
Therefore user must setup the PWM-timer before enable Capture feature. After capture feature is
enabled, the capture always latched PWM-counter to Capture Rising Latch Register (CRLR)
when input channel has a rising transition and latched PWM-counter to Capture Falling Latch
Register (CFLR) when input channel has a falling transition. Capture channel 0 interrupt is
programmable by setting CCR0.CRL_IE0[1] (Rising latch Interrupt enable) and
CCR0.CFL_IE0[2]] (Falling latch Interrupt enable) to decide the condition of interrupt occur.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 37 - Revision V1.0
Capture channel 1 has the same feature by setting CCR0.CRL_IE1[17] and CCR0.CFL_IE1[18].
And capture channel 0 to channel 3 on each group have the same feature by setting the
corresponding control bits in CCR0 and CCR2. For each group, whenever Capture issues
Interrupt 0/1/2/3, the PWM counter 0/1/2/3 will be reload at this moment.
The maximum captured frequency that PWM can capture is confined by the capture interrupt
latency. When capture interrupt occurred, software will do at least three steps, they are: Read
PIIRx to get interrupt source and Read PWM_CRLx/PWM_CFLx(x=0 and 3) to get capture value
and finally write 1 to clear PIIRx. If interrupt latency will take time T0 to finish, the capture signal
mustn’t transition during this interval (T0). In this case, the maximum capture frequency will be
1/T0. For example:
HCLK = 50 MHz, PWM_CLK = 25 MHz, Interrupt latency is 900 ns
So the maximum capture frequency will is 1/900ns ≈ 1000 kHz
6.6.2 Features
6.6.2.1 PWM function features:
PWM group has two PWM generators. Each PWM generator supports one 8-bit prescaler, one
clock divider, two PWM-timers (down counter), one dead-zone generator and two PWM outputs.
Up to 16 bits resolution
PWM Interrupt request synchronized with PWM period
One-shot or Auto-reload mode PWM
Up to 2 PWM group (PWMA/PWMB) to support 8 PWM channels
6.6.2.2 Capture Function Features:
Timing control logic shared with PWM Generators
8 capture input channels shared with 8 PWM output channels
Each channel supports one rising latch register (CRLR), one falling latch register (CFLR)
and Capture interrupt flag (CAPIFx)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 38 - Revision V1.0
6.7 Serial Peripheral Interface (SPI) Controller
6.7.1 Overview
The Serial Peripheral Interface (SPI) is a synchronous serial data communication protocol which
operates in full duplex mode. Devices communicate in master/slave mode with 4-wire bi-direction
interface. NuMicro M051™ series contains up to two sets of SPI controller performing a serial-to-
parallel conversion on data received from a peripheral device, and a parallel-to-serial conversion
on data transmitted to a peripheral device. Each set of SPI controller can be set as a master; it
also can be configured as a slave device controlled by an off-chip master device.
6.7.2 Features
z Up to two sets of SPI controller
z Support master or slave mode operation
z Configurable bit length up to 32 bits of a transfer word and configurable word numbers up to 2
of a transaction, so the maximum bit length is 64 bits for each data transfer
z Provide burst mode operation, transmit/receive can be transferred up to two times word
transaction in one transfer
z Support MSB or LSB first transfer
z Byte or word Suspend Mode
z Variable output serial clock frequency in master mode
z Support two programmable serial clock frequencies in master mode
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 39 - Revision V1.0
6.8 Timer Controller
6.8.1 Overview
The timer controller includes four 32-bit timers, TIMER0~TIMER3, which allows user to easily
implement a timer control for applications. The timer can perform functions like frequency
measurement, interval measurement, clock generation, delay timing, and so on. The timer can
generates an interrupt signal upon timeout, or provide the current value of count during operation.
6.8.2 Features:
Provides four channels of 32-bit timers with one 8-bit pre-scale counter with four 24-bit up-
timer
Independent clock source for each timer.
24-bit timer value is readable through TDR (Timer Data Register)
Provides one-shot, periodic and toggle operation modes.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 40 - Revision V1.0
6.9 Watchdog Timer (WDT)
6.9.1 Overview
The purpose of Watchdog Timer is to perform a system reset when system runs into an unknown
state. This prevents system from hanging for an infinite period of time. Besides, this Watchdog
Timer supports another function to wakeup CPU from power-down mode. The watchdog timer
includes a 18-bit free running counter with programmable time-out intervals. Table 6–4 shows the
watchdog timeout interval selection and Figure 6–14 shows the timing of watchdog interrupt
signal and reset signal.
Setting WTE (WDTCR [7]) enables the watchdog timer and the WDT counter starts counting up.
When the counter reaches the selected time-out interval, Watchdog timer interrupt flag WTIF will
be set immediately to request a WDT interrupt if the watchdog timer interrupt enable bit WTIE is
set, in the meanwhile, a specified delay time (1024 * TWDT) follows the time-out event. User must
set WTR (WDTCR [0]) (Watchdog timer reset) high to reset the 18-bit WDT counter to avoid CPU
from Watchdog timer reset before the delay time expires. WTR bit is cleared automatically by
hardware after WDT counter is reset. There are eight time-out intervals with specific delay time
which are selected by Watchdog timer interval select bits WTIS (WDTCR [10:8]). If the WDT
counter has not been cleared after the specific delay time expires, the watchdog timer will set
Watchdog Timer Reset Flag (WTRF) high and reset CPU. This reset will last 63 WDT clocks
(TRST) then CPU restarts executing program from reset vector (0x0000 0000). WTRF will not be
cleared by Watchdog reset. User may poll WTFR by software to recognize the reset source. WDT
also provides wakeup function. When chip is powered down and the Watchdog Timer Wakeup
Function Enable bit (WDTR[4]) is set, if the WDT counter has not been cleared after the specific
delay time expires, the chip will be waken up from power down state.
WTIS Timeout Interval
Selection
TTIS
Interrupt Period
TINT
WTR Timeout Interval
(WDT_CLK=10 kHz)
Min. TWTR ~ Max. TWTR
000 24 * TWDT 1024 * TWDT 1.6 ms ~ 104 ms
001 26 * TWDT 1024 * TWDT 6.4 ms ~ 108.8 ms
010 28 * TWDT 1024 * TWDT 25.6 ms ~ 128 ms
011 210 * TWDT 1024 * TWDT 102.4 ms ~ 204.8 ms
100 212 * TWDT 1024 * TWDT 409.6 ms ~ 512 ms
101 214 * TWDT 1024 * TWDT 1.6384 s ~ 1.7408 s
110 216 * TWDT 1024 * TWDT 6.5536 s ~ 6.656 s
111 218 * TWDT 1024 * TWDT 26.2144 s ~ 26.3168 s
Table 6–4 Watchdog Timeout Interval Selection
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 41 - Revision V1.0
Figure 6–14 Timing of Interrupt and Reset Signal
6.9.2 Features
18-bit free running counter to avoid CPU from Watchdog timer reset before the delay time
expires.
Selectable time-out interval (2^4 ~ 2^18) and the time out interval is 1.6 ms ~ 26.21 s (if
WDT_CLK = 10 kHz).
Reset period = WDT_CLK * 63
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 42 - Revision V1.0
6.10 UART Interface Controller
NuMicro M051™ series provides up to two channels of Universal Asynchronous
Receiver/Transmitters (UART). UART0~1 performs Normal Speed UART, and support flow
control function.
6.10.1 Overview
The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel
conversion on data received from the peripheral, and a parallel-to-serial conversion on data
transmitted from the CPU. The UART controller also supports IrDA SIR Function, and RS-485
mode functions. Each UART channel supports five types of interrupts including transmitter FIFO
empty interrupt (INT_THRE), receiver threshold level reaching interrupt (INT_RDA), line status
interrupt (parity error or framing error or break interrupt) (INT_RLS), receiver buffer time out
interrupt (INT_TOUT), and MODEM/Wakeup status interrupt (INT_MODEM). Interrupt number 12
(vector number is 28) supports UART0 interrupt. Interrupt number 13 (vector number is 29)
supports UART1 interrupt. Refer to Nested Vectored Interrupt Controller chapter for System
Interrupt Map.
The UART0~1 are equipped 15-bytes transmitter FIFO (TX_FIFO) and 15-bytes receiver FIFO
(RX_FIFO). The CPU can read the status of the UART at any time during the operation. The
reported status information includes the type and condition of the transfer operations being
performed by the UART, as well as 3 error conditions (parity error, framing error, and break
interrupt) probably occur while receiving data. The UART includes a programmable baud rate
generator that is capable of dividing clock input by divisors to produce the serial clock that
transmitter and receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD +
2], where M and BRD are defined in Baud Rate Divider Register (UA_BAUD). The Table 6–5 and
Table 6–6 list the equations in the various conditions and the UART baud rate setting table.
Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud rate equation
0 0 0 B A UART_CLK / [16 * (A+2)]
1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8
2 1 1 Don’t care A UART_CLK / (A+2), A must >=3
Table 6–5 UART Baud Rate Equation
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 43 - Revision V1.0
System clock = 22.1184 MHz
Baud rate Mode0 Mode1 Mode2
921600 x A=0,B=11 A=22
460800 A=1 A=1,B=15
A=2,B=11 A=46
230400 A=4 A=4,B=15
A=6,B=11 A=94
115200 A=10 A=10,B=15
A=14,B=11 A=190
57600 A=22 A=22,B=15
A=30,B=11 A=382
38400 A=34
A=62,B=8
A=46,B=11
A=34,B=15
A=574
19200 A=70
A=126,B=8
A=94,B=11
A=70,B=15
A=1150
9600 A=142
A=254,B=8
A=190,B=11
A=142,B=15
A=2302
4800 A=286
A=510,B=8
A=382,B=11
A=286,B=15
A=4606
Table 6–6 UART Baud Rate Setting Table
The UART0 and UART1 controllers support auto-flow control function that uses two low-level
signals, /CTS (clear-to-send) and /RTS (request-to-send), to control the flow of data transfer
between the UART and external devices (ex: Modem). When auto-flow is enabled, the UART is
not allowed to receive data until the UART asserts /RTS to external device. When the number of
bytes in the RX FIFO equals the value of RTS_TRI_LEV (UA_FCR [19:16]), the /RTS is de-
asserted. The UART sends data out when UART controller detects /CTS is asserted from external
device. If a valid asserted /CTS is not detected the UART controller will not send data out.
The UART controllers also provides Serial IrDA (SIR, Serial Infrared) function (User must set
IrDA_EN (UA_FUN_SEL[1:0]) to enable IrDA function). The SIR specification defines a short-
range infrared asynchronous serial transmission mode with one start bit, 8 data bits, and 1 stop
bit. The maximum data rate is 115.2 Kbps (half duplex). The IrDA SIR block contains an IrDA SIR
Protocol encoder/decoder. The IrDA SIR protocol is half-duplex only. So it cannot transmit and
receive data at the same time. The IrDA SIR physical layer specifies a minimum 10ms transfer
delay between transmission and reception. This delay feature must be implemented by software.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 44 - Revision V1.0
Another alternate function of UART controllers is RS-485 9 bit mode function, and direction
control provided by RTS pin or can program GPIO (P0.3 for RTS0 and P0.1 for RTS 1) to
implement the function by software. The RS-485 mode is selected by setting the UA_FUN_SEL
register to select RS-485 function. The RS-485 driver control is implemented using the RTS
control signal from an asynchronous serial port to enable the RS-485 driver. In RS-485 mode,
many characteristics of the RX and TX are same as UART.
6.10.2 Features
Full duplex, asynchronous communications
Separate receive / transmit 15 bytes (UART0/UART1) entry FIFO for data payloads
Support hardware auto flow control/flow control function (CTS, RTS) and programmable RTS
flow control trigger level (UART0 and UART1 support)
Programmable receiver buffer trigger level
Support programmable baud-rate generator for each channel individually
Support CTS wake up function (UART0 and UART1 support)
Support 7 bit receiver buffer time out detection function
Programmable transmitting data delay time between the last stop and the next start bit by
setting UA_TOR [DLY] register
Support break error, frame error, and parity error detect function
Fully programmable serial-interface characteristics
Programmable number of data bit, 5, 6, 7, 8 bit character
Programmable parity bit, even, odd, no parity or stick parity bit generation and detection
Programmable stop bit, 1, 1.5, or 2 stop bit generation
Support IrDA SIR function mode
Support for 3/16 bit duration for normal mode
Support RS-485 function mode.
Support RS-485 9bit mode
Support hardware or software direct enable control provided by RTS pin
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 45 - Revision V1.0
6.11 Analog-to-Digital Convert er (ADC)
6.11.1 Overview
NuMicro M051™ series contain one 12-bit successive approximation analog-to-digital converters
(SAR A/D converter) with 8 input channels. The A/D converter supports four operation modes:
single, burst, single-cycle scan and continuous scan mode. The A/D converters can be started by
software and external STADC/P3.2 pin.
6.11.2 Features
Analog input voltage range: 0~AVDD (Max to 5.0V).
12-bit resolution and 10-bit accuracy is guaranteed.
Up to 8 single-end analog input channels or 4 differential analog input channels.
Maximum ADC clock frequency is 16 MHz.
Up to 600k SPS conversion rate.
Four operating modes
- Single mode: A/D conversion is performed one time on a specified channel.
- Single-cycle scan mode: A/D conversion is performed one cycle on all specified
channels with the sequence from the lowest numbered channel to the highest numbered
channel.
- Continuous scan mode: A/D converter continuously performs Single-cycle scan mode
until software stops A/D conversion.
- Burst mode: A/D conversion will sample and convert the specified single channel and
sequentially store in FIFO.
An A/D conversion can be started by
- Software Write 1 to ADST bit
- External pin STADC
Conversion results are held in data registers for each channel with valid and overrun
indicators.
Conversion result can be compared with specify value and user can select whether to
generate an interrupt when conversion result matches the compare register setting.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 46 - Revision V1.0
Channel 7 supports 2 input sources: external analog voltage and internal fixed bandgap
voltage.
Support Self-calibration to minimize conversion error.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 47 - Revision V1.0
6.12 External Bus Interface (EBI)
6.12.1 Overview
NuMicro M051™ series equips an external bus interface (EBI) for external device used.
To save the connections between external device and this chip, EBI support address bus and
data bus multiplex mode. And, address latch enable (ALE) signal supported differentiate the
address and data cycle.
6.12.2 Features
External Bus Interface has the following functions:
1. External devices with max. 64K-byte size (8 bit data width)/128K-byte (16 bit data width)
supported
2. Variable external bus base clock (MCLK) supported
3. 8 bit or 16 bit data width supported
4. Variable data access time (tACC), address latch enable time (tALE) and address hold time
(tAHD) supported
5. Address bus and data bus multiplex mode supported to save the address pins
6. Configurable idle cycle supported for different access condition: Write command finish
(W2X), Read-to-Read (R2R)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 48 - Revision V1.0
6.13 Flash Memory Controller (FMC)
6.13.1 Overview
M058/M0516 equips with 64K/32K bytes on chip embedded Flash EEPROM for application
program memory (APROM) that can be updated through ISP/IAP procedure. In System
Programming (ISP) function enables user to update program memory when chip is soldered on
PCB. After chip power on Cortex-M0 CPU fetches code from APROM or LDROM decided by boot
select (CBS) in Config0. By the way, NuMicro M051™ series also provide additional 4K bytes
DATA Flash for user to store some application depended data before chip power off.
6.13.2 Features
Run up to 50 MHz with zero wait state for continuous address read access
64/32KB application program memory (APROM)
4KB in system programming (ISP) loader program memory (LDROM)
Fixed 4KB data flash with 512 bytes page erase unit
In System Program (ISP)/In Application Program (IAP) to update on chip Flash EPROM
In Circuit Program (ICP) via serial wire debug interface (SWD)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 49 - Revision V1.0
7 TYPICAL APPLICATION CIRCUIT
AA12
RI2C1
4.7K
AD0
RI2C2
4.7K
AD1
AD2
DVDD
RXD0
TXD 0
DVDD
I2C-EEPROM
24LC64
UI2C1
SOIC8\ 1.27\5. 6MM
GND
4A2
3A1
2A0
1
SDA 5
SCL 6
WP 7
VCC 8
I2C
AD3
EEPROM
ADDRESS:0H
CB9
0.1 uF
DVDD
MET22
MET23
DVDD
DVDD
MISO_1
nSS1
P32
USPI1
W25X16VSSIG
SOIC -8P
CS#
1
DO
2
WP#
3
GND
4DI 5
CLK 6
HOLD# 7
VCC 8
SPI
DVDD
RSPI1
4.7K
RSPI 2
4.7K
CB7
0.1 uF
SCLK1
MOSI _1
SDA
SCL
SDA
AD4
SCL
nWR
AD5
AD12
AD6
AD11
AD10
AD13
AD7
AD14
nTICER ST
AVDD
AD5
AD6
P40
ALE
AD7
AD9
AD8
AD3
UART_TXD
RXD0
TXD1
RXD1
TXD0
S1
SW D IP-4
SWDIP8
1
2
3
4
8
7
6
5
UART_RXD
AD4
nRD
AD5
EBI
D12MO
AD6
L1 FB
AD7
CB3
0.1 uF
CB4
0.1 uF
nWR
AVDD
DVDD
D12MI
DVSS
CB8
0.1 uF
DVSS
U4
M052_54 LQFP 48
M052_LQFP_48
AIN1/T2/P1.1 44
AIN2/RXD 1/P1.2 45
AIN3/TXD1/P1.3 46
AIN3/SS0/P1.4 47
P4.2 48
MOSI_0/AIN5/P1.5
1
MISO_0/AIN6/P1.6
2
SCLK0/AIN7/P1.7
3
VSS
17
LDO_C AP
18
P2.0 /AD 8/PW M 0
19
P2.1 /AD 9/PW M 1
20
P2.2 /AD 10/P W M 2
21
P2.3 /AD 11/P W M 3
22
P2.4 /AD 12/P W M 4
23
P4.0
24
P2.6/AD14/PWM6 26
P4.6/ICE_CLK 30
P4.7/ICE_DAT 31
P0.7/AD7/SCLK1 32
P0.6/AD6/MISO_1 33
P0.5/AD5/MOSI_1 34
P0.4/AD4/SS1 35
P4.1 36
P0.3/AD3/R TS0 37
P0.2/AD2/C TS0 38
P0.1/AD1/R TS1 39
RST
4
RXD/P3.0
5
AVSS
6
MCLK/INT1/P3.3
9
TXD/ P 3 .1
7
INT0/P3.2
8
SDA/T0/P3.4
10
SCL/T1/P3.5
11
P4.3
12
P3.6 /W R /C K O
13
P4.5/ALE 29
P4.4/CS 28
AIN0/T2/P1.0 43
AVDD 42
VDD 41
P0.0/AD0/C TS1 40
P3.7 /R D
14
XTAL1
16 XTAL2
15
P2.5/AD13/PWM5 25
P2.7/AD15/PWM7 27
MOSI_ 0
AA15
AVSS
MISO_ 0
SCLK0
AA14
AVSS
nTICERST
AA13
DVSS
P33
P41
L2 FB
AA5
AD4
TICEDA T
ADC Input
TICECL K
ALE
AA6
nCS
CB5
0.1 uF
DVDD
DVDD
DVSS
CB6
0.1 uF
DVSS
AD15
U3
BS616LV4017EG70(TSOP-44)
A4
1
A3
2
A2
3
A1
4
A0
5
CS
6
I/O0
7
I/O1
8
I/O2
9
I/O3
10
VCC
11
VSS
12
I/O4
13
I/O5
14
I/O6
15
I/O7
16
WE
17
A17
18
A16
19
A15
20
A14
21
A13
22
NC 28
A8 27
A12 23
A11 24
A9 26
A10 25
I/O8 29
I/O9 30
I/O10 31
I/O11 32
VCC 33
VSS 34
I/O12 35
I/O13 36
I/O14 37
I/O15 38
LB 39
UB 40
OE 41
A5 44
A6 43
A7 42 AA7
AD3
CB1
0.1 uF
AD2
nRD
Tit le
Size Document Number Rev
Date: Sheet of
Application.dsn
1.0
M052_54 Application Circuit
11Thursday , Augus t 19, 2010
C5
10uF
TAN T- B
AD1
AD0
DVDD
AD12
AD11
AD10
AD9
AD8
ALE
AD15
AD14
AD13
CB2
0.1 uF
AA10
AA9
AA8
P42
U2
74F373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
OE
1LE
11
Q0 2
Q1 5
Q2 6
Q3 9
Q4 12
Q5 15
Q6 16
Q7 19
VCC 20
GND
10
AA13
AA12
AA11
AA15
AA14
AD15
nSS0
AD14
TXD 1
AD13
RXD1
AD12
P11
AA4
AD11
AA0
AA3
P43
AA1
AD10
AA2
C3
820pF
AA2
AD9
AA3
AA1
AA4
AD8
AA0
AA5
nCS
U1
74F373
D0
3
D1
4
D2
7
D3
8
D4
13
D5
14
D6
17
D7
18
OE
1LE
11
Q0 2
Q1 5
Q2 6
Q3 9
Q4 12
Q5 15
Q6 16
Q7 19
VCC 20
GND
10
AA6
ADC
AA8
AD0
AA7
AD1
ICE Interface
C1
10uF/10V
TAN T- A
DVDD
AA9
R1
10K
Reset Circuit
AD2
X1
12MHz
XT A L3 - 1
C4
20p
D12MO
C2
20p
D12MI
Crystal
AA10
CON1
1X2 HEADER
1
1
2
2
UART_TXD
UART_RXD
UART
DVDD
VDD NET4
NET5
NET40
NET3
NET9
NET8
NET6
NET7
VSS
R4 33
NET10
R6 33
NET12
NET13NET11
U5
MAX2 32 A
SOP16/150
C1+
1
V+
2
C1-
3
C2+
4
C2-
5
V-
6
T2OUT
7
R2IN
8R2OUT 9
T2I N 10
T1I N 11
R1OUT 12
R1IN 13
T1OUT 14
GND 15
VCC 16
AA11
C7
1uF
TAN T-A
C6
1uF
TAN T- A
C9
1uF
TAN T-A
C8 1uF
TAN T- A
P1
DB9-M (公)
DB9L-HP
5
9
4
8
3
7
2
6
1
10
11
R3
33
R5
33
ICEJP1
HEADER 5X2
HEADER5X2
1 2
3 4
5 6
7 8
910
nTICERST
TI C EC L K
TI C ED A T
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 50 - Revision V1.0
8 ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT
DC Power Supply VDD−VSS -0.3 +7.0 V
Input Voltage VIN VSS-0.3 VDD+0.3 V
Oscillator Frequency 1/tCLCL 0 40 MHz
Operating Temperature TA -40 +85 °C
Storage Temperature TST -55 +150 °C
Maximum Current into VDD - 120 mA
Maximum Current out of VSS 120 mA
Maximum Current sunk by a I/O pin 35 mA
Maximum Current sourced by a I/O
pin 35 mA
Maximum Current sunk by total I/O
pins 100 mA
Maximum Current sourced by total
I/O pins 100 mA
Note: Exposure to conditions beyond those listed under absolute maximum ratings may adversely affect s the lif t and reliability of the device.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 51 - Revision V1.0
8.2 DC Electrical Characteristics
(VDD-VSS=2.5~5.5V, TA = 25°C, FOSC = 50 MHz unless otherwise specified.)
SPECIFICATION
PARAMETER SYM. MIN. TYP. MAX. UNIT TEST CONDITIONS
Operation voltage VDD 2.5 5.5 V VDD =2.5V ~ 5.5V up to 50 MHz
Power Ground VSS
AVSS -0.3 V
LDO Output Voltage VLDO -10% 2.45 +10% V VDD > 2.7V
Band Gap Analog Input VBG -5% 1.26 +5% V VDD =2.5V ~ 5.5V
Analog Operating
Voltage AVDD 0 VDD V
IDD1 32 mA VDD= 5.5V@50 MHz,
enable all IP and PLL, XTAL=12 MHz
IDD2 24 mA VDD=5.5V@50 MHz, disable all IP and
enable PLL, XTAL=12 MHz
IDD3 31 mA VDD = 3V@50 MHz, enable all IP and PLL,
XTAL=12 MHz
Operating Current
Normal Run Mode
@ 50 MHz
IDD4 23 mA VDD = 3V@50 MHz, disable all IP and
enable PLL, XTAL=12 MHz
IDD5 17 mA VDD = 5.5V@ 12MHz, enable all IP and
disable PLL, XTAL=12 MHz
IDD6 14 mA VDD = 5.5V@12 MHz, disable all IP and
disable PLL, XTAL=12 MHz
IDD7 16 mA VDD = 3V@12 MHz, enable all IP and
disable PLL, XTAL=12 MHz
Operating Current
Normal Run Mode
@ 12 MHz
IDD8 13 mA VDD = 3V@12 MHz, disable all IP and
disable PLL, XTAL=12 MHz
IDD9 12 mA VDD = 5.5V@4 MHz, enable all IP and
disable PLL, XTAL=4MHz
IDD10 10 mA VDD = 5.5V@4 MHz, disable all IP and
disable PLL, XTAL=4MHz
IDD11 10 mA VDD = 3V@4 MHz, enable all IP and
disable PLL, XTAL=4MHz
Operating Current
Normal Run Mode
@ 4 MHz
IDD12 9 mA VDD = 3V@4 MHz, disable all IP and
disable PLL, XTAL=4 MHz
Operating Current IIDLE1 19 mA VDD= 5.5V@50 MHz, enable all IP and
PLL, XTAL=12 MHz
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 52 - Revision V1.0
IIDLE2 11 mA VDD=5.5V@50 MHz, disable all IP and
enable PLL, XTAL=12 MHz
IIDLE3 18 mA VDD = 3V@50 MHz, enable all IP and PLL,
XTAL=12 MHz
Idle Mode
@ 50 MHz
IIDLE4 10 mA VDD = 3V@50 MHz, disable all IP and
enable PLL, XTAL=12 MHz
IIDLE5 10 mA VDD = 5.5V@12 MHz, enable all IP and
disable PLL, XTAL=12 MHz
IIDLE6 7 mA VDD = 5.5V@12 MHz, disable all IP and
disable PLL, XTAL=12 MHz
IIDLE7 9 mA VDD = 3V@12 MHz, enable all IP and
disable PLL, XTAL=12 MHz
Operating Current
Idle Mode
@ 12 MHz
IIDLE8 6 mA VDD = 3V@12 MHz, disable all IP and
disable PLL, XTAL=12 MHz
IIDLE9 5 mA VDD = 5.5V@4 MHz, enable all IP and
disable PLL, XTAL=4 MHz
IIDLE10 4 mA VDD = 5.5V@4 MHz, disable all IP and
disable PLL, XTAL=4 MHz
IIDLE11 4 mA VDD = 3V@4 MHz, enable all IP and
disable PLL, XTAL=4 MHz
Operating Current
Idle Mode
@ 4 MHz
IIDLE12 3 mA VDD = 3V@4 MHz, disable all IP and
disable PLL, XTAL=4 MHz
IPWD1 15 μA VDD = 5.5V, No load @ Disable BOV
function
Standby Current
Power-down Mode
(Deep Sleep Mode) IPWD2 11 μA VDD = 3.0V, No load @ Disable BOV
function
Input Current P0/1/2/3/4
(Quasi-bidirectional
mode)
IIN1 -50
-60 μA VDD = 5.5V, VIN = 0.4V
Input Leakage Current
P0/1/2/3/4 ILK -2 - +2
μA VDD = 5.5V, 0<VIN<VDD
Logic 1 to 0 Transition
Current P0/1/2/3/4
(Quasi-bidiretional
mode)
ITL
[3] -650 - -200 μA VDD = 5.5V, VIN<2.0V
-0.3 - 0.8 VDD = 4.5V
Input Low Voltage
P0/1/2/3/4 (TTL input) VIL1 -0.3 - 0.6 V VDD = 2.5V
2.0 -
VDD
+0.2 VDD = 5.5V
Input High Voltage
P0/1/2/3/4 (TTL input) VIH1
1.5 -
VDD
+0.2
V
VDD =3.0V
0 - 0.8 V VDD = 4.5V
Input Low Voltage XT1[*2] VIL3 0 - 0.4 VDD = 3.0V
3.5 -
VDD
+0.2 V VDD = 5.5V
Input High Voltage
XT1[*2] VIH3
2.4 -
VDD
+0.2 V
DD = 3.0V
Negative going threshold
(Schmitt input), /RST
VILS -0.5 - 0.3VDD V
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 53 - Revision V1.0
Positive going threshold
(Schmitt input), /RST VIHS 0.7VDD - VDD+0.
5 V
Internal /RST pin pull up
resistor RRST 40 150 KΩ
Negative going threshold
(Schmitt input),
P0/1/2/3/4
VILS -0.5 - 0.2VDD V
Positive going threshold
(Schmitt input),
P0/1/2/3/4
VIHS 0.4VDD - VDD
+0.5 V
ISR11 -300 -370 -450 μA VDD = 4.5V, VS = 2.4V
ISR12 -50 -70 -90 μA VDD = 2.7V, VS = 2.2V
Source Current
P0/1/2/3/4 (Quasi-
bidirectional Mode)
ISR12 -40 -60 -80 μA VDD = 2.5V, VS = 2.0V
ISR21 -20 -24 -28 mA VDD = 4.5V, VS = 2.4V
ISR22 -4 -6 -8 mA VDD = 2.7V, VS = 2.2V
Source Current
P0/1/2/3/4 (Push-pull
Mode)
ISR22 -3 -5 -7 mA VDD = 2.5V, VS = 2.0V
ISK1 10 16 20 mA VDD = 4.5V, VS = 0.45V
ISK1 7 10 13 mA VDD = 2.7V, VS = 0.45V
Sink Current P0/1/2/3/4
(Quasi-bidirectional and
Push-pull Mode)
ISK1 6 9 12 mA VDD = 2.5V, VS = 0.45V
Brownout voltage with
BOV_VL [1:0] =00b VBO2.2 2.1 2.2 2.3 V
Brownout voltage with
BOV_VL [1:0] =01b VBO2.7 2.6 2.7 2.8 V
Brownout voltage with
BOV_VL [1:0] =10b VBO3.8 3.7 3.8 3.9 V
Brownout voltage with
BOV_VL [1:0] =11b VBO4.5 4.4 4.5 4.6 V
Hysteresis range of BOD
voltage VBH 30 - 150 mV VDD = 2.5V~5.5V
Notes:
1. /RST pin is a Schmitt trigger input.
2. XTAL1 is a CMOS input.
3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, 5he transition current
reaches its maximum value when Vin approximates to 2V .
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 54 - Revision V1.0
8.3 AC Electrical Characteristics
8.3.1 External Crystal
Note: Duty cycle is 50%.
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITION
Clock High Time tCHCX 20 - 125 nS
Clock Low Time tCLCX 20 - 125 nS
Clock Rise Time tCLCH - - 10 nS
Clock Fall Time tCHCL - - 10 nS
8.3.2 External Oscillator
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Input clock frequency External crystal 4 12 24 MHz
Temperature - -40 - 85 ℃
VDD - 2.5 5 5.5 V
Operating current 12 MHz@ VDD = 5V - 5 - mA
8.3.3 Typical Crystal Application Circuits
CRYSTAL C1 C2
4 MHz ~ 24 MHz Optional
(Depend on crystal specification)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 55 - Revision V1.0
Figure 8–1 Typical Crystal Application Circuit
8.3.4 Internal 22.1184 MHz RC Oscillator
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Supply voltage[1] - 2.5 - 5.5 V
Center Frequency - - 22.1184 MHz
+25 C; V DD =5V -1 - +1 %
Calibrated Internal Oscillator
Frequency -40C~+85C;
VDD=2.5V~5.5V -3 - +3 %
Accuracy of Un-calibrated
Internal Oscillator Frequency
-40C~+85C;
VDD=2.5V~5.5V -25 - +25 %
Operating current VDD =5V - 500 - uA
8.3.5 Internal 10kHz RC Oscillator
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Supply voltage[1] - 2.5 - 5.5 V
Center Frequency - - 10 - kHz
+25 C; V DD =5V -30 - +30 %
Calibrated Internal Oscillator
Frequency -40C~+85C;
VDD=2.5V~5.5V -50 - +50 %
Operating current VDD =5V - 5 - uA
Notes:
1. Internal operation voltage comes form LDO.
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 56 - Revision V1.0
8.4 Analog Characteristics
8.4.1 Specification of 600kHz sps 12-bit SARADC
PARAMETER SYM. MIN. TYP. MAX. UNIT
Resolution - - - 12 Bit
Differential nonlinearity error DNL - ±1.2 - LSB
Integral nonlinearity error INL - ±1.5 - LSB
Offset error EO - +4 10 LSB
Gain error (Transfer gain) EG - +7 1.005 -
Monotonic - Guaranteed -
ADC clock frequency FADC - - 20 MHz
Calibration time TCAL - 127 - Clock
Sample time TS - 7 - Clock
Conversion time TADC - 13 - Clock
Sample rate FS - - 600 k sps
VLDO - 2.5 - V
Supply voltage
VADD 3 - 5.5 V
IDD - 0.5 - mA
Supply current (Avg.)
IDDA - 1.5 - mA
Input voltage range VIN 0 - AVDD V
Capacitance CIN - 5 - pF
8.4.2 Specification of LDO & Power management
PARAMETER MIN TYP MAX UNIT NOTE
Input Voltage 2.7 5 5.5 V VDD input voltage
Output Voltage
(bypass=0)
-10% 2.45 +10% V LDO output voltage
Output Voltage
(bypass=1)
-10% Input Voltage +10% V Input Voltage < 2.7V
Quiescent Current - 100 - uA
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 57 - Revision V1.0
(PD=0, bypass=0)
Quiescent Current
(PD=1, bypass=0)
- 5 - uA
Quiescent Current
(PD=1, bypass=1)
- 5 - uA
Iload (PD=0) - - 100 mA
Iload (PD=1) - - 100 uA
Cbp - 1u - F Resr=1ohm
Cload - 250p - F
Note:
1. It is recommended that a 10uF or higher capacitor and a 100nF bypass capacitor are
connected between VDD and the closest VSS pin of the device.
2. For ensuring power stability, a 4.7uF or higher capacitor must be connected between LDO
pin and the closest VSS pin of the device. Also a 100nF bypass capacitor between LDO and
VSS help suppressing output noise.
8.4.3 Specification of Low Voltage Reset
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Operation voltage - 1.7 - 5.5 V
Quiescent current VDD5V=5.5V - - 5 uA
Temperature=25° 1.7 2.0 2.3 V
Temperature=-40° - 2.4 - V
Threshold voltage
Temperature=85° - 1.6 - V
Hysteresis - 0 0 0 V
8.4.4 Specification of Brownout Detector
Parameter Condition Min. Typ. Max. Unit
Operation voltage - 2.5 - 5.5 V
Quiescent current AVDD=5.5V - - 125 μA
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 58 - Revision V1.0
Temperature - -40 25 85 ℃
BOV_VL[1:0]=11 4.4 4.5 4.6 V
BOV_VL [1:0]=10 3.7 3.8 3.9 V
BOV_VL [1:0]=01 2.6 2.7 2.8 V
Brownout voltage
BOV_VL [1:0]=00 2.1 2.2 2.3 V
Hysteresis - 30m - 150m V
8.4.5 Specification of Power-On Reset (5V)
Parameter Condition Min. Typ. Max. Unit
Reset voltage V+ - 2 - V
Quiescent current Vin>reset voltage - 1 - nA
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 59 - Revision V1.0
8.5 SPI Dynamic characteristics
Symbol Parameter Min Typ Max Unit
SPI master mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor)
tDS Data setup time 35 - - ns
tDH Data hold time 0 - - ns
tV Data output valid time - - 10 ns
SPI master mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor)
tDS Data setup time 45 - - ns
tDH Data hold time 0 - - ns
tV Data output valid time - - 16 ns
SPI slave mode (VDD = 4.5V ~ 5.5V, 30pF loading Capacitor)
tDS Data setup time 0 - - ns
tDH Data hold time 2*PCLK+4 - - ns
tV Data output valid time - - 2*PCLK+40 ns
SPI slave mode (VDD = 3.0V ~ 3.6V, 30pF loading Capacitor)
tDS Data setup time 0 - - ns
tDH Data hold time 2*PCLK+5 - - ns
tV Data output valid time - - 2*PCLK+50 ns
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 60 - Revision V1.0
Figure 8–2 SPI Master timing
Figure 8–3 SPI Slave timing
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 61 - Revision V1.0
9 PACKAGE DIMENSIONS
9.1 LQFP-48 (7x7x1.4mm2 Footprint 2.0mm)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 62 - Revision V1.0
9.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitc h 0.5 mm)
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 63 - Revision V1.0
10 REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
V1.0 Mar 15, 2011 - Initial issued
M058/M0516 Data Sheet
Publication Release Date: Mar 15, 2011
- 64 - Revision V1.0
Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe property
damage. Such applications are deemed, “Insec ure Usage”.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomic
energy control instruments, airplane or spaceship instruments, the control or operation of
dynamic, brake or safety systems designed for vehicular use, traffic signal instruments, all
types of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customer’s risk, and in the event that third parties lay
claims to Nuvoton as a result of customer’s Insecure Usage, customer shall indemnify the
damages and liabilities thus incurred by Nuvoton.
