CAT28LV65W-20T - ON Semiconductor L.L.C.

Characteristics subject to change without notice

■CMOS and TTL compatible I/O

■Automatic page write operation:

– 1 to 32 bytes in 5ms

– Page load timer

■End of write detection:

– Toggle bit

– DATADATA

DATADATA

DATA polling

– RDY/BUSYBUSY

BUSYBUSY

BUSY

■Hardware and software write protection

■100,000 program/erase cycles

■100 year data retention

DESCRIPTION

The CAT28LV65 is a low voltage, low power, CMOS

parallel EEPROM organized as 8K x 8-bits. It requires a

simple interface for in-system programming. On-chip

address and data latches, self-timed write cycle with

auto-clear and VCC power up/down write protection

eliminate additional timing and protection hardware.

DATA Polling, RDY/BUSY and Toggle status bit signal

the start and end of the self-timed write cycle. Additionally,

the CAT28LV65 features hardware and software write

protection.

The CAT28LV65 is manufactured using Catalyst’s

advanced CMOS floating gate technology. It is designed

to endure 100,000 program/erase cycles and has a data

retention of 100 years. The device is available in JEDEC

approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32-

pin PLCC packages.

BLOCK DIAGRAM

FEATURES

■3.0V to 3.6V supply

■Read access times:

– 150/200/250ns

■Low power CMOS dissipation:

– Active: 8 mA max.

– Standby: 100 µA max.

■Simple write operation:

– On-chip address and data latches

– Self-timed write cycle with auto-clear

■Fast write cycle time:

– 5ms max.

■Commercial, industrial and automotive

temperature ranges

ADDR. BUFFER

& LATCHES

ADDR. BUFFER

& LATCHES

INADVERTENT

WRITE

PROTECTION

CONTROL

LOGIC

TIMER

ROW

DECODER

COLUMN

DECODER

HIGH V OL TA GE

GENERATOR

A5–A12

A0–A4

I/O0–I/O7

I/O BUFFERS

8,192 x 8

E2PROM

ARRAY

32 BYTE PAGE

VCC

DATA POLLING,

RDY/BUSY &

TOGGLE BIT

RDY/BUSY

64K-Bit CMOS PARALLEL EEPROM

CAT28LV65

Characteristics subject to change without notice

PIN CONFIGURATION

DIP Package (P, L)

TSOP Top View (8mm x 13.4mm) (H13)

SOIC Package (J, W) (K, X)

PLCC Package (N, G)

Vcc

RDY/BUSY

A12

A10

I/07

I/06

I/05

I/04

I/03

GND

I/O1

I/O0

I/O2

A11 1

PIN FUNCTIONS

Pin Name Function Pin Name Function

A0–A12 Address Inputs WE Write Enable

I/O0–I/O7Data Inputs/Outputs VCC 3.0 to 3.6 V Supply

CE Chip Enable VSS Ground

OE Output Enable NC No Connect

RDY/BSY Ready/Busy Status

I/O2

VSS

I/O6

I/O5

I/O0

I/O1

A10

I/O7

RDY/BUSY

A12

A6A9

A11

VCC

I/O4

I/O3

I/O013

A11

26 OE

A10

22 I/O7

I/O1

I/O2

VSS

I/O3

I/O4

I/O5

14 15 16 17 18 19 20

4321323130

A12

RDY/BUSY

VCC

I/O6

TOP VIEW

I/O2

VSS

I/O6

I/O5

I/O0

I/O1

A10

I/O7

A12

A6A9

A11

VCC

I/O4

I/O3

RDY/BUSY

CAT28LV65

Characteristics subject to change without notice

*COMMENT

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device.

These are stress ratings only, and functional operation

of the device at these or any other conditions outside of

those listed in the operational sections of this specifica-

tion is not implied. Exposure to any absolute maximum

rating for extended periods may affect device perfor-

mance and reliability.

ABSOLUTE MAXIMUM RATINGS*

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

Voltage on Any Pin with

Respect to Ground(2) ........... –2.0V to +VCC + 2.0V

VCC with Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (Ta = 25°C)................................... 1.0W

Lead Soldering Temperature (10 secs)............ 300°C

Output Short Circuit Current(3) ........................ 100 mA

RELIABILITY CHARACTERISTICS

Symbol Parameter Min. Max. Units Test Method

NEND(1) Endurance 105Cycles/Byte MIL-STD-883, Test Method 1033

TDR(1) Data Retention 100 Years MIL-STD-883, Test Method 1008

VZAP(1) ESD Susceptibility 2000 Volts MIL-STD-883, Test Method 3015

ILTH(1)(4) Latch-Up 100 mA JEDEC Standard 17

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is VCC +0.5V, which may overshoot to VCC +2.0V for periods of less than 20 ns.

(3) Output shorted for no more than one second. No more than one output shorted at a time.

(4) Latch-up protection is provided for stresses up to 100mA on address and data pins from –1V to VCC +1V.

MODE SELECTION

Mode CE WE OE I/O Power

Read L H L DOUT ACTIVE

Byte Write (WE Controlled) L H DIN ACTIVE

Byte Write (CE Controlled) L H DIN ACTIVE

Standby, and Write Inhibit H X X High-Z STANDBY

Read and Write Inhibit X H H High-Z ACTIVE

CAPACITANCE TA = 25°C, f = 1.0 MHz

Symbol Test Max. Units Conditions

CI/O(1) Input/Output Capacitance 10 pF VI/O = 0V

CIN(1) Input Capacitance 6 pF VIN = 0V

CAT28LV65

Characteristics subject to change without notice

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) Output floating (High-Z) is defined as the state when the external data line is no longer driven by the output buffer.

(3) VIHC = VCC –0.3V to VCC +0.3V.

D.C. OPERATING CHARACTERISTICS

Vcc = 3.0V to 3.6V, unless otherwise specified.

Limits

Symbol Parameter Min. Typ. Max. Units Test Conditions

ICC VCC Current (Operating, TTL) 8 mA CE = OE = VIL,

f = 1/tRC min, All I/O’s Open

ISBC(3) VCC Current (Standby, CMOS) 100 µA CE = VIHC,

All I/O’s Open

ILI Input Leakage Current –1 1 µAV

IN = GND to VCC

ILO Output Leakage Current –5 5 µAV

OUT = GND to VCC,

CE = VIH

VIH(3) High Level Input Voltage 2 VCC +0.3 V

VIL Low Level Input Voltage –0.3 0.6 V

VOH High Level Output Voltage 2 V IOH = –100µA

VOL Low Level Output Voltage 0.3 V IOL = 1.0mA

VWI Write Inhibit Voltage 2 V

28LV65-15 28LV65-20 28LV65-25

Symbol Parameter Min. Max. Min. Max. Min. Max. Units

tRC Read Cycle Time 150 200 250 ns

tCE CE Access Time 150 200 250 ns

tAA Address Access Time 150 200 250 ns

tOE OEAccess Time 70 80 100 ns

tLZ(1) CE Low to Active Output 0 0 0 ns

tOLZ(1) OE Low to Active Output 0 0 0 ns

tHZ(1)(2) CE High to High-Z Output 50 50 55 ns

tOHZ(1)(2) OE High to High-Z Output 50 50 55 ns

Output Hold from

tOH(1) Address Change 0 0 0 ns

A.C. CHARACTERISTICS, Read Cycle

Vcc = 3.0V to 3.6V, unless otherwise specified.

CAT28LV65

Characteristics subject to change without notice

DEVICE

UNDER

TEST

Vcc

1.8 K

OUTPUT

CL INCLUDES JIG CAPACITANCE

= 100 pF

1. 3K

INPUT PULSE LEVELS REFERENCE POINTS

2.0 V

0.6 V

V - 0.3 V

0.0 V

Figure 1. A.C. Testing Input/Output Waveform(4)

Figure 2. A.C. Testing Load Circuit (example)

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) A write pulse of less than 20ns duration will not initiate a write cycle.

(3) A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin;

however a transition from HIGH to LOW within tBLC max. stops the timer.

(4) Input rise and fall times (10% and 90%) < 10 ns.

28LV65-15 28LV65-20 28LV65-25

Symbol Parameter Min Max Min Max Min Max Units

tWC Write Cycle Time 5 5 5 ms

tAS Address Setup Time0 0 0 0 ns

tAH Address Hold Time 100 100 100 ns

tCS CE Setup Time 0 0 0 ns

tCH CE Hold Time 0 0 0 ns

tCW(2) CE Pulse Time 110 150 150 ns

tOES OE Setup Time 0 10 10 ns

tOEH OE Hold Time 0 10 10 ns

tWP(2) WE Pulse Width 110 150 150 ns

tDS Data Setup Time 60 100 100 ns

tDH Data Hold Time 0 0 0 ns

tINIT(1) Write Inhibit Period

After Power-up 5 10 5 10 5 10 ms

tBLC(1)(3) Byte Load Cycle Time 0.05 100 0.1 100 0.1 100 µs

tRB WE Low to RDY/Busy Low 220 220 220 ns

A.C. CHARACTERISTICS, Write Cycle

Vcc = 3.0V to 3.6V, unless otherwise specified.

CAT28LV65

Characteristics subject to change without notice

ADDRESS

DATA OUT

tAS

DATA IN D A TA V ALID

HIGH-Z

tCS

tAH tCH

tWC

tOEH

tBLC

tDH

tDS

tWP

RDY/BUSY

tOES

tRB

HIGH-Z HIGH-Z

ADDRESS

tRC

DATA OUT D A TA V ALIDD A TA V ALID

tCE

tOE

tOH

tAA

tOHZ

tHZ

VIH

HIGH-Z

tLZ

tOLZ

Byte Write

A write cycle is executed when both CE and WE are low,

and OE is high. Write cycles can be initiated using either

WE or CE, with the address input being latched on the

falling edge of WE or CE, whichever occurs last. Data,

conversely, is latched on the rising edge of WE or CE,

whichever occurs first. Once initiated, a byte write cycle

automatically erases the addressed byte and the new

data is written within 5 ms.

DEVICE OPERATION

Read

Data stored in the CAT28LV65 is transferred to the data

bus when WE is held high, and both OE and CE are held

low. The data bus is set to a high impedance state when

either CE or OE goes high. This 2-line control architec-

ture can be used to eliminate bus contention in a system

environment.

Figure 4. Byte Write Cycle [WE Controlled]

Figure 3. Read Cycle

CAT28LV65

Characteristics subject to change without notice

ADDRESS

DATA OUT

tAS

DATA IN DATA VALID

HIGH-Z

tAH

tWC

tOEH

tDH

tDS

tOES

tBLC

tCH

tCS

tCW

RDY/BUSY

tRB

HIGH-Z HIGH-Z

Page Write

The page write mode of the CAT28LV65 (essentially an

extended BYTE WRITE mode) allows from 1 to 32 bytes

of data to be programmed within a single EEPROM write

cycle. This effectively reduces the byte-write time by a

factor of 32.

Following an initial WRITE operation (WE pulsed low, for

tWP, and then high) the page write mode can begin by

issuing sequential WE pulses, which load the address

and data bytes into a 32 byte temporary buffer. The page

address where data is to be written, specified by bits A5

to A12, is latched on the last falling edge of WE. Each

byte within the page is defined by address bits A0 to A4

(which can be loaded in any order) during the first and

subsequent write cycles. Each successive byte load

cycle must begin within tBLC MAX of the rising edge of the

preceding WE pulse. There is no page write window

limitation as long as WE is pulsed low within tBLC MAX.

Upon completion of the page write sequence, WE must

stay high a minimum of tBLC MAX for the internal auto-

matic program cycle to commence. This programming

cycle consists of an erase cycle, which erases any data

that existed in each addressed cell, and a write cycle,

which writes new data back into the cell. A page write will

only write data to the locations that were addressed and

will not rewrite the entire page.

ADDRESS

I/O

tWP tBLC

BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2

LAST BYTE

tWC

Figure 6. Page Mode Write Cycle

Figure 5. Byte Write Cycle [CE Controlled]

CAT28LV65

Characteristics subject to change without notice

I/O6

tOEH tOE tOES

tWC

(1) (1)

ADDRESS

I/O7DIN = X DOUT = X DOUT = X

tOE

tOEH

tWC

tOES

DATADATA

DATA Polling

DATA polling is provided to indicate the completion of

write cycle. Once a byte write or page write cycle is

initiated, attempting to read the last byte written will

output the complement of that data on I/O7 (I/O0–I/O6

are indeterminate) until the programming cycle is com-

plete. Upon completion of the self-timed write cycle, all

I/O’s will output true data during a read cycle.

Toggle Bit

In addition to the DATA Polling feature, the device offers

an additional method for determining the completion of

a write cycle. While a write cycle is in progress, reading

data from the device will result in I/O6 toggling between

one and zero. However, once the write is complete, I/O6

stops toggling and valid data can be read from the

device.

Ready/BUSYBUSY

BUSYBUSY

BUSY (RDY/BUSYBUSY

BUSYBUSY

BUSY)

The RDY/BUSY pin is an open drain output which

indicates device status during programming. It is pulled

low during the write cycle and released at the end of

programming. Several devices may be OR-tied to the

same RDY/BUSY line.

Figure 7. DATA Polling

28LV65 F11

Figure 8. Toggle Bit

Note:

(1) Beginning and ending state of I/O6 is indeterminate.

CAT28LV65

Characteristics subject to change without notice

HARDWARE DATA PROTECTION

The following is a list of hardware data protection fea-

tures that are incorporated into the CAT28LV65.

(1) VCC sense provides for write protection when VCC

falls below 2.0V min.

(2) A power on delay mechanism, tINIT (see AC charac-

teristics), provides a 5 to 10 ms delay before a write

sequence, after VCC has reached 2.40V min.

(3) Write inhibit is activated by holding any one of OE

low, CE high or WE high.

(4) Noise pulses of less than 20 ns on the WE or CE

inputs will not result in a write cycle.

SOFTWARE DATA PROTECTION

The CAT28LV65 features a software controlled data

protection scheme which, once enabled, requires a data

algorithm to be issued to the device before a write can be

performed. The device is shipped from Catalyst with the

software protection NOT ENABLED (the CAT28LV65 is

in the standard operating mode).

Figure 9. Write Sequence for Activating Software

Data Protection Figure 10. Write Sequence for Deactivating

Software Data Protection

SOFTWARE DATA

PRO TECTION A CTIV A TED (12)

WRITE DATA: XX

WRITE LAST BYTE

LAST ADDRESS

TO ANY ADDRESS

WRITE DATA: AA

ADDRESS: 1555

WRITE DATA: 55

ADDRESS: 0AAA

WRITE DATA: A0

ADDRESS: 1555

WRITE DATA: AA

ADDRESS: 1555

WRITE DATA: 55

ADDRESS: 0AAA

WRITE DATA: 80

ADDRESS: 1555

WRITE DATA: AA

ADDRESS: 1555

WRITE DATA: 55

ADDRESS: 0AAA

WRITE DATA: 20

ADDRESS: 1555

Note:

(1) Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC

Max., after SDP activation.

(1)

CAT28LV65

Characteristics subject to change without notice

To activate the software data protection, the device must

be sent three write commands to specific addresses with

specific data (Figure 9). This sequence of commands

(along with subsequent writes) must adhere to the page

write timing specifications (Figure 11). Once this is done,

all subsequent byte or page writes to the device must be

preceded by this same set of write commands. The data

protection mechanism is activated until a deactivate

sequence is issued regardless of power on/off transi-

tions. This gives the user added inadvertent write pro-

tection on power-up in addition to the hardware protec-

tion provided.

To allow the user the ability to program the device with

an EEPROM programmer (or for testing purposes) there

is a software command sequence for deactivating the

data protection. The six step algorithm (Figure 10) will

reset the internal protection circuitry, and the device will

return to standard operating mode (Figure 12 provides

reset timing). After the sixth byte of this reset sequence

has been issued, standard byte or page writing can

commence.

Figure 11. Software Data Protection Timing

tWP

1555 55

0AAA A0

1555

DATA

ADDRESS

tBLC

tWC

BYTE OR

PAGE

WRITES

ENABLED

Figure 12. Resetting Software Data Protection Timing

1555 55

0AAA

DATA

ADDRESS tWC

1555 AA

1555 55

0AAA 20

1555 SDP

RESET

DEVICE

UNPROTECTED

CAT28LV65

Characteristics subject to change without notice

ORDERING INFORMATION

Notes:

(1) The device used in the above example is a CAT28LV65NI-25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).

Prefix Device # Suffix

28LV65

Product

Number

CAT

Optional

Company

NIT

Tape & Reel

Package

P: PDIP

J: SOIC (JEDEC)

K: SOIC (EIAJ)

N: PLCC

-25

Temperature Range

Blank = Commercial (0˚C to +70˚C)

I = Industrial (-40˚C to +85˚C)

A = Automotive (-40˚ to +105˚C)*

Speed

15: 150ns

20: 200ns

25: 250ns

* -40˚C to +125˚C is available upon request

L: PDIP (Lead free, Halogen free)

W: SOIC (JEDEC) (Lead free, Halogen free)

X: SOIC (EIAJ) (Lead free, Halogen free)

G: PLCC (Lead free, Halogen free)

H13: TSOP (8mmx13.4mm) (Lead free, Halogen free)

CAT28LV65

Characteristics subject to change without notice

REVISION HISTORY

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