Never stop thinking.
Data Sheet, Rev. 1.21, September 2005
Communication CPE
AMD8513
USB-to-10/100 Mbps Ethernet LAN Controller
Edition 2005-09-13
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2005.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Template: template_A4_3.0.fm / 3 / 2005-01-17
Trademarks
ABM®, ACE®, AOP®, ARCOFI®, ASM®, ASP®, DigiTape®, DuSLIC®, EPIC®, ELIC®, FALC®, GEMINAX®, IDEC®,
INCA®, IOM®, IPAT®-2, ISAC®, ITAC®, IWE®, IWORX®, MUSAC®, MuSLIC®, OCTAT®, OptiPort®, POTSWIRE®,
QUAT®, QuadFALC®, SCOUT®, SICAT®, SICOFI®, SIDEC®, SLICOFI®, SMINT®, SOCRATES®, VINETIC®,
10BaseV®, 10BaseVX® are registered trademarks of Infineon Technologies AG. 10BaseS™, EasyPort™,
VDSLite™ are trademarks of Infineon Technologies AG. Microsoft® is a registered trademark of Microsoft
Corporation, Linux® of Linus Torvalds, Visio® of Visio Corporation, and FrameMaker® of Adobe Systems
Incorporated.
USB-to-10/100 Mbps Ethernet LAN Controller
Revision History: 2005-09-13, Rev. 1.21
Previous Version:
Page/Date Subjects (major changes since last revision)
2001-12 Rev. 0.1: Preliminary
2002-01 Rev. 1.0: Rearrange
2002-06 Rev. 1.1:
1.VAARef I/O is power pin, not input pin in P.7
2.GNDRef I/O is power pin, not input pin in P.7
3.Modify Pin Assignment Diagram P.5
4.Make small correction on P1, P2, P5, P10, P13, P17, P19, P35, P37, P38
2002-06 Rev 1.2:
1.Remove power consumption @ mode 1 in P.2
2.Change power consumption in P.33
3.Add layout guide in Appendix A
2005-09-13 Rev 1.21: when changed to the new Infineon format
Data Sheet 4 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1 Product Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.1 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2 Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 Pin Assignment Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2 Pin Description by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.2.1 Host Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.2 Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2.3 LED Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.4 EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.5 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.6 POWER USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.7 POWER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3 Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1 USB Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.1 SIE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1.2 USB Command & EP Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2 FIFO Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 TX FIFO and RX FIFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4 10/100M Ethernet PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4 USB Device Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1 Endpoint 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2 Endpoint 1 Bulk IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2.1 Endpoint 2 Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.2.2 Endpoint 3 Interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5 USB Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1 USB Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.1 Get Register (Vendor Specific) Single/Burst Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.2 Set Register (Vendor Specific) Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.1.3 Get Status (Device) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.4 Get Status (Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.5 Get Status (EP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.6 Get Status (EP1) Bulk In . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.7 Get Status (EP2) Bulk OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.8 Get Status (EP3) Interrupt IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.9 Get Descriptor (Device) Total 18-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1.10 Get Descriptor (Configuration) Total 39-byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1.11 Get Descriptor (String) Index 0, LanguageID Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.12 Get Descriptor (String) Index 1, Manufacture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.13 Get Descriptor (String) Index 2, Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.14 Get Descriptor (String) Index 3, Serial No. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
5.1.15 Get Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table of Contents
Data Sheet 5 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Table of Contents
5.1.16 Get Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.17 Clear Feature (Device) Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.18 Set Feature (Device) Remote Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1.19 Clear Feature (EP 0, 1, 2, 3) Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
5.1.20 Set Feature (EP 0, 1, 2, 3) Halt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6 Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.1.1 System Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2 PHY Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2.1 PHY Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.2 Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
7.3.1 USB Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8 EEPROM Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2 GPIO Interface DC Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.1 Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.2 USB Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3 EEPROM Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
10 EEPROM Interface & Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
10.1 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
11 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
12 Appendix Layout Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Data Sheet 6 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
List of Figures
Figure 1 Pin Diagram 11
Figure 2 Block Diagram 15
Figure 3 Packet Form when Receive 17
Figure 4 Packet Form when Transmit 18
Figure 5 EEPROM Interface Timing 77
Figure 6 Package 80
Figure 7 Placement 1 84
Figure 8 Placement 2 84
Figure 9 Trace Routing 1 85
Figure 10 Trace Routing 2 85
Figure 11 Trace Routing 3 86
Figure 12 Power and Ground 1 86
Figure 13 Power and Ground 2 86
Figure 14 Power and Ground 3 87
List of Figures
Data Sheet 7 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
List of Tables
Table 1 Abbreviations for Pin Type 11
Table 2 Abbreviations for Buffer Type 12
Table 3 Host Interface 12
Table 4 Physical Interface 13
Table 5 LED Interface 13
Table 6 Mapping between LED action and EEPROM 0B[7:6] setting 13
Table 7 EEPROM Interface 14
Table 8 Miscellaneous 14
Table 9 Power USB 15
Table 10 Power 15
Table 11 USB Received Status 17
Table 12 USB Packet Format 17
Table 13 Interrupt Packet Form 18
Table 14 Interrupt Packet Form 18
Table 15 Setup Stage 18
Table 16 Data Stage 18
Table 17 Setup Stage 19
Table 18 Data Stage 19
Table 19 Setup Stage 19
Table 20 Setup Stage 19
Table 21 1st OUT Transfer 19
Table 22 2nd OUT Transfer 19
Table 23 3rd OUT Transfer 19
Table 24 Setup Stage 19
Table 25 Data Stage 20
Table 26 Setup Stage 20
Table 27 Data Stage 20
Table 28 Setup Stage 20
Table 29 Data Stage 20
Table 30 Setup Stage 20
Table 31 Data Stage 20
Table 32 Setup Stage 21
Table 33 Data Stage 21
Table 34 Setup Stage 21
Table 35 Data Stage 21
Table 36 Setup Stage 21
Table 37 Data Stage: wLength Field Specifies the Total byte Count to Return 1 21
Table 38 Data Stage: wLength Field Specifies the Total byte Count to Return 2 21
Table 39 Data Stage: wLength Field Specifies the Total byte Count to Return 3 21
Table 40 Setup Stage 22
Table 41 Configuration Descriptor 1 22
Table 42 Configuration Descriptor 2 22
Table 43 Interface 0 Descriptor 22
Table 44 EP1 Descriptor 22
Table 45 EP2 Descriptor 22
Table 46 EP3 Descriptor 22
Table 47 Setup Stage 23
Table 48 Data Stage 23
Table 49 Setup Stage 23
List of Tables
ADM8513
Data Sheet
List of Tables
Data Sheet 8 Rev. 1.21, 2005-09-13
Table 50 Data Stage 23
Table 51 Setup Stage 23
Table 52 Data Stage 23
Table 53 Setup Stage 23
Table 54 Data Stage 24
Table 55 Setup Stage 24
Table 56 Data Stage 24
Table 57 Setup Stage 24
Table 58 Data Stage 24
Table 59 Setup Stage 24
Table 60 Setup Stage 24
Table 61 Setup Stage 25
Table 62 Setup Stage 25
Table 63 Registers Address Space 26
Table 64 Registers Overview 26
Table 65 Register Access Types 29
Table 66 Registers Clock DomainsRegisters Clock Domains 30
Table 67 Reserved Registers 33
Table 68 Wakeup Frame 0 Mask Registers 51
Table 69 Wakeup Frame 1 Mask Registers 53
Table 70 Wakeup Frame 2 Mask Registers 56
Table 71 Registers Address SpaceRegisters Address Space 64
Table 72 Registers Overview 64
Table 73 Register Access Types 65
Table 74 Registers Clock DomainsRegisters Clock Domains 66
Table 75 Absolute Maximum Rating 74
Table 76 Operating Condition 74
Table 77 USB Interface DC Specification 74
Table 78 EEPROM Interface DC Specification 75
Table 79 GPIO Interface DC Specification 75
Table 80 GPIO Interface DC Specification 76
Table 81 EEPROM Interface Timing 76
Table 82 EEPROM Interface 77
Table 83 EEPROM Example 78
Table 84 Dimensions for 48 Pin LQFP Package 82
Data Sheet 9 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Product Overview
1Product Overview
1.1 Package Information
1.2 Features
Main features:
•Industrial Standard
– IEEE 802.3/802.3u 10Base-T/100Base-Tx compliant.
– Supports IEEE 802.3x flow control
– Supports Auto-Negotiation for 10BASE-T and 100BASE-TX
– USB specification 1.0 and 1.1 compliant
•USB Interface
– USB specification 1.0 and 1.1 compliant
– Full-Speed USB Device
– Supports 1 USB configuration and 1 interface
– Supports all USB standard commands
– Supports two vendor specific commands
– Supports USB Suspend/Resume detection logic
– Supports 4 endpoints: 1 control endpoint with maximum 8-byte packet, 1 bulk IN endpoint with maximum
64-byte packet, 1 bulk OUT endpoint with maximum 64-byte packet and 1 interrupt IN endpoint with
maximum 8-byte packet
•MAC/PHY
– Integrates the PHY by using address 1
– Supports configurable threshold for PAUSE frame.
– Supports Auto-Negotiation
– Provides transmit wave-shaper, receive filter, and adapter equalizer.
– Provides MLT-3 transceiver with DC restoration for Base-Line wander.
– Supports external transmit/receive transformer with turn ration 1:1.
•EEPROM Interface
– Provides serial interface to access 93C46 EEPROM
– Automatically load device ID, vendor ID from EEPROM after power-on reset
•FIFO
– Synchronous SRAM.
– Internal 2K-byte two port asynchronous SRAM.
•LED Interface
– 2 LED operation modes
– LED0: speed indication for 10Mbps or 100Mbps.
– LED1: link indication.
– LED2: full duplex indication.
•Support Power Save Function @ USB suspend mode
– Mode 0: Resume by remote wakeup or host when OS goes into standby
Product Name Product Type Package Ordering Number
ADM8513 ADM8513-AD-T-1 P-LQFP-48-5 Q67801H 62A101 1)
1) “x” stands as key to Infineon packing variants, such as “Tape&reel, drypacked”.
ADM8513X ADM8513X-AD-T-1 PG-LQFP-48-5 Q67801H 98A101
ADM8513
Data Sheet
Product Overview
Data Sheet 10 Rev. 1.21, 2005-09-13
– Mode 1: Resume by host when OS goes into standby.
•Miscellaneous
– Supports 6 GPIO pins
– Provides 48-pin LQFP package
–3.3 V power supply with 5 V/3.3 V I/O tolerance
•Support Driver
– Win98/ME/2000/XP
– Linux driver, WinCE 3.0&4.0 driver
– Manufacturing test utilities:
– EEPROM Burn-in program
– MFG testing program
Data Sheet 11 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Interface Description
2Interface Description
2.1 Pin Assignment Diagram
Pin Diagram ADM8513.
Figure 1 Pin Diagram
2.2 Pin Description by Function
Table 1 Abbreviations for Pin Type
Abbreviations Description
IStandard input-only pin. Digital levels.
OOutput. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog levels.
AO Output. Analog levels.
AI/O Input or Output. Analog levels.
PWR Power
GND Ground
MCL Must be connected to Low (JEDEC Standard)
MCH Must be connected to High (JEDEC Standard)
VAAT
TXON
TXOP
GNDT
CLK25_I
CLK25_O
VAARef
RIBB
GNDRef
TSTB
TSTA
GNDR
48 47 46 45 44 43 42 41 40 39 38 37
VDD33 1 36 RXIP
EECS 235RXIN
EESK 3 34 VAAR
EEDI 4 33 LED0
EEDO 532LED1
VDD33 6 31 LED2
Vss 7 30 Vss
GPIO1 829VDD33
GPIO0 9 28 GPIO5
POREN# 10 27 GPIO4
NC 11 26 GPIO3
Vss 12 25 Vss
13 14 15 16 17 18 19 20 21 22 23 24
VDD33
RST#
CLK48_O
CLK48_I
Vss
UVss
DP
DM
UVDD33
VDD33
Vss
GPIO2
ADM8513
rev. 1.0a
ADM8513
Data Sheet
Interface Description
Data Sheet 12 Rev. 1.21, 2005-09-13
2.2.1 Host Interface
2.2.2 Physical Interface
NU Not Usable (JEDEC Standard)
NC Not Connected (JEDEC Standard)
Table 2 Abbreviations for Buffer Type
Abbreviations Description
ZHigh impedance
PU1 Pull up, 10 kΩ
PD1 Pull down, 10 kΩ
PD2 Pull down, 20 kΩ
TS Tristate capability: The corresponding pin has 3 operational states: Low, high and high-
impedance.
OD Open Drain. The corresponding pin has 2 operational states, active low and tristate, and
allows multiple devices to share as a wire-OR. An external pull-up is required to sustain the
inactive state until another agent drives it, and must be provided by the central resource.
OC Open Collector
PP Push-Pull. The corresponding pin has 2 operational states: Active-low and active-high
(identical to output with no type attribute).
OD/PP Open-Drain or Push-Pull. The corresponding pin can be configured either as an output with
the OD attribute or as an output with the PP attribute.
ST Schmitt-Trigger characteristics
TTL TTL characteristics
Table 3 Host Interface
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
16 CLK48_I IInput Clock
48 MHz clock input from crystal or oscillator.
15 CLK48_O OOutput for Crystal
14 RST# IExternal Hardware Reset Input
Schmitt-trigger, internal pull high.
20 DM I/O USB Data Minus pin
19 DP I/O USB Data Plus Pin
Table 1 Abbreviations for Pin Type (cont’d)
Abbreviations Description
Data Sheet 13 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Interface Description
2.2.3 LED Interface
Note: The LED interface is EEPROM-programmable, 2 bit EEPROM control bit, Address 0B[7:6] at EEPROM, is
used to select LED mode, the default setting are:
1. LED0: 100Mbps(on, drive '0') or 10Mbps(off, drive '1')
2. LED1: link (keeps on when link ok) or activity (blinks with 10Hz when Pegasus II is receiving or transmitting but
not colliding
3. LED2: full duplex (keeps on when in full duplex mode) or collision (blinks with 20Hz when colliding)
4. All LED pins will be tri-state when using external PHY (offset 81h with bit[4:2] = 001B)
Mapping between LED action and EEPROM 0B[7:6] setting
Table 4 Physical Interface
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
86, 35 RXIP, RXIN IRX Input
46, 47 TXOP, TXON OTX Output
44 CLK25_I ICrystal Input
25MHz
43 CLK25_O OCrystal Output
25MHz
41 RIBB IReference Bias Resistor, tied to external 10K(1%)
resistor to ground
38, 39 TSTA, TSTB OTest Output Pin
Table 5LED Interface
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
33 LED0 OLED display for 100M b/s or 10M b/s speed.
Active low indicates 100Base-TX, active high indicates 10
BaseT.
32 LED1 OLED display for link and activity status.
Active low when link is established.
31 LED2 OLED display for Full Duplex or Collision status.
Active low indicates full duplex, high indicates collision in
half duplex.
Table 6 Mapping between LED action and EEPROM 0B[7:6] setting
EEPROM 0B[7:6] LED Action
0,0
LED0 10 / 100 (OFF/ON)
LED1 LINK / ACTIVITY (ON/FLASH)
LED2 FULL DUP / COL (ON/FLASH)
0,1
LED0 ACTIVITY when LINK (FLASH)
LED1 LINK 10(ON)
LED2 LINK 100(ON)
ADM8513
Data Sheet
Interface Description
Data Sheet 14 Rev. 1.21, 2005-09-13
2.2.4 EEPROM Interface
2.2.5 Miscellaneous
2.2.6 POWER USB
Table 7 EEPROM Interface
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
2EECS OEEPROM Chip Select
This pin enables the EEPROM during loading of the
Ethernet configuration data.
CMOS I/O with 5 V tolerant, 2mA
4EEDI OEEPROM Data In
The MAC will use this pin to serially write opcodes,
addresses and data into the serial EEPROM.
CMOS I/O with 5 V tolerant, 2mA
5EEDO IEEPROM Data Out, internal pull low
The MAC will read the contents of the EEPROM serially
through this pin.
Input, pull down, 5 V tolerant
3EESK OEEPROM Clock
After reset, the MAC if configured, will read the contents of
the EEPROM using EESK, EEDO, and EEDI. This pin
provides the clock for the EEPROM.
CMOS I/O with 5 V tolerant, 2mA
Table 8 Miscellaneous
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
9GPIO5 I/O General Purpose Input/Output Pins
These pins are used as general purpose Input/Output pins
and offset 0A[1] = 0 in EEPROM.
Default is internal pull-low
8GPIO4
24 GPIO3
26 GPIO2
27 GPIO1
28 GPIO0
10 POREN# ITest Pins
11 NC XTest Pins
Data Sheet 15 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Interface Description
2.2.7 POWER
2.3 Block Diagram
Figure 2 Block Diagram
Table 9 Power USB
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
21 UVDD 33 PWR 3.3V power supply for USB transceiver
18 UVSS PWR Ground for USB transceiver
Table 10 Power
Pin or Ball
No.
Name Pin
Type
Buffer
Type
Function
1, 6, 13, 22,
29
VDD 33 PWR 3.3V Power Supply.
7, 12, 23, 17,
25, 30
VSS PWR Ground
42 VAARef PWR +3.3V Power Supply for PHY.
40 GNDRed PWR +3.3V Power Ground for PHY
48 VAAT PWR +3.3V for Transmitter
45 GNDT PWR GND for Transmitter
34 VAAR PWR +3.3V for Receiver
37 GNDR PWR GND for Receiver
SIE
USB
Command
&
EP
Decoder FIFO Controller
2K TX FIFO
RX
SRAM
10/100M
Ethernet
MAC
10/100
M
Ethernet
Ph
RJ45
DP
DM
ADM8513
Data Sheet
Function Description
Data Sheet 16 Rev. 1.21, 2005-09-13
3Function Description
3.1 USB Interface
USB is a likely solution any time you want to use a computer to communication with devices outside the computer.
The interface is suitable for one-of-kind and small-scale designs as well as mass-produced, standard peripheral.
The benefits to USB are easy to use, fast and reliable data transfers, flexibility, low cost and power conservation.
3.1.1 SIE
SIE (Serial Interface Engine) is to control USB communications and check USB protocol, then transfer protocol to
EP decoder. The SIE and USB transceivers, which provide the hardware interface to the USB cable, together
comprise the USB engine.
3.1.2 USB Command & EP Decoder
The detail description is in “USB Command”.
3.2 FIFO Controller
FIFO Controller in receive path is in charge of:
• Stores received Ethernet packets to SRAM and multiple packets can be stored to SRAM. If more than
maximum packet counts are received or total packet size is more than the size of SRAM, the subsequent
coming Ethernet packet will be discarded.
• FIFO controller will load data from SRAM to internal RX FIFO then inform EP Decoder that 64-byte data or a
packet is ready in RX FIFO. Before FIFO controller informs about this, any USB access to bulk IN endpoint will
return NAK. This is to maintain the data transfer on the USB bus via bulk IN transfer which is continuous, thus
a 64-byte internal RX FIFO is needed.
• If an Ethernet packet is being received and loading into SRAM while FIFO Controller is moving data from
SRAM to internal RX FIFO, writing the Ethernet packet to SRAM will get the higher priority.
3.3 TX FIFO and RX FIFO
RX FIFO is a one-port 64-byte FIFO and TX FIFO is a two-port 2K-byte FIFO.
3.4 10/100M Ethernet PHY
The Ethernet PHY is compliant to IEEE 802.3u 100BASE-TX and IEEE802.3 10BASE-T. It provides the whole
physical layer functions for both 10M and 100M Ethernet speed.
4 USB Device Endpoint Operation
4.1 Endpoint 0
Endpoint 0 is in charge of response to standard USB commands and vendor specific commands. Internal register
settings are also via this endpoint. The response to each command is described in section 6.
Data Sheet 17 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
USB Device Endpoint Operation
4.2 Endpoint 1 Bulk IN
Endpoint 1 is in charge of sending the received Ethernet packet to USB host. An Ethernet packet will be split to
multiple 64 bytes USB packets on USB. The end of the Ethernet packet is indicated by less then 64-byte or 0 length
data transfer in this pipe. The Ethernet received status is optionally reported at the end of the packet.
While accessing to this endpoint, if RXFIFO is either full or any packet is inside, the data in RXFIFO is returned in
USB data stage. If ACK is received from USB host, data in RXFIFO is flushed. If no response or NAK is received
from USB host, the content in RXFIFO will be re-transmitted. If RXFIFO isn't ready for transmission, NAK is
returned to USB host.
Figure 3 Packet Form when Receive
The Received Status is Reported as Follows:
4.2.1 Endpoint 2 Bulk OUT
Endpoint 2 is in charge of sending the USB packet to Ethernet. An Ethernet packet is concatenated by multiple 64
bytes USB packets on USB. The first two bytes in every first concatenated USB packet indicate the length of the
Ethernet packet. The end of the Ethernet packet is indicated by less then 64-byte or 0 length data transfer in this
pipe. The Ethernet transmit status is reported in transmit status register.
When accessing to this endpoint, data in USB data stage is transferred to TXFIFO, if TXFIFO is free and ACK is
returned. If TXFIFO isn’t free, NAK is returned.
Table 11 USB Received Status
Offset Bit Field Description
Offset0 7-0 rx_bytecnt_lo The received byte count[7:0].
Offset1 3-0 rx_bytecnt_hi The received byte count[11:8].
7-4 reserved
Offset2 0multicast_frame Indicates received a multicast frame.
1long_pkt Indicates received packet length > 1518 bytes.
2runt_pkt Indicates received packet length < 64 bytes.
3crc_err Indicates CRC check error.
4dribble_bit Indicates packet length is not integer multiple of 8-
bit.
7-5 reserved
Offset3 7-0 reserved
1/10/100 MAC Layer
(64 to 1514 bytes)
64 64
64 64 0 to
63
ˁˁ
ˁ
One Ethernet Packet
to
Multiple USB Packet
Ethernet
Packet
USB Packet
ADM8513
Data Sheet
USB Commands
Data Sheet 18 Rev. 1.21, 2005-09-13
Figure 4 Packet Form when Transmit
4.2.2 Endpoint 3 Interrupt IN
Endpoint 3 is in charge of returning the current Ethernet transfer status every polling interval. When accessing to
this endpoint, 8 bytes data is returned to USB host. The 8-byte packet contains
5USB Commands
5.1 USB Command
5.1.1 Get Register (Vendor Specific) Single/Burst Read
Table 12 USB Packet Format
Field 1st Byte in 1st USB Packet 2nd Byte in 1st USB Packet The Following Packets
Content len[7:0]: Low byte Ethernet
packet length
{reserved[4:0], len[10:8]} Ethernet packet
Table 13 Interrupt Packet Form
Offset0 Offset1 Offset2 Offset3 Offset4
tx_status(Reg2BH)tx_status(Reg2CH)rx_status(Reg2DH)rx_lostpkt(Reg2EH)rx_lostpkt(Reg2FH)
Table 14 Interrupt Packet Form
Offset5 Offset6(1B) Offset7(1B)
wakeup_status(Reg7AH)Packet number in RX FIFO
(Reg82H)
7’b00, length error
Table 15 Setup Stage
bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B)
C0 F0 0RegIndex[7:0] 00 Length Low Length High
1/10/100 MAC Layer
(64 to 1514 bytes)
64 64
64 64 0 to
63
ˁˁ
ˁ
Multiple USB Packet
to
One Ethernet Packet
Ethernet
Packet
USB Packet
Data Sheet 19 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
USB Commands
The returned total number of registers depends on the length field.
5.1.2 Set Register (Vendor Specific) Burst Write
Ex. Write 44 to RegIndex = 05H, the transfer will be
If wLength > 1, more than 1 register is accessed (burst write) and mask is not supported => DataStage for 8-byte
OUT transfer appears
Ex. Burst write 20 registers from RegIndex = 07H and data from 01D to 20D
• Setup Stage
• Data Stage
Table 16 Data Stage
Offset0(1B) Offset1(1B) Offset2(1B)
{RegIndex} {RegIndex+1) {RegIndex+2)
Table 17 Setup Stage
bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B)
40 F1 0RegIndex[7:0] 00 Length Low Length High
Table 18 Data Stage
Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B)
{RegIndex} {RegIndex+1} {RegIndex+2} {RegIndex+3}
Table 19 Setup Stage
bmReq bReq wValue
L(1B)
wValue
H(1B)
wIndexLow
(1B)
wIndexHigh
(1B)
wLength
L(1B)
wLength
H(1B)
40 F1 44 00 05 00 01 00
Table 20 Setup Stage
bmReq bReq wValue(2B) wIndexLow(1B) wIndexHigh(1B) wLength L(1B) wLength H(1B)
40 F1 0000 07 00 14 00
Table 21 1st OUT Transfer
Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B)
01 02 03 04 05 06 07 08
Table 22 2nd OUT Transfer
Offset0(1B) Offset1(1B) Offset2(1B) Offset3(1B) Offset4(1B) Offset5(1B) Offset6(1B) Offset7(1B)
09 0A 0B 0C 0D 0E 0F 10
ADM8513
Data Sheet
USB Commands
Data Sheet 20 Rev. 1.21, 2005-09-13
5.1.3 Get Status (Device)
5.1.4 Get Status (Interface)
5.1.5 Get Status (EP0)
5.1.6 Get Status (EP1) Bulk In
Table 23 3rd OUT Transfer
Offset0(1B) Offset1(1B) Offset2(1B)
11 12 13
Table 24 Setup Stage
bmReq bReq wValue(2B) wIndex(2B) wLength L(1B) wLength H(1B)
80 0 0 0 2 0
Table 25 Data Stage
D[15:2] D[1]: Remote Wakeup D[0]:Self Powered
0Register of remote_wakeup 1
Table 26 Setup Stage
bmReq bReq wValue(2B) wIndex(2B) wLength L(1B) wLength H(1B)
81 0 0 0 2 0
Table 27 Data Stage
D[15:0]
0
Table 28 Setup Stage
bmReq bReq wValue(2B) wIndex L(1B) wIndex H(1B) wLength
L(1B)
wLength
H(1B)
82 0080 or 00 00 2 0
Table 29 Data Stage
D[15:1] D[0]: Halt
0Register of ep0_halt
Data Sheet 21 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
USB Commands
5.1.7 Get Status (EP2) Bulk OUT
5.1.8 Get Status (EP3) Interrupt IN
5.1.9 Get Descriptor (Device) Total 18-byte
Table 30 Setup Stage
bmReq bReq wValue(2B) wIndex L(1B) wIndex H(1B) wLength
L(1B)
wLength
H(1B)
82 0081 00 2 0
Table 31 Data Stage
D[15:1] D[0]: Halt
0Register of ep1_halt
Table 32 Setup Stage
bmReq bReq wValue(2B) wIndex L(1B) wIndex H(1B) wLength
L(1B)
WLength
H(1B)
82 0002 00 2 0
Table 33 Data Stage
D[15:1] D[0]: Halt
0register of ep2_halt
Table 34 Setup Stage
bmReq bReq wValue(2B) wIndex L(1B) wIndex H(1B) wLength
L(1B)
wLength
H(1B)
82 0083 00 2 0
Table 35 Data Stage
D[15:1] D[0]: Halt
0register of ep3_halt
Table 36 Setup Stage
bmReq bReq wValue L(1B) wValue H(1B) wIndex(2B) wLength
L(1B)
wLength
H(1B)
80 601 00 0Length low Length high
ADM8513
Data Sheet
USB Commands
Data Sheet 22 Rev. 1.21, 2005-09-13
5.1.10 Get Descriptor (Configuration) Total 39-byte
• Data Stage
Table 37 Data Stage: wLength Field Specifies the Total byte Count to Return 1
Offset 0 Offset 1
(type)
Offset 2 (USB
release no. L)
Offset 3 (USB
release no. H)
Offset 4
(Class code)
Offset 5 (Sub
Class Code)
Offset 6
(Protocol)
Offset 7 (EP0
MaxPktSize)
12(1B)01(1B)10(1B)01(1B)FF(1B)00(1B)ff(1B)8(1B)
Table 38 Data Stage: wLength Field Specifies the Total byte Count to Return 2
Offset 8 (vendor ID)
Low
Offset 9(vendor ID)
High
Offset 10
(productID) Low
Offset 11
(productID) High
Offset 12 (releaseID
Low)
(1B)(1B)(1B)(1B)01(1B)
Table 39 Data Stage: wLength Field Specifies the Total byte Count to Return 3
Offset 13 (releaseID
High)
Offset 14
(manufacture)
Offset 15 (Product) Offset 16 (serial
no.)
Offset 17 (no. of
config)
01(1B)01(1B)02(1B)03(1B)01(1B)
Table 40 Setup Stage
BmReq bReq wValue L(1B) wValue H(1B) wIndex(2B) wLength
L(1B)
wLength
H(1B)
80 602 00 0Length low Length high
Table 41 Configuration Descriptor 1
Offset 0 (Length) Offset 1 (DscrType) Offset 2
(TotalLength) Low
Offset 3
(TotalLength) High
Offset 4
(NumInterface)
09(1B)02(1B)27(1B)00(1B)01(1B)
Table 42 Configuration Descriptor 2
Offset 5 (ConfgValue) Offset 6 (StringIndex) Offset 7 (Attribute) Offset 8(MaxPower)
00(1B)00(1B)E0(1B)max_pwr(1B)
Table 43 Interface 0 Descriptor
Offset 0
(Length)
Offset 1
(DscrType)
Offset 2
(Interface
Num)
Offset 3
(AltInterfa
ce)
Offset 4
(NumEP)
Offset 5
(IntfClass)
Offset 6
(IntfSubCl
ass)
Offset 7
(IntfProto
col)
Offset 8
(StringInd
ex)
09(1B)04(1B)00(1B)00(1B)03(1B)FF(1B)E0(1B)FF(1B)00(1B)
Data Sheet 23 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
USB Commands
5.1.11 Get Descriptor (String) Index 0, LanguageID Code
5.1.12 Get Descriptor (String) Index 1, Manufacture
Table 44 EP1 Descriptor
Offset 0
(Length)
Offset 1
(DscrType)
Offset 2
(EPAddr)
Offset 3
(Attribute)
Offset 4
(MaxPktSize)
Low
Offset 5
(MaxPktSize)
High
Offset 6
(Interval)
07(1B)05(1B)81(1B)02(1B) bulk 64(1B)00(1B)00(1B)
Table 45 EP2 Descriptor
Offset 0
(Length)
Offset 1
(DscrType)
Offset 2
(EPAddr)
Offset 3
(Attribute)
Offset 4
(MaxPktSize)
Low
Offset 4
(MaxPktSize)
High
Offset 6
(Interval)
07(1B)05(1B)02(1B)02(1B) bulk 64(1B)00(1B)00(1B)
Table 46 EP3 Descriptor
Offset 0
(Length)
Offset 1
(DscrType)
Offset 2
(EPAddr)
Offset 3
(Attribute)
Offset 4
(MaxPktSize)
Low
Offset 5
(MaxPktSize)
High
Offset 6
(Interval)
07(1B)05(1B)83(1B)03(1B) interrupt 08(1B)00(1B)ep3_interval(1B)
Table 47 Setup Stage
BmReq bReq wValue L(1B) wValue H(1B) wIndex(2B) wLength
Low(1B)
wLength
High(1B)
80 06 00 03 0000 Length Low Length High
Table 48 Data Stage
Offset0 (Length) Offset1 (DscrType) Offset2 (LanguageID) L Offset3 (LanguageID) H
04(1B)03(1B)09(1B)04(1B)
Table 49 Setup Stage
BmReq bReq wValue L(1B) wValue H(1B) wIndex (2B) wLength
Low(1B)
wLength
High(1B)
80 06 01 03 0904 Length Low Length High
Table 50 Data Stage
Offset0 (Length) Offset1 (DscrType)
length(1B) 03(1B) String
ADM8513
Data Sheet
USB Commands
Data Sheet 24 Rev. 1.21, 2005-09-13
5.1.13 Get Descriptor (String) Index 2, Product
5.1.14 Get Descriptor (String) Index 3, Serial No.
5.1.15 Get Configuration
5.1.16 Get Interface
Table 51 Setup Stage
BmReq bReq wValue L(1B) wValue H(1B) wIndex (2B) wLength
Low(1B)
wLength
High(1B)
80 06 02 03 0904 Length Low Length High
Table 52 Data Stage
Offset 0 (Length) Offset 1 (DscrType)
length(1B)03(1B)String
Table 53 Setup Stage
BmReq bReq wValue L(1B) wValue H(1B) wIndex (2B) wLength
Low(1B)
wLength
High(1B)
80 06 03 03 0904 Length Low Length High
Table 54 Data Stage
Offset 0 (Length) Offset 1 (DscrType)
Length(1B)03(1B)String
Table 55 Setup Stage
BmReq bReq wValue(2B) wIndex(2B) wLength
Low(1B)
wLength
High(1B)
80 08 0 0 1 0
Table 56 Data Stage
Offset 0 (ConfgValue)(1B)
Table 57 Setup Stage
BmReq bReq wValue(2B) wIndex(2B) wLength
Low(1B)
wLength
High(1B)
81 10 0 0 1 0
Data Sheet 25 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
USB Commands
5.1.17 Clear Feature (Device) Remote Wakeup
5.1.18 Set Feature (Device) Remote Wakeup
5.1.19 Clear Feature (EP 0, 1, 2, 3) Halt
5.1.20 Set Feature (EP 0, 1, 2, 3) Halt
Table 58 Data Stage
Offset0 (AltIntf) (1B)
00
Table 59 Setup Stage
BmReq bReq wValue L(1B) WValue H(1B) wIndex(2B) wLength(2B)
00 01 01 00 0 0
Table 60 Setup Stage
BmReq bReq wValue L(1B) WValue H(1B) wIndex(2B) wLength(2B)
00 03 01 00 0 0
Table 61 Setup Stage
BmReq bReq wValue(2B) WIndex L(1B) wIndex L(2B) WLength(2B)
02 03 0000 EP no 00 0
Table 62 Setup Stage
BmReq bReq wValue(2B) WIndex H(1B) wIndex H(2B) WLength(2B)
02 03 0000 EP no 00 0
ADM8513
Data Sheet
Registers Description
Data Sheet 26 Rev. 1.21, 2005-09-13
6 Registers Description
6.1 System Registers
Table 63 Registers Address Space
Module Base Address End Address Note
System Registers 0000 0000H0000 0081H
Table 64 Registers Overview
Register Short Name Register Long Name Offset Address Page Number
Res30_Res155 Reserved 30~Reserved 155 82~FFH34
EC0 Ethernet Control 0 00H30
EC1 Ethernet Control 1 01H31
EC2 Ethernet Control 2 02H32
Res0 Reserved 0 03H33
Res1 Reserved 1 04H33
Res2 Reserved 2 05H33
Res3 Reserved 3 06H33
Res4 Reserved 4 07H33
MA0 Multicast Address 0 08H34
MA1 Multicast Address 1 09H34
MA2 Multicast Address 2 0AH35
MA3 Multicast Address 3 0BH35
MA4 Multicast Address 4 0CH36
MA5 Multicast Address 5 0DH36
MA6 Multicast Address 6 0EH37
MA7 Multicast Address 7 0FH37
EID0 Ethernet ID 0 10H38
EID1 Ethernet ID 1 11H38
EID2 Ethernet ID 2 12H39
EID3 Ethernet ID 3 13H39
EID4 Ethernet ID 4 14H40
EID5 Ethernet ID 5 15H40
Res5 Reserved 5 16H33
Res6 Reserved 6 17H33
PT Pause Timer 18H41
RPNBFC Receive Packet Number Based Flow Control 1AH41
ORFBFC Occupied Receive FIFO Based Flow Control 1BH42
EP1C EP1 Control 1CH42
Res7 Reserved 7 1CH33
Data Sheet 27 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Res8 Reserved 8 1DH33
Res9 Reserved 9 1EH33
Res10 Reserved 10 1FH33
EEPROMO EEPROM Offset 20H43
EEPROMDL EEPROM Data Low 21H43
EEPROMDH EEPROM Data High 22H43
EEPROMAC EEPROM Access Control 23H45
Res11 Reserved 11 24H33
PHYA PHY Address 25H45
PHYDL PHY Data Low 26H46
PHYDH PHY Data High 27H46
PHYAC PHY Access Control 28H47
Res12 Reserved 12 29H33
USBBS USB Bus Status 2AH47
TS1 Transmit Status 1 2BH47
TS2 Transmit Status 2 2CH49
RS Receive Status 2DH49
RLPCH Receive Lost Packet Count High 2EH50
RLPCL Receive Lost Packet Count Low 2FH50
WUF0M_0 Wakeup Frame 0 Mask 30H50
WUF0M_1 Wakeup Frame 0 Mask 1 31H51
WUF0M_2 Wakeup Frame 0 Mask 2 32H51
WUF0M_3 Wakeup Frame 0 Mask 3 33H51
WUF0M_4 Wakeup Frame 0 Mask 4 34H51
WUF0M_5 Wakeup Frame 0 Mask 5 35H51
WUF0M_6 Wakeup Frame 0 Mask 6 36H51
WUF0M_7 Wakeup Frame 0 Mask 7 37H51
WUF0M_8 Wakeup Frame 0 Mask 8 38H51
WUF0M_9 Wakeup Frame 0 Mask 9 39H51
WUF0M_10 Wakeup Frame 0 Mask 10 3AH51
WUF0M_11 Wakeup Frame 0 Mask 11 3BH51
WUF0M_12 Wakeup Frame 0 Mask 12 3CH51
WUF0M_13 Wakeup Frame 0 Mask 13 3DH51
WUF0M_14 Wakeup Frame 0 Mask 14 3EH51
WUF0M_15 Wakeup Frame 0 Mask 15 3FH51
WUF0O_0 Wakeup Frame 0 Offset 40H51
WUF0CRCL Wakeup Frame 0 CRC Low 41H52
WUF0CRCH Wakeup Frame 0 CRC High 42H52
Res13 Reserved 13 43H33
Res14 Reserved 14 44H33
Res15 Reserved 15 45H33
Table 64 Registers Overview (cont’d)
Register Short Name Register Long Name Offset Address Page Number
ADM8513
Data Sheet
Registers Description
Data Sheet 28 Rev. 1.21, 2005-09-13
Res16 Reserved 16 46H33
Res17 Reserved 17 47H33
WUF1M_0 Wakeup Frame 1 Mask 48H53
WUF1M_1 Wakeup Frame 1 Mask 1 49H53
WUF1M_2 Wakeup Frame 1 Mask 2 4AH53
WUF1M_3 Wakeup Frame 1 Mask 3 4BH53
WUF1M_4 Wakeup Frame 1 Mask 4 4CH53
WUF1M_5 Wakeup Frame 1 Mask 5 4DH53
WUF1M_6 Wakeup Frame 1 Mask 6 4EH53
WUF1M_7 Wakeup Frame 1 Mask 7 4FH53
WUF1M_8 Wakeup Frame 1 Mask 8 50H53
WUF1M_9 Wakeup Frame 1 Mask 9 51H53
WUF1M_10 Wakeup Frame 1 Mask 10 52H53
WUF1M_12 Wakeup Frame 1 Mask 12 54H53
WUF1M_13 Wakeup Frame 1 Mask 13 55H53
WUF1M_11 Wakeup Frame 1 Mask 11 56H53
WUF1M_14 Wakeup Frame 1 Mask 14 56H53
WUF1M_15 Wakeup Frame 1 Mask 15 57H53
WUF1O Wakeup Frame 1 Offset 58H53
WUF1CRCL Wakeup Frame 1 CRC Low 59H55
WUF1CRCH Wakeup Frame 1 CRC High 5AH55
Res18 Reserved 18 5BH33
Res19 Reserved 19 5CH33
Res20 Reserved 20 5DH33
Res21 Reserved 21 5EH33
Res22 Reserved 22 5FH33
WUF2M Wakeup Frame 2 Mask 60H56
WUF2M_1 Wakeup Frame 2 Mask 1 61H56
WUF2M_2 Wakeup Frame 2 Mask 2 62H56
WUF2M_3 Wakeup Frame 2 Mask 3 63H56
WUF2M_4 Wakeup Frame 2 Mask 4 64H56
WUF2M_5 Wakeup Frame 2 Mask 5 65H56
WUF2M_6 Wakeup Frame 2 Mask 6 66H56
WUF2M_7 Wakeup Frame 2 Mask 7 67H56
WUF2M_8 Wakeup Frame 2 Mask 8 68H56
WUF2M_9 Wakeup Frame 2 Mask 9 69H56
WUF2M_10 Wakeup Frame 2 Mask 10 6AH56
WUF2M_11 Wakeup Frame 2 Mask 11 6BH56
WUF2M_12 Wakeup Frame 2 Mask 12 6CH56
WUF2M_13 Wakeup Frame 2 Mask 13 6DH56
WUF2M_14 Wakeup Frame 2 Mask 14 6EH56
Table 64 Registers Overview (cont’d)
Register Short Name Register Long Name Offset Address Page Number
Data Sheet 29 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
The register is addressed wordwise.
WUF2M_15 Wakeup Frame 2 Mask 15 6FH56
WUF2O Wakeup Frame 2 Offset 70H56
WUF2CRCL Wakeup Frame 2 CRC Low 71H58
WUF2CRCH Wakeup Frame 2 CRC High 72H58
Res23 Reserved 23 73H33
Res24 Reserved 24 74H33
Res25 Reserved 25 75H33
Res26 Reserved 26 76H34
Res27 Reserved 27 77H34
WUC Wakeup Control 78H59
Res28 Reserved 28 79H34
WUS Wakeup Status 7AH60
IPHYC Internal PHY Control 7BH60
GPIO54C GPIO[5:4] Control 7CH61
Res29 Reserved 29 7DH34
GPIO10C GPIO[1:0] Control 7EH62
GPIO32C GPIO[3:2] Control 7FH63
Test TEST 80H64
TM Test Mode 81H64
Table 65 Register Access Types
Mode Symbol Description HW Description SW
read/write rw Register is used as input for the HW Register is readable and writable by SW
read rRegister is written by HW (register
between input and output -> one cycle
delay)
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
Read only ro Register is set by HW (register between
input and output -> one cycle delay)
SW can only read this register
Read virtual rv Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
SW can only read this register
Latch high,
self clearing
lhsc Latch high signal at high level, clear on
read
SW can read the register
Latch low,
self clearing
llsc Latch high signal at low-level, clear on
read
SW can read the register
Latch high,
mask clearing
lhmk Latch high signal at high level, register
cleared with written mask
SW can read the register, with write mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk Latch high signal at low-level, register
cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Table 64 Registers Overview (cont’d)
Register Short Name Register Long Name Offset Address Page Number
ADM8513
Data Sheet
Registers Description
Data Sheet 30 Rev. 1.21, 2005-09-13
6.1.1 System Registers
Ethernet Control 0
Interrupt high,
self clearing
ihsc Differentiates the input signal (low-
>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc Differentiates the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk Differentiates the input signal (high-
>low) register cleared with written mask
SW can read the register, with write mask
the register can be cleared
Interrupt low,
mask clearing
ilmk Differentiates the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable
register
ien Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset lor rw register, value is latched after first
clock cycle after reset
Register is readable and writable by SW
Read/write
self clearing
rwsc Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is readable and writable by SW.
Table 66 Registers Clock DomainsRegisters Clock Domains
Clock Short Name Description
EC0 Offset Reset Value
Ethernet Control 0 00H09H
Field Bits Type Description
TXE 7rw Ethernet Transmission Enable
RXE 6rw Ethernet Receive Enable
RXFCE 5rw Receive Pause Frame Enable
WOE 4rw Wake-on-LAN Mode Enable
RXSA 3rw Status Append at the End of Received Packet Enable
Table 65 Register Access Types (cont’d)
Mode Symbol Description HW Description SW
UZ
7;(
UZ
5;(
UZ
5;)&(
UZ
:2(
UZ
5;6$
UZ
6%2
UZ
5;0$
UZ
5;&6
Data Sheet 31 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Ethernet Control 1
SBO 2rw Stop Back Off
0BCNOT, Back-off counter isn’t affected by carrier
1BCST, Back-off counter stops when carrier is active and resumes
when carrier drops
RXMA 1rw Receive All Multicast Packet
RXCS 0rw Include CRC in Receive Packet
EC1 Offset Reset Value
Ethernet Control 1 01H00H
Field Bits Type Description
Res 7:6 ro Reserved
FD 5rw Full Dublex
0BHDM, Half-duplex mode
1BFDM, Full-duplex mode
10M 4rw 10mode
0B10Base, 10Base-T mode
1B100Base, 100Base-T mode
RM 3rw Reset MAC
After write 1, HW will clear this bit after MAC reset.
MII 2 r MII Mode
0BMIIM, MII mode
Res 1:0 ro Reserved
Field Bits Type Description
UR
5HV
UZ
)'
UZ
0
UZ
50
U
0,,
UR
5HV
ADM8513
Data Sheet
Registers Description
Data Sheet 32 Rev. 1.21, 2005-09-13
Ethernet Control 2
EC2 Offset Reset Value
Ethernet Control 2 02H00H
Field Bits Type Description
MEPL 7rw Max Ethernet Packet Length
0B1528B, 1528 bytes
1B1638B, 1638 bytes, Default is 0
Res 6ro Reserved
LEEPRS 5rw Load EEPROM Start
When this bit is written with 1, HW will start to load EEPROM.
EEPRW 4rw EEPROM Write Enable/disable
0BWEDC, EEPROM writes enable/disable command
1BWC, EEPROM writes command
LB 3rw MAC Loop Back Mode Enable
PROM 2rw Promiscuous
0BRPP, Receives packets which pass the address filter
1BRAP, Receives any packet
RXBP 1rw Receive Bad Packets
0BFABP, Filters all bad packet
1BRBPP, Receives bad packets which pass the address filter
EP3RC 0rw EP3 Read Cleared
0BAEP3, Access EP3, no effect to those registers.
1BOEP3, Once EP3 is accessed, those registers (2B-2F, 7A) will be
cleared.
UZ
0(3/
UR
5HV
UZ
/((356
UZ
((35:
UZ
/%
UZ
3520
UZ
5;%3
UZ
(35&
Data Sheet 33 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Reserved 0
Similar Registers
Res0 Offset Reset Value
Reserved 0 03H00H
Field Bits Type Description
Res 7:0 ro Reserved
Table 67 Reserved Registers
Register Short Name Register Long Name Offset Address Page Number
Res1 Reserved 1 04H
Res2 Reserved 2 05H
Res3 Reserved 3 06H
Res4 Reserved 4 07H
Res5 Reserved 5 16H
Res6 Reserved 6 17H
Res7 Reserved 7 1CH
Res8 Reserved 8 1DH
Res9 Reserved 9 1EH
Res10 Reserved 10 1FH
Res11 Reserved 11 24H
Res12 Reserved 12 29H
Res13 Reserved 13 43H
Res14 Reserved 14 44H
Res15 Reserved 15 45H
Res16 Reserved 16 46H
Res17 Reserved 17 47H
Res18 Reserved 18 5BH
Res19 Reserved 19 5CH
Res20 Reserved 20 5DH
Res21 Reserved 21 5EH
Res22 Reserved 22 5FH
Res23 Reserved 23 73H
Res24 Reserved 24 74H
Res25 Reserved 25 75H
UR
5HV
ADM8513
Data Sheet
Registers Description
Data Sheet 34 Rev. 1.21, 2005-09-13
Multicast Address 0
Multicast Address 1
Res26 Reserved 26 76H
Res27 Reserved 27 77H
Res28 Reserved 28 79H
Res29 Reserved 29 7DH
Res30_Res155 Reserved 30~Reserved 155 82~FFH
MA0 Offset Reset Value
Multicast Address 0 08H00H
Field Bits Type Description
MAB0 7:0 rw Multicast 0
Multicast address byte [7:0]
MA1 Offset Reset Value
Multicast Address 1 09H00H
Field Bits Type Description
MAB1 7:0 rw Multicast 1
Multicast address byte [15:8]
Table 67 Reserved Registers (cont’d)
Register Short Name Register Long Name Offset Address Page Number
UZ
0$%
UZ
0$%
Data Sheet 35 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Multicast Address 2
Multicast Address 3
MA2 Offset Reset Value
Multicast Address 2 0AH00H
Field Bits Type Description
MAB2 7:0 rw Multicast 2
Multicast address byte [23:16]
MA3 Offset Reset Value
Multicast Address 3 0BH00H
Field Bits Type Description
MAB3 7:0 rw Multicast 3
Multicast address byte [31:24]
UZ
0$%
UZ
0$%
ADM8513
Data Sheet
Registers Description
Data Sheet 36 Rev. 1.21, 2005-09-13
Multicast Address 4
Multicast Address 5
MA4 Offset Reset Value
Multicast Address 4 0CH00H
Field Bits Type Description
MAB4 7:0 rw Multicast 4
Multicast address byte [39:32]
MA5 Offset Reset Value
Multicast Address 5 0DH00H
Field Bits Type Description
MAB5 7:0 rw Multicast 5
Multicast address byte [47:40]
UZ
0$%
UZ
0$%
Data Sheet 37 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Multicast Address 6
Multicast Address 7
MA6 Offset Reset Value
Multicast Address 6 0EH00H
Field Bits Type Description
MAB6 7:0 rw Multicast 6
Multicast address byte [55:48]
MA7 Offset Reset Value
Multicast Address 7 0FH00H
Field Bits Type Description
MAB7 7:0 rw Multicast 7
Multicast address byte [63:56]
UZ
0$%
UZ
0$%
ADM8513
Data Sheet
Registers Description
Data Sheet 38 Rev. 1.21, 2005-09-13
Ethernet ID 0
Ethernet ID 1
EID0 Offset Reset Value
Ethernet ID 0 10H00H
Field Bits Type Description
EID0 7:0 rw Ethernet ID 0
The 1st byte of Ethernet ID is automatically loaded from EEPROM after
HW reset.
EID1 Offset Reset Value
Ethernet ID 1 11H00H
Field Bits Type Description
EID1 7:0 rw Ethernet ID 1
The 2nd byte of Ethernet ID.
UZ
(,'
UZ
(,'
Data Sheet 39 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Ethernet ID 2
Ethernet ID 3
EID2 Offset Reset Value
Ethernet ID 2 12H00H
Field Bits Type Description
EID2 7:0 rw Ethernet ID 2
The 3rd byte of Ethernet ID.
EID3 Offset Reset Value
Ethernet ID 3 13H00H
Field Bits Type Description
EID3 7:0 rw Ethernet ID 3
The 4th byte of Ethernet ID.
UZ
(,'
UZ
(,'
ADM8513
Data Sheet
Registers Description
Data Sheet 40 Rev. 1.21, 2005-09-13
Ethernet ID 4
Ethernet ID 5
EID4 Offset Reset Value
Ethernet ID 4 14H00H
Field Bits Type Description
EID4 7:0 rw Ethernet ID 4
The 5th byte of Ethernet ID.
EID5 Offset Reset Value
Ethernet ID 5 15H00H
Field Bits Type Description
EID5 7:0 rw Ethernet ID 5
The 6th byte of Ethernet ID.
UZ
(,'
UZ
(,'
Data Sheet 41 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Pause Timer
Receive Packet Number Based Flow Control
PT Offset Reset Value
Pause Timer 18H00H
Field Bits Type Description
PT 7:0 rw Pause Timer
The [11:4] of pause time in the PAUSE frame.
RPNBFC Offset Reset Value
Receive Packet Number Based Flow Control 1AH00H
Field Bits Type Description
PN 6:1 rw Packet Number
This field specifies the threshold for transmitting the PAUSE frame. As
the received packet number is more than or equal to this field, the PAUSE
frame is sent automatically by HW.
FCP 0rw Flow Control Packet
1BRPN, Enables pause frame transmission based on received packet
number
UZ
37
5HV
UZ
31
UZ
)&3
ADM8513
Data Sheet
Registers Description
Data Sheet 42 Rev. 1.21, 2005-09-13
Occupied Receive FIFO Based Flow Control
EP1 Control
ORFBFC Offset Reset Value
Occupied Receive FIFO Based Flow Control 1BH00H
Field Bits Type Description
RXS 6:1 rw RX Size
This field specifies the Kbyte threshold for transmitting the PAUSE frame.
As the received FIFO is occupied than or equal to this field, the PAUSE
frame is sent automatically by HW.
If this field = 2, as receive FIFO is occupied more than or equal to 2 Kbyte,
the PAUSE frame is transmitted.
FCRXS 0rw Flow Control RX Size
1BRFS, Enables pause frame transmission based on occupied
received FIFO size
EP1C Offset Reset Value
EP1 Control 1CH04H
Field Bits Type Description
EP1S0E 7rw EP1 Send
0BDEP1, Disables EP1 send 1-byte 00 function
1BEEP1, Enables EP1 send 1-byte 00 when more than frame_
interval’s NAK is received
FID 6:5 rw Frame Interval Detail
This value is the detailed scale of frame interval, it is from 0ms to 3ms.
00B, for more than 0 plus frame_interval ms NAK, EP1 sends 1-byte 00
01B, for more than 1 plus frame_interval ms NAK, EP1 sends 1-byte 00
11B, for more than 3 plus frame_interval ms NAK, EP1 sends 1-byte 00
5HV
UZ
5;6
UZ
)&5;6
UZ
(36(
UZ
),'
UZ
),
Data Sheet 43 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
EEPROM Offset
EEPROM Data Low
EEPROM Data High
FI 4:0 rw Frame Interval
This value multiply with 4 is the frame interval, it is from 4ms to 124ms
00001B, for more than 4 ms NAK, EP1 sends 1-byte 00
00010B, for more than 8 ms NAK, EP1 sends 1-byte 00
11111B, for more than 124 ms NAK, EP1 sends 1-byte 00
EEPROMO Offset Reset Value
EEPROM Offset 20H00H
Field Bits Type Description
ROMO 5:0 rw ROM Offset
SW sets this register when access to EEPROM.
EEPROMDL Offset Reset Value
EEPROM Data Low 21H00H
Field Bits Type Description
ROMDL 7:0 rw ROM Data Low
EEPROM Write: The data set in this register will be written to EEPROM
EEPROM Read: The data red from EEPROM will be stored in this register
EEPROMDH Offset Reset Value
EEPROM Data High 22H00H
Field Bits Type Description
5HV
UZ
5202
UZ
520'/
ADM8513
Data Sheet
Registers Description
Data Sheet 44 Rev. 1.21, 2005-09-13
Field Bits Type Description
ROMDH 7:0 rw ROM Data High
EEPROM Write: The data set in this register will be written to EEPROM
EEPROM Read: The data read from EEPROM will be stored in this
register
UZ
520'+
Data Sheet 45 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
EEPROM Access Control
PHY Address
EEPROMAC Offset Reset Value
EEPROM Access Control 23H00H
Field Bits Type Description
DO 2rw Done
Set by HW to indicate successful completion of EEPROM access.
Clear by SW when initiate a new access to EEPROM
RDE 1rw Read Access to EEPROM
Set by SW to initiate a read access to EEPROM.
SW sets this bit after it well setting the rom_offset.
WRE 0rw Write Access to EEPROM
Set by SW to initiate a write access to EEPROM.
SW set this bit after it well setting the rom_offset, romdata_lo and
romdata_hi.
PHYA Offset Reset Value
PHY Address 25H00H
Field Bits Type Description
PHYA 4:0 rw MII PHY Address
5HV
UZ
'2
UZ
5'(
UZ
:5(
5HV
UZ
3+<$
ADM8513
Data Sheet
Registers Description
Data Sheet 46 Rev. 1.21, 2005-09-13
PHY Data Low
PHY Data High
PHYDL Offset Reset Value
PHY Data Low 26H00H
Field Bits Type Description
PHYDL 7:0 rw PHY Data Low
SW set this register when write to PHY register.
HW set this register when read data from PHY register.
PHYDH Offset Reset Value
PHY Data High 27H00H
Field Bits Type Description
PHYDH 7:0 rw PHY Data High
SW set this register when write to PHY register.
HW set this register when read data from PHY register.
UZ
3+<'/
UZ
3+<'+
Data Sheet 47 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
PHY Access Control
USB Bus Status
Transmit Status 1
PHYAC Offset Reset Value
PHY Access Control 28H00H
Field Bits Type Description
DO 7rw Done
Set by HW to indicate successful completion of PHY access.
Clear by SW when initiate a new access to PHY.
RDPHY 6rw Read Access to PHY Register
Set by SW to initiate a read access to PHY register.
SW set this bit after it well setting the phy_addr and phyreg_addr.
WRPHY 5rw Write Access to PHY Register
Set by SW to initiate a write access to PHY register. SW set this bit after
it well setting the phy_addr, phyreg_addr and phyreg_data.
PHYRA 4:0 rw PHY Register Address
USBBS Offset Reset Value
USB Bus Status 2AH00H
Field Bits Type Description
USBR 1rw USB Bus in Resume State
Set by HW to indicate usb bus in resumed state.
Clear by SW read this register.
USBS 0rw USB Bus in Suspend State
Set by HW to indicate usb bus in suspended state.
Clear by SW read this register.
UZ
'2
UZ
5'3+<
UZ
:53+<
UZ
3+<5$
5HV
UZ
86%5
UZ
86%6
ADM8513
Data Sheet
Registers Description
Data Sheet 48 Rev. 1.21, 2005-09-13
TS1 Offset Reset Value
Transmit Status 1 2BH00H
Field Bits Type Description
TXUE 7 r TX Underrun Error
Set by HW to indicate tx underrun error.
Clear by SW read this register or after EP3 is accessed.
EC 6 r Excessive Collision
Set by HW to indicate excessive collision.
Clear by SW read this register or after EP3 is accessed.
LC 5 r Late Collision Error
Set by HW to indicate late collision error.
Clear this register by SW Read or after EP3 is accessed.
NC 4 r No Carrier
Set by HW to indicate no carrier.
Clear this register by SW Read or after EP3 is accessed.
CL 3 r Carrier Loss
Set by HW to indicate carrier loss.
Clear this register by SW Read or after EP3 is accessed.
JTO 2 r Jabber Time Out
Set by HW to indicate jabber time out.
Clear this register by SW Read or after EP3 is accessed.
U
7;8(
U
(&
U
/&
U
1&
U
&/
U
-72 5HV
Data Sheet 49 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Transmit Status 2
Receive Status
TS2 Offset Reset Value
Transmit Status 2 2CH00H
Field Bits Type Description
TXFF 7 r TX Fifo Full
Set by HW to indicate tx fifo full.
Clear this register by SW Read or after EP3 is accessed.
TXFE 6 r TX Fifo Empty
Set by HW to indicate tx fifo empty.
Clear this register by SW Read or after EP3 is accessed.
TXPC 3:0 rTX Packet Count
Set by HW to indicate Ethernet transmit packet counts every interrupt EP
polling. If more than 15 packets have been transmitted, this value will stay
as 15.
Clear by SW read or after EP3 is accessed.
RS Offset Reset Value
Receive Status 2DH00H
Field Bits Type Description
RXP 1 r RX Pause
Set by HW to indicate a PAUSE frame is received.
Clear this register by SW Read or after EP3 is accessed.
RXO 0 r RX Overflow
Set by HW to indicate external SRAM overflow.
Clear this register by SW Read or after EP3 is accessed.
U
7;))
U
7;)( 5HV
U
7;3&
5HV
U
5;3
U
5;2
ADM8513
Data Sheet
Registers Description
Data Sheet 50 Rev. 1.21, 2005-09-13
Receive Lost Packet Count High
Receive Lost Packet Count Low
Wakeup Frame 0 Mask
RLPCH Offset Reset Value
Receive Lost Packet Count High 2EH00H
Field Bits Type Description
RPL 7 r Received Packet Lost
RXLPC 6:0 rRX Lost Packet Counts
The [14:8] of lost packet counts due to receive FIFO overflow.
Clear this register by SW Read or after EP3 is accessed.
RLPCL Offset Reset Value
Receive Lost Packet Count Low 2FH00H
Field Bits Type Description
RXLPC 7:0 rRX Lost Packet Counts
The [7:0] of lost packet counts due to receive FIFO overflow.
Clear this register by SW Read or after EP3 is accessed.
WUF0M_0 Offset Reset Value
Wakeup Frame 0 Mask 30H00H
U
53/
U
5;/3&
U
5;/3&
UZ
)0
Data Sheet 51 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Similar Registers
Wakeup Frame 0 Offset
Field Bits Type Description
F0M 7:0 rw The 128 Mask Bits for Frame 0
Table 68 Wakeup Frame 0 Mask Registers
Register Short Name Register Long Name Offset Address Page Number
WUF0M_1 Wakeup Frame 0 Mask 1 31H
WUF0M_2 Wakeup Frame 0 Mask 2 32H
WUF0M_3 Wakeup Frame 0 Mask 3 33H
WUF0M_4 Wakeup Frame 0 Mask 4 34H
WUF0M_5 Wakeup Frame 0 Mask 5 35H
WUF0M_6 Wakeup Frame 0 Mask 6 36H
WUF0M_7 Wakeup Frame 0 Mask 7 37H
WUF0M_8 Wakeup Frame 0 Mask 8 38H
WUF0M_9 Wakeup Frame 0 Mask 9 39H
WUF0M_10 Wakeup Frame 0 Mask 10 3AH
WUF0M_11 Wakeup Frame 0 Mask 11 3BH
WUF0M_12 Wakeup Frame 0 Mask 12 3CH
WUF0M_13 Wakeup Frame 0 Mask 13 3DH
WUF0M_14 Wakeup Frame 0 Mask 14 3EH
WUF0M_15 Wakeup Frame 0 Mask 15 3FH
WUF0O_0 Offset Reset Value
Wakeup Frame 0 Offset 40H00H
Field Bits Type Description
F0O 7:0 rw Offset for Wakeup Frame 0
UZ
)2
ADM8513
Data Sheet
Registers Description
Data Sheet 52 Rev. 1.21, 2005-09-13
Wakeup Frame 0 CRC Low
Wakeup Frame 0 CRC High
WUF0CRCL Offset Reset Value
Wakeup Frame 0 CRC Low 41H00H
Field Bits Type Description
F0CRCL 7:0 rw The Low Byte of CRC16 Match for Frame 0
WUF0CRCH Offset Reset Value
Wakeup Frame 0 CRC High 42H00H
Field Bits Type Description
F0CRCH 7:0 rw The High Byte of CRC16 Match for Frame 0
UZ
)&5&/
UZ
)&5&+
Data Sheet 53 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Wakeup Frame 1 Mask
Similar Registers
Wakeup Frame 1 Offset
WUF1M_0 Offset Reset Value
Wakeup Frame 1 Mask 48H00H
Field Bits Type Description
F1M 7:0 rw The 128 Mask Bits for Frame 1
Table 69 Wakeup Frame 1 Mask Registers
Register Short Name Register Long Name Offset Address Page Number
WUF1M_1 Wakeup Frame 1 Mask 1 49H
WUF1M_2 Wakeup Frame 1 Mask 2 4AH
WUF1M_3 Wakeup Frame 1 Mask 3 4BH
WUF1M_4 Wakeup Frame 1 Mask 4 4CH
WUF1M_5 Wakeup Frame 1 Mask 5 4DH
WUF1M_6 Wakeup Frame 1 Mask 6 4EH
WUF1M_7 Wakeup Frame 1 Mask 7 4FH
WUF1M_8 Wakeup Frame 1 Mask 8 50H
WUF1M_9 Wakeup Frame 1 Mask 9 51H
WUF1M_10 Wakeup Frame 1 Mask 10 52H
WUF1M_11 Wakeup Frame 1 Mask 11 56H
WUF1M_12 Wakeup Frame 1 Mask 12 54H
WUF1M_13 Wakeup Frame 1 Mask 13 55H
WUF1M_14 Wakeup Frame 1 Mask 14 56H
WUF1M_15 Wakeup Frame 1 Mask 15 57H
WUF1O Offset Reset Value
Wakeup Frame 1 Offset 58H00H
UZ
)0
ADM8513
Data Sheet
Registers Description
Data Sheet 54 Rev. 1.21, 2005-09-13
Field Bits Type Description
F1O 7:0 rw Offset for Wakeup Frame 1
UZ
)2
Data Sheet 55 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Wakeup Frame 1 CRC Low
Wakeup Frame 1 CRC High
WUF1CRCL Offset Reset Value
Wakeup Frame 1 CRC Low 59H00H
Field Bits Type Description
7:0 rw The Low Byte of CRC16 Match for Frame 1
WUF1CRCH Offset Reset Value
Wakeup Frame 1 CRC High 5AH00H
Field Bits Type Description
F1CRCH 7:0 rw The High Byte of CRC16 Match for Frame 1
UZ
UZ
)&5&+
ADM8513
Data Sheet
Registers Description
Data Sheet 56 Rev. 1.21, 2005-09-13
Wakeup Frame 2 Mask
Similar Registers
Wakeup Frame 2 Offset
WUF2M Offset Reset Value
Wakeup Frame 2 Mask 60H00H
Field Bits Type Description
F2M 7:0 rw The 128 Mask Bits for Frame 2
Table 70 Wakeup Frame 2 Mask Registers
Register Short Name Register Long Name Offset Address Page Number
WUF2M_1 Wakeup Frame 2 Mask 1 61H
WUF2M_2 Wakeup Frame 2 Mask 2 62H
WUF2M_3 Wakeup Frame 2 Mask 3 63H
WUF2M_4 Wakeup Frame 2 Mask 4 64H
WUF2M_5 Wakeup Frame 2 Mask 5 65H
WUF2M_6 Wakeup Frame 2 Mask 6 66H
WUF2M_7 Wakeup Frame 2 Mask 7 67H
WUF2M_8 Wakeup Frame 2 Mask 8 68H
WUF2M_9 Wakeup Frame 2 Mask 9 69H
WUF2M_10 Wakeup Frame 2 Mask 10 6AH
WUF2M_11 Wakeup Frame 2 Mask 11 6BH
WUF2M_12 Wakeup Frame 2 Mask 12 6CH
WUF2M_13 Wakeup Frame 2 Mask 13 6DH
WUF2M_14 Wakeup Frame 2 Mask 14 6EH
WUF2M_15 Wakeup Frame 2 Mask 15 6FH
WUF2O Offset Reset Value
Wakeup Frame 2 Offset 70H00H
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Data Sheet 57 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Field Bits Type Description
F2O 7:0 rw Offset for Wakeup Frame 2
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)2
ADM8513
Data Sheet
Registers Description
Data Sheet 58 Rev. 1.21, 2005-09-13
Wakeup Frame 2 CRC Low
Wakeup Frame 2 CRC High
WUF2CRCL Offset Reset Value
Wakeup Frame 2 CRC Low 71H00H
Field Bits Type Description
F2CRCL 7:0 rw The Low Byte of CRC16 Match for Frame 2
WUF2CRCH Offset Reset Value
Wakeup Frame 2 CRC High 72H00H
Field Bits Type Description
F2CRCH 7:0 rw The High Byte of CRC16 Match for Frame 2
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Data Sheet 59 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Wakeup Control
WUC Offset Reset Value
Wakeup Control 78H04H
Field Bits Type Description
EMP 7rw Enable Magic Packet
Set by SW to enable magic packet wakeup function.
1BEMP, Enables magic packet wakeup function
ELS 6rw Enable Link Status
Set by SW to enable link status wakeup function.
1BELS, Enables link status wakeup function
EWF0 5rw Enable Wakeup Frame 0
Set by SW to enable wakeup frame0 wakeup function
1BEWF0, Enables wakeup frame0 wakeup function
WUF1 4rw Enable Wakeup Frame 1
Set by SW to enable wakeup frame1 wakeup function
1B EWF1, Enables wakeup frame1 wakeup function
WUF2 3rw Enable Wakeup Frame 2
Set by SW to enable wakeup frame2 wakeup function
1BEWF2, Enables wakeup frame2 wakeup function
CRC16 2rw CRC-16 Initial Type
0BCRC16, CRC-16 initial contents = 0000H
1BCRC16, CRC-16 initial contents = ffffH
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:8)
UZ
&5& 5HV
ADM8513
Data Sheet
Registers Description
Data Sheet 60 Rev. 1.21, 2005-09-13
Wakeup Status
Internal PHY Control
WUS Offset Reset Value
Wakeup Status 7AH00H
Field Bits Type Description
RXMP 7 r Receives a Magic Packet
Set by HW when receive a magic packet.
Clear by SW read this register.
1BRMP, Means ADM8513 receives a magic packet
LW 6 r Receives a Link Status Change
Set by HW when link status change.Clear by SW read this register.
1BRLS, Means ADM8513 receives a link status change
RXWF 5 r Receives a Wakeup Frame
Set by HW when receive a wakeup frame.Clear by SW read this register.
1BRWF, Means ADM8513 receives a wakeup frame
LS 0 r Indicate the Current Link Status
link_sts
0BLOFF, Link off
1BLON, Link on
IPHYC Offset Reset Value
Internal PHY Control 7BH00H
Field Bits Type Description
EPHY 1rw Enable PHY
0BDIN, Disables internal 10/100 PHY
1BEIN, Enables internal 10/100 PHY
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5;03
U
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5;:) 5HV
U
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5HV
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3+<5
Data Sheet 61 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
GPIO[5:4] Control
PHYR 0rw Internal PHY Reset
The internal PHY is reset when this bit is written with 1 and stops reset
when this bit is written with 0.
1BRIPHY, Reset internal PHY
GPIO54C Offset Reset Value
GPIO[5:4] Control 7CH00H
Field Bits Type Description
G5OE 5rw GPIO5 Output Enable
0BIN, GPIO5 is used for input
1BOUT, GPIO5 is used for output
G5OV 4rw GPIO5 Output Value
When GPIO5 is used for output, this value is driven to GPIO5 pin.
G5IV 3 r GPIO5 Input Value
When GPIO5 is used for input, this field reflects the status of GPIO5.
Default is pulled-down.
G4OE 2rw GPIO4 Output Enable
0BIN, GPIO4 is used for input
1BOUT, GPIO4 is used for output
G4OV 1rw GPIO4 Output Value
When GPIO4 is used for output, this value is driven to GPIO4 pin.
G4IV 0 r GPIO4 Input Value
When GPIO4 is used for input, this field reflects the status of GPIO4.
Default is pulled-down.
Field Bits Type Description
5HV
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*,9
ADM8513
Data Sheet
Registers Description
Data Sheet 62 Rev. 1.21, 2005-09-13
GPIO[1:0] Control
GPIO10C Offset Reset Value
GPIO[1:0] Control 7EH00H
Field Bits Type Description
G1OE 5rw GPIO1 Output Enable
0B IN, GPIO1 is used for input
1B OUT, GPIO1 is used for output
G1OV 4rw GPIO1 Output Value
When GPIO1 is used for output, this value is driven to GPIO1 pin. Set by
SW.
G1IV 3 r GPIO1 Input Value
When GPIO1 is used for input, this field reflects the status of GPIO1. Set
by HW.
G1OE 2rw GPIO0 Output Enable
0B IN, GPIO0 is used for input
1B OUT, GPIO0 is used for output
G0OV 1rw GPIO0 Output Value
When GPIO0 is used for output, this value is driven to GPIO0 pin. Set by
SW.
G0IV 0 r GPIO0 Input Value
When GPIO0 is used for input, this field reflects the status of GPIO0. Set
by HW.
5HV
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*,9
Data Sheet 63 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
GPIO[3:2] Control
GPIO32C Offset Reset Value
GPIO[3:2] Control 7FH00H
Field Bits Type Description
G3OE 5rw GPIO3 Output Enable
0BIN, GPIO3 is used for input
1BOUT, GPIO3 is used for output
G3OV 4rw GPIO3 Output Value
When GPIO3 is used for output, this value is driven to GPIO3 pin. Set by
SW.
G3IV 3 r GPIO3 Input Value
When GPIO3 is used for input, this field reflects the status of GPIO3. Set
by HW.
G2OE 2rw GPIO2 Output Enable
0BIN, GPIO2 is used for input
1BOUT, GPIO2 is used for output
G2OV 1rw GPIO2 Output Value
When GPIO2 is used for output, this value is driven to GPIO2 pin. Set by
SW.
G2IV 0 r GPIO2 Input Value
When GPIO2 is used for input, this field reflects the status of GPIO2. Set
by HW.
5HV
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*,9
ADM8513
Data Sheet
Registers Description
Data Sheet 64 Rev. 1.21, 2005-09-13
TEST
Test Mode
6.2 PHY Registers Description
Test Offset Reset Value
TEST 80H00H
Field Bits Type Description
Res 7:0 ro Reserved
TM Offset Reset Value
Test Mode 81H00H
Field Bits Type Description
Res 7:0 ro Reserved
Table 71 Registers Address SpaceRegisters Address Space
Module Base Address End Address Note
System Registers 0000 0000H0000 0006H
Table 72 Registers Overview
Register Short Name Register Long Name Offset Address Page Number
CTL Control 0H67
STA Status 1H68
PHYI1 PHY Identifier 1 2H70
PHYI2 PHY Identifier 2 3H70
ANA Auto-Negotiation Advertisement 4H71
UR
5HV
UR
5HV
Data Sheet 65 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
The register is addressed wordwise.
ANLPA Auto-Negotiation Link Partner Ability 5H72
ANE Auto-Negotiation Expansion 6H72
Table 73 Register Access Types
Mode Symbol Description HW Description SW
read/write rw Register is used as input for the HW Register is readable and writable by SW
read rRegister is written by HW (register
between input and output -> one cycle
delay)
Value written by software is ignored by
hardware; that is, software may write any
value to this field without affecting hardware
behavior (= Target for development.)
Read only ro Register is set by HW (register between
input and output -> one cycle delay)
SW can only read this register
Read virtual rv Physically, there is no new register, the
input of the signal is connected directly
to the address multiplexer.
SW can only read this register
Latch high,
self clearing
lhsc Latch high signal at high level, clear on
read
SW can read the register
Latch low,
self clearing
llsc Latch high signal at low-level, clear on
read
SW can read the register
Latch high,
mask clearing
lhmk Latch high signal at high level, register
cleared with written mask
SW can read the register, with write mask
the register can be cleared (1 clears)
Latch low,
mask clearing
llmk Latch high signal at low-level, register
cleared on read
SW can read the register, with write mask
the register can be cleared (1 clears)
Interrupt high,
self clearing
ihsc Differentiate the input signal (low-
>high) register cleared on read
SW can read the register
Interrupt low,
self clearing
ilsc Differentiate the input signal (high-
>low) register cleared on read
SW can read the register
Interrupt high,
mask clearing
ihmk Differentiate the input signal (high-
>low) register cleared with written mask
SW can read the register, with write mask
the register can be cleared
Interrupt low,
mask clearing
ilmk Differentiate the input signal (low-
>high) register cleared with written
mask
SW can read the register, with write mask
the register can be cleared
Interrupt enable
register
ien Enables the interrupt source for
interrupt generation
SW can read and write this register
latch_on_reset lor rw register, value is latched after first
clock cycle after reset
Register is readable and writable by SW
Read/write
self clearing
rwsc Register is used as input for the hw, the
register will be cleared due to a HW
mechanism.
Writing to the register generates a strobe
signal for the HW (1 pdi clock cycle)
Register is readable and writable by SW.
Table 72 Registers Overview (cont’d)
Register Short Name Register Long Name Offset Address Page Number
ADM8513
Data Sheet
Registers Description
Data Sheet 66 Rev. 1.21, 2005-09-13
6.2.1 PHY Registers
Table 74 Registers Clock DomainsRegisters Clock Domains
Clock Short Name Description
Data Sheet 67 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Control
SC
Self Clearing
Reset
Reset this port only. This will cause the following:
1. Restart the auto-negotiation process.
CTL Offset Reset Value
Control 0H1000H
Field Bits Type Description
RST 15 rwsc Reset
0BNO, Normal operation
1BPR, PHY Reset
LP 14 rw Loopback
0BDL, Disable loopback
1BEL, Enable loopback
SS 13 rw Speed Selection
0B10M, 10 Mbit/s
1B100M, 100 Mbit/s
ANE 12 rw Autonegotiation Enable
0BDAN, Disable auto-neg
1BEAN, Enable auto-neg
PD 11 rw Power Down
0BNO, Normal operation
1BPD, Power Down
ISO 10 rw Isolate
0BNO, normal operation
1BIPHY, isolate PHY from MII
RA 9rwsc Restart Autonegotiation
1BRAN, Restart Auto-neg
DM 8rw Duplex Mode
0BHA, Half
1BFU, Full
CT 7ro Collision Test
Not implemented
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ADM8513
Data Sheet
Registers Description
Data Sheet 68 Rev. 1.21, 2005-09-13
2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These
registers are not reset by this bit to allow test configurations to be written and then not affected by resetting the
port.
Note: No reset is performed to analogue sections of the port. There is also no physical reset to any internal
clock synthesisers or the local clock recovery oscillator which will continue to run throughout the reset period.
However since the port is restarted and autoneg re-run the process of locking the frequency of the local
oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization
process.
LoopbackLoop back of transmit data to receive via a path as closed to the wire as possible. When set inhibits
actual transmission on the wire.
Speed SelectionForces speed of Phy only when auto-negotiation is disabled. The default state of this bit will be
determined by a power-up configuration pin in this case. Otherwise it defaults to 1.
Auto-neg EnableDefaults to pin programmed value. When cleared allows forcing of speed and duplex settings.
When set (after being cleared) causes re-start of auto-neg process. Pin programming at power-up allows it to
come up disabled and for software to write the desired capability before allowing the first negotiation to commence.
Restart NegotiationOnly has effect when auto-negotiating. Restarts state machine.
Power DownHas no effect in this device. Test mode power down modes may be implemented in other specific
modules.
IsolatePuts RMII receive signals into high impedance state and ignores transmit signals.
Duplex ModeWhen bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex (bit =
0).
Collision TestAlways 0 because collision signal is not implemented.
Status
STA Offset Reset Value
Status 1H7849H
Field Bits Type Description
100T4 15 ro 100 BASE T4
Not supported
100FD 14 ro 100BASE-X Full Duplex
0B100FDN, PHY is not 100BASE-X full duplex capable
1B100FD, PHY is 100BASE-X full duplex capable
100HD 13 ro 100BASE-X Half Duplex
0B100HDN, PHY is not 100BASE-X half duplex capable
1B100HD, PHY is 100BASE-X half duplex capable
10FD 12 ro 10 Mbit/s Full Duplex
0B10FDN, PHY is not 10 Mbit/s Full duplex capable
1B10FD, PHY is 10 Mbit/s Full duplex capable
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Data Sheet 69 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Note: Jabber Detect Only used in 10Base-T mode. Read as 0 in 100Base-TX mode.
PHY Identifier 2 and 3
Each PHY has an identifier, which is assigned to the device.
The identifier contains a total of 32 bits, which consists of the following: 22 bits of a 24 bit organizationally unique
identifier (OUI) for the manufacturer; a 6-bit manufacturer’s model number; a 4-bit manufacturer’s revision number.
For an explanation of how the OUI maps to the register, please refer to IEEE 802-1990 clause 5.1
10HD 11 ro 10 Mbit/s Half Duplex
0B10HDN, PHY is not 10 Mbit/s Half duplex capable
1B10HD, PHY is 10 Mbit/s Half duplex capable
100TFD 10 ro 100BASE-T2 Full Duplex
Not Supported
100THD 9ro 100BASE-T2 Half Duplex
Not Supported
MFPS 6ro MF Preamble Suppression
0BMFPSN, PHY cannot accept management frames with preamble
suppression
1BMFPS, PHY can accept management frames with preamble
suppression
ANC 5ro Auto-neg Complete
0BANI, Auto-neg incomplete
1BANC, Auto-neg completed
RF 4ro, lh Remote Fault
0BRFN, No remote fault detected
1BRF, Remote fault detected
ANA 3ro Auto-neg Ability
0BANN, PHY cannot auto-negotiate
1BAN, PHY can auto-negotiate
LS 2ro, ll Link Status
0BLD, Link is down
1BLU, Link is up
JD 1 ro, lh Jabber Detect
1BJCD, Jabber condition detected
EC 0ro Extended Capability
0BBSC, Basic register set capabilities only
1BEC, Extended register capabilities
Field Bits Type Description
ADM8513
Data Sheet
Registers Description
Data Sheet 70 Rev. 1.21, 2005-09-13
PHY Identifier 1
PHY Identifier 2
Note: This uses the OUI of Infineon-ADMtek, device type of 1 and rev 0.
PHYI1 Offset Reset Value
PHY Identifier 1 2H001DH
Field Bits Type Description
PHYI 15:0 ro PHY Identifier[31-16]
OUI (bits 3-18)
PHYI2 Offset Reset Value
PHY Identifier 2 3H2411H
Field Bits Type Description
PHYI1 15:10 ro PHY Identifier[15-10]
OUI (bits 19-24)
PHYI2 9:4 ro PHY Identifier[9-4]
Manufacturer’s Model Number (bits 5-0)
PHYI3 3:0 ro PHY Identifier[3-0]
Revision Number (bits 3-0);Register 3, bit 0 is LS bit of PHY Identifier
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Data Sheet 71 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
Auto-Negotiation Advertisement
ANA Offset Reset Value
Auto-Negotiation Advertisement 4H0001H
Field Bits Type Description
NP 15 rw Next Page
0BNNP, Device not set to use Next Page
1BNP, Device set to use Next Page
RF 13 rw Remote Fault
0BNFD, No fault detected
1BRF, Local remote fault sent to link partner
NI 12:11 ro Not Implemented
Technology ability bits A7-A6
PAU 10 rw Pause
Technology ability bit A5
NI 9ro Not Implemented
Technology ability bit A4
100FD 8rw 100BASE-TX Full Duplex
Technology ability bit A3
0B100NFD, Unit is not capable of Full Duplex
1B100FD, Unit is capable of Full Duplex
100HD 7rw 100BASE-TX Half Duplex
Technology ability bit A2
0B100NHD, Unit is not capable of Half Duplex 100BASE-TX
1B100HD, Unit is capable of Half Duplex
10FD 6rw 10BASE-T Full Duplex
Technology ability bit A1
0B10NFD, Unit is not capable of Full Duplex 10BASE-T
1B10FD, Unit is capable of Full Duplex 10BASE-T
10HD 5rw 10BASE-T Half Duplex
Technology ability bit A0
0B10NHD, Unit is not capable of Half Duplex 10BASE-T
1B10HD, Unit is capable of Half Duplex 10BASE-T
SF 4:0 ro Selector Field
Identifies type of message being sent. Currently only one value is
defined.
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ADM8513
Data Sheet
Registers Description
Data Sheet 72 Rev. 1.21, 2005-09-13
Auto-Negotiation Link Partner Ability
The register is used to view the advertised capabilities of the link partner once auto negotiation is complete. The
contents of this register should not be relied upon unless register 1 bit 5 is set (auto negotiation complete). After
negotiation this register should contain a copy of the link partner's register 4. All bits are therefore defined in the
same way as for register 4.All bits are readable only.This register is used for Base Page code word only.Base
Page Register Format
Auto-Negotiation Expansion
ANLPA Offset Reset Value
Auto-Negotiation Link Partner Ability 5H0000H
Field Bits Type Description
NP 15 ro Next Page
0B, Base Page is requested
1B, Link Partner is requesting Next Page function
ACK 14 ro Acknowledge
Link Partner acknowledgement bit
RF 13 ro Remote Fault
Link Partner is indicating a fault
TA 12:5 ro Technology Ability
Link Partner technology ability field.
SF 4:0 ro Selector Field
Link Partner selector field
ANE Offset Reset Value
Auto-Negotiation Expansion 6H0004H
Field Bits Type Description
PDF 4ro, lh Parallel Detection Fault
0BNFD, No fault detected
1BFD, Local Device Parallel Detection Fault
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Data Sheet 73 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Registers Description
LPNP 3ro Link Partner Next Page Able
0BNNP, Link Partner is not Next Page Able
1BNP, Link Partner is Next Page Able
NPA 2ro Next Page Able
0B, Local device is not Next Page Able
1B, Local device is Next Page Able
PR 1ro, lh Page Received
0BNPR, A New Page has not been received
1BPR, A New Page has been received
LPAN 0ro Link Partner Auto Negotiation Able
0BNAN, Link Partner is not Auto negotiation able
1BAN, Link Partner is Auto negotiation able
Field Bits Type Description
ADM8513
Data Sheet
Electrical Characteristics
Data Sheet 74 Rev. 1.21, 2005-09-13
7Electrical Characteristics
7.1 Absolute Maximum Ratings
7.2 Operating Condition
7.3 DC Specifications
7.3.1 USB Interface DC Specification
Table 75 Absolute Maximum Rating
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply Voltage VDD ––4.6 V –
DC Input Voltage VIN – – 6 V –
DC Output Voltage VOUT ––4.6 V –
Power Consumption PC––126 mA @ Idle State
––7 mA @ Suspend Mode
––142 mA @ 10M Full Duplex
Mode
––152 mA @ 100M Full Duplex
Mode
Storage Temperature TSTG -65 –150 °C –
Operation Temperature TAMB -40 –125 W –
ESD Rating VESD ––2000 V –
Table 76 Operating Condition
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Supply Voltage VDD 3.0 –3.6 V –
Supply Current IDD ––150 mA –
Table 77 USB Interface DC Specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input High Voltage VIH 2.0 – – V –
Input Low Voltage VIL – – 0.8 V –
Differential Input Sensitivity VDI 0.2 – – V –
Data Sheet 75 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
EEPROM Interface DC Specification
8 EEPROM Interface DC Specification
8.1 Recommended Operating Conditions
8.2 GPIO Interface DC Specification
9Timing
Differential Common Mode
Range
VCM 0.8 –2.5 V –
Output High Voltage VCH 2.8 –3.6 V –
Output Low Voltage VOL 0.0 –0.3 V –
Output Signal Crossover
Voltage
VCRS 1.3 –2.0 V –
Table 78 EEPROM Interface DC Specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input High Voltage VIH 1.8 –5.5 V –
Input Low Voltage VIL -0.5 –1.0 V –
Input Leakage Current II± 1 –± 1000 nA VIN 3.3V or 0 V
Output High Voltage VOH 2.4 – – V –
Output Low Voltage VOL – – 0.4 V –
Input Pin Capacitance CIN – – 5.66 pF –
Table 79 GPIO Interface DC Specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Input High Voltage VIH 1.8 –5.5 V –
Input Low Voltage VIL -0.5 –1.0 V –
Input Leakage Current II± 1 –± 1000 nA VIN 3.3 V or 0 V
Output High Voltage VOH 2.4 – – V –
Output Low Voltage VOL – – 0.4 V –
Input Pin Capacitance CIN – – 5.64 pF –
Table 77 USB Interface DC Specification (cont’d)
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
ADM8513
Data Sheet
Timing
Data Sheet 76 Rev. 1.21, 2005-09-13
9.1 Reset Timing
ADM8513 can be reset either by hardware, software or USB reset.
• A hardware reset is accomplished by asserting the RST# pin after powering up the device. It should have a
duration of at least 100 ms to ensure the external 12 MHz and crystal is in stable and correct frequency. All
registers will be reset to default values.
• A software reset is accomplished by setting the reset bit (bit 4) of the Ethernet Control Register (address 01H).
This software reset will reset all registers to default values.
• When ADM8513 sees an SE0 on USB bus for more than 2.5 s. This USB reset will reset all registers to default
values
9.2 USB Interface Timing
9.3 EEPROM Interface Timing
Table 80 GPIO Interface DC Specification
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
Rise Time TFR 4 – 20 ns CL=50 pF
Fall Time TFF 4 – 20 ns CL=50 pF
Rise and fall time matching TFRFF 90 –111.11 %TFRFF =TFR /TFF
Table 81 EEPROM Interface Timing
Parameter Symbol Values Unit Note / Test Condition
Min. Typ. Max.
EESK Clock Frequency tEESK 0–1MHz –
EECS Setup Time to EESK tEECSS 0.2 – – µs –
EECS Hold Time from EESK tEECSH 0––ns –
EEDO Hold Time from EESK tEEDOH 70 – – ns –
EEDO Output Delay to “1” or “0” tEEDOP ––2µs –
EEDI Setup Time to EESK tEEDIS 0.4 – – µs –
EEDI Hold Time from EESK tEEDIH 0.4 – – µs –
Data Sheet 77 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
EEPROM Interface & Example
Figure 5 EEPROM Interface Timing
10 EEPROM Interface & Example
If the EEPROM contents from offset 0 to offset 5 is “FF_FF_FF_FF_FF_FF”, the EEPROM isn't programmed
correctly. The default values for every field are used instead of loading from EEPROM.
Table 82 EEPROM Interface
Offset(Byte) Field Description
00 node_id0 The 1st byte of Ethernet node ID.
01 node_id1 The 2st byte of Ethernet node ID.
02 node_id2 The 3st byte of Ethernet node ID.
03 node_id3 The 4st byte of Ethernet node ID.
04 node_id4 The 5st byte of Ethernet node ID.
05 node_id5 The 6st byte of Ethernet node ID.
06-07 Reserved
08 Max_Pwr The maximum USB power consumption.
09 Ep3_Interval The polling interval for endpoint 3. If this value is 0, EP3 is disabled.
0A[0] Reserved
0A[1] USB_Sel 0A[1] = 1: select internal USB transceiver.
0A[4:2] PHY Mode 0A[4:2]= 000
0B[0] Reserved
0B[5:1] Reserved
0B[7:6] LED Mode Refer to Pin assignment
0C Languageid_lo The low byte of language ID.
0D Languageid_hi The high byte of language ID.
0E-0F Reserved
10 Manuid_lo The low byte of manufacture ID.
11 Manuid_hi The high byte of manufacture ID.
EECS
t
EECSS t
EECSH
t
EESKS
EESK
t
EEDIS t
EEDIH
EEDI
t
EEDOH t
EEDOP
EEDO
t
EEDOP t
EEDOH
ADM8513
Data Sheet
EEPROM Interface & Example
Data Sheet 78 Rev. 1.21, 2005-09-13
10.1 Example
offset(byte) Value
0000H: 00, 00 E8 00 02 2C 00 00,
0008H: 50 01 02 00 09 04 00 00
0010H: A6 07 13 85 0E 10 2A 20
0018H: 0A 38 00 00 00 00 00 00
0020H: 0E 03 41 00 44 00 4D 00
0028H: 74 00 65 00 6B 00 00 00
0030H: 1E 00 55 00 53 00 42 00
0038H: 20 00 31 00 30 00 2F 00
0040H: 2A 03 55 00 53 00 42 00
0048H: -20 00 54 00 6F 00 20 00
0050H: 4C 00 41 00 4E 00 20 00
0058H: 43 00 6F 00 6E 00 76 00
0060H: 65 00 72 00 74 00 65 00
0068H: 72 00 00 00 00 00 00 00
0070H: 0A 03 30 00 30 00 30 00
0078H: 31 00 00 00 00 00 00 00
12 ProID_lo The low byte of product ID.
13 ProID_hi The high byte of product ID.
14 Manu_str_len The length for manufacture string.
15 Manu_str_offset The word offset address of manufacture string.
16 Pro_str_len The length for product string.
17 Pro_str_offset The word offset address of product string.
18 Seri_str_len The length for serial number string.
19 Seri_str_offset The word offset address of serial number string.
Table 83 EEPROM Example
Offset(Byte) Value Description
00-05 00_00_E8_10
_46_02
NIC node ID
08 50 maximum power 160mA
09 01 interrupt endpoint 3 polling interval 1ms
0A 02 isochronous endpoint disables, selects internal USB transceiver
Uses internal Ethernet PHY, Wakes on Lan en
0C-0D 0904 Language ID 0409
10-11 A607 manufacture ID 07A6
12-13 8513 product ID 8513
14 0E manufacture string length 0E bytes
15 10 manufacture string starts from word offset 10h, thus byte offset 20H.
Table 82 EEPROM Interface (cont’d)
Offset(Byte) Field Description
Data Sheet 79 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
EEPROM Interface & Example
16 1E product string length 1E bytes
17 18 product string starts from word offset 18h, thus byte offset 30H.
18 0A serial number string length 0A bytes
19 38 serial number string starts from word offset 38h, thus byte offset 70H.
20-2E 0E 03 41 00 44
00 4D 00 74 00
65 00 6B 00
0E:descriptor size 14 bytes
03: string descriptor
41........: UNICODE encoded string
30-4E 1E 03 55 00 53
00 42 00
20
00................
1E:descriptor size 30 bytes
03: string descriptor
55........: UNICODE encoded string
50-5A 0A 03 30 00 30
00 30 00
31 00
0A: descriptor size 10 bytes
03: string descriptor
30........: UNICODE encoded string
Table 83 EEPROM Example (cont’d)
Offset(Byte) Value Description
ADM8513
Data Sheet
Package
Data Sheet 80 Rev. 1.21, 2005-09-13
11 Package
Figure 6 Package
Data Sheet 81 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Package
Note: This diagram has a 32pin. But, the relative parameters presents 48pin package data. So, please ignore the
pin number and regard the diagram as 48pin. Make an example: Parameter “E” (9mm) means the distance
between the two opposite sides. Parameter "e" (0.8mm) means the distance between two adjacent pins.
D&E1 means body size.
ADM8513
Data Sheet
Package
Data Sheet 82 Rev. 1.21, 2005-09-13
Table 84 Dimensions for 48 Pin LQFP Package
Symbol Millimeter (mm) Inch
Min.Typ. Max. Min. Typ. Max.
A – – 1.60 – – 0.063
A10.05 –0.15 0.002 –0.006
A21.35 1.40 1.45 0.053 0.005 0.057
D9.00 BSC. 0.354 BSC.
D17.00 BSC 0.276 BSC.
E9.00 BSC 0.354 BSC.
E17.00 BSC 0.276 BSC.
R20.08 –0.20 0.003 –0.008
R10.08 – – 0.003 – –
Θ0° 3.5° 7° 0° 3.5° 7°
Θ10° – – 0° – –
Θ211° 12° 13° 11° 12° 13°
Θ311° 12° 13° 11° 12° 13°
c0.09 –0.20 0.004 –0.008
L0.45 0.60 0.75 0.018 0.024 0.030
L11.00 Ref. 0.039 Ref.
S0.20 – – 0.008 – –
32L
b0.30 0.35 0.45 0.0012 0.0014 0.018
e0.80 BSC. 0.031 BSC.
D25.60 0.220
E25.60 0.220
Tolerance of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.10 0.003
ddd 0.20 0.008
34L
b0.17 0.20 0.27 0.007 0.008 0.011
e0.50 BSC. 0.020 BSC.
D25.00 0.197
E25.00 0.197
Tolerance of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
48L
b0.17 0.20 0.27 0.007 0.008 0.011
Data Sheet 83 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Package
e0.50 BSC. 0.020 BSC.
D25.50 0.217
E25.50 0.217
Tolerance of Form and Position
aaa 0.20 0.008
bbb 0.20 0.008
ccc 0.08 0.003
ddd 0.08 0.003
Table 84 Dimensions for 48 Pin LQFP Package (cont’d)
Symbol Millimeter (mm) Inch
ADM8513
Data Sheet
Appendix Layout Guide
Data Sheet 84 Rev. 1.21, 2005-09-13
12 Appendix Layout Guide
Placement:
• At USB side, place ADM8513 and USB connector as close as possible.
• At Ethernet side, place ADM8513, transformer and RJ45 as close as possible.
• The crystal or OSC device should be closed to ADM8513 and away from the following items
– Any analog signal
– PCB edge
– Any other high frequency components and their associated traces.
If you can't avoid those designs, please add a Resistor between Crystal (or OSC) and ADM8513 chip clk48_I
pin as figure show:
Figure 7 Placement 1
• Place the filtering capacitor as closed as possible at the Vcc pin of ADM8513 and its trace must be short and
wide.
Figure 8 Placement 2
To pin 29 : clk48_I To pin 28 : clk48_O
CLKOUTCLKIN
C3
20PF
L1
2.2UH
R1 22.1K
C5
10PF
C2
0.01UF
X1
48M
R2 33
Data Sheet 85 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Appendix Layout Guide
Trace routing
• Keep USB differential pair data signal D+ and D-:
– Trace width should be as wide as possible.
– Make D+ and D- traces route at the same signal plane and not pass through the other plane.
– Inhibit crossover on D+ and D-
– The termination resistance (R2,R3) and decoupling capacitors (C1,C2) should be closed to ADM8513.
– D+ and D- Signal trace length should be equal and as short as possible.
• Arrangement Tx and Rx trace
– Tx+/- and Rx+/- trace avoid right angle and round angle >90 degree, suggested.
– Trace width must be wide and should be wider than 8 mils.
– Signal trace length between Tx+/- differential pairs should be crossed and have equal length.The total length
should be no longer than 2 cm. The same requirement applies to Rx+/- also.
– Make Tx and Rx trace route at the same signal plane and not pass through the other plane.
– Every differential pairs as cross as possible, but no less than 8 mils and space should be almost equal.
– Keep space large between Tx and Rx differential pairs, even separated ground planes underneath Tx and
Rx signal pairs.
– Away from clock and power traces.
– If Tx routed trace must cross, the trace can be swapped between chip and transformer, and transformer to
RJ45,too.
Figure 9 Trace Routing 1
Figure 10 Trace Routing 2
• Digital signal should be away from analog signal and Vcc traces. If you can't avoid this situation, analog signal
or Vcc trace should cross over 90 degree at other plane.
Bad Good
ADM8513
Data Sheet
Appendix Layout Guide
Data Sheet 86 Rev. 1.21, 2005-09-13
Figure 11 Trace Routing 3
• Vcc trace should be short and prefer route in the format of the plane a special for GND.
Power and Ground
• All of the Vcc pin should have a 0.1uF SMD capacitors which placed with it. To be effective, the capacitors
should be placed as close as possible at the pin.
• The chassis ground plane connected to the USB B type and network connector chassis should be isolated from
the signal plane with 0.1uF capacitors or bead to prevent any radiation from leaking and resulting in EMI failure.
• Right angle is recommend when partition Vcc as well as GND planes.
• Avoid Vcc and ground planes placing directly under the transformer.See the Figure as below.
Figure 12 Power and Ground 1
• If you use a captive cable (plus the shield wire) it may require additional filtering for EMI test pass and the length
of unshielded cable should be limited to 3cm or less.
Figure 13 Power and Ground 2
Data Sheet 87 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Appendix Layout Guide
• Please connect 10K Ohm Ribb resistance gnd, pin40(GndRef) and pin37(GndR) first then use signal via to
Gnd (Specially for 2 layers board design).
Figure 14 Power and Ground 3
Bad Good
ADM8513
Data Sheet
References
Data Sheet 88 Rev. 1.21, 2005-09-13
References
[1]
[2]
[3]
[4]
[5]
[6]
Data Sheet 89 Rev. 1.21, 2005-09-13
ADM8513
Data Sheet
Terminology
Terminology
A
B
