DATA SHEET MOS INTEGRATED CIRCUIT PD3778 10600 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR The PD3778 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to electrical signal and has the function of color separation. The PD3778 has 3 rows of 10600 pixels, and each row has a double-sided readout type of charge transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color image scanners and so on. FEATURES * Valid photocell : 10600 pixels x 3 * Photocell's pitch : 4 m * Photocell size : 4 x 4 m 2 * Line spacing : 48 m (12 lines) Red line-Green line, Green line-Blue line * Color filter : Primary colors (red, green and blue), pigment filter (with light resistance 107 lx*hour) * Resolution : 48 dot/mm A4 (210 x 297 mm) size (shorter side) 1200 dpi US letter (8.5" x 11") size (shorter side) * Drive clock level : CMOS output under 5 V operation * Data rate : 5 MHz MAX. * Power supply : +12 V * On-chip circuits : Reset feed-through level clamp circuits Voltage amplifiers ORDERING INFORMATION Part Number PD3778CY Package CCD linear image sensor 32-pin plastic DIP (400 mil) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14374EJ1V0DSJ1 (1st edition) Date published October 2000 N CP(K) Printed in Japan (c) 1999 2 BLOCK DIAGRAM VOD GND GND 2 1 29 1 16 22 19 CCD analog shift register 18 TG1 (Blue) 17 TG2 (Green) 15 TG3 (Red) D67 D66 D65 S10600 Photocell (Blue) S10599 S2 ........ S1 30 D64 VOUT1 (Blue) D14 Transfer gate Transfer gate CCD analog shift register D67 D66 D65 S10600 Photocell (Green) S10599 S2 ........ S1 31 D64 VOUT2 (Green) D14 Transfer gate Transfer gate CCD analog shift register CCD analog shift register D67 D66 D65 S10600 Photocell (Red) S10599 ........ S2 32 S1 VOUT3 (Red) D64 Transfer gate D14 Data Sheet S14374EJ1V0DS00 CCD analog shift register Transfer gate CCD analog shift register 2 14 11 CLB RB 2 1 PD3778 3 PD3778 PIN CONFIGURATION (Top View) CCD linear image sensor 32-pin plastic DIP (400 mil) * PD3778CY 32 VOUT3 Output signal 3 (Red) Reset gate clock RB 2 31 VOUT2 Output signal 2 (Green) Reset feed-through level clamp clock CLB 3 30 VOUT1 Output signal 1 (Blue) No connection NC 4 29 VOD Output drain voltage No connection NC 5 28 NC No connection Internal connection IC 6 27 IC Internal connection Internal connection IC 7 26 IC Internal connection No connection NC 8 25 NC No connection No connection NC 9 24 NC No connection No connection NC 10 23 NC No connection Shift register clock 1 1 11 22 2 Shift register clock 2 Internal connection IC 12 21 IC Internal connection Internal connection IC 13 20 IC Internal connection Shift register clock 2 2 14 19 1 Shift register clock 1 Transfer gate clock 3 (for Red) TG3 15 18 TG1 Transfer gate clock 1 (for Blue) Ground GND 16 17 TG2 Transfer gate clock 2 (for Green) Blue 10600 Green 10600 Red 10600 1 1 1 GND 1 Ground Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. Data Sheet S14374EJ1V0DS00 3 PD3778 PHOTOCELL STRUCTURE DIAGRAM PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing) 4 m 4 m 2 m 2 m 12 lines (48 m) 4 m Green photocell array Channel stopper 12 lines (48 m) 4 m Aluminum shield 4 Blue photocell array Data Sheet S14374EJ1V0DS00 Red photocell array PD3778 ABSOLUTE MAXIMUM RATINGS (TA = +25 C) Parameter Symbol Ratings Unit Output drain voltage VOD -0.3 to +15 V Shift register clock voltage V 1 , V 2 -0.3 to +8 V Reset gate clock voltage VRB -0.3 to +8 V Reset feed-through level clamp clock voltage VCLB -0.3 to +8 V Transfer gate clock voltage VTG1 to VTG3 -0.3 to +8 V Operating ambient temperature TA -25 to +60 C Storage temperature Tstg -40 to +70 C Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. RECOMMENDED OPERATING CONDITIONS (TA = +25 C) Parameter Symbol MIN. TYP. MAX. Unit Output drain voltage VOD 11.4 12.0 12.6 V Shift register clock high level V1H, V2H 4.5 5.0 5.5 V Shift register clock low level V1L, V2L -0.3 0 +0.5 V Reset gate clock high level VRBH 4.5 5.0 5.5 V Reset gate clock low level VRBL -0.3 0 +0.5 V Reset feed-through level clamp clock high level VCLBH 4.5 5.0 5.5 V Reset feed-through level clamp clock low level VCLBL -0.3 0 +0.5 V Transfer gate clock high level VTG1H to VTG3H 4.5 V1HNote V1HNote V Transfer gate clock low level VTG1L to VTG3L -0.3 0 +0.5 V Data rate fRB - 1.0 5.0 MHz Note When Transfer gate clock high level (VTG1H to VTG3H) is higher than Shift register clock high level (V1H), Image lag can increase. Data Sheet S14374EJ1V0DS00 5 PD3778 ELECTRICAL CHARACTERISTICS TA = +25 C, VOD = 12 V, data rate (fRB) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 Vp-p, light source: 3200 K halogen lamp +C-500S (infrared cut filter, t = 1mm) + HA-50 (heat absorbing filter, t = 3 mm) Parameter Symbol Saturation voltage Test Conditions Vsat Saturation exposure Unit 2.0 2.5 - V 0.694 lx*s Green SEG 0.757 lx*s Blue SEB 1.250 lx*s VOUT = 1.0 V Average dark signal ADS Dark signal non-uniformity DSNU Power consumption Output impedance 6 20 % Light shielding 0.2 4.0 mV Light shielding 1.5 4.0 mV PW 400 600 mW ZO 0.5 1 k Red RR 2.52 3.60 4.68 V/lx*s Green RG 2.31 3.30 4.29 V/lx*s Blue RB 1.40 2.00 2.60 V/lx*s 2.0 10.0 % 6.0 7.0 V Image lag IL Note1 Output fall delay time MAX. SER PRNU Offset level TYP. Red Photo response non-uniformity Response MIN. VOUT = 1.0 V VOS Note2 Total transfer efficiency 4.0 td VOUT = 1.0 V TTE VOUT = 1.0 V, 50 ns 92 98 % 0 1.0 data rate = 5 MHz Register imbalance Response peak RI Random noise (CDS) 4.0 630 nm Green 540 nm Blue 460 nm Note1 DR1 Vsat /DSNU 1666 times DR2 Vsat / CDS 2500 times RFTN Light shielding -1000 -300 +500 mV CDS Light shielding - 1.0 - mV Notes 1. Refer to TIMING CHART 2. 2. When each fall time of 1 and 2 (t2, t1) is the TYP. value (refer to TIMING CHART 2). 6 % Red Dynamic range Reset feed-through noise VOUT = 1.0 V Data Sheet S14374EJ1V0DS00 PD3778 INPUT PIN CAPACITANCE (TA = +25 C, VOD = 12 V) Parameter Shift register clock pin capacitance 1 Symbol 1 Pin No. MIN. TYP. MAX. Unit 11 400 pF 19 400 pF 14 400 pF 22 400 pF RB 2 15 pF Reset feed-through level clamp clock pin capacitance CCLB CLB 3 15 pF Transfer gate clock pin capacitance TG1 18 120 pF TG2 17 120 pF TG3 15 120 pF Shift register clock pin capacitance 2 Reset gate clock pin capacitance C 1 Pin name C 2 CRB CTG 2 Remark Pins 11 and 19 (1), 14 and 22 (2) are each connected inside of the device. Data Sheet S14374EJ1V0DS00 7 8 TIMING CHART 1 (for each color) 8 7 6 5 4 3 2 1 1 TG1 to TG3 2 RB 61 62 63 64 65 66 Note 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sheet S14374EJ1V0DS00 10663 10664 10665 10666 10667 10668 10669 CLB Note VOUT1 to VOUT3 Optical black (49 pixels) Valid photocell (10600 pixels) Invalid photocell (2 pixels) Invalid photocell (3 pixels) Note Input the RB and CLB pulses continuously during this period, too. PD3778 TIMING CHART 2 (for each color) t1 90 % 1 10 % 90 % 2 10 % t5 Data Sheet S14374EJ1V0DS00 RB t3 t6 t4 90 % 10 % t10 CLB t2 t8 t7 t9 t11 90 % 10 % + td td RFTN VOUT _ VOS 10 % RFTN 10 % PD3778 9 PD3778 TG1 to TG3, 1, 2 TIMING CHART t13 t14 t12 90 % TG1 to TG3 10 % t16 t15 90 % 1 2 Symbol MIN. TYP. MAX. Unit t1, t2 0 25 - ns t3 20 50 - ns t4 70 250 - ns t5, t6 0 25 - ns t7 30 50 - ns t8, t9 0 25 - ns t10 30 50 - ns t11 5 15 - ns t12 5000 10000 - ns t13, t14 0 50 - ns t15, t16 900 1000 - ns 1, 2 cross points 1 2.0 V or more 2.0 V or more 2 Remark Adjust cross points of 1 and 2 with input resistance of each pin. 10 Data Sheet S14374EJ1V0DS00 PD3778 DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: Vsat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (IX) and storage time (s) when saturation of output voltage occurs. 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of uniform illumination. This is calculated by the following formula. PRNU (%) = x x 100 x x : maximum of xj - x 10600 x j x= j=1 10600 xj : Output voltage of valid pixel number j VOUT Register Dark DC level 4. x x Average dark signal: ADS Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula. 10600 d ADS (mV) = j j=1 10600 dj : Dark signal of valid pixel number j 5. Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum of dj - ADS j = 1 to 10600 dj : Dark signal of valid pixel number j VOUT ADS Register Dark DC level DSNU Data Sheet S14374EJ1V0DS00 11 PD3778 6. Output impedance: ZO Impedance of the output pins viewed from outside. 7. Response: R Output voltage divided by exposure (Ix*s). Note that the response varies with a light source (spectral characteristic). 8. Image Lag: IL The rate between the last output voltage and the next one after read out the data of a line. TG ON Light OFF VOUT V1 VOUT V1 IL (%) = 9. VOUT x100 Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels. n 2 2 n (V2j - 1 - V2j) j= 1 RI (%) = n 1 n Vj x 100 j= 1 n : Number of valid pixels Vj : Output voltage of each pixel 12 Data Sheet S14374EJ1V0DS00 PD3778 10. Random noise (CDS): CDS Random noise (CDS) CDS is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data sampling at dark (light shielding). This is measured by the following procedure. 1. One valid photocell in one reading is fixed as measurement point. 2. The output level is measured during the Reset feed-through period which is averaged over 100 ns to get "VDi". 3. The output level is measured during the Video output time averaged over 100 ns to get "VOi". 4. The correlated double sampling output is defined by "VCDSi = VDi - VOi". 5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines). 6. Calculate the standard deviation CDS using the following formula. 100 CDS (mV) = (VCDS - V) i 2 , V= i=1 100 1 100 VCDS i 100 i=1 Reset feed-through VOUT Video output Data Sheet S14374EJ1V0DS00 13 PD3778 STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC 8 STORAGE TIME OUTPUT VOLTAGE CHARACTERISTIC (TA = +25 C) 2 1 Relative Output Voltage Relative Output Voltage 4 2 1 0.5 0.2 0.25 0.1 0 10 20 30 40 0.1 50 Operating Ambient Temperature TA(C) 1 5 10 Storage Time (ms) TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (TA = +25 C) 100 R B G Response Ratio (%) 80 60 40 G 20 B 0 400 500 600 Wavelength (nm) 14 Data Sheet S14374EJ1V0DS00 700 800 PD3778 APPLICATION CIRCUIT EXAMPLE PD3778 1 47 RB 47 CLB 2 3 32 GND VOUT3 RB VOUT2 CLB VOUT1 B3 31 B2 +12 V 30 4 B1 10 29 NC VOD + 5 28 NC +5 V NC 6 0.1 F 27 IC IC IC IC NC NC 7 47 F/25 V +5 V 26 + 8 25 + 10 F/16 V 0.1 F 9 24 NC NC 10 4.7 1 11 NC NC 1 2 IC IC IC IC 2 1 12 4.7 4.7 TG 14 15 22 10 F/16 V 4.7 21 13 2 0.1 F 23 20 TG3 TG1 GND TG2 16 19 4.7 18 4.7 17 4.7 Caution Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected. Remark The inverters shown in the above application circuit example are the 74HC04 or 74AC04. Data Sheet S14374EJ1V0DS00 15 PD3778 B1 to B3 EQUIVALENT CIRCUIT 12 V + 100 CCD VOUT 47 F/25 V 100 2SC945 2 k 16 Data Sheet S14374EJ1V0DS00 PD3778 PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (400 mil) (Unit : mm) 1st valid pixel 6.150.3 1 12.60.5 1 9.250.3 17 9.050.3 32 16 4.10.5 54.80.5 55.20.5 10.16 (1.80) 2.580.3 (5.42) 1.020.15 2 2.54 3 0.250.05 0~1 0 4.210.5 0.460.06 4.550.5 38.1 Name Plastic cap Dimensions 52.2x6.4x0.7 1 The 1st valid pixel Refractive index 4 1.5 The center of the pin1 2 The surface of the chip 3 The bottom of the package The top of the cap The surface of the chip 4 Thickness of plastic cap over CCD chip 32C-1CCD-PKG3 Data Sheet S14374EJ1V0DS00 17 PD3778 RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "Semiconductor Device Mounting Technology Manual"(C10535E). Type of Through-hole Device PD3778CY : CCD linear image sensor 32-pin plastic DIP (400 mil) Process Partial heating method Conditions Pin temperature: 300 C or below, Heat time: 3 seconds or less (per pin) Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap. The optical characteristics could be degraded by such contact. 18 Data Sheet S14374EJ1V0DS00 PD3778 NOTES ON CLEANING THE PLASTIC CAP 1 CLEANING THE PLASTIC CAP Care should be taken when cleaning the surface to prevent scratches. The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below. Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is recommended that a clean surface or cloth be used. 2 RECOMMENDED SOLVENTS The following are the recommended solvents for cleaning the CCD plastic cap. Use of solvents other than these could result in optical or physical degradation in the plastic cap. Please consult your sales office when considering an alternative solvent. Solvents Symbol Ethyl Alcohol EtOH Methyl Alcohol MeOH Isopropyl Alcohol IPA N-methyl Pyrrolidone NMP Data Sheet S14374EJ1V0DS00 19 PD3778 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. 20 Data Sheet S14374EJ1V0DS00 PD3778 [MEMO] Data Sheet S14374EJ1V0DS00 21 PD3778 [MEMO] 22 Data Sheet S14374EJ1V0DS00 PD3778 [MEMO] Data Sheet S14374EJ1V0DS00 23 PD3778 * The information in this document is current as of July, 1999. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. 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